2 * linux/drivers/video/amba-clcd.c
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
11 * ARM PrimeCell PL110 Color LCD Controller
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/list.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/clcd.h>
26 #include <linux/clk.h>
27 #include <linux/hardirq.h>
29 #include <asm/sizes.h>
31 #define to_clcd(info) container_of(info, struct clcd_fb, fb)
33 /* This is limited to 16 characters when displayed by X startup */
34 static const char *clcd_name
= "CLCD FB";
37 * Unfortunately, the enable/disable functions may be called either from
38 * process or IRQ context, and we _need_ to delay. This is _not_ good.
40 static inline void clcdfb_sleep(unsigned int ms
)
49 static inline void clcdfb_set_start(struct clcd_fb
*fb
)
51 unsigned long ustart
= fb
->fb
.fix
.smem_start
;
54 ustart
+= fb
->fb
.var
.yoffset
* fb
->fb
.fix
.line_length
;
55 lstart
= ustart
+ fb
->fb
.var
.yres
* fb
->fb
.fix
.line_length
/ 2;
57 writel(ustart
, fb
->regs
+ CLCD_UBAS
);
58 writel(lstart
, fb
->regs
+ CLCD_LBAS
);
61 static void clcdfb_disable(struct clcd_fb
*fb
)
65 if (fb
->board
->disable
)
66 fb
->board
->disable(fb
);
68 val
= readl(fb
->regs
+ CLCD_CNTL
);
69 if (val
& CNTL_LCDPWR
) {
71 writel(val
, fb
->regs
+ CLCD_CNTL
);
75 if (val
& CNTL_LCDEN
) {
77 writel(val
, fb
->regs
+ CLCD_CNTL
);
81 * Disable CLCD clock source.
86 static void clcdfb_enable(struct clcd_fb
*fb
, u32 cntl
)
89 * Enable the CLCD clock source.
94 * Bring up by first enabling..
97 writel(cntl
, fb
->regs
+ CLCD_CNTL
);
102 * and now apply power.
105 writel(cntl
, fb
->regs
+ CLCD_CNTL
);
108 * finally, enable the interface.
110 if (fb
->board
->enable
)
111 fb
->board
->enable(fb
);
115 clcdfb_set_bitfields(struct clcd_fb
*fb
, struct fb_var_screeninfo
*var
)
119 memset(&var
->transp
, 0, sizeof(var
->transp
));
121 var
->red
.msb_right
= 0;
122 var
->green
.msb_right
= 0;
123 var
->blue
.msb_right
= 0;
125 switch (var
->bits_per_pixel
) {
130 var
->red
.length
= var
->bits_per_pixel
;
132 var
->green
.length
= var
->bits_per_pixel
;
133 var
->green
.offset
= 0;
134 var
->blue
.length
= var
->bits_per_pixel
;
135 var
->blue
.offset
= 0;
139 var
->blue
.length
= 5;
141 * Green length can be 5 or 6 depending whether
142 * we're operating in RGB555 or RGB565 mode.
144 if (var
->green
.length
!= 5 && var
->green
.length
!= 6)
145 var
->green
.length
= 6;
148 if (fb
->panel
->cntl
& CNTL_LCDTFT
) {
150 var
->green
.length
= 8;
151 var
->blue
.length
= 8;
160 * >= 16bpp displays have separate colour component bitfields
161 * encoded in the pixel data. Calculate their position from
162 * the bitfield length defined above.
164 if (ret
== 0 && var
->bits_per_pixel
>= 16) {
165 if (fb
->panel
->cntl
& CNTL_BGR
) {
166 var
->blue
.offset
= 0;
167 var
->green
.offset
= var
->blue
.offset
+ var
->blue
.length
;
168 var
->red
.offset
= var
->green
.offset
+ var
->green
.length
;
171 var
->green
.offset
= var
->red
.offset
+ var
->red
.length
;
172 var
->blue
.offset
= var
->green
.offset
+ var
->green
.length
;
179 static int clcdfb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
181 struct clcd_fb
*fb
= to_clcd(info
);
184 if (fb
->board
->check
)
185 ret
= fb
->board
->check(fb
, var
);
188 var
->xres_virtual
* var
->bits_per_pixel
/ 8 *
189 var
->yres_virtual
> fb
->fb
.fix
.smem_len
)
193 ret
= clcdfb_set_bitfields(fb
, var
);
198 static int clcdfb_set_par(struct fb_info
*info
)
200 struct clcd_fb
*fb
= to_clcd(info
);
201 struct clcd_regs regs
;
203 fb
->fb
.fix
.line_length
= fb
->fb
.var
.xres_virtual
*
204 fb
->fb
.var
.bits_per_pixel
/ 8;
206 if (fb
->fb
.var
.bits_per_pixel
<= 8)
207 fb
->fb
.fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
209 fb
->fb
.fix
.visual
= FB_VISUAL_TRUECOLOR
;
211 fb
->board
->decode(fb
, ®s
);
215 writel(regs
.tim0
, fb
->regs
+ CLCD_TIM0
);
216 writel(regs
.tim1
, fb
->regs
+ CLCD_TIM1
);
217 writel(regs
.tim2
, fb
->regs
+ CLCD_TIM2
);
218 writel(regs
.tim3
, fb
->regs
+ CLCD_TIM3
);
220 clcdfb_set_start(fb
);
222 clk_set_rate(fb
->clk
, (1000000000 / regs
.pixclock
) * 1000);
224 fb
->clcd_cntl
= regs
.cntl
;
226 clcdfb_enable(fb
, regs
.cntl
);
229 printk(KERN_INFO
"CLCD: Registers set to\n"
230 KERN_INFO
" %08x %08x %08x %08x\n"
231 KERN_INFO
" %08x %08x %08x %08x\n",
232 readl(fb
->regs
+ CLCD_TIM0
), readl(fb
->regs
+ CLCD_TIM1
),
233 readl(fb
->regs
+ CLCD_TIM2
), readl(fb
->regs
+ CLCD_TIM3
),
234 readl(fb
->regs
+ CLCD_UBAS
), readl(fb
->regs
+ CLCD_LBAS
),
235 readl(fb
->regs
+ CLCD_IENB
), readl(fb
->regs
+ CLCD_CNTL
));
241 static inline u32
convert_bitfield(int val
, struct fb_bitfield
*bf
)
243 unsigned int mask
= (1 << bf
->length
) - 1;
245 return (val
>> (16 - bf
->length
) & mask
) << bf
->offset
;
249 * Set a single color register. The values supplied have a 16 bit
250 * magnitude. Return != 0 for invalid regno.
253 clcdfb_setcolreg(unsigned int regno
, unsigned int red
, unsigned int green
,
254 unsigned int blue
, unsigned int transp
, struct fb_info
*info
)
256 struct clcd_fb
*fb
= to_clcd(info
);
259 fb
->cmap
[regno
] = convert_bitfield(transp
, &fb
->fb
.var
.transp
) |
260 convert_bitfield(blue
, &fb
->fb
.var
.blue
) |
261 convert_bitfield(green
, &fb
->fb
.var
.green
) |
262 convert_bitfield(red
, &fb
->fb
.var
.red
);
264 if (fb
->fb
.fix
.visual
== FB_VISUAL_PSEUDOCOLOR
&& regno
< 256) {
265 int hw_reg
= CLCD_PALETTE
+ ((regno
* 2) & ~3);
266 u32 val
, mask
, newval
;
268 newval
= (red
>> 11) & 0x001f;
269 newval
|= (green
>> 6) & 0x03e0;
270 newval
|= (blue
>> 1) & 0x7c00;
273 * 3.2.11: if we're configured for big endian
274 * byte order, the palette entries are swapped.
276 if (fb
->clcd_cntl
& CNTL_BEBO
)
286 val
= readl(fb
->regs
+ hw_reg
) & mask
;
287 writel(val
| newval
, fb
->regs
+ hw_reg
);
294 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
295 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
296 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
297 * to e.g. a video mode which doesn't support it. Implements VESA suspend
298 * and powerdown modes on hardware that supports disabling hsync/vsync:
299 * blank_mode == 2: suspend vsync
300 * blank_mode == 3: suspend hsync
301 * blank_mode == 4: powerdown
303 static int clcdfb_blank(int blank_mode
, struct fb_info
*info
)
305 struct clcd_fb
*fb
= to_clcd(info
);
307 if (blank_mode
!= 0) {
310 clcdfb_enable(fb
, fb
->clcd_cntl
);
315 static int clcdfb_mmap(struct fb_info
*info
,
316 struct vm_area_struct
*vma
)
318 struct clcd_fb
*fb
= to_clcd(info
);
319 unsigned long len
, off
= vma
->vm_pgoff
<< PAGE_SHIFT
;
322 len
= info
->fix
.smem_len
;
324 if (off
<= len
&& vma
->vm_end
- vma
->vm_start
<= len
- off
&&
326 ret
= fb
->board
->mmap(fb
, vma
);
331 static struct fb_ops clcdfb_ops
= {
332 .owner
= THIS_MODULE
,
333 .fb_check_var
= clcdfb_check_var
,
334 .fb_set_par
= clcdfb_set_par
,
335 .fb_setcolreg
= clcdfb_setcolreg
,
336 .fb_blank
= clcdfb_blank
,
337 .fb_fillrect
= cfb_fillrect
,
338 .fb_copyarea
= cfb_copyarea
,
339 .fb_imageblit
= cfb_imageblit
,
340 .fb_mmap
= clcdfb_mmap
,
343 static int clcdfb_register(struct clcd_fb
*fb
)
347 fb
->clk
= clk_get(&fb
->dev
->dev
, NULL
);
348 if (IS_ERR(fb
->clk
)) {
349 ret
= PTR_ERR(fb
->clk
);
353 fb
->fb
.fix
.mmio_start
= fb
->dev
->res
.start
;
354 fb
->fb
.fix
.mmio_len
= 4096;
356 fb
->regs
= ioremap(fb
->fb
.fix
.mmio_start
, fb
->fb
.fix
.mmio_len
);
358 printk(KERN_ERR
"CLCD: unable to remap registers\n");
363 fb
->fb
.fbops
= &clcdfb_ops
;
364 fb
->fb
.flags
= FBINFO_FLAG_DEFAULT
;
365 fb
->fb
.pseudo_palette
= fb
->cmap
;
367 strncpy(fb
->fb
.fix
.id
, clcd_name
, sizeof(fb
->fb
.fix
.id
));
368 fb
->fb
.fix
.type
= FB_TYPE_PACKED_PIXELS
;
369 fb
->fb
.fix
.type_aux
= 0;
370 fb
->fb
.fix
.xpanstep
= 0;
371 fb
->fb
.fix
.ypanstep
= 0;
372 fb
->fb
.fix
.ywrapstep
= 0;
373 fb
->fb
.fix
.accel
= FB_ACCEL_NONE
;
375 fb
->fb
.var
.xres
= fb
->panel
->mode
.xres
;
376 fb
->fb
.var
.yres
= fb
->panel
->mode
.yres
;
377 fb
->fb
.var
.xres_virtual
= fb
->panel
->mode
.xres
;
378 fb
->fb
.var
.yres_virtual
= fb
->panel
->mode
.yres
;
379 fb
->fb
.var
.bits_per_pixel
= fb
->panel
->bpp
;
380 fb
->fb
.var
.grayscale
= fb
->panel
->grayscale
;
381 fb
->fb
.var
.pixclock
= fb
->panel
->mode
.pixclock
;
382 fb
->fb
.var
.left_margin
= fb
->panel
->mode
.left_margin
;
383 fb
->fb
.var
.right_margin
= fb
->panel
->mode
.right_margin
;
384 fb
->fb
.var
.upper_margin
= fb
->panel
->mode
.upper_margin
;
385 fb
->fb
.var
.lower_margin
= fb
->panel
->mode
.lower_margin
;
386 fb
->fb
.var
.hsync_len
= fb
->panel
->mode
.hsync_len
;
387 fb
->fb
.var
.vsync_len
= fb
->panel
->mode
.vsync_len
;
388 fb
->fb
.var
.sync
= fb
->panel
->mode
.sync
;
389 fb
->fb
.var
.vmode
= fb
->panel
->mode
.vmode
;
390 fb
->fb
.var
.activate
= FB_ACTIVATE_NOW
;
391 fb
->fb
.var
.nonstd
= 0;
392 fb
->fb
.var
.height
= fb
->panel
->height
;
393 fb
->fb
.var
.width
= fb
->panel
->width
;
394 fb
->fb
.var
.accel_flags
= 0;
396 fb
->fb
.monspecs
.hfmin
= 0;
397 fb
->fb
.monspecs
.hfmax
= 100000;
398 fb
->fb
.monspecs
.vfmin
= 0;
399 fb
->fb
.monspecs
.vfmax
= 400;
400 fb
->fb
.monspecs
.dclkmin
= 1000000;
401 fb
->fb
.monspecs
.dclkmax
= 100000000;
404 * Make sure that the bitfields are set appropriately.
406 clcdfb_set_bitfields(fb
, &fb
->fb
.var
);
409 * Allocate colourmap.
411 fb_alloc_cmap(&fb
->fb
.cmap
, 256, 0);
414 * Ensure interrupts are disabled.
416 writel(0, fb
->regs
+ CLCD_IENB
);
418 fb_set_var(&fb
->fb
, &fb
->fb
.var
);
420 printk(KERN_INFO
"CLCD: %s hardware, %s display\n",
421 fb
->board
->name
, fb
->panel
->mode
.name
);
423 ret
= register_framebuffer(&fb
->fb
);
427 printk(KERN_ERR
"CLCD: cannot register framebuffer (%d)\n", ret
);
436 static int clcdfb_probe(struct amba_device
*dev
, void *id
)
438 struct clcd_board
*board
= dev
->dev
.platform_data
;
445 ret
= amba_request_regions(dev
, NULL
);
447 printk(KERN_ERR
"CLCD: unable to reserve regs region\n");
451 fb
= kzalloc(sizeof(struct clcd_fb
), GFP_KERNEL
);
453 printk(KERN_INFO
"CLCD: could not allocate new clcd_fb struct\n");
461 ret
= fb
->board
->setup(fb
);
465 ret
= clcdfb_register(fb
);
467 amba_set_drvdata(dev
, fb
);
471 fb
->board
->remove(fb
);
475 amba_release_regions(dev
);
480 static int clcdfb_remove(struct amba_device
*dev
)
482 struct clcd_fb
*fb
= amba_get_drvdata(dev
);
484 amba_set_drvdata(dev
, NULL
);
487 unregister_framebuffer(&fb
->fb
);
491 fb
->board
->remove(fb
);
495 amba_release_regions(dev
);
500 static struct amba_id clcdfb_id_table
[] = {
508 static struct amba_driver clcd_driver
= {
510 .name
= "clcd-pl11x",
512 .probe
= clcdfb_probe
,
513 .remove
= clcdfb_remove
,
514 .id_table
= clcdfb_id_table
,
517 static int __init
amba_clcdfb_init(void)
519 if (fb_get_options("ambafb", NULL
))
522 return amba_driver_register(&clcd_driver
);
525 module_init(amba_clcdfb_init
);
527 static void __exit
amba_clcdfb_exit(void)
529 amba_driver_unregister(&clcd_driver
);
532 module_exit(amba_clcdfb_exit
);
534 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
535 MODULE_LICENSE("GPL");
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