4 #ifdef CONFIG_FB_RADEON_DEBUG
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/delay.h>
12 #include <linux/pci.h>
16 #ifdef CONFIG_FB_RADEON_I2C
17 #include <linux/i2c.h>
18 #include <linux/i2c-algo-bit.h>
23 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
27 #include <video/radeon.h>
29 /***************************************************************
30 * Most of the definitions here are adapted right from XFree86 *
31 ***************************************************************/
35 * Chip families. Must fit in the low 16 bits of a long word
42 CHIP_FAMILY_RS100
, /* U1 (IGP320M) or A3 (IGP320)*/
44 CHIP_FAMILY_RS200
, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
48 CHIP_FAMILY_RS300
, /* Radeon 9000 IGP */
53 CHIP_FAMILY_RV380
, /* RV370/RV380/M22/M24 */
54 CHIP_FAMILY_R420
, /* R420/R423/M18 */
60 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
61 ((rinfo)->family == CHIP_FAMILY_RV200) || \
62 ((rinfo)->family == CHIP_FAMILY_RS100) || \
63 ((rinfo)->family == CHIP_FAMILY_RS200) || \
64 ((rinfo)->family == CHIP_FAMILY_RV250) || \
65 ((rinfo)->family == CHIP_FAMILY_RV280) || \
66 ((rinfo)->family == CHIP_FAMILY_RS300))
69 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
70 ((rinfo)->family == CHIP_FAMILY_RV350) || \
71 ((rinfo)->family == CHIP_FAMILY_R350) || \
72 ((rinfo)->family == CHIP_FAMILY_RV380) || \
73 ((rinfo)->family == CHIP_FAMILY_R420) || \
74 ((rinfo)->family == CHIP_FAMILY_RC410) || \
75 ((rinfo)->family == CHIP_FAMILY_RS480))
80 enum radeon_chip_flags
{
81 CHIP_FAMILY_MASK
= 0x0000ffffUL
,
82 CHIP_FLAGS_MASK
= 0xffff0000UL
,
83 CHIP_IS_MOBILITY
= 0x00010000UL
,
84 CHIP_IS_IGP
= 0x00020000UL
,
85 CHIP_HAS_CRTC2
= 0x00040000UL
,
92 CHIP_ERRATA_R300_CG
= 0x00000001,
93 CHIP_ERRATA_PLL_DUMMYREADS
= 0x00000002,
94 CHIP_ERRATA_PLL_DELAY
= 0x00000004,
101 enum radeon_montype
{
106 MT_CTV
, /* composite TV */
107 MT_STV
/* S-Video out */
146 * This structure contains the various registers manipulated by this
147 * driver for setting or restoring a mode. It's mostly copied from
148 * XFree's RADEONSaveRec structure. A few chip settings might still be
149 * tweaked without beeing reflected or saved in these registers though
152 /* Common registers */
154 u32 ovr_wid_left_right
;
155 u32 ovr_wid_top_bottom
;
169 /* Other registers to save for VT switches or driver load/unload */
172 u32 clock_cntl_index
;
176 /* Surface/tiling registers */
177 u32 surf_lower_bound
[8];
178 u32 surf_upper_bound
[8];
185 u32 crtc_h_total_disp
;
186 u32 crtc_h_sync_strt_wid
;
187 u32 crtc_v_total_disp
;
188 u32 crtc_v_sync_strt_wid
;
190 u32 crtc_offset_cntl
;
193 u32 grph_buffer_cntl
;
196 /* CRTC2 registers */
199 u32 disp_output_cntl
;
201 u32 disp2_merge_cntl
;
202 u32 grph2_buffer_cntl
;
203 u32 crtc2_h_total_disp
;
204 u32 crtc2_h_sync_strt_wid
;
205 u32 crtc2_v_total_disp
;
206 u32 crtc2_v_sync_strt_wid
;
208 u32 crtc2_offset_cntl
;
211 /* Flat panel regs */
212 u32 fp_crtc_h_total_disp
;
213 u32 fp_crtc_v_total_disp
;
216 u32 fp_h_sync_strt_wid
;
217 u32 fp2_h_sync_strt_wid
;
220 u32 fp_v_sync_strt_wid
;
221 u32 fp2_v_sync_strt_wid
;
226 u32 tmds_transmitter_cntl
;
228 /* Computed values for PLL */
239 /* Computed values for PLL2 */
240 u32 dot_clock_freq_2
;
257 int hOver_plus
, hSync_width
, hblank
;
258 int vOver_plus
, vSync_width
, vblank
;
259 int hAct_high
, vAct_high
, interlaced
;
261 int use_bios_dividers
;
267 struct radeonfb_info
;
269 #ifdef CONFIG_FB_RADEON_I2C
270 struct radeon_i2c_chan
{
271 struct radeonfb_info
*rinfo
;
273 struct i2c_adapter adapter
;
274 struct i2c_algo_bit_data algo
;
278 enum radeon_pm_mode
{
279 radeon_pm_none
= 0, /* Nothing supported */
280 radeon_pm_d2
= 0x00000001, /* Can do D2 state */
281 radeon_pm_off
= 0x00000002, /* Can resume from D3 cold */
284 typedef void (*reinit_function_ptr
)(struct radeonfb_info
*rinfo
);
286 struct radeonfb_info
{
287 struct fb_info
*info
;
289 struct radeon_regs state
;
290 struct radeon_regs init_state
;
294 unsigned long mmio_base_phys
;
295 unsigned long fb_base_phys
;
297 void __iomem
*mmio_base
;
298 void __iomem
*fb_base
;
300 unsigned long fb_local_base
;
302 struct pci_dev
*pdev
;
303 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
304 struct device_node
*of_node
;
307 void __iomem
*bios_seg
;
310 u32 pseudo_palette
[16];
311 struct { u8 red
, green
, blue
, pad
; }
318 unsigned long video_ram
;
319 unsigned long mapped_vram
;
323 int pitch
, bpp
, depth
;
330 struct panel_info panel_info
;
333 struct fb_videomode
*mon1_modedb
;
338 u32 dp_gui_master_cntl
;
350 enum radeon_pm_mode pm_mode
;
351 reinit_function_ptr reinit_func
;
353 /* Lock on register access */
356 /* Timer used for delayed LVDS operations */
357 struct timer_list lvds_timer
;
358 u32 pending_lvds_gen_cntl
;
360 #ifdef CONFIG_FB_RADEON_I2C
361 struct radeon_i2c_chan i2c
[4];
368 #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
375 /* Note about this function: we have some rare cases where we must not schedule,
376 * this typically happen with our special "wake up early" hook which allows us to
377 * wake up the graphic chip (and thus get the console back) before everything else
378 * on some machines that support that mechanism. At this point, interrupts are off
379 * and scheduling is not permitted
381 static inline void _radeon_msleep(struct radeonfb_info
*rinfo
, unsigned long ms
)
383 if (rinfo
->no_schedule
|| oops_in_progress
)
390 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
391 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
392 #define INREG16(addr) readw((rinfo->mmio_base)+addr)
393 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
394 #define INREG(addr) readl((rinfo->mmio_base)+addr)
395 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
397 static inline void _OUTREGP(struct radeonfb_info
*rinfo
, u32 addr
,
403 spin_lock_irqsave(&rinfo
->reg_lock
, flags
);
408 spin_unlock_irqrestore(&rinfo
->reg_lock
, flags
);
411 #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
414 * Note about PLL register accesses:
416 * I have removed the spinlock on them on purpose. The driver now
417 * expects that it will only manipulate the PLL registers in normal
418 * task environment, where radeon_msleep() will be called, protected
419 * by a semaphore (currently the console semaphore) so that no conflict
420 * will happen on the PLL register index.
422 * With the latest changes to the VT layer, this is guaranteed for all
423 * calls except the actual drawing/blits which aren't supposed to use
424 * the PLL registers anyway
426 * This is very important for the workarounds to work properly. The only
427 * possible exception to this rule is the call to unblank(), which may
428 * be done at irq time if an oops is in progress.
430 static inline void radeon_pll_errata_after_index(struct radeonfb_info
*rinfo
)
432 if (!(rinfo
->errata
& CHIP_ERRATA_PLL_DUMMYREADS
))
435 (void)INREG(CLOCK_CNTL_DATA
);
436 (void)INREG(CRTC_GEN_CNTL
);
439 static inline void radeon_pll_errata_after_data(struct radeonfb_info
*rinfo
)
441 if (rinfo
->errata
& CHIP_ERRATA_PLL_DELAY
) {
442 /* we can't deal with posted writes here ... */
443 _radeon_msleep(rinfo
, 5);
445 if (rinfo
->errata
& CHIP_ERRATA_R300_CG
) {
447 save
= INREG(CLOCK_CNTL_INDEX
);
448 tmp
= save
& ~(0x3f | PLL_WR_EN
);
449 OUTREG(CLOCK_CNTL_INDEX
, tmp
);
450 tmp
= INREG(CLOCK_CNTL_DATA
);
451 OUTREG(CLOCK_CNTL_INDEX
, save
);
455 static inline u32
__INPLL(struct radeonfb_info
*rinfo
, u32 addr
)
459 OUTREG8(CLOCK_CNTL_INDEX
, addr
& 0x0000003f);
460 radeon_pll_errata_after_index(rinfo
);
461 data
= INREG(CLOCK_CNTL_DATA
);
462 radeon_pll_errata_after_data(rinfo
);
466 static inline void __OUTPLL(struct radeonfb_info
*rinfo
, unsigned int index
,
470 OUTREG8(CLOCK_CNTL_INDEX
, (index
& 0x0000003f) | 0x00000080);
471 radeon_pll_errata_after_index(rinfo
);
472 OUTREG(CLOCK_CNTL_DATA
, val
);
473 radeon_pll_errata_after_data(rinfo
);
477 static inline void __OUTPLLP(struct radeonfb_info
*rinfo
, unsigned int index
,
482 tmp
= __INPLL(rinfo
, index
);
485 __OUTPLL(rinfo
, index
, tmp
);
489 #define INPLL(addr) __INPLL(rinfo, addr)
490 #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
491 #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
494 #define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
495 #define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
496 (readb(rinfo->bios_seg + (v) + 1) << 8))
497 #define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
498 (readb(rinfo->bios_seg + (v) + 1) << 8) | \
499 (readb(rinfo->bios_seg + (v) + 2) << 16) | \
500 (readb(rinfo->bios_seg + (v) + 3) << 24))
505 static inline int round_div(int num
, int den
)
507 return (num
+ (den
/ 2)) / den
;
510 static inline int var_to_depth(const struct fb_var_screeninfo
*var
)
512 if (var
->bits_per_pixel
!= 16)
513 return var
->bits_per_pixel
;
514 return (var
->green
.length
== 5) ? 15 : 16;
517 static inline u32
radeon_get_dstbpp(u16 depth
)
534 * 2D Engine helper routines
536 static inline void radeon_engine_flush (struct radeonfb_info
*rinfo
)
541 OUTREGP(RB2D_DSTCACHE_CTLSTAT
, RB2D_DC_FLUSH_ALL
,
544 for (i
=0; i
< 2000000; i
++) {
545 if (!(INREG(RB2D_DSTCACHE_CTLSTAT
) & RB2D_DC_BUSY
))
549 printk(KERN_ERR
"radeonfb: Flush Timeout !\n");
553 static inline void _radeon_fifo_wait(struct radeonfb_info
*rinfo
, int entries
)
557 for (i
=0; i
<2000000; i
++) {
558 if ((INREG(RBBM_STATUS
) & 0x7f) >= entries
)
562 printk(KERN_ERR
"radeonfb: FIFO Timeout !\n");
566 static inline void _radeon_engine_idle(struct radeonfb_info
*rinfo
)
570 /* ensure FIFO is empty before waiting for idle */
571 _radeon_fifo_wait (rinfo
, 64);
573 for (i
=0; i
<2000000; i
++) {
574 if (((INREG(RBBM_STATUS
) & GUI_ACTIVE
)) == 0) {
575 radeon_engine_flush (rinfo
);
580 printk(KERN_ERR
"radeonfb: Idle Timeout !\n");
584 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
585 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
586 #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
590 extern void radeon_create_i2c_busses(struct radeonfb_info
*rinfo
);
591 extern void radeon_delete_i2c_busses(struct radeonfb_info
*rinfo
);
592 extern int radeon_probe_i2c_connector(struct radeonfb_info
*rinfo
, int conn
, u8
**out_edid
);
595 extern int radeonfb_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
);
596 extern int radeonfb_pci_resume(struct pci_dev
*pdev
);
597 extern void radeonfb_pm_init(struct radeonfb_info
*rinfo
, int dynclk
, int ignore_devlist
, int force_sleep
);
598 extern void radeonfb_pm_exit(struct radeonfb_info
*rinfo
);
600 /* Monitor probe functions */
601 extern void radeon_probe_screens(struct radeonfb_info
*rinfo
,
602 const char *monitor_layout
, int ignore_edid
);
603 extern void radeon_check_modes(struct radeonfb_info
*rinfo
, const char *mode_option
);
604 extern int radeon_match_mode(struct radeonfb_info
*rinfo
,
605 struct fb_var_screeninfo
*dest
,
606 const struct fb_var_screeninfo
*src
);
608 /* Accel functions */
609 extern void radeonfb_fillrect(struct fb_info
*info
, const struct fb_fillrect
*region
);
610 extern void radeonfb_copyarea(struct fb_info
*info
, const struct fb_copyarea
*area
);
611 extern void radeonfb_imageblit(struct fb_info
*p
, const struct fb_image
*image
);
612 extern int radeonfb_sync(struct fb_info
*info
);
613 extern void radeonfb_engine_init (struct radeonfb_info
*rinfo
);
614 extern void radeonfb_engine_reset(struct radeonfb_info
*rinfo
);
616 /* Other functions */
617 extern int radeon_screen_blank(struct radeonfb_info
*rinfo
, int blank
, int mode_switch
);
618 extern void radeon_write_mode (struct radeonfb_info
*rinfo
, struct radeon_regs
*mode
,
621 /* Backlight functions */
622 #ifdef CONFIG_FB_RADEON_BACKLIGHT
623 extern void radeonfb_bl_init(struct radeonfb_info
*rinfo
);
624 extern void radeonfb_bl_exit(struct radeonfb_info
*rinfo
);
626 static inline void radeonfb_bl_init(struct radeonfb_info
*rinfo
) {}
627 static inline void radeonfb_bl_exit(struct radeonfb_info
*rinfo
) {}
630 #endif /* __RADEONFB_H__ */