2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/slab.h>
34 #include <video/da8xx-fb.h>
36 #define DRIVER_NAME "da8xx_lcdc"
38 /* LCD Status Register */
39 #define LCD_END_OF_FRAME1 BIT(9)
40 #define LCD_END_OF_FRAME0 BIT(8)
41 #define LCD_PL_LOAD_DONE BIT(6)
42 #define LCD_FIFO_UNDERFLOW BIT(5)
43 #define LCD_SYNC_LOST BIT(2)
45 /* LCD DMA Control Register */
46 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
47 #define LCD_DMA_BURST_1 0x0
48 #define LCD_DMA_BURST_2 0x1
49 #define LCD_DMA_BURST_4 0x2
50 #define LCD_DMA_BURST_8 0x3
51 #define LCD_DMA_BURST_16 0x4
52 #define LCD_END_OF_FRAME_INT_ENA BIT(2)
53 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
55 /* LCD Control Register */
56 #define LCD_CLK_DIVISOR(x) ((x) << 8)
57 #define LCD_RASTER_MODE 0x01
59 /* LCD Raster Control Register */
60 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
61 #define PALETTE_AND_DATA 0x00
62 #define PALETTE_ONLY 0x01
63 #define DATA_ONLY 0x02
65 #define LCD_MONO_8BIT_MODE BIT(9)
66 #define LCD_RASTER_ORDER BIT(8)
67 #define LCD_TFT_MODE BIT(7)
68 #define LCD_UNDERFLOW_INT_ENA BIT(6)
69 #define LCD_PL_ENABLE BIT(4)
70 #define LCD_MONOCHROME_MODE BIT(1)
71 #define LCD_RASTER_ENABLE BIT(0)
72 #define LCD_TFT_ALT_ENABLE BIT(23)
73 #define LCD_STN_565_ENABLE BIT(24)
75 /* LCD Raster Timing 2 Register */
76 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
77 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
78 #define LCD_SYNC_CTRL BIT(25)
79 #define LCD_SYNC_EDGE BIT(24)
80 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
81 #define LCD_INVERT_LINE_CLOCK BIT(21)
82 #define LCD_INVERT_FRAME_CLOCK BIT(20)
85 #define LCD_CTRL_REG 0x4
86 #define LCD_STAT_REG 0x8
87 #define LCD_RASTER_CTRL_REG 0x28
88 #define LCD_RASTER_TIMING_0_REG 0x2C
89 #define LCD_RASTER_TIMING_1_REG 0x30
90 #define LCD_RASTER_TIMING_2_REG 0x34
91 #define LCD_DMA_CTRL_REG 0x40
92 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
93 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
94 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
95 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
97 #define LCD_NUM_BUFFERS 2
99 #define WSI_TIMEOUT 50
100 #define PALETTE_SIZE 256
101 #define LEFT_MARGIN 64
102 #define RIGHT_MARGIN 64
103 #define UPPER_MARGIN 32
104 #define LOWER_MARGIN 32
106 static resource_size_t da8xx_fb_reg_base
;
107 static struct resource
*lcdc_regs
;
109 static inline unsigned int lcdc_read(unsigned int addr
)
111 return (unsigned int)__raw_readl(da8xx_fb_reg_base
+ (addr
));
114 static inline void lcdc_write(unsigned int val
, unsigned int addr
)
116 __raw_writel(val
, da8xx_fb_reg_base
+ (addr
));
119 struct da8xx_fb_par
{
120 resource_size_t p_palette_base
;
121 unsigned char *v_palette_base
;
122 dma_addr_t vram_phys
;
123 unsigned long vram_size
;
125 unsigned int dma_start
;
126 unsigned int dma_end
;
127 struct clk
*lcdc_clk
;
129 unsigned short pseudo_palette
[16];
130 unsigned int palette_sz
;
131 unsigned int pxl_clk
;
133 wait_queue_head_t vsync_wait
;
136 #ifdef CONFIG_CPU_FREQ
137 struct notifier_block freq_transition
;
139 void (*panel_power_ctrl
)(int);
142 /* Variable Screen Information */
143 static struct fb_var_screeninfo da8xx_fb_var __devinitdata
= {
151 .pixclock
= 46666, /* 46us - AUO display */
153 .left_margin
= LEFT_MARGIN
,
154 .right_margin
= RIGHT_MARGIN
,
155 .upper_margin
= UPPER_MARGIN
,
156 .lower_margin
= LOWER_MARGIN
,
158 .vmode
= FB_VMODE_NONINTERLACED
161 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata
= {
162 .id
= "DA8xx FB Drv",
163 .type
= FB_TYPE_PACKED_PIXELS
,
165 .visual
= FB_VISUAL_PSEUDOCOLOR
,
169 .accel
= FB_ACCEL_NONE
173 const char name
[25]; /* Full name <vendor>_<model> */
174 unsigned short width
;
175 unsigned short height
;
176 int hfp
; /* Horizontal front porch */
177 int hbp
; /* Horizontal back porch */
178 int hsw
; /* Horizontal Sync Pulse Width */
179 int vfp
; /* Vertical front porch */
180 int vbp
; /* Vertical back porch */
181 int vsw
; /* Vertical Sync Pulse Width */
182 unsigned int pxl_clk
; /* Pixel clock */
183 unsigned char invert_pxl_clk
; /* Invert Pixel clock */
186 static struct da8xx_panel known_lcd_panels
[] = {
187 /* Sharp LCD035Q3DG01 */
189 .name
= "Sharp_LCD035Q3DG01",
201 /* Sharp LK043T1DG01 */
203 .name
= "Sharp_LK043T1DG01",
217 /* Enable the Raster Engine of the LCD Controller */
218 static inline void lcd_enable_raster(void)
222 reg
= lcdc_read(LCD_RASTER_CTRL_REG
);
223 if (!(reg
& LCD_RASTER_ENABLE
))
224 lcdc_write(reg
| LCD_RASTER_ENABLE
, LCD_RASTER_CTRL_REG
);
227 /* Disable the Raster Engine of the LCD Controller */
228 static inline void lcd_disable_raster(void)
232 reg
= lcdc_read(LCD_RASTER_CTRL_REG
);
233 if (reg
& LCD_RASTER_ENABLE
)
234 lcdc_write(reg
& ~LCD_RASTER_ENABLE
, LCD_RASTER_CTRL_REG
);
237 static void lcd_blit(int load_mode
, struct da8xx_fb_par
*par
)
244 /* init reg to clear PLM (loading mode) fields */
245 reg_ras
= lcdc_read(LCD_RASTER_CTRL_REG
);
246 reg_ras
&= ~(3 << 20);
248 reg_dma
= lcdc_read(LCD_DMA_CTRL_REG
);
250 if (load_mode
== LOAD_DATA
) {
251 start
= par
->dma_start
;
254 reg_ras
|= LCD_PALETTE_LOAD_MODE(DATA_ONLY
);
255 reg_dma
|= LCD_END_OF_FRAME_INT_ENA
;
256 reg_dma
|= LCD_DUAL_FRAME_BUFFER_ENABLE
;
258 lcdc_write(start
, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
259 lcdc_write(end
, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
260 lcdc_write(start
, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG
);
261 lcdc_write(end
, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG
);
262 } else if (load_mode
== LOAD_PALETTE
) {
263 start
= par
->p_palette_base
;
264 end
= start
+ par
->palette_sz
- 1;
266 reg_ras
|= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY
);
267 reg_ras
|= LCD_PL_ENABLE
;
269 lcdc_write(start
, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
270 lcdc_write(end
, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
273 lcdc_write(reg_dma
, LCD_DMA_CTRL_REG
);
274 lcdc_write(reg_ras
, LCD_RASTER_CTRL_REG
);
277 * The Raster enable bit must be set after all other control fields are
283 /* Configure the Burst Size of DMA */
284 static int lcd_cfg_dma(int burst_size
)
288 reg
= lcdc_read(LCD_DMA_CTRL_REG
) & 0x00000001;
289 switch (burst_size
) {
291 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1
);
294 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2
);
297 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4
);
300 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8
);
303 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16
);
308 lcdc_write(reg
, LCD_DMA_CTRL_REG
);
313 static void lcd_cfg_ac_bias(int period
, int transitions_per_int
)
317 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
318 reg
= lcdc_read(LCD_RASTER_TIMING_2_REG
) & 0xFFF00000;
319 reg
|= LCD_AC_BIAS_FREQUENCY(period
) |
320 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int
);
321 lcdc_write(reg
, LCD_RASTER_TIMING_2_REG
);
324 static void lcd_cfg_horizontal_sync(int back_porch
, int pulse_width
,
329 reg
= lcdc_read(LCD_RASTER_TIMING_0_REG
) & 0xf;
330 reg
|= ((back_porch
& 0xff) << 24)
331 | ((front_porch
& 0xff) << 16)
332 | ((pulse_width
& 0x3f) << 10);
333 lcdc_write(reg
, LCD_RASTER_TIMING_0_REG
);
336 static void lcd_cfg_vertical_sync(int back_porch
, int pulse_width
,
341 reg
= lcdc_read(LCD_RASTER_TIMING_1_REG
) & 0x3ff;
342 reg
|= ((back_porch
& 0xff) << 24)
343 | ((front_porch
& 0xff) << 16)
344 | ((pulse_width
& 0x3f) << 10);
345 lcdc_write(reg
, LCD_RASTER_TIMING_1_REG
);
348 static int lcd_cfg_display(const struct lcd_ctrl_config
*cfg
)
352 reg
= lcdc_read(LCD_RASTER_CTRL_REG
) & ~(LCD_TFT_MODE
|
354 LCD_MONOCHROME_MODE
);
356 switch (cfg
->p_disp_panel
->panel_shade
) {
358 reg
|= LCD_MONOCHROME_MODE
;
359 if (cfg
->mono_8bit_mode
)
360 reg
|= LCD_MONO_8BIT_MODE
;
364 if (cfg
->tft_alt_mode
)
365 reg
|= LCD_TFT_ALT_ENABLE
;
369 if (cfg
->stn_565_mode
)
370 reg
|= LCD_STN_565_ENABLE
;
377 /* enable additional interrupts here */
378 reg
|= LCD_UNDERFLOW_INT_ENA
;
380 lcdc_write(reg
, LCD_RASTER_CTRL_REG
);
382 reg
= lcdc_read(LCD_RASTER_TIMING_2_REG
);
385 reg
|= LCD_SYNC_CTRL
;
387 reg
&= ~LCD_SYNC_CTRL
;
390 reg
|= LCD_SYNC_EDGE
;
392 reg
&= ~LCD_SYNC_EDGE
;
394 if (cfg
->invert_line_clock
)
395 reg
|= LCD_INVERT_LINE_CLOCK
;
397 reg
&= ~LCD_INVERT_LINE_CLOCK
;
399 if (cfg
->invert_frm_clock
)
400 reg
|= LCD_INVERT_FRAME_CLOCK
;
402 reg
&= ~LCD_INVERT_FRAME_CLOCK
;
404 lcdc_write(reg
, LCD_RASTER_TIMING_2_REG
);
409 static int lcd_cfg_frame_buffer(struct da8xx_fb_par
*par
, u32 width
, u32 height
,
410 u32 bpp
, u32 raster_order
)
414 /* Set the Panel Width */
415 /* Pixels per line = (PPL + 1)*16 */
416 /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
418 reg
= lcdc_read(LCD_RASTER_TIMING_0_REG
);
420 reg
|= ((width
>> 4) - 1) << 4;
421 lcdc_write(reg
, LCD_RASTER_TIMING_0_REG
);
423 /* Set the Panel Height */
424 reg
= lcdc_read(LCD_RASTER_TIMING_1_REG
);
425 reg
= ((height
- 1) & 0x3ff) | (reg
& 0xfffffc00);
426 lcdc_write(reg
, LCD_RASTER_TIMING_1_REG
);
428 /* Set the Raster Order of the Frame Buffer */
429 reg
= lcdc_read(LCD_RASTER_CTRL_REG
) & ~(1 << 8);
431 reg
|= LCD_RASTER_ORDER
;
432 lcdc_write(reg
, LCD_RASTER_CTRL_REG
);
439 par
->palette_sz
= 16 * 2;
443 par
->palette_sz
= 256 * 2;
453 static int fb_setcolreg(unsigned regno
, unsigned red
, unsigned green
,
454 unsigned blue
, unsigned transp
,
455 struct fb_info
*info
)
457 struct da8xx_fb_par
*par
= info
->par
;
458 unsigned short *palette
= (unsigned short *) par
->v_palette_base
;
465 if (info
->fix
.visual
== FB_VISUAL_DIRECTCOLOR
)
468 if (info
->var
.bits_per_pixel
== 8) {
473 pal
= (red
& 0x0f00);
474 pal
|= (green
& 0x00f0);
475 pal
|= (blue
& 0x000f);
477 if (palette
[regno
] != pal
) {
479 palette
[regno
] = pal
;
481 } else if ((info
->var
.bits_per_pixel
== 16) && regno
< 16) {
482 red
>>= (16 - info
->var
.red
.length
);
483 red
<<= info
->var
.red
.offset
;
485 green
>>= (16 - info
->var
.green
.length
);
486 green
<<= info
->var
.green
.offset
;
488 blue
>>= (16 - info
->var
.blue
.length
);
489 blue
<<= info
->var
.blue
.offset
;
491 par
->pseudo_palette
[regno
] = red
| green
| blue
;
493 if (palette
[0] != 0x4000) {
499 /* Update the palette in the h/w as needed. */
501 lcd_blit(LOAD_PALETTE
, par
);
506 static void lcd_reset(struct da8xx_fb_par
*par
)
508 /* Disable the Raster if previously Enabled */
509 lcd_disable_raster();
511 /* DMA has to be disabled */
512 lcdc_write(0, LCD_DMA_CTRL_REG
);
513 lcdc_write(0, LCD_RASTER_CTRL_REG
);
516 static void lcd_calc_clk_divider(struct da8xx_fb_par
*par
)
518 unsigned int lcd_clk
, div
;
520 lcd_clk
= clk_get_rate(par
->lcdc_clk
);
521 div
= lcd_clk
/ par
->pxl_clk
;
523 /* Configure the LCD clock divisor. */
524 lcdc_write(LCD_CLK_DIVISOR(div
) |
525 (LCD_RASTER_MODE
& 0x1), LCD_CTRL_REG
);
528 static int lcd_init(struct da8xx_fb_par
*par
, const struct lcd_ctrl_config
*cfg
,
529 struct da8xx_panel
*panel
)
536 /* Calculate the divider */
537 lcd_calc_clk_divider(par
);
539 if (panel
->invert_pxl_clk
)
540 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG
) |
541 LCD_INVERT_PIXEL_CLOCK
), LCD_RASTER_TIMING_2_REG
);
543 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG
) &
544 ~LCD_INVERT_PIXEL_CLOCK
), LCD_RASTER_TIMING_2_REG
);
546 /* Configure the DMA burst size. */
547 ret
= lcd_cfg_dma(cfg
->dma_burst_sz
);
551 /* Configure the AC bias properties. */
552 lcd_cfg_ac_bias(cfg
->ac_bias
, cfg
->ac_bias_intrpt
);
554 /* Configure the vertical and horizontal sync properties. */
555 lcd_cfg_vertical_sync(panel
->vbp
, panel
->vsw
, panel
->vfp
);
556 lcd_cfg_horizontal_sync(panel
->hbp
, panel
->hsw
, panel
->hfp
);
558 /* Configure for disply */
559 ret
= lcd_cfg_display(cfg
);
563 if (QVGA
!= cfg
->p_disp_panel
->panel_type
)
566 if (cfg
->bpp
<= cfg
->p_disp_panel
->max_bpp
&&
567 cfg
->bpp
>= cfg
->p_disp_panel
->min_bpp
)
570 bpp
= cfg
->p_disp_panel
->max_bpp
;
573 ret
= lcd_cfg_frame_buffer(par
, (unsigned int)panel
->width
,
574 (unsigned int)panel
->height
, bpp
,
580 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG
) & 0xfff00fff) |
581 (cfg
->fdd
<< 12), LCD_RASTER_CTRL_REG
);
586 static irqreturn_t
lcdc_irq_handler(int irq
, void *arg
)
588 struct da8xx_fb_par
*par
= arg
;
589 u32 stat
= lcdc_read(LCD_STAT_REG
);
592 if ((stat
& LCD_SYNC_LOST
) && (stat
& LCD_FIFO_UNDERFLOW
)) {
593 lcd_disable_raster();
594 lcdc_write(stat
, LCD_STAT_REG
);
596 } else if (stat
& LCD_PL_LOAD_DONE
) {
598 * Must disable raster before changing state of any control bit.
599 * And also must be disabled before clearing the PL loading
600 * interrupt via the following write to the status register. If
601 * this is done after then one gets multiple PL done interrupts.
603 lcd_disable_raster();
605 lcdc_write(stat
, LCD_STAT_REG
);
607 /* Disable PL completion inerrupt */
608 reg_ras
= lcdc_read(LCD_RASTER_CTRL_REG
);
609 reg_ras
&= ~LCD_PL_ENABLE
;
610 lcdc_write(reg_ras
, LCD_RASTER_CTRL_REG
);
612 /* Setup and start data loading mode */
613 lcd_blit(LOAD_DATA
, par
);
615 lcdc_write(stat
, LCD_STAT_REG
);
617 if (stat
& LCD_END_OF_FRAME0
) {
618 lcdc_write(par
->dma_start
,
619 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
620 lcdc_write(par
->dma_end
,
621 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
623 wake_up_interruptible(&par
->vsync_wait
);
626 if (stat
& LCD_END_OF_FRAME1
) {
627 lcdc_write(par
->dma_start
,
628 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG
);
629 lcdc_write(par
->dma_end
,
630 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG
);
632 wake_up_interruptible(&par
->vsync_wait
);
639 static int fb_check_var(struct fb_var_screeninfo
*var
,
640 struct fb_info
*info
)
644 switch (var
->bits_per_pixel
) {
649 var
->green
.offset
= 0;
650 var
->green
.length
= 8;
651 var
->blue
.offset
= 0;
652 var
->blue
.length
= 8;
653 var
->transp
.offset
= 0;
654 var
->transp
.length
= 0;
659 var
->green
.offset
= 0;
660 var
->green
.length
= 4;
661 var
->blue
.offset
= 0;
662 var
->blue
.length
= 4;
663 var
->transp
.offset
= 0;
664 var
->transp
.length
= 0;
666 case 16: /* RGB 565 */
667 var
->red
.offset
= 11;
669 var
->green
.offset
= 5;
670 var
->green
.length
= 6;
671 var
->blue
.offset
= 0;
672 var
->blue
.length
= 5;
673 var
->transp
.offset
= 0;
674 var
->transp
.length
= 0;
680 var
->red
.msb_right
= 0;
681 var
->green
.msb_right
= 0;
682 var
->blue
.msb_right
= 0;
683 var
->transp
.msb_right
= 0;
687 #ifdef CONFIG_CPU_FREQ
688 static int lcd_da8xx_cpufreq_transition(struct notifier_block
*nb
,
689 unsigned long val
, void *data
)
691 struct da8xx_fb_par
*par
;
693 par
= container_of(nb
, struct da8xx_fb_par
, freq_transition
);
694 if (val
== CPUFREQ_PRECHANGE
) {
695 lcd_disable_raster();
696 } else if (val
== CPUFREQ_POSTCHANGE
) {
697 lcd_calc_clk_divider(par
);
704 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par
*par
)
706 par
->freq_transition
.notifier_call
= lcd_da8xx_cpufreq_transition
;
708 return cpufreq_register_notifier(&par
->freq_transition
,
709 CPUFREQ_TRANSITION_NOTIFIER
);
712 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par
*par
)
714 cpufreq_unregister_notifier(&par
->freq_transition
,
715 CPUFREQ_TRANSITION_NOTIFIER
);
719 static int __devexit
fb_remove(struct platform_device
*dev
)
721 struct fb_info
*info
= dev_get_drvdata(&dev
->dev
);
724 struct da8xx_fb_par
*par
= info
->par
;
726 #ifdef CONFIG_CPU_FREQ
727 lcd_da8xx_cpufreq_deregister(par
);
729 if (par
->panel_power_ctrl
)
730 par
->panel_power_ctrl(0);
732 lcd_disable_raster();
733 lcdc_write(0, LCD_RASTER_CTRL_REG
);
736 lcdc_write(0, LCD_DMA_CTRL_REG
);
738 unregister_framebuffer(info
);
739 fb_dealloc_cmap(&info
->cmap
);
740 dma_free_coherent(NULL
, PALETTE_SIZE
, par
->v_palette_base
,
741 par
->p_palette_base
);
742 dma_free_coherent(NULL
, par
->vram_size
, par
->vram_virt
,
744 free_irq(par
->irq
, par
);
745 clk_disable(par
->lcdc_clk
);
746 clk_put(par
->lcdc_clk
);
747 framebuffer_release(info
);
748 iounmap((void __iomem
*)da8xx_fb_reg_base
);
749 release_mem_region(lcdc_regs
->start
, resource_size(lcdc_regs
));
756 * Function to wait for vertical sync which for this LCD peripheral
757 * translates into waiting for the current raster frame to complete.
759 static int fb_wait_for_vsync(struct fb_info
*info
)
761 struct da8xx_fb_par
*par
= info
->par
;
765 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
766 * race condition here where the ISR could have occurred just before or
767 * just after this set. But since we are just coarsely waiting for
768 * a frame to complete then that's OK. i.e. if the frame completed
769 * just before this code executed then we have to wait another full
770 * frame time but there is no way to avoid such a situation. On the
771 * other hand if the frame completed just after then we don't need
772 * to wait long at all. Either way we are guaranteed to return to the
773 * user immediately after a frame completion which is all that is
777 ret
= wait_event_interruptible_timeout(par
->vsync_wait
,
778 par
->vsync_flag
!= 0,
788 static int fb_ioctl(struct fb_info
*info
, unsigned int cmd
,
791 struct lcd_sync_arg sync_arg
;
794 case FBIOGET_CONTRAST
:
795 case FBIOPUT_CONTRAST
:
796 case FBIGET_BRIGHTNESS
:
797 case FBIPUT_BRIGHTNESS
:
802 if (copy_from_user(&sync_arg
, (char *)arg
,
803 sizeof(struct lcd_sync_arg
)))
805 lcd_cfg_horizontal_sync(sync_arg
.back_porch
,
806 sync_arg
.pulse_width
,
807 sync_arg
.front_porch
);
810 if (copy_from_user(&sync_arg
, (char *)arg
,
811 sizeof(struct lcd_sync_arg
)))
813 lcd_cfg_vertical_sync(sync_arg
.back_porch
,
814 sync_arg
.pulse_width
,
815 sync_arg
.front_porch
);
817 case FBIO_WAITFORVSYNC
:
818 return fb_wait_for_vsync(info
);
825 static int cfb_blank(int blank
, struct fb_info
*info
)
827 struct da8xx_fb_par
*par
= info
->par
;
830 if (par
->blank
== blank
)
835 case FB_BLANK_UNBLANK
:
836 if (par
->panel_power_ctrl
)
837 par
->panel_power_ctrl(1);
841 case FB_BLANK_POWERDOWN
:
842 if (par
->panel_power_ctrl
)
843 par
->panel_power_ctrl(0);
845 lcd_disable_raster();
855 * Set new x,y offsets in the virtual display for the visible area and switch
858 static int da8xx_pan_display(struct fb_var_screeninfo
*var
,
862 struct fb_var_screeninfo new_var
;
863 struct da8xx_fb_par
*par
= fbi
->par
;
864 struct fb_fix_screeninfo
*fix
= &fbi
->fix
;
868 if (var
->xoffset
!= fbi
->var
.xoffset
||
869 var
->yoffset
!= fbi
->var
.yoffset
) {
870 memcpy(&new_var
, &fbi
->var
, sizeof(new_var
));
871 new_var
.xoffset
= var
->xoffset
;
872 new_var
.yoffset
= var
->yoffset
;
873 if (fb_check_var(&new_var
, fbi
))
876 memcpy(&fbi
->var
, &new_var
, sizeof(new_var
));
878 start
= fix
->smem_start
+
879 new_var
.yoffset
* fix
->line_length
+
880 new_var
.xoffset
* fbi
->var
.bits_per_pixel
/ 8;
881 end
= start
+ fbi
->var
.yres
* fix
->line_length
- 1;
882 par
->dma_start
= start
;
890 static struct fb_ops da8xx_fb_ops
= {
891 .owner
= THIS_MODULE
,
892 .fb_check_var
= fb_check_var
,
893 .fb_setcolreg
= fb_setcolreg
,
894 .fb_pan_display
= da8xx_pan_display
,
895 .fb_ioctl
= fb_ioctl
,
896 .fb_fillrect
= cfb_fillrect
,
897 .fb_copyarea
= cfb_copyarea
,
898 .fb_imageblit
= cfb_imageblit
,
899 .fb_blank
= cfb_blank
,
902 static int __devinit
fb_probe(struct platform_device
*device
)
904 struct da8xx_lcdc_platform_data
*fb_pdata
=
905 device
->dev
.platform_data
;
906 struct lcd_ctrl_config
*lcd_cfg
;
907 struct da8xx_panel
*lcdc_info
;
908 struct fb_info
*da8xx_fb_info
;
909 struct clk
*fb_clk
= NULL
;
910 struct da8xx_fb_par
*par
;
914 if (fb_pdata
== NULL
) {
915 dev_err(&device
->dev
, "Can not get platform data\n");
919 lcdc_regs
= platform_get_resource(device
, IORESOURCE_MEM
, 0);
921 dev_err(&device
->dev
,
922 "Can not get memory resource for LCD controller\n");
926 len
= resource_size(lcdc_regs
);
928 lcdc_regs
= request_mem_region(lcdc_regs
->start
, len
, lcdc_regs
->name
);
932 da8xx_fb_reg_base
= (resource_size_t
)ioremap(lcdc_regs
->start
, len
);
933 if (!da8xx_fb_reg_base
) {
935 goto err_request_mem
;
938 fb_clk
= clk_get(&device
->dev
, NULL
);
939 if (IS_ERR(fb_clk
)) {
940 dev_err(&device
->dev
, "Can not get device clock\n");
944 ret
= clk_enable(fb_clk
);
948 for (i
= 0, lcdc_info
= known_lcd_panels
;
949 i
< ARRAY_SIZE(known_lcd_panels
);
951 if (strcmp(fb_pdata
->type
, lcdc_info
->name
) == 0)
955 if (i
== ARRAY_SIZE(known_lcd_panels
)) {
956 dev_err(&device
->dev
, "GLCD: No valid panel found\n");
958 goto err_clk_disable
;
960 dev_info(&device
->dev
, "GLCD: Found %s panel\n",
963 lcd_cfg
= (struct lcd_ctrl_config
*)fb_pdata
->controller_data
;
965 da8xx_fb_info
= framebuffer_alloc(sizeof(struct da8xx_fb_par
),
967 if (!da8xx_fb_info
) {
968 dev_dbg(&device
->dev
, "Memory allocation failed for fb_info\n");
970 goto err_clk_disable
;
973 par
= da8xx_fb_info
->par
;
974 par
->lcdc_clk
= fb_clk
;
975 par
->pxl_clk
= lcdc_info
->pxl_clk
;
976 if (fb_pdata
->panel_power_ctrl
) {
977 par
->panel_power_ctrl
= fb_pdata
->panel_power_ctrl
;
978 par
->panel_power_ctrl(1);
981 if (lcd_init(par
, lcd_cfg
, lcdc_info
) < 0) {
982 dev_err(&device
->dev
, "lcd_init failed\n");
987 /* allocate frame buffer */
988 par
->vram_size
= lcdc_info
->width
* lcdc_info
->height
* lcd_cfg
->bpp
;
989 par
->vram_size
= PAGE_ALIGN(par
->vram_size
/8);
990 par
->vram_size
= par
->vram_size
* LCD_NUM_BUFFERS
;
992 par
->vram_virt
= dma_alloc_coherent(NULL
,
994 (resource_size_t
*) &par
->vram_phys
,
995 GFP_KERNEL
| GFP_DMA
);
996 if (!par
->vram_virt
) {
997 dev_err(&device
->dev
,
998 "GLCD: kmalloc for frame buffer failed\n");
1000 goto err_release_fb
;
1003 da8xx_fb_info
->screen_base
= (char __iomem
*) par
->vram_virt
;
1004 da8xx_fb_fix
.smem_start
= par
->vram_phys
;
1005 da8xx_fb_fix
.smem_len
= par
->vram_size
;
1006 da8xx_fb_fix
.line_length
= (lcdc_info
->width
* lcd_cfg
->bpp
) / 8;
1008 par
->dma_start
= par
->vram_phys
;
1009 par
->dma_end
= par
->dma_start
+ lcdc_info
->height
*
1010 da8xx_fb_fix
.line_length
- 1;
1012 /* allocate palette buffer */
1013 par
->v_palette_base
= dma_alloc_coherent(NULL
,
1016 &par
->p_palette_base
,
1017 GFP_KERNEL
| GFP_DMA
);
1018 if (!par
->v_palette_base
) {
1019 dev_err(&device
->dev
,
1020 "GLCD: kmalloc for palette buffer failed\n");
1022 goto err_release_fb_mem
;
1024 memset(par
->v_palette_base
, 0, PALETTE_SIZE
);
1026 par
->irq
= platform_get_irq(device
, 0);
1029 goto err_release_pl_mem
;
1032 /* Initialize par */
1033 da8xx_fb_info
->var
.bits_per_pixel
= lcd_cfg
->bpp
;
1035 da8xx_fb_var
.xres
= lcdc_info
->width
;
1036 da8xx_fb_var
.xres_virtual
= lcdc_info
->width
;
1038 da8xx_fb_var
.yres
= lcdc_info
->height
;
1039 da8xx_fb_var
.yres_virtual
= lcdc_info
->height
* LCD_NUM_BUFFERS
;
1041 da8xx_fb_var
.grayscale
=
1042 lcd_cfg
->p_disp_panel
->panel_shade
== MONOCHROME
? 1 : 0;
1043 da8xx_fb_var
.bits_per_pixel
= lcd_cfg
->bpp
;
1045 da8xx_fb_var
.hsync_len
= lcdc_info
->hsw
;
1046 da8xx_fb_var
.vsync_len
= lcdc_info
->vsw
;
1048 /* Initialize fbinfo */
1049 da8xx_fb_info
->flags
= FBINFO_FLAG_DEFAULT
;
1050 da8xx_fb_info
->fix
= da8xx_fb_fix
;
1051 da8xx_fb_info
->var
= da8xx_fb_var
;
1052 da8xx_fb_info
->fbops
= &da8xx_fb_ops
;
1053 da8xx_fb_info
->pseudo_palette
= par
->pseudo_palette
;
1054 da8xx_fb_info
->fix
.visual
= (da8xx_fb_info
->var
.bits_per_pixel
<= 8) ?
1055 FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_TRUECOLOR
;
1057 ret
= fb_alloc_cmap(&da8xx_fb_info
->cmap
, PALETTE_SIZE
, 0);
1059 goto err_release_pl_mem
;
1060 da8xx_fb_info
->cmap
.len
= par
->palette_sz
;
1062 /* initialize var_screeninfo */
1063 da8xx_fb_var
.activate
= FB_ACTIVATE_FORCE
;
1064 fb_set_var(da8xx_fb_info
, &da8xx_fb_var
);
1066 dev_set_drvdata(&device
->dev
, da8xx_fb_info
);
1068 /* initialize the vsync wait queue */
1069 init_waitqueue_head(&par
->vsync_wait
);
1070 par
->vsync_timeout
= HZ
/ 5;
1072 /* Register the Frame Buffer */
1073 if (register_framebuffer(da8xx_fb_info
) < 0) {
1074 dev_err(&device
->dev
,
1075 "GLCD: Frame Buffer Registration Failed!\n");
1077 goto err_dealloc_cmap
;
1080 #ifdef CONFIG_CPU_FREQ
1081 ret
= lcd_da8xx_cpufreq_register(par
);
1083 dev_err(&device
->dev
, "failed to register cpufreq\n");
1088 ret
= request_irq(par
->irq
, lcdc_irq_handler
, 0, DRIVER_NAME
, par
);
1094 #ifdef CONFIG_CPU_FREQ
1095 lcd_da8xx_cpufreq_deregister(par
);
1098 unregister_framebuffer(da8xx_fb_info
);
1101 fb_dealloc_cmap(&da8xx_fb_info
->cmap
);
1104 dma_free_coherent(NULL
, PALETTE_SIZE
, par
->v_palette_base
,
1105 par
->p_palette_base
);
1108 dma_free_coherent(NULL
, par
->vram_size
, par
->vram_virt
, par
->vram_phys
);
1111 framebuffer_release(da8xx_fb_info
);
1114 clk_disable(fb_clk
);
1120 iounmap((void __iomem
*)da8xx_fb_reg_base
);
1123 release_mem_region(lcdc_regs
->start
, len
);
1129 static int fb_suspend(struct platform_device
*dev
, pm_message_t state
)
1131 struct fb_info
*info
= platform_get_drvdata(dev
);
1132 struct da8xx_fb_par
*par
= info
->par
;
1135 if (par
->panel_power_ctrl
)
1136 par
->panel_power_ctrl(0);
1138 fb_set_suspend(info
, 1);
1139 lcd_disable_raster();
1140 clk_disable(par
->lcdc_clk
);
1145 static int fb_resume(struct platform_device
*dev
)
1147 struct fb_info
*info
= platform_get_drvdata(dev
);
1148 struct da8xx_fb_par
*par
= info
->par
;
1151 if (par
->panel_power_ctrl
)
1152 par
->panel_power_ctrl(1);
1154 clk_enable(par
->lcdc_clk
);
1155 lcd_enable_raster();
1156 fb_set_suspend(info
, 0);
1162 #define fb_suspend NULL
1163 #define fb_resume NULL
1166 static struct platform_driver da8xx_fb_driver
= {
1168 .remove
= __devexit_p(fb_remove
),
1169 .suspend
= fb_suspend
,
1170 .resume
= fb_resume
,
1172 .name
= DRIVER_NAME
,
1173 .owner
= THIS_MODULE
,
1177 static int __init
da8xx_fb_init(void)
1179 return platform_driver_register(&da8xx_fb_driver
);
1182 static void __exit
da8xx_fb_cleanup(void)
1184 platform_driver_unregister(&da8xx_fb_driver
);
1187 module_init(da8xx_fb_init
);
1188 module_exit(da8xx_fb_cleanup
);
1190 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1191 MODULE_AUTHOR("Texas Instruments");
1192 MODULE_LICENSE("GPL");