projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'sh-mobile-lcdc' of git://linuxtv.org/pinchartl/fbdev into fbdev-next
[deliverable/linux.git] / drivers / video / da8xx-fb.c
1 /*
2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
4 *
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/slab.h>
34 #include <video/da8xx-fb.h>
35
36 #define DRIVER_NAME "da8xx_lcdc"
37
38 #define LCD_VERSION_1 1
39 #define LCD_VERSION_2 2
40
41 /* LCD Status Register */
42 #define LCD_END_OF_FRAME1 BIT(9)
43 #define LCD_END_OF_FRAME0 BIT(8)
44 #define LCD_PL_LOAD_DONE BIT(6)
45 #define LCD_FIFO_UNDERFLOW BIT(5)
46 #define LCD_SYNC_LOST BIT(2)
47
48 /* LCD DMA Control Register */
49 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
50 #define LCD_DMA_BURST_1 0x0
51 #define LCD_DMA_BURST_2 0x1
52 #define LCD_DMA_BURST_4 0x2
53 #define LCD_DMA_BURST_8 0x3
54 #define LCD_DMA_BURST_16 0x4
55 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
56 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
57 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
58 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
59
60 /* LCD Control Register */
61 #define LCD_CLK_DIVISOR(x) ((x) << 8)
62 #define LCD_RASTER_MODE 0x01
63
64 /* LCD Raster Control Register */
65 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
66 #define PALETTE_AND_DATA 0x00
67 #define PALETTE_ONLY 0x01
68 #define DATA_ONLY 0x02
69
70 #define LCD_MONO_8BIT_MODE BIT(9)
71 #define LCD_RASTER_ORDER BIT(8)
72 #define LCD_TFT_MODE BIT(7)
73 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
74 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
75 #define LCD_V1_PL_INT_ENA BIT(4)
76 #define LCD_V2_PL_INT_ENA BIT(6)
77 #define LCD_MONOCHROME_MODE BIT(1)
78 #define LCD_RASTER_ENABLE BIT(0)
79 #define LCD_TFT_ALT_ENABLE BIT(23)
80 #define LCD_STN_565_ENABLE BIT(24)
81 #define LCD_V2_DMA_CLK_EN BIT(2)
82 #define LCD_V2_LIDD_CLK_EN BIT(1)
83 #define LCD_V2_CORE_CLK_EN BIT(0)
84 #define LCD_V2_LPP_B10 26
85
86 /* LCD Raster Timing 2 Register */
87 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
88 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
89 #define LCD_SYNC_CTRL BIT(25)
90 #define LCD_SYNC_EDGE BIT(24)
91 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
92 #define LCD_INVERT_LINE_CLOCK BIT(21)
93 #define LCD_INVERT_FRAME_CLOCK BIT(20)
94
95 /* LCD Block */
96 #define LCD_PID_REG 0x0
97 #define LCD_CTRL_REG 0x4
98 #define LCD_STAT_REG 0x8
99 #define LCD_RASTER_CTRL_REG 0x28
100 #define LCD_RASTER_TIMING_0_REG 0x2C
101 #define LCD_RASTER_TIMING_1_REG 0x30
102 #define LCD_RASTER_TIMING_2_REG 0x34
103 #define LCD_DMA_CTRL_REG 0x40
104 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
105 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
106 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
107 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
108
109 /* Interrupt Registers available only in Version 2 */
110 #define LCD_RAW_STAT_REG 0x58
111 #define LCD_MASKED_STAT_REG 0x5c
112 #define LCD_INT_ENABLE_SET_REG 0x60
113 #define LCD_INT_ENABLE_CLR_REG 0x64
114 #define LCD_END_OF_INT_IND_REG 0x68
115
116 /* Clock registers available only on Version 2 */
117 #define LCD_CLK_ENABLE_REG 0x6c
118 #define LCD_CLK_RESET_REG 0x70
119
120 #define LCD_NUM_BUFFERS 2
121
122 #define WSI_TIMEOUT 50
123 #define PALETTE_SIZE 256
124 #define LEFT_MARGIN 64
125 #define RIGHT_MARGIN 64
126 #define UPPER_MARGIN 32
127 #define LOWER_MARGIN 32
128
129 static resource_size_t da8xx_fb_reg_base;
130 static struct resource *lcdc_regs;
131 static unsigned int lcd_revision;
132 static irq_handler_t lcdc_irq_handler;
133
134 static inline unsigned int lcdc_read(unsigned int addr)
135 {
136 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
137 }
138
139 static inline void lcdc_write(unsigned int val, unsigned int addr)
140 {
141 __raw_writel(val, da8xx_fb_reg_base + (addr));
142 }
143
144 struct da8xx_fb_par {
145 resource_size_t p_palette_base;
146 unsigned char *v_palette_base;
147 dma_addr_t vram_phys;
148 unsigned long vram_size;
149 void *vram_virt;
150 unsigned int dma_start;
151 unsigned int dma_end;
152 struct clk *lcdc_clk;
153 int irq;
154 unsigned short pseudo_palette[16];
155 unsigned int palette_sz;
156 unsigned int pxl_clk;
157 int blank;
158 wait_queue_head_t vsync_wait;
159 int vsync_flag;
160 int vsync_timeout;
161 #ifdef CONFIG_CPU_FREQ
162 struct notifier_block freq_transition;
163 #endif
164 void (*panel_power_ctrl)(int);
165 };
166
167 /* Variable Screen Information */
168 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
169 .xoffset = 0,
170 .yoffset = 0,
171 .transp = {0, 0, 0},
172 .nonstd = 0,
173 .activate = 0,
174 .height = -1,
175 .width = -1,
176 .pixclock = 46666, /* 46us - AUO display */
177 .accel_flags = 0,
178 .left_margin = LEFT_MARGIN,
179 .right_margin = RIGHT_MARGIN,
180 .upper_margin = UPPER_MARGIN,
181 .lower_margin = LOWER_MARGIN,
182 .sync = 0,
183 .vmode = FB_VMODE_NONINTERLACED
184 };
185
186 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
187 .id = "DA8xx FB Drv",
188 .type = FB_TYPE_PACKED_PIXELS,
189 .type_aux = 0,
190 .visual = FB_VISUAL_PSEUDOCOLOR,
191 .xpanstep = 0,
192 .ypanstep = 1,
193 .ywrapstep = 0,
194 .accel = FB_ACCEL_NONE
195 };
196
197 struct da8xx_panel {
198 const char name[25]; /* Full name <vendor>_<model> */
199 unsigned short width;
200 unsigned short height;
201 int hfp; /* Horizontal front porch */
202 int hbp; /* Horizontal back porch */
203 int hsw; /* Horizontal Sync Pulse Width */
204 int vfp; /* Vertical front porch */
205 int vbp; /* Vertical back porch */
206 int vsw; /* Vertical Sync Pulse Width */
207 unsigned int pxl_clk; /* Pixel clock */
208 unsigned char invert_pxl_clk; /* Invert Pixel clock */
209 };
210
211 static struct da8xx_panel known_lcd_panels[] = {
212 /* Sharp LCD035Q3DG01 */
213 [0] = {
214 .name = "Sharp_LCD035Q3DG01",
215 .width = 320,
216 .height = 240,
217 .hfp = 8,
218 .hbp = 6,
219 .hsw = 0,
220 .vfp = 2,
221 .vbp = 2,
222 .vsw = 0,
223 .pxl_clk = 4608000,
224 .invert_pxl_clk = 1,
225 },
226 /* Sharp LK043T1DG01 */
227 [1] = {
228 .name = "Sharp_LK043T1DG01",
229 .width = 480,
230 .height = 272,
231 .hfp = 2,
232 .hbp = 2,
233 .hsw = 41,
234 .vfp = 2,
235 .vbp = 2,
236 .vsw = 10,
237 .pxl_clk = 7833600,
238 .invert_pxl_clk = 0,
239 },
240 };
241
242 /* Enable the Raster Engine of the LCD Controller */
243 static inline void lcd_enable_raster(void)
244 {
245 u32 reg;
246
247 reg = lcdc_read(LCD_RASTER_CTRL_REG);
248 if (!(reg & LCD_RASTER_ENABLE))
249 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
250 }
251
252 /* Disable the Raster Engine of the LCD Controller */
253 static inline void lcd_disable_raster(void)
254 {
255 u32 reg;
256
257 reg = lcdc_read(LCD_RASTER_CTRL_REG);
258 if (reg & LCD_RASTER_ENABLE)
259 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
260 }
261
262 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
263 {
264 u32 start;
265 u32 end;
266 u32 reg_ras;
267 u32 reg_dma;
268 u32 reg_int;
269
270 /* init reg to clear PLM (loading mode) fields */
271 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
272 reg_ras &= ~(3 << 20);
273
274 reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
275
276 if (load_mode == LOAD_DATA) {
277 start = par->dma_start;
278 end = par->dma_end;
279
280 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
281 if (lcd_revision == LCD_VERSION_1) {
282 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
283 } else {
284 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
285 LCD_V2_END_OF_FRAME0_INT_ENA |
286 LCD_V2_END_OF_FRAME1_INT_ENA;
287 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
288 }
289 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
290
291 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
292 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
293 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
294 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
295 } else if (load_mode == LOAD_PALETTE) {
296 start = par->p_palette_base;
297 end = start + par->palette_sz - 1;
298
299 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
300
301 if (lcd_revision == LCD_VERSION_1) {
302 reg_ras |= LCD_V1_PL_INT_ENA;
303 } else {
304 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
305 LCD_V2_PL_INT_ENA;
306 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
307 }
308
309 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
310 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
311 }
312
313 lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
314 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
315
316 /*
317 * The Raster enable bit must be set after all other control fields are
318 * set.
319 */
320 lcd_enable_raster();
321 }
322
323 /* Configure the Burst Size of DMA */
324 static int lcd_cfg_dma(int burst_size)
325 {
326 u32 reg;
327
328 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
329 switch (burst_size) {
330 case 1:
331 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
332 break;
333 case 2:
334 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
335 break;
336 case 4:
337 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
338 break;
339 case 8:
340 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
341 break;
342 case 16:
343 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
344 break;
345 default:
346 return -EINVAL;
347 }
348 lcdc_write(reg, LCD_DMA_CTRL_REG);
349
350 return 0;
351 }
352
353 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
354 {
355 u32 reg;
356
357 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
358 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
359 reg |= LCD_AC_BIAS_FREQUENCY(period) |
360 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
361 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
362 }
363
364 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
365 int front_porch)
366 {
367 u32 reg;
368
369 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
370 reg |= ((back_porch & 0xff) << 24)
371 | ((front_porch & 0xff) << 16)
372 | ((pulse_width & 0x3f) << 10);
373 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
374 }
375
376 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
377 int front_porch)
378 {
379 u32 reg;
380
381 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
382 reg |= ((back_porch & 0xff) << 24)
383 | ((front_porch & 0xff) << 16)
384 | ((pulse_width & 0x3f) << 10);
385 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
386 }
387
388 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
389 {
390 u32 reg;
391 u32 reg_int;
392
393 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
394 LCD_MONO_8BIT_MODE |
395 LCD_MONOCHROME_MODE);
396
397 switch (cfg->p_disp_panel->panel_shade) {
398 case MONOCHROME:
399 reg |= LCD_MONOCHROME_MODE;
400 if (cfg->mono_8bit_mode)
401 reg |= LCD_MONO_8BIT_MODE;
402 break;
403 case COLOR_ACTIVE:
404 reg |= LCD_TFT_MODE;
405 if (cfg->tft_alt_mode)
406 reg |= LCD_TFT_ALT_ENABLE;
407 break;
408
409 case COLOR_PASSIVE:
410 if (cfg->stn_565_mode)
411 reg |= LCD_STN_565_ENABLE;
412 break;
413
414 default:
415 return -EINVAL;
416 }
417
418 /* enable additional interrupts here */
419 if (lcd_revision == LCD_VERSION_1) {
420 reg |= LCD_V1_UNDERFLOW_INT_ENA;
421 } else {
422 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
423 LCD_V2_UNDERFLOW_INT_ENA;
424 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
425 }
426
427 lcdc_write(reg, LCD_RASTER_CTRL_REG);
428
429 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
430
431 if (cfg->sync_ctrl)
432 reg |= LCD_SYNC_CTRL;
433 else
434 reg &= ~LCD_SYNC_CTRL;
435
436 if (cfg->sync_edge)
437 reg |= LCD_SYNC_EDGE;
438 else
439 reg &= ~LCD_SYNC_EDGE;
440
441 if (cfg->invert_line_clock)
442 reg |= LCD_INVERT_LINE_CLOCK;
443 else
444 reg &= ~LCD_INVERT_LINE_CLOCK;
445
446 if (cfg->invert_frm_clock)
447 reg |= LCD_INVERT_FRAME_CLOCK;
448 else
449 reg &= ~LCD_INVERT_FRAME_CLOCK;
450
451 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
452
453 return 0;
454 }
455
456 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
457 u32 bpp, u32 raster_order)
458 {
459 u32 reg;
460
461 /* Set the Panel Width */
462 /* Pixels per line = (PPL + 1)*16 */
463 /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
464 width &= 0x3f0;
465 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
466 reg &= 0xfffffc00;
467 reg |= ((width >> 4) - 1) << 4;
468 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
469
470 /* Set the Panel Height */
471 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
472 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
473 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
474
475 /* Set the Raster Order of the Frame Buffer */
476 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
477 if (raster_order)
478 reg |= LCD_RASTER_ORDER;
479 lcdc_write(reg, LCD_RASTER_CTRL_REG);
480
481 switch (bpp) {
482 case 1:
483 case 2:
484 case 4:
485 case 16:
486 par->palette_sz = 16 * 2;
487 break;
488
489 case 8:
490 par->palette_sz = 256 * 2;
491 break;
492
493 default:
494 return -EINVAL;
495 }
496
497 return 0;
498 }
499
500 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
501 unsigned blue, unsigned transp,
502 struct fb_info *info)
503 {
504 struct da8xx_fb_par *par = info->par;
505 unsigned short *palette = (unsigned short *) par->v_palette_base;
506 u_short pal;
507 int update_hw = 0;
508
509 if (regno > 255)
510 return 1;
511
512 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
513 return 1;
514
515 if (info->var.bits_per_pixel == 8) {
516 red >>= 4;
517 green >>= 8;
518 blue >>= 12;
519
520 pal = (red & 0x0f00);
521 pal |= (green & 0x00f0);
522 pal |= (blue & 0x000f);
523
524 if (palette[regno] != pal) {
525 update_hw = 1;
526 palette[regno] = pal;
527 }
528 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
529 red >>= (16 - info->var.red.length);
530 red <<= info->var.red.offset;
531
532 green >>= (16 - info->var.green.length);
533 green <<= info->var.green.offset;
534
535 blue >>= (16 - info->var.blue.length);
536 blue <<= info->var.blue.offset;
537
538 par->pseudo_palette[regno] = red | green | blue;
539
540 if (palette[0] != 0x4000) {
541 update_hw = 1;
542 palette[0] = 0x4000;
543 }
544 }
545
546 /* Update the palette in the h/w as needed. */
547 if (update_hw)
548 lcd_blit(LOAD_PALETTE, par);
549
550 return 0;
551 }
552
553 static void lcd_reset(struct da8xx_fb_par *par)
554 {
555 /* Disable the Raster if previously Enabled */
556 lcd_disable_raster();
557
558 /* DMA has to be disabled */
559 lcdc_write(0, LCD_DMA_CTRL_REG);
560 lcdc_write(0, LCD_RASTER_CTRL_REG);
561
562 if (lcd_revision == LCD_VERSION_2)
563 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
564 }
565
566 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
567 {
568 unsigned int lcd_clk, div;
569
570 lcd_clk = clk_get_rate(par->lcdc_clk);
571 div = lcd_clk / par->pxl_clk;
572
573 /* Configure the LCD clock divisor. */
574 lcdc_write(LCD_CLK_DIVISOR(div) |
575 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
576
577 if (lcd_revision == LCD_VERSION_2)
578 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
579 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
580
581 }
582
583 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
584 struct da8xx_panel *panel)
585 {
586 u32 bpp;
587 int ret = 0;
588
589 lcd_reset(par);
590
591 /* Calculate the divider */
592 lcd_calc_clk_divider(par);
593
594 if (panel->invert_pxl_clk)
595 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
596 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
597 else
598 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
599 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
600
601 /* Configure the DMA burst size. */
602 ret = lcd_cfg_dma(cfg->dma_burst_sz);
603 if (ret < 0)
604 return ret;
605
606 /* Configure the AC bias properties. */
607 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
608
609 /* Configure the vertical and horizontal sync properties. */
610 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
611 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
612
613 /* Configure for disply */
614 ret = lcd_cfg_display(cfg);
615 if (ret < 0)
616 return ret;
617
618 if (QVGA != cfg->p_disp_panel->panel_type)
619 return -EINVAL;
620
621 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
622 cfg->bpp >= cfg->p_disp_panel->min_bpp)
623 bpp = cfg->bpp;
624 else
625 bpp = cfg->p_disp_panel->max_bpp;
626 if (bpp == 12)
627 bpp = 16;
628 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
629 (unsigned int)panel->height, bpp,
630 cfg->raster_order);
631 if (ret < 0)
632 return ret;
633
634 /* Configure FDD */
635 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
636 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
637
638 return 0;
639 }
640
641 /* IRQ handler for version 2 of LCDC */
642 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
643 {
644 struct da8xx_fb_par *par = arg;
645 u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
646 u32 reg_int;
647
648 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
649 lcd_disable_raster();
650 lcdc_write(stat, LCD_MASKED_STAT_REG);
651 lcd_enable_raster();
652 } else if (stat & LCD_PL_LOAD_DONE) {
653 /*
654 * Must disable raster before changing state of any control bit.
655 * And also must be disabled before clearing the PL loading
656 * interrupt via the following write to the status register. If
657 * this is done after then one gets multiple PL done interrupts.
658 */
659 lcd_disable_raster();
660
661 lcdc_write(stat, LCD_MASKED_STAT_REG);
662
663 /* Disable PL completion inerrupt */
664 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
665 (LCD_V2_PL_INT_ENA);
666 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
667
668 /* Setup and start data loading mode */
669 lcd_blit(LOAD_DATA, par);
670 } else {
671 lcdc_write(stat, LCD_MASKED_STAT_REG);
672
673 if (stat & LCD_END_OF_FRAME0) {
674 lcdc_write(par->dma_start,
675 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
676 lcdc_write(par->dma_end,
677 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
678 par->vsync_flag = 1;
679 wake_up_interruptible(&par->vsync_wait);
680 }
681
682 if (stat & LCD_END_OF_FRAME1) {
683 lcdc_write(par->dma_start,
684 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
685 lcdc_write(par->dma_end,
686 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
687 par->vsync_flag = 1;
688 wake_up_interruptible(&par->vsync_wait);
689 }
690 }
691
692 lcdc_write(0, LCD_END_OF_INT_IND_REG);
693 return IRQ_HANDLED;
694 }
695
696 /* IRQ handler for version 1 LCDC */
697 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
698 {
699 struct da8xx_fb_par *par = arg;
700 u32 stat = lcdc_read(LCD_STAT_REG);
701 u32 reg_ras;
702
703 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
704 lcd_disable_raster();
705 lcdc_write(stat, LCD_STAT_REG);
706 lcd_enable_raster();
707 } else if (stat & LCD_PL_LOAD_DONE) {
708 /*
709 * Must disable raster before changing state of any control bit.
710 * And also must be disabled before clearing the PL loading
711 * interrupt via the following write to the status register. If
712 * this is done after then one gets multiple PL done interrupts.
713 */
714 lcd_disable_raster();
715
716 lcdc_write(stat, LCD_STAT_REG);
717
718 /* Disable PL completion inerrupt */
719 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
720 reg_ras &= ~LCD_V1_PL_INT_ENA;
721 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
722
723 /* Setup and start data loading mode */
724 lcd_blit(LOAD_DATA, par);
725 } else {
726 lcdc_write(stat, LCD_STAT_REG);
727
728 if (stat & LCD_END_OF_FRAME0) {
729 lcdc_write(par->dma_start,
730 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
731 lcdc_write(par->dma_end,
732 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
733 par->vsync_flag = 1;
734 wake_up_interruptible(&par->vsync_wait);
735 }
736
737 if (stat & LCD_END_OF_FRAME1) {
738 lcdc_write(par->dma_start,
739 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
740 lcdc_write(par->dma_end,
741 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
742 par->vsync_flag = 1;
743 wake_up_interruptible(&par->vsync_wait);
744 }
745 }
746
747 return IRQ_HANDLED;
748 }
749
750 static int fb_check_var(struct fb_var_screeninfo *var,
751 struct fb_info *info)
752 {
753 int err = 0;
754
755 switch (var->bits_per_pixel) {
756 case 1:
757 case 8:
758 var->red.offset = 0;
759 var->red.length = 8;
760 var->green.offset = 0;
761 var->green.length = 8;
762 var->blue.offset = 0;
763 var->blue.length = 8;
764 var->transp.offset = 0;
765 var->transp.length = 0;
766 break;
767 case 4:
768 var->red.offset = 0;
769 var->red.length = 4;
770 var->green.offset = 0;
771 var->green.length = 4;
772 var->blue.offset = 0;
773 var->blue.length = 4;
774 var->transp.offset = 0;
775 var->transp.length = 0;
776 break;
777 case 16: /* RGB 565 */
778 var->red.offset = 11;
779 var->red.length = 5;
780 var->green.offset = 5;
781 var->green.length = 6;
782 var->blue.offset = 0;
783 var->blue.length = 5;
784 var->transp.offset = 0;
785 var->transp.length = 0;
786 break;
787 default:
788 err = -EINVAL;
789 }
790
791 var->red.msb_right = 0;
792 var->green.msb_right = 0;
793 var->blue.msb_right = 0;
794 var->transp.msb_right = 0;
795 return err;
796 }
797
798 #ifdef CONFIG_CPU_FREQ
799 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
800 unsigned long val, void *data)
801 {
802 struct da8xx_fb_par *par;
803
804 par = container_of(nb, struct da8xx_fb_par, freq_transition);
805 if (val == CPUFREQ_PRECHANGE) {
806 lcd_disable_raster();
807 } else if (val == CPUFREQ_POSTCHANGE) {
808 lcd_calc_clk_divider(par);
809 lcd_enable_raster();
810 }
811
812 return 0;
813 }
814
815 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
816 {
817 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
818
819 return cpufreq_register_notifier(&par->freq_transition,
820 CPUFREQ_TRANSITION_NOTIFIER);
821 }
822
823 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
824 {
825 cpufreq_unregister_notifier(&par->freq_transition,
826 CPUFREQ_TRANSITION_NOTIFIER);
827 }
828 #endif
829
830 static int __devexit fb_remove(struct platform_device *dev)
831 {
832 struct fb_info *info = dev_get_drvdata(&dev->dev);
833
834 if (info) {
835 struct da8xx_fb_par *par = info->par;
836
837 #ifdef CONFIG_CPU_FREQ
838 lcd_da8xx_cpufreq_deregister(par);
839 #endif
840 if (par->panel_power_ctrl)
841 par->panel_power_ctrl(0);
842
843 lcd_disable_raster();
844 lcdc_write(0, LCD_RASTER_CTRL_REG);
845
846 /* disable DMA */
847 lcdc_write(0, LCD_DMA_CTRL_REG);
848
849 unregister_framebuffer(info);
850 fb_dealloc_cmap(&info->cmap);
851 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
852 par->p_palette_base);
853 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
854 par->vram_phys);
855 free_irq(par->irq, par);
856 clk_disable(par->lcdc_clk);
857 clk_put(par->lcdc_clk);
858 framebuffer_release(info);
859 iounmap((void __iomem *)da8xx_fb_reg_base);
860 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
861
862 }
863 return 0;
864 }
865
866 /*
867 * Function to wait for vertical sync which for this LCD peripheral
868 * translates into waiting for the current raster frame to complete.
869 */
870 static int fb_wait_for_vsync(struct fb_info *info)
871 {
872 struct da8xx_fb_par *par = info->par;
873 int ret;
874
875 /*
876 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
877 * race condition here where the ISR could have occurred just before or
878 * just after this set. But since we are just coarsely waiting for
879 * a frame to complete then that's OK. i.e. if the frame completed
880 * just before this code executed then we have to wait another full
881 * frame time but there is no way to avoid such a situation. On the
882 * other hand if the frame completed just after then we don't need
883 * to wait long at all. Either way we are guaranteed to return to the
884 * user immediately after a frame completion which is all that is
885 * required.
886 */
887 par->vsync_flag = 0;
888 ret = wait_event_interruptible_timeout(par->vsync_wait,
889 par->vsync_flag != 0,
890 par->vsync_timeout);
891 if (ret < 0)
892 return ret;
893 if (ret == 0)
894 return -ETIMEDOUT;
895
896 return 0;
897 }
898
899 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
900 unsigned long arg)
901 {
902 struct lcd_sync_arg sync_arg;
903
904 switch (cmd) {
905 case FBIOGET_CONTRAST:
906 case FBIOPUT_CONTRAST:
907 case FBIGET_BRIGHTNESS:
908 case FBIPUT_BRIGHTNESS:
909 case FBIGET_COLOR:
910 case FBIPUT_COLOR:
911 return -ENOTTY;
912 case FBIPUT_HSYNC:
913 if (copy_from_user(&sync_arg, (char *)arg,
914 sizeof(struct lcd_sync_arg)))
915 return -EFAULT;
916 lcd_cfg_horizontal_sync(sync_arg.back_porch,
917 sync_arg.pulse_width,
918 sync_arg.front_porch);
919 break;
920 case FBIPUT_VSYNC:
921 if (copy_from_user(&sync_arg, (char *)arg,
922 sizeof(struct lcd_sync_arg)))
923 return -EFAULT;
924 lcd_cfg_vertical_sync(sync_arg.back_porch,
925 sync_arg.pulse_width,
926 sync_arg.front_porch);
927 break;
928 case FBIO_WAITFORVSYNC:
929 return fb_wait_for_vsync(info);
930 default:
931 return -EINVAL;
932 }
933 return 0;
934 }
935
936 static int cfb_blank(int blank, struct fb_info *info)
937 {
938 struct da8xx_fb_par *par = info->par;
939 int ret = 0;
940
941 if (par->blank == blank)
942 return 0;
943
944 par->blank = blank;
945 switch (blank) {
946 case FB_BLANK_UNBLANK:
947 if (par->panel_power_ctrl)
948 par->panel_power_ctrl(1);
949
950 lcd_enable_raster();
951 break;
952 case FB_BLANK_POWERDOWN:
953 if (par->panel_power_ctrl)
954 par->panel_power_ctrl(0);
955
956 lcd_disable_raster();
957 break;
958 default:
959 ret = -EINVAL;
960 }
961
962 return ret;
963 }
964
965 /*
966 * Set new x,y offsets in the virtual display for the visible area and switch
967 * to the new mode.
968 */
969 static int da8xx_pan_display(struct fb_var_screeninfo *var,
970 struct fb_info *fbi)
971 {
972 int ret = 0;
973 struct fb_var_screeninfo new_var;
974 struct da8xx_fb_par *par = fbi->par;
975 struct fb_fix_screeninfo *fix = &fbi->fix;
976 unsigned int end;
977 unsigned int start;
978
979 if (var->xoffset != fbi->var.xoffset ||
980 var->yoffset != fbi->var.yoffset) {
981 memcpy(&new_var, &fbi->var, sizeof(new_var));
982 new_var.xoffset = var->xoffset;
983 new_var.yoffset = var->yoffset;
984 if (fb_check_var(&new_var, fbi))
985 ret = -EINVAL;
986 else {
987 memcpy(&fbi->var, &new_var, sizeof(new_var));
988
989 start = fix->smem_start +
990 new_var.yoffset * fix->line_length +
991 new_var.xoffset * fbi->var.bits_per_pixel / 8;
992 end = start + fbi->var.yres * fix->line_length - 1;
993 par->dma_start = start;
994 par->dma_end = end;
995 }
996 }
997
998 return ret;
999 }
1000
1001 static struct fb_ops da8xx_fb_ops = {
1002 .owner = THIS_MODULE,
1003 .fb_check_var = fb_check_var,
1004 .fb_setcolreg = fb_setcolreg,
1005 .fb_pan_display = da8xx_pan_display,
1006 .fb_ioctl = fb_ioctl,
1007 .fb_fillrect = cfb_fillrect,
1008 .fb_copyarea = cfb_copyarea,
1009 .fb_imageblit = cfb_imageblit,
1010 .fb_blank = cfb_blank,
1011 };
1012
1013 static int __devinit fb_probe(struct platform_device *device)
1014 {
1015 struct da8xx_lcdc_platform_data *fb_pdata =
1016 device->dev.platform_data;
1017 struct lcd_ctrl_config *lcd_cfg;
1018 struct da8xx_panel *lcdc_info;
1019 struct fb_info *da8xx_fb_info;
1020 struct clk *fb_clk = NULL;
1021 struct da8xx_fb_par *par;
1022 resource_size_t len;
1023 int ret, i;
1024
1025 if (fb_pdata == NULL) {
1026 dev_err(&device->dev, "Can not get platform data\n");
1027 return -ENOENT;
1028 }
1029
1030 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1031 if (!lcdc_regs) {
1032 dev_err(&device->dev,
1033 "Can not get memory resource for LCD controller\n");
1034 return -ENOENT;
1035 }
1036
1037 len = resource_size(lcdc_regs);
1038
1039 lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1040 if (!lcdc_regs)
1041 return -EBUSY;
1042
1043 da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1044 if (!da8xx_fb_reg_base) {
1045 ret = -EBUSY;
1046 goto err_request_mem;
1047 }
1048
1049 fb_clk = clk_get(&device->dev, NULL);
1050 if (IS_ERR(fb_clk)) {
1051 dev_err(&device->dev, "Can not get device clock\n");
1052 ret = -ENODEV;
1053 goto err_ioremap;
1054 }
1055 ret = clk_enable(fb_clk);
1056 if (ret)
1057 goto err_clk_put;
1058
1059 /* Determine LCD IP Version */
1060 switch (lcdc_read(LCD_PID_REG)) {
1061 case 0x4C100102:
1062 lcd_revision = LCD_VERSION_1;
1063 break;
1064 case 0x4F200800:
1065 lcd_revision = LCD_VERSION_2;
1066 break;
1067 default:
1068 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1069 "defaulting to LCD revision 1\n",
1070 lcdc_read(LCD_PID_REG));
1071 lcd_revision = LCD_VERSION_1;
1072 break;
1073 }
1074
1075 for (i = 0, lcdc_info = known_lcd_panels;
1076 i < ARRAY_SIZE(known_lcd_panels);
1077 i++, lcdc_info++) {
1078 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1079 break;
1080 }
1081
1082 if (i == ARRAY_SIZE(known_lcd_panels)) {
1083 dev_err(&device->dev, "GLCD: No valid panel found\n");
1084 ret = -ENODEV;
1085 goto err_clk_disable;
1086 } else
1087 dev_info(&device->dev, "GLCD: Found %s panel\n",
1088 fb_pdata->type);
1089
1090 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1091
1092 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1093 &device->dev);
1094 if (!da8xx_fb_info) {
1095 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1096 ret = -ENOMEM;
1097 goto err_clk_disable;
1098 }
1099
1100 par = da8xx_fb_info->par;
1101 par->lcdc_clk = fb_clk;
1102 par->pxl_clk = lcdc_info->pxl_clk;
1103 if (fb_pdata->panel_power_ctrl) {
1104 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1105 par->panel_power_ctrl(1);
1106 }
1107
1108 if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1109 dev_err(&device->dev, "lcd_init failed\n");
1110 ret = -EFAULT;
1111 goto err_release_fb;
1112 }
1113
1114 /* allocate frame buffer */
1115 par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1116 par->vram_size = PAGE_ALIGN(par->vram_size/8);
1117 par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1118
1119 par->vram_virt = dma_alloc_coherent(NULL,
1120 par->vram_size,
1121 (resource_size_t *) &par->vram_phys,
1122 GFP_KERNEL | GFP_DMA);
1123 if (!par->vram_virt) {
1124 dev_err(&device->dev,
1125 "GLCD: kmalloc for frame buffer failed\n");
1126 ret = -EINVAL;
1127 goto err_release_fb;
1128 }
1129
1130 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1131 da8xx_fb_fix.smem_start = par->vram_phys;
1132 da8xx_fb_fix.smem_len = par->vram_size;
1133 da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
1134
1135 par->dma_start = par->vram_phys;
1136 par->dma_end = par->dma_start + lcdc_info->height *
1137 da8xx_fb_fix.line_length - 1;
1138
1139 /* allocate palette buffer */
1140 par->v_palette_base = dma_alloc_coherent(NULL,
1141 PALETTE_SIZE,
1142 (resource_size_t *)
1143 &par->p_palette_base,
1144 GFP_KERNEL | GFP_DMA);
1145 if (!par->v_palette_base) {
1146 dev_err(&device->dev,
1147 "GLCD: kmalloc for palette buffer failed\n");
1148 ret = -EINVAL;
1149 goto err_release_fb_mem;
1150 }
1151 memset(par->v_palette_base, 0, PALETTE_SIZE);
1152
1153 par->irq = platform_get_irq(device, 0);
1154 if (par->irq < 0) {
1155 ret = -ENOENT;
1156 goto err_release_pl_mem;
1157 }
1158
1159 /* Initialize par */
1160 da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1161
1162 da8xx_fb_var.xres = lcdc_info->width;
1163 da8xx_fb_var.xres_virtual = lcdc_info->width;
1164
1165 da8xx_fb_var.yres = lcdc_info->height;
1166 da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1167
1168 da8xx_fb_var.grayscale =
1169 lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1170 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1171
1172 da8xx_fb_var.hsync_len = lcdc_info->hsw;
1173 da8xx_fb_var.vsync_len = lcdc_info->vsw;
1174
1175 /* Initialize fbinfo */
1176 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1177 da8xx_fb_info->fix = da8xx_fb_fix;
1178 da8xx_fb_info->var = da8xx_fb_var;
1179 da8xx_fb_info->fbops = &da8xx_fb_ops;
1180 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1181 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1182 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1183
1184 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1185 if (ret)
1186 goto err_release_pl_mem;
1187 da8xx_fb_info->cmap.len = par->palette_sz;
1188
1189 /* initialize var_screeninfo */
1190 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1191 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1192
1193 dev_set_drvdata(&device->dev, da8xx_fb_info);
1194
1195 /* initialize the vsync wait queue */
1196 init_waitqueue_head(&par->vsync_wait);
1197 par->vsync_timeout = HZ / 5;
1198
1199 /* Register the Frame Buffer */
1200 if (register_framebuffer(da8xx_fb_info) < 0) {
1201 dev_err(&device->dev,
1202 "GLCD: Frame Buffer Registration Failed!\n");
1203 ret = -EINVAL;
1204 goto err_dealloc_cmap;
1205 }
1206
1207 #ifdef CONFIG_CPU_FREQ
1208 ret = lcd_da8xx_cpufreq_register(par);
1209 if (ret) {
1210 dev_err(&device->dev, "failed to register cpufreq\n");
1211 goto err_cpu_freq;
1212 }
1213 #endif
1214
1215 if (lcd_revision == LCD_VERSION_1)
1216 lcdc_irq_handler = lcdc_irq_handler_rev01;
1217 else
1218 lcdc_irq_handler = lcdc_irq_handler_rev02;
1219
1220 ret = request_irq(par->irq, lcdc_irq_handler, 0,
1221 DRIVER_NAME, par);
1222 if (ret)
1223 goto irq_freq;
1224 return 0;
1225
1226 irq_freq:
1227 #ifdef CONFIG_CPU_FREQ
1228 lcd_da8xx_cpufreq_deregister(par);
1229 #endif
1230 err_cpu_freq:
1231 unregister_framebuffer(da8xx_fb_info);
1232
1233 err_dealloc_cmap:
1234 fb_dealloc_cmap(&da8xx_fb_info->cmap);
1235
1236 err_release_pl_mem:
1237 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1238 par->p_palette_base);
1239
1240 err_release_fb_mem:
1241 dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1242
1243 err_release_fb:
1244 framebuffer_release(da8xx_fb_info);
1245
1246 err_clk_disable:
1247 clk_disable(fb_clk);
1248
1249 err_clk_put:
1250 clk_put(fb_clk);
1251
1252 err_ioremap:
1253 iounmap((void __iomem *)da8xx_fb_reg_base);
1254
1255 err_request_mem:
1256 release_mem_region(lcdc_regs->start, len);
1257
1258 return ret;
1259 }
1260
1261 #ifdef CONFIG_PM
1262 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1263 {
1264 struct fb_info *info = platform_get_drvdata(dev);
1265 struct da8xx_fb_par *par = info->par;
1266
1267 console_lock();
1268 if (par->panel_power_ctrl)
1269 par->panel_power_ctrl(0);
1270
1271 fb_set_suspend(info, 1);
1272 lcd_disable_raster();
1273 clk_disable(par->lcdc_clk);
1274 console_unlock();
1275
1276 return 0;
1277 }
1278 static int fb_resume(struct platform_device *dev)
1279 {
1280 struct fb_info *info = platform_get_drvdata(dev);
1281 struct da8xx_fb_par *par = info->par;
1282
1283 console_lock();
1284 if (par->panel_power_ctrl)
1285 par->panel_power_ctrl(1);
1286
1287 clk_enable(par->lcdc_clk);
1288 lcd_enable_raster();
1289 fb_set_suspend(info, 0);
1290 console_unlock();
1291
1292 return 0;
1293 }
1294 #else
1295 #define fb_suspend NULL
1296 #define fb_resume NULL
1297 #endif
1298
1299 static struct platform_driver da8xx_fb_driver = {
1300 .probe = fb_probe,
1301 .remove = __devexit_p(fb_remove),
1302 .suspend = fb_suspend,
1303 .resume = fb_resume,
1304 .driver = {
1305 .name = DRIVER_NAME,
1306 .owner = THIS_MODULE,
1307 },
1308 };
1309
1310 static int __init da8xx_fb_init(void)
1311 {
1312 return platform_driver_register(&da8xx_fb_driver);
1313 }
1314
1315 static void __exit da8xx_fb_cleanup(void)
1316 {
1317 platform_driver_unregister(&da8xx_fb_driver);
1318 }
1319
1320 module_init(da8xx_fb_init);
1321 module_exit(da8xx_fb_cleanup);
1322
1323 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1324 MODULE_AUTHOR("Texas Instruments");
1325 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.057065 seconds and 6 git commands to generate.