drivers/video/dnfb.c

   1 #include <linux/kernel.h>
   2 #include <linux/errno.h>
   3 #include <linux/string.h>
   4 #include <linux/mm.h>
   5 #include <linux/tty.h>
   6 #include <linux/slab.h>
   7 #include <linux/delay.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/platform_device.h>
  10
  11 #include <asm/setup.h>
  12 #include <asm/system.h>
  13 #include <asm/irq.h>
  14 #include <asm/amigahw.h>
  15 #include <asm/amigaints.h>
  16 #include <asm/apollohw.h>
  17 #include <linux/fb.h>
  18 #include <linux/module.h>
  19
  20 /* apollo video HW definitions */
  21
  22 /*
  23  * Control Registers.   IOBASE + $x
  24  *
  25  * Note: these are the Memory/IO BASE definitions for a mono card set to the
  26  * alternate address
  27  *
  28  * Control 3A and 3B serve identical functions except that 3A
  29  * deals with control 1 and 3b deals with Color LUT reg.
  30  */
  31
  32 #define AP_IOBASE       0x3b0   /* Base address of 1 plane board. */
  33 #define AP_STATUS       isaIO2mem(AP_IOBASE+0)  /* Status register.  Read */
  34 #define AP_WRITE_ENABLE isaIO2mem(AP_IOBASE+0)  /* Write Enable Register Write */
  35 #define AP_DEVICE_ID    isaIO2mem(AP_IOBASE+1)  /* Device ID Register. Read */
  36 #define AP_ROP_1        isaIO2mem(AP_IOBASE+2)  /* Raster Operation reg. Write Word */
  37 #define AP_DIAG_MEM_REQ isaIO2mem(AP_IOBASE+4)  /* Diagnostic Memory Request. Write Word */
  38 #define AP_CONTROL_0    isaIO2mem(AP_IOBASE+8)  /* Control Register 0.  Read/Write */
  39 #define AP_CONTROL_1    isaIO2mem(AP_IOBASE+0xa)        /* Control Register 1.  Read/Write */
  40 #define AP_CONTROL_3A   isaIO2mem(AP_IOBASE+0xe)        /* Control Register 3a. Read/Write */
  41 #define AP_CONTROL_2    isaIO2mem(AP_IOBASE+0xc)        /* Control Register 2. Read/Write */
  42
  43
  44 #define FRAME_BUFFER_START 0x0FA0000
  45 #define FRAME_BUFFER_LEN 0x40000
  46
  47 /* CREG 0 */
  48 #define VECTOR_MODE 0x40        /* 010x.xxxx */
  49 #define DBLT_MODE   0x80        /* 100x.xxxx */
  50 #define NORMAL_MODE 0xE0        /* 111x.xxxx */
  51 #define SHIFT_BITS  0x1F        /* xxx1.1111 */
  52         /* other bits are Shift value */
  53
  54 /* CREG 1 */
  55 #define AD_BLT      0x80        /* 1xxx.xxxx */
  56 #define NORMAL      0x80 /* 1xxx.xxxx */        /* What is happening here ?? */
  57 #define INVERSE     0x00 /* 0xxx.xxxx */        /* Clearing this reverses the screen */
  58 #define PIX_BLT     0x00        /* 0xxx.xxxx */
  59
  60 #define AD_HIBIT        0x40    /* xIxx.xxxx */
  61
  62 #define ROP_EN          0x10    /* xxx1.xxxx */
  63 #define DST_EQ_SRC      0x00    /* xxx0.xxxx */
  64 #define nRESET_SYNC     0x08    /* xxxx.1xxx */
  65 #define SYNC_ENAB       0x02    /* xxxx.xx1x */
  66
  67 #define BLANK_DISP      0x00    /* xxxx.xxx0 */
  68 #define ENAB_DISP       0x01    /* xxxx.xxx1 */
  69
  70 #define NORM_CREG1      (nRESET_SYNC | SYNC_ENAB | ENAB_DISP)   /* no reset sync */
  71
  72 /* CREG 2 */
  73
  74 /*
  75  * Following 3 defines are common to 1, 4 and 8 plane.
  76  */
  77
  78 #define S_DATA_1s   0x00 /* 00xx.xxxx */        /* set source to all 1's -- vector drawing */
  79 #define S_DATA_PIX  0x40 /* 01xx.xxxx */        /* takes source from ls-bits and replicates over 16 bits */
  80 #define S_DATA_PLN  0xC0 /* 11xx.xxxx */        /* normal, each data access =16-bits in
  81                                                    one plane of image mem */
  82
  83 /* CREG 3A/CREG 3B */
  84 #       define RESET_CREG 0x80  /* 1000.0000 */
  85
  86 /* ROP REG  -  all one nibble */
  87 /*      ********* NOTE : this is used r0,r1,r2,r3 *********** */
  88 #define ROP(r2,r3,r0,r1) ( (U_SHORT)((r0)|((r1)<<4)|((r2)<<8)|((r3)<<12)) )
  89 #define DEST_ZERO               0x0
  90 #define SRC_AND_DEST    0x1
  91 #define SRC_AND_nDEST   0x2
  92 #define SRC                             0x3
  93 #define nSRC_AND_DEST   0x4
  94 #define DEST                    0x5
  95 #define SRC_XOR_DEST    0x6
  96 #define SRC_OR_DEST             0x7
  97 #define SRC_NOR_DEST    0x8
  98 #define SRC_XNOR_DEST   0x9
  99 #define nDEST                   0xA
 100 #define SRC_OR_nDEST    0xB
 101 #define nSRC                    0xC
 102 #define nSRC_OR_DEST    0xD
 103 #define SRC_NAND_DEST   0xE
 104 #define DEST_ONE                0xF
 105
 106 #define SWAP(A) ((A>>8) | ((A&0xff) <<8))
 107
 108 /* frame buffer operations */
 109
 110 static int dnfb_blank(int blank, struct fb_info *info);
 111 static void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 112
 113 static struct fb_ops dn_fb_ops = {
 114         .owner          = THIS_MODULE,
 115         .fb_blank       = dnfb_blank,
 116         .fb_fillrect    = cfb_fillrect,
 117         .fb_copyarea    = dnfb_copyarea,
 118         .fb_imageblit   = cfb_imageblit,
 119         .fb_cursor      = soft_cursor,
 120 };
 121
 122 struct fb_var_screeninfo dnfb_var __devinitdata = {
 123         .xres           = 1280,
 124         .yres           = 1024,
 125         .xres_virtual   = 2048,
 126         .yres_virtual   = 1024,
 127         .bits_per_pixel = 1,
 128         .height         = -1,
 129         .width          = -1,
 130         .vmode          = FB_VMODE_NONINTERLACED,
 131 };
 132
 133 static struct fb_fix_screeninfo dnfb_fix __devinitdata = {
 134         .id             = "Apollo Mono",
 135         .smem_start     = (FRAME_BUFFER_START + IO_BASE),
 136         .smem_len       = FRAME_BUFFER_LEN,
 137         .type           = FB_TYPE_PACKED_PIXELS,
 138         .visual         = FB_VISUAL_MONO10,
 139         .line_length    = 256,
 140 };
 141
 142 static int dnfb_blank(int blank, struct fb_info *info)
 143 {
 144         if (blank)
 145                 out_8(AP_CONTROL_3A, 0x0);
 146         else
 147                 out_8(AP_CONTROL_3A, 0x1);
 148         return 0;
 149 }
 150
 151 static
 152 void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
 153 {
 154
 155         int incr, y_delta, pre_read = 0, x_end, x_word_count;
 156         uint start_mask, end_mask, dest;
 157         ushort *src, dummy;
 158         short i, j;
 159
 160         incr = (area->dy <= area->sy) ? 1 : -1;
 161
 162         src = (ushort *)(info->screen_base + area->sy * info->fix.line_length +
 163                         (area->sx >> 4));
 164         dest = area->dy * (info->fix.line_length >> 1) + (area->dx >> 4);
 165
 166         if (incr > 0) {
 167                 y_delta = (info->fix.line_length * 8) - area->sx - area->width;
 168                 x_end = area->dx + area->width - 1;
 169                 x_word_count = (x_end >> 4) - (area->dx >> 4) + 1;
 170                 start_mask = 0xffff0000 >> (area->dx & 0xf);
 171                 end_mask = 0x7ffff >> (x_end & 0xf);
 172                 out_8(AP_CONTROL_0,
 173                      (((area->dx & 0xf) - (area->sx & 0xf)) % 16) | (0x4 << 5));
 174                 if ((area->dx & 0xf) < (area->sx & 0xf))
 175                         pre_read = 1;
 176         } else {
 177                 y_delta = -((info->fix.line_length * 8) - area->sx - area->width);
 178                 x_end = area->dx - area->width + 1;
 179                 x_word_count = (area->dx >> 4) - (x_end >> 4) + 1;
 180                 start_mask = 0x7ffff >> (area->dx & 0xf);
 181                 end_mask = 0xffff0000 >> (x_end & 0xf);
 182                 out_8(AP_CONTROL_0,
 183                      ((-((area->sx & 0xf) - (area->dx & 0xf))) % 16) |
 184                      (0x4 << 5));
 185                 if ((area->dx & 0xf) > (area->sx & 0xf))
 186                         pre_read = 1;
 187         }
 188
 189         for (i = 0; i < area->height; i++) {
 190
 191                 out_8(AP_CONTROL_3A, 0xc | (dest >> 16));
 192
 193                 if (pre_read) {
 194                         dummy = *src;
 195                         src += incr;
 196                 }
 197
 198                 if (x_word_count) {
 199                         out_8(AP_WRITE_ENABLE, start_mask);
 200                         *src = dest;
 201                         src += incr;
 202                         dest += incr;
 203                         out_8(AP_WRITE_ENABLE, 0);
 204
 205                         for (j = 1; j < (x_word_count - 1); j++) {
 206                                 *src = dest;
 207                                 src += incr;
 208                                 dest += incr;
 209                         }
 210
 211                         out_8(AP_WRITE_ENABLE, start_mask);
 212                         *src = dest;
 213                         dest += incr;
 214                         src += incr;
 215                 } else {
 216                         out_8(AP_WRITE_ENABLE, start_mask | end_mask);
 217                         *src = dest;
 218                         dest += incr;
 219                         src += incr;
 220                 }
 221                 src += (y_delta / 16);
 222                 dest += (y_delta / 16);
 223         }
 224         out_8(AP_CONTROL_0, NORMAL_MODE);
 225 }
 226
 227 /*
 228  * Initialization
 229  */
 230
 231 static int __devinit dnfb_probe(struct device *device)
 232 {
 233         struct platform_device *dev = to_platform_device(device);
 234         struct fb_info *info;
 235         int err = 0;
 236
 237         info = framebuffer_alloc(0, &dev->dev);
 238         if (!info)
 239                 return -ENOMEM;
 240
 241         info->fbops = &dn_fb_ops;
 242         info->fix = dnfb_fix;
 243         info->var = dnfb_var;
 244         info->var.red.length = 1;
 245         info->var.red.offset = 0;
 246         info->var.green = info->var.blue = info->var.red;
 247         info->screen_base = (u_char *) info->fix.smem_start;
 248
 249         err = fb_alloc_cmap(&info->cmap, 2, 0);
 250         if (err < 0) {
 251                 framebuffer_release(info);
 252                 return err;
 253         }
 254
 255         err = register_framebuffer(info);
 256         if (err < 0) {
 257                 fb_dealloc_cmap(&info->cmap);
 258                 framebuffer_release(info);
 259                 return err;
 260         }
 261         dev_set_drvdata(&dev->dev, info);
 262
 263         /* now we have registered we can safely setup the hardware */
 264         out_8(AP_CONTROL_3A, RESET_CREG);
 265         out_be16(AP_WRITE_ENABLE, 0x0);
 266         out_8(AP_CONTROL_0, NORMAL_MODE);
 267         out_8(AP_CONTROL_1, (AD_BLT | DST_EQ_SRC | NORM_CREG1));
 268         out_8(AP_CONTROL_2, S_DATA_PLN);
 269         out_be16(AP_ROP_1, SWAP(0x3));
 270
 271         printk("apollo frame buffer alive and kicking !\n");
 272         return err;
 273 }
 274
 275 static struct device_driver dnfb_driver = {
 276         .name   = "dnfb",
 277         .bus    = &platform_bus_type,
 278         .probe  = dnfb_probe,
 279 };
 280
 281 static struct platform_device dnfb_device = {
 282         .name   = "dnfb",
 283 };
 284
 285 int __init dnfb_init(void)
 286 {
 287         int ret;
 288
 289         if (fb_get_options("dnfb", NULL))
 290                 return -ENODEV;
 291
 292         ret = driver_register(&dnfb_driver);
 293
 294         if (!ret) {
 295                 ret = platform_device_register(&dnfb_device);
 296                 if (ret)
 297                         driver_unregister(&dnfb_driver);
 298         }
 299         return ret;
 300 }
 301
 302 module_init(dnfb_init);
 303
 304 MODULE_LICENSE("GPL");