2 * linux/drivers/video/acornfb.h
4 * Copyright (C) 1998,1999 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Frame buffer code for Acorn platforms
12 #if defined(HAS_VIDC20)
13 #include <asm/hardware/iomd.h>
14 #define VIDC_PALETTE_SIZE 256
15 #define VIDC_NAME "VIDC20"
18 #define EXTEND8(x) ((x)|(x)<<8)
19 #define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12)
21 struct vidc20_palette
{
40 struct vidc20_palette vidc20
;
41 struct vidc_palette vidc
;
47 unsigned long screen_end
;
48 unsigned int dram_size
;
49 unsigned int vram_half_sam
;
50 unsigned int palette_size
;
52 unsigned int using_vram
: 1;
53 unsigned int dpms
: 1;
55 union palette palette
[VIDC_PALETTE_SIZE
];
57 u32 pseudo_palette
[16];
64 u_int h_display_start
;
72 u_int v_display_start
;
97 const struct modey_params
*modey
;
104 #define VIDC20_CTRL 0xe0000000
105 #define VIDC20_CTRL_PIX_VCLK (0 << 0)
106 #define VIDC20_CTRL_PIX_HCLK (1 << 0)
107 #define VIDC20_CTRL_PIX_RCLK (2 << 0)
108 #define VIDC20_CTRL_PIX_CK (0 << 2)
109 #define VIDC20_CTRL_PIX_CK2 (1 << 2)
110 #define VIDC20_CTRL_PIX_CK3 (2 << 2)
111 #define VIDC20_CTRL_PIX_CK4 (3 << 2)
112 #define VIDC20_CTRL_PIX_CK5 (4 << 2)
113 #define VIDC20_CTRL_PIX_CK6 (5 << 2)
114 #define VIDC20_CTRL_PIX_CK7 (6 << 2)
115 #define VIDC20_CTRL_PIX_CK8 (7 << 2)
116 #define VIDC20_CTRL_1BPP (0 << 5)
117 #define VIDC20_CTRL_2BPP (1 << 5)
118 #define VIDC20_CTRL_4BPP (2 << 5)
119 #define VIDC20_CTRL_8BPP (3 << 5)
120 #define VIDC20_CTRL_16BPP (4 << 5)
121 #define VIDC20_CTRL_32BPP (6 << 5)
122 #define VIDC20_CTRL_FIFO_NS (0 << 8)
123 #define VIDC20_CTRL_FIFO_4 (1 << 8)
124 #define VIDC20_CTRL_FIFO_8 (2 << 8)
125 #define VIDC20_CTRL_FIFO_12 (3 << 8)
126 #define VIDC20_CTRL_FIFO_16 (4 << 8)
127 #define VIDC20_CTRL_FIFO_20 (5 << 8)
128 #define VIDC20_CTRL_FIFO_24 (6 << 8)
129 #define VIDC20_CTRL_FIFO_28 (7 << 8)
130 #define VIDC20_CTRL_INT (1 << 12)
131 #define VIDC20_CTRL_DUP (1 << 13)
132 #define VIDC20_CTRL_PDOWN (1 << 14)
134 #define VIDC20_ECTL 0xc0000000
135 #define VIDC20_ECTL_REG(x) ((x) & 0xf3)
136 #define VIDC20_ECTL_ECK (1 << 2)
137 #define VIDC20_ECTL_REDPED (1 << 8)
138 #define VIDC20_ECTL_GREENPED (1 << 9)
139 #define VIDC20_ECTL_BLUEPED (1 << 10)
140 #define VIDC20_ECTL_DAC (1 << 12)
141 #define VIDC20_ECTL_LCDGS (1 << 13)
142 #define VIDC20_ECTL_HRM (1 << 14)
144 #define VIDC20_ECTL_HS_MASK (3 << 16)
145 #define VIDC20_ECTL_HS_HSYNC (0 << 16)
146 #define VIDC20_ECTL_HS_NHSYNC (1 << 16)
147 #define VIDC20_ECTL_HS_CSYNC (2 << 16)
148 #define VIDC20_ECTL_HS_NCSYNC (3 << 16)
150 #define VIDC20_ECTL_VS_MASK (3 << 18)
151 #define VIDC20_ECTL_VS_VSYNC (0 << 18)
152 #define VIDC20_ECTL_VS_NVSYNC (1 << 18)
153 #define VIDC20_ECTL_VS_CSYNC (2 << 18)
154 #define VIDC20_ECTL_VS_NCSYNC (3 << 18)
156 #define VIDC20_DCTL 0xf0000000
157 /* 0-9 = number of words in scanline */
158 #define VIDC20_DCTL_SNA (1 << 12)
159 #define VIDC20_DCTL_HDIS (1 << 13)
160 #define VIDC20_DCTL_BUS_NS (0 << 16)
161 #define VIDC20_DCTL_BUS_D31_0 (1 << 16)
162 #define VIDC20_DCTL_BUS_D63_32 (2 << 16)
163 #define VIDC20_DCTL_BUS_D63_0 (3 << 16)
164 #define VIDC20_DCTL_VRAM_DIS (0 << 18)
165 #define VIDC20_DCTL_VRAM_PXCLK (1 << 18)
166 #define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18)
167 #define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18)
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