2 * HDMI driver definition for TI OMAP4 Processor.
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/hdmi.h>
26 #include <video/omapdss.h>
32 #define HDMI_WP_REVISION 0x0
33 #define HDMI_WP_SYSCONFIG 0x10
34 #define HDMI_WP_IRQSTATUS_RAW 0x24
35 #define HDMI_WP_IRQSTATUS 0x28
36 #define HDMI_WP_IRQENABLE_SET 0x2C
37 #define HDMI_WP_IRQENABLE_CLR 0x30
38 #define HDMI_WP_IRQWAKEEN 0x34
39 #define HDMI_WP_PWR_CTRL 0x40
40 #define HDMI_WP_DEBOUNCE 0x44
41 #define HDMI_WP_VIDEO_CFG 0x50
42 #define HDMI_WP_VIDEO_SIZE 0x60
43 #define HDMI_WP_VIDEO_TIMING_H 0x68
44 #define HDMI_WP_VIDEO_TIMING_V 0x6C
45 #define HDMI_WP_CLK 0x70
46 #define HDMI_WP_AUDIO_CFG 0x80
47 #define HDMI_WP_AUDIO_CFG2 0x84
48 #define HDMI_WP_AUDIO_CTRL 0x88
49 #define HDMI_WP_AUDIO_DATA 0x8C
51 /* HDMI WP IRQ flags */
52 #define HDMI_IRQ_CORE (1 << 0)
53 #define HDMI_IRQ_OCP_TIMEOUT (1 << 4)
54 #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)
55 #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)
56 #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)
57 #define HDMI_IRQ_VIDEO_VSYNC (1 << 16)
58 #define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)
59 #define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)
60 #define HDMI_IRQ_LINK_CONNECT (1 << 25)
61 #define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
62 #define HDMI_IRQ_PLL_LOCK (1 << 29)
63 #define HDMI_IRQ_PLL_UNLOCK (1 << 30)
64 #define HDMI_IRQ_PLL_RECAL (1 << 31)
68 #define PLLCTRL_PLL_CONTROL 0x0
69 #define PLLCTRL_PLL_STATUS 0x4
70 #define PLLCTRL_PLL_GO 0x8
71 #define PLLCTRL_CFG1 0xC
72 #define PLLCTRL_CFG2 0x10
73 #define PLLCTRL_CFG3 0x14
74 #define PLLCTRL_SSC_CFG1 0x18
75 #define PLLCTRL_SSC_CFG2 0x1C
76 #define PLLCTRL_CFG4 0x20
80 #define HDMI_TXPHY_TX_CTRL 0x0
81 #define HDMI_TXPHY_DIGITAL_CTRL 0x4
82 #define HDMI_TXPHY_POWER_CTRL 0x8
83 #define HDMI_TXPHY_PAD_CFG_CTRL 0xC
84 #define HDMI_TXPHY_BIST_CONTROL 0x1C
87 HDMI_PLLPWRCMD_ALLOFF
= 0,
88 HDMI_PLLPWRCMD_PLLONLY
= 1,
89 HDMI_PLLPWRCMD_BOTHON_ALLCLKS
= 2,
90 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK
= 3
94 HDMI_PHYPWRCMD_OFF
= 0,
95 HDMI_PHYPWRCMD_LDOON
= 1,
96 HDMI_PHYPWRCMD_TXON
= 2
99 enum hdmi_core_hdmi_dvi
{
104 enum hdmi_clk_refsel
{
105 HDMI_REFSEL_PCLK
= 0,
106 HDMI_REFSEL_REF1
= 1,
107 HDMI_REFSEL_REF2
= 2,
108 HDMI_REFSEL_SYSCLK
= 3
111 enum hdmi_packing_mode
{
112 HDMI_PACK_10b_RGB_YUV444
= 0,
113 HDMI_PACK_24b_RGB_YUV444_YUV422
= 1,
114 HDMI_PACK_20b_YUV422
= 2,
115 HDMI_PACK_ALREADYPACKED
= 7
118 enum hdmi_stereo_channels
{
119 HDMI_AUDIO_STEREO_NOCHANNELS
= 0,
120 HDMI_AUDIO_STEREO_ONECHANNEL
= 1,
121 HDMI_AUDIO_STEREO_TWOCHANNELS
= 2,
122 HDMI_AUDIO_STEREO_THREECHANNELS
= 3,
123 HDMI_AUDIO_STEREO_FOURCHANNELS
= 4
126 enum hdmi_audio_type
{
127 HDMI_AUDIO_TYPE_LPCM
= 0,
128 HDMI_AUDIO_TYPE_IEC
= 1
131 enum hdmi_audio_justify
{
132 HDMI_AUDIO_JUSTIFY_LEFT
= 0,
133 HDMI_AUDIO_JUSTIFY_RIGHT
= 1
136 enum hdmi_audio_sample_order
{
137 HDMI_AUDIO_SAMPLE_RIGHT_FIRST
= 0,
138 HDMI_AUDIO_SAMPLE_LEFT_FIRST
= 1
141 enum hdmi_audio_samples_perword
{
142 HDMI_AUDIO_ONEWORD_ONESAMPLE
= 0,
143 HDMI_AUDIO_ONEWORD_TWOSAMPLES
= 1
146 enum hdmi_audio_sample_size_omap
{
147 HDMI_AUDIO_SAMPLE_16BITS
= 0,
148 HDMI_AUDIO_SAMPLE_24BITS
= 1
151 enum hdmi_audio_transf_mode
{
152 HDMI_AUDIO_TRANSF_DMA
= 0,
153 HDMI_AUDIO_TRANSF_IRQ
= 1
156 enum hdmi_audio_blk_strt_end_sig
{
157 HDMI_AUDIO_BLOCK_SIG_STARTEND_ON
= 0,
158 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF
= 1
161 enum hdmi_core_audio_layout
{
162 HDMI_AUDIO_LAYOUT_2CH
= 0,
163 HDMI_AUDIO_LAYOUT_8CH
= 1
166 enum hdmi_core_cts_mode
{
167 HDMI_AUDIO_CTS_MODE_HW
= 0,
168 HDMI_AUDIO_CTS_MODE_SW
= 1
171 enum hdmi_audio_mclk_mode
{
172 HDMI_AUDIO_MCLK_128FS
= 0,
173 HDMI_AUDIO_MCLK_256FS
= 1,
174 HDMI_AUDIO_MCLK_384FS
= 2,
175 HDMI_AUDIO_MCLK_512FS
= 3,
176 HDMI_AUDIO_MCLK_768FS
= 4,
177 HDMI_AUDIO_MCLK_1024FS
= 5,
178 HDMI_AUDIO_MCLK_1152FS
= 6,
179 HDMI_AUDIO_MCLK_192FS
= 7
182 /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
183 enum hdmi_core_infoframe
{
184 HDMI_INFOFRAME_AVI_DB1Y_RGB
= 0,
185 HDMI_INFOFRAME_AVI_DB1Y_YUV422
= 1,
186 HDMI_INFOFRAME_AVI_DB1Y_YUV444
= 2,
187 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF
= 0,
188 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON
= 1,
189 HDMI_INFOFRAME_AVI_DB1B_NO
= 0,
190 HDMI_INFOFRAME_AVI_DB1B_VERT
= 1,
191 HDMI_INFOFRAME_AVI_DB1B_HORI
= 2,
192 HDMI_INFOFRAME_AVI_DB1B_VERTHORI
= 3,
193 HDMI_INFOFRAME_AVI_DB1S_0
= 0,
194 HDMI_INFOFRAME_AVI_DB1S_1
= 1,
195 HDMI_INFOFRAME_AVI_DB1S_2
= 2,
196 HDMI_INFOFRAME_AVI_DB2C_NO
= 0,
197 HDMI_INFOFRAME_AVI_DB2C_ITU601
= 1,
198 HDMI_INFOFRAME_AVI_DB2C_ITU709
= 2,
199 HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED
= 3,
200 HDMI_INFOFRAME_AVI_DB2M_NO
= 0,
201 HDMI_INFOFRAME_AVI_DB2M_43
= 1,
202 HDMI_INFOFRAME_AVI_DB2M_169
= 2,
203 HDMI_INFOFRAME_AVI_DB2R_SAME
= 8,
204 HDMI_INFOFRAME_AVI_DB2R_43
= 9,
205 HDMI_INFOFRAME_AVI_DB2R_169
= 10,
206 HDMI_INFOFRAME_AVI_DB2R_149
= 11,
207 HDMI_INFOFRAME_AVI_DB3ITC_NO
= 0,
208 HDMI_INFOFRAME_AVI_DB3ITC_YES
= 1,
209 HDMI_INFOFRAME_AVI_DB3EC_XVYUV601
= 0,
210 HDMI_INFOFRAME_AVI_DB3EC_XVYUV709
= 1,
211 HDMI_INFOFRAME_AVI_DB3Q_DEFAULT
= 0,
212 HDMI_INFOFRAME_AVI_DB3Q_LR
= 1,
213 HDMI_INFOFRAME_AVI_DB3Q_FR
= 2,
214 HDMI_INFOFRAME_AVI_DB3SC_NO
= 0,
215 HDMI_INFOFRAME_AVI_DB3SC_HORI
= 1,
216 HDMI_INFOFRAME_AVI_DB3SC_VERT
= 2,
217 HDMI_INFOFRAME_AVI_DB3SC_HORIVERT
= 3,
218 HDMI_INFOFRAME_AVI_DB5PR_NO
= 0,
219 HDMI_INFOFRAME_AVI_DB5PR_2
= 1,
220 HDMI_INFOFRAME_AVI_DB5PR_3
= 2,
221 HDMI_INFOFRAME_AVI_DB5PR_4
= 3,
222 HDMI_INFOFRAME_AVI_DB5PR_5
= 4,
223 HDMI_INFOFRAME_AVI_DB5PR_6
= 5,
224 HDMI_INFOFRAME_AVI_DB5PR_7
= 6,
225 HDMI_INFOFRAME_AVI_DB5PR_8
= 7,
226 HDMI_INFOFRAME_AVI_DB5PR_9
= 8,
227 HDMI_INFOFRAME_AVI_DB5PR_10
= 9,
235 struct hdmi_video_format
{
236 enum hdmi_packing_mode packing_mode
;
237 u32 y_res
; /* Line per panel */
238 u32 x_res
; /* pixel per line */
242 struct omap_video_timings timings
;
246 /* HDMI PLL structure */
247 struct hdmi_pll_info
{
254 enum hdmi_clk_refsel refsel
;
257 struct hdmi_audio_format
{
258 enum hdmi_stereo_channels stereo_channels
;
259 u8 active_chnnls_msk
;
260 enum hdmi_audio_type type
;
261 enum hdmi_audio_justify justification
;
262 enum hdmi_audio_sample_order sample_order
;
263 enum hdmi_audio_samples_perword samples_per_word
;
264 enum hdmi_audio_sample_size_omap sample_size
;
265 enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end
;
268 struct hdmi_audio_dma
{
271 enum hdmi_audio_transf_mode mode
;
275 struct hdmi_core_audio_i2s_config
{
285 struct hdmi_core_audio_config
{
286 struct hdmi_core_audio_i2s_config i2s_cfg
;
287 struct snd_aes_iec958
*iec60958_cfg
;
292 enum hdmi_core_audio_layout layout
;
293 enum hdmi_core_cts_mode cts_mode
;
295 enum hdmi_audio_mclk_mode mclk_mode
;
298 bool en_parallel_aud_input
;
303 * Refer to section 8.2 in HDMI 1.3 specification for
304 * details about infoframe databytes
306 struct hdmi_core_infoframe_avi
{
307 /* Y0, Y1 rgb,yCbCr */
309 /* A0 Active information Present */
311 /* B0, B1 Bar info data valid */
313 /* S0, S1 scan information */
315 /* C0, C1 colorimetry */
317 /* M0, M1 Aspect ratio (4:3, 16:9) */
319 /* R0...R3 Active format aspect ratio */
320 u8 db2_active_fmt_ar
;
321 /* ITC IT content. */
323 /* EC0, EC1, EC2 Extended colorimetry */
325 /* Q1, Q0 Quantization range */
327 /* SC1, SC0 Non-uniform picture scaling */
329 /* VIC0..6 Video format identification */
331 /* PR0..PR3 Pixel repetition factor */
333 /* Line number end of top bar */
334 u16 db6_7_line_eoftop
;
335 /* Line number start of bottom bar */
336 u16 db8_9_line_sofbottom
;
337 /* Pixel number end of left bar */
338 u16 db10_11_pixel_eofleft
;
339 /* Pixel number start of right bar */
340 u16 db12_13_pixel_sofright
;
343 struct hdmi_wp_data
{
347 struct hdmi_pll_data
{
350 struct hdmi_pll_info info
;
353 struct hdmi_phy_data
{
360 struct hdmi_core_data
{
363 struct hdmi_core_infoframe_avi avi_cfg
;
364 struct hdmi_avi_infoframe avi_infoframe
;
367 static inline void hdmi_write_reg(void __iomem
*base_addr
, const u32 idx
,
370 __raw_writel(val
, base_addr
+ idx
);
373 static inline u32
hdmi_read_reg(void __iomem
*base_addr
, const u32 idx
)
375 return __raw_readl(base_addr
+ idx
);
378 #define REG_FLD_MOD(base, idx, val, start, end) \
379 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
381 #define REG_GET(base, idx, start, end) \
382 FLD_GET(hdmi_read_reg(base, idx), start, end)
384 static inline int hdmi_wait_for_bit_change(void __iomem
*base_addr
,
385 const u32 idx
, int b2
, int b1
, u32 val
)
388 while (val
!= (v
= REG_GET(base_addr
, idx
, b2
, b1
))) {
396 /* HDMI wrapper funcs */
397 int hdmi_wp_video_start(struct hdmi_wp_data
*wp
);
398 void hdmi_wp_video_stop(struct hdmi_wp_data
*wp
);
399 void hdmi_wp_dump(struct hdmi_wp_data
*wp
, struct seq_file
*s
);
400 u32
hdmi_wp_get_irqstatus(struct hdmi_wp_data
*wp
);
401 void hdmi_wp_set_irqstatus(struct hdmi_wp_data
*wp
, u32 irqstatus
);
402 void hdmi_wp_set_irqenable(struct hdmi_wp_data
*wp
, u32 mask
);
403 void hdmi_wp_clear_irqenable(struct hdmi_wp_data
*wp
, u32 mask
);
404 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data
*wp
, enum hdmi_phy_pwr val
);
405 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data
*wp
, enum hdmi_pll_pwr val
);
406 void hdmi_wp_video_config_format(struct hdmi_wp_data
*wp
,
407 struct hdmi_video_format
*video_fmt
);
408 void hdmi_wp_video_config_interface(struct hdmi_wp_data
*wp
,
409 struct omap_video_timings
*timings
);
410 void hdmi_wp_video_config_timing(struct hdmi_wp_data
*wp
,
411 struct omap_video_timings
*timings
);
412 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format
*video_fmt
,
413 struct omap_video_timings
*timings
, struct hdmi_config
*param
);
414 int hdmi_wp_init(struct platform_device
*pdev
, struct hdmi_wp_data
*wp
);
417 int hdmi_pll_enable(struct hdmi_pll_data
*pll
, struct hdmi_wp_data
*wp
);
418 void hdmi_pll_disable(struct hdmi_pll_data
*pll
, struct hdmi_wp_data
*wp
);
419 void hdmi_pll_dump(struct hdmi_pll_data
*pll
, struct seq_file
*s
);
420 void hdmi_pll_compute(struct hdmi_pll_data
*pll
, unsigned long clkin
, int phy
);
421 int hdmi_pll_init(struct platform_device
*pdev
, struct hdmi_pll_data
*pll
);
424 int hdmi_phy_configure(struct hdmi_phy_data
*phy
, struct hdmi_config
*cfg
);
425 void hdmi_phy_dump(struct hdmi_phy_data
*phy
, struct seq_file
*s
);
426 int hdmi_phy_init(struct platform_device
*pdev
, struct hdmi_phy_data
*phy
);
427 int hdmi_phy_parse_lanes(struct hdmi_phy_data
*phy
, const u32
*lanes
);
429 /* HDMI common funcs */
430 const struct hdmi_config
*hdmi_default_timing(void);
431 const struct hdmi_config
*hdmi_get_timings(int mode
, int code
);
432 struct hdmi_cm
hdmi_get_code(struct omap_video_timings
*timing
);
433 int hdmi_parse_lanes_of(struct platform_device
*pdev
, struct device_node
*ep
,
434 struct hdmi_phy_data
*phy
);
436 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
437 int hdmi_compute_acr(u32 pclk
, u32 sample_freq
, u32
*n
, u32
*cts
);
438 int hdmi_wp_audio_enable(struct hdmi_wp_data
*wp
, bool enable
);
439 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data
*wp
, bool enable
);
440 void hdmi_wp_audio_config_format(struct hdmi_wp_data
*wp
,
441 struct hdmi_audio_format
*aud_fmt
);
442 void hdmi_wp_audio_config_dma(struct hdmi_wp_data
*wp
,
443 struct hdmi_audio_dma
*aud_dma
);
444 static inline bool hdmi_mode_has_audio(int mode
)
446 return mode
== HDMI_HDMI
? true : false;