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[PATCH] drivers/video/: possible cleanups
[deliverable/linux.git] / drivers / video / i810 / i810_main.c
1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_main.c -- Intel 810 frame buffer device
3 *
4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
5 * All Rights Reserved
6 *
7 * Contributors:
8 * Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets
9 * and enabling the power-on state of
10 * external VGA connectors for
11 * secondary displays
12 *
13 * Fredrik Andersson <krueger@shell.linux.se> - alpha testing of
14 * the VESA GTF
15 *
16 * Brad Corrion <bcorrion@web-co.com> - alpha testing of customized
17 * timings support
18 *
19 * The code framework is a modification of vfb.c by Geert Uytterhoeven.
20 * DotClock and PLL calculations are partly based on i810_driver.c
21 * in xfree86 v4.0.3 by Precision Insight.
22 * Watermark calculation and tables are based on i810_wmark.c
23 * in xfre86 v4.0.3 by Precision Insight. Slight modifications
24 * only to allow for integer operations instead of floating point.
25 *
26 * This file is subject to the terms and conditions of the GNU General Public
27 * License. See the file COPYING in the main directory of this archive for
28 * more details.
29 */
30
31 #include <linux/module.h>
32 #include <linux/config.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
36 #include <linux/mm.h>
37 #include <linux/tty.h>
38 #include <linux/slab.h>
39 #include <linux/fb.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/pci_ids.h>
43 #include <linux/resource.h>
44 #include <linux/unistd.h>
45 #include <linux/console.h>
46
47 #include <asm/io.h>
48 #include <asm/div64.h>
49 #include <asm/page.h>
50
51 #include "i810_regs.h"
52 #include "i810.h"
53 #include "i810_main.h"
54
55 /*
56 * voffset - framebuffer offset in MiB from aperture start address. In order for
57 * the driver to work with X, we must try to use memory holes left untouched by X. The
58 * following table lists where X's different surfaces start at.
59 *
60 * ---------------------------------------------
61 * : : 64 MiB : 32 MiB :
62 * ----------------------------------------------
63 * : FrontBuffer : 0 : 0 :
64 * : DepthBuffer : 48 : 16 :
65 * : BackBuffer : 56 : 24 :
66 * ----------------------------------------------
67 *
68 * So for chipsets with 64 MiB Aperture sizes, 32 MiB for v_offset is okay, allowing up to
69 * 15 + 1 MiB of Framebuffer memory. For 32 MiB Aperture sizes, a v_offset of 8 MiB should
70 * work, allowing 7 + 1 MiB of Framebuffer memory.
71 * Note, the size of the hole may change depending on how much memory you allocate to X,
72 * and how the memory is split up between these surfaces.
73 *
74 * Note: Anytime the DepthBuffer or FrontBuffer is overlapped, X would still run but with
75 * DRI disabled. But if the Frontbuffer is overlapped, X will fail to load.
76 *
77 * Experiment with v_offset to find out which works best for you.
78 */
79 static u32 v_offset_default __initdata; /* For 32 MiB Aper size, 8 should be the default */
80 static u32 voffset __initdata = 0;
81
82 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
83 static int __devinit i810fb_init_pci (struct pci_dev *dev,
84 const struct pci_device_id *entry);
85 static void __exit i810fb_remove_pci(struct pci_dev *dev);
86 static int i810fb_resume(struct pci_dev *dev);
87 static int i810fb_suspend(struct pci_dev *dev, pm_message_t state);
88
89 /* Chipset Specific Functions */
90 static int i810fb_set_par (struct fb_info *info);
91 static int i810fb_getcolreg (u8 regno, u8 *red, u8 *green, u8 *blue,
92 u8 *transp, struct fb_info *info);
93 static int i810fb_setcolreg (unsigned regno, unsigned red, unsigned green, unsigned blue,
94 unsigned transp, struct fb_info *info);
95 static int i810fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
96 static int i810fb_blank (int blank_mode, struct fb_info *info);
97
98 /* Initialization */
99 static void i810fb_release_resource (struct fb_info *info, struct i810fb_par *par);
100
101 /* PCI */
102 static const char *i810_pci_list[] __devinitdata = {
103 "Intel(R) 810 Framebuffer Device" ,
104 "Intel(R) 810-DC100 Framebuffer Device" ,
105 "Intel(R) 810E Framebuffer Device" ,
106 "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" ,
107 "Intel(R) 815 (Internal Graphics only) Framebuffer Device" ,
108 "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device"
109 };
110
111 static struct pci_device_id i810fb_pci_tbl[] = {
112 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
114 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
116 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
118 /* mvo: added i815 PCI-ID */
119 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
121 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
123 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
125 { 0 },
126 };
127
128 static struct pci_driver i810fb_driver = {
129 .name = "i810fb",
130 .id_table = i810fb_pci_tbl,
131 .probe = i810fb_init_pci,
132 .remove = __exit_p(i810fb_remove_pci),
133 .suspend = i810fb_suspend,
134 .resume = i810fb_resume,
135 };
136
137 static char *mode_option __devinitdata = NULL;
138 static int vram __devinitdata = 4;
139 static int bpp __devinitdata = 8;
140 static int mtrr __devinitdata;
141 static int accel __devinitdata;
142 static int hsync1 __devinitdata;
143 static int hsync2 __devinitdata;
144 static int vsync1 __devinitdata;
145 static int vsync2 __devinitdata;
146 static int xres __devinitdata;
147 static int yres __devinitdata;
148 static int vyres __devinitdata;
149 static int sync __devinitdata;
150 static int extvga __devinitdata;
151 static int dcolor __devinitdata;
152
153 /*------------------------------------------------------------*/
154
155 /**************************************************************
156 * Hardware Low Level Routines *
157 **************************************************************/
158
159 /**
160 * i810_screen_off - turns off/on display
161 * @mmio: address of register space
162 * @mode: on or off
163 *
164 * DESCRIPTION:
165 * Blanks/unblanks the display
166 */
167 static void i810_screen_off(u8 __iomem *mmio, u8 mode)
168 {
169 u32 count = WAIT_COUNT;
170 u8 val;
171
172 i810_writeb(SR_INDEX, mmio, SR01);
173 val = i810_readb(SR_DATA, mmio);
174 val = (mode == OFF) ? val | SCR_OFF :
175 val & ~SCR_OFF;
176
177 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
178 i810_writeb(SR_INDEX, mmio, SR01);
179 i810_writeb(SR_DATA, mmio, val);
180 }
181
182 /**
183 * i810_dram_off - turns off/on dram refresh
184 * @mmio: address of register space
185 * @mode: on or off
186 *
187 * DESCRIPTION:
188 * Turns off DRAM refresh. Must be off for only 2 vsyncs
189 * before data becomes corrupt
190 */
191 static void i810_dram_off(u8 __iomem *mmio, u8 mode)
192 {
193 u8 val;
194
195 val = i810_readb(DRAMCH, mmio);
196 val &= DRAM_OFF;
197 val = (mode == OFF) ? val : val | DRAM_ON;
198 i810_writeb(DRAMCH, mmio, val);
199 }
200
201 /**
202 * i810_protect_regs - allows rw/ro mode of certain VGA registers
203 * @mmio: address of register space
204 * @mode: protect/unprotect
205 *
206 * DESCRIPTION:
207 * The IBM VGA standard allows protection of certain VGA registers.
208 * This will protect or unprotect them.
209 */
210 static void i810_protect_regs(u8 __iomem *mmio, int mode)
211 {
212 u8 reg;
213
214 i810_writeb(CR_INDEX_CGA, mmio, CR11);
215 reg = i810_readb(CR_DATA_CGA, mmio);
216 reg = (mode == OFF) ? reg & ~0x80 :
217 reg | 0x80;
218
219 i810_writeb(CR_INDEX_CGA, mmio, CR11);
220 i810_writeb(CR_DATA_CGA, mmio, reg);
221 }
222
223 /**
224 * i810_load_pll - loads values for the hardware PLL clock
225 * @par: pointer to i810fb_par structure
226 *
227 * DESCRIPTION:
228 * Loads the P, M, and N registers.
229 */
230 static void i810_load_pll(struct i810fb_par *par)
231 {
232 u32 tmp1, tmp2;
233 u8 __iomem *mmio = par->mmio_start_virtual;
234
235 tmp1 = par->regs.M | par->regs.N << 16;
236 tmp2 = i810_readl(DCLK_2D, mmio);
237 tmp2 &= ~MN_MASK;
238 i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
239
240 tmp1 = par->regs.P;
241 tmp2 = i810_readl(DCLK_0DS, mmio);
242 tmp2 &= ~(P_OR << 16);
243 i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2);
244
245 i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1);
246
247 }
248
249 /**
250 * i810_load_vga - load standard VGA registers
251 * @par: pointer to i810fb_par structure
252 *
253 * DESCRIPTION:
254 * Load values to VGA registers
255 */
256 static void i810_load_vga(struct i810fb_par *par)
257 {
258 u8 __iomem *mmio = par->mmio_start_virtual;
259
260 /* interlace */
261 i810_writeb(CR_INDEX_CGA, mmio, CR70);
262 i810_writeb(CR_DATA_CGA, mmio, par->interlace);
263
264 i810_writeb(CR_INDEX_CGA, mmio, CR00);
265 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00);
266 i810_writeb(CR_INDEX_CGA, mmio, CR01);
267 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01);
268 i810_writeb(CR_INDEX_CGA, mmio, CR02);
269 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02);
270 i810_writeb(CR_INDEX_CGA, mmio, CR03);
271 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03);
272 i810_writeb(CR_INDEX_CGA, mmio, CR04);
273 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04);
274 i810_writeb(CR_INDEX_CGA, mmio, CR05);
275 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05);
276 i810_writeb(CR_INDEX_CGA, mmio, CR06);
277 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06);
278 i810_writeb(CR_INDEX_CGA, mmio, CR09);
279 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09);
280 i810_writeb(CR_INDEX_CGA, mmio, CR10);
281 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10);
282 i810_writeb(CR_INDEX_CGA, mmio, CR11);
283 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11);
284 i810_writeb(CR_INDEX_CGA, mmio, CR12);
285 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12);
286 i810_writeb(CR_INDEX_CGA, mmio, CR15);
287 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15);
288 i810_writeb(CR_INDEX_CGA, mmio, CR16);
289 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16);
290 }
291
292 /**
293 * i810_load_vgax - load extended VGA registers
294 * @par: pointer to i810fb_par structure
295 *
296 * DESCRIPTION:
297 * Load values to extended VGA registers
298 */
299 static void i810_load_vgax(struct i810fb_par *par)
300 {
301 u8 __iomem *mmio = par->mmio_start_virtual;
302
303 i810_writeb(CR_INDEX_CGA, mmio, CR30);
304 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30);
305 i810_writeb(CR_INDEX_CGA, mmio, CR31);
306 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31);
307 i810_writeb(CR_INDEX_CGA, mmio, CR32);
308 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32);
309 i810_writeb(CR_INDEX_CGA, mmio, CR33);
310 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33);
311 i810_writeb(CR_INDEX_CGA, mmio, CR35);
312 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35);
313 i810_writeb(CR_INDEX_CGA, mmio, CR39);
314 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39);
315 }
316
317 /**
318 * i810_load_2d - load grahics registers
319 * @par: pointer to i810fb_par structure
320 *
321 * DESCRIPTION:
322 * Load values to graphics registers
323 */
324 static void i810_load_2d(struct i810fb_par *par)
325 {
326 u32 tmp;
327 u8 tmp8;
328 u8 __iomem *mmio = par->mmio_start_virtual;
329
330 i810_writel(FW_BLC, mmio, par->watermark);
331 tmp = i810_readl(PIXCONF, mmio);
332 tmp |= 1 | 1 << 20;
333 i810_writel(PIXCONF, mmio, tmp);
334
335 i810_writel(OVRACT, mmio, par->ovract);
336
337 i810_writeb(GR_INDEX, mmio, GR10);
338 tmp8 = i810_readb(GR_DATA, mmio);
339 tmp8 |= 2;
340 i810_writeb(GR_INDEX, mmio, GR10);
341 i810_writeb(GR_DATA, mmio, tmp8);
342 }
343
344 /**
345 * i810_hires - enables high resolution mode
346 * @mmio: address of register space
347 */
348 static void i810_hires(u8 __iomem *mmio)
349 {
350 u8 val;
351
352 i810_writeb(CR_INDEX_CGA, mmio, CR80);
353 val = i810_readb(CR_DATA_CGA, mmio);
354 i810_writeb(CR_INDEX_CGA, mmio, CR80);
355 i810_writeb(CR_DATA_CGA, mmio, val | 1);
356 /* Stop LCD displays from flickering */
357 i810_writel(MEM_MODE, mmio, i810_readl(MEM_MODE, mmio) | 4);
358 }
359
360 /**
361 * i810_load_pitch - loads the characters per line of the display
362 * @par: pointer to i810fb_par structure
363 *
364 * DESCRIPTION:
365 * Loads the characters per line
366 */
367 static void i810_load_pitch(struct i810fb_par *par)
368 {
369 u32 tmp, pitch;
370 u8 val;
371 u8 __iomem *mmio = par->mmio_start_virtual;
372
373 pitch = par->pitch >> 3;
374 i810_writeb(SR_INDEX, mmio, SR01);
375 val = i810_readb(SR_DATA, mmio);
376 val &= 0xE0;
377 val |= 1 | 1 << 2;
378 i810_writeb(SR_INDEX, mmio, SR01);
379 i810_writeb(SR_DATA, mmio, val);
380
381 tmp = pitch & 0xFF;
382 i810_writeb(CR_INDEX_CGA, mmio, CR13);
383 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp);
384
385 tmp = pitch >> 8;
386 i810_writeb(CR_INDEX_CGA, mmio, CR41);
387 val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F;
388 i810_writeb(CR_INDEX_CGA, mmio, CR41);
389 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val);
390 }
391
392 /**
393 * i810_load_color - loads the color depth of the display
394 * @par: pointer to i810fb_par structure
395 *
396 * DESCRIPTION:
397 * Loads the color depth of the display and the graphics engine
398 */
399 static void i810_load_color(struct i810fb_par *par)
400 {
401 u8 __iomem *mmio = par->mmio_start_virtual;
402 u32 reg1;
403 u16 reg2;
404
405 reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27);
406 reg2 = i810_readw(BLTCNTL, mmio) & ~0x30;
407
408 reg1 |= 0x8000 | par->pixconf;
409 reg2 |= par->bltcntl;
410 i810_writel(PIXCONF, mmio, reg1);
411 i810_writew(BLTCNTL, mmio, reg2);
412 }
413
414 /**
415 * i810_load_regs - loads all registers for the mode
416 * @par: pointer to i810fb_par structure
417 *
418 * DESCRIPTION:
419 * Loads registers
420 */
421 static void i810_load_regs(struct i810fb_par *par)
422 {
423 u8 __iomem *mmio = par->mmio_start_virtual;
424
425 i810_screen_off(mmio, OFF);
426 i810_protect_regs(mmio, OFF);
427 i810_dram_off(mmio, OFF);
428 i810_load_pll(par);
429 i810_load_vga(par);
430 i810_load_vgax(par);
431 i810_dram_off(mmio, ON);
432 i810_load_2d(par);
433 i810_hires(mmio);
434 i810_screen_off(mmio, ON);
435 i810_protect_regs(mmio, ON);
436 i810_load_color(par);
437 i810_load_pitch(par);
438 }
439
440 static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue,
441 u8 __iomem *mmio)
442 {
443 i810_writeb(CLUT_INDEX_WRITE, mmio, regno);
444 i810_writeb(CLUT_DATA, mmio, red);
445 i810_writeb(CLUT_DATA, mmio, green);
446 i810_writeb(CLUT_DATA, mmio, blue);
447 }
448
449 static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue,
450 u8 __iomem *mmio)
451 {
452 i810_writeb(CLUT_INDEX_READ, mmio, regno);
453 *red = i810_readb(CLUT_DATA, mmio);
454 *green = i810_readb(CLUT_DATA, mmio);
455 *blue = i810_readb(CLUT_DATA, mmio);
456 }
457
458 /************************************************************
459 * VGA State Restore *
460 ************************************************************/
461 static void i810_restore_pll(struct i810fb_par *par)
462 {
463 u32 tmp1, tmp2;
464 u8 __iomem *mmio = par->mmio_start_virtual;
465
466 tmp1 = par->hw_state.dclk_2d;
467 tmp2 = i810_readl(DCLK_2D, mmio);
468 tmp1 &= ~MN_MASK;
469 tmp2 &= MN_MASK;
470 i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
471
472 tmp1 = par->hw_state.dclk_1d;
473 tmp2 = i810_readl(DCLK_1D, mmio);
474 tmp1 &= ~MN_MASK;
475 tmp2 &= MN_MASK;
476 i810_writel(DCLK_1D, mmio, tmp1 | tmp2);
477
478 i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds);
479 }
480
481 static void i810_restore_dac(struct i810fb_par *par)
482 {
483 u32 tmp1, tmp2;
484 u8 __iomem *mmio = par->mmio_start_virtual;
485
486 tmp1 = par->hw_state.pixconf;
487 tmp2 = i810_readl(PIXCONF, mmio);
488 tmp1 &= DAC_BIT;
489 tmp2 &= ~DAC_BIT;
490 i810_writel(PIXCONF, mmio, tmp1 | tmp2);
491 }
492
493 static void i810_restore_vgax(struct i810fb_par *par)
494 {
495 u8 i, j;
496 u8 __iomem *mmio = par->mmio_start_virtual;
497
498 for (i = 0; i < 4; i++) {
499 i810_writeb(CR_INDEX_CGA, mmio, CR30+i);
500 i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i));
501 }
502 i810_writeb(CR_INDEX_CGA, mmio, CR35);
503 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35);
504 i810_writeb(CR_INDEX_CGA, mmio, CR39);
505 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
506 i810_writeb(CR_INDEX_CGA, mmio, CR41);
507 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
508
509 /*restore interlace*/
510 i810_writeb(CR_INDEX_CGA, mmio, CR70);
511 i = par->hw_state.cr70;
512 i &= INTERLACE_BIT;
513 j = i810_readb(CR_DATA_CGA, mmio);
514 i810_writeb(CR_INDEX_CGA, mmio, CR70);
515 i810_writeb(CR_DATA_CGA, mmio, j | i);
516
517 i810_writeb(CR_INDEX_CGA, mmio, CR80);
518 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80);
519 i810_writeb(MSR_WRITE, mmio, par->hw_state.msr);
520 i810_writeb(SR_INDEX, mmio, SR01);
521 i = (par->hw_state.sr01) & ~0xE0 ;
522 j = i810_readb(SR_DATA, mmio) & 0xE0;
523 i810_writeb(SR_INDEX, mmio, SR01);
524 i810_writeb(SR_DATA, mmio, i | j);
525 }
526
527 static void i810_restore_vga(struct i810fb_par *par)
528 {
529 u8 i;
530 u8 __iomem *mmio = par->mmio_start_virtual;
531
532 for (i = 0; i < 10; i++) {
533 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
534 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i));
535 }
536 for (i = 0; i < 8; i++) {
537 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
538 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i));
539 }
540 }
541
542 static void i810_restore_addr_map(struct i810fb_par *par)
543 {
544 u8 tmp;
545 u8 __iomem *mmio = par->mmio_start_virtual;
546
547 i810_writeb(GR_INDEX, mmio, GR10);
548 tmp = i810_readb(GR_DATA, mmio);
549 tmp &= ADDR_MAP_MASK;
550 tmp |= par->hw_state.gr10;
551 i810_writeb(GR_INDEX, mmio, GR10);
552 i810_writeb(GR_DATA, mmio, tmp);
553 }
554
555 static void i810_restore_2d(struct i810fb_par *par)
556 {
557 u32 tmp_long;
558 u16 tmp_word;
559 u8 __iomem *mmio = par->mmio_start_virtual;
560
561 tmp_word = i810_readw(BLTCNTL, mmio);
562 tmp_word &= ~(3 << 4);
563 tmp_word |= par->hw_state.bltcntl;
564 i810_writew(BLTCNTL, mmio, tmp_word);
565
566 i810_dram_off(mmio, OFF);
567 i810_writel(PIXCONF, mmio, par->hw_state.pixconf);
568 i810_dram_off(mmio, ON);
569
570 tmp_word = i810_readw(HWSTAM, mmio);
571 tmp_word &= 3 << 13;
572 tmp_word |= par->hw_state.hwstam;
573 i810_writew(HWSTAM, mmio, tmp_word);
574
575 tmp_long = i810_readl(FW_BLC, mmio);
576 tmp_long &= FW_BLC_MASK;
577 tmp_long |= par->hw_state.fw_blc;
578 i810_writel(FW_BLC, mmio, tmp_long);
579
580 i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga);
581 i810_writew(IER, mmio, par->hw_state.ier);
582 i810_writew(IMR, mmio, par->hw_state.imr);
583 i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas);
584 }
585
586 static void i810_restore_vga_state(struct i810fb_par *par)
587 {
588 u8 __iomem *mmio = par->mmio_start_virtual;
589
590 i810_screen_off(mmio, OFF);
591 i810_protect_regs(mmio, OFF);
592 i810_dram_off(mmio, OFF);
593 i810_restore_pll(par);
594 i810_restore_dac(par);
595 i810_restore_vga(par);
596 i810_restore_vgax(par);
597 i810_restore_addr_map(par);
598 i810_dram_off(mmio, ON);
599 i810_restore_2d(par);
600 i810_screen_off(mmio, ON);
601 i810_protect_regs(mmio, ON);
602 }
603
604 /***********************************************************************
605 * VGA State Save *
606 ***********************************************************************/
607
608 static void i810_save_vgax(struct i810fb_par *par)
609 {
610 u8 i;
611 u8 __iomem *mmio = par->mmio_start_virtual;
612
613 for (i = 0; i < 4; i++) {
614 i810_writeb(CR_INDEX_CGA, mmio, CR30 + i);
615 *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio);
616 }
617 i810_writeb(CR_INDEX_CGA, mmio, CR35);
618 par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio);
619 i810_writeb(CR_INDEX_CGA, mmio, CR39);
620 par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio);
621 i810_writeb(CR_INDEX_CGA, mmio, CR41);
622 par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio);
623 i810_writeb(CR_INDEX_CGA, mmio, CR70);
624 par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio);
625 par->hw_state.msr = i810_readb(MSR_READ, mmio);
626 i810_writeb(CR_INDEX_CGA, mmio, CR80);
627 par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio);
628 i810_writeb(SR_INDEX, mmio, SR01);
629 par->hw_state.sr01 = i810_readb(SR_DATA, mmio);
630 }
631
632 static void i810_save_vga(struct i810fb_par *par)
633 {
634 u8 i;
635 u8 __iomem *mmio = par->mmio_start_virtual;
636
637 for (i = 0; i < 10; i++) {
638 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
639 *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio);
640 }
641 for (i = 0; i < 8; i++) {
642 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
643 *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio);
644 }
645 }
646
647 static void i810_save_2d(struct i810fb_par *par)
648 {
649 u8 __iomem *mmio = par->mmio_start_virtual;
650
651 par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio);
652 par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio);
653 par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio);
654 par->hw_state.pixconf = i810_readl(PIXCONF, mmio);
655 par->hw_state.fw_blc = i810_readl(FW_BLC, mmio);
656 par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio);
657 par->hw_state.hwstam = i810_readw(HWSTAM, mmio);
658 par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio);
659 par->hw_state.ier = i810_readw(IER, mmio);
660 par->hw_state.imr = i810_readw(IMR, mmio);
661 par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio);
662 }
663
664 static void i810_save_vga_state(struct i810fb_par *par)
665 {
666 i810_save_vga(par);
667 i810_save_vgax(par);
668 i810_save_2d(par);
669 }
670
671 /************************************************************
672 * Helpers *
673 ************************************************************/
674 /**
675 * get_line_length - calculates buffer pitch in bytes
676 * @par: pointer to i810fb_par structure
677 * @xres_virtual: virtual resolution of the frame
678 * @bpp: bits per pixel
679 *
680 * DESCRIPTION:
681 * Calculates buffer pitch in bytes.
682 */
683 static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp)
684 {
685 u32 length;
686
687 length = xres_virtual*bpp;
688 length = (length+31)&-32;
689 length >>= 3;
690 return length;
691 }
692
693 /**
694 * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value
695 * @freq: target pixelclock in picoseconds
696 * @m: where to write M register
697 * @n: where to write N register
698 * @p: where to write P register
699 *
700 * DESCRIPTION:
701 * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P)
702 * Repeatedly computes the Freq until the actual Freq is equal to
703 * the target Freq or until the loop count is zero. In the latter
704 * case, the actual frequency nearest the target will be used.
705 */
706 static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p)
707 {
708 u32 m_reg, n_reg, p_divisor, n_target_max;
709 u32 m_target, n_target, p_target, n_best, m_best, mod;
710 u32 f_out, target_freq, diff = 0, mod_min, diff_min;
711
712 diff_min = mod_min = 0xFFFFFFFF;
713 n_best = m_best = m_target = f_out = 0;
714
715 target_freq = freq;
716 n_target_max = 30;
717
718 /*
719 * find P such that target freq is 16x reference freq (Hz).
720 */
721 p_divisor = 1;
722 p_target = 0;
723 while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) &&
724 p_divisor <= 32) {
725 p_divisor <<= 1;
726 p_target++;
727 }
728
729 n_reg = m_reg = n_target = 3;
730 while (diff_min && mod_min && (n_target < n_target_max)) {
731 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg);
732 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg);
733 m_target = m_reg;
734 n_target = n_reg;
735 if (f_out <= target_freq) {
736 n_reg++;
737 diff = target_freq - f_out;
738 } else {
739 m_reg++;
740 diff = f_out - target_freq;
741 }
742
743 if (diff_min > diff) {
744 diff_min = diff;
745 n_best = n_target;
746 m_best = m_target;
747 }
748
749 if (!diff && mod_min > mod) {
750 mod_min = mod;
751 n_best = n_target;
752 m_best = m_target;
753 }
754 }
755 if (m) *m = (m_best - 2) & 0x3FF;
756 if (n) *n = (n_best - 2) & 0x3FF;
757 if (p) *p = (p_target << 4);
758 }
759
760 /*************************************************************
761 * Hardware Cursor Routines *
762 *************************************************************/
763
764 /**
765 * i810_enable_cursor - show or hide the hardware cursor
766 * @mmio: address of register space
767 * @mode: show (1) or hide (0)
768 *
769 * Description:
770 * Shows or hides the hardware cursor
771 */
772 static void i810_enable_cursor(u8 __iomem *mmio, int mode)
773 {
774 u32 temp;
775
776 temp = i810_readl(PIXCONF, mmio);
777 temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK :
778 temp & ~CURSOR_ENABLE_MASK;
779
780 i810_writel(PIXCONF, mmio, temp);
781 }
782
783 static void i810_reset_cursor_image(struct i810fb_par *par)
784 {
785 u8 __iomem *addr = par->cursor_heap.virtual;
786 int i, j;
787
788 for (i = 64; i--; ) {
789 for (j = 0; j < 8; j++) {
790 i810_writeb(j, addr, 0xff);
791 i810_writeb(j+8, addr, 0x00);
792 }
793 addr +=16;
794 }
795 }
796
797 static void i810_load_cursor_image(int width, int height, u8 *data,
798 struct i810fb_par *par)
799 {
800 u8 __iomem *addr = par->cursor_heap.virtual;
801 int i, j, w = width/8;
802 int mod = width % 8, t_mask, d_mask;
803
804 t_mask = 0xff >> mod;
805 d_mask = ~(0xff >> mod);
806 for (i = height; i--; ) {
807 for (j = 0; j < w; j++) {
808 i810_writeb(j+0, addr, 0x00);
809 i810_writeb(j+8, addr, *data++);
810 }
811 if (mod) {
812 i810_writeb(j+0, addr, t_mask);
813 i810_writeb(j+8, addr, *data++ & d_mask);
814 }
815 addr += 16;
816 }
817 }
818
819 static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info)
820 {
821 struct i810fb_par *par = info->par;
822 u8 __iomem *mmio = par->mmio_start_virtual;
823 u8 red, green, blue, trans, temp;
824
825 i810fb_getcolreg(bg, &red, &green, &blue, &trans, info);
826
827 temp = i810_readb(PIXCONF1, mmio);
828 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
829
830 i810_write_dac(4, red, green, blue, mmio);
831
832 i810_writeb(PIXCONF1, mmio, temp);
833
834 i810fb_getcolreg(fg, &red, &green, &blue, &trans, info);
835 temp = i810_readb(PIXCONF1, mmio);
836 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
837
838 i810_write_dac(5, red, green, blue, mmio);
839
840 i810_writeb(PIXCONF1, mmio, temp);
841 }
842
843 /**
844 * i810_init_cursor - initializes the cursor
845 * @par: pointer to i810fb_par structure
846 *
847 * DESCRIPTION:
848 * Initializes the cursor registers
849 */
850 static void i810_init_cursor(struct i810fb_par *par)
851 {
852 u8 __iomem *mmio = par->mmio_start_virtual;
853
854 i810_enable_cursor(mmio, OFF);
855 i810_writel(CURBASE, mmio, par->cursor_heap.physical);
856 i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR);
857 }
858
859 /*********************************************************************
860 * Framebuffer hook helpers *
861 *********************************************************************/
862 /**
863 * i810_round_off - Round off values to capability of hardware
864 * @var: pointer to fb_var_screeninfo structure
865 *
866 * DESCRIPTION:
867 * @var contains user-defined information for the mode to be set.
868 * This will try modify those values to ones nearest the
869 * capability of the hardware
870 */
871 static void i810_round_off(struct fb_var_screeninfo *var)
872 {
873 u32 xres, yres, vxres, vyres;
874
875 /*
876 * Presently supports only these configurations
877 */
878
879 xres = var->xres;
880 yres = var->yres;
881 vxres = var->xres_virtual;
882 vyres = var->yres_virtual;
883
884 var->bits_per_pixel += 7;
885 var->bits_per_pixel &= ~7;
886
887 if (var->bits_per_pixel < 8)
888 var->bits_per_pixel = 8;
889 if (var->bits_per_pixel > 32)
890 var->bits_per_pixel = 32;
891
892 round_off_xres(&xres);
893 if (xres < 40)
894 xres = 40;
895 if (xres > 2048)
896 xres = 2048;
897 xres = (xres + 7) & ~7;
898
899 if (vxres < xres)
900 vxres = xres;
901
902 round_off_yres(&xres, &yres);
903 if (yres < 1)
904 yres = 1;
905 if (yres >= 2048)
906 yres = 2048;
907
908 if (vyres < yres)
909 vyres = yres;
910
911 if (var->bits_per_pixel == 32)
912 var->accel_flags = 0;
913
914 /* round of horizontal timings to nearest 8 pixels */
915 var->left_margin = (var->left_margin + 4) & ~7;
916 var->right_margin = (var->right_margin + 4) & ~7;
917 var->hsync_len = (var->hsync_len + 4) & ~7;
918
919 if (var->vmode & FB_VMODE_INTERLACED) {
920 if (!((yres + var->upper_margin + var->vsync_len +
921 var->lower_margin) & 1))
922 var->upper_margin++;
923 }
924
925 var->xres = xres;
926 var->yres = yres;
927 var->xres_virtual = vxres;
928 var->yres_virtual = vyres;
929 }
930
931 /**
932 * set_color_bitfields - sets rgba fields
933 * @var: pointer to fb_var_screeninfo
934 *
935 * DESCRIPTION:
936 * The length, offset and ordering for each color field
937 * (red, green, blue) will be set as specified
938 * by the hardware
939 */
940 static void set_color_bitfields(struct fb_var_screeninfo *var)
941 {
942 switch (var->bits_per_pixel) {
943 case 8:
944 var->red.offset = 0;
945 var->red.length = 8;
946 var->green.offset = 0;
947 var->green.length = 8;
948 var->blue.offset = 0;
949 var->blue.length = 8;
950 var->transp.offset = 0;
951 var->transp.length = 0;
952 break;
953 case 16:
954 var->green.length = (var->green.length == 5) ? 5 : 6;
955 var->red.length = 5;
956 var->blue.length = 5;
957 var->transp.length = 6 - var->green.length;
958 var->blue.offset = 0;
959 var->green.offset = 5;
960 var->red.offset = 5 + var->green.length;
961 var->transp.offset = (5 + var->red.offset) & 15;
962 break;
963 case 24: /* RGB 888 */
964 case 32: /* RGBA 8888 */
965 var->red.offset = 16;
966 var->red.length = 8;
967 var->green.offset = 8;
968 var->green.length = 8;
969 var->blue.offset = 0;
970 var->blue.length = 8;
971 var->transp.length = var->bits_per_pixel - 24;
972 var->transp.offset = (var->transp.length) ? 24 : 0;
973 break;
974 }
975 var->red.msb_right = 0;
976 var->green.msb_right = 0;
977 var->blue.msb_right = 0;
978 var->transp.msb_right = 0;
979 }
980
981 /**
982 * i810_check_params - check if contents in var are valid
983 * @var: pointer to fb_var_screeninfo
984 * @info: pointer to fb_info
985 *
986 * DESCRIPTION:
987 * This will check if the framebuffer size is sufficient
988 * for the current mode and if the user's monitor has the
989 * required specifications to display the current mode.
990 */
991 static int i810_check_params(struct fb_var_screeninfo *var,
992 struct fb_info *info)
993 {
994 struct i810fb_par *par = info->par;
995 int line_length, vidmem, mode_valid = 0, retval = 0;
996 u32 vyres = var->yres_virtual, vxres = var->xres_virtual;
997 /*
998 * Memory limit
999 */
1000 line_length = get_line_length(par, vxres, var->bits_per_pixel);
1001 vidmem = line_length*vyres;
1002
1003 if (vidmem > par->fb.size) {
1004 vyres = par->fb.size/line_length;
1005 if (vyres < var->yres) {
1006 vyres = yres;
1007 vxres = par->fb.size/vyres;
1008 vxres /= var->bits_per_pixel >> 3;
1009 line_length = get_line_length(par, vxres,
1010 var->bits_per_pixel);
1011 vidmem = line_length * yres;
1012 if (vxres < var->xres) {
1013 printk("i810fb: required video memory, "
1014 "%d bytes, for %dx%d-%d (virtual) "
1015 "is out of range\n",
1016 vidmem, vxres, vyres,
1017 var->bits_per_pixel);
1018 return -ENOMEM;
1019 }
1020 }
1021 }
1022
1023 var->xres_virtual = vxres;
1024 var->yres_virtual = vyres;
1025
1026 /*
1027 * Monitor limit
1028 */
1029 switch (var->bits_per_pixel) {
1030 case 8:
1031 info->monspecs.dclkmax = 234000000;
1032 break;
1033 case 16:
1034 info->monspecs.dclkmax = 229000000;
1035 break;
1036 case 24:
1037 case 32:
1038 info->monspecs.dclkmax = 204000000;
1039 break;
1040 }
1041
1042 info->monspecs.dclkmin = 15000000;
1043
1044 if (!fb_validate_mode(var, info))
1045 mode_valid = 1;
1046
1047 #ifdef CONFIG_FB_I810_I2C
1048 if (!mode_valid && info->monspecs.gtf &&
1049 !fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1050 mode_valid = 1;
1051
1052 if (!mode_valid && info->monspecs.modedb_len) {
1053 struct fb_videomode *mode;
1054
1055 mode = fb_find_best_mode(var, &info->modelist);
1056 if (mode) {
1057 fb_videomode_to_var(var, mode);
1058 mode_valid = 1;
1059 }
1060 }
1061 #endif
1062 if (!mode_valid && info->monspecs.modedb_len == 0) {
1063 if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) {
1064 int default_sync = (info->monspecs.hfmin-HFMIN)
1065 |(info->monspecs.hfmax-HFMAX)
1066 |(info->monspecs.vfmin-VFMIN)
1067 |(info->monspecs.vfmax-VFMAX);
1068 printk("i810fb: invalid video mode%s\n",
1069 default_sync ? "" : ". Specifying "
1070 "vsyncN/hsyncN parameters may help");
1071 retval = -EINVAL;
1072 }
1073 }
1074
1075 return retval;
1076 }
1077
1078 /**
1079 * encode_fix - fill up fb_fix_screeninfo structure
1080 * @fix: pointer to fb_fix_screeninfo
1081 * @info: pointer to fb_info
1082 *
1083 * DESCRIPTION:
1084 * This will set up parameters that are unmodifiable by the user.
1085 */
1086 static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
1087 {
1088 struct i810fb_par *par = info->par;
1089
1090 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1091
1092 strcpy(fix->id, "I810");
1093 fix->smem_start = par->fb.physical;
1094 fix->smem_len = par->fb.size;
1095 fix->type = FB_TYPE_PACKED_PIXELS;
1096 fix->type_aux = 0;
1097 fix->xpanstep = 8;
1098 fix->ypanstep = 1;
1099
1100 switch (info->var.bits_per_pixel) {
1101 case 8:
1102 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1103 break;
1104 case 16:
1105 case 24:
1106 case 32:
1107 if (info->var.nonstd)
1108 fix->visual = FB_VISUAL_DIRECTCOLOR;
1109 else
1110 fix->visual = FB_VISUAL_TRUECOLOR;
1111 break;
1112 default:
1113 return -EINVAL;
1114 }
1115 fix->ywrapstep = 0;
1116 fix->line_length = par->pitch;
1117 fix->mmio_start = par->mmio_start_phys;
1118 fix->mmio_len = MMIO_SIZE;
1119 fix->accel = FB_ACCEL_I810;
1120
1121 return 0;
1122 }
1123
1124 /**
1125 * decode_var - modify par according to contents of var
1126 * @var: pointer to fb_var_screeninfo
1127 * @par: pointer to i810fb_par
1128 *
1129 * DESCRIPTION:
1130 * Based on the contents of @var, @par will be dynamically filled up.
1131 * @par contains all information necessary to modify the hardware.
1132 */
1133 static void decode_var(const struct fb_var_screeninfo *var,
1134 struct i810fb_par *par)
1135 {
1136 u32 xres, yres, vxres, vyres;
1137
1138 xres = var->xres;
1139 yres = var->yres;
1140 vxres = var->xres_virtual;
1141 vyres = var->yres_virtual;
1142
1143 switch (var->bits_per_pixel) {
1144 case 8:
1145 par->pixconf = PIXCONF8;
1146 par->bltcntl = 0;
1147 par->depth = 1;
1148 par->blit_bpp = BPP8;
1149 break;
1150 case 16:
1151 if (var->green.length == 5)
1152 par->pixconf = PIXCONF15;
1153 else
1154 par->pixconf = PIXCONF16;
1155 par->bltcntl = 16;
1156 par->depth = 2;
1157 par->blit_bpp = BPP16;
1158 break;
1159 case 24:
1160 par->pixconf = PIXCONF24;
1161 par->bltcntl = 32;
1162 par->depth = 3;
1163 par->blit_bpp = BPP24;
1164 break;
1165 case 32:
1166 par->pixconf = PIXCONF32;
1167 par->bltcntl = 0;
1168 par->depth = 4;
1169 par->blit_bpp = 3 << 24;
1170 break;
1171 }
1172 if (var->nonstd && var->bits_per_pixel != 8)
1173 par->pixconf |= 1 << 27;
1174
1175 i810_calc_dclk(var->pixclock, &par->regs.M,
1176 &par->regs.N, &par->regs.P);
1177 i810fb_encode_registers(var, par, xres, yres);
1178
1179 par->watermark = i810_get_watermark(var, par);
1180 par->pitch = get_line_length(par, vxres, var->bits_per_pixel);
1181 }
1182
1183 /**
1184 * i810fb_getcolreg - gets red, green and blue values of the hardware DAC
1185 * @regno: DAC index
1186 * @red: red
1187 * @green: green
1188 * @blue: blue
1189 * @transp: transparency (alpha)
1190 * @info: pointer to fb_info
1191 *
1192 * DESCRIPTION:
1193 * Gets the red, green and blue values of the hardware DAC as pointed by @regno
1194 * and writes them to @red, @green and @blue respectively
1195 */
1196 static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue,
1197 u8 *transp, struct fb_info *info)
1198 {
1199 struct i810fb_par *par = info->par;
1200 u8 __iomem *mmio = par->mmio_start_virtual;
1201 u8 temp;
1202
1203 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1204 if ((info->var.green.length == 5 && regno > 31) ||
1205 (info->var.green.length == 6 && regno > 63))
1206 return 1;
1207 }
1208
1209 temp = i810_readb(PIXCONF1, mmio);
1210 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1211
1212 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1213 info->var.green.length == 5)
1214 i810_read_dac(regno * 8, red, green, blue, mmio);
1215
1216 else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1217 info->var.green.length == 6) {
1218 u8 tmp;
1219
1220 i810_read_dac(regno * 8, red, &tmp, blue, mmio);
1221 i810_read_dac(regno * 4, &tmp, green, &tmp, mmio);
1222 }
1223 else
1224 i810_read_dac(regno, red, green, blue, mmio);
1225
1226 *transp = 0;
1227 i810_writeb(PIXCONF1, mmio, temp);
1228
1229 return 0;
1230 }
1231
1232 /******************************************************************
1233 * Framebuffer device-specific hooks *
1234 ******************************************************************/
1235
1236 static int i810fb_open(struct fb_info *info, int user)
1237 {
1238 struct i810fb_par *par = info->par;
1239 u32 count = atomic_read(&par->use_count);
1240
1241 if (count == 0) {
1242 memset(&par->state, 0, sizeof(struct vgastate));
1243 par->state.flags = VGA_SAVE_CMAP;
1244 par->state.vgabase = par->mmio_start_virtual;
1245 save_vga(&par->state);
1246
1247 i810_save_vga_state(par);
1248 }
1249
1250 atomic_inc(&par->use_count);
1251
1252 return 0;
1253 }
1254
1255 static int i810fb_release(struct fb_info *info, int user)
1256 {
1257 struct i810fb_par *par = info->par;
1258 u32 count;
1259
1260 count = atomic_read(&par->use_count);
1261 if (count == 0)
1262 return -EINVAL;
1263
1264 if (count == 1) {
1265 i810_restore_vga_state(par);
1266 restore_vga(&par->state);
1267 }
1268
1269 atomic_dec(&par->use_count);
1270
1271 return 0;
1272 }
1273
1274
1275 static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1276 unsigned blue, unsigned transp,
1277 struct fb_info *info)
1278 {
1279 struct i810fb_par *par = info->par;
1280 u8 __iomem *mmio = par->mmio_start_virtual;
1281 u8 temp;
1282 int i;
1283
1284 if (regno > 255) return 1;
1285
1286 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1287 if ((info->var.green.length == 5 && regno > 31) ||
1288 (info->var.green.length == 6 && regno > 63))
1289 return 1;
1290 }
1291
1292 if (info->var.grayscale)
1293 red = green = blue = (19595 * red + 38470 * green +
1294 7471 * blue) >> 16;
1295
1296 temp = i810_readb(PIXCONF1, mmio);
1297 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1298
1299 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1300 info->var.green.length == 5) {
1301 for (i = 0; i < 8; i++)
1302 i810_write_dac((u8) (regno * 8) + i, (u8) red,
1303 (u8) green, (u8) blue, mmio);
1304 } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1305 info->var.green.length == 6) {
1306 u8 r, g, b;
1307
1308 if (regno < 32) {
1309 for (i = 0; i < 8; i++)
1310 i810_write_dac((u8) (regno * 8) + i,
1311 (u8) red, (u8) green,
1312 (u8) blue, mmio);
1313 }
1314 i810_read_dac((u8) (regno*4), &r, &g, &b, mmio);
1315 for (i = 0; i < 4; i++)
1316 i810_write_dac((u8) (regno*4) + i, r, (u8) green,
1317 b, mmio);
1318 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
1319 i810_write_dac((u8) regno, (u8) red, (u8) green,
1320 (u8) blue, mmio);
1321 }
1322
1323 i810_writeb(PIXCONF1, mmio, temp);
1324
1325 if (regno < 16) {
1326 switch (info->var.bits_per_pixel) {
1327 case 16:
1328 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1329 if (info->var.green.length == 5)
1330 ((u32 *)info->pseudo_palette)[regno] =
1331 (regno << 10) | (regno << 5) |
1332 regno;
1333 else
1334 ((u32 *)info->pseudo_palette)[regno] =
1335 (regno << 11) | (regno << 5) |
1336 regno;
1337 } else {
1338 if (info->var.green.length == 5) {
1339 /* RGB 555 */
1340 ((u32 *)info->pseudo_palette)[regno] =
1341 ((red & 0xf800) >> 1) |
1342 ((green & 0xf800) >> 6) |
1343 ((blue & 0xf800) >> 11);
1344 } else {
1345 /* RGB 565 */
1346 ((u32 *)info->pseudo_palette)[regno] =
1347 (red & 0xf800) |
1348 ((green & 0xf800) >> 5) |
1349 ((blue & 0xf800) >> 11);
1350 }
1351 }
1352 break;
1353 case 24: /* RGB 888 */
1354 case 32: /* RGBA 8888 */
1355 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
1356 ((u32 *)info->pseudo_palette)[regno] =
1357 (regno << 16) | (regno << 8) |
1358 regno;
1359 else
1360 ((u32 *)info->pseudo_palette)[regno] =
1361 ((red & 0xff00) << 8) |
1362 (green & 0xff00) |
1363 ((blue & 0xff00) >> 8);
1364 break;
1365 }
1366 }
1367 return 0;
1368 }
1369
1370 static int i810fb_pan_display(struct fb_var_screeninfo *var,
1371 struct fb_info *info)
1372 {
1373 struct i810fb_par *par = info->par;
1374 u32 total;
1375
1376 total = var->xoffset * par->depth +
1377 var->yoffset * info->fix.line_length;
1378 i810fb_load_front(total, info);
1379
1380 return 0;
1381 }
1382
1383 static int i810fb_blank (int blank_mode, struct fb_info *info)
1384 {
1385 struct i810fb_par *par = info->par;
1386 u8 __iomem *mmio = par->mmio_start_virtual;
1387 int mode = 0, pwr, scr_off = 0;
1388
1389 pwr = i810_readl(PWR_CLKC, mmio);
1390
1391 switch (blank_mode) {
1392 case FB_BLANK_UNBLANK:
1393 mode = POWERON;
1394 pwr |= 1;
1395 scr_off = ON;
1396 break;
1397 case FB_BLANK_NORMAL:
1398 mode = POWERON;
1399 pwr |= 1;
1400 scr_off = OFF;
1401 break;
1402 case FB_BLANK_VSYNC_SUSPEND:
1403 mode = STANDBY;
1404 pwr |= 1;
1405 scr_off = OFF;
1406 break;
1407 case FB_BLANK_HSYNC_SUSPEND:
1408 mode = SUSPEND;
1409 pwr |= 1;
1410 scr_off = OFF;
1411 break;
1412 case FB_BLANK_POWERDOWN:
1413 mode = POWERDOWN;
1414 pwr &= ~1;
1415 scr_off = OFF;
1416 break;
1417 default:
1418 return -EINVAL;
1419 }
1420
1421 i810_screen_off(mmio, scr_off);
1422 i810_writel(HVSYNC, mmio, mode);
1423 i810_writel(PWR_CLKC, mmio, pwr);
1424
1425 return 0;
1426 }
1427
1428 static int i810fb_set_par(struct fb_info *info)
1429 {
1430 struct i810fb_par *par = info->par;
1431
1432 decode_var(&info->var, par);
1433 i810_load_regs(par);
1434 i810_init_cursor(par);
1435 encode_fix(&info->fix, info);
1436
1437 if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) {
1438 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
1439 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
1440 FBINFO_HWACCEL_IMAGEBLIT;
1441 info->pixmap.scan_align = 2;
1442 } else {
1443 info->pixmap.scan_align = 1;
1444 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1445 }
1446 return 0;
1447 }
1448
1449 static int i810fb_check_var(struct fb_var_screeninfo *var,
1450 struct fb_info *info)
1451 {
1452 int err;
1453
1454 if (IS_DVT) {
1455 var->vmode &= ~FB_VMODE_MASK;
1456 var->vmode |= FB_VMODE_NONINTERLACED;
1457 }
1458 if (var->vmode & FB_VMODE_DOUBLE) {
1459 var->vmode &= ~FB_VMODE_MASK;
1460 var->vmode |= FB_VMODE_NONINTERLACED;
1461 }
1462
1463 i810_round_off(var);
1464 if ((err = i810_check_params(var, info)))
1465 return err;
1466
1467 i810fb_fill_var_timings(var);
1468 set_color_bitfields(var);
1469 return 0;
1470 }
1471
1472 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1473 {
1474 struct i810fb_par *par = info->par;
1475 u8 __iomem *mmio = par->mmio_start_virtual;
1476
1477 if (!par->dev_flags & LOCKUP)
1478 return -ENXIO;
1479
1480 if (cursor->image.width > 64 || cursor->image.height > 64)
1481 return -ENXIO;
1482
1483 if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) {
1484 i810_init_cursor(par);
1485 cursor->set |= FB_CUR_SETALL;
1486 }
1487
1488 i810_enable_cursor(mmio, OFF);
1489
1490 if (cursor->set & FB_CUR_SETPOS) {
1491 u32 tmp;
1492
1493 tmp = (cursor->image.dx - info->var.xoffset) & 0xffff;
1494 tmp |= (cursor->image.dy - info->var.yoffset) << 16;
1495 i810_writel(CURPOS, mmio, tmp);
1496 }
1497
1498 if (cursor->set & FB_CUR_SETSIZE)
1499 i810_reset_cursor_image(par);
1500
1501 if (cursor->set & FB_CUR_SETCMAP)
1502 i810_load_cursor_colors(cursor->image.fg_color,
1503 cursor->image.bg_color,
1504 info);
1505
1506 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1507 int size = ((cursor->image.width + 7) >> 3) *
1508 cursor->image.height;
1509 int i;
1510 u8 *data = kmalloc(64 * 8, GFP_KERNEL);
1511
1512 if (data == NULL)
1513 return -ENOMEM;
1514
1515 switch (cursor->rop) {
1516 case ROP_XOR:
1517 for (i = 0; i < size; i++)
1518 data[i] = cursor->image.data[i] ^ cursor->mask[i];
1519 break;
1520 case ROP_COPY:
1521 default:
1522 for (i = 0; i < size; i++)
1523 data[i] = cursor->image.data[i] & cursor->mask[i];
1524 break;
1525 }
1526
1527 i810_load_cursor_image(cursor->image.width,
1528 cursor->image.height, data,
1529 par);
1530 kfree(data);
1531 }
1532
1533 if (cursor->enable)
1534 i810_enable_cursor(mmio, ON);
1535
1536 return 0;
1537 }
1538
1539 static struct fb_ops i810fb_ops __devinitdata = {
1540 .owner = THIS_MODULE,
1541 .fb_open = i810fb_open,
1542 .fb_release = i810fb_release,
1543 .fb_check_var = i810fb_check_var,
1544 .fb_set_par = i810fb_set_par,
1545 .fb_setcolreg = i810fb_setcolreg,
1546 .fb_blank = i810fb_blank,
1547 .fb_pan_display = i810fb_pan_display,
1548 .fb_fillrect = i810fb_fillrect,
1549 .fb_copyarea = i810fb_copyarea,
1550 .fb_imageblit = i810fb_imageblit,
1551 .fb_cursor = i810fb_cursor,
1552 .fb_sync = i810fb_sync,
1553 };
1554
1555 /***********************************************************************
1556 * Power Management *
1557 ***********************************************************************/
1558 static int i810fb_suspend(struct pci_dev *dev, pm_message_t state)
1559 {
1560 struct fb_info *info = pci_get_drvdata(dev);
1561 struct i810fb_par *par = info->par;
1562
1563 par->cur_state = state.event;
1564
1565 if (state.event == PM_EVENT_FREEZE) {
1566 dev->dev.power.power_state = state;
1567 return 0;
1568 }
1569
1570 acquire_console_sem();
1571 fb_set_suspend(info, 1);
1572
1573 if (info->fbops->fb_sync)
1574 info->fbops->fb_sync(info);
1575
1576 i810fb_blank(FB_BLANK_POWERDOWN, info);
1577 agp_unbind_memory(par->i810_gtt.i810_fb_memory);
1578 agp_unbind_memory(par->i810_gtt.i810_cursor_memory);
1579
1580 pci_save_state(dev);
1581 pci_disable_device(dev);
1582 pci_set_power_state(dev, pci_choose_state(dev, state));
1583 release_console_sem();
1584
1585 return 0;
1586 }
1587
1588 static int i810fb_resume(struct pci_dev *dev)
1589 {
1590 struct fb_info *info = pci_get_drvdata(dev);
1591 struct i810fb_par *par = info->par;
1592 int cur_state = par->cur_state;
1593
1594 par->cur_state = PM_EVENT_ON;
1595
1596 if (cur_state == PM_EVENT_FREEZE) {
1597 pci_set_power_state(dev, PCI_D0);
1598 return 0;
1599 }
1600
1601 acquire_console_sem();
1602 pci_set_power_state(dev, PCI_D0);
1603 pci_restore_state(dev);
1604 pci_enable_device(dev);
1605 pci_set_master(dev);
1606 agp_bind_memory(par->i810_gtt.i810_fb_memory,
1607 par->fb.offset);
1608 agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1609 par->cursor_heap.offset);
1610 i810fb_set_par(info);
1611 fb_set_suspend (info, 0);
1612 info->fbops->fb_blank(VESA_NO_BLANKING, info);
1613 release_console_sem();
1614 return 0;
1615 }
1616 /***********************************************************************
1617 * AGP resource allocation *
1618 ***********************************************************************/
1619
1620 static void __devinit i810_fix_pointers(struct i810fb_par *par)
1621 {
1622 par->fb.physical = par->aperture.physical+(par->fb.offset << 12);
1623 par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12);
1624 par->iring.physical = par->aperture.physical +
1625 (par->iring.offset << 12);
1626 par->iring.virtual = par->aperture.virtual +
1627 (par->iring.offset << 12);
1628 par->cursor_heap.virtual = par->aperture.virtual+
1629 (par->cursor_heap.offset << 12);
1630 }
1631
1632 static void __devinit i810_fix_offsets(struct i810fb_par *par)
1633 {
1634 if (vram + 1 > par->aperture.size >> 20)
1635 vram = (par->aperture.size >> 20) - 1;
1636 if (v_offset_default > (par->aperture.size >> 20))
1637 v_offset_default = (par->aperture.size >> 20);
1638 if (vram + v_offset_default + 1 > par->aperture.size >> 20)
1639 v_offset_default = (par->aperture.size >> 20) - (vram + 1);
1640
1641 par->fb.size = vram << 20;
1642 par->fb.offset = v_offset_default << 20;
1643 par->fb.offset >>= 12;
1644
1645 par->iring.offset = par->fb.offset + (par->fb.size >> 12);
1646 par->iring.size = RINGBUFFER_SIZE;
1647
1648 par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12);
1649 par->cursor_heap.size = 4096;
1650 }
1651
1652 static int __devinit i810_alloc_agp_mem(struct fb_info *info)
1653 {
1654 struct i810fb_par *par = info->par;
1655 int size;
1656 struct agp_bridge_data *bridge;
1657
1658 i810_fix_offsets(par);
1659 size = par->fb.size + par->iring.size;
1660
1661 if (!(bridge = agp_backend_acquire(par->dev))) {
1662 printk("i810fb_alloc_fbmem: cannot acquire agpgart\n");
1663 return -ENODEV;
1664 }
1665 if (!(par->i810_gtt.i810_fb_memory =
1666 agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) {
1667 printk("i810fb_alloc_fbmem: can't allocate framebuffer "
1668 "memory\n");
1669 agp_backend_release(bridge);
1670 return -ENOMEM;
1671 }
1672 if (agp_bind_memory(par->i810_gtt.i810_fb_memory,
1673 par->fb.offset)) {
1674 printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n");
1675 agp_backend_release(bridge);
1676 return -EBUSY;
1677 }
1678
1679 if (!(par->i810_gtt.i810_cursor_memory =
1680 agp_allocate_memory(bridge, par->cursor_heap.size >> 12,
1681 AGP_PHYSICAL_MEMORY))) {
1682 printk("i810fb_alloc_cursormem: can't allocate"
1683 "cursor memory\n");
1684 agp_backend_release(bridge);
1685 return -ENOMEM;
1686 }
1687 if (agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1688 par->cursor_heap.offset)) {
1689 printk("i810fb_alloc_cursormem: cannot bind cursor memory\n");
1690 agp_backend_release(bridge);
1691 return -EBUSY;
1692 }
1693
1694 par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical;
1695
1696 i810_fix_pointers(par);
1697
1698 agp_backend_release(bridge);
1699
1700 return 0;
1701 }
1702
1703 /***************************************************************
1704 * Initialization *
1705 ***************************************************************/
1706
1707 /**
1708 * i810_init_monspecs
1709 * @info: pointer to device specific info structure
1710 *
1711 * DESCRIPTION:
1712 * Sets the the user monitor's horizontal and vertical
1713 * frequency limits
1714 */
1715 static void __devinit i810_init_monspecs(struct fb_info *info)
1716 {
1717 if (!hsync1)
1718 hsync1 = HFMIN;
1719 if (!hsync2)
1720 hsync2 = HFMAX;
1721 if (!info->monspecs.hfmax)
1722 info->monspecs.hfmax = hsync2;
1723 if (!info->monspecs.hfmin)
1724 info->monspecs.hfmin = hsync1;
1725 if (hsync2 < hsync1)
1726 info->monspecs.hfmin = hsync2;
1727
1728 if (!vsync1)
1729 vsync1 = VFMIN;
1730 if (!vsync2)
1731 vsync2 = VFMAX;
1732 if (IS_DVT && vsync1 < 60)
1733 vsync1 = 60;
1734 if (!info->monspecs.vfmax)
1735 info->monspecs.vfmax = vsync2;
1736 if (!info->monspecs.vfmin)
1737 info->monspecs.vfmin = vsync1;
1738 if (vsync2 < vsync1)
1739 info->monspecs.vfmin = vsync2;
1740 }
1741
1742 /**
1743 * i810_init_defaults - initializes default values to use
1744 * @par: pointer to i810fb_par structure
1745 * @info: pointer to current fb_info structure
1746 */
1747 static void __devinit i810_init_defaults(struct i810fb_par *par,
1748 struct fb_info *info)
1749 {
1750 if (voffset)
1751 v_offset_default = voffset;
1752 else if (par->aperture.size > 32 * 1024 * 1024)
1753 v_offset_default = 16;
1754 else
1755 v_offset_default = 8;
1756
1757 if (!vram)
1758 vram = 1;
1759
1760 if (accel)
1761 par->dev_flags |= HAS_ACCELERATION;
1762
1763 if (sync)
1764 par->dev_flags |= ALWAYS_SYNC;
1765
1766 if (bpp < 8)
1767 bpp = 8;
1768
1769 par->i810fb_ops = i810fb_ops;
1770
1771 if (xres)
1772 info->var.xres = xres;
1773 else
1774 info->var.xres = 640;
1775
1776 if (yres)
1777 info->var.yres = yres;
1778 else
1779 info->var.yres = 480;
1780
1781 if (!vyres)
1782 vyres = (vram << 20)/(info->var.xres*bpp >> 3);
1783
1784 info->var.yres_virtual = vyres;
1785 info->var.bits_per_pixel = bpp;
1786
1787 if (dcolor)
1788 info->var.nonstd = 1;
1789
1790 if (par->dev_flags & HAS_ACCELERATION)
1791 info->var.accel_flags = 1;
1792
1793 i810_init_monspecs(info);
1794 }
1795
1796 /**
1797 * i810_init_device - initialize device
1798 * @par: pointer to i810fb_par structure
1799 */
1800 static void __devinit i810_init_device(struct i810fb_par *par)
1801 {
1802 u8 reg;
1803 u8 __iomem *mmio = par->mmio_start_virtual;
1804
1805 if (mtrr) set_mtrr(par);
1806
1807 i810_init_cursor(par);
1808
1809 /* mvo: enable external vga-connector (for laptops) */
1810 if (extvga) {
1811 i810_writel(HVSYNC, mmio, 0);
1812 i810_writel(PWR_CLKC, mmio, 3);
1813 }
1814
1815 pci_read_config_byte(par->dev, 0x50, &reg);
1816 reg &= FREQ_MASK;
1817 par->mem_freq = (reg) ? 133 : 100;
1818
1819 }
1820
1821 static int __devinit
1822 i810_allocate_pci_resource(struct i810fb_par *par,
1823 const struct pci_device_id *entry)
1824 {
1825 int err;
1826
1827 if ((err = pci_enable_device(par->dev))) {
1828 printk("i810fb_init: cannot enable device\n");
1829 return err;
1830 }
1831 par->res_flags |= PCI_DEVICE_ENABLED;
1832
1833 if (pci_resource_len(par->dev, 0) > 512 * 1024) {
1834 par->aperture.physical = pci_resource_start(par->dev, 0);
1835 par->aperture.size = pci_resource_len(par->dev, 0);
1836 par->mmio_start_phys = pci_resource_start(par->dev, 1);
1837 } else {
1838 par->aperture.physical = pci_resource_start(par->dev, 1);
1839 par->aperture.size = pci_resource_len(par->dev, 1);
1840 par->mmio_start_phys = pci_resource_start(par->dev, 0);
1841 }
1842 if (!par->aperture.size) {
1843 printk("i810fb_init: device is disabled\n");
1844 return -ENOMEM;
1845 }
1846
1847 if (!request_mem_region(par->aperture.physical,
1848 par->aperture.size,
1849 i810_pci_list[entry->driver_data])) {
1850 printk("i810fb_init: cannot request framebuffer region\n");
1851 return -ENODEV;
1852 }
1853 par->res_flags |= FRAMEBUFFER_REQ;
1854
1855 par->aperture.virtual = ioremap_nocache(par->aperture.physical,
1856 par->aperture.size);
1857 if (!par->aperture.virtual) {
1858 printk("i810fb_init: cannot remap framebuffer region\n");
1859 return -ENODEV;
1860 }
1861
1862 if (!request_mem_region(par->mmio_start_phys,
1863 MMIO_SIZE,
1864 i810_pci_list[entry->driver_data])) {
1865 printk("i810fb_init: cannot request mmio region\n");
1866 return -ENODEV;
1867 }
1868 par->res_flags |= MMIO_REQ;
1869
1870 par->mmio_start_virtual = ioremap_nocache(par->mmio_start_phys,
1871 MMIO_SIZE);
1872 if (!par->mmio_start_virtual) {
1873 printk("i810fb_init: cannot remap mmio region\n");
1874 return -ENODEV;
1875 }
1876
1877 return 0;
1878 }
1879
1880 static void __devinit i810fb_find_init_mode(struct fb_info *info)
1881 {
1882 struct fb_videomode mode;
1883 struct fb_var_screeninfo var;
1884 struct fb_monspecs *specs = &info->monspecs;
1885 int found = 0;
1886 #ifdef CONFIG_FB_I810_I2C
1887 int i;
1888 int err;
1889 struct i810fb_par *par = info->par;
1890 #endif
1891
1892 INIT_LIST_HEAD(&info->modelist);
1893 memset(&mode, 0, sizeof(struct fb_videomode));
1894 var = info->var;
1895 #ifdef CONFIG_FB_I810_I2C
1896 i810_create_i2c_busses(par);
1897
1898 for (i = 0; i < 4; i++) {
1899 err = i810_probe_i2c_connector(info, &par->edid, i+1);
1900 if (!err)
1901 break;
1902 }
1903
1904 if (!err)
1905 printk("i810fb_init_pci: DDC probe successful\n");
1906
1907 fb_edid_to_monspecs(par->edid, specs);
1908
1909 if (specs->modedb == NULL)
1910 printk("i810fb_init_pci: Unable to get Mode Database\n");
1911
1912 fb_videomode_to_modelist(specs->modedb, specs->modedb_len,
1913 &info->modelist);
1914 if (specs->modedb != NULL) {
1915 struct fb_videomode *m;
1916
1917 if (xres && yres) {
1918 if ((m = fb_find_best_mode(&var, &info->modelist))) {
1919 mode = *m;
1920 found = 1;
1921 }
1922 }
1923
1924 if (!found) {
1925 m = fb_find_best_display(&info->monspecs, &info->modelist);
1926 mode = *m;
1927 found = 1;
1928 }
1929
1930 fb_videomode_to_var(&var, &mode);
1931 }
1932 #endif
1933 if (mode_option)
1934 fb_find_mode(&var, info, mode_option, specs->modedb,
1935 specs->modedb_len, (found) ? &mode : NULL,
1936 info->var.bits_per_pixel);
1937
1938 info->var = var;
1939 fb_destroy_modedb(specs->modedb);
1940 specs->modedb = NULL;
1941 }
1942
1943 #ifndef MODULE
1944 static int __devinit i810fb_setup(char *options)
1945 {
1946 char *this_opt, *suffix = NULL;
1947
1948 if (!options || !*options)
1949 return 0;
1950
1951 while ((this_opt = strsep(&options, ",")) != NULL) {
1952 if (!strncmp(this_opt, "mtrr", 4))
1953 mtrr = 1;
1954 else if (!strncmp(this_opt, "accel", 5))
1955 accel = 1;
1956 else if (!strncmp(this_opt, "extvga", 6))
1957 extvga = 1;
1958 else if (!strncmp(this_opt, "sync", 4))
1959 sync = 1;
1960 else if (!strncmp(this_opt, "vram:", 5))
1961 vram = (simple_strtoul(this_opt+5, NULL, 0));
1962 else if (!strncmp(this_opt, "voffset:", 8))
1963 voffset = (simple_strtoul(this_opt+8, NULL, 0));
1964 else if (!strncmp(this_opt, "xres:", 5))
1965 xres = simple_strtoul(this_opt+5, NULL, 0);
1966 else if (!strncmp(this_opt, "yres:", 5))
1967 yres = simple_strtoul(this_opt+5, NULL, 0);
1968 else if (!strncmp(this_opt, "vyres:", 6))
1969 vyres = simple_strtoul(this_opt+6, NULL, 0);
1970 else if (!strncmp(this_opt, "bpp:", 4))
1971 bpp = simple_strtoul(this_opt+4, NULL, 0);
1972 else if (!strncmp(this_opt, "hsync1:", 7)) {
1973 hsync1 = simple_strtoul(this_opt+7, &suffix, 0);
1974 if (strncmp(suffix, "H", 1))
1975 hsync1 *= 1000;
1976 } else if (!strncmp(this_opt, "hsync2:", 7)) {
1977 hsync2 = simple_strtoul(this_opt+7, &suffix, 0);
1978 if (strncmp(suffix, "H", 1))
1979 hsync2 *= 1000;
1980 } else if (!strncmp(this_opt, "vsync1:", 7))
1981 vsync1 = simple_strtoul(this_opt+7, NULL, 0);
1982 else if (!strncmp(this_opt, "vsync2:", 7))
1983 vsync2 = simple_strtoul(this_opt+7, NULL, 0);
1984 else if (!strncmp(this_opt, "dcolor", 6))
1985 dcolor = 1;
1986 else
1987 mode_option = this_opt;
1988 }
1989 return 0;
1990 }
1991 #endif
1992
1993 static int __devinit i810fb_init_pci (struct pci_dev *dev,
1994 const struct pci_device_id *entry)
1995 {
1996 struct fb_info *info;
1997 struct i810fb_par *par = NULL;
1998 struct fb_videomode mode;
1999 int i, err = -1, vfreq, hfreq, pixclock;
2000
2001 i = 0;
2002
2003 info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev);
2004 if (!info)
2005 return -ENOMEM;
2006
2007 par = info->par;
2008 par->dev = dev;
2009
2010 if (!(info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL))) {
2011 i810fb_release_resource(info, par);
2012 return -ENOMEM;
2013 }
2014 memset(info->pixmap.addr, 0, 8*1024);
2015 info->pixmap.size = 8*1024;
2016 info->pixmap.buf_align = 8;
2017 info->pixmap.access_align = 32;
2018 info->pixmap.flags = FB_PIXMAP_SYSTEM;
2019
2020 if ((err = i810_allocate_pci_resource(par, entry))) {
2021 i810fb_release_resource(info, par);
2022 return err;
2023 }
2024
2025 i810_init_defaults(par, info);
2026
2027 if ((err = i810_alloc_agp_mem(info))) {
2028 i810fb_release_resource(info, par);
2029 return err;
2030 }
2031
2032 i810_init_device(par);
2033
2034 info->screen_base = par->fb.virtual;
2035 info->fbops = &par->i810fb_ops;
2036 info->pseudo_palette = par->pseudo_palette;
2037 fb_alloc_cmap(&info->cmap, 256, 0);
2038 i810fb_find_init_mode(info);
2039
2040 if ((err = info->fbops->fb_check_var(&info->var, info))) {
2041 i810fb_release_resource(info, par);
2042 return err;
2043 }
2044
2045 fb_var_to_videomode(&mode, &info->var);
2046 fb_add_videomode(&mode, &info->modelist);
2047 encode_fix(&info->fix, info);
2048
2049 i810fb_init_ringbuffer(info);
2050 err = register_framebuffer(info);
2051
2052 if (err < 0) {
2053 i810fb_release_resource(info, par);
2054 printk("i810fb_init: cannot register framebuffer device\n");
2055 return err;
2056 }
2057
2058 pci_set_drvdata(dev, info);
2059 pixclock = 1000000000/(info->var.pixclock);
2060 pixclock *= 1000;
2061 hfreq = pixclock/(info->var.xres + info->var.left_margin +
2062 info->var.hsync_len + info->var.right_margin);
2063 vfreq = hfreq/(info->var.yres + info->var.upper_margin +
2064 info->var.vsync_len + info->var.lower_margin);
2065
2066 printk("I810FB: fb%d : %s v%d.%d.%d%s\n"
2067 "I810FB: Video RAM : %dK\n"
2068 "I810FB: Monitor : H: %d-%d KHz V: %d-%d Hz\n"
2069 "I810FB: Mode : %dx%d-%dbpp@%dHz\n",
2070 info->node,
2071 i810_pci_list[entry->driver_data],
2072 VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION,
2073 (int) par->fb.size>>10, info->monspecs.hfmin/1000,
2074 info->monspecs.hfmax/1000, info->monspecs.vfmin,
2075 info->monspecs.vfmax, info->var.xres,
2076 info->var.yres, info->var.bits_per_pixel, vfreq);
2077 return 0;
2078 }
2079
2080 /***************************************************************
2081 * De-initialization *
2082 ***************************************************************/
2083
2084 static void i810fb_release_resource(struct fb_info *info,
2085 struct i810fb_par *par)
2086 {
2087 struct gtt_data *gtt = &par->i810_gtt;
2088 unset_mtrr(par);
2089
2090 i810_delete_i2c_busses(par);
2091
2092 if (par->i810_gtt.i810_cursor_memory)
2093 agp_free_memory(gtt->i810_cursor_memory);
2094 if (par->i810_gtt.i810_fb_memory)
2095 agp_free_memory(gtt->i810_fb_memory);
2096
2097 if (par->mmio_start_virtual)
2098 iounmap(par->mmio_start_virtual);
2099 if (par->aperture.virtual)
2100 iounmap(par->aperture.virtual);
2101 kfree(par->edid);
2102 if (par->res_flags & FRAMEBUFFER_REQ)
2103 release_mem_region(par->aperture.physical,
2104 par->aperture.size);
2105 if (par->res_flags & MMIO_REQ)
2106 release_mem_region(par->mmio_start_phys, MMIO_SIZE);
2107
2108 if (par->res_flags & PCI_DEVICE_ENABLED)
2109 pci_disable_device(par->dev);
2110
2111 framebuffer_release(info);
2112
2113 }
2114
2115 static void __exit i810fb_remove_pci(struct pci_dev *dev)
2116 {
2117 struct fb_info *info = pci_get_drvdata(dev);
2118 struct i810fb_par *par = info->par;
2119
2120 unregister_framebuffer(info);
2121 i810fb_release_resource(info, par);
2122 pci_set_drvdata(dev, NULL);
2123 printk("cleanup_module: unloaded i810 framebuffer device\n");
2124 }
2125
2126 #ifndef MODULE
2127 static int __devinit i810fb_init(void)
2128 {
2129 char *option = NULL;
2130
2131 if (fb_get_options("i810fb", &option))
2132 return -ENODEV;
2133 i810fb_setup(option);
2134
2135 return pci_register_driver(&i810fb_driver);
2136 }
2137 #endif
2138
2139 /*********************************************************************
2140 * Modularization *
2141 *********************************************************************/
2142
2143 #ifdef MODULE
2144
2145 static int __devinit i810fb_init(void)
2146 {
2147 hsync1 *= 1000;
2148 hsync2 *= 1000;
2149
2150 return pci_register_driver(&i810fb_driver);
2151 }
2152
2153 module_param(vram, int, 0);
2154 MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB"
2155 " (default=4)");
2156 module_param(voffset, int, 0);
2157 MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer "
2158 "memory (0 to maximum aperture size), in MiB (default = 48)");
2159 module_param(bpp, int, 0);
2160 MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel"
2161 " (default = 8)");
2162 module_param(xres, int, 0);
2163 MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)");
2164 module_param(yres, int, 0);
2165 MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)");
2166 module_param(vyres,int, 0);
2167 MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines"
2168 " (default = 480)");
2169 module_param(hsync1, int, 0);
2170 MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz"
2171 " (default = 29)");
2172 module_param(hsync2, int, 0);
2173 MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz"
2174 " (default = 30)");
2175 module_param(vsync1, int, 0);
2176 MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz"
2177 " (default = 50)");
2178 module_param(vsync2, int, 0);
2179 MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz"
2180 " (default = 60)");
2181 module_param(accel, bool, 0);
2182 MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)");
2183 module_param(mtrr, bool, 0);
2184 MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)");
2185 module_param(extvga, bool, 0);
2186 MODULE_PARM_DESC(extvga, "Enable external VGA connector (default = 0)");
2187 module_param(sync, bool, 0);
2188 MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing"
2189 " (default = 0)");
2190 module_param(dcolor, bool, 0);
2191 MODULE_PARM_DESC(dcolor, "use DirectColor visuals"
2192 " (default = 0 = TrueColor)");
2193 module_param(mode_option, charp, 0);
2194 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
2195
2196 MODULE_AUTHOR("Tony A. Daplas");
2197 MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and"
2198 " compatible cards");
2199 MODULE_LICENSE("GPL");
2200
2201 static void __exit i810fb_exit(void)
2202 {
2203 pci_unregister_driver(&i810fb_driver);
2204 }
2205 module_exit(i810fb_exit);
2206
2207 #endif /* MODULE */
2208
2209 module_init(i810fb_init);
Linux kernel - Deliverables
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