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[PATCH] powerpc: Kill _machine and hard-coded platform numbers
[deliverable/linux.git] / drivers / video / nvidia / nvidia.c
1 /*
2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
3 *
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 *
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
17 #include <linux/mm.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/fb.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #ifdef CONFIG_MTRR
25 #include <asm/mtrr.h>
26 #endif
27 #ifdef CONFIG_PPC_OF
28 #include <asm/prom.h>
29 #include <asm/pci-bridge.h>
30 #endif
31 #ifdef CONFIG_PMAC_BACKLIGHT
32 #include <asm/machdep.h>
33 #include <asm/backlight.h>
34 #endif
35
36 #include "nv_local.h"
37 #include "nv_type.h"
38 #include "nv_proto.h"
39 #include "nv_dma.h"
40
41 #ifndef CONFIG_PCI /* sanity check */
42 #error This driver requires PCI support.
43 #endif
44
45 #undef CONFIG_FB_NVIDIA_DEBUG
46 #ifdef CONFIG_FB_NVIDIA_DEBUG
47 #define NVTRACE printk
48 #else
49 #define NVTRACE if (0) printk
50 #endif
51
52 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
53 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
54
55 #ifdef CONFIG_FB_NVIDIA_DEBUG
56 #define assert(expr) \
57 if (!(expr)) { \
58 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
59 #expr,__FILE__,__FUNCTION__,__LINE__); \
60 BUG(); \
61 }
62 #else
63 #define assert(expr)
64 #endif
65
66 #define PFX "nvidiafb: "
67
68 /* HW cursor parameters */
69 #define MAX_CURS 32
70
71 static struct pci_device_id nvidiafb_pci_tbl[] = {
72 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
74 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
76 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
77 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
78 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
79 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
80 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
81 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
82 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
83 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
84 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
85 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
86 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
87 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
88 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
90 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
91 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
92 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
93 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
94 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
95 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
96 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
97 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
98 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
100 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
102 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
104 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
106 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
108 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
110 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
112 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
114 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
116 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
118 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
120 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
122 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
124 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
126 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
128 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
130 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
132 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
134 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
136 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
138 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
140 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
142 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
144 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
146 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
148 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
150 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
152 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
154 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
156 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
158 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
160 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
162 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
164 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
166 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
168 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
170 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
172 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
174 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
176 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
178 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
180 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
182 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
184 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
186 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
188 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
190 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
192 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
194 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
196 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
198 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
200 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
202 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
204 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
206 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
208 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
210 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
212 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
214 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
216 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
218 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
220 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
222 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
224 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
226 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
228 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
230 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
232 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
234 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
236 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
238 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
240 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
242 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
244 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
246 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
248 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
250 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
252 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
254 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
256 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
258 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
260 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
262 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
264 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
266 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
268 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
270 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
272 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
274 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
276 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
278 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
280 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
282 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
284 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
286 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
288 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
290 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1,
291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
292 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1,
293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
294 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2,
295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
296 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1,
297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
298 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
300 {PCI_VENDOR_ID_NVIDIA, 0x0252,
301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
302 {PCI_VENDOR_ID_NVIDIA, 0x0313,
303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
304 {PCI_VENDOR_ID_NVIDIA, 0x0316,
305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
306 {PCI_VENDOR_ID_NVIDIA, 0x0317,
307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
308 {PCI_VENDOR_ID_NVIDIA, 0x031D,
309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
310 {PCI_VENDOR_ID_NVIDIA, 0x031E,
311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
312 {PCI_VENDOR_ID_NVIDIA, 0x031F,
313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
314 {PCI_VENDOR_ID_NVIDIA, 0x0329,
315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
316 {PCI_VENDOR_ID_NVIDIA, 0x032F,
317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
318 {PCI_VENDOR_ID_NVIDIA, 0x0345,
319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
320 {PCI_VENDOR_ID_NVIDIA, 0x0349,
321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
322 {PCI_VENDOR_ID_NVIDIA, 0x034B,
323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
324 {PCI_VENDOR_ID_NVIDIA, 0x034F,
325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
326 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
328 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
330 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
332 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
334 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
336 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
338 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
340 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
342 {PCI_VENDOR_ID_NVIDIA, 0x0142,
343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
344 {PCI_VENDOR_ID_NVIDIA, 0x0143,
345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
346 {PCI_VENDOR_ID_NVIDIA, 0x0144,
347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
348 {PCI_VENDOR_ID_NVIDIA, 0x0145,
349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
350 {PCI_VENDOR_ID_NVIDIA, 0x0146,
351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
352 {PCI_VENDOR_ID_NVIDIA, 0x0147,
353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
354 {PCI_VENDOR_ID_NVIDIA, 0x0148,
355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
356 {PCI_VENDOR_ID_NVIDIA, 0x0149,
357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
358 {PCI_VENDOR_ID_NVIDIA, 0x014b,
359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
360 {PCI_VENDOR_ID_NVIDIA, 0x14c,
361 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
362 {PCI_VENDOR_ID_NVIDIA, 0x014d,
363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
364 {PCI_VENDOR_ID_NVIDIA, 0x0160,
365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
366 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
367 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
368 {PCI_VENDOR_ID_NVIDIA, 0x0162,
369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
370 {PCI_VENDOR_ID_NVIDIA, 0x0163,
371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
372 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
373 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
374 {PCI_VENDOR_ID_NVIDIA, 0x0165,
375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
376 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
378 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
380 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
382 {PCI_VENDOR_ID_NVIDIA, 0x0169,
383 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
384 {PCI_VENDOR_ID_NVIDIA, 0x016b,
385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
386 {PCI_VENDOR_ID_NVIDIA, 0x016c,
387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
388 {PCI_VENDOR_ID_NVIDIA, 0x016d,
389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
390 {PCI_VENDOR_ID_NVIDIA, 0x016e,
391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
392 {PCI_VENDOR_ID_NVIDIA, 0x0210,
393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
394 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
396 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
398 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
400 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT,
401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
402 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX,
403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
404 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800,
405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
406 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX,
407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
408 {PCI_VENDOR_ID_NVIDIA, 0x021d,
409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
410 {PCI_VENDOR_ID_NVIDIA, 0x021e,
411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
412 {PCI_VENDOR_ID_NVIDIA, 0x0220,
413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
414 {PCI_VENDOR_ID_NVIDIA, 0x0221,
415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
416 {PCI_VENDOR_ID_NVIDIA, 0x0222,
417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
418 {PCI_VENDOR_ID_NVIDIA, 0x0228,
419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
420 {0,} /* terminate list */
421 };
422
423 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
424
425 /* command line data, set in nvidiafb_setup() */
426 static int flatpanel __devinitdata = -1; /* Autodetect later */
427 static int fpdither __devinitdata = -1;
428 static int forceCRTC __devinitdata = -1;
429 static int hwcur __devinitdata = 0;
430 static int noaccel __devinitdata = 0;
431 static int noscale __devinitdata = 0;
432 static int paneltweak __devinitdata = 0;
433 static int vram __devinitdata = 0;
434 static int bpp __devinitdata = 8;
435 #ifdef CONFIG_MTRR
436 static int nomtrr __devinitdata = 0;
437 #endif
438
439 static char *mode_option __devinitdata = NULL;
440
441 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
442 .type = FB_TYPE_PACKED_PIXELS,
443 .xpanstep = 8,
444 .ypanstep = 1,
445 };
446
447 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
448 .xres = 640,
449 .yres = 480,
450 .xres_virtual = 640,
451 .yres_virtual = 480,
452 .bits_per_pixel = 8,
453 .red = {0, 8, 0},
454 .green = {0, 8, 0},
455 .blue = {0, 8, 0},
456 .transp = {0, 0, 0},
457 .activate = FB_ACTIVATE_NOW,
458 .height = -1,
459 .width = -1,
460 .pixclock = 39721,
461 .left_margin = 40,
462 .right_margin = 24,
463 .upper_margin = 32,
464 .lower_margin = 11,
465 .hsync_len = 96,
466 .vsync_len = 2,
467 .vmode = FB_VMODE_NONINTERLACED
468 };
469
470 /*
471 * Backlight control
472 */
473 #ifdef CONFIG_PMAC_BACKLIGHT
474
475 static int nvidia_backlight_levels[] = {
476 0x158,
477 0x192,
478 0x1c6,
479 0x200,
480 0x234,
481 0x268,
482 0x2a2,
483 0x2d6,
484 0x310,
485 0x344,
486 0x378,
487 0x3b2,
488 0x3e6,
489 0x41a,
490 0x454,
491 0x534,
492 };
493
494 /* ------------------------------------------------------------------------- *
495 *
496 * Backlight operations
497 *
498 * ------------------------------------------------------------------------- */
499
500 static int nvidia_set_backlight_enable(int on, int level, void *data)
501 {
502 struct nvidia_par *par = data;
503 u32 tmp_pcrt, tmp_pmc, fpcontrol;
504
505 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
506 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
507 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
508
509 if (on && (level > BACKLIGHT_OFF)) {
510 tmp_pcrt |= 0x1;
511 tmp_pmc |= (1 << 31); // backlight bit
512 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
513 }
514
515 if (on)
516 fpcontrol |= par->fpSyncs;
517 else
518 fpcontrol |= 0x20000022;
519
520 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
521 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
522 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
523
524 return 0;
525 }
526
527 static int nvidia_set_backlight_level(int level, void *data)
528 {
529 return nvidia_set_backlight_enable(1, level, data);
530 }
531
532 static struct backlight_controller nvidia_backlight_controller = {
533 nvidia_set_backlight_enable,
534 nvidia_set_backlight_level
535 };
536
537 #endif /* CONFIG_PMAC_BACKLIGHT */
538
539 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
540 u16 bg, u16 fg, u32 w, u32 h)
541 {
542 u32 *data = (u32 *) data8;
543 int i, j, k = 0;
544 u32 b, tmp;
545
546 w = (w + 1) & ~1;
547
548 for (i = 0; i < h; i++) {
549 b = *data++;
550 reverse_order(&b);
551
552 for (j = 0; j < w / 2; j++) {
553 tmp = 0;
554 #if defined (__BIG_ENDIAN)
555 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
556 b <<= 1;
557 tmp |= (b & (1 << 31)) ? fg : bg;
558 b <<= 1;
559 #else
560 tmp = (b & 1) ? fg : bg;
561 b >>= 1;
562 tmp |= (b & 1) ? fg << 16 : bg << 16;
563 b >>= 1;
564 #endif
565 NV_WR32(&par->CURSOR[k++], 0, tmp);
566 }
567 k += (MAX_CURS - w) / 2;
568 }
569 }
570
571 static void nvidia_write_clut(struct nvidia_par *par,
572 u8 regnum, u8 red, u8 green, u8 blue)
573 {
574 NVWriteDacMask(par, 0xff);
575 NVWriteDacWriteAddr(par, regnum);
576 NVWriteDacData(par, red);
577 NVWriteDacData(par, green);
578 NVWriteDacData(par, blue);
579 }
580
581 static void nvidia_read_clut(struct nvidia_par *par,
582 u8 regnum, u8 * red, u8 * green, u8 * blue)
583 {
584 NVWriteDacMask(par, 0xff);
585 NVWriteDacReadAddr(par, regnum);
586 *red = NVReadDacData(par);
587 *green = NVReadDacData(par);
588 *blue = NVReadDacData(par);
589 }
590
591 static int nvidia_panel_tweak(struct nvidia_par *par,
592 struct _riva_hw_state *state)
593 {
594 int tweak = 0;
595
596 if (par->paneltweak) {
597 tweak = par->paneltweak;
598 } else {
599 /* begin flat panel hacks */
600 /* This is unfortunate, but some chips need this register
601 tweaked or else you get artifacts where adjacent pixels are
602 swapped. There are no hard rules for what to set here so all
603 we can do is experiment and apply hacks. */
604
605 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
606 /* At least one NV34 laptop needs this workaround. */
607 tweak = -1;
608 }
609
610 if((par->Chipset & 0xfff0) == 0x0310) {
611 tweak = 1;
612 }
613 /* end flat panel hacks */
614 }
615
616 return tweak;
617 }
618
619 static void nvidia_save_vga(struct nvidia_par *par,
620 struct _riva_hw_state *state)
621 {
622 int i;
623
624 NVTRACE_ENTER();
625 NVLockUnlock(par, 0);
626
627 NVUnloadStateExt(par, state);
628
629 state->misc_output = NVReadMiscOut(par);
630
631 for (i = 0; i < NUM_CRT_REGS; i++)
632 state->crtc[i] = NVReadCrtc(par, i);
633
634 for (i = 0; i < NUM_ATC_REGS; i++)
635 state->attr[i] = NVReadAttr(par, i);
636
637 for (i = 0; i < NUM_GRC_REGS; i++)
638 state->gra[i] = NVReadGr(par, i);
639
640 for (i = 0; i < NUM_SEQ_REGS; i++)
641 state->seq[i] = NVReadSeq(par, i);
642 NVTRACE_LEAVE();
643 }
644
645 #undef DUMP_REG
646
647 static void nvidia_write_regs(struct nvidia_par *par)
648 {
649 struct _riva_hw_state *state = &par->ModeReg;
650 int i;
651
652 NVTRACE_ENTER();
653
654 NVLoadStateExt(par, state);
655
656 NVWriteMiscOut(par, state->misc_output);
657
658 for (i = 1; i < NUM_SEQ_REGS; i++) {
659 #ifdef DUMP_REG
660 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
661 #endif
662 NVWriteSeq(par, i, state->seq[i]);
663 }
664
665 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
666 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
667
668 for (i = 0; i < NUM_CRT_REGS; i++) {
669 switch (i) {
670 case 0x19:
671 case 0x20 ... 0x40:
672 break;
673 default:
674 #ifdef DUMP_REG
675 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
676 #endif
677 NVWriteCrtc(par, i, state->crtc[i]);
678 }
679 }
680
681 for (i = 0; i < NUM_GRC_REGS; i++) {
682 #ifdef DUMP_REG
683 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
684 #endif
685 NVWriteGr(par, i, state->gra[i]);
686 }
687
688 for (i = 0; i < NUM_ATC_REGS; i++) {
689 #ifdef DUMP_REG
690 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
691 #endif
692 NVWriteAttr(par, i, state->attr[i]);
693 }
694
695 NVTRACE_LEAVE();
696 }
697
698 static void nvidia_vga_protect(struct nvidia_par *par, int on)
699 {
700 unsigned char tmp;
701
702 if (on) {
703 /*
704 * Turn off screen and disable sequencer.
705 */
706 tmp = NVReadSeq(par, 0x01);
707
708 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
709 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
710 } else {
711 /*
712 * Reenable sequencer, then turn on screen.
713 */
714
715 tmp = NVReadSeq(par, 0x01);
716
717 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
718 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
719 }
720 }
721
722
723
724 static int nvidia_calc_regs(struct fb_info *info)
725 {
726 struct nvidia_par *par = info->par;
727 struct _riva_hw_state *state = &par->ModeReg;
728 int i, depth = fb_get_color_depth(&info->var, &info->fix);
729 int h_display = info->var.xres / 8 - 1;
730 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
731 int h_end = (info->var.xres + info->var.right_margin +
732 info->var.hsync_len) / 8 - 1;
733 int h_total = (info->var.xres + info->var.right_margin +
734 info->var.hsync_len + info->var.left_margin) / 8 - 5;
735 int h_blank_s = h_display;
736 int h_blank_e = h_total + 4;
737 int v_display = info->var.yres - 1;
738 int v_start = info->var.yres + info->var.lower_margin - 1;
739 int v_end = (info->var.yres + info->var.lower_margin +
740 info->var.vsync_len) - 1;
741 int v_total = (info->var.yres + info->var.lower_margin +
742 info->var.vsync_len + info->var.upper_margin) - 2;
743 int v_blank_s = v_display;
744 int v_blank_e = v_total + 1;
745
746 /*
747 * Set all CRTC values.
748 */
749
750 if (info->var.vmode & FB_VMODE_INTERLACED)
751 v_total |= 1;
752
753 if (par->FlatPanel == 1) {
754 v_start = v_total - 3;
755 v_end = v_total - 2;
756 v_blank_s = v_start;
757 h_start = h_total - 5;
758 h_end = h_total - 2;
759 h_blank_e = h_total + 4;
760 }
761
762 state->crtc[0x0] = Set8Bits(h_total);
763 state->crtc[0x1] = Set8Bits(h_display);
764 state->crtc[0x2] = Set8Bits(h_blank_s);
765 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
766 | SetBit(7);
767 state->crtc[0x4] = Set8Bits(h_start);
768 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
769 | SetBitField(h_end, 4: 0, 4:0);
770 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
771 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
772 | SetBitField(v_display, 8: 8, 1:1)
773 | SetBitField(v_start, 8: 8, 2:2)
774 | SetBitField(v_blank_s, 8: 8, 3:3)
775 | SetBit(4)
776 | SetBitField(v_total, 9: 9, 5:5)
777 | SetBitField(v_display, 9: 9, 6:6)
778 | SetBitField(v_start, 9: 9, 7:7);
779 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
780 | SetBit(6)
781 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
782 state->crtc[0x10] = Set8Bits(v_start);
783 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
784 state->crtc[0x12] = Set8Bits(v_display);
785 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
786 (info->var.bits_per_pixel / 8));
787 state->crtc[0x15] = Set8Bits(v_blank_s);
788 state->crtc[0x16] = Set8Bits(v_blank_e);
789
790 state->attr[0x10] = 0x01;
791
792 if (par->Television)
793 state->attr[0x11] = 0x00;
794
795 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
796 | SetBitField(v_blank_s, 10: 10, 3:3)
797 | SetBitField(v_start, 10: 10, 2:2)
798 | SetBitField(v_display, 10: 10, 1:1)
799 | SetBitField(v_total, 10: 10, 0:0);
800
801 state->horiz = SetBitField(h_total, 8: 8, 0:0)
802 | SetBitField(h_display, 8: 8, 1:1)
803 | SetBitField(h_blank_s, 8: 8, 2:2)
804 | SetBitField(h_start, 8: 8, 3:3);
805
806 state->extra = SetBitField(v_total, 11: 11, 0:0)
807 | SetBitField(v_display, 11: 11, 2:2)
808 | SetBitField(v_start, 11: 11, 4:4)
809 | SetBitField(v_blank_s, 11: 11, 6:6);
810
811 if (info->var.vmode & FB_VMODE_INTERLACED) {
812 h_total = (h_total >> 1) & ~1;
813 state->interlace = Set8Bits(h_total);
814 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
815 } else {
816 state->interlace = 0xff; /* interlace off */
817 }
818
819 /*
820 * Calculate the extended registers.
821 */
822
823 if (depth < 24)
824 i = depth;
825 else
826 i = 32;
827
828 if (par->Architecture >= NV_ARCH_10)
829 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
830 par->CursorStart);
831
832 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
833 state->misc_output &= ~0x40;
834 else
835 state->misc_output |= 0x40;
836 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
837 state->misc_output &= ~0x80;
838 else
839 state->misc_output |= 0x80;
840
841 NVCalcStateExt(par, state, i, info->var.xres_virtual,
842 info->var.xres, info->var.yres_virtual,
843 1000000000 / info->var.pixclock, info->var.vmode);
844
845 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
846 if (par->FlatPanel == 1) {
847 state->pixel |= (1 << 7);
848
849 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
850 || (par->fpHeight <= info->var.yres)) {
851 state->scale |= (1 << 8);
852 }
853
854 if (!par->crtcSync_read) {
855 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
856 par->crtcSync_read = 1;
857 }
858
859 par->PanelTweak = nvidia_panel_tweak(par, state);
860 }
861
862 state->vpll = state->pll;
863 state->vpll2 = state->pll;
864 state->vpllB = state->pllB;
865 state->vpll2B = state->pllB;
866
867 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
868 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
869
870 if (par->CRTCnumber) {
871 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
872 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
873 state->crtcOwner = 3;
874 state->pllsel |= 0x20000800;
875 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
876 if (par->twoStagePLL)
877 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
878 } else if (par->twoHeads) {
879 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
880 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
881 state->crtcOwner = 0;
882 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
883 if (par->twoStagePLL)
884 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
885 }
886
887 state->cursorConfig = 0x00000100;
888
889 if (info->var.vmode & FB_VMODE_DOUBLE)
890 state->cursorConfig |= (1 << 4);
891
892 if (par->alphaCursor) {
893 if ((par->Chipset & 0x0ff0) != 0x0110)
894 state->cursorConfig |= 0x04011000;
895 else
896 state->cursorConfig |= 0x14011000;
897 state->general |= (1 << 29);
898 } else
899 state->cursorConfig |= 0x02000000;
900
901 if (par->twoHeads) {
902 if ((par->Chipset & 0x0ff0) == 0x0110) {
903 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
904 ~0x00010000;
905 if (par->FPDither)
906 state->dither |= 0x00010000;
907 } else {
908 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
909 if (par->FPDither)
910 state->dither |= 1;
911 }
912 }
913
914 state->timingH = 0;
915 state->timingV = 0;
916 state->displayV = info->var.xres;
917
918 return 0;
919 }
920
921 static void nvidia_init_vga(struct fb_info *info)
922 {
923 struct nvidia_par *par = info->par;
924 struct _riva_hw_state *state = &par->ModeReg;
925 int i;
926
927 for (i = 0; i < 0x10; i++)
928 state->attr[i] = i;
929 state->attr[0x10] = 0x41;
930 state->attr[0x11] = 0xff;
931 state->attr[0x12] = 0x0f;
932 state->attr[0x13] = 0x00;
933 state->attr[0x14] = 0x00;
934
935 memset(state->crtc, 0x00, NUM_CRT_REGS);
936 state->crtc[0x0a] = 0x20;
937 state->crtc[0x17] = 0xe3;
938 state->crtc[0x18] = 0xff;
939 state->crtc[0x28] = 0x40;
940
941 memset(state->gra, 0x00, NUM_GRC_REGS);
942 state->gra[0x05] = 0x40;
943 state->gra[0x06] = 0x05;
944 state->gra[0x07] = 0x0f;
945 state->gra[0x08] = 0xff;
946
947 state->seq[0x00] = 0x03;
948 state->seq[0x01] = 0x01;
949 state->seq[0x02] = 0x0f;
950 state->seq[0x03] = 0x00;
951 state->seq[0x04] = 0x0e;
952
953 state->misc_output = 0xeb;
954 }
955
956 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
957 {
958 struct nvidia_par *par = info->par;
959 u8 data[MAX_CURS * MAX_CURS / 8];
960 int i, set = cursor->set;
961 u16 fg, bg;
962
963 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
964 return -ENXIO;
965
966 NVShowHideCursor(par, 0);
967
968 if (par->cursor_reset) {
969 set = FB_CUR_SETALL;
970 par->cursor_reset = 0;
971 }
972
973 if (set & FB_CUR_SETSIZE)
974 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
975
976 if (set & FB_CUR_SETPOS) {
977 u32 xx, yy, temp;
978
979 yy = cursor->image.dy - info->var.yoffset;
980 xx = cursor->image.dx - info->var.xoffset;
981 temp = xx & 0xFFFF;
982 temp |= yy << 16;
983
984 NV_WR32(par->PRAMDAC, 0x0000300, temp);
985 }
986
987 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
988 u32 bg_idx = cursor->image.bg_color;
989 u32 fg_idx = cursor->image.fg_color;
990 u32 s_pitch = (cursor->image.width + 7) >> 3;
991 u32 d_pitch = MAX_CURS / 8;
992 u8 *dat = (u8 *) cursor->image.data;
993 u8 *msk = (u8 *) cursor->mask;
994 u8 *src;
995
996 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
997
998 if (src) {
999 switch (cursor->rop) {
1000 case ROP_XOR:
1001 for (i = 0; i < s_pitch * cursor->image.height; i++)
1002 src[i] = dat[i] ^ msk[i];
1003 break;
1004 case ROP_COPY:
1005 default:
1006 for (i = 0; i < s_pitch * cursor->image.height; i++)
1007 src[i] = dat[i] & msk[i];
1008 break;
1009 }
1010
1011 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1012 cursor->image.height);
1013
1014 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1015 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1016 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
1017
1018 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1019 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1020 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1021
1022 NVLockUnlock(par, 0);
1023
1024 nvidiafb_load_cursor_image(par, data, bg, fg,
1025 cursor->image.width,
1026 cursor->image.height);
1027 kfree(src);
1028 }
1029 }
1030
1031 if (cursor->enable)
1032 NVShowHideCursor(par, 1);
1033
1034 return 0;
1035 }
1036
1037 static int nvidiafb_set_par(struct fb_info *info)
1038 {
1039 struct nvidia_par *par = info->par;
1040
1041 NVTRACE_ENTER();
1042
1043 NVLockUnlock(par, 1);
1044 if (!par->FlatPanel || !par->twoHeads)
1045 par->FPDither = 0;
1046
1047 if (par->FPDither < 0) {
1048 if ((par->Chipset & 0x0ff0) == 0x0110)
1049 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
1050 & 0x00010000);
1051 else
1052 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
1053 printk(KERN_INFO PFX "Flat panel dithering %s\n",
1054 par->FPDither ? "enabled" : "disabled");
1055 }
1056
1057 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1058 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1059
1060 nvidia_init_vga(info);
1061 nvidia_calc_regs(info);
1062
1063 NVLockUnlock(par, 0);
1064 if (par->twoHeads) {
1065 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1066 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
1067 NVLockUnlock(par, 0);
1068 }
1069
1070 nvidia_vga_protect(par, 1);
1071
1072 nvidia_write_regs(par);
1073
1074 #if defined (__BIG_ENDIAN)
1075 /* turn on LFB swapping */
1076 {
1077 unsigned char tmp;
1078
1079 VGA_WR08(par->PCIO, 0x3d4, 0x46);
1080 tmp = VGA_RD08(par->PCIO, 0x3d5);
1081 tmp |= (1 << 7);
1082 VGA_WR08(par->PCIO, 0x3d5, tmp);
1083 }
1084 #endif
1085
1086 info->fix.line_length = (info->var.xres_virtual *
1087 info->var.bits_per_pixel) >> 3;
1088 if (info->var.accel_flags) {
1089 info->fbops->fb_imageblit = nvidiafb_imageblit;
1090 info->fbops->fb_fillrect = nvidiafb_fillrect;
1091 info->fbops->fb_copyarea = nvidiafb_copyarea;
1092 info->fbops->fb_sync = nvidiafb_sync;
1093 info->pixmap.scan_align = 4;
1094 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1095 NVResetGraphics(info);
1096 } else {
1097 info->fbops->fb_imageblit = cfb_imageblit;
1098 info->fbops->fb_fillrect = cfb_fillrect;
1099 info->fbops->fb_copyarea = cfb_copyarea;
1100 info->fbops->fb_sync = NULL;
1101 info->pixmap.scan_align = 1;
1102 info->flags |= FBINFO_HWACCEL_DISABLED;
1103 }
1104
1105 par->cursor_reset = 1;
1106
1107 nvidia_vga_protect(par, 0);
1108
1109 NVTRACE_LEAVE();
1110 return 0;
1111 }
1112
1113 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1114 unsigned blue, unsigned transp,
1115 struct fb_info *info)
1116 {
1117 struct nvidia_par *par = info->par;
1118 int i;
1119
1120 NVTRACE_ENTER();
1121 if (regno >= (1 << info->var.green.length))
1122 return -EINVAL;
1123
1124 if (info->var.grayscale) {
1125 /* gray = 0.30*R + 0.59*G + 0.11*B */
1126 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1127 }
1128
1129 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1130 ((u32 *) info->pseudo_palette)[regno] =
1131 (regno << info->var.red.offset) |
1132 (regno << info->var.green.offset) |
1133 (regno << info->var.blue.offset);
1134 }
1135
1136 switch (info->var.bits_per_pixel) {
1137 case 8:
1138 /* "transparent" stuff is completely ignored. */
1139 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1140 break;
1141 case 16:
1142 if (info->var.green.length == 5) {
1143 for (i = 0; i < 8; i++) {
1144 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1145 green >> 8, blue >> 8);
1146 }
1147 } else {
1148 u8 r, g, b;
1149
1150 if (regno < 32) {
1151 for (i = 0; i < 8; i++) {
1152 nvidia_write_clut(par, regno * 8 + i,
1153 red >> 8, green >> 8,
1154 blue >> 8);
1155 }
1156 }
1157
1158 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1159
1160 for (i = 0; i < 4; i++)
1161 nvidia_write_clut(par, regno * 4 + i, r,
1162 green >> 8, b);
1163 }
1164 break;
1165 case 32:
1166 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1167 break;
1168 default:
1169 /* do nothing */
1170 break;
1171 }
1172
1173 NVTRACE_LEAVE();
1174 return 0;
1175 }
1176
1177 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1178 struct fb_info *info)
1179 {
1180 struct nvidia_par *par = info->par;
1181 int memlen, vramlen, mode_valid = 0;
1182 int pitch, err = 0;
1183
1184 NVTRACE_ENTER();
1185
1186 var->transp.offset = 0;
1187 var->transp.length = 0;
1188
1189 var->xres &= ~7;
1190
1191 if (var->bits_per_pixel <= 8)
1192 var->bits_per_pixel = 8;
1193 else if (var->bits_per_pixel <= 16)
1194 var->bits_per_pixel = 16;
1195 else
1196 var->bits_per_pixel = 32;
1197
1198 switch (var->bits_per_pixel) {
1199 case 8:
1200 var->red.offset = 0;
1201 var->red.length = 8;
1202 var->green.offset = 0;
1203 var->green.length = 8;
1204 var->blue.offset = 0;
1205 var->blue.length = 8;
1206 var->transp.offset = 0;
1207 var->transp.length = 0;
1208 break;
1209 case 16:
1210 var->green.length = (var->green.length < 6) ? 5 : 6;
1211 var->red.length = 5;
1212 var->blue.length = 5;
1213 var->transp.length = 6 - var->green.length;
1214 var->blue.offset = 0;
1215 var->green.offset = 5;
1216 var->red.offset = 5 + var->green.length;
1217 var->transp.offset = (5 + var->red.offset) & 15;
1218 break;
1219 case 32: /* RGBA 8888 */
1220 var->red.offset = 16;
1221 var->red.length = 8;
1222 var->green.offset = 8;
1223 var->green.length = 8;
1224 var->blue.offset = 0;
1225 var->blue.length = 8;
1226 var->transp.length = 8;
1227 var->transp.offset = 24;
1228 break;
1229 }
1230
1231 var->red.msb_right = 0;
1232 var->green.msb_right = 0;
1233 var->blue.msb_right = 0;
1234 var->transp.msb_right = 0;
1235
1236 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1237 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1238 mode_valid = 1;
1239
1240 /* calculate modeline if supported by monitor */
1241 if (!mode_valid && info->monspecs.gtf) {
1242 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1243 mode_valid = 1;
1244 }
1245
1246 if (!mode_valid) {
1247 struct fb_videomode *mode;
1248
1249 mode = fb_find_best_mode(var, &info->modelist);
1250 if (mode) {
1251 fb_videomode_to_var(var, mode);
1252 mode_valid = 1;
1253 }
1254 }
1255
1256 if (!mode_valid && info->monspecs.modedb_len)
1257 return -EINVAL;
1258
1259 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1260 par->fpHeight < var->yres))
1261 return -EINVAL;
1262
1263 if (var->yres_virtual < var->yres)
1264 var->yres_virtual = var->yres;
1265
1266 if (var->xres_virtual < var->xres)
1267 var->xres_virtual = var->xres;
1268
1269 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1270
1271 vramlen = info->screen_size;
1272 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1273 memlen = pitch * var->yres_virtual;
1274
1275 if (memlen > vramlen) {
1276 var->yres_virtual = vramlen / pitch;
1277
1278 if (var->yres_virtual < var->yres) {
1279 var->yres_virtual = var->yres;
1280 var->xres_virtual = vramlen / var->yres_virtual;
1281 var->xres_virtual /= var->bits_per_pixel / 8;
1282 var->xres_virtual &= ~63;
1283 pitch = (var->xres_virtual *
1284 var->bits_per_pixel + 7) / 8;
1285 memlen = pitch * var->yres;
1286
1287 if (var->xres_virtual < var->xres) {
1288 printk("nvidiafb: required video memory, "
1289 "%d bytes, for %dx%d-%d (virtual) "
1290 "is out of range\n",
1291 memlen, var->xres_virtual,
1292 var->yres_virtual, var->bits_per_pixel);
1293 err = -ENOMEM;
1294 }
1295 }
1296 }
1297
1298 if (var->accel_flags) {
1299 if (var->yres_virtual > 0x7fff)
1300 var->yres_virtual = 0x7fff;
1301 if (var->xres_virtual > 0x7fff)
1302 var->xres_virtual = 0x7fff;
1303 }
1304
1305 var->xres_virtual &= ~63;
1306
1307 NVTRACE_LEAVE();
1308
1309 return err;
1310 }
1311
1312 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1313 struct fb_info *info)
1314 {
1315 struct nvidia_par *par = info->par;
1316 u32 total;
1317
1318 total = var->yoffset * info->fix.line_length + var->xoffset;
1319
1320 NVSetStartAddress(par, total);
1321
1322 return 0;
1323 }
1324
1325 static int nvidiafb_blank(int blank, struct fb_info *info)
1326 {
1327 struct nvidia_par *par = info->par;
1328 unsigned char tmp, vesa;
1329
1330 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1331 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1332
1333 NVTRACE_ENTER();
1334
1335 if (blank)
1336 tmp |= 0x20;
1337
1338 switch (blank) {
1339 case FB_BLANK_UNBLANK:
1340 case FB_BLANK_NORMAL:
1341 break;
1342 case FB_BLANK_VSYNC_SUSPEND:
1343 vesa |= 0x80;
1344 break;
1345 case FB_BLANK_HSYNC_SUSPEND:
1346 vesa |= 0x40;
1347 break;
1348 case FB_BLANK_POWERDOWN:
1349 vesa |= 0xc0;
1350 break;
1351 }
1352
1353 NVWriteSeq(par, 0x01, tmp);
1354 NVWriteCrtc(par, 0x1a, vesa);
1355
1356 #ifdef CONFIG_PMAC_BACKLIGHT
1357 if (par->FlatPanel && machine_is(powermac)) {
1358 set_backlight_enable(!blank);
1359 }
1360 #endif
1361
1362 NVTRACE_LEAVE();
1363
1364 return 0;
1365 }
1366
1367 static struct fb_ops nvidia_fb_ops = {
1368 .owner = THIS_MODULE,
1369 .fb_check_var = nvidiafb_check_var,
1370 .fb_set_par = nvidiafb_set_par,
1371 .fb_setcolreg = nvidiafb_setcolreg,
1372 .fb_pan_display = nvidiafb_pan_display,
1373 .fb_blank = nvidiafb_blank,
1374 .fb_fillrect = nvidiafb_fillrect,
1375 .fb_copyarea = nvidiafb_copyarea,
1376 .fb_imageblit = nvidiafb_imageblit,
1377 .fb_cursor = nvidiafb_cursor,
1378 .fb_sync = nvidiafb_sync,
1379 };
1380
1381 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1382 {
1383 struct fb_monspecs *specs = &info->monspecs;
1384 struct fb_videomode modedb;
1385 struct nvidia_par *par = info->par;
1386 int lpitch;
1387
1388 NVTRACE_ENTER();
1389 info->flags = FBINFO_DEFAULT
1390 | FBINFO_HWACCEL_IMAGEBLIT
1391 | FBINFO_HWACCEL_FILLRECT
1392 | FBINFO_HWACCEL_COPYAREA
1393 | FBINFO_HWACCEL_YPAN;
1394
1395 fb_videomode_to_modelist(info->monspecs.modedb,
1396 info->monspecs.modedb_len, &info->modelist);
1397 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1398
1399 switch (bpp) {
1400 case 0 ... 8:
1401 bpp = 8;
1402 break;
1403 case 9 ... 16:
1404 bpp = 16;
1405 break;
1406 default:
1407 bpp = 32;
1408 break;
1409 }
1410
1411 if (specs->modedb != NULL) {
1412 struct fb_videomode *modedb;
1413
1414 modedb = fb_find_best_display(specs, &info->modelist);
1415 fb_videomode_to_var(&nvidiafb_default_var, modedb);
1416 nvidiafb_default_var.bits_per_pixel = bpp;
1417 } else if (par->fpWidth && par->fpHeight) {
1418 char buf[16];
1419
1420 memset(buf, 0, 16);
1421 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1422 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1423 specs->modedb_len, &modedb, bpp);
1424 }
1425
1426 if (mode_option)
1427 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1428 specs->modedb, specs->modedb_len, &modedb, bpp);
1429
1430 info->var = nvidiafb_default_var;
1431 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1432 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1433 info->pseudo_palette = par->pseudo_palette;
1434 fb_alloc_cmap(&info->cmap, 256, 0);
1435 fb_destroy_modedb(info->monspecs.modedb);
1436 info->monspecs.modedb = NULL;
1437
1438 /* maximize virtual vertical length */
1439 lpitch = info->var.xres_virtual *
1440 ((info->var.bits_per_pixel + 7) >> 3);
1441 info->var.yres_virtual = info->screen_size / lpitch;
1442
1443 info->pixmap.scan_align = 4;
1444 info->pixmap.buf_align = 4;
1445 info->pixmap.access_align = 32;
1446 info->pixmap.size = 8 * 1024;
1447 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1448
1449 if (!hwcur)
1450 info->fbops->fb_cursor = NULL;
1451
1452 info->var.accel_flags = (!noaccel);
1453
1454 switch (par->Architecture) {
1455 case NV_ARCH_04:
1456 info->fix.accel = FB_ACCEL_NV4;
1457 break;
1458 case NV_ARCH_10:
1459 info->fix.accel = FB_ACCEL_NV_10;
1460 break;
1461 case NV_ARCH_20:
1462 info->fix.accel = FB_ACCEL_NV_20;
1463 break;
1464 case NV_ARCH_30:
1465 info->fix.accel = FB_ACCEL_NV_30;
1466 break;
1467 case NV_ARCH_40:
1468 info->fix.accel = FB_ACCEL_NV_40;
1469 break;
1470 }
1471
1472 NVTRACE_LEAVE();
1473
1474 return nvidiafb_check_var(&info->var, info);
1475 }
1476
1477 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1478 {
1479 struct nvidia_par *par = info->par;
1480 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1481
1482 printk("nvidiafb: PCI id - %x\n", id);
1483 if ((id & 0xfff0) == 0x00f0) {
1484 /* pci-e */
1485 printk("nvidiafb: PCI-E card\n");
1486 id = NV_RD32(par->REGS, 0x1800);
1487
1488 if ((id & 0x0000ffff) == 0x000010DE)
1489 id = 0x10DE0000 | (id >> 16);
1490 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1491 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1492 ((id >> 8) & 0x000000ff);
1493 }
1494
1495 printk("nvidiafb: Actual id - %x\n", id);
1496 return id;
1497 }
1498
1499 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1500 {
1501 struct nvidia_par *par = info->par;
1502 u32 arch = 0;
1503
1504 switch (par->Chipset & 0x0ff0) {
1505 case 0x0100: /* GeForce 256 */
1506 case 0x0110: /* GeForce2 MX */
1507 case 0x0150: /* GeForce2 */
1508 case 0x0170: /* GeForce4 MX */
1509 case 0x0180: /* GeForce4 MX (8x AGP) */
1510 case 0x01A0: /* nForce */
1511 case 0x01F0: /* nForce2 */
1512 arch = NV_ARCH_10;
1513 break;
1514 case 0x0200: /* GeForce3 */
1515 case 0x0250: /* GeForce4 Ti */
1516 case 0x0280: /* GeForce4 Ti (8x AGP) */
1517 arch = NV_ARCH_20;
1518 break;
1519 case 0x0300: /* GeForceFX 5800 */
1520 case 0x0310: /* GeForceFX 5600 */
1521 case 0x0320: /* GeForceFX 5200 */
1522 case 0x0330: /* GeForceFX 5900 */
1523 case 0x0340: /* GeForceFX 5700 */
1524 arch = NV_ARCH_30;
1525 break;
1526 case 0x0040:
1527 case 0x00C0:
1528 case 0x0120:
1529 case 0x0130:
1530 case 0x0140:
1531 case 0x0160:
1532 case 0x01D0:
1533 case 0x0090:
1534 case 0x0210:
1535 case 0x0220:
1536 case 0x0230:
1537 case 0x0290:
1538 case 0x0390:
1539 arch = NV_ARCH_40;
1540 break;
1541 case 0x0020: /* TNT, TNT2 */
1542 arch = NV_ARCH_04;
1543 break;
1544 default: /* unknown architecture */
1545 break;
1546 }
1547
1548 return arch;
1549 }
1550
1551 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1552 const struct pci_device_id *ent)
1553 {
1554 struct nvidia_par *par;
1555 struct fb_info *info;
1556 unsigned short cmd;
1557
1558
1559 NVTRACE_ENTER();
1560 assert(pd != NULL);
1561
1562 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1563
1564 if (!info)
1565 goto err_out;
1566
1567 par = info->par;
1568 par->pci_dev = pd;
1569
1570 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1571
1572 if (info->pixmap.addr == NULL)
1573 goto err_out_kfree;
1574
1575 memset(info->pixmap.addr, 0, 8 * 1024);
1576
1577 if (pci_enable_device(pd)) {
1578 printk(KERN_ERR PFX "cannot enable PCI device\n");
1579 goto err_out_enable;
1580 }
1581
1582 if (pci_request_regions(pd, "nvidiafb")) {
1583 printk(KERN_ERR PFX "cannot request PCI regions\n");
1584 goto err_out_request;
1585 }
1586
1587 par->FlatPanel = flatpanel;
1588 if (flatpanel == 1)
1589 printk(KERN_INFO PFX "flatpanel support enabled\n");
1590 par->FPDither = fpdither;
1591
1592 par->CRTCnumber = forceCRTC;
1593 par->FpScale = (!noscale);
1594 par->paneltweak = paneltweak;
1595
1596 /* enable IO and mem if not already done */
1597 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1598 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1599 pci_write_config_word(pd, PCI_COMMAND, cmd);
1600
1601 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1602 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1603 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1604
1605 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1606
1607 if (!par->REGS) {
1608 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1609 goto err_out_free_base0;
1610 }
1611
1612 par->Chipset = nvidia_get_chipset(info);
1613 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1614 par->Architecture = nvidia_get_arch(info);
1615
1616 if (par->Architecture == 0) {
1617 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1618 goto err_out_arch;
1619 }
1620
1621 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1622
1623 if (NVCommonSetup(info))
1624 goto err_out_arch;
1625
1626 par->FbAddress = nvidiafb_fix.smem_start;
1627 par->FbMapSize = par->RamAmountKBytes * 1024;
1628 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1629 par->FbMapSize = vram * 1024 * 1024;
1630
1631 /* Limit amount of vram to 64 MB */
1632 if (par->FbMapSize > 64 * 1024 * 1024)
1633 par->FbMapSize = 64 * 1024 * 1024;
1634
1635 if(par->Architecture >= NV_ARCH_40)
1636 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1637 else
1638 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1639 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1640 16 * 1024;
1641 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1642 par->CursorStart = par->FbUsableSize + (32 * 1024);
1643
1644 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1645 info->screen_size = par->FbUsableSize;
1646 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1647
1648 if (!info->screen_base) {
1649 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1650 goto err_out_free_base1;
1651 }
1652
1653 par->FbStart = info->screen_base;
1654
1655 #ifdef CONFIG_MTRR
1656 if (!nomtrr) {
1657 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1658 par->RamAmountKBytes * 1024,
1659 MTRR_TYPE_WRCOMB, 1);
1660 if (par->mtrr.vram < 0) {
1661 printk(KERN_ERR PFX "unable to setup MTRR\n");
1662 } else {
1663 par->mtrr.vram_valid = 1;
1664 /* let there be speed */
1665 printk(KERN_INFO PFX "MTRR set to ON\n");
1666 }
1667 }
1668 #endif /* CONFIG_MTRR */
1669
1670 info->fbops = &nvidia_fb_ops;
1671 info->fix = nvidiafb_fix;
1672
1673 if (nvidia_set_fbinfo(info) < 0) {
1674 printk(KERN_ERR PFX "error setting initial video mode\n");
1675 goto err_out_iounmap_fb;
1676 }
1677
1678 nvidia_save_vga(par, &par->SavedReg);
1679
1680 if (register_framebuffer(info) < 0) {
1681 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1682 goto err_out_iounmap_fb;
1683 }
1684
1685 pci_set_drvdata(pd, info);
1686
1687 printk(KERN_INFO PFX
1688 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1689 info->fix.id,
1690 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1691 #ifdef CONFIG_PMAC_BACKLIGHT
1692 if (par->FlatPanel && machine_is(powermac))
1693 register_backlight_controller(&nvidia_backlight_controller,
1694 par, "mnca");
1695 #endif
1696 NVTRACE_LEAVE();
1697 return 0;
1698
1699 err_out_iounmap_fb:
1700 iounmap(info->screen_base);
1701 err_out_free_base1:
1702 fb_destroy_modedb(info->monspecs.modedb);
1703 nvidia_delete_i2c_busses(par);
1704 err_out_arch:
1705 iounmap(par->REGS);
1706 err_out_free_base0:
1707 pci_release_regions(pd);
1708 err_out_request:
1709 pci_disable_device(pd);
1710 err_out_enable:
1711 kfree(info->pixmap.addr);
1712 err_out_kfree:
1713 framebuffer_release(info);
1714 err_out:
1715 return -ENODEV;
1716 }
1717
1718 static void __exit nvidiafb_remove(struct pci_dev *pd)
1719 {
1720 struct fb_info *info = pci_get_drvdata(pd);
1721 struct nvidia_par *par = info->par;
1722
1723 NVTRACE_ENTER();
1724 if (!info)
1725 return;
1726
1727 unregister_framebuffer(info);
1728 #ifdef CONFIG_MTRR
1729 if (par->mtrr.vram_valid)
1730 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1731 info->fix.smem_len);
1732 #endif /* CONFIG_MTRR */
1733
1734 iounmap(info->screen_base);
1735 fb_destroy_modedb(info->monspecs.modedb);
1736 nvidia_delete_i2c_busses(par);
1737 iounmap(par->REGS);
1738 pci_release_regions(pd);
1739 pci_disable_device(pd);
1740 kfree(info->pixmap.addr);
1741 framebuffer_release(info);
1742 pci_set_drvdata(pd, NULL);
1743 NVTRACE_LEAVE();
1744 }
1745
1746 /* ------------------------------------------------------------------------- *
1747 *
1748 * initialization
1749 *
1750 * ------------------------------------------------------------------------- */
1751
1752 #ifndef MODULE
1753 static int __devinit nvidiafb_setup(char *options)
1754 {
1755 char *this_opt;
1756
1757 NVTRACE_ENTER();
1758 if (!options || !*options)
1759 return 0;
1760
1761 while ((this_opt = strsep(&options, ",")) != NULL) {
1762 if (!strncmp(this_opt, "forceCRTC", 9)) {
1763 char *p;
1764
1765 p = this_opt + 9;
1766 if (!*p || !*(++p))
1767 continue;
1768 forceCRTC = *p - '0';
1769 if (forceCRTC < 0 || forceCRTC > 1)
1770 forceCRTC = -1;
1771 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1772 flatpanel = 1;
1773 } else if (!strncmp(this_opt, "hwcur", 5)) {
1774 hwcur = 1;
1775 } else if (!strncmp(this_opt, "noaccel", 6)) {
1776 noaccel = 1;
1777 } else if (!strncmp(this_opt, "noscale", 7)) {
1778 noscale = 1;
1779 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1780 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1781 } else if (!strncmp(this_opt, "vram:", 5)) {
1782 vram = simple_strtoul(this_opt+5, NULL, 0);
1783 #ifdef CONFIG_MTRR
1784 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1785 nomtrr = 1;
1786 #endif
1787 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1788 fpdither = simple_strtol(this_opt+9, NULL, 0);
1789 } else if (!strncmp(this_opt, "bpp:", 4)) {
1790 bpp = simple_strtoul(this_opt+4, NULL, 0);
1791 } else
1792 mode_option = this_opt;
1793 }
1794 NVTRACE_LEAVE();
1795 return 0;
1796 }
1797 #endif /* !MODULE */
1798
1799 static struct pci_driver nvidiafb_driver = {
1800 .name = "nvidiafb",
1801 .id_table = nvidiafb_pci_tbl,
1802 .probe = nvidiafb_probe,
1803 .remove = __exit_p(nvidiafb_remove),
1804 };
1805
1806 /* ------------------------------------------------------------------------- *
1807 *
1808 * modularization
1809 *
1810 * ------------------------------------------------------------------------- */
1811
1812 static int __devinit nvidiafb_init(void)
1813 {
1814 #ifndef MODULE
1815 char *option = NULL;
1816
1817 if (fb_get_options("nvidiafb", &option))
1818 return -ENODEV;
1819 nvidiafb_setup(option);
1820 #endif
1821 return pci_register_driver(&nvidiafb_driver);
1822 }
1823
1824 module_init(nvidiafb_init);
1825
1826 #ifdef MODULE
1827 static void __exit nvidiafb_exit(void)
1828 {
1829 pci_unregister_driver(&nvidiafb_driver);
1830 }
1831
1832 module_exit(nvidiafb_exit);
1833
1834 module_param(flatpanel, int, 0);
1835 MODULE_PARM_DESC(flatpanel,
1836 "Enables experimental flat panel support for some chipsets. "
1837 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1838 module_param(fpdither, int, 0);
1839 MODULE_PARM_DESC(fpdither,
1840 "Enables dithering of flat panel for 6 bits panels. "
1841 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1842 module_param(hwcur, int, 0);
1843 MODULE_PARM_DESC(hwcur,
1844 "Enables hardware cursor implementation. (0 or 1=enabled) "
1845 "(default=0)");
1846 module_param(noaccel, int, 0);
1847 MODULE_PARM_DESC(noaccel,
1848 "Disables hardware acceleration. (0 or 1=disable) "
1849 "(default=0)");
1850 module_param(noscale, int, 0);
1851 MODULE_PARM_DESC(noscale,
1852 "Disables screen scaleing. (0 or 1=disable) "
1853 "(default=0, do scaling)");
1854 module_param(paneltweak, int, 0);
1855 MODULE_PARM_DESC(paneltweak,
1856 "Tweak display settings for flatpanels. "
1857 "(default=0, no tweaks)");
1858 module_param(forceCRTC, int, 0);
1859 MODULE_PARM_DESC(forceCRTC,
1860 "Forces usage of a particular CRTC in case autodetection "
1861 "fails. (0 or 1) (default=autodetect)");
1862 module_param(vram, int, 0);
1863 MODULE_PARM_DESC(vram,
1864 "amount of framebuffer memory to remap in MiB"
1865 "(default=0 - remap entire memory)");
1866 module_param(mode_option, charp, 0);
1867 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1868 module_param(bpp, int, 0);
1869 MODULE_PARM_DESC(bpp, "pixel width in bits"
1870 "(default=8)");
1871 #ifdef CONFIG_MTRR
1872 module_param(nomtrr, bool, 0);
1873 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1874 "(default=0)");
1875 #endif
1876
1877 MODULE_AUTHOR("Antonino Daplas");
1878 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1879 MODULE_LICENSE("GPL");
1880 #endif /* MODULE */
1881
Linux kernel - Deliverables
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