projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
video: Remove unnecessary semicolons
[deliverable/linux.git] / drivers / video / omap2 / dss / dsi.c
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
41
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44
45 #include "dss.h"
46 #include "dss_features.h"
47
48 #define DSI_CATCH_MISSING_TE
49
50 struct dsi_reg { u16 idx; };
51
52 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
53
54 #define DSI_SZ_REGS SZ_1K
55 /* DSI Protocol Engine */
56
57 #define DSI_REVISION DSI_REG(0x0000)
58 #define DSI_SYSCONFIG DSI_REG(0x0010)
59 #define DSI_SYSSTATUS DSI_REG(0x0014)
60 #define DSI_IRQSTATUS DSI_REG(0x0018)
61 #define DSI_IRQENABLE DSI_REG(0x001C)
62 #define DSI_CTRL DSI_REG(0x0040)
63 #define DSI_GNQ DSI_REG(0x0044)
64 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
65 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
66 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
67 #define DSI_CLK_CTRL DSI_REG(0x0054)
68 #define DSI_TIMING1 DSI_REG(0x0058)
69 #define DSI_TIMING2 DSI_REG(0x005C)
70 #define DSI_VM_TIMING1 DSI_REG(0x0060)
71 #define DSI_VM_TIMING2 DSI_REG(0x0064)
72 #define DSI_VM_TIMING3 DSI_REG(0x0068)
73 #define DSI_CLK_TIMING DSI_REG(0x006C)
74 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
75 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
76 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
77 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
78 #define DSI_VM_TIMING4 DSI_REG(0x0080)
79 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
80 #define DSI_VM_TIMING5 DSI_REG(0x0088)
81 #define DSI_VM_TIMING6 DSI_REG(0x008C)
82 #define DSI_VM_TIMING7 DSI_REG(0x0090)
83 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
84 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
85 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
86 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
87 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
88 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
89 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
90 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
91
92 /* DSIPHY_SCP */
93
94 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
95 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
96 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
97 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
98 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
99
100 /* DSI_PLL_CTRL_SCP */
101
102 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
103 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
104 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
105 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
106 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
107
108 #define REG_GET(dsidev, idx, start, end) \
109 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
110
111 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
112 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
113
114 /* Global interrupts */
115 #define DSI_IRQ_VC0 (1 << 0)
116 #define DSI_IRQ_VC1 (1 << 1)
117 #define DSI_IRQ_VC2 (1 << 2)
118 #define DSI_IRQ_VC3 (1 << 3)
119 #define DSI_IRQ_WAKEUP (1 << 4)
120 #define DSI_IRQ_RESYNC (1 << 5)
121 #define DSI_IRQ_PLL_LOCK (1 << 7)
122 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
123 #define DSI_IRQ_PLL_RECALL (1 << 9)
124 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
125 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
126 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
127 #define DSI_IRQ_TE_TRIGGER (1 << 16)
128 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
129 #define DSI_IRQ_SYNC_LOST (1 << 18)
130 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
131 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
132 #define DSI_IRQ_ERROR_MASK \
133 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
134 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
135 #define DSI_IRQ_CHANNEL_MASK 0xf
136
137 /* Virtual channel interrupts */
138 #define DSI_VC_IRQ_CS (1 << 0)
139 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
140 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
141 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
142 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
143 #define DSI_VC_IRQ_BTA (1 << 5)
144 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
145 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
146 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
147 #define DSI_VC_IRQ_ERROR_MASK \
148 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
149 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
150 DSI_VC_IRQ_FIFO_TX_UDF)
151
152 /* ComplexIO interrupts */
153 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
154 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
155 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
156 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
157 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
158 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
159 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
160 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
161 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
162 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
163 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
164 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
165 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
166 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
167 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
168 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
169 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
170 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
171 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
172 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
173 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
183 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
185 #define DSI_CIO_IRQ_ERROR_MASK \
186 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
187 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
188 DSI_CIO_IRQ_ERRSYNCESC5 | \
189 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
190 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
191 DSI_CIO_IRQ_ERRESC5 | \
192 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
193 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
194 DSI_CIO_IRQ_ERRCONTROL5 | \
195 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
200
201 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
202
203 static int dsi_display_init_dispc(struct platform_device *dsidev,
204 struct omap_overlay_manager *mgr);
205 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
206 struct omap_overlay_manager *mgr);
207
208 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
209
210 #define DSI_MAX_NR_ISRS 2
211 #define DSI_MAX_NR_LANES 5
212
213 enum dsi_lane_function {
214 DSI_LANE_UNUSED = 0,
215 DSI_LANE_CLK,
216 DSI_LANE_DATA1,
217 DSI_LANE_DATA2,
218 DSI_LANE_DATA3,
219 DSI_LANE_DATA4,
220 };
221
222 struct dsi_lane_config {
223 enum dsi_lane_function function;
224 u8 polarity;
225 };
226
227 struct dsi_isr_data {
228 omap_dsi_isr_t isr;
229 void *arg;
230 u32 mask;
231 };
232
233 enum fifo_size {
234 DSI_FIFO_SIZE_0 = 0,
235 DSI_FIFO_SIZE_32 = 1,
236 DSI_FIFO_SIZE_64 = 2,
237 DSI_FIFO_SIZE_96 = 3,
238 DSI_FIFO_SIZE_128 = 4,
239 };
240
241 enum dsi_vc_source {
242 DSI_VC_SOURCE_L4 = 0,
243 DSI_VC_SOURCE_VP,
244 };
245
246 struct dsi_irq_stats {
247 unsigned long last_reset;
248 unsigned irq_count;
249 unsigned dsi_irqs[32];
250 unsigned vc_irqs[4][32];
251 unsigned cio_irqs[32];
252 };
253
254 struct dsi_isr_tables {
255 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
256 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
257 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
258 };
259
260 struct dsi_clk_calc_ctx {
261 struct platform_device *dsidev;
262
263 /* inputs */
264
265 const struct omap_dss_dsi_config *config;
266
267 unsigned long req_pck_min, req_pck_nom, req_pck_max;
268
269 /* outputs */
270
271 struct dsi_clock_info dsi_cinfo;
272 struct dispc_clock_info dispc_cinfo;
273
274 struct omap_video_timings dispc_vm;
275 struct omap_dss_dsi_videomode_timings dsi_vm;
276 };
277
278 struct dsi_data {
279 struct platform_device *pdev;
280 void __iomem *base;
281
282 int module_id;
283
284 int irq;
285
286 struct clk *dss_clk;
287 struct clk *sys_clk;
288
289 struct dispc_clock_info user_dispc_cinfo;
290 struct dsi_clock_info user_dsi_cinfo;
291
292 struct dsi_clock_info current_cinfo;
293
294 bool vdds_dsi_enabled;
295 struct regulator *vdds_dsi_reg;
296
297 struct {
298 enum dsi_vc_source source;
299 struct omap_dss_device *dssdev;
300 enum fifo_size fifo_size;
301 int vc_id;
302 } vc[4];
303
304 struct mutex lock;
305 struct semaphore bus_lock;
306
307 unsigned pll_locked;
308
309 spinlock_t irq_lock;
310 struct dsi_isr_tables isr_tables;
311 /* space for a copy used by the interrupt handler */
312 struct dsi_isr_tables isr_tables_copy;
313
314 int update_channel;
315 #ifdef DSI_PERF_MEASURE
316 unsigned update_bytes;
317 #endif
318
319 bool te_enabled;
320 bool ulps_enabled;
321
322 void (*framedone_callback)(int, void *);
323 void *framedone_data;
324
325 struct delayed_work framedone_timeout_work;
326
327 #ifdef DSI_CATCH_MISSING_TE
328 struct timer_list te_timer;
329 #endif
330
331 unsigned long cache_req_pck;
332 unsigned long cache_clk_freq;
333 struct dsi_clock_info cache_cinfo;
334
335 u32 errors;
336 spinlock_t errors_lock;
337 #ifdef DSI_PERF_MEASURE
338 ktime_t perf_setup_time;
339 ktime_t perf_start_time;
340 #endif
341 int debug_read;
342 int debug_write;
343
344 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
345 spinlock_t irq_stats_lock;
346 struct dsi_irq_stats irq_stats;
347 #endif
348 /* DSI PLL Parameter Ranges */
349 unsigned long regm_max, regn_max;
350 unsigned long regm_dispc_max, regm_dsi_max;
351 unsigned long fint_min, fint_max;
352 unsigned long lpdiv_max;
353
354 unsigned num_lanes_supported;
355 unsigned line_buffer_size;
356
357 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
358 unsigned num_lanes_used;
359
360 unsigned scp_clk_refcount;
361
362 struct dss_lcd_mgr_config mgr_config;
363 struct omap_video_timings timings;
364 enum omap_dss_dsi_pixel_format pix_fmt;
365 enum omap_dss_dsi_mode mode;
366 struct omap_dss_dsi_videomode_timings vm_timings;
367
368 struct omap_dss_device output;
369 };
370
371 struct dsi_packet_sent_handler_data {
372 struct platform_device *dsidev;
373 struct completion *completion;
374 };
375
376 #ifdef DSI_PERF_MEASURE
377 static bool dsi_perf;
378 module_param(dsi_perf, bool, 0644);
379 #endif
380
381 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
382 {
383 return dev_get_drvdata(&dsidev->dev);
384 }
385
386 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
387 {
388 return to_platform_device(dssdev->dev);
389 }
390
391 struct platform_device *dsi_get_dsidev_from_id(int module)
392 {
393 struct omap_dss_device *out;
394 enum omap_dss_output_id id;
395
396 switch (module) {
397 case 0:
398 id = OMAP_DSS_OUTPUT_DSI1;
399 break;
400 case 1:
401 id = OMAP_DSS_OUTPUT_DSI2;
402 break;
403 default:
404 return NULL;
405 }
406
407 out = omap_dss_get_output(id);
408
409 return out ? to_platform_device(out->dev) : NULL;
410 }
411
412 static inline void dsi_write_reg(struct platform_device *dsidev,
413 const struct dsi_reg idx, u32 val)
414 {
415 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
416
417 __raw_writel(val, dsi->base + idx.idx);
418 }
419
420 static inline u32 dsi_read_reg(struct platform_device *dsidev,
421 const struct dsi_reg idx)
422 {
423 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
424
425 return __raw_readl(dsi->base + idx.idx);
426 }
427
428 static void dsi_bus_lock(struct omap_dss_device *dssdev)
429 {
430 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
431 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
432
433 down(&dsi->bus_lock);
434 }
435
436 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
437 {
438 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
439 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
440
441 up(&dsi->bus_lock);
442 }
443
444 static bool dsi_bus_is_locked(struct platform_device *dsidev)
445 {
446 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
447
448 return dsi->bus_lock.count == 0;
449 }
450
451 static void dsi_completion_handler(void *data, u32 mask)
452 {
453 complete((struct completion *)data);
454 }
455
456 static inline int wait_for_bit_change(struct platform_device *dsidev,
457 const struct dsi_reg idx, int bitnum, int value)
458 {
459 unsigned long timeout;
460 ktime_t wait;
461 int t;
462
463 /* first busyloop to see if the bit changes right away */
464 t = 100;
465 while (t-- > 0) {
466 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
467 return value;
468 }
469
470 /* then loop for 500ms, sleeping for 1ms in between */
471 timeout = jiffies + msecs_to_jiffies(500);
472 while (time_before(jiffies, timeout)) {
473 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
474 return value;
475
476 wait = ns_to_ktime(1000 * 1000);
477 set_current_state(TASK_UNINTERRUPTIBLE);
478 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
479 }
480
481 return !value;
482 }
483
484 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
485 {
486 switch (fmt) {
487 case OMAP_DSS_DSI_FMT_RGB888:
488 case OMAP_DSS_DSI_FMT_RGB666:
489 return 24;
490 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
491 return 18;
492 case OMAP_DSS_DSI_FMT_RGB565:
493 return 16;
494 default:
495 BUG();
496 return 0;
497 }
498 }
499
500 #ifdef DSI_PERF_MEASURE
501 static void dsi_perf_mark_setup(struct platform_device *dsidev)
502 {
503 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
504 dsi->perf_setup_time = ktime_get();
505 }
506
507 static void dsi_perf_mark_start(struct platform_device *dsidev)
508 {
509 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
510 dsi->perf_start_time = ktime_get();
511 }
512
513 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
514 {
515 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
516 ktime_t t, setup_time, trans_time;
517 u32 total_bytes;
518 u32 setup_us, trans_us, total_us;
519
520 if (!dsi_perf)
521 return;
522
523 t = ktime_get();
524
525 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
526 setup_us = (u32)ktime_to_us(setup_time);
527 if (setup_us == 0)
528 setup_us = 1;
529
530 trans_time = ktime_sub(t, dsi->perf_start_time);
531 trans_us = (u32)ktime_to_us(trans_time);
532 if (trans_us == 0)
533 trans_us = 1;
534
535 total_us = setup_us + trans_us;
536
537 total_bytes = dsi->update_bytes;
538
539 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
540 "%u bytes, %u kbytes/sec\n",
541 name,
542 setup_us,
543 trans_us,
544 total_us,
545 1000*1000 / total_us,
546 total_bytes,
547 total_bytes * 1000 / total_us);
548 }
549 #else
550 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
551 {
552 }
553
554 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
555 {
556 }
557
558 static inline void dsi_perf_show(struct platform_device *dsidev,
559 const char *name)
560 {
561 }
562 #endif
563
564 static int verbose_irq;
565
566 static void print_irq_status(u32 status)
567 {
568 if (status == 0)
569 return;
570
571 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
572 return;
573
574 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
575
576 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
577 status,
578 verbose_irq ? PIS(VC0) : "",
579 verbose_irq ? PIS(VC1) : "",
580 verbose_irq ? PIS(VC2) : "",
581 verbose_irq ? PIS(VC3) : "",
582 PIS(WAKEUP),
583 PIS(RESYNC),
584 PIS(PLL_LOCK),
585 PIS(PLL_UNLOCK),
586 PIS(PLL_RECALL),
587 PIS(COMPLEXIO_ERR),
588 PIS(HS_TX_TIMEOUT),
589 PIS(LP_RX_TIMEOUT),
590 PIS(TE_TRIGGER),
591 PIS(ACK_TRIGGER),
592 PIS(SYNC_LOST),
593 PIS(LDO_POWER_GOOD),
594 PIS(TA_TIMEOUT));
595 #undef PIS
596 }
597
598 static void print_irq_status_vc(int channel, u32 status)
599 {
600 if (status == 0)
601 return;
602
603 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
604 return;
605
606 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
607
608 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
609 channel,
610 status,
611 PIS(CS),
612 PIS(ECC_CORR),
613 PIS(ECC_NO_CORR),
614 verbose_irq ? PIS(PACKET_SENT) : "",
615 PIS(BTA),
616 PIS(FIFO_TX_OVF),
617 PIS(FIFO_RX_OVF),
618 PIS(FIFO_TX_UDF),
619 PIS(PP_BUSY_CHANGE));
620 #undef PIS
621 }
622
623 static void print_irq_status_cio(u32 status)
624 {
625 if (status == 0)
626 return;
627
628 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
629
630 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
631 status,
632 PIS(ERRSYNCESC1),
633 PIS(ERRSYNCESC2),
634 PIS(ERRSYNCESC3),
635 PIS(ERRESC1),
636 PIS(ERRESC2),
637 PIS(ERRESC3),
638 PIS(ERRCONTROL1),
639 PIS(ERRCONTROL2),
640 PIS(ERRCONTROL3),
641 PIS(STATEULPS1),
642 PIS(STATEULPS2),
643 PIS(STATEULPS3),
644 PIS(ERRCONTENTIONLP0_1),
645 PIS(ERRCONTENTIONLP1_1),
646 PIS(ERRCONTENTIONLP0_2),
647 PIS(ERRCONTENTIONLP1_2),
648 PIS(ERRCONTENTIONLP0_3),
649 PIS(ERRCONTENTIONLP1_3),
650 PIS(ULPSACTIVENOT_ALL0),
651 PIS(ULPSACTIVENOT_ALL1));
652 #undef PIS
653 }
654
655 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
656 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
657 u32 *vcstatus, u32 ciostatus)
658 {
659 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
660 int i;
661
662 spin_lock(&dsi->irq_stats_lock);
663
664 dsi->irq_stats.irq_count++;
665 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
666
667 for (i = 0; i < 4; ++i)
668 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
669
670 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
671
672 spin_unlock(&dsi->irq_stats_lock);
673 }
674 #else
675 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
676 #endif
677
678 static int debug_irq;
679
680 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
681 u32 *vcstatus, u32 ciostatus)
682 {
683 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
684 int i;
685
686 if (irqstatus & DSI_IRQ_ERROR_MASK) {
687 DSSERR("DSI error, irqstatus %x\n", irqstatus);
688 print_irq_status(irqstatus);
689 spin_lock(&dsi->errors_lock);
690 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
691 spin_unlock(&dsi->errors_lock);
692 } else if (debug_irq) {
693 print_irq_status(irqstatus);
694 }
695
696 for (i = 0; i < 4; ++i) {
697 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
698 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
699 i, vcstatus[i]);
700 print_irq_status_vc(i, vcstatus[i]);
701 } else if (debug_irq) {
702 print_irq_status_vc(i, vcstatus[i]);
703 }
704 }
705
706 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
707 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
708 print_irq_status_cio(ciostatus);
709 } else if (debug_irq) {
710 print_irq_status_cio(ciostatus);
711 }
712 }
713
714 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
715 unsigned isr_array_size, u32 irqstatus)
716 {
717 struct dsi_isr_data *isr_data;
718 int i;
719
720 for (i = 0; i < isr_array_size; i++) {
721 isr_data = &isr_array[i];
722 if (isr_data->isr && isr_data->mask & irqstatus)
723 isr_data->isr(isr_data->arg, irqstatus);
724 }
725 }
726
727 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
728 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
729 {
730 int i;
731
732 dsi_call_isrs(isr_tables->isr_table,
733 ARRAY_SIZE(isr_tables->isr_table),
734 irqstatus);
735
736 for (i = 0; i < 4; ++i) {
737 if (vcstatus[i] == 0)
738 continue;
739 dsi_call_isrs(isr_tables->isr_table_vc[i],
740 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
741 vcstatus[i]);
742 }
743
744 if (ciostatus != 0)
745 dsi_call_isrs(isr_tables->isr_table_cio,
746 ARRAY_SIZE(isr_tables->isr_table_cio),
747 ciostatus);
748 }
749
750 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
751 {
752 struct platform_device *dsidev;
753 struct dsi_data *dsi;
754 u32 irqstatus, vcstatus[4], ciostatus;
755 int i;
756
757 dsidev = (struct platform_device *) arg;
758 dsi = dsi_get_dsidrv_data(dsidev);
759
760 spin_lock(&dsi->irq_lock);
761
762 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
763
764 /* IRQ is not for us */
765 if (!irqstatus) {
766 spin_unlock(&dsi->irq_lock);
767 return IRQ_NONE;
768 }
769
770 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
771 /* flush posted write */
772 dsi_read_reg(dsidev, DSI_IRQSTATUS);
773
774 for (i = 0; i < 4; ++i) {
775 if ((irqstatus & (1 << i)) == 0) {
776 vcstatus[i] = 0;
777 continue;
778 }
779
780 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
781
782 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
783 /* flush posted write */
784 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
785 }
786
787 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
788 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
789
790 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
791 /* flush posted write */
792 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
793 } else {
794 ciostatus = 0;
795 }
796
797 #ifdef DSI_CATCH_MISSING_TE
798 if (irqstatus & DSI_IRQ_TE_TRIGGER)
799 del_timer(&dsi->te_timer);
800 #endif
801
802 /* make a copy and unlock, so that isrs can unregister
803 * themselves */
804 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
805 sizeof(dsi->isr_tables));
806
807 spin_unlock(&dsi->irq_lock);
808
809 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
810
811 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
812
813 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
814
815 return IRQ_HANDLED;
816 }
817
818 /* dsi->irq_lock has to be locked by the caller */
819 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
820 struct dsi_isr_data *isr_array,
821 unsigned isr_array_size, u32 default_mask,
822 const struct dsi_reg enable_reg,
823 const struct dsi_reg status_reg)
824 {
825 struct dsi_isr_data *isr_data;
826 u32 mask;
827 u32 old_mask;
828 int i;
829
830 mask = default_mask;
831
832 for (i = 0; i < isr_array_size; i++) {
833 isr_data = &isr_array[i];
834
835 if (isr_data->isr == NULL)
836 continue;
837
838 mask |= isr_data->mask;
839 }
840
841 old_mask = dsi_read_reg(dsidev, enable_reg);
842 /* clear the irqstatus for newly enabled irqs */
843 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
844 dsi_write_reg(dsidev, enable_reg, mask);
845
846 /* flush posted writes */
847 dsi_read_reg(dsidev, enable_reg);
848 dsi_read_reg(dsidev, status_reg);
849 }
850
851 /* dsi->irq_lock has to be locked by the caller */
852 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
853 {
854 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
855 u32 mask = DSI_IRQ_ERROR_MASK;
856 #ifdef DSI_CATCH_MISSING_TE
857 mask |= DSI_IRQ_TE_TRIGGER;
858 #endif
859 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
860 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
861 DSI_IRQENABLE, DSI_IRQSTATUS);
862 }
863
864 /* dsi->irq_lock has to be locked by the caller */
865 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
866 {
867 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
868
869 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
870 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
871 DSI_VC_IRQ_ERROR_MASK,
872 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
873 }
874
875 /* dsi->irq_lock has to be locked by the caller */
876 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
877 {
878 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
879
880 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
881 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
882 DSI_CIO_IRQ_ERROR_MASK,
883 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
884 }
885
886 static void _dsi_initialize_irq(struct platform_device *dsidev)
887 {
888 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
889 unsigned long flags;
890 int vc;
891
892 spin_lock_irqsave(&dsi->irq_lock, flags);
893
894 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
895
896 _omap_dsi_set_irqs(dsidev);
897 for (vc = 0; vc < 4; ++vc)
898 _omap_dsi_set_irqs_vc(dsidev, vc);
899 _omap_dsi_set_irqs_cio(dsidev);
900
901 spin_unlock_irqrestore(&dsi->irq_lock, flags);
902 }
903
904 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
905 struct dsi_isr_data *isr_array, unsigned isr_array_size)
906 {
907 struct dsi_isr_data *isr_data;
908 int free_idx;
909 int i;
910
911 BUG_ON(isr == NULL);
912
913 /* check for duplicate entry and find a free slot */
914 free_idx = -1;
915 for (i = 0; i < isr_array_size; i++) {
916 isr_data = &isr_array[i];
917
918 if (isr_data->isr == isr && isr_data->arg == arg &&
919 isr_data->mask == mask) {
920 return -EINVAL;
921 }
922
923 if (isr_data->isr == NULL && free_idx == -1)
924 free_idx = i;
925 }
926
927 if (free_idx == -1)
928 return -EBUSY;
929
930 isr_data = &isr_array[free_idx];
931 isr_data->isr = isr;
932 isr_data->arg = arg;
933 isr_data->mask = mask;
934
935 return 0;
936 }
937
938 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
939 struct dsi_isr_data *isr_array, unsigned isr_array_size)
940 {
941 struct dsi_isr_data *isr_data;
942 int i;
943
944 for (i = 0; i < isr_array_size; i++) {
945 isr_data = &isr_array[i];
946 if (isr_data->isr != isr || isr_data->arg != arg ||
947 isr_data->mask != mask)
948 continue;
949
950 isr_data->isr = NULL;
951 isr_data->arg = NULL;
952 isr_data->mask = 0;
953
954 return 0;
955 }
956
957 return -EINVAL;
958 }
959
960 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
961 void *arg, u32 mask)
962 {
963 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
964 unsigned long flags;
965 int r;
966
967 spin_lock_irqsave(&dsi->irq_lock, flags);
968
969 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
970 ARRAY_SIZE(dsi->isr_tables.isr_table));
971
972 if (r == 0)
973 _omap_dsi_set_irqs(dsidev);
974
975 spin_unlock_irqrestore(&dsi->irq_lock, flags);
976
977 return r;
978 }
979
980 static int dsi_unregister_isr(struct platform_device *dsidev,
981 omap_dsi_isr_t isr, void *arg, u32 mask)
982 {
983 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
984 unsigned long flags;
985 int r;
986
987 spin_lock_irqsave(&dsi->irq_lock, flags);
988
989 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
990 ARRAY_SIZE(dsi->isr_tables.isr_table));
991
992 if (r == 0)
993 _omap_dsi_set_irqs(dsidev);
994
995 spin_unlock_irqrestore(&dsi->irq_lock, flags);
996
997 return r;
998 }
999
1000 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1001 omap_dsi_isr_t isr, void *arg, u32 mask)
1002 {
1003 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1004 unsigned long flags;
1005 int r;
1006
1007 spin_lock_irqsave(&dsi->irq_lock, flags);
1008
1009 r = _dsi_register_isr(isr, arg, mask,
1010 dsi->isr_tables.isr_table_vc[channel],
1011 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1012
1013 if (r == 0)
1014 _omap_dsi_set_irqs_vc(dsidev, channel);
1015
1016 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1017
1018 return r;
1019 }
1020
1021 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1022 omap_dsi_isr_t isr, void *arg, u32 mask)
1023 {
1024 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1025 unsigned long flags;
1026 int r;
1027
1028 spin_lock_irqsave(&dsi->irq_lock, flags);
1029
1030 r = _dsi_unregister_isr(isr, arg, mask,
1031 dsi->isr_tables.isr_table_vc[channel],
1032 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1033
1034 if (r == 0)
1035 _omap_dsi_set_irqs_vc(dsidev, channel);
1036
1037 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1038
1039 return r;
1040 }
1041
1042 static int dsi_register_isr_cio(struct platform_device *dsidev,
1043 omap_dsi_isr_t isr, void *arg, u32 mask)
1044 {
1045 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1046 unsigned long flags;
1047 int r;
1048
1049 spin_lock_irqsave(&dsi->irq_lock, flags);
1050
1051 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1052 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1053
1054 if (r == 0)
1055 _omap_dsi_set_irqs_cio(dsidev);
1056
1057 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1058
1059 return r;
1060 }
1061
1062 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1063 omap_dsi_isr_t isr, void *arg, u32 mask)
1064 {
1065 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1066 unsigned long flags;
1067 int r;
1068
1069 spin_lock_irqsave(&dsi->irq_lock, flags);
1070
1071 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1072 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1073
1074 if (r == 0)
1075 _omap_dsi_set_irqs_cio(dsidev);
1076
1077 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1078
1079 return r;
1080 }
1081
1082 static u32 dsi_get_errors(struct platform_device *dsidev)
1083 {
1084 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1085 unsigned long flags;
1086 u32 e;
1087 spin_lock_irqsave(&dsi->errors_lock, flags);
1088 e = dsi->errors;
1089 dsi->errors = 0;
1090 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1091 return e;
1092 }
1093
1094 int dsi_runtime_get(struct platform_device *dsidev)
1095 {
1096 int r;
1097 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1098
1099 DSSDBG("dsi_runtime_get\n");
1100
1101 r = pm_runtime_get_sync(&dsi->pdev->dev);
1102 WARN_ON(r < 0);
1103 return r < 0 ? r : 0;
1104 }
1105
1106 void dsi_runtime_put(struct platform_device *dsidev)
1107 {
1108 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1109 int r;
1110
1111 DSSDBG("dsi_runtime_put\n");
1112
1113 r = pm_runtime_put_sync(&dsi->pdev->dev);
1114 WARN_ON(r < 0 && r != -ENOSYS);
1115 }
1116
1117 static int dsi_regulator_init(struct platform_device *dsidev)
1118 {
1119 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1120 struct regulator *vdds_dsi;
1121
1122 if (dsi->vdds_dsi_reg != NULL)
1123 return 0;
1124
1125 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdds_dsi");
1126
1127 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
1128 if (IS_ERR(vdds_dsi))
1129 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "VCXIO");
1130
1131 if (IS_ERR(vdds_dsi)) {
1132 DSSERR("can't get VDDS_DSI regulator\n");
1133 return PTR_ERR(vdds_dsi);
1134 }
1135
1136 dsi->vdds_dsi_reg = vdds_dsi;
1137
1138 return 0;
1139 }
1140
1141 /* source clock for DSI PLL. this could also be PCLKFREE */
1142 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1143 bool enable)
1144 {
1145 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1146
1147 if (enable)
1148 clk_prepare_enable(dsi->sys_clk);
1149 else
1150 clk_disable_unprepare(dsi->sys_clk);
1151
1152 if (enable && dsi->pll_locked) {
1153 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1154 DSSERR("cannot lock PLL when enabling clocks\n");
1155 }
1156 }
1157
1158 static void _dsi_print_reset_status(struct platform_device *dsidev)
1159 {
1160 u32 l;
1161 int b0, b1, b2;
1162
1163 /* A dummy read using the SCP interface to any DSIPHY register is
1164 * required after DSIPHY reset to complete the reset of the DSI complex
1165 * I/O. */
1166 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1167
1168 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1169 b0 = 28;
1170 b1 = 27;
1171 b2 = 26;
1172 } else {
1173 b0 = 24;
1174 b1 = 25;
1175 b2 = 26;
1176 }
1177
1178 #define DSI_FLD_GET(fld, start, end)\
1179 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1180
1181 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1182 DSI_FLD_GET(PLL_STATUS, 0, 0),
1183 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1184 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1185 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1186 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1187 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1188 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1189 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1190
1191 #undef DSI_FLD_GET
1192 }
1193
1194 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1195 {
1196 DSSDBG("dsi_if_enable(%d)\n", enable);
1197
1198 enable = enable ? 1 : 0;
1199 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1200
1201 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1202 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1203 return -EIO;
1204 }
1205
1206 return 0;
1207 }
1208
1209 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1210 {
1211 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1212
1213 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1214 }
1215
1216 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1217 {
1218 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1219
1220 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1221 }
1222
1223 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1224 {
1225 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1226
1227 return dsi->current_cinfo.clkin4ddr / 16;
1228 }
1229
1230 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1231 {
1232 unsigned long r;
1233 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1234
1235 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1236 /* DSI FCLK source is DSS_CLK_FCK */
1237 r = clk_get_rate(dsi->dss_clk);
1238 } else {
1239 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1240 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1241 }
1242
1243 return r;
1244 }
1245
1246 static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo,
1247 unsigned long lp_clk_min, unsigned long lp_clk_max)
1248 {
1249 unsigned long dsi_fclk = cinfo->dsi_pll_hsdiv_dsi_clk;
1250 unsigned lp_clk_div;
1251 unsigned long lp_clk;
1252
1253 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1254 lp_clk = dsi_fclk / 2 / lp_clk_div;
1255
1256 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1257 return -EINVAL;
1258
1259 cinfo->lp_clk_div = lp_clk_div;
1260 cinfo->lp_clk = lp_clk;
1261
1262 return 0;
1263 }
1264
1265 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1266 {
1267 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1268 unsigned long dsi_fclk;
1269 unsigned lp_clk_div;
1270 unsigned long lp_clk;
1271
1272 lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
1273
1274 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1275 return -EINVAL;
1276
1277 dsi_fclk = dsi_fclk_rate(dsidev);
1278
1279 lp_clk = dsi_fclk / 2 / lp_clk_div;
1280
1281 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1282 dsi->current_cinfo.lp_clk = lp_clk;
1283 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1284
1285 /* LP_CLK_DIVISOR */
1286 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1287
1288 /* LP_RX_SYNCHRO_ENABLE */
1289 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1290
1291 return 0;
1292 }
1293
1294 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1295 {
1296 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1297
1298 if (dsi->scp_clk_refcount++ == 0)
1299 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1300 }
1301
1302 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1303 {
1304 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1305
1306 WARN_ON(dsi->scp_clk_refcount == 0);
1307 if (--dsi->scp_clk_refcount == 0)
1308 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1309 }
1310
1311 enum dsi_pll_power_state {
1312 DSI_PLL_POWER_OFF = 0x0,
1313 DSI_PLL_POWER_ON_HSCLK = 0x1,
1314 DSI_PLL_POWER_ON_ALL = 0x2,
1315 DSI_PLL_POWER_ON_DIV = 0x3,
1316 };
1317
1318 static int dsi_pll_power(struct platform_device *dsidev,
1319 enum dsi_pll_power_state state)
1320 {
1321 int t = 0;
1322
1323 /* DSI-PLL power command 0x3 is not working */
1324 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1325 state == DSI_PLL_POWER_ON_DIV)
1326 state = DSI_PLL_POWER_ON_ALL;
1327
1328 /* PLL_PWR_CMD */
1329 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1330
1331 /* PLL_PWR_STATUS */
1332 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1333 if (++t > 1000) {
1334 DSSERR("Failed to set DSI PLL power mode to %d\n",
1335 state);
1336 return -ENODEV;
1337 }
1338 udelay(1);
1339 }
1340
1341 return 0;
1342 }
1343
1344 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
1345 {
1346 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1347 return clk_get_rate(dsi->sys_clk);
1348 }
1349
1350 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
1351 unsigned long out_min, dsi_hsdiv_calc_func func, void *data)
1352 {
1353 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1354 int regm, regm_start, regm_stop;
1355 unsigned long out_max;
1356 unsigned long out;
1357
1358 out_min = out_min ? out_min : 1;
1359 out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1360
1361 regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul);
1362 regm_stop = min(pll / out_min, dsi->regm_dispc_max);
1363
1364 for (regm = regm_start; regm <= regm_stop; ++regm) {
1365 out = pll / regm;
1366
1367 if (func(regm, out, data))
1368 return true;
1369 }
1370
1371 return false;
1372 }
1373
1374 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
1375 unsigned long pll_min, unsigned long pll_max,
1376 dsi_pll_calc_func func, void *data)
1377 {
1378 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1379 int regn, regn_start, regn_stop;
1380 int regm, regm_start, regm_stop;
1381 unsigned long fint, pll;
1382 const unsigned long pll_hw_max = 1800000000;
1383 unsigned long fint_hw_min, fint_hw_max;
1384
1385 fint_hw_min = dsi->fint_min;
1386 fint_hw_max = dsi->fint_max;
1387
1388 regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
1389 regn_stop = min(clkin / fint_hw_min, dsi->regn_max);
1390
1391 pll_max = pll_max ? pll_max : ULONG_MAX;
1392
1393 for (regn = regn_start; regn <= regn_stop; ++regn) {
1394 fint = clkin / regn;
1395
1396 regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
1397 1ul);
1398 regm_stop = min3(pll_max / fint / 2,
1399 pll_hw_max / fint / 2,
1400 dsi->regm_max);
1401
1402 for (regm = regm_start; regm <= regm_stop; ++regm) {
1403 pll = 2 * regm * fint;
1404
1405 if (func(regn, regm, fint, pll, data))
1406 return true;
1407 }
1408 }
1409
1410 return false;
1411 }
1412
1413 /* calculate clock rates using dividers in cinfo */
1414 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1415 struct dsi_clock_info *cinfo)
1416 {
1417 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1418
1419 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1420 return -EINVAL;
1421
1422 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1423 return -EINVAL;
1424
1425 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1426 return -EINVAL;
1427
1428 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1429 return -EINVAL;
1430
1431 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1432 cinfo->fint = cinfo->clkin / cinfo->regn;
1433
1434 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1435 return -EINVAL;
1436
1437 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1438
1439 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1440 return -EINVAL;
1441
1442 if (cinfo->regm_dispc > 0)
1443 cinfo->dsi_pll_hsdiv_dispc_clk =
1444 cinfo->clkin4ddr / cinfo->regm_dispc;
1445 else
1446 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1447
1448 if (cinfo->regm_dsi > 0)
1449 cinfo->dsi_pll_hsdiv_dsi_clk =
1450 cinfo->clkin4ddr / cinfo->regm_dsi;
1451 else
1452 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1453
1454 return 0;
1455 }
1456
1457 static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
1458 {
1459 unsigned long max_dsi_fck;
1460
1461 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1462
1463 cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1464 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1465 }
1466
1467 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1468 struct dsi_clock_info *cinfo)
1469 {
1470 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1471 int r = 0;
1472 u32 l;
1473 int f = 0;
1474 u8 regn_start, regn_end, regm_start, regm_end;
1475 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1476
1477 DSSDBG("DSI PLL clock config starts");
1478
1479 dsi->current_cinfo.clkin = cinfo->clkin;
1480 dsi->current_cinfo.fint = cinfo->fint;
1481 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1482 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1483 cinfo->dsi_pll_hsdiv_dispc_clk;
1484 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1485 cinfo->dsi_pll_hsdiv_dsi_clk;
1486
1487 dsi->current_cinfo.regn = cinfo->regn;
1488 dsi->current_cinfo.regm = cinfo->regm;
1489 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1490 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1491
1492 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1493
1494 DSSDBG("clkin rate %ld\n", cinfo->clkin);
1495
1496 /* DSIPHY == CLKIN4DDR */
1497 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1498 cinfo->regm,
1499 cinfo->regn,
1500 cinfo->clkin,
1501 cinfo->clkin4ddr);
1502
1503 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1504 cinfo->clkin4ddr / 1000 / 1000 / 2);
1505
1506 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1507
1508 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1509 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1510 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1511 cinfo->dsi_pll_hsdiv_dispc_clk);
1512 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1513 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1514 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1515 cinfo->dsi_pll_hsdiv_dsi_clk);
1516
1517 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1518 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1519 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1520 &regm_dispc_end);
1521 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1522 &regm_dsi_end);
1523
1524 /* DSI_PLL_AUTOMODE = manual */
1525 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1526
1527 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1528 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1529 /* DSI_PLL_REGN */
1530 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1531 /* DSI_PLL_REGM */
1532 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1533 /* DSI_CLOCK_DIV */
1534 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1535 regm_dispc_start, regm_dispc_end);
1536 /* DSIPROTO_CLOCK_DIV */
1537 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1538 regm_dsi_start, regm_dsi_end);
1539 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1540
1541 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1542
1543 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1544
1545 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1546 f = cinfo->fint < 1000000 ? 0x3 :
1547 cinfo->fint < 1250000 ? 0x4 :
1548 cinfo->fint < 1500000 ? 0x5 :
1549 cinfo->fint < 1750000 ? 0x6 :
1550 0x7;
1551
1552 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1553 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1554 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1555
1556 l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
1557 }
1558
1559 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1560 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1561 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1562 if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1563 l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
1564 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1565
1566 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1567
1568 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1569 DSSERR("dsi pll go bit not going down.\n");
1570 r = -EIO;
1571 goto err;
1572 }
1573
1574 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1575 DSSERR("cannot lock PLL\n");
1576 r = -EIO;
1577 goto err;
1578 }
1579
1580 dsi->pll_locked = 1;
1581
1582 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1583 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1584 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1585 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1586 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1587 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1588 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1589 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1590 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1591 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1592 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1593 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1594 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1595 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1596 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1597 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1598
1599 DSSDBG("PLL config done\n");
1600 err:
1601 return r;
1602 }
1603
1604 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1605 bool enable_hsdiv)
1606 {
1607 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1608 int r = 0;
1609 enum dsi_pll_power_state pwstate;
1610
1611 DSSDBG("PLL init\n");
1612
1613 /*
1614 * It seems that on many OMAPs we need to enable both to have a
1615 * functional HSDivider.
1616 */
1617 enable_hsclk = enable_hsdiv = true;
1618
1619 r = dsi_regulator_init(dsidev);
1620 if (r)
1621 return r;
1622
1623 dsi_enable_pll_clock(dsidev, 1);
1624 /*
1625 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1626 */
1627 dsi_enable_scp_clk(dsidev);
1628
1629 if (!dsi->vdds_dsi_enabled) {
1630 r = regulator_enable(dsi->vdds_dsi_reg);
1631 if (r)
1632 goto err0;
1633 dsi->vdds_dsi_enabled = true;
1634 }
1635
1636 /* XXX PLL does not come out of reset without this... */
1637 dispc_pck_free_enable(1);
1638
1639 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1640 DSSERR("PLL not coming out of reset.\n");
1641 r = -ENODEV;
1642 dispc_pck_free_enable(0);
1643 goto err1;
1644 }
1645
1646 /* XXX ... but if left on, we get problems when planes do not
1647 * fill the whole display. No idea about this */
1648 dispc_pck_free_enable(0);
1649
1650 if (enable_hsclk && enable_hsdiv)
1651 pwstate = DSI_PLL_POWER_ON_ALL;
1652 else if (enable_hsclk)
1653 pwstate = DSI_PLL_POWER_ON_HSCLK;
1654 else if (enable_hsdiv)
1655 pwstate = DSI_PLL_POWER_ON_DIV;
1656 else
1657 pwstate = DSI_PLL_POWER_OFF;
1658
1659 r = dsi_pll_power(dsidev, pwstate);
1660
1661 if (r)
1662 goto err1;
1663
1664 DSSDBG("PLL init done\n");
1665
1666 return 0;
1667 err1:
1668 if (dsi->vdds_dsi_enabled) {
1669 regulator_disable(dsi->vdds_dsi_reg);
1670 dsi->vdds_dsi_enabled = false;
1671 }
1672 err0:
1673 dsi_disable_scp_clk(dsidev);
1674 dsi_enable_pll_clock(dsidev, 0);
1675 return r;
1676 }
1677
1678 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1679 {
1680 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1681
1682 dsi->pll_locked = 0;
1683 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1684 if (disconnect_lanes) {
1685 WARN_ON(!dsi->vdds_dsi_enabled);
1686 regulator_disable(dsi->vdds_dsi_reg);
1687 dsi->vdds_dsi_enabled = false;
1688 }
1689
1690 dsi_disable_scp_clk(dsidev);
1691 dsi_enable_pll_clock(dsidev, 0);
1692
1693 DSSDBG("PLL uninit done\n");
1694 }
1695
1696 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1697 struct seq_file *s)
1698 {
1699 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1700 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1701 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1702 int dsi_module = dsi->module_id;
1703
1704 dispc_clk_src = dss_get_dispc_clk_source();
1705 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1706
1707 if (dsi_runtime_get(dsidev))
1708 return;
1709
1710 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1711
1712 seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
1713
1714 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1715
1716 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1717 cinfo->clkin4ddr, cinfo->regm);
1718
1719 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1720 dss_feat_get_clk_source_name(dsi_module == 0 ?
1721 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1722 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1723 cinfo->dsi_pll_hsdiv_dispc_clk,
1724 cinfo->regm_dispc,
1725 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1726 "off" : "on");
1727
1728 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1729 dss_feat_get_clk_source_name(dsi_module == 0 ?
1730 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1731 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1732 cinfo->dsi_pll_hsdiv_dsi_clk,
1733 cinfo->regm_dsi,
1734 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1735 "off" : "on");
1736
1737 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1738
1739 seq_printf(s, "dsi fclk source = %s (%s)\n",
1740 dss_get_generic_clk_source_name(dsi_clk_src),
1741 dss_feat_get_clk_source_name(dsi_clk_src));
1742
1743 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1744
1745 seq_printf(s, "DDR_CLK\t\t%lu\n",
1746 cinfo->clkin4ddr / 4);
1747
1748 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1749
1750 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1751
1752 dsi_runtime_put(dsidev);
1753 }
1754
1755 void dsi_dump_clocks(struct seq_file *s)
1756 {
1757 struct platform_device *dsidev;
1758 int i;
1759
1760 for (i = 0; i < MAX_NUM_DSI; i++) {
1761 dsidev = dsi_get_dsidev_from_id(i);
1762 if (dsidev)
1763 dsi_dump_dsidev_clocks(dsidev, s);
1764 }
1765 }
1766
1767 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1768 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1769 struct seq_file *s)
1770 {
1771 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1772 unsigned long flags;
1773 struct dsi_irq_stats stats;
1774
1775 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1776
1777 stats = dsi->irq_stats;
1778 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1779 dsi->irq_stats.last_reset = jiffies;
1780
1781 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1782
1783 seq_printf(s, "period %u ms\n",
1784 jiffies_to_msecs(jiffies - stats.last_reset));
1785
1786 seq_printf(s, "irqs %d\n", stats.irq_count);
1787 #define PIS(x) \
1788 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1789
1790 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1791 PIS(VC0);
1792 PIS(VC1);
1793 PIS(VC2);
1794 PIS(VC3);
1795 PIS(WAKEUP);
1796 PIS(RESYNC);
1797 PIS(PLL_LOCK);
1798 PIS(PLL_UNLOCK);
1799 PIS(PLL_RECALL);
1800 PIS(COMPLEXIO_ERR);
1801 PIS(HS_TX_TIMEOUT);
1802 PIS(LP_RX_TIMEOUT);
1803 PIS(TE_TRIGGER);
1804 PIS(ACK_TRIGGER);
1805 PIS(SYNC_LOST);
1806 PIS(LDO_POWER_GOOD);
1807 PIS(TA_TIMEOUT);
1808 #undef PIS
1809
1810 #define PIS(x) \
1811 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1812 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1813 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1814 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1815 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1816
1817 seq_printf(s, "-- VC interrupts --\n");
1818 PIS(CS);
1819 PIS(ECC_CORR);
1820 PIS(PACKET_SENT);
1821 PIS(FIFO_TX_OVF);
1822 PIS(FIFO_RX_OVF);
1823 PIS(BTA);
1824 PIS(ECC_NO_CORR);
1825 PIS(FIFO_TX_UDF);
1826 PIS(PP_BUSY_CHANGE);
1827 #undef PIS
1828
1829 #define PIS(x) \
1830 seq_printf(s, "%-20s %10d\n", #x, \
1831 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1832
1833 seq_printf(s, "-- CIO interrupts --\n");
1834 PIS(ERRSYNCESC1);
1835 PIS(ERRSYNCESC2);
1836 PIS(ERRSYNCESC3);
1837 PIS(ERRESC1);
1838 PIS(ERRESC2);
1839 PIS(ERRESC3);
1840 PIS(ERRCONTROL1);
1841 PIS(ERRCONTROL2);
1842 PIS(ERRCONTROL3);
1843 PIS(STATEULPS1);
1844 PIS(STATEULPS2);
1845 PIS(STATEULPS3);
1846 PIS(ERRCONTENTIONLP0_1);
1847 PIS(ERRCONTENTIONLP1_1);
1848 PIS(ERRCONTENTIONLP0_2);
1849 PIS(ERRCONTENTIONLP1_2);
1850 PIS(ERRCONTENTIONLP0_3);
1851 PIS(ERRCONTENTIONLP1_3);
1852 PIS(ULPSACTIVENOT_ALL0);
1853 PIS(ULPSACTIVENOT_ALL1);
1854 #undef PIS
1855 }
1856
1857 static void dsi1_dump_irqs(struct seq_file *s)
1858 {
1859 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1860
1861 dsi_dump_dsidev_irqs(dsidev, s);
1862 }
1863
1864 static void dsi2_dump_irqs(struct seq_file *s)
1865 {
1866 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1867
1868 dsi_dump_dsidev_irqs(dsidev, s);
1869 }
1870 #endif
1871
1872 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1873 struct seq_file *s)
1874 {
1875 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1876
1877 if (dsi_runtime_get(dsidev))
1878 return;
1879 dsi_enable_scp_clk(dsidev);
1880
1881 DUMPREG(DSI_REVISION);
1882 DUMPREG(DSI_SYSCONFIG);
1883 DUMPREG(DSI_SYSSTATUS);
1884 DUMPREG(DSI_IRQSTATUS);
1885 DUMPREG(DSI_IRQENABLE);
1886 DUMPREG(DSI_CTRL);
1887 DUMPREG(DSI_COMPLEXIO_CFG1);
1888 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1889 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1890 DUMPREG(DSI_CLK_CTRL);
1891 DUMPREG(DSI_TIMING1);
1892 DUMPREG(DSI_TIMING2);
1893 DUMPREG(DSI_VM_TIMING1);
1894 DUMPREG(DSI_VM_TIMING2);
1895 DUMPREG(DSI_VM_TIMING3);
1896 DUMPREG(DSI_CLK_TIMING);
1897 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1898 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1899 DUMPREG(DSI_COMPLEXIO_CFG2);
1900 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1901 DUMPREG(DSI_VM_TIMING4);
1902 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1903 DUMPREG(DSI_VM_TIMING5);
1904 DUMPREG(DSI_VM_TIMING6);
1905 DUMPREG(DSI_VM_TIMING7);
1906 DUMPREG(DSI_STOPCLK_TIMING);
1907
1908 DUMPREG(DSI_VC_CTRL(0));
1909 DUMPREG(DSI_VC_TE(0));
1910 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1911 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1912 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1913 DUMPREG(DSI_VC_IRQSTATUS(0));
1914 DUMPREG(DSI_VC_IRQENABLE(0));
1915
1916 DUMPREG(DSI_VC_CTRL(1));
1917 DUMPREG(DSI_VC_TE(1));
1918 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1919 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1920 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1921 DUMPREG(DSI_VC_IRQSTATUS(1));
1922 DUMPREG(DSI_VC_IRQENABLE(1));
1923
1924 DUMPREG(DSI_VC_CTRL(2));
1925 DUMPREG(DSI_VC_TE(2));
1926 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1927 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1928 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1929 DUMPREG(DSI_VC_IRQSTATUS(2));
1930 DUMPREG(DSI_VC_IRQENABLE(2));
1931
1932 DUMPREG(DSI_VC_CTRL(3));
1933 DUMPREG(DSI_VC_TE(3));
1934 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1935 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1936 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1937 DUMPREG(DSI_VC_IRQSTATUS(3));
1938 DUMPREG(DSI_VC_IRQENABLE(3));
1939
1940 DUMPREG(DSI_DSIPHY_CFG0);
1941 DUMPREG(DSI_DSIPHY_CFG1);
1942 DUMPREG(DSI_DSIPHY_CFG2);
1943 DUMPREG(DSI_DSIPHY_CFG5);
1944
1945 DUMPREG(DSI_PLL_CONTROL);
1946 DUMPREG(DSI_PLL_STATUS);
1947 DUMPREG(DSI_PLL_GO);
1948 DUMPREG(DSI_PLL_CONFIGURATION1);
1949 DUMPREG(DSI_PLL_CONFIGURATION2);
1950
1951 dsi_disable_scp_clk(dsidev);
1952 dsi_runtime_put(dsidev);
1953 #undef DUMPREG
1954 }
1955
1956 static void dsi1_dump_regs(struct seq_file *s)
1957 {
1958 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1959
1960 dsi_dump_dsidev_regs(dsidev, s);
1961 }
1962
1963 static void dsi2_dump_regs(struct seq_file *s)
1964 {
1965 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1966
1967 dsi_dump_dsidev_regs(dsidev, s);
1968 }
1969
1970 enum dsi_cio_power_state {
1971 DSI_COMPLEXIO_POWER_OFF = 0x0,
1972 DSI_COMPLEXIO_POWER_ON = 0x1,
1973 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1974 };
1975
1976 static int dsi_cio_power(struct platform_device *dsidev,
1977 enum dsi_cio_power_state state)
1978 {
1979 int t = 0;
1980
1981 /* PWR_CMD */
1982 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1983
1984 /* PWR_STATUS */
1985 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1986 26, 25) != state) {
1987 if (++t > 1000) {
1988 DSSERR("failed to set complexio power state to "
1989 "%d\n", state);
1990 return -ENODEV;
1991 }
1992 udelay(1);
1993 }
1994
1995 return 0;
1996 }
1997
1998 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1999 {
2000 int val;
2001
2002 /* line buffer on OMAP3 is 1024 x 24bits */
2003 /* XXX: for some reason using full buffer size causes
2004 * considerable TX slowdown with update sizes that fill the
2005 * whole buffer */
2006 if (!dss_has_feature(FEAT_DSI_GNQ))
2007 return 1023 * 3;
2008
2009 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2010
2011 switch (val) {
2012 case 1:
2013 return 512 * 3; /* 512x24 bits */
2014 case 2:
2015 return 682 * 3; /* 682x24 bits */
2016 case 3:
2017 return 853 * 3; /* 853x24 bits */
2018 case 4:
2019 return 1024 * 3; /* 1024x24 bits */
2020 case 5:
2021 return 1194 * 3; /* 1194x24 bits */
2022 case 6:
2023 return 1365 * 3; /* 1365x24 bits */
2024 case 7:
2025 return 1920 * 3; /* 1920x24 bits */
2026 default:
2027 BUG();
2028 return 0;
2029 }
2030 }
2031
2032 static int dsi_set_lane_config(struct platform_device *dsidev)
2033 {
2034 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2035 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2036 static const enum dsi_lane_function functions[] = {
2037 DSI_LANE_CLK,
2038 DSI_LANE_DATA1,
2039 DSI_LANE_DATA2,
2040 DSI_LANE_DATA3,
2041 DSI_LANE_DATA4,
2042 };
2043 u32 r;
2044 int i;
2045
2046 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2047
2048 for (i = 0; i < dsi->num_lanes_used; ++i) {
2049 unsigned offset = offsets[i];
2050 unsigned polarity, lane_number;
2051 unsigned t;
2052
2053 for (t = 0; t < dsi->num_lanes_supported; ++t)
2054 if (dsi->lanes[t].function == functions[i])
2055 break;
2056
2057 if (t == dsi->num_lanes_supported)
2058 return -EINVAL;
2059
2060 lane_number = t;
2061 polarity = dsi->lanes[t].polarity;
2062
2063 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2064 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2065 }
2066
2067 /* clear the unused lanes */
2068 for (; i < dsi->num_lanes_supported; ++i) {
2069 unsigned offset = offsets[i];
2070
2071 r = FLD_MOD(r, 0, offset + 2, offset);
2072 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2073 }
2074
2075 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2076
2077 return 0;
2078 }
2079
2080 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2081 {
2082 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2083
2084 /* convert time in ns to ddr ticks, rounding up */
2085 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2086 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2087 }
2088
2089 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2090 {
2091 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2092
2093 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2094 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2095 }
2096
2097 static void dsi_cio_timings(struct platform_device *dsidev)
2098 {
2099 u32 r;
2100 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2101 u32 tlpx_half, tclk_trail, tclk_zero;
2102 u32 tclk_prepare;
2103
2104 /* calculate timings */
2105
2106 /* 1 * DDR_CLK = 2 * UI */
2107
2108 /* min 40ns + 4*UI max 85ns + 6*UI */
2109 ths_prepare = ns2ddr(dsidev, 70) + 2;
2110
2111 /* min 145ns + 10*UI */
2112 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2113
2114 /* min max(8*UI, 60ns+4*UI) */
2115 ths_trail = ns2ddr(dsidev, 60) + 5;
2116
2117 /* min 100ns */
2118 ths_exit = ns2ddr(dsidev, 145);
2119
2120 /* tlpx min 50n */
2121 tlpx_half = ns2ddr(dsidev, 25);
2122
2123 /* min 60ns */
2124 tclk_trail = ns2ddr(dsidev, 60) + 2;
2125
2126 /* min 38ns, max 95ns */
2127 tclk_prepare = ns2ddr(dsidev, 65);
2128
2129 /* min tclk-prepare + tclk-zero = 300ns */
2130 tclk_zero = ns2ddr(dsidev, 260);
2131
2132 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2133 ths_prepare, ddr2ns(dsidev, ths_prepare),
2134 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2135 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2136 ths_trail, ddr2ns(dsidev, ths_trail),
2137 ths_exit, ddr2ns(dsidev, ths_exit));
2138
2139 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2140 "tclk_zero %u (%uns)\n",
2141 tlpx_half, ddr2ns(dsidev, tlpx_half),
2142 tclk_trail, ddr2ns(dsidev, tclk_trail),
2143 tclk_zero, ddr2ns(dsidev, tclk_zero));
2144 DSSDBG("tclk_prepare %u (%uns)\n",
2145 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2146
2147 /* program timings */
2148
2149 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2150 r = FLD_MOD(r, ths_prepare, 31, 24);
2151 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2152 r = FLD_MOD(r, ths_trail, 15, 8);
2153 r = FLD_MOD(r, ths_exit, 7, 0);
2154 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2155
2156 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2157 r = FLD_MOD(r, tlpx_half, 20, 16);
2158 r = FLD_MOD(r, tclk_trail, 15, 8);
2159 r = FLD_MOD(r, tclk_zero, 7, 0);
2160
2161 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2162 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
2163 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
2164 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
2165 }
2166
2167 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2168
2169 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2170 r = FLD_MOD(r, tclk_prepare, 7, 0);
2171 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2172 }
2173
2174 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2175 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2176 unsigned mask_p, unsigned mask_n)
2177 {
2178 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2179 int i;
2180 u32 l;
2181 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2182
2183 l = 0;
2184
2185 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2186 unsigned p = dsi->lanes[i].polarity;
2187
2188 if (mask_p & (1 << i))
2189 l |= 1 << (i * 2 + (p ? 0 : 1));
2190
2191 if (mask_n & (1 << i))
2192 l |= 1 << (i * 2 + (p ? 1 : 0));
2193 }
2194
2195 /*
2196 * Bits in REGLPTXSCPDAT4TO0DXDY:
2197 * 17: DY0 18: DX0
2198 * 19: DY1 20: DX1
2199 * 21: DY2 22: DX2
2200 * 23: DY3 24: DX3
2201 * 25: DY4 26: DX4
2202 */
2203
2204 /* Set the lane override configuration */
2205
2206 /* REGLPTXSCPDAT4TO0DXDY */
2207 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2208
2209 /* Enable lane override */
2210
2211 /* ENLPTXSCPDAT */
2212 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2213 }
2214
2215 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2216 {
2217 /* Disable lane override */
2218 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2219 /* Reset the lane override configuration */
2220 /* REGLPTXSCPDAT4TO0DXDY */
2221 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2222 }
2223
2224 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2225 {
2226 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2227 int t, i;
2228 bool in_use[DSI_MAX_NR_LANES];
2229 static const u8 offsets_old[] = { 28, 27, 26 };
2230 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2231 const u8 *offsets;
2232
2233 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2234 offsets = offsets_old;
2235 else
2236 offsets = offsets_new;
2237
2238 for (i = 0; i < dsi->num_lanes_supported; ++i)
2239 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2240
2241 t = 100000;
2242 while (true) {
2243 u32 l;
2244 int ok;
2245
2246 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2247
2248 ok = 0;
2249 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2250 if (!in_use[i] || (l & (1 << offsets[i])))
2251 ok++;
2252 }
2253
2254 if (ok == dsi->num_lanes_supported)
2255 break;
2256
2257 if (--t == 0) {
2258 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2259 if (!in_use[i] || (l & (1 << offsets[i])))
2260 continue;
2261
2262 DSSERR("CIO TXCLKESC%d domain not coming " \
2263 "out of reset\n", i);
2264 }
2265 return -EIO;
2266 }
2267 }
2268
2269 return 0;
2270 }
2271
2272 /* return bitmask of enabled lanes, lane0 being the lsb */
2273 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2274 {
2275 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2276 unsigned mask = 0;
2277 int i;
2278
2279 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2280 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2281 mask |= 1 << i;
2282 }
2283
2284 return mask;
2285 }
2286
2287 static int dsi_cio_init(struct platform_device *dsidev)
2288 {
2289 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2290 int r;
2291 u32 l;
2292
2293 DSSDBG("DSI CIO init starts");
2294
2295 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2296 if (r)
2297 return r;
2298
2299 dsi_enable_scp_clk(dsidev);
2300
2301 /* A dummy read using the SCP interface to any DSIPHY register is
2302 * required after DSIPHY reset to complete the reset of the DSI complex
2303 * I/O. */
2304 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2305
2306 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2307 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2308 r = -EIO;
2309 goto err_scp_clk_dom;
2310 }
2311
2312 r = dsi_set_lane_config(dsidev);
2313 if (r)
2314 goto err_scp_clk_dom;
2315
2316 /* set TX STOP MODE timer to maximum for this operation */
2317 l = dsi_read_reg(dsidev, DSI_TIMING1);
2318 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2319 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2320 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2321 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2322 dsi_write_reg(dsidev, DSI_TIMING1, l);
2323
2324 if (dsi->ulps_enabled) {
2325 unsigned mask_p;
2326 int i;
2327
2328 DSSDBG("manual ulps exit\n");
2329
2330 /* ULPS is exited by Mark-1 state for 1ms, followed by
2331 * stop state. DSS HW cannot do this via the normal
2332 * ULPS exit sequence, as after reset the DSS HW thinks
2333 * that we are not in ULPS mode, and refuses to send the
2334 * sequence. So we need to send the ULPS exit sequence
2335 * manually by setting positive lines high and negative lines
2336 * low for 1ms.
2337 */
2338
2339 mask_p = 0;
2340
2341 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2342 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2343 continue;
2344 mask_p |= 1 << i;
2345 }
2346
2347 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2348 }
2349
2350 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2351 if (r)
2352 goto err_cio_pwr;
2353
2354 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2355 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2356 r = -ENODEV;
2357 goto err_cio_pwr_dom;
2358 }
2359
2360 dsi_if_enable(dsidev, true);
2361 dsi_if_enable(dsidev, false);
2362 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2363
2364 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2365 if (r)
2366 goto err_tx_clk_esc_rst;
2367
2368 if (dsi->ulps_enabled) {
2369 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2370 ktime_t wait = ns_to_ktime(1000 * 1000);
2371 set_current_state(TASK_UNINTERRUPTIBLE);
2372 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2373
2374 /* Disable the override. The lanes should be set to Mark-11
2375 * state by the HW */
2376 dsi_cio_disable_lane_override(dsidev);
2377 }
2378
2379 /* FORCE_TX_STOP_MODE_IO */
2380 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2381
2382 dsi_cio_timings(dsidev);
2383
2384 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2385 /* DDR_CLK_ALWAYS_ON */
2386 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2387 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2388 }
2389
2390 dsi->ulps_enabled = false;
2391
2392 DSSDBG("CIO init done\n");
2393
2394 return 0;
2395
2396 err_tx_clk_esc_rst:
2397 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2398 err_cio_pwr_dom:
2399 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2400 err_cio_pwr:
2401 if (dsi->ulps_enabled)
2402 dsi_cio_disable_lane_override(dsidev);
2403 err_scp_clk_dom:
2404 dsi_disable_scp_clk(dsidev);
2405 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2406 return r;
2407 }
2408
2409 static void dsi_cio_uninit(struct platform_device *dsidev)
2410 {
2411 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2412
2413 /* DDR_CLK_ALWAYS_ON */
2414 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2415
2416 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2417 dsi_disable_scp_clk(dsidev);
2418 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2419 }
2420
2421 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2422 enum fifo_size size1, enum fifo_size size2,
2423 enum fifo_size size3, enum fifo_size size4)
2424 {
2425 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2426 u32 r = 0;
2427 int add = 0;
2428 int i;
2429
2430 dsi->vc[0].fifo_size = size1;
2431 dsi->vc[1].fifo_size = size2;
2432 dsi->vc[2].fifo_size = size3;
2433 dsi->vc[3].fifo_size = size4;
2434
2435 for (i = 0; i < 4; i++) {
2436 u8 v;
2437 int size = dsi->vc[i].fifo_size;
2438
2439 if (add + size > 4) {
2440 DSSERR("Illegal FIFO configuration\n");
2441 BUG();
2442 return;
2443 }
2444
2445 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2446 r |= v << (8 * i);
2447 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2448 add += size;
2449 }
2450
2451 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2452 }
2453
2454 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2455 enum fifo_size size1, enum fifo_size size2,
2456 enum fifo_size size3, enum fifo_size size4)
2457 {
2458 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2459 u32 r = 0;
2460 int add = 0;
2461 int i;
2462
2463 dsi->vc[0].fifo_size = size1;
2464 dsi->vc[1].fifo_size = size2;
2465 dsi->vc[2].fifo_size = size3;
2466 dsi->vc[3].fifo_size = size4;
2467
2468 for (i = 0; i < 4; i++) {
2469 u8 v;
2470 int size = dsi->vc[i].fifo_size;
2471
2472 if (add + size > 4) {
2473 DSSERR("Illegal FIFO configuration\n");
2474 BUG();
2475 return;
2476 }
2477
2478 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2479 r |= v << (8 * i);
2480 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2481 add += size;
2482 }
2483
2484 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2485 }
2486
2487 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2488 {
2489 u32 r;
2490
2491 r = dsi_read_reg(dsidev, DSI_TIMING1);
2492 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2493 dsi_write_reg(dsidev, DSI_TIMING1, r);
2494
2495 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2496 DSSERR("TX_STOP bit not going down\n");
2497 return -EIO;
2498 }
2499
2500 return 0;
2501 }
2502
2503 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2504 {
2505 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2506 }
2507
2508 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2509 {
2510 struct dsi_packet_sent_handler_data *vp_data =
2511 (struct dsi_packet_sent_handler_data *) data;
2512 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2513 const int channel = dsi->update_channel;
2514 u8 bit = dsi->te_enabled ? 30 : 31;
2515
2516 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2517 complete(vp_data->completion);
2518 }
2519
2520 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2521 {
2522 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2523 DECLARE_COMPLETION_ONSTACK(completion);
2524 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2525 int r = 0;
2526 u8 bit;
2527
2528 bit = dsi->te_enabled ? 30 : 31;
2529
2530 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2531 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2532 if (r)
2533 goto err0;
2534
2535 /* Wait for completion only if TE_EN/TE_START is still set */
2536 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2537 if (wait_for_completion_timeout(&completion,
2538 msecs_to_jiffies(10)) == 0) {
2539 DSSERR("Failed to complete previous frame transfer\n");
2540 r = -EIO;
2541 goto err1;
2542 }
2543 }
2544
2545 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2546 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2547
2548 return 0;
2549 err1:
2550 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2551 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2552 err0:
2553 return r;
2554 }
2555
2556 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2557 {
2558 struct dsi_packet_sent_handler_data *l4_data =
2559 (struct dsi_packet_sent_handler_data *) data;
2560 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2561 const int channel = dsi->update_channel;
2562
2563 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2564 complete(l4_data->completion);
2565 }
2566
2567 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2568 {
2569 DECLARE_COMPLETION_ONSTACK(completion);
2570 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2571 int r = 0;
2572
2573 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2574 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2575 if (r)
2576 goto err0;
2577
2578 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2579 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2580 if (wait_for_completion_timeout(&completion,
2581 msecs_to_jiffies(10)) == 0) {
2582 DSSERR("Failed to complete previous l4 transfer\n");
2583 r = -EIO;
2584 goto err1;
2585 }
2586 }
2587
2588 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2589 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2590
2591 return 0;
2592 err1:
2593 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2594 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2595 err0:
2596 return r;
2597 }
2598
2599 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2600 {
2601 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2602
2603 WARN_ON(!dsi_bus_is_locked(dsidev));
2604
2605 WARN_ON(in_interrupt());
2606
2607 if (!dsi_vc_is_enabled(dsidev, channel))
2608 return 0;
2609
2610 switch (dsi->vc[channel].source) {
2611 case DSI_VC_SOURCE_VP:
2612 return dsi_sync_vc_vp(dsidev, channel);
2613 case DSI_VC_SOURCE_L4:
2614 return dsi_sync_vc_l4(dsidev, channel);
2615 default:
2616 BUG();
2617 return -EINVAL;
2618 }
2619 }
2620
2621 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2622 bool enable)
2623 {
2624 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2625 channel, enable);
2626
2627 enable = enable ? 1 : 0;
2628
2629 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2630
2631 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2632 0, enable) != enable) {
2633 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2634 return -EIO;
2635 }
2636
2637 return 0;
2638 }
2639
2640 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2641 {
2642 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2643 u32 r;
2644
2645 DSSDBG("Initial config of virtual channel %d", channel);
2646
2647 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2648
2649 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2650 DSSERR("VC(%d) busy when trying to configure it!\n",
2651 channel);
2652
2653 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2654 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2655 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2656 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2657 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2658 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2659 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2660 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2661 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2662
2663 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2664 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2665
2666 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2667
2668 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2669 }
2670
2671 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2672 enum dsi_vc_source source)
2673 {
2674 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2675
2676 if (dsi->vc[channel].source == source)
2677 return 0;
2678
2679 DSSDBG("Source config of virtual channel %d", channel);
2680
2681 dsi_sync_vc(dsidev, channel);
2682
2683 dsi_vc_enable(dsidev, channel, 0);
2684
2685 /* VC_BUSY */
2686 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2687 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2688 return -EIO;
2689 }
2690
2691 /* SOURCE, 0 = L4, 1 = video port */
2692 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2693
2694 /* DCS_CMD_ENABLE */
2695 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2696 bool enable = source == DSI_VC_SOURCE_VP;
2697 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2698 }
2699
2700 dsi_vc_enable(dsidev, channel, 1);
2701
2702 dsi->vc[channel].source = source;
2703
2704 return 0;
2705 }
2706
2707 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2708 bool enable)
2709 {
2710 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2711 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2712
2713 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2714
2715 WARN_ON(!dsi_bus_is_locked(dsidev));
2716
2717 dsi_vc_enable(dsidev, channel, 0);
2718 dsi_if_enable(dsidev, 0);
2719
2720 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2721
2722 dsi_vc_enable(dsidev, channel, 1);
2723 dsi_if_enable(dsidev, 1);
2724
2725 dsi_force_tx_stop_mode_io(dsidev);
2726
2727 /* start the DDR clock by sending a NULL packet */
2728 if (dsi->vm_timings.ddr_clk_always_on && enable)
2729 dsi_vc_send_null(dssdev, channel);
2730 }
2731
2732 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2733 {
2734 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2735 u32 val;
2736 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2737 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2738 (val >> 0) & 0xff,
2739 (val >> 8) & 0xff,
2740 (val >> 16) & 0xff,
2741 (val >> 24) & 0xff);
2742 }
2743 }
2744
2745 static void dsi_show_rx_ack_with_err(u16 err)
2746 {
2747 DSSERR("\tACK with ERROR (%#x):\n", err);
2748 if (err & (1 << 0))
2749 DSSERR("\t\tSoT Error\n");
2750 if (err & (1 << 1))
2751 DSSERR("\t\tSoT Sync Error\n");
2752 if (err & (1 << 2))
2753 DSSERR("\t\tEoT Sync Error\n");
2754 if (err & (1 << 3))
2755 DSSERR("\t\tEscape Mode Entry Command Error\n");
2756 if (err & (1 << 4))
2757 DSSERR("\t\tLP Transmit Sync Error\n");
2758 if (err & (1 << 5))
2759 DSSERR("\t\tHS Receive Timeout Error\n");
2760 if (err & (1 << 6))
2761 DSSERR("\t\tFalse Control Error\n");
2762 if (err & (1 << 7))
2763 DSSERR("\t\t(reserved7)\n");
2764 if (err & (1 << 8))
2765 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2766 if (err & (1 << 9))
2767 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2768 if (err & (1 << 10))
2769 DSSERR("\t\tChecksum Error\n");
2770 if (err & (1 << 11))
2771 DSSERR("\t\tData type not recognized\n");
2772 if (err & (1 << 12))
2773 DSSERR("\t\tInvalid VC ID\n");
2774 if (err & (1 << 13))
2775 DSSERR("\t\tInvalid Transmission Length\n");
2776 if (err & (1 << 14))
2777 DSSERR("\t\t(reserved14)\n");
2778 if (err & (1 << 15))
2779 DSSERR("\t\tDSI Protocol Violation\n");
2780 }
2781
2782 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2783 int channel)
2784 {
2785 /* RX_FIFO_NOT_EMPTY */
2786 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2787 u32 val;
2788 u8 dt;
2789 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2790 DSSERR("\trawval %#08x\n", val);
2791 dt = FLD_GET(val, 5, 0);
2792 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2793 u16 err = FLD_GET(val, 23, 8);
2794 dsi_show_rx_ack_with_err(err);
2795 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2796 DSSERR("\tDCS short response, 1 byte: %#x\n",
2797 FLD_GET(val, 23, 8));
2798 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2799 DSSERR("\tDCS short response, 2 byte: %#x\n",
2800 FLD_GET(val, 23, 8));
2801 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2802 DSSERR("\tDCS long response, len %d\n",
2803 FLD_GET(val, 23, 8));
2804 dsi_vc_flush_long_data(dsidev, channel);
2805 } else {
2806 DSSERR("\tunknown datatype 0x%02x\n", dt);
2807 }
2808 }
2809 return 0;
2810 }
2811
2812 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2813 {
2814 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2815
2816 if (dsi->debug_write || dsi->debug_read)
2817 DSSDBG("dsi_vc_send_bta %d\n", channel);
2818
2819 WARN_ON(!dsi_bus_is_locked(dsidev));
2820
2821 /* RX_FIFO_NOT_EMPTY */
2822 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2823 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2824 dsi_vc_flush_receive_data(dsidev, channel);
2825 }
2826
2827 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2828
2829 /* flush posted write */
2830 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2831
2832 return 0;
2833 }
2834
2835 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2836 {
2837 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2838 DECLARE_COMPLETION_ONSTACK(completion);
2839 int r = 0;
2840 u32 err;
2841
2842 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2843 &completion, DSI_VC_IRQ_BTA);
2844 if (r)
2845 goto err0;
2846
2847 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2848 DSI_IRQ_ERROR_MASK);
2849 if (r)
2850 goto err1;
2851
2852 r = dsi_vc_send_bta(dsidev, channel);
2853 if (r)
2854 goto err2;
2855
2856 if (wait_for_completion_timeout(&completion,
2857 msecs_to_jiffies(500)) == 0) {
2858 DSSERR("Failed to receive BTA\n");
2859 r = -EIO;
2860 goto err2;
2861 }
2862
2863 err = dsi_get_errors(dsidev);
2864 if (err) {
2865 DSSERR("Error while sending BTA: %x\n", err);
2866 r = -EIO;
2867 goto err2;
2868 }
2869 err2:
2870 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2871 DSI_IRQ_ERROR_MASK);
2872 err1:
2873 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2874 &completion, DSI_VC_IRQ_BTA);
2875 err0:
2876 return r;
2877 }
2878
2879 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2880 int channel, u8 data_type, u16 len, u8 ecc)
2881 {
2882 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2883 u32 val;
2884 u8 data_id;
2885
2886 WARN_ON(!dsi_bus_is_locked(dsidev));
2887
2888 data_id = data_type | dsi->vc[channel].vc_id << 6;
2889
2890 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2891 FLD_VAL(ecc, 31, 24);
2892
2893 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2894 }
2895
2896 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2897 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2898 {
2899 u32 val;
2900
2901 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2902
2903 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2904 b1, b2, b3, b4, val); */
2905
2906 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2907 }
2908
2909 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2910 u8 data_type, u8 *data, u16 len, u8 ecc)
2911 {
2912 /*u32 val; */
2913 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2914 int i;
2915 u8 *p;
2916 int r = 0;
2917 u8 b1, b2, b3, b4;
2918
2919 if (dsi->debug_write)
2920 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2921
2922 /* len + header */
2923 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2924 DSSERR("unable to send long packet: packet too long.\n");
2925 return -EINVAL;
2926 }
2927
2928 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2929
2930 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2931
2932 p = data;
2933 for (i = 0; i < len >> 2; i++) {
2934 if (dsi->debug_write)
2935 DSSDBG("\tsending full packet %d\n", i);
2936
2937 b1 = *p++;
2938 b2 = *p++;
2939 b3 = *p++;
2940 b4 = *p++;
2941
2942 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2943 }
2944
2945 i = len % 4;
2946 if (i) {
2947 b1 = 0; b2 = 0; b3 = 0;
2948
2949 if (dsi->debug_write)
2950 DSSDBG("\tsending remainder bytes %d\n", i);
2951
2952 switch (i) {
2953 case 3:
2954 b1 = *p++;
2955 b2 = *p++;
2956 b3 = *p++;
2957 break;
2958 case 2:
2959 b1 = *p++;
2960 b2 = *p++;
2961 break;
2962 case 1:
2963 b1 = *p++;
2964 break;
2965 }
2966
2967 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2968 }
2969
2970 return r;
2971 }
2972
2973 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2974 u8 data_type, u16 data, u8 ecc)
2975 {
2976 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2977 u32 r;
2978 u8 data_id;
2979
2980 WARN_ON(!dsi_bus_is_locked(dsidev));
2981
2982 if (dsi->debug_write)
2983 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2984 channel,
2985 data_type, data & 0xff, (data >> 8) & 0xff);
2986
2987 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2988
2989 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2990 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2991 return -EINVAL;
2992 }
2993
2994 data_id = data_type | dsi->vc[channel].vc_id << 6;
2995
2996 r = (data_id << 0) | (data << 8) | (ecc << 24);
2997
2998 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2999
3000 return 0;
3001 }
3002
3003 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3004 {
3005 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3006
3007 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3008 0, 0);
3009 }
3010
3011 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3012 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3013 {
3014 int r;
3015
3016 if (len == 0) {
3017 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3018 r = dsi_vc_send_short(dsidev, channel,
3019 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3020 } else if (len == 1) {
3021 r = dsi_vc_send_short(dsidev, channel,
3022 type == DSS_DSI_CONTENT_GENERIC ?
3023 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3024 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3025 } else if (len == 2) {
3026 r = dsi_vc_send_short(dsidev, channel,
3027 type == DSS_DSI_CONTENT_GENERIC ?
3028 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3029 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3030 data[0] | (data[1] << 8), 0);
3031 } else {
3032 r = dsi_vc_send_long(dsidev, channel,
3033 type == DSS_DSI_CONTENT_GENERIC ?
3034 MIPI_DSI_GENERIC_LONG_WRITE :
3035 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3036 }
3037
3038 return r;
3039 }
3040
3041 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3042 u8 *data, int len)
3043 {
3044 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3045
3046 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3047 DSS_DSI_CONTENT_DCS);
3048 }
3049
3050 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3051 u8 *data, int len)
3052 {
3053 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3054
3055 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3056 DSS_DSI_CONTENT_GENERIC);
3057 }
3058
3059 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3060 u8 *data, int len, enum dss_dsi_content_type type)
3061 {
3062 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3063 int r;
3064
3065 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3066 if (r)
3067 goto err;
3068
3069 r = dsi_vc_send_bta_sync(dssdev, channel);
3070 if (r)
3071 goto err;
3072
3073 /* RX_FIFO_NOT_EMPTY */
3074 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3075 DSSERR("rx fifo not empty after write, dumping data:\n");
3076 dsi_vc_flush_receive_data(dsidev, channel);
3077 r = -EIO;
3078 goto err;
3079 }
3080
3081 return 0;
3082 err:
3083 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3084 channel, data[0], len);
3085 return r;
3086 }
3087
3088 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3089 int len)
3090 {
3091 return dsi_vc_write_common(dssdev, channel, data, len,
3092 DSS_DSI_CONTENT_DCS);
3093 }
3094
3095 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3096 int len)
3097 {
3098 return dsi_vc_write_common(dssdev, channel, data, len,
3099 DSS_DSI_CONTENT_GENERIC);
3100 }
3101
3102 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3103 int channel, u8 dcs_cmd)
3104 {
3105 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3106 int r;
3107
3108 if (dsi->debug_read)
3109 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3110 channel, dcs_cmd);
3111
3112 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3113 if (r) {
3114 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3115 " failed\n", channel, dcs_cmd);
3116 return r;
3117 }
3118
3119 return 0;
3120 }
3121
3122 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3123 int channel, u8 *reqdata, int reqlen)
3124 {
3125 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3126 u16 data;
3127 u8 data_type;
3128 int r;
3129
3130 if (dsi->debug_read)
3131 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3132 channel, reqlen);
3133
3134 if (reqlen == 0) {
3135 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3136 data = 0;
3137 } else if (reqlen == 1) {
3138 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3139 data = reqdata[0];
3140 } else if (reqlen == 2) {
3141 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3142 data = reqdata[0] | (reqdata[1] << 8);
3143 } else {
3144 BUG();
3145 return -EINVAL;
3146 }
3147
3148 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3149 if (r) {
3150 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3151 " failed\n", channel, reqlen);
3152 return r;
3153 }
3154
3155 return 0;
3156 }
3157
3158 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3159 u8 *buf, int buflen, enum dss_dsi_content_type type)
3160 {
3161 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3162 u32 val;
3163 u8 dt;
3164 int r;
3165
3166 /* RX_FIFO_NOT_EMPTY */
3167 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3168 DSSERR("RX fifo empty when trying to read.\n");
3169 r = -EIO;
3170 goto err;
3171 }
3172
3173 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3174 if (dsi->debug_read)
3175 DSSDBG("\theader: %08x\n", val);
3176 dt = FLD_GET(val, 5, 0);
3177 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3178 u16 err = FLD_GET(val, 23, 8);
3179 dsi_show_rx_ack_with_err(err);
3180 r = -EIO;
3181 goto err;
3182
3183 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3184 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3185 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3186 u8 data = FLD_GET(val, 15, 8);
3187 if (dsi->debug_read)
3188 DSSDBG("\t%s short response, 1 byte: %02x\n",
3189 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3190 "DCS", data);
3191
3192 if (buflen < 1) {
3193 r = -EIO;
3194 goto err;
3195 }
3196
3197 buf[0] = data;
3198
3199 return 1;
3200 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3201 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3202 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3203 u16 data = FLD_GET(val, 23, 8);
3204 if (dsi->debug_read)
3205 DSSDBG("\t%s short response, 2 byte: %04x\n",
3206 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3207 "DCS", data);
3208
3209 if (buflen < 2) {
3210 r = -EIO;
3211 goto err;
3212 }
3213
3214 buf[0] = data & 0xff;
3215 buf[1] = (data >> 8) & 0xff;
3216
3217 return 2;
3218 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3219 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3220 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3221 int w;
3222 int len = FLD_GET(val, 23, 8);
3223 if (dsi->debug_read)
3224 DSSDBG("\t%s long response, len %d\n",
3225 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3226 "DCS", len);
3227
3228 if (len > buflen) {
3229 r = -EIO;
3230 goto err;
3231 }
3232
3233 /* two byte checksum ends the packet, not included in len */
3234 for (w = 0; w < len + 2;) {
3235 int b;
3236 val = dsi_read_reg(dsidev,
3237 DSI_VC_SHORT_PACKET_HEADER(channel));
3238 if (dsi->debug_read)
3239 DSSDBG("\t\t%02x %02x %02x %02x\n",
3240 (val >> 0) & 0xff,
3241 (val >> 8) & 0xff,
3242 (val >> 16) & 0xff,
3243 (val >> 24) & 0xff);
3244
3245 for (b = 0; b < 4; ++b) {
3246 if (w < len)
3247 buf[w] = (val >> (b * 8)) & 0xff;
3248 /* we discard the 2 byte checksum */
3249 ++w;
3250 }
3251 }
3252
3253 return len;
3254 } else {
3255 DSSERR("\tunknown datatype 0x%02x\n", dt);
3256 r = -EIO;
3257 goto err;
3258 }
3259
3260 err:
3261 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3262 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3263
3264 return r;
3265 }
3266
3267 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3268 u8 *buf, int buflen)
3269 {
3270 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3271 int r;
3272
3273 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3274 if (r)
3275 goto err;
3276
3277 r = dsi_vc_send_bta_sync(dssdev, channel);
3278 if (r)
3279 goto err;
3280
3281 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3282 DSS_DSI_CONTENT_DCS);
3283 if (r < 0)
3284 goto err;
3285
3286 if (r != buflen) {
3287 r = -EIO;
3288 goto err;
3289 }
3290
3291 return 0;
3292 err:
3293 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3294 return r;
3295 }
3296
3297 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3298 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3299 {
3300 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3301 int r;
3302
3303 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3304 if (r)
3305 return r;
3306
3307 r = dsi_vc_send_bta_sync(dssdev, channel);
3308 if (r)
3309 return r;
3310
3311 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3312 DSS_DSI_CONTENT_GENERIC);
3313 if (r < 0)
3314 return r;
3315
3316 if (r != buflen) {
3317 r = -EIO;
3318 return r;
3319 }
3320
3321 return 0;
3322 }
3323
3324 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3325 u16 len)
3326 {
3327 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3328
3329 return dsi_vc_send_short(dsidev, channel,
3330 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3331 }
3332
3333 static int dsi_enter_ulps(struct platform_device *dsidev)
3334 {
3335 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3336 DECLARE_COMPLETION_ONSTACK(completion);
3337 int r, i;
3338 unsigned mask;
3339
3340 DSSDBG("Entering ULPS");
3341
3342 WARN_ON(!dsi_bus_is_locked(dsidev));
3343
3344 WARN_ON(dsi->ulps_enabled);
3345
3346 if (dsi->ulps_enabled)
3347 return 0;
3348
3349 /* DDR_CLK_ALWAYS_ON */
3350 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3351 dsi_if_enable(dsidev, 0);
3352 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3353 dsi_if_enable(dsidev, 1);
3354 }
3355
3356 dsi_sync_vc(dsidev, 0);
3357 dsi_sync_vc(dsidev, 1);
3358 dsi_sync_vc(dsidev, 2);
3359 dsi_sync_vc(dsidev, 3);
3360
3361 dsi_force_tx_stop_mode_io(dsidev);
3362
3363 dsi_vc_enable(dsidev, 0, false);
3364 dsi_vc_enable(dsidev, 1, false);
3365 dsi_vc_enable(dsidev, 2, false);
3366 dsi_vc_enable(dsidev, 3, false);
3367
3368 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3369 DSSERR("HS busy when enabling ULPS\n");
3370 return -EIO;
3371 }
3372
3373 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3374 DSSERR("LP busy when enabling ULPS\n");
3375 return -EIO;
3376 }
3377
3378 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3379 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3380 if (r)
3381 return r;
3382
3383 mask = 0;
3384
3385 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3386 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3387 continue;
3388 mask |= 1 << i;
3389 }
3390 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3391 /* LANEx_ULPS_SIG2 */
3392 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3393
3394 /* flush posted write and wait for SCP interface to finish the write */
3395 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3396
3397 if (wait_for_completion_timeout(&completion,
3398 msecs_to_jiffies(1000)) == 0) {
3399 DSSERR("ULPS enable timeout\n");
3400 r = -EIO;
3401 goto err;
3402 }
3403
3404 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3405 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3406
3407 /* Reset LANEx_ULPS_SIG2 */
3408 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3409
3410 /* flush posted write and wait for SCP interface to finish the write */
3411 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3412
3413 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3414
3415 dsi_if_enable(dsidev, false);
3416
3417 dsi->ulps_enabled = true;
3418
3419 return 0;
3420
3421 err:
3422 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3423 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3424 return r;
3425 }
3426
3427 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3428 unsigned ticks, bool x4, bool x16)
3429 {
3430 unsigned long fck;
3431 unsigned long total_ticks;
3432 u32 r;
3433
3434 BUG_ON(ticks > 0x1fff);
3435
3436 /* ticks in DSI_FCK */
3437 fck = dsi_fclk_rate(dsidev);
3438
3439 r = dsi_read_reg(dsidev, DSI_TIMING2);
3440 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3441 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3442 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3443 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3444 dsi_write_reg(dsidev, DSI_TIMING2, r);
3445
3446 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3447
3448 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3449 total_ticks,
3450 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3451 (total_ticks * 1000) / (fck / 1000 / 1000));
3452 }
3453
3454 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3455 bool x8, bool x16)
3456 {
3457 unsigned long fck;
3458 unsigned long total_ticks;
3459 u32 r;
3460
3461 BUG_ON(ticks > 0x1fff);
3462
3463 /* ticks in DSI_FCK */
3464 fck = dsi_fclk_rate(dsidev);
3465
3466 r = dsi_read_reg(dsidev, DSI_TIMING1);
3467 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3468 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3469 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3470 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3471 dsi_write_reg(dsidev, DSI_TIMING1, r);
3472
3473 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3474
3475 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3476 total_ticks,
3477 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3478 (total_ticks * 1000) / (fck / 1000 / 1000));
3479 }
3480
3481 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3482 unsigned ticks, bool x4, bool x16)
3483 {
3484 unsigned long fck;
3485 unsigned long total_ticks;
3486 u32 r;
3487
3488 BUG_ON(ticks > 0x1fff);
3489
3490 /* ticks in DSI_FCK */
3491 fck = dsi_fclk_rate(dsidev);
3492
3493 r = dsi_read_reg(dsidev, DSI_TIMING1);
3494 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3495 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3496 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3497 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3498 dsi_write_reg(dsidev, DSI_TIMING1, r);
3499
3500 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3501
3502 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3503 total_ticks,
3504 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3505 (total_ticks * 1000) / (fck / 1000 / 1000));
3506 }
3507
3508 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3509 unsigned ticks, bool x4, bool x16)
3510 {
3511 unsigned long fck;
3512 unsigned long total_ticks;
3513 u32 r;
3514
3515 BUG_ON(ticks > 0x1fff);
3516
3517 /* ticks in TxByteClkHS */
3518 fck = dsi_get_txbyteclkhs(dsidev);
3519
3520 r = dsi_read_reg(dsidev, DSI_TIMING2);
3521 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3522 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3523 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3524 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3525 dsi_write_reg(dsidev, DSI_TIMING2, r);
3526
3527 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3528
3529 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3530 total_ticks,
3531 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3532 (total_ticks * 1000) / (fck / 1000 / 1000));
3533 }
3534
3535 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3536 {
3537 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3538 int num_line_buffers;
3539
3540 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3541 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3542 struct omap_video_timings *timings = &dsi->timings;
3543 /*
3544 * Don't use line buffers if width is greater than the video
3545 * port's line buffer size
3546 */
3547 if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3548 num_line_buffers = 0;
3549 else
3550 num_line_buffers = 2;
3551 } else {
3552 /* Use maximum number of line buffers in command mode */
3553 num_line_buffers = 2;
3554 }
3555
3556 /* LINE_BUFFER */
3557 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3558 }
3559
3560 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3561 {
3562 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3563 bool sync_end;
3564 u32 r;
3565
3566 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3567 sync_end = true;
3568 else
3569 sync_end = false;
3570
3571 r = dsi_read_reg(dsidev, DSI_CTRL);
3572 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3573 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3574 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3575 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3576 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3577 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3578 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3579 dsi_write_reg(dsidev, DSI_CTRL, r);
3580 }
3581
3582 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3583 {
3584 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3585 int blanking_mode = dsi->vm_timings.blanking_mode;
3586 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3587 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3588 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3589 u32 r;
3590
3591 /*
3592 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3593 * 1 = Long blanking packets are sent in corresponding blanking periods
3594 */
3595 r = dsi_read_reg(dsidev, DSI_CTRL);
3596 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3597 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3598 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3599 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3600 dsi_write_reg(dsidev, DSI_CTRL, r);
3601 }
3602
3603 /*
3604 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3605 * results in maximum transition time for data and clock lanes to enter and
3606 * exit HS mode. Hence, this is the scenario where the least amount of command
3607 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3608 * clock cycles that can be used to interleave command mode data in HS so that
3609 * all scenarios are satisfied.
3610 */
3611 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3612 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3613 {
3614 int transition;
3615
3616 /*
3617 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3618 * time of data lanes only, if it isn't set, we need to consider HS
3619 * transition time of both data and clock lanes. HS transition time
3620 * of Scenario 3 is considered.
3621 */
3622 if (ddr_alwon) {
3623 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3624 } else {
3625 int trans1, trans2;
3626 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3627 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3628 enter_hs + 1;
3629 transition = max(trans1, trans2);
3630 }
3631
3632 return blank > transition ? blank - transition : 0;
3633 }
3634
3635 /*
3636 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3637 * results in maximum transition time for data lanes to enter and exit LP mode.
3638 * Hence, this is the scenario where the least amount of command mode data can
3639 * be interleaved. We program the minimum amount of bytes that can be
3640 * interleaved in LP so that all scenarios are satisfied.
3641 */
3642 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3643 int lp_clk_div, int tdsi_fclk)
3644 {
3645 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3646 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3647 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3648 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3649 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3650
3651 /* maximum LP transition time according to Scenario 1 */
3652 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3653
3654 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3655 tlp_avail = thsbyte_clk * (blank - trans_lp);
3656
3657 ttxclkesc = tdsi_fclk * lp_clk_div;
3658
3659 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3660 26) / 16;
3661
3662 return max(lp_inter, 0);
3663 }
3664
3665 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3666 {
3667 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3668 int blanking_mode;
3669 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3670 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3671 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3672 int tclk_trail, ths_exit, exiths_clk;
3673 bool ddr_alwon;
3674 struct omap_video_timings *timings = &dsi->timings;
3675 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3676 int ndl = dsi->num_lanes_used - 1;
3677 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1;
3678 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3679 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3680 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3681 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3682 u32 r;
3683
3684 r = dsi_read_reg(dsidev, DSI_CTRL);
3685 blanking_mode = FLD_GET(r, 20, 20);
3686 hfp_blanking_mode = FLD_GET(r, 21, 21);
3687 hbp_blanking_mode = FLD_GET(r, 22, 22);
3688 hsa_blanking_mode = FLD_GET(r, 23, 23);
3689
3690 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3691 hbp = FLD_GET(r, 11, 0);
3692 hfp = FLD_GET(r, 23, 12);
3693 hsa = FLD_GET(r, 31, 24);
3694
3695 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3696 ddr_clk_post = FLD_GET(r, 7, 0);
3697 ddr_clk_pre = FLD_GET(r, 15, 8);
3698
3699 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3700 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3701 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3702
3703 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3704 lp_clk_div = FLD_GET(r, 12, 0);
3705 ddr_alwon = FLD_GET(r, 13, 13);
3706
3707 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3708 ths_exit = FLD_GET(r, 7, 0);
3709
3710 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3711 tclk_trail = FLD_GET(r, 15, 8);
3712
3713 exiths_clk = ths_exit + tclk_trail;
3714
3715 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3716 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3717
3718 if (!hsa_blanking_mode) {
3719 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3720 enter_hs_mode_lat, exit_hs_mode_lat,
3721 exiths_clk, ddr_clk_pre, ddr_clk_post);
3722 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3723 enter_hs_mode_lat, exit_hs_mode_lat,
3724 lp_clk_div, dsi_fclk_hsdiv);
3725 }
3726
3727 if (!hfp_blanking_mode) {
3728 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3729 enter_hs_mode_lat, exit_hs_mode_lat,
3730 exiths_clk, ddr_clk_pre, ddr_clk_post);
3731 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3732 enter_hs_mode_lat, exit_hs_mode_lat,
3733 lp_clk_div, dsi_fclk_hsdiv);
3734 }
3735
3736 if (!hbp_blanking_mode) {
3737 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3738 enter_hs_mode_lat, exit_hs_mode_lat,
3739 exiths_clk, ddr_clk_pre, ddr_clk_post);
3740
3741 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3742 enter_hs_mode_lat, exit_hs_mode_lat,
3743 lp_clk_div, dsi_fclk_hsdiv);
3744 }
3745
3746 if (!blanking_mode) {
3747 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3748 enter_hs_mode_lat, exit_hs_mode_lat,
3749 exiths_clk, ddr_clk_pre, ddr_clk_post);
3750
3751 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3752 enter_hs_mode_lat, exit_hs_mode_lat,
3753 lp_clk_div, dsi_fclk_hsdiv);
3754 }
3755
3756 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3757 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3758 bl_interleave_hs);
3759
3760 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3761 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3762 bl_interleave_lp);
3763
3764 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3765 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3766 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3767 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3768 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3769
3770 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3771 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3772 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3773 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3774 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3775
3776 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3777 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3778 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3779 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3780 }
3781
3782 static int dsi_proto_config(struct platform_device *dsidev)
3783 {
3784 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3785 u32 r;
3786 int buswidth = 0;
3787
3788 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3789 DSI_FIFO_SIZE_32,
3790 DSI_FIFO_SIZE_32,
3791 DSI_FIFO_SIZE_32);
3792
3793 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3794 DSI_FIFO_SIZE_32,
3795 DSI_FIFO_SIZE_32,
3796 DSI_FIFO_SIZE_32);
3797
3798 /* XXX what values for the timeouts? */
3799 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3800 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3801 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3802 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3803
3804 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3805 case 16:
3806 buswidth = 0;
3807 break;
3808 case 18:
3809 buswidth = 1;
3810 break;
3811 case 24:
3812 buswidth = 2;
3813 break;
3814 default:
3815 BUG();
3816 return -EINVAL;
3817 }
3818
3819 r = dsi_read_reg(dsidev, DSI_CTRL);
3820 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3821 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3822 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3823 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3824 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3825 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3826 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3827 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3828 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3829 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3830 /* DCS_CMD_CODE, 1=start, 0=continue */
3831 r = FLD_MOD(r, 0, 25, 25);
3832 }
3833
3834 dsi_write_reg(dsidev, DSI_CTRL, r);
3835
3836 dsi_config_vp_num_line_buffers(dsidev);
3837
3838 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3839 dsi_config_vp_sync_events(dsidev);
3840 dsi_config_blanking_modes(dsidev);
3841 dsi_config_cmd_mode_interleaving(dsidev);
3842 }
3843
3844 dsi_vc_initial_config(dsidev, 0);
3845 dsi_vc_initial_config(dsidev, 1);
3846 dsi_vc_initial_config(dsidev, 2);
3847 dsi_vc_initial_config(dsidev, 3);
3848
3849 return 0;
3850 }
3851
3852 static void dsi_proto_timings(struct platform_device *dsidev)
3853 {
3854 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3855 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3856 unsigned tclk_pre, tclk_post;
3857 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3858 unsigned ths_trail, ths_exit;
3859 unsigned ddr_clk_pre, ddr_clk_post;
3860 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3861 unsigned ths_eot;
3862 int ndl = dsi->num_lanes_used - 1;
3863 u32 r;
3864
3865 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3866 ths_prepare = FLD_GET(r, 31, 24);
3867 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3868 ths_zero = ths_prepare_ths_zero - ths_prepare;
3869 ths_trail = FLD_GET(r, 15, 8);
3870 ths_exit = FLD_GET(r, 7, 0);
3871
3872 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3873 tlpx = FLD_GET(r, 20, 16) * 2;
3874 tclk_trail = FLD_GET(r, 15, 8);
3875 tclk_zero = FLD_GET(r, 7, 0);
3876
3877 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3878 tclk_prepare = FLD_GET(r, 7, 0);
3879
3880 /* min 8*UI */
3881 tclk_pre = 20;
3882 /* min 60ns + 52*UI */
3883 tclk_post = ns2ddr(dsidev, 60) + 26;
3884
3885 ths_eot = DIV_ROUND_UP(4, ndl);
3886
3887 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3888 4);
3889 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3890
3891 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3892 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3893
3894 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3895 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3896 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3897 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3898
3899 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3900 ddr_clk_pre,
3901 ddr_clk_post);
3902
3903 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3904 DIV_ROUND_UP(ths_prepare, 4) +
3905 DIV_ROUND_UP(ths_zero + 3, 4);
3906
3907 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3908
3909 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3910 FLD_VAL(exit_hs_mode_lat, 15, 0);
3911 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3912
3913 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3914 enter_hs_mode_lat, exit_hs_mode_lat);
3915
3916 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3917 /* TODO: Implement a video mode check_timings function */
3918 int hsa = dsi->vm_timings.hsa;
3919 int hfp = dsi->vm_timings.hfp;
3920 int hbp = dsi->vm_timings.hbp;
3921 int vsa = dsi->vm_timings.vsa;
3922 int vfp = dsi->vm_timings.vfp;
3923 int vbp = dsi->vm_timings.vbp;
3924 int window_sync = dsi->vm_timings.window_sync;
3925 bool hsync_end;
3926 struct omap_video_timings *timings = &dsi->timings;
3927 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3928 int tl, t_he, width_bytes;
3929
3930 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3931 t_he = hsync_end ?
3932 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3933
3934 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3935
3936 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3937 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3938 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3939
3940 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3941 hfp, hsync_end ? hsa : 0, tl);
3942 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3943 vsa, timings->y_res);
3944
3945 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3946 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3947 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3948 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3949 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3950
3951 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3952 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3953 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3954 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3955 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3956 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3957
3958 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3959 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3960 r = FLD_MOD(r, tl, 31, 16); /* TL */
3961 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3962 }
3963 }
3964
3965 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3966 const struct omap_dsi_pin_config *pin_cfg)
3967 {
3968 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3969 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3970 int num_pins;
3971 const int *pins;
3972 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3973 int num_lanes;
3974 int i;
3975
3976 static const enum dsi_lane_function functions[] = {
3977 DSI_LANE_CLK,
3978 DSI_LANE_DATA1,
3979 DSI_LANE_DATA2,
3980 DSI_LANE_DATA3,
3981 DSI_LANE_DATA4,
3982 };
3983
3984 num_pins = pin_cfg->num_pins;
3985 pins = pin_cfg->pins;
3986
3987 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3988 || num_pins % 2 != 0)
3989 return -EINVAL;
3990
3991 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3992 lanes[i].function = DSI_LANE_UNUSED;
3993
3994 num_lanes = 0;
3995
3996 for (i = 0; i < num_pins; i += 2) {
3997 u8 lane, pol;
3998 int dx, dy;
3999
4000 dx = pins[i];
4001 dy = pins[i + 1];
4002
4003 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4004 return -EINVAL;
4005
4006 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4007 return -EINVAL;
4008
4009 if (dx & 1) {
4010 if (dy != dx - 1)
4011 return -EINVAL;
4012 pol = 1;
4013 } else {
4014 if (dy != dx + 1)
4015 return -EINVAL;
4016 pol = 0;
4017 }
4018
4019 lane = dx / 2;
4020
4021 lanes[lane].function = functions[i / 2];
4022 lanes[lane].polarity = pol;
4023 num_lanes++;
4024 }
4025
4026 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4027 dsi->num_lanes_used = num_lanes;
4028
4029 return 0;
4030 }
4031
4032 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4033 {
4034 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4035 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4036 struct omap_overlay_manager *mgr = dsi->output.manager;
4037 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4038 struct omap_dss_device *out = &dsi->output;
4039 u8 data_type;
4040 u16 word_count;
4041 int r;
4042
4043 if (out == NULL || out->manager == NULL) {
4044 DSSERR("failed to enable display: no output/manager\n");
4045 return -ENODEV;
4046 }
4047
4048 r = dsi_display_init_dispc(dsidev, mgr);
4049 if (r)
4050 goto err_init_dispc;
4051
4052 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4053 switch (dsi->pix_fmt) {
4054 case OMAP_DSS_DSI_FMT_RGB888:
4055 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4056 break;
4057 case OMAP_DSS_DSI_FMT_RGB666:
4058 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4059 break;
4060 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4061 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4062 break;
4063 case OMAP_DSS_DSI_FMT_RGB565:
4064 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4065 break;
4066 default:
4067 r = -EINVAL;
4068 goto err_pix_fmt;
4069 }
4070
4071 dsi_if_enable(dsidev, false);
4072 dsi_vc_enable(dsidev, channel, false);
4073
4074 /* MODE, 1 = video mode */
4075 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4076
4077 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4078
4079 dsi_vc_write_long_header(dsidev, channel, data_type,
4080 word_count, 0);
4081
4082 dsi_vc_enable(dsidev, channel, true);
4083 dsi_if_enable(dsidev, true);
4084 }
4085
4086 r = dss_mgr_enable(mgr);
4087 if (r)
4088 goto err_mgr_enable;
4089
4090 return 0;
4091
4092 err_mgr_enable:
4093 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4094 dsi_if_enable(dsidev, false);
4095 dsi_vc_enable(dsidev, channel, false);
4096 }
4097 err_pix_fmt:
4098 dsi_display_uninit_dispc(dsidev, mgr);
4099 err_init_dispc:
4100 return r;
4101 }
4102
4103 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4104 {
4105 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4106 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4107 struct omap_overlay_manager *mgr = dsi->output.manager;
4108
4109 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4110 dsi_if_enable(dsidev, false);
4111 dsi_vc_enable(dsidev, channel, false);
4112
4113 /* MODE, 0 = command mode */
4114 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4115
4116 dsi_vc_enable(dsidev, channel, true);
4117 dsi_if_enable(dsidev, true);
4118 }
4119
4120 dss_mgr_disable(mgr);
4121
4122 dsi_display_uninit_dispc(dsidev, mgr);
4123 }
4124
4125 static void dsi_update_screen_dispc(struct platform_device *dsidev)
4126 {
4127 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4128 struct omap_overlay_manager *mgr = dsi->output.manager;
4129 unsigned bytespp;
4130 unsigned bytespl;
4131 unsigned bytespf;
4132 unsigned total_len;
4133 unsigned packet_payload;
4134 unsigned packet_len;
4135 u32 l;
4136 int r;
4137 const unsigned channel = dsi->update_channel;
4138 const unsigned line_buf_size = dsi->line_buffer_size;
4139 u16 w = dsi->timings.x_res;
4140 u16 h = dsi->timings.y_res;
4141
4142 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4143
4144 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4145
4146 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4147 bytespl = w * bytespp;
4148 bytespf = bytespl * h;
4149
4150 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4151 * number of lines in a packet. See errata about VP_CLK_RATIO */
4152
4153 if (bytespf < line_buf_size)
4154 packet_payload = bytespf;
4155 else
4156 packet_payload = (line_buf_size) / bytespl * bytespl;
4157
4158 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4159 total_len = (bytespf / packet_payload) * packet_len;
4160
4161 if (bytespf % packet_payload)
4162 total_len += (bytespf % packet_payload) + 1;
4163
4164 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4165 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4166
4167 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4168 packet_len, 0);
4169
4170 if (dsi->te_enabled)
4171 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4172 else
4173 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4174 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4175
4176 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4177 * because DSS interrupts are not capable of waking up the CPU and the
4178 * framedone interrupt could be delayed for quite a long time. I think
4179 * the same goes for any DSS interrupts, but for some reason I have not
4180 * seen the problem anywhere else than here.
4181 */
4182 dispc_disable_sidle();
4183
4184 dsi_perf_mark_start(dsidev);
4185
4186 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4187 msecs_to_jiffies(250));
4188 BUG_ON(r == 0);
4189
4190 dss_mgr_set_timings(mgr, &dsi->timings);
4191
4192 dss_mgr_start_update(mgr);
4193
4194 if (dsi->te_enabled) {
4195 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4196 * for TE is longer than the timer allows */
4197 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4198
4199 dsi_vc_send_bta(dsidev, channel);
4200
4201 #ifdef DSI_CATCH_MISSING_TE
4202 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4203 #endif
4204 }
4205 }
4206
4207 #ifdef DSI_CATCH_MISSING_TE
4208 static void dsi_te_timeout(unsigned long arg)
4209 {
4210 DSSERR("TE not received for 250ms!\n");
4211 }
4212 #endif
4213
4214 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4215 {
4216 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4217
4218 /* SIDLEMODE back to smart-idle */
4219 dispc_enable_sidle();
4220
4221 if (dsi->te_enabled) {
4222 /* enable LP_RX_TO again after the TE */
4223 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4224 }
4225
4226 dsi->framedone_callback(error, dsi->framedone_data);
4227
4228 if (!error)
4229 dsi_perf_show(dsidev, "DISPC");
4230 }
4231
4232 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4233 {
4234 struct dsi_data *dsi = container_of(work, struct dsi_data,
4235 framedone_timeout_work.work);
4236 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4237 * 250ms which would conflict with this timeout work. What should be
4238 * done is first cancel the transfer on the HW, and then cancel the
4239 * possibly scheduled framedone work. However, cancelling the transfer
4240 * on the HW is buggy, and would probably require resetting the whole
4241 * DSI */
4242
4243 DSSERR("Framedone not received for 250ms!\n");
4244
4245 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4246 }
4247
4248 static void dsi_framedone_irq_callback(void *data)
4249 {
4250 struct platform_device *dsidev = (struct platform_device *) data;
4251 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4252
4253 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4254 * turns itself off. However, DSI still has the pixels in its buffers,
4255 * and is sending the data.
4256 */
4257
4258 cancel_delayed_work(&dsi->framedone_timeout_work);
4259
4260 dsi_handle_framedone(dsidev, 0);
4261 }
4262
4263 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4264 void (*callback)(int, void *), void *data)
4265 {
4266 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4267 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4268 u16 dw, dh;
4269
4270 dsi_perf_mark_setup(dsidev);
4271
4272 dsi->update_channel = channel;
4273
4274 dsi->framedone_callback = callback;
4275 dsi->framedone_data = data;
4276
4277 dw = dsi->timings.x_res;
4278 dh = dsi->timings.y_res;
4279
4280 #ifdef DSI_PERF_MEASURE
4281 dsi->update_bytes = dw * dh *
4282 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4283 #endif
4284 dsi_update_screen_dispc(dsidev);
4285
4286 return 0;
4287 }
4288
4289 /* Display funcs */
4290
4291 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4292 {
4293 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4294 struct dispc_clock_info dispc_cinfo;
4295 int r;
4296 unsigned long fck;
4297
4298 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4299
4300 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4301 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4302
4303 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4304 if (r) {
4305 DSSERR("Failed to calc dispc clocks\n");
4306 return r;
4307 }
4308
4309 dsi->mgr_config.clock_info = dispc_cinfo;
4310
4311 return 0;
4312 }
4313
4314 static int dsi_display_init_dispc(struct platform_device *dsidev,
4315 struct omap_overlay_manager *mgr)
4316 {
4317 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4318 int r;
4319
4320 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4321 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4322 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4323
4324 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4325 r = dss_mgr_register_framedone_handler(mgr,
4326 dsi_framedone_irq_callback, dsidev);
4327 if (r) {
4328 DSSERR("can't register FRAMEDONE handler\n");
4329 goto err;
4330 }
4331
4332 dsi->mgr_config.stallmode = true;
4333 dsi->mgr_config.fifohandcheck = true;
4334 } else {
4335 dsi->mgr_config.stallmode = false;
4336 dsi->mgr_config.fifohandcheck = false;
4337 }
4338
4339 /*
4340 * override interlace, logic level and edge related parameters in
4341 * omap_video_timings with default values
4342 */
4343 dsi->timings.interlace = false;
4344 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4345 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4346 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4347 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4348 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4349
4350 dss_mgr_set_timings(mgr, &dsi->timings);
4351
4352 r = dsi_configure_dispc_clocks(dsidev);
4353 if (r)
4354 goto err1;
4355
4356 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4357 dsi->mgr_config.video_port_width =
4358 dsi_get_pixel_size(dsi->pix_fmt);
4359 dsi->mgr_config.lcden_sig_polarity = 0;
4360
4361 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4362
4363 return 0;
4364 err1:
4365 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4366 dss_mgr_unregister_framedone_handler(mgr,
4367 dsi_framedone_irq_callback, dsidev);
4368 err:
4369 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4370 return r;
4371 }
4372
4373 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4374 struct omap_overlay_manager *mgr)
4375 {
4376 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4377
4378 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4379 dss_mgr_unregister_framedone_handler(mgr,
4380 dsi_framedone_irq_callback, dsidev);
4381
4382 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4383 }
4384
4385 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4386 {
4387 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4388 struct dsi_clock_info cinfo;
4389 int r;
4390
4391 cinfo = dsi->user_dsi_cinfo;
4392
4393 r = dsi_calc_clock_rates(dsidev, &cinfo);
4394 if (r) {
4395 DSSERR("Failed to calc dsi clocks\n");
4396 return r;
4397 }
4398
4399 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4400 if (r) {
4401 DSSERR("Failed to set dsi clocks\n");
4402 return r;
4403 }
4404
4405 return 0;
4406 }
4407
4408 static int dsi_display_init_dsi(struct platform_device *dsidev)
4409 {
4410 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4411 int r;
4412
4413 r = dsi_pll_init(dsidev, true, true);
4414 if (r)
4415 goto err0;
4416
4417 r = dsi_configure_dsi_clocks(dsidev);
4418 if (r)
4419 goto err1;
4420
4421 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4422 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4423 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4424
4425 DSSDBG("PLL OK\n");
4426
4427 r = dsi_cio_init(dsidev);
4428 if (r)
4429 goto err2;
4430
4431 _dsi_print_reset_status(dsidev);
4432
4433 dsi_proto_timings(dsidev);
4434 dsi_set_lp_clk_divisor(dsidev);
4435
4436 if (1)
4437 _dsi_print_reset_status(dsidev);
4438
4439 r = dsi_proto_config(dsidev);
4440 if (r)
4441 goto err3;
4442
4443 /* enable interface */
4444 dsi_vc_enable(dsidev, 0, 1);
4445 dsi_vc_enable(dsidev, 1, 1);
4446 dsi_vc_enable(dsidev, 2, 1);
4447 dsi_vc_enable(dsidev, 3, 1);
4448 dsi_if_enable(dsidev, 1);
4449 dsi_force_tx_stop_mode_io(dsidev);
4450
4451 return 0;
4452 err3:
4453 dsi_cio_uninit(dsidev);
4454 err2:
4455 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4456 err1:
4457 dsi_pll_uninit(dsidev, true);
4458 err0:
4459 return r;
4460 }
4461
4462 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4463 bool disconnect_lanes, bool enter_ulps)
4464 {
4465 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4466
4467 if (enter_ulps && !dsi->ulps_enabled)
4468 dsi_enter_ulps(dsidev);
4469
4470 /* disable interface */
4471 dsi_if_enable(dsidev, 0);
4472 dsi_vc_enable(dsidev, 0, 0);
4473 dsi_vc_enable(dsidev, 1, 0);
4474 dsi_vc_enable(dsidev, 2, 0);
4475 dsi_vc_enable(dsidev, 3, 0);
4476
4477 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4478 dsi_cio_uninit(dsidev);
4479 dsi_pll_uninit(dsidev, disconnect_lanes);
4480 }
4481
4482 static int dsi_display_enable(struct omap_dss_device *dssdev)
4483 {
4484 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4485 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4486 int r = 0;
4487
4488 DSSDBG("dsi_display_enable\n");
4489
4490 WARN_ON(!dsi_bus_is_locked(dsidev));
4491
4492 mutex_lock(&dsi->lock);
4493
4494 r = dsi_runtime_get(dsidev);
4495 if (r)
4496 goto err_get_dsi;
4497
4498 dsi_enable_pll_clock(dsidev, 1);
4499
4500 _dsi_initialize_irq(dsidev);
4501
4502 r = dsi_display_init_dsi(dsidev);
4503 if (r)
4504 goto err_init_dsi;
4505
4506 mutex_unlock(&dsi->lock);
4507
4508 return 0;
4509
4510 err_init_dsi:
4511 dsi_enable_pll_clock(dsidev, 0);
4512 dsi_runtime_put(dsidev);
4513 err_get_dsi:
4514 mutex_unlock(&dsi->lock);
4515 DSSDBG("dsi_display_enable FAILED\n");
4516 return r;
4517 }
4518
4519 static void dsi_display_disable(struct omap_dss_device *dssdev,
4520 bool disconnect_lanes, bool enter_ulps)
4521 {
4522 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4523 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4524
4525 DSSDBG("dsi_display_disable\n");
4526
4527 WARN_ON(!dsi_bus_is_locked(dsidev));
4528
4529 mutex_lock(&dsi->lock);
4530
4531 dsi_sync_vc(dsidev, 0);
4532 dsi_sync_vc(dsidev, 1);
4533 dsi_sync_vc(dsidev, 2);
4534 dsi_sync_vc(dsidev, 3);
4535
4536 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4537
4538 dsi_runtime_put(dsidev);
4539 dsi_enable_pll_clock(dsidev, 0);
4540
4541 mutex_unlock(&dsi->lock);
4542 }
4543
4544 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4545 {
4546 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4547 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4548
4549 dsi->te_enabled = enable;
4550 return 0;
4551 }
4552
4553 #ifdef PRINT_VERBOSE_VM_TIMINGS
4554 static void print_dsi_vm(const char *str,
4555 const struct omap_dss_dsi_videomode_timings *t)
4556 {
4557 unsigned long byteclk = t->hsclk / 4;
4558 int bl, wc, pps, tot;
4559
4560 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4561 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4562 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4563 tot = bl + pps;
4564
4565 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4566
4567 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4568 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4569 str,
4570 byteclk,
4571 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4572 bl, pps, tot,
4573 TO_DSI_T(t->hss),
4574 TO_DSI_T(t->hsa),
4575 TO_DSI_T(t->hse),
4576 TO_DSI_T(t->hbp),
4577 TO_DSI_T(pps),
4578 TO_DSI_T(t->hfp),
4579
4580 TO_DSI_T(bl),
4581 TO_DSI_T(pps),
4582
4583 TO_DSI_T(tot));
4584 #undef TO_DSI_T
4585 }
4586
4587 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4588 {
4589 unsigned long pck = t->pixel_clock * 1000;
4590 int hact, bl, tot;
4591
4592 hact = t->x_res;
4593 bl = t->hsw + t->hbp + t->hfp;
4594 tot = hact + bl;
4595
4596 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4597
4598 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4599 "%u/%u/%u/%u = %u + %u = %u\n",
4600 str,
4601 pck,
4602 t->hsw, t->hbp, hact, t->hfp,
4603 bl, hact, tot,
4604 TO_DISPC_T(t->hsw),
4605 TO_DISPC_T(t->hbp),
4606 TO_DISPC_T(hact),
4607 TO_DISPC_T(t->hfp),
4608 TO_DISPC_T(bl),
4609 TO_DISPC_T(hact),
4610 TO_DISPC_T(tot));
4611 #undef TO_DISPC_T
4612 }
4613
4614 /* note: this is not quite accurate */
4615 static void print_dsi_dispc_vm(const char *str,
4616 const struct omap_dss_dsi_videomode_timings *t)
4617 {
4618 struct omap_video_timings vm = { 0 };
4619 unsigned long byteclk = t->hsclk / 4;
4620 unsigned long pck;
4621 u64 dsi_tput;
4622 int dsi_hact, dsi_htot;
4623
4624 dsi_tput = (u64)byteclk * t->ndl * 8;
4625 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4626 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4627 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4628
4629 vm.pixel_clock = pck / 1000;
4630 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4631 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4632 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4633 vm.x_res = t->hact;
4634
4635 print_dispc_vm(str, &vm);
4636 }
4637 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4638
4639 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4640 unsigned long pck, void *data)
4641 {
4642 struct dsi_clk_calc_ctx *ctx = data;
4643 struct omap_video_timings *t = &ctx->dispc_vm;
4644
4645 ctx->dispc_cinfo.lck_div = lckd;
4646 ctx->dispc_cinfo.pck_div = pckd;
4647 ctx->dispc_cinfo.lck = lck;
4648 ctx->dispc_cinfo.pck = pck;
4649
4650 *t = *ctx->config->timings;
4651 t->pixel_clock = pck / 1000;
4652 t->x_res = ctx->config->timings->x_res;
4653 t->y_res = ctx->config->timings->y_res;
4654 t->hsw = t->hfp = t->hbp = t->vsw = 1;
4655 t->vfp = t->vbp = 0;
4656
4657 return true;
4658 }
4659
4660 static bool dsi_cm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4661 void *data)
4662 {
4663 struct dsi_clk_calc_ctx *ctx = data;
4664
4665 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4666 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4667
4668 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4669 dsi_cm_calc_dispc_cb, ctx);
4670 }
4671
4672 static bool dsi_cm_calc_pll_cb(int regn, int regm, unsigned long fint,
4673 unsigned long pll, void *data)
4674 {
4675 struct dsi_clk_calc_ctx *ctx = data;
4676
4677 ctx->dsi_cinfo.regn = regn;
4678 ctx->dsi_cinfo.regm = regm;
4679 ctx->dsi_cinfo.fint = fint;
4680 ctx->dsi_cinfo.clkin4ddr = pll;
4681
4682 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
4683 dsi_cm_calc_hsdiv_cb, ctx);
4684 }
4685
4686 static bool dsi_cm_calc(struct dsi_data *dsi,
4687 const struct omap_dss_dsi_config *cfg,
4688 struct dsi_clk_calc_ctx *ctx)
4689 {
4690 unsigned long clkin;
4691 int bitspp, ndl;
4692 unsigned long pll_min, pll_max;
4693 unsigned long pck, txbyteclk;
4694
4695 clkin = clk_get_rate(dsi->sys_clk);
4696 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4697 ndl = dsi->num_lanes_used - 1;
4698
4699 /*
4700 * Here we should calculate minimum txbyteclk to be able to send the
4701 * frame in time, and also to handle TE. That's not very simple, though,
4702 * especially as we go to LP between each pixel packet due to HW
4703 * "feature". So let's just estimate very roughly and multiply by 1.5.
4704 */
4705 pck = cfg->timings->pixel_clock * 1000;
4706 pck = pck * 3 / 2;
4707 txbyteclk = pck * bitspp / 8 / ndl;
4708
4709 memset(ctx, 0, sizeof(*ctx));
4710 ctx->dsidev = dsi->pdev;
4711 ctx->config = cfg;
4712 ctx->req_pck_min = pck;
4713 ctx->req_pck_nom = pck;
4714 ctx->req_pck_max = pck * 3 / 2;
4715 ctx->dsi_cinfo.clkin = clkin;
4716
4717 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4718 pll_max = cfg->hs_clk_max * 4;
4719
4720 return dsi_pll_calc(dsi->pdev, clkin,
4721 pll_min, pll_max,
4722 dsi_cm_calc_pll_cb, ctx);
4723 }
4724
4725 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4726 {
4727 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4728 const struct omap_dss_dsi_config *cfg = ctx->config;
4729 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4730 int ndl = dsi->num_lanes_used - 1;
4731 unsigned long hsclk = ctx->dsi_cinfo.clkin4ddr / 4;
4732 unsigned long byteclk = hsclk / 4;
4733
4734 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4735 int xres;
4736 int panel_htot, panel_hbl; /* pixels */
4737 int dispc_htot, dispc_hbl; /* pixels */
4738 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4739 int hfp, hsa, hbp;
4740 const struct omap_video_timings *req_vm;
4741 struct omap_video_timings *dispc_vm;
4742 struct omap_dss_dsi_videomode_timings *dsi_vm;
4743 u64 dsi_tput, dispc_tput;
4744
4745 dsi_tput = (u64)byteclk * ndl * 8;
4746
4747 req_vm = cfg->timings;
4748 req_pck_min = ctx->req_pck_min;
4749 req_pck_max = ctx->req_pck_max;
4750 req_pck_nom = ctx->req_pck_nom;
4751
4752 dispc_pck = ctx->dispc_cinfo.pck;
4753 dispc_tput = (u64)dispc_pck * bitspp;
4754
4755 xres = req_vm->x_res;
4756
4757 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4758 panel_htot = xres + panel_hbl;
4759
4760 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4761
4762 /*
4763 * When there are no line buffers, DISPC and DSI must have the
4764 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4765 */
4766 if (dsi->line_buffer_size < xres * bitspp / 8) {
4767 if (dispc_tput != dsi_tput)
4768 return false;
4769 } else {
4770 if (dispc_tput < dsi_tput)
4771 return false;
4772 }
4773
4774 /* DSI tput must be over the min requirement */
4775 if (dsi_tput < (u64)bitspp * req_pck_min)
4776 return false;
4777
4778 /* When non-burst mode, DSI tput must be below max requirement. */
4779 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4780 if (dsi_tput > (u64)bitspp * req_pck_max)
4781 return false;
4782 }
4783
4784 hss = DIV_ROUND_UP(4, ndl);
4785
4786 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4787 if (ndl == 3 && req_vm->hsw == 0)
4788 hse = 1;
4789 else
4790 hse = DIV_ROUND_UP(4, ndl);
4791 } else {
4792 hse = 0;
4793 }
4794
4795 /* DSI htot to match the panel's nominal pck */
4796 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4797
4798 /* fail if there would be no time for blanking */
4799 if (dsi_htot < hss + hse + dsi_hact)
4800 return false;
4801
4802 /* total DSI blanking needed to achieve panel's TL */
4803 dsi_hbl = dsi_htot - dsi_hact;
4804
4805 /* DISPC htot to match the DSI TL */
4806 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4807
4808 /* verify that the DSI and DISPC TLs are the same */
4809 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4810 return false;
4811
4812 dispc_hbl = dispc_htot - xres;
4813
4814 /* setup DSI videomode */
4815
4816 dsi_vm = &ctx->dsi_vm;
4817 memset(dsi_vm, 0, sizeof(*dsi_vm));
4818
4819 dsi_vm->hsclk = hsclk;
4820
4821 dsi_vm->ndl = ndl;
4822 dsi_vm->bitspp = bitspp;
4823
4824 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4825 hsa = 0;
4826 } else if (ndl == 3 && req_vm->hsw == 0) {
4827 hsa = 0;
4828 } else {
4829 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4830 hsa = max(hsa - hse, 1);
4831 }
4832
4833 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4834 hbp = max(hbp, 1);
4835
4836 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4837 if (hfp < 1) {
4838 int t;
4839 /* we need to take cycles from hbp */
4840
4841 t = 1 - hfp;
4842 hbp = max(hbp - t, 1);
4843 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4844
4845 if (hfp < 1 && hsa > 0) {
4846 /* we need to take cycles from hsa */
4847 t = 1 - hfp;
4848 hsa = max(hsa - t, 1);
4849 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4850 }
4851 }
4852
4853 if (hfp < 1)
4854 return false;
4855
4856 dsi_vm->hss = hss;
4857 dsi_vm->hsa = hsa;
4858 dsi_vm->hse = hse;
4859 dsi_vm->hbp = hbp;
4860 dsi_vm->hact = xres;
4861 dsi_vm->hfp = hfp;
4862
4863 dsi_vm->vsa = req_vm->vsw;
4864 dsi_vm->vbp = req_vm->vbp;
4865 dsi_vm->vact = req_vm->y_res;
4866 dsi_vm->vfp = req_vm->vfp;
4867
4868 dsi_vm->trans_mode = cfg->trans_mode;
4869
4870 dsi_vm->blanking_mode = 0;
4871 dsi_vm->hsa_blanking_mode = 1;
4872 dsi_vm->hfp_blanking_mode = 1;
4873 dsi_vm->hbp_blanking_mode = 1;
4874
4875 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4876 dsi_vm->window_sync = 4;
4877
4878 /* setup DISPC videomode */
4879
4880 dispc_vm = &ctx->dispc_vm;
4881 *dispc_vm = *req_vm;
4882 dispc_vm->pixel_clock = dispc_pck / 1000;
4883
4884 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4885 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4886 req_pck_nom);
4887 hsa = max(hsa, 1);
4888 } else {
4889 hsa = 1;
4890 }
4891
4892 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4893 hbp = max(hbp, 1);
4894
4895 hfp = dispc_hbl - hsa - hbp;
4896 if (hfp < 1) {
4897 int t;
4898 /* we need to take cycles from hbp */
4899
4900 t = 1 - hfp;
4901 hbp = max(hbp - t, 1);
4902 hfp = dispc_hbl - hsa - hbp;
4903
4904 if (hfp < 1) {
4905 /* we need to take cycles from hsa */
4906 t = 1 - hfp;
4907 hsa = max(hsa - t, 1);
4908 hfp = dispc_hbl - hsa - hbp;
4909 }
4910 }
4911
4912 if (hfp < 1)
4913 return false;
4914
4915 dispc_vm->hfp = hfp;
4916 dispc_vm->hsw = hsa;
4917 dispc_vm->hbp = hbp;
4918
4919 return true;
4920 }
4921
4922
4923 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4924 unsigned long pck, void *data)
4925 {
4926 struct dsi_clk_calc_ctx *ctx = data;
4927
4928 ctx->dispc_cinfo.lck_div = lckd;
4929 ctx->dispc_cinfo.pck_div = pckd;
4930 ctx->dispc_cinfo.lck = lck;
4931 ctx->dispc_cinfo.pck = pck;
4932
4933 if (dsi_vm_calc_blanking(ctx) == false)
4934 return false;
4935
4936 #ifdef PRINT_VERBOSE_VM_TIMINGS
4937 print_dispc_vm("dispc", &ctx->dispc_vm);
4938 print_dsi_vm("dsi ", &ctx->dsi_vm);
4939 print_dispc_vm("req ", ctx->config->timings);
4940 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4941 #endif
4942
4943 return true;
4944 }
4945
4946 static bool dsi_vm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4947 void *data)
4948 {
4949 struct dsi_clk_calc_ctx *ctx = data;
4950 unsigned long pck_max;
4951
4952 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4953 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4954
4955 /*
4956 * In burst mode we can let the dispc pck be arbitrarily high, but it
4957 * limits our scaling abilities. So for now, don't aim too high.
4958 */
4959
4960 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4961 pck_max = ctx->req_pck_max + 10000000;
4962 else
4963 pck_max = ctx->req_pck_max;
4964
4965 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4966 dsi_vm_calc_dispc_cb, ctx);
4967 }
4968
4969 static bool dsi_vm_calc_pll_cb(int regn, int regm, unsigned long fint,
4970 unsigned long pll, void *data)
4971 {
4972 struct dsi_clk_calc_ctx *ctx = data;
4973
4974 ctx->dsi_cinfo.regn = regn;
4975 ctx->dsi_cinfo.regm = regm;
4976 ctx->dsi_cinfo.fint = fint;
4977 ctx->dsi_cinfo.clkin4ddr = pll;
4978
4979 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
4980 dsi_vm_calc_hsdiv_cb, ctx);
4981 }
4982
4983 static bool dsi_vm_calc(struct dsi_data *dsi,
4984 const struct omap_dss_dsi_config *cfg,
4985 struct dsi_clk_calc_ctx *ctx)
4986 {
4987 const struct omap_video_timings *t = cfg->timings;
4988 unsigned long clkin;
4989 unsigned long pll_min;
4990 unsigned long pll_max;
4991 int ndl = dsi->num_lanes_used - 1;
4992 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4993 unsigned long byteclk_min;
4994
4995 clkin = clk_get_rate(dsi->sys_clk);
4996
4997 memset(ctx, 0, sizeof(*ctx));
4998 ctx->dsidev = dsi->pdev;
4999 ctx->config = cfg;
5000
5001 ctx->dsi_cinfo.clkin = clkin;
5002
5003 /* these limits should come from the panel driver */
5004 ctx->req_pck_min = t->pixel_clock * 1000 - 1000;
5005 ctx->req_pck_nom = t->pixel_clock * 1000;
5006 ctx->req_pck_max = t->pixel_clock * 1000 + 1000;
5007
5008 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
5009 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
5010
5011 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
5012 pll_max = cfg->hs_clk_max * 4;
5013 } else {
5014 unsigned long byteclk_max;
5015 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
5016 ndl * 8);
5017
5018 pll_max = byteclk_max * 4 * 4;
5019 }
5020
5021 return dsi_pll_calc(dsi->pdev, clkin,
5022 pll_min, pll_max,
5023 dsi_vm_calc_pll_cb, ctx);
5024 }
5025
5026 static int dsi_set_config(struct omap_dss_device *dssdev,
5027 const struct omap_dss_dsi_config *config)
5028 {
5029 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5030 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5031 struct dsi_clk_calc_ctx ctx;
5032 bool ok;
5033 int r;
5034
5035 mutex_lock(&dsi->lock);
5036
5037 dsi->pix_fmt = config->pixel_format;
5038 dsi->mode = config->mode;
5039
5040 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
5041 ok = dsi_vm_calc(dsi, config, &ctx);
5042 else
5043 ok = dsi_cm_calc(dsi, config, &ctx);
5044
5045 if (!ok) {
5046 DSSERR("failed to find suitable DSI clock settings\n");
5047 r = -EINVAL;
5048 goto err;
5049 }
5050
5051 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
5052
5053 r = dsi_lp_clock_calc(&ctx.dsi_cinfo, config->lp_clk_min,
5054 config->lp_clk_max);
5055 if (r) {
5056 DSSERR("failed to find suitable DSI LP clock settings\n");
5057 goto err;
5058 }
5059
5060 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
5061 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
5062
5063 dsi->timings = ctx.dispc_vm;
5064 dsi->vm_timings = ctx.dsi_vm;
5065
5066 mutex_unlock(&dsi->lock);
5067
5068 return 0;
5069 err:
5070 mutex_unlock(&dsi->lock);
5071
5072 return r;
5073 }
5074
5075 /*
5076 * Return a hardcoded channel for the DSI output. This should work for
5077 * current use cases, but this can be later expanded to either resolve
5078 * the channel in some more dynamic manner, or get the channel as a user
5079 * parameter.
5080 */
5081 static enum omap_channel dsi_get_channel(int module_id)
5082 {
5083 switch (omapdss_get_version()) {
5084 case OMAPDSS_VER_OMAP24xx:
5085 DSSWARN("DSI not supported\n");
5086 return OMAP_DSS_CHANNEL_LCD;
5087
5088 case OMAPDSS_VER_OMAP34xx_ES1:
5089 case OMAPDSS_VER_OMAP34xx_ES3:
5090 case OMAPDSS_VER_OMAP3630:
5091 case OMAPDSS_VER_AM35xx:
5092 return OMAP_DSS_CHANNEL_LCD;
5093
5094 case OMAPDSS_VER_OMAP4430_ES1:
5095 case OMAPDSS_VER_OMAP4430_ES2:
5096 case OMAPDSS_VER_OMAP4:
5097 switch (module_id) {
5098 case 0:
5099 return OMAP_DSS_CHANNEL_LCD;
5100 case 1:
5101 return OMAP_DSS_CHANNEL_LCD2;
5102 default:
5103 DSSWARN("unsupported module id\n");
5104 return OMAP_DSS_CHANNEL_LCD;
5105 }
5106
5107 case OMAPDSS_VER_OMAP5:
5108 switch (module_id) {
5109 case 0:
5110 return OMAP_DSS_CHANNEL_LCD;
5111 case 1:
5112 return OMAP_DSS_CHANNEL_LCD3;
5113 default:
5114 DSSWARN("unsupported module id\n");
5115 return OMAP_DSS_CHANNEL_LCD;
5116 }
5117
5118 default:
5119 DSSWARN("unsupported DSS version\n");
5120 return OMAP_DSS_CHANNEL_LCD;
5121 }
5122 }
5123
5124 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5125 {
5126 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5127 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5128 int i;
5129
5130 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5131 if (!dsi->vc[i].dssdev) {
5132 dsi->vc[i].dssdev = dssdev;
5133 *channel = i;
5134 return 0;
5135 }
5136 }
5137
5138 DSSERR("cannot get VC for display %s", dssdev->name);
5139 return -ENOSPC;
5140 }
5141
5142 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5143 {
5144 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5145 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5146
5147 if (vc_id < 0 || vc_id > 3) {
5148 DSSERR("VC ID out of range\n");
5149 return -EINVAL;
5150 }
5151
5152 if (channel < 0 || channel > 3) {
5153 DSSERR("Virtual Channel out of range\n");
5154 return -EINVAL;
5155 }
5156
5157 if (dsi->vc[channel].dssdev != dssdev) {
5158 DSSERR("Virtual Channel not allocated to display %s\n",
5159 dssdev->name);
5160 return -EINVAL;
5161 }
5162
5163 dsi->vc[channel].vc_id = vc_id;
5164
5165 return 0;
5166 }
5167
5168 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5169 {
5170 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5171 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5172
5173 if ((channel >= 0 && channel <= 3) &&
5174 dsi->vc[channel].dssdev == dssdev) {
5175 dsi->vc[channel].dssdev = NULL;
5176 dsi->vc[channel].vc_id = 0;
5177 }
5178 }
5179
5180 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5181 {
5182 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5183 DSSERR("%s (%s) not active\n",
5184 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5185 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5186 }
5187
5188 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5189 {
5190 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5191 DSSERR("%s (%s) not active\n",
5192 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5193 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5194 }
5195
5196 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5197 {
5198 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5199
5200 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5201 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5202 dsi->regm_dispc_max =
5203 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5204 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5205 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5206 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5207 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5208 }
5209
5210 static int dsi_get_clocks(struct platform_device *dsidev)
5211 {
5212 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5213 struct clk *clk;
5214
5215 clk = devm_clk_get(&dsidev->dev, "fck");
5216 if (IS_ERR(clk)) {
5217 DSSERR("can't get fck\n");
5218 return PTR_ERR(clk);
5219 }
5220
5221 dsi->dss_clk = clk;
5222
5223 clk = devm_clk_get(&dsidev->dev, "sys_clk");
5224 if (IS_ERR(clk)) {
5225 DSSERR("can't get sys_clk\n");
5226 return PTR_ERR(clk);
5227 }
5228
5229 dsi->sys_clk = clk;
5230
5231 return 0;
5232 }
5233
5234 static int dsi_connect(struct omap_dss_device *dssdev,
5235 struct omap_dss_device *dst)
5236 {
5237 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5238 struct omap_overlay_manager *mgr;
5239 int r;
5240
5241 r = dsi_regulator_init(dsidev);
5242 if (r)
5243 return r;
5244
5245 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
5246 if (!mgr)
5247 return -ENODEV;
5248
5249 r = dss_mgr_connect(mgr, dssdev);
5250 if (r)
5251 return r;
5252
5253 r = omapdss_output_set_device(dssdev, dst);
5254 if (r) {
5255 DSSERR("failed to connect output to new device: %s\n",
5256 dssdev->name);
5257 dss_mgr_disconnect(mgr, dssdev);
5258 return r;
5259 }
5260
5261 return 0;
5262 }
5263
5264 static void dsi_disconnect(struct omap_dss_device *dssdev,
5265 struct omap_dss_device *dst)
5266 {
5267 WARN_ON(dst != dssdev->dst);
5268
5269 if (dst != dssdev->dst)
5270 return;
5271
5272 omapdss_output_unset_device(dssdev);
5273
5274 if (dssdev->manager)
5275 dss_mgr_disconnect(dssdev->manager, dssdev);
5276 }
5277
5278 static const struct omapdss_dsi_ops dsi_ops = {
5279 .connect = dsi_connect,
5280 .disconnect = dsi_disconnect,
5281
5282 .bus_lock = dsi_bus_lock,
5283 .bus_unlock = dsi_bus_unlock,
5284
5285 .enable = dsi_display_enable,
5286 .disable = dsi_display_disable,
5287
5288 .enable_hs = dsi_vc_enable_hs,
5289
5290 .configure_pins = dsi_configure_pins,
5291 .set_config = dsi_set_config,
5292
5293 .enable_video_output = dsi_enable_video_output,
5294 .disable_video_output = dsi_disable_video_output,
5295
5296 .update = dsi_update,
5297
5298 .enable_te = dsi_enable_te,
5299
5300 .request_vc = dsi_request_vc,
5301 .set_vc_id = dsi_set_vc_id,
5302 .release_vc = dsi_release_vc,
5303
5304 .dcs_write = dsi_vc_dcs_write,
5305 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
5306 .dcs_read = dsi_vc_dcs_read,
5307
5308 .gen_write = dsi_vc_generic_write,
5309 .gen_write_nosync = dsi_vc_generic_write_nosync,
5310 .gen_read = dsi_vc_generic_read,
5311
5312 .bta_sync = dsi_vc_send_bta_sync,
5313
5314 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5315 };
5316
5317 static void dsi_init_output(struct platform_device *dsidev)
5318 {
5319 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5320 struct omap_dss_device *out = &dsi->output;
5321
5322 out->dev = &dsidev->dev;
5323 out->id = dsi->module_id == 0 ?
5324 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5325
5326 out->output_type = OMAP_DISPLAY_TYPE_DSI;
5327 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5328 out->dispc_channel = dsi_get_channel(dsi->module_id);
5329 out->ops.dsi = &dsi_ops;
5330 out->owner = THIS_MODULE;
5331
5332 omapdss_register_output(out);
5333 }
5334
5335 static void dsi_uninit_output(struct platform_device *dsidev)
5336 {
5337 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5338 struct omap_dss_device *out = &dsi->output;
5339
5340 omapdss_unregister_output(out);
5341 }
5342
5343 /* DSI1 HW IP initialisation */
5344 static int omap_dsihw_probe(struct platform_device *dsidev)
5345 {
5346 u32 rev;
5347 int r, i;
5348 struct resource *dsi_mem;
5349 struct dsi_data *dsi;
5350
5351 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5352 if (!dsi)
5353 return -ENOMEM;
5354
5355 dsi->module_id = dsidev->id;
5356 dsi->pdev = dsidev;
5357 dev_set_drvdata(&dsidev->dev, dsi);
5358
5359 spin_lock_init(&dsi->irq_lock);
5360 spin_lock_init(&dsi->errors_lock);
5361 dsi->errors = 0;
5362
5363 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5364 spin_lock_init(&dsi->irq_stats_lock);
5365 dsi->irq_stats.last_reset = jiffies;
5366 #endif
5367
5368 mutex_init(&dsi->lock);
5369 sema_init(&dsi->bus_lock, 1);
5370
5371 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5372 dsi_framedone_timeout_work_callback);
5373
5374 #ifdef DSI_CATCH_MISSING_TE
5375 init_timer(&dsi->te_timer);
5376 dsi->te_timer.function = dsi_te_timeout;
5377 dsi->te_timer.data = 0;
5378 #endif
5379 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
5380 if (!dsi_mem) {
5381 DSSERR("can't get IORESOURCE_MEM DSI\n");
5382 return -EINVAL;
5383 }
5384
5385 dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
5386 resource_size(dsi_mem));
5387 if (!dsi->base) {
5388 DSSERR("can't ioremap DSI\n");
5389 return -ENOMEM;
5390 }
5391
5392 dsi->irq = platform_get_irq(dsi->pdev, 0);
5393 if (dsi->irq < 0) {
5394 DSSERR("platform_get_irq failed\n");
5395 return -ENODEV;
5396 }
5397
5398 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5399 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5400 if (r < 0) {
5401 DSSERR("request_irq failed\n");
5402 return r;
5403 }
5404
5405 /* DSI VCs initialization */
5406 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5407 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5408 dsi->vc[i].dssdev = NULL;
5409 dsi->vc[i].vc_id = 0;
5410 }
5411
5412 dsi_calc_clock_param_ranges(dsidev);
5413
5414 r = dsi_get_clocks(dsidev);
5415 if (r)
5416 return r;
5417
5418 pm_runtime_enable(&dsidev->dev);
5419
5420 r = dsi_runtime_get(dsidev);
5421 if (r)
5422 goto err_runtime_get;
5423
5424 rev = dsi_read_reg(dsidev, DSI_REVISION);
5425 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5426 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5427
5428 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5429 * of data to 3 by default */
5430 if (dss_has_feature(FEAT_DSI_GNQ))
5431 /* NB_DATA_LANES */
5432 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5433 else
5434 dsi->num_lanes_supported = 3;
5435
5436 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5437
5438 dsi_init_output(dsidev);
5439
5440 dsi_runtime_put(dsidev);
5441
5442 if (dsi->module_id == 0)
5443 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5444 else if (dsi->module_id == 1)
5445 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5446
5447 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5448 if (dsi->module_id == 0)
5449 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5450 else if (dsi->module_id == 1)
5451 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5452 #endif
5453 return 0;
5454
5455 err_runtime_get:
5456 pm_runtime_disable(&dsidev->dev);
5457 return r;
5458 }
5459
5460 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5461 {
5462 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5463
5464 WARN_ON(dsi->scp_clk_refcount > 0);
5465
5466 dsi_uninit_output(dsidev);
5467
5468 pm_runtime_disable(&dsidev->dev);
5469
5470 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5471 regulator_disable(dsi->vdds_dsi_reg);
5472 dsi->vdds_dsi_enabled = false;
5473 }
5474
5475 return 0;
5476 }
5477
5478 static int dsi_runtime_suspend(struct device *dev)
5479 {
5480 dispc_runtime_put();
5481
5482 return 0;
5483 }
5484
5485 static int dsi_runtime_resume(struct device *dev)
5486 {
5487 int r;
5488
5489 r = dispc_runtime_get();
5490 if (r)
5491 return r;
5492
5493 return 0;
5494 }
5495
5496 static const struct dev_pm_ops dsi_pm_ops = {
5497 .runtime_suspend = dsi_runtime_suspend,
5498 .runtime_resume = dsi_runtime_resume,
5499 };
5500
5501 static struct platform_driver omap_dsihw_driver = {
5502 .probe = omap_dsihw_probe,
5503 .remove = __exit_p(omap_dsihw_remove),
5504 .driver = {
5505 .name = "omapdss_dsi",
5506 .owner = THIS_MODULE,
5507 .pm = &dsi_pm_ops,
5508 },
5509 };
5510
5511 int __init dsi_init_platform_driver(void)
5512 {
5513 return platform_driver_register(&omap_dsihw_driver);
5514 }
5515
5516 void __exit dsi_uninit_platform_driver(void)
5517 {
5518 platform_driver_unregister(&omap_dsihw_driver);
5519 }
Linux kernel - Deliverables
This page took 0.145695 seconds and 5 git commands to generate.