2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/seq_file.h>
31 #include <linux/platform_device.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/kthread.h>
34 #include <linux/wait.h>
36 #include <plat/display.h>
37 #include <plat/clock.h>
41 /*#define VERBOSE_IRQ*/
42 #define DSI_CATCH_MISSING_TE
44 #define DSI_BASE 0x4804FC00
46 struct dsi_reg
{ u16 idx
; };
48 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
50 #define DSI_SZ_REGS SZ_1K
51 /* DSI Protocol Engine */
53 #define DSI_REVISION DSI_REG(0x0000)
54 #define DSI_SYSCONFIG DSI_REG(0x0010)
55 #define DSI_SYSSTATUS DSI_REG(0x0014)
56 #define DSI_IRQSTATUS DSI_REG(0x0018)
57 #define DSI_IRQENABLE DSI_REG(0x001C)
58 #define DSI_CTRL DSI_REG(0x0040)
59 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
60 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
61 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
62 #define DSI_CLK_CTRL DSI_REG(0x0054)
63 #define DSI_TIMING1 DSI_REG(0x0058)
64 #define DSI_TIMING2 DSI_REG(0x005C)
65 #define DSI_VM_TIMING1 DSI_REG(0x0060)
66 #define DSI_VM_TIMING2 DSI_REG(0x0064)
67 #define DSI_VM_TIMING3 DSI_REG(0x0068)
68 #define DSI_CLK_TIMING DSI_REG(0x006C)
69 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
70 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
71 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
72 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
73 #define DSI_VM_TIMING4 DSI_REG(0x0080)
74 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
75 #define DSI_VM_TIMING5 DSI_REG(0x0088)
76 #define DSI_VM_TIMING6 DSI_REG(0x008C)
77 #define DSI_VM_TIMING7 DSI_REG(0x0090)
78 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
79 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
80 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
83 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
84 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
85 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
89 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
90 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
91 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
92 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94 /* DSI_PLL_CTRL_SCP */
96 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
97 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
98 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
99 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
100 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
102 #define REG_GET(idx, start, end) \
103 FLD_GET(dsi_read_reg(idx), start, end)
105 #define REG_FLD_MOD(idx, val, start, end) \
106 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
108 /* Global interrupts */
109 #define DSI_IRQ_VC0 (1 << 0)
110 #define DSI_IRQ_VC1 (1 << 1)
111 #define DSI_IRQ_VC2 (1 << 2)
112 #define DSI_IRQ_VC3 (1 << 3)
113 #define DSI_IRQ_WAKEUP (1 << 4)
114 #define DSI_IRQ_RESYNC (1 << 5)
115 #define DSI_IRQ_PLL_LOCK (1 << 7)
116 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
117 #define DSI_IRQ_PLL_RECALL (1 << 9)
118 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
119 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
120 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
121 #define DSI_IRQ_TE_TRIGGER (1 << 16)
122 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
123 #define DSI_IRQ_SYNC_LOST (1 << 18)
124 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
125 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
126 #define DSI_IRQ_ERROR_MASK \
127 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
129 #define DSI_IRQ_CHANNEL_MASK 0xf
131 /* Virtual channel interrupts */
132 #define DSI_VC_IRQ_CS (1 << 0)
133 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
134 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
135 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
136 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
137 #define DSI_VC_IRQ_BTA (1 << 5)
138 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
139 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
140 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
141 #define DSI_VC_IRQ_ERROR_MASK \
142 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
143 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
144 DSI_VC_IRQ_FIFO_TX_UDF)
146 /* ComplexIO interrupts */
147 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
148 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
149 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
150 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
151 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
152 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
153 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
154 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
155 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
156 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
157 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
158 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
159 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
164 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
165 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
166 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
168 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
169 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
170 #define DSI_DT_DCS_READ 0x06
171 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
172 #define DSI_DT_NULL_PACKET 0x09
173 #define DSI_DT_DCS_LONG_WRITE 0x39
175 #define DSI_DT_RX_ACK_WITH_ERR 0x02
176 #define DSI_DT_RX_DCS_LONG_READ 0x1c
177 #define DSI_DT_RX_SHORT_READ_1 0x21
178 #define DSI_DT_RX_SHORT_READ_2 0x22
180 #define FINT_MAX 2100000
181 #define FINT_MIN 750000
182 #define REGN_MAX (1 << 7)
183 #define REGM_MAX ((1 << 11) - 1)
184 #define REGM3_MAX (1 << 4)
185 #define REGM4_MAX (1 << 4)
186 #define LP_DIV_MAX ((1 << 13) - 1)
190 DSI_FIFO_SIZE_32
= 1,
191 DSI_FIFO_SIZE_64
= 2,
192 DSI_FIFO_SIZE_96
= 3,
193 DSI_FIFO_SIZE_128
= 4,
201 struct dsi_update_region
{
204 struct omap_dss_device
*device
;
207 struct dsi_irq_stats
{
208 unsigned long last_reset
;
210 unsigned dsi_irqs
[32];
211 unsigned vc_irqs
[4][32];
212 unsigned cio_irqs
[32];
219 struct dsi_clock_info current_cinfo
;
221 struct regulator
*vdds_dsi_reg
;
224 enum dsi_vc_mode mode
;
225 struct omap_dss_device
*dssdev
;
226 enum fifo_size fifo_size
;
227 int dest_per
; /* destination peripheral 0-3 */
231 struct mutex bus_lock
;
235 struct completion bta_completion
;
237 struct task_struct
*thread
;
238 wait_queue_head_t waitqueue
;
240 spinlock_t update_lock
;
241 bool framedone_received
;
242 struct dsi_update_region update_region
;
243 struct dsi_update_region active_update_region
;
244 struct completion update_completion
;
246 enum omap_dss_update_mode user_update_mode
;
247 enum omap_dss_update_mode update_mode
;
251 #ifdef DSI_CATCH_MISSING_TE
252 struct timer_list te_timer
;
255 unsigned long cache_req_pck
;
256 unsigned long cache_clk_freq
;
257 struct dsi_clock_info cache_cinfo
;
260 spinlock_t errors_lock
;
262 ktime_t perf_setup_time
;
263 ktime_t perf_start_time
;
264 ktime_t perf_start_time_auto
;
265 int perf_measure_frames
;
270 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
271 spinlock_t irq_stats_lock
;
272 struct dsi_irq_stats irq_stats
;
277 static unsigned int dsi_perf
;
278 module_param_named(dsi_perf
, dsi_perf
, bool, 0644);
281 static inline void dsi_write_reg(const struct dsi_reg idx
, u32 val
)
283 __raw_writel(val
, dsi
.base
+ idx
.idx
);
286 static inline u32
dsi_read_reg(const struct dsi_reg idx
)
288 return __raw_readl(dsi
.base
+ idx
.idx
);
292 void dsi_save_context(void)
296 void dsi_restore_context(void)
300 void dsi_bus_lock(void)
302 mutex_lock(&dsi
.bus_lock
);
304 EXPORT_SYMBOL(dsi_bus_lock
);
306 void dsi_bus_unlock(void)
308 mutex_unlock(&dsi
.bus_lock
);
310 EXPORT_SYMBOL(dsi_bus_unlock
);
312 static bool dsi_bus_is_locked(void)
314 return mutex_is_locked(&dsi
.bus_lock
);
317 static inline int wait_for_bit_change(const struct dsi_reg idx
, int bitnum
,
322 while (REG_GET(idx
, bitnum
, bitnum
) != value
) {
331 static void dsi_perf_mark_setup(void)
333 dsi
.perf_setup_time
= ktime_get();
336 static void dsi_perf_mark_start(void)
338 dsi
.perf_start_time
= ktime_get();
341 static void dsi_perf_mark_start_auto(void)
343 dsi
.perf_measure_frames
= 0;
344 dsi
.perf_start_time_auto
= ktime_get();
347 static void dsi_perf_show(const char *name
)
349 ktime_t t
, setup_time
, trans_time
;
351 u32 setup_us
, trans_us
, total_us
;
356 if (dsi
.update_mode
== OMAP_DSS_UPDATE_DISABLED
)
361 setup_time
= ktime_sub(dsi
.perf_start_time
, dsi
.perf_setup_time
);
362 setup_us
= (u32
)ktime_to_us(setup_time
);
366 trans_time
= ktime_sub(t
, dsi
.perf_start_time
);
367 trans_us
= (u32
)ktime_to_us(trans_time
);
371 total_us
= setup_us
+ trans_us
;
373 total_bytes
= dsi
.active_update_region
.w
*
374 dsi
.active_update_region
.h
*
375 dsi
.active_update_region
.device
->ctrl
.pixel_size
/ 8;
377 if (dsi
.update_mode
== OMAP_DSS_UPDATE_AUTO
) {
378 static u32 s_total_trans_us
, s_total_setup_us
;
379 static u32 s_min_trans_us
= 0xffffffff, s_min_setup_us
;
380 static u32 s_max_trans_us
, s_max_setup_us
;
381 const int numframes
= 100;
382 ktime_t total_time_auto
;
383 u32 total_time_auto_us
;
385 dsi
.perf_measure_frames
++;
387 if (setup_us
< s_min_setup_us
)
388 s_min_setup_us
= setup_us
;
390 if (setup_us
> s_max_setup_us
)
391 s_max_setup_us
= setup_us
;
393 s_total_setup_us
+= setup_us
;
395 if (trans_us
< s_min_trans_us
)
396 s_min_trans_us
= trans_us
;
398 if (trans_us
> s_max_trans_us
)
399 s_max_trans_us
= trans_us
;
401 s_total_trans_us
+= trans_us
;
403 if (dsi
.perf_measure_frames
< numframes
)
406 total_time_auto
= ktime_sub(t
, dsi
.perf_start_time_auto
);
407 total_time_auto_us
= (u32
)ktime_to_us(total_time_auto
);
409 printk(KERN_INFO
"DSI(%s): %u fps, setup %u/%u/%u, "
412 1000 * 1000 * numframes
/ total_time_auto_us
,
415 s_total_setup_us
/ numframes
,
418 s_total_trans_us
/ numframes
);
420 s_total_setup_us
= 0;
421 s_min_setup_us
= 0xffffffff;
423 s_total_trans_us
= 0;
424 s_min_trans_us
= 0xffffffff;
426 dsi_perf_mark_start_auto();
428 printk(KERN_INFO
"DSI(%s): %u us + %u us = %u us (%uHz), "
429 "%u bytes, %u kbytes/sec\n",
434 1000*1000 / total_us
,
436 total_bytes
* 1000 / total_us
);
440 #define dsi_perf_mark_setup()
441 #define dsi_perf_mark_start()
442 #define dsi_perf_mark_start_auto()
443 #define dsi_perf_show(x)
446 static void print_irq_status(u32 status
)
449 if ((status
& ~DSI_IRQ_CHANNEL_MASK
) == 0)
452 printk(KERN_DEBUG
"DSI IRQ: 0x%x: ", status
);
455 if (status & DSI_IRQ_##x) \
481 static void print_irq_status_vc(int channel
, u32 status
)
484 if ((status
& ~DSI_VC_IRQ_PACKET_SENT
) == 0)
487 printk(KERN_DEBUG
"DSI VC(%d) IRQ 0x%x: ", channel
, status
);
490 if (status & DSI_VC_IRQ_##x) \
507 static void print_irq_status_cio(u32 status
)
509 printk(KERN_DEBUG
"DSI CIO IRQ 0x%x: ", status
);
512 if (status & DSI_CIO_IRQ_##x) \
526 PIS(ERRCONTENTIONLP0_1
);
527 PIS(ERRCONTENTIONLP1_1
);
528 PIS(ERRCONTENTIONLP0_2
);
529 PIS(ERRCONTENTIONLP1_2
);
530 PIS(ERRCONTENTIONLP0_3
);
531 PIS(ERRCONTENTIONLP1_3
);
532 PIS(ULPSACTIVENOT_ALL0
);
533 PIS(ULPSACTIVENOT_ALL1
);
539 static int debug_irq
;
541 /* called from dss */
542 void dsi_irq_handler(void)
544 u32 irqstatus
, vcstatus
, ciostatus
;
547 irqstatus
= dsi_read_reg(DSI_IRQSTATUS
);
549 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
550 spin_lock(&dsi
.irq_stats_lock
);
551 dsi
.irq_stats
.irq_count
++;
552 dss_collect_irq_stats(irqstatus
, dsi
.irq_stats
.dsi_irqs
);
555 if (irqstatus
& DSI_IRQ_ERROR_MASK
) {
556 DSSERR("DSI error, irqstatus %x\n", irqstatus
);
557 print_irq_status(irqstatus
);
558 spin_lock(&dsi
.errors_lock
);
559 dsi
.errors
|= irqstatus
& DSI_IRQ_ERROR_MASK
;
560 spin_unlock(&dsi
.errors_lock
);
561 } else if (debug_irq
) {
562 print_irq_status(irqstatus
);
565 #ifdef DSI_CATCH_MISSING_TE
566 if (irqstatus
& DSI_IRQ_TE_TRIGGER
)
567 del_timer(&dsi
.te_timer
);
570 for (i
= 0; i
< 4; ++i
) {
571 if ((irqstatus
& (1<<i
)) == 0)
574 vcstatus
= dsi_read_reg(DSI_VC_IRQSTATUS(i
));
576 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
577 dss_collect_irq_stats(vcstatus
, dsi
.irq_stats
.vc_irqs
[i
]);
580 if (vcstatus
& DSI_VC_IRQ_BTA
)
581 complete(&dsi
.bta_completion
);
583 if (vcstatus
& DSI_VC_IRQ_ERROR_MASK
) {
584 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
586 print_irq_status_vc(i
, vcstatus
);
587 } else if (debug_irq
) {
588 print_irq_status_vc(i
, vcstatus
);
591 dsi_write_reg(DSI_VC_IRQSTATUS(i
), vcstatus
);
592 /* flush posted write */
593 dsi_read_reg(DSI_VC_IRQSTATUS(i
));
596 if (irqstatus
& DSI_IRQ_COMPLEXIO_ERR
) {
597 ciostatus
= dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS
);
599 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
600 dss_collect_irq_stats(ciostatus
, dsi
.irq_stats
.cio_irqs
);
603 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS
, ciostatus
);
604 /* flush posted write */
605 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS
);
607 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus
);
608 print_irq_status_cio(ciostatus
);
611 dsi_write_reg(DSI_IRQSTATUS
, irqstatus
& ~DSI_IRQ_CHANNEL_MASK
);
612 /* flush posted write */
613 dsi_read_reg(DSI_IRQSTATUS
);
615 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
616 spin_unlock(&dsi
.irq_stats_lock
);
621 static void _dsi_initialize_irq(void)
626 /* disable all interrupts */
627 dsi_write_reg(DSI_IRQENABLE
, 0);
628 for (i
= 0; i
< 4; ++i
)
629 dsi_write_reg(DSI_VC_IRQENABLE(i
), 0);
630 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE
, 0);
632 /* clear interrupt status */
633 l
= dsi_read_reg(DSI_IRQSTATUS
);
634 dsi_write_reg(DSI_IRQSTATUS
, l
& ~DSI_IRQ_CHANNEL_MASK
);
636 for (i
= 0; i
< 4; ++i
) {
637 l
= dsi_read_reg(DSI_VC_IRQSTATUS(i
));
638 dsi_write_reg(DSI_VC_IRQSTATUS(i
), l
);
641 l
= dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS
);
642 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS
, l
);
644 /* enable error irqs */
645 l
= DSI_IRQ_ERROR_MASK
;
646 #ifdef DSI_CATCH_MISSING_TE
647 l
|= DSI_IRQ_TE_TRIGGER
;
649 dsi_write_reg(DSI_IRQENABLE
, l
);
651 l
= DSI_VC_IRQ_ERROR_MASK
;
652 for (i
= 0; i
< 4; ++i
)
653 dsi_write_reg(DSI_VC_IRQENABLE(i
), l
);
655 /* XXX zonda responds incorrectly, causing control error:
656 Exit from LP-ESC mode to LP11 uses wrong transition states on the
657 data lines LP0 and LN0. */
658 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE
,
659 -1 & (~DSI_CIO_IRQ_ERRCONTROL2
));
662 static u32
dsi_get_errors(void)
666 spin_lock_irqsave(&dsi
.errors_lock
, flags
);
669 spin_unlock_irqrestore(&dsi
.errors_lock
, flags
);
673 static void dsi_vc_enable_bta_irq(int channel
)
677 dsi_write_reg(DSI_VC_IRQSTATUS(channel
), DSI_VC_IRQ_BTA
);
679 l
= dsi_read_reg(DSI_VC_IRQENABLE(channel
));
681 dsi_write_reg(DSI_VC_IRQENABLE(channel
), l
);
684 static void dsi_vc_disable_bta_irq(int channel
)
688 l
= dsi_read_reg(DSI_VC_IRQENABLE(channel
));
689 l
&= ~DSI_VC_IRQ_BTA
;
690 dsi_write_reg(DSI_VC_IRQENABLE(channel
), l
);
693 /* DSI func clock. this could also be DSI2_PLL_FCLK */
694 static inline void enable_clocks(bool enable
)
697 dss_clk_enable(DSS_CLK_ICK
| DSS_CLK_FCK1
);
699 dss_clk_disable(DSS_CLK_ICK
| DSS_CLK_FCK1
);
702 /* source clock for DSI PLL. this could also be PCLKFREE */
703 static inline void dsi_enable_pll_clock(bool enable
)
706 dss_clk_enable(DSS_CLK_FCK2
);
708 dss_clk_disable(DSS_CLK_FCK2
);
710 if (enable
&& dsi
.pll_locked
) {
711 if (wait_for_bit_change(DSI_PLL_STATUS
, 1, 1) != 1)
712 DSSERR("cannot lock PLL when enabling clocks\n");
717 static void _dsi_print_reset_status(void)
724 /* A dummy read using the SCP interface to any DSIPHY register is
725 * required after DSIPHY reset to complete the reset of the DSI complex
727 l
= dsi_read_reg(DSI_DSIPHY_CFG5
);
729 printk(KERN_DEBUG
"DSI resets: ");
731 l
= dsi_read_reg(DSI_PLL_STATUS
);
732 printk("PLL (%d) ", FLD_GET(l
, 0, 0));
734 l
= dsi_read_reg(DSI_COMPLEXIO_CFG1
);
735 printk("CIO (%d) ", FLD_GET(l
, 29, 29));
737 l
= dsi_read_reg(DSI_DSIPHY_CFG5
);
738 printk("PHY (%x, %d, %d, %d)\n",
745 #define _dsi_print_reset_status()
748 static inline int dsi_if_enable(bool enable
)
750 DSSDBG("dsi_if_enable(%d)\n", enable
);
752 enable
= enable
? 1 : 0;
753 REG_FLD_MOD(DSI_CTRL
, enable
, 0, 0); /* IF_EN */
755 if (wait_for_bit_change(DSI_CTRL
, 0, enable
) != enable
) {
756 DSSERR("Failed to set dsi_if_enable to %d\n", enable
);
763 unsigned long dsi_get_dsi1_pll_rate(void)
765 return dsi
.current_cinfo
.dsi1_pll_fclk
;
768 static unsigned long dsi_get_dsi2_pll_rate(void)
770 return dsi
.current_cinfo
.dsi2_pll_fclk
;
773 static unsigned long dsi_get_txbyteclkhs(void)
775 return dsi
.current_cinfo
.clkin4ddr
/ 16;
778 static unsigned long dsi_fclk_rate(void)
782 if (dss_get_dsi_clk_source() == 0) {
783 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
784 r
= dss_clk_get_rate(DSS_CLK_FCK1
);
786 /* DSI FCLK source is DSI2_PLL_FCLK */
787 r
= dsi_get_dsi2_pll_rate();
793 static int dsi_set_lp_clk_divisor(struct omap_dss_device
*dssdev
)
795 unsigned long dsi_fclk
;
797 unsigned long lp_clk
;
799 lp_clk_div
= dssdev
->phy
.dsi
.div
.lp_clk_div
;
801 if (lp_clk_div
== 0 || lp_clk_div
> LP_DIV_MAX
)
804 dsi_fclk
= dsi_fclk_rate();
806 lp_clk
= dsi_fclk
/ 2 / lp_clk_div
;
808 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div
, lp_clk
);
809 dsi
.current_cinfo
.lp_clk
= lp_clk
;
810 dsi
.current_cinfo
.lp_clk_div
= lp_clk_div
;
812 REG_FLD_MOD(DSI_CLK_CTRL
, lp_clk_div
, 12, 0); /* LP_CLK_DIVISOR */
814 REG_FLD_MOD(DSI_CLK_CTRL
, dsi_fclk
> 30000000 ? 1 : 0,
815 21, 21); /* LP_RX_SYNCHRO_ENABLE */
821 enum dsi_pll_power_state
{
822 DSI_PLL_POWER_OFF
= 0x0,
823 DSI_PLL_POWER_ON_HSCLK
= 0x1,
824 DSI_PLL_POWER_ON_ALL
= 0x2,
825 DSI_PLL_POWER_ON_DIV
= 0x3,
828 static int dsi_pll_power(enum dsi_pll_power_state state
)
832 REG_FLD_MOD(DSI_CLK_CTRL
, state
, 31, 30); /* PLL_PWR_CMD */
835 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL
), 29, 28) != state
) {
837 DSSERR("Failed to set DSI PLL power mode to %d\n",
847 /* calculate clock rates using dividers in cinfo */
848 static int dsi_calc_clock_rates(struct dsi_clock_info
*cinfo
)
850 if (cinfo
->regn
== 0 || cinfo
->regn
> REGN_MAX
)
853 if (cinfo
->regm
== 0 || cinfo
->regm
> REGM_MAX
)
856 if (cinfo
->regm3
> REGM3_MAX
)
859 if (cinfo
->regm4
> REGM4_MAX
)
862 if (cinfo
->use_dss2_fck
) {
863 cinfo
->clkin
= dss_clk_get_rate(DSS_CLK_FCK2
);
864 /* XXX it is unclear if highfreq should be used
865 * with DSS2_FCK source also */
868 cinfo
->clkin
= dispc_pclk_rate();
870 if (cinfo
->clkin
< 32000000)
876 cinfo
->fint
= cinfo
->clkin
/ (cinfo
->regn
* (cinfo
->highfreq
? 2 : 1));
878 if (cinfo
->fint
> FINT_MAX
|| cinfo
->fint
< FINT_MIN
)
881 cinfo
->clkin4ddr
= 2 * cinfo
->regm
* cinfo
->fint
;
883 if (cinfo
->clkin4ddr
> 1800 * 1000 * 1000)
886 if (cinfo
->regm3
> 0)
887 cinfo
->dsi1_pll_fclk
= cinfo
->clkin4ddr
/ cinfo
->regm3
;
889 cinfo
->dsi1_pll_fclk
= 0;
891 if (cinfo
->regm4
> 0)
892 cinfo
->dsi2_pll_fclk
= cinfo
->clkin4ddr
/ cinfo
->regm4
;
894 cinfo
->dsi2_pll_fclk
= 0;
899 int dsi_pll_calc_clock_div_pck(bool is_tft
, unsigned long req_pck
,
900 struct dsi_clock_info
*dsi_cinfo
,
901 struct dispc_clock_info
*dispc_cinfo
)
903 struct dsi_clock_info cur
, best
;
904 struct dispc_clock_info best_dispc
;
907 unsigned long dss_clk_fck2
;
909 dss_clk_fck2
= dss_clk_get_rate(DSS_CLK_FCK2
);
911 if (req_pck
== dsi
.cache_req_pck
&&
912 dsi
.cache_cinfo
.clkin
== dss_clk_fck2
) {
913 DSSDBG("DSI clock info found from cache\n");
914 *dsi_cinfo
= dsi
.cache_cinfo
;
915 dispc_find_clk_divs(is_tft
, req_pck
, dsi_cinfo
->dsi1_pll_fclk
,
920 min_fck_per_pck
= CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
;
922 if (min_fck_per_pck
&&
923 req_pck
* min_fck_per_pck
> DISPC_MAX_FCK
) {
924 DSSERR("Requested pixel clock not possible with the current "
925 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
926 "the constraint off.\n");
930 DSSDBG("dsi_pll_calc\n");
933 memset(&best
, 0, sizeof(best
));
934 memset(&best_dispc
, 0, sizeof(best_dispc
));
936 memset(&cur
, 0, sizeof(cur
));
937 cur
.clkin
= dss_clk_fck2
;
938 cur
.use_dss2_fck
= 1;
941 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
942 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
943 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
944 for (cur
.regn
= 1; cur
.regn
< REGN_MAX
; ++cur
.regn
) {
945 if (cur
.highfreq
== 0)
946 cur
.fint
= cur
.clkin
/ cur
.regn
;
948 cur
.fint
= cur
.clkin
/ (2 * cur
.regn
);
950 if (cur
.fint
> FINT_MAX
|| cur
.fint
< FINT_MIN
)
953 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
954 for (cur
.regm
= 1; cur
.regm
< REGM_MAX
; ++cur
.regm
) {
957 a
= 2 * cur
.regm
* (cur
.clkin
/1000);
958 b
= cur
.regn
* (cur
.highfreq
+ 1);
959 cur
.clkin4ddr
= a
/ b
* 1000;
961 if (cur
.clkin4ddr
> 1800 * 1000 * 1000)
964 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
965 for (cur
.regm3
= 1; cur
.regm3
< REGM3_MAX
;
967 struct dispc_clock_info cur_dispc
;
968 cur
.dsi1_pll_fclk
= cur
.clkin4ddr
/ cur
.regm3
;
970 /* this will narrow down the search a bit,
971 * but still give pixclocks below what was
973 if (cur
.dsi1_pll_fclk
< req_pck
)
976 if (cur
.dsi1_pll_fclk
> DISPC_MAX_FCK
)
979 if (min_fck_per_pck
&&
981 req_pck
* min_fck_per_pck
)
986 dispc_find_clk_divs(is_tft
, req_pck
,
990 if (abs(cur_dispc
.pck
- req_pck
) <
991 abs(best_dispc
.pck
- req_pck
)) {
993 best_dispc
= cur_dispc
;
995 if (cur_dispc
.pck
== req_pck
)
1003 if (min_fck_per_pck
) {
1004 DSSERR("Could not find suitable clock settings.\n"
1005 "Turning FCK/PCK constraint off and"
1007 min_fck_per_pck
= 0;
1011 DSSERR("Could not find suitable clock settings.\n");
1016 /* DSI2_PLL_FCLK (regm4) is not used */
1018 best
.dsi2_pll_fclk
= 0;
1023 *dispc_cinfo
= best_dispc
;
1025 dsi
.cache_req_pck
= req_pck
;
1026 dsi
.cache_clk_freq
= 0;
1027 dsi
.cache_cinfo
= best
;
1032 int dsi_pll_set_clock_div(struct dsi_clock_info
*cinfo
)
1040 dsi
.current_cinfo
.fint
= cinfo
->fint
;
1041 dsi
.current_cinfo
.clkin4ddr
= cinfo
->clkin4ddr
;
1042 dsi
.current_cinfo
.dsi1_pll_fclk
= cinfo
->dsi1_pll_fclk
;
1043 dsi
.current_cinfo
.dsi2_pll_fclk
= cinfo
->dsi2_pll_fclk
;
1045 dsi
.current_cinfo
.regn
= cinfo
->regn
;
1046 dsi
.current_cinfo
.regm
= cinfo
->regm
;
1047 dsi
.current_cinfo
.regm3
= cinfo
->regm3
;
1048 dsi
.current_cinfo
.regm4
= cinfo
->regm4
;
1050 DSSDBG("DSI Fint %ld\n", cinfo
->fint
);
1052 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1053 cinfo
->use_dss2_fck
? "dss2_fck" : "pclkfree",
1057 /* DSIPHY == CLKIN4DDR */
1058 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1062 cinfo
->highfreq
+ 1,
1065 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1066 cinfo
->clkin4ddr
/ 1000 / 1000 / 2);
1068 DSSDBG("Clock lane freq %ld Hz\n", cinfo
->clkin4ddr
/ 4);
1070 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1071 cinfo
->regm3
, cinfo
->dsi1_pll_fclk
);
1072 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1073 cinfo
->regm4
, cinfo
->dsi2_pll_fclk
);
1075 REG_FLD_MOD(DSI_PLL_CONTROL
, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1077 l
= dsi_read_reg(DSI_PLL_CONFIGURATION1
);
1078 l
= FLD_MOD(l
, 1, 0, 0); /* DSI_PLL_STOPMODE */
1079 l
= FLD_MOD(l
, cinfo
->regn
- 1, 7, 1); /* DSI_PLL_REGN */
1080 l
= FLD_MOD(l
, cinfo
->regm
, 18, 8); /* DSI_PLL_REGM */
1081 l
= FLD_MOD(l
, cinfo
->regm3
> 0 ? cinfo
->regm3
- 1 : 0,
1082 22, 19); /* DSI_CLOCK_DIV */
1083 l
= FLD_MOD(l
, cinfo
->regm4
> 0 ? cinfo
->regm4
- 1 : 0,
1084 26, 23); /* DSIPROTO_CLOCK_DIV */
1085 dsi_write_reg(DSI_PLL_CONFIGURATION1
, l
);
1087 BUG_ON(cinfo
->fint
< 750000 || cinfo
->fint
> 2100000);
1088 if (cinfo
->fint
< 1000000)
1090 else if (cinfo
->fint
< 1250000)
1092 else if (cinfo
->fint
< 1500000)
1094 else if (cinfo
->fint
< 1750000)
1099 l
= dsi_read_reg(DSI_PLL_CONFIGURATION2
);
1100 l
= FLD_MOD(l
, f
, 4, 1); /* DSI_PLL_FREQSEL */
1101 l
= FLD_MOD(l
, cinfo
->use_dss2_fck
? 0 : 1,
1102 11, 11); /* DSI_PLL_CLKSEL */
1103 l
= FLD_MOD(l
, cinfo
->highfreq
,
1104 12, 12); /* DSI_PLL_HIGHFREQ */
1105 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1106 l
= FLD_MOD(l
, 0, 14, 14); /* DSIPHY_CLKINEN */
1107 l
= FLD_MOD(l
, 1, 20, 20); /* DSI_HSDIVBYPASS */
1108 dsi_write_reg(DSI_PLL_CONFIGURATION2
, l
);
1110 REG_FLD_MOD(DSI_PLL_GO
, 1, 0, 0); /* DSI_PLL_GO */
1112 if (wait_for_bit_change(DSI_PLL_GO
, 0, 0) != 0) {
1113 DSSERR("dsi pll go bit not going down.\n");
1118 if (wait_for_bit_change(DSI_PLL_STATUS
, 1, 1) != 1) {
1119 DSSERR("cannot lock PLL\n");
1126 l
= dsi_read_reg(DSI_PLL_CONFIGURATION2
);
1127 l
= FLD_MOD(l
, 0, 0, 0); /* DSI_PLL_IDLE */
1128 l
= FLD_MOD(l
, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1129 l
= FLD_MOD(l
, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1130 l
= FLD_MOD(l
, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1131 l
= FLD_MOD(l
, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1132 l
= FLD_MOD(l
, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1133 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1134 l
= FLD_MOD(l
, 1, 14, 14); /* DSIPHY_CLKINEN */
1135 l
= FLD_MOD(l
, 0, 15, 15); /* DSI_BYPASSEN */
1136 l
= FLD_MOD(l
, 1, 16, 16); /* DSS_CLOCK_EN */
1137 l
= FLD_MOD(l
, 0, 17, 17); /* DSS_CLOCK_PWDN */
1138 l
= FLD_MOD(l
, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1139 l
= FLD_MOD(l
, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1140 l
= FLD_MOD(l
, 0, 20, 20); /* DSI_HSDIVBYPASS */
1141 dsi_write_reg(DSI_PLL_CONFIGURATION2
, l
);
1143 DSSDBG("PLL config done\n");
1148 int dsi_pll_init(struct omap_dss_device
*dssdev
, bool enable_hsclk
,
1152 enum dsi_pll_power_state pwstate
;
1154 DSSDBG("PLL init\n");
1157 dsi_enable_pll_clock(1);
1159 r
= regulator_enable(dsi
.vdds_dsi_reg
);
1163 /* XXX PLL does not come out of reset without this... */
1164 dispc_pck_free_enable(1);
1166 if (wait_for_bit_change(DSI_PLL_STATUS
, 0, 1) != 1) {
1167 DSSERR("PLL not coming out of reset.\n");
1172 /* XXX ... but if left on, we get problems when planes do not
1173 * fill the whole display. No idea about this */
1174 dispc_pck_free_enable(0);
1176 if (enable_hsclk
&& enable_hsdiv
)
1177 pwstate
= DSI_PLL_POWER_ON_ALL
;
1178 else if (enable_hsclk
)
1179 pwstate
= DSI_PLL_POWER_ON_HSCLK
;
1180 else if (enable_hsdiv
)
1181 pwstate
= DSI_PLL_POWER_ON_DIV
;
1183 pwstate
= DSI_PLL_POWER_OFF
;
1185 r
= dsi_pll_power(pwstate
);
1190 DSSDBG("PLL init done\n");
1194 regulator_disable(dsi
.vdds_dsi_reg
);
1197 dsi_enable_pll_clock(0);
1201 void dsi_pll_uninit(void)
1204 dsi_enable_pll_clock(0);
1207 dsi_pll_power(DSI_PLL_POWER_OFF
);
1208 regulator_disable(dsi
.vdds_dsi_reg
);
1209 DSSDBG("PLL uninit done\n");
1212 void dsi_dump_clocks(struct seq_file
*s
)
1215 struct dsi_clock_info
*cinfo
= &dsi
.current_cinfo
;
1219 clksel
= REG_GET(DSI_PLL_CONFIGURATION2
, 11, 11);
1221 seq_printf(s
, "- DSI PLL -\n");
1223 seq_printf(s
, "dsi pll source = %s\n",
1225 "dss2_alwon_fclk" : "pclkfree");
1227 seq_printf(s
, "Fint\t\t%-16luregn %u\n", cinfo
->fint
, cinfo
->regn
);
1229 seq_printf(s
, "CLKIN4DDR\t%-16luregm %u\n",
1230 cinfo
->clkin4ddr
, cinfo
->regm
);
1232 seq_printf(s
, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1233 cinfo
->dsi1_pll_fclk
,
1235 dss_get_dispc_clk_source() == 0 ? "off" : "on");
1237 seq_printf(s
, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1238 cinfo
->dsi2_pll_fclk
,
1240 dss_get_dsi_clk_source() == 0 ? "off" : "on");
1242 seq_printf(s
, "- DSI -\n");
1244 seq_printf(s
, "dsi fclk source = %s\n",
1245 dss_get_dsi_clk_source() == 0 ?
1246 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1248 seq_printf(s
, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1250 seq_printf(s
, "DDR_CLK\t\t%lu\n",
1251 cinfo
->clkin4ddr
/ 4);
1253 seq_printf(s
, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1255 seq_printf(s
, "LP_CLK\t\t%lu\n", cinfo
->lp_clk
);
1257 seq_printf(s
, "VP_CLK\t\t%lu\n"
1265 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1266 void dsi_dump_irqs(struct seq_file
*s
)
1268 unsigned long flags
;
1269 struct dsi_irq_stats stats
;
1271 spin_lock_irqsave(&dsi
.irq_stats_lock
, flags
);
1273 stats
= dsi
.irq_stats
;
1274 memset(&dsi
.irq_stats
, 0, sizeof(dsi
.irq_stats
));
1275 dsi
.irq_stats
.last_reset
= jiffies
;
1277 spin_unlock_irqrestore(&dsi
.irq_stats_lock
, flags
);
1279 seq_printf(s
, "period %u ms\n",
1280 jiffies_to_msecs(jiffies
- stats
.last_reset
));
1282 seq_printf(s
, "irqs %d\n", stats
.irq_count
);
1284 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1286 seq_printf(s
, "-- DSI interrupts --\n");
1302 PIS(LDO_POWER_GOOD
);
1307 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1308 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1309 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1310 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1311 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1313 seq_printf(s
, "-- VC interrupts --\n");
1322 PIS(PP_BUSY_CHANGE
);
1326 seq_printf(s, "%-20s %10d\n", #x, \
1327 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1329 seq_printf(s
, "-- CIO interrupts --\n");
1342 PIS(ERRCONTENTIONLP0_1
);
1343 PIS(ERRCONTENTIONLP1_1
);
1344 PIS(ERRCONTENTIONLP0_2
);
1345 PIS(ERRCONTENTIONLP1_2
);
1346 PIS(ERRCONTENTIONLP0_3
);
1347 PIS(ERRCONTENTIONLP1_3
);
1348 PIS(ULPSACTIVENOT_ALL0
);
1349 PIS(ULPSACTIVENOT_ALL1
);
1354 void dsi_dump_regs(struct seq_file
*s
)
1356 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1358 dss_clk_enable(DSS_CLK_ICK
| DSS_CLK_FCK1
);
1360 DUMPREG(DSI_REVISION
);
1361 DUMPREG(DSI_SYSCONFIG
);
1362 DUMPREG(DSI_SYSSTATUS
);
1363 DUMPREG(DSI_IRQSTATUS
);
1364 DUMPREG(DSI_IRQENABLE
);
1366 DUMPREG(DSI_COMPLEXIO_CFG1
);
1367 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS
);
1368 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE
);
1369 DUMPREG(DSI_CLK_CTRL
);
1370 DUMPREG(DSI_TIMING1
);
1371 DUMPREG(DSI_TIMING2
);
1372 DUMPREG(DSI_VM_TIMING1
);
1373 DUMPREG(DSI_VM_TIMING2
);
1374 DUMPREG(DSI_VM_TIMING3
);
1375 DUMPREG(DSI_CLK_TIMING
);
1376 DUMPREG(DSI_TX_FIFO_VC_SIZE
);
1377 DUMPREG(DSI_RX_FIFO_VC_SIZE
);
1378 DUMPREG(DSI_COMPLEXIO_CFG2
);
1379 DUMPREG(DSI_RX_FIFO_VC_FULLNESS
);
1380 DUMPREG(DSI_VM_TIMING4
);
1381 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS
);
1382 DUMPREG(DSI_VM_TIMING5
);
1383 DUMPREG(DSI_VM_TIMING6
);
1384 DUMPREG(DSI_VM_TIMING7
);
1385 DUMPREG(DSI_STOPCLK_TIMING
);
1387 DUMPREG(DSI_VC_CTRL(0));
1388 DUMPREG(DSI_VC_TE(0));
1389 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1390 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1391 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1392 DUMPREG(DSI_VC_IRQSTATUS(0));
1393 DUMPREG(DSI_VC_IRQENABLE(0));
1395 DUMPREG(DSI_VC_CTRL(1));
1396 DUMPREG(DSI_VC_TE(1));
1397 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1398 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1399 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1400 DUMPREG(DSI_VC_IRQSTATUS(1));
1401 DUMPREG(DSI_VC_IRQENABLE(1));
1403 DUMPREG(DSI_VC_CTRL(2));
1404 DUMPREG(DSI_VC_TE(2));
1405 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1406 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1407 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1408 DUMPREG(DSI_VC_IRQSTATUS(2));
1409 DUMPREG(DSI_VC_IRQENABLE(2));
1411 DUMPREG(DSI_VC_CTRL(3));
1412 DUMPREG(DSI_VC_TE(3));
1413 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1414 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1415 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1416 DUMPREG(DSI_VC_IRQSTATUS(3));
1417 DUMPREG(DSI_VC_IRQENABLE(3));
1419 DUMPREG(DSI_DSIPHY_CFG0
);
1420 DUMPREG(DSI_DSIPHY_CFG1
);
1421 DUMPREG(DSI_DSIPHY_CFG2
);
1422 DUMPREG(DSI_DSIPHY_CFG5
);
1424 DUMPREG(DSI_PLL_CONTROL
);
1425 DUMPREG(DSI_PLL_STATUS
);
1426 DUMPREG(DSI_PLL_GO
);
1427 DUMPREG(DSI_PLL_CONFIGURATION1
);
1428 DUMPREG(DSI_PLL_CONFIGURATION2
);
1430 dss_clk_disable(DSS_CLK_ICK
| DSS_CLK_FCK1
);
1434 enum dsi_complexio_power_state
{
1435 DSI_COMPLEXIO_POWER_OFF
= 0x0,
1436 DSI_COMPLEXIO_POWER_ON
= 0x1,
1437 DSI_COMPLEXIO_POWER_ULPS
= 0x2,
1440 static int dsi_complexio_power(enum dsi_complexio_power_state state
)
1445 REG_FLD_MOD(DSI_COMPLEXIO_CFG1
, state
, 28, 27);
1448 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1
), 26, 25) != state
) {
1450 DSSERR("failed to set complexio power state to "
1460 static void dsi_complexio_config(struct omap_dss_device
*dssdev
)
1464 int clk_lane
= dssdev
->phy
.dsi
.clk_lane
;
1465 int data1_lane
= dssdev
->phy
.dsi
.data1_lane
;
1466 int data2_lane
= dssdev
->phy
.dsi
.data2_lane
;
1467 int clk_pol
= dssdev
->phy
.dsi
.clk_pol
;
1468 int data1_pol
= dssdev
->phy
.dsi
.data1_pol
;
1469 int data2_pol
= dssdev
->phy
.dsi
.data2_pol
;
1471 r
= dsi_read_reg(DSI_COMPLEXIO_CFG1
);
1472 r
= FLD_MOD(r
, clk_lane
, 2, 0);
1473 r
= FLD_MOD(r
, clk_pol
, 3, 3);
1474 r
= FLD_MOD(r
, data1_lane
, 6, 4);
1475 r
= FLD_MOD(r
, data1_pol
, 7, 7);
1476 r
= FLD_MOD(r
, data2_lane
, 10, 8);
1477 r
= FLD_MOD(r
, data2_pol
, 11, 11);
1478 dsi_write_reg(DSI_COMPLEXIO_CFG1
, r
);
1480 /* The configuration of the DSI complex I/O (number of data lanes,
1481 position, differential order) should not be changed while
1482 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1483 the hardware to take into account a new configuration of the complex
1484 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1485 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1486 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1487 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1488 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1489 DSI complex I/O configuration is unknown. */
1492 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1493 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1494 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1495 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1499 static inline unsigned ns2ddr(unsigned ns
)
1501 /* convert time in ns to ddr ticks, rounding up */
1502 unsigned long ddr_clk
= dsi
.current_cinfo
.clkin4ddr
/ 4;
1503 return (ns
* (ddr_clk
/ 1000 / 1000) + 999) / 1000;
1506 static inline unsigned ddr2ns(unsigned ddr
)
1508 unsigned long ddr_clk
= dsi
.current_cinfo
.clkin4ddr
/ 4;
1509 return ddr
* 1000 * 1000 / (ddr_clk
/ 1000);
1512 static void dsi_complexio_timings(void)
1515 u32 ths_prepare
, ths_prepare_ths_zero
, ths_trail
, ths_exit
;
1516 u32 tlpx_half
, tclk_trail
, tclk_zero
;
1519 /* calculate timings */
1521 /* 1 * DDR_CLK = 2 * UI */
1523 /* min 40ns + 4*UI max 85ns + 6*UI */
1524 ths_prepare
= ns2ddr(70) + 2;
1526 /* min 145ns + 10*UI */
1527 ths_prepare_ths_zero
= ns2ddr(175) + 2;
1529 /* min max(8*UI, 60ns+4*UI) */
1530 ths_trail
= ns2ddr(60) + 5;
1533 ths_exit
= ns2ddr(145);
1536 tlpx_half
= ns2ddr(25);
1539 tclk_trail
= ns2ddr(60) + 2;
1541 /* min 38ns, max 95ns */
1542 tclk_prepare
= ns2ddr(65);
1544 /* min tclk-prepare + tclk-zero = 300ns */
1545 tclk_zero
= ns2ddr(260);
1547 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1548 ths_prepare
, ddr2ns(ths_prepare
),
1549 ths_prepare_ths_zero
, ddr2ns(ths_prepare_ths_zero
));
1550 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1551 ths_trail
, ddr2ns(ths_trail
),
1552 ths_exit
, ddr2ns(ths_exit
));
1554 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1555 "tclk_zero %u (%uns)\n",
1556 tlpx_half
, ddr2ns(tlpx_half
),
1557 tclk_trail
, ddr2ns(tclk_trail
),
1558 tclk_zero
, ddr2ns(tclk_zero
));
1559 DSSDBG("tclk_prepare %u (%uns)\n",
1560 tclk_prepare
, ddr2ns(tclk_prepare
));
1562 /* program timings */
1564 r
= dsi_read_reg(DSI_DSIPHY_CFG0
);
1565 r
= FLD_MOD(r
, ths_prepare
, 31, 24);
1566 r
= FLD_MOD(r
, ths_prepare_ths_zero
, 23, 16);
1567 r
= FLD_MOD(r
, ths_trail
, 15, 8);
1568 r
= FLD_MOD(r
, ths_exit
, 7, 0);
1569 dsi_write_reg(DSI_DSIPHY_CFG0
, r
);
1571 r
= dsi_read_reg(DSI_DSIPHY_CFG1
);
1572 r
= FLD_MOD(r
, tlpx_half
, 22, 16);
1573 r
= FLD_MOD(r
, tclk_trail
, 15, 8);
1574 r
= FLD_MOD(r
, tclk_zero
, 7, 0);
1575 dsi_write_reg(DSI_DSIPHY_CFG1
, r
);
1577 r
= dsi_read_reg(DSI_DSIPHY_CFG2
);
1578 r
= FLD_MOD(r
, tclk_prepare
, 7, 0);
1579 dsi_write_reg(DSI_DSIPHY_CFG2
, r
);
1583 static int dsi_complexio_init(struct omap_dss_device
*dssdev
)
1587 DSSDBG("dsi_complexio_init\n");
1589 /* CIO_CLK_ICG, enable L3 clk to CIO */
1590 REG_FLD_MOD(DSI_CLK_CTRL
, 1, 14, 14);
1592 /* A dummy read using the SCP interface to any DSIPHY register is
1593 * required after DSIPHY reset to complete the reset of the DSI complex
1595 dsi_read_reg(DSI_DSIPHY_CFG5
);
1597 if (wait_for_bit_change(DSI_DSIPHY_CFG5
, 30, 1) != 1) {
1598 DSSERR("ComplexIO PHY not coming out of reset.\n");
1603 dsi_complexio_config(dssdev
);
1605 r
= dsi_complexio_power(DSI_COMPLEXIO_POWER_ON
);
1610 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1
, 29, 1) != 1) {
1611 DSSERR("ComplexIO not coming out of reset.\n");
1616 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1
, 21, 1) != 1) {
1617 DSSERR("ComplexIO LDO power down.\n");
1622 dsi_complexio_timings();
1625 The configuration of the DSI complex I/O (number of data lanes,
1626 position, differential order) should not be changed while
1627 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1628 hardware to recognize a new configuration of the complex I/O (done
1629 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1630 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1631 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1632 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1633 bit to 1. If the sequence is not followed, the DSi complex I/O
1634 configuration is undetermined.
1638 REG_FLD_MOD(DSI_CLK_CTRL
, 1, 20, 20); /* LP_CLK_ENABLE */
1642 DSSDBG("CIO init done\n");
1647 static void dsi_complexio_uninit(void)
1649 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF
);
1652 static int _dsi_wait_reset(void)
1656 while (REG_GET(DSI_SYSSTATUS
, 0, 0) == 0) {
1658 DSSERR("soft reset failed\n");
1667 static int _dsi_reset(void)
1670 REG_FLD_MOD(DSI_SYSCONFIG
, 1, 1, 1);
1671 return _dsi_wait_reset();
1674 static void dsi_reset_tx_fifo(int channel
)
1679 /* set fifosize of the channel to 0, then return the old size */
1680 l
= dsi_read_reg(DSI_TX_FIFO_VC_SIZE
);
1682 mask
= FLD_MASK((8 * channel
) + 7, (8 * channel
) + 4);
1683 dsi_write_reg(DSI_TX_FIFO_VC_SIZE
, l
& ~mask
);
1685 dsi_write_reg(DSI_TX_FIFO_VC_SIZE
, l
);
1688 static void dsi_config_tx_fifo(enum fifo_size size1
, enum fifo_size size2
,
1689 enum fifo_size size3
, enum fifo_size size4
)
1695 dsi
.vc
[0].fifo_size
= size1
;
1696 dsi
.vc
[1].fifo_size
= size2
;
1697 dsi
.vc
[2].fifo_size
= size3
;
1698 dsi
.vc
[3].fifo_size
= size4
;
1700 for (i
= 0; i
< 4; i
++) {
1702 int size
= dsi
.vc
[i
].fifo_size
;
1704 if (add
+ size
> 4) {
1705 DSSERR("Illegal FIFO configuration\n");
1709 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
1711 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1715 dsi_write_reg(DSI_TX_FIFO_VC_SIZE
, r
);
1718 static void dsi_config_rx_fifo(enum fifo_size size1
, enum fifo_size size2
,
1719 enum fifo_size size3
, enum fifo_size size4
)
1725 dsi
.vc
[0].fifo_size
= size1
;
1726 dsi
.vc
[1].fifo_size
= size2
;
1727 dsi
.vc
[2].fifo_size
= size3
;
1728 dsi
.vc
[3].fifo_size
= size4
;
1730 for (i
= 0; i
< 4; i
++) {
1732 int size
= dsi
.vc
[i
].fifo_size
;
1734 if (add
+ size
> 4) {
1735 DSSERR("Illegal FIFO configuration\n");
1739 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
1741 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1745 dsi_write_reg(DSI_RX_FIFO_VC_SIZE
, r
);
1748 static int dsi_force_tx_stop_mode_io(void)
1752 r
= dsi_read_reg(DSI_TIMING1
);
1753 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1754 dsi_write_reg(DSI_TIMING1
, r
);
1756 if (wait_for_bit_change(DSI_TIMING1
, 15, 0) != 0) {
1757 DSSERR("TX_STOP bit not going down\n");
1764 static void dsi_vc_print_status(int channel
)
1768 r
= dsi_read_reg(DSI_VC_CTRL(channel
));
1769 DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
1770 "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
1776 FLD_GET(r
, 20, 20));
1778 r
= dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS
);
1779 DSSDBG("EMPTINESS %d\n", (r
>> (8 * channel
)) & 0xff);
1782 static int dsi_vc_enable(int channel
, bool enable
)
1784 if (dsi
.update_mode
!= OMAP_DSS_UPDATE_AUTO
)
1785 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1788 enable
= enable
? 1 : 0;
1790 REG_FLD_MOD(DSI_VC_CTRL(channel
), enable
, 0, 0);
1792 if (wait_for_bit_change(DSI_VC_CTRL(channel
), 0, enable
) != enable
) {
1793 DSSERR("Failed to set dsi_vc_enable to %d\n", enable
);
1800 static void dsi_vc_initial_config(int channel
)
1804 DSSDBGF("%d", channel
);
1806 r
= dsi_read_reg(DSI_VC_CTRL(channel
));
1808 if (FLD_GET(r
, 15, 15)) /* VC_BUSY */
1809 DSSERR("VC(%d) busy when trying to configure it!\n",
1812 r
= FLD_MOD(r
, 0, 1, 1); /* SOURCE, 0 = L4 */
1813 r
= FLD_MOD(r
, 0, 2, 2); /* BTA_SHORT_EN */
1814 r
= FLD_MOD(r
, 0, 3, 3); /* BTA_LONG_EN */
1815 r
= FLD_MOD(r
, 0, 4, 4); /* MODE, 0 = command */
1816 r
= FLD_MOD(r
, 1, 7, 7); /* CS_TX_EN */
1817 r
= FLD_MOD(r
, 1, 8, 8); /* ECC_TX_EN */
1818 r
= FLD_MOD(r
, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1820 r
= FLD_MOD(r
, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1821 r
= FLD_MOD(r
, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1823 dsi_write_reg(DSI_VC_CTRL(channel
), r
);
1825 dsi
.vc
[channel
].mode
= DSI_VC_MODE_L4
;
1828 static void dsi_vc_config_l4(int channel
)
1830 if (dsi
.vc
[channel
].mode
== DSI_VC_MODE_L4
)
1833 DSSDBGF("%d", channel
);
1835 dsi_vc_enable(channel
, 0);
1837 if (REG_GET(DSI_VC_CTRL(channel
), 15, 15)) /* VC_BUSY */
1838 DSSERR("vc(%d) busy when trying to config for L4\n", channel
);
1840 REG_FLD_MOD(DSI_VC_CTRL(channel
), 0, 1, 1); /* SOURCE, 0 = L4 */
1842 dsi_vc_enable(channel
, 1);
1844 dsi
.vc
[channel
].mode
= DSI_VC_MODE_L4
;
1847 static void dsi_vc_config_vp(int channel
)
1849 if (dsi
.vc
[channel
].mode
== DSI_VC_MODE_VP
)
1852 DSSDBGF("%d", channel
);
1854 dsi_vc_enable(channel
, 0);
1856 if (REG_GET(DSI_VC_CTRL(channel
), 15, 15)) /* VC_BUSY */
1857 DSSERR("vc(%d) busy when trying to config for VP\n", channel
);
1859 REG_FLD_MOD(DSI_VC_CTRL(channel
), 1, 1, 1); /* SOURCE, 1 = video port */
1861 dsi_vc_enable(channel
, 1);
1863 dsi
.vc
[channel
].mode
= DSI_VC_MODE_VP
;
1867 void omapdss_dsi_vc_enable_hs(int channel
, bool enable
)
1869 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel
, enable
);
1871 WARN_ON(!dsi_bus_is_locked());
1873 dsi_vc_enable(channel
, 0);
1876 REG_FLD_MOD(DSI_VC_CTRL(channel
), enable
, 9, 9);
1878 dsi_vc_enable(channel
, 1);
1881 dsi_force_tx_stop_mode_io();
1883 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs
);
1885 static void dsi_vc_flush_long_data(int channel
)
1887 while (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) {
1889 val
= dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel
));
1890 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1894 (val
>> 24) & 0xff);
1898 static void dsi_show_rx_ack_with_err(u16 err
)
1900 DSSERR("\tACK with ERROR (%#x):\n", err
);
1902 DSSERR("\t\tSoT Error\n");
1904 DSSERR("\t\tSoT Sync Error\n");
1906 DSSERR("\t\tEoT Sync Error\n");
1908 DSSERR("\t\tEscape Mode Entry Command Error\n");
1910 DSSERR("\t\tLP Transmit Sync Error\n");
1912 DSSERR("\t\tHS Receive Timeout Error\n");
1914 DSSERR("\t\tFalse Control Error\n");
1916 DSSERR("\t\t(reserved7)\n");
1918 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1920 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1921 if (err
& (1 << 10))
1922 DSSERR("\t\tChecksum Error\n");
1923 if (err
& (1 << 11))
1924 DSSERR("\t\tData type not recognized\n");
1925 if (err
& (1 << 12))
1926 DSSERR("\t\tInvalid VC ID\n");
1927 if (err
& (1 << 13))
1928 DSSERR("\t\tInvalid Transmission Length\n");
1929 if (err
& (1 << 14))
1930 DSSERR("\t\t(reserved14)\n");
1931 if (err
& (1 << 15))
1932 DSSERR("\t\tDSI Protocol Violation\n");
1935 static u16
dsi_vc_flush_receive_data(int channel
)
1937 /* RX_FIFO_NOT_EMPTY */
1938 while (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) {
1941 val
= dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel
));
1942 DSSDBG("\trawval %#08x\n", val
);
1943 dt
= FLD_GET(val
, 5, 0);
1944 if (dt
== DSI_DT_RX_ACK_WITH_ERR
) {
1945 u16 err
= FLD_GET(val
, 23, 8);
1946 dsi_show_rx_ack_with_err(err
);
1947 } else if (dt
== DSI_DT_RX_SHORT_READ_1
) {
1948 DSSDBG("\tDCS short response, 1 byte: %#x\n",
1949 FLD_GET(val
, 23, 8));
1950 } else if (dt
== DSI_DT_RX_SHORT_READ_2
) {
1951 DSSDBG("\tDCS short response, 2 byte: %#x\n",
1952 FLD_GET(val
, 23, 8));
1953 } else if (dt
== DSI_DT_RX_DCS_LONG_READ
) {
1954 DSSDBG("\tDCS long response, len %d\n",
1955 FLD_GET(val
, 23, 8));
1956 dsi_vc_flush_long_data(channel
);
1958 DSSERR("\tunknown datatype 0x%02x\n", dt
);
1964 static int dsi_vc_send_bta(int channel
)
1966 if (dsi
.update_mode
!= OMAP_DSS_UPDATE_AUTO
&&
1967 (dsi
.debug_write
|| dsi
.debug_read
))
1968 DSSDBG("dsi_vc_send_bta %d\n", channel
);
1970 WARN_ON(!dsi_bus_is_locked());
1972 if (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1973 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1974 dsi_vc_flush_receive_data(channel
);
1977 REG_FLD_MOD(DSI_VC_CTRL(channel
), 1, 6, 6); /* BTA_EN */
1982 int dsi_vc_send_bta_sync(int channel
)
1987 INIT_COMPLETION(dsi
.bta_completion
);
1989 dsi_vc_enable_bta_irq(channel
);
1991 r
= dsi_vc_send_bta(channel
);
1995 if (wait_for_completion_timeout(&dsi
.bta_completion
,
1996 msecs_to_jiffies(500)) == 0) {
1997 DSSERR("Failed to receive BTA\n");
2002 err
= dsi_get_errors();
2004 DSSERR("Error while sending BTA: %x\n", err
);
2009 dsi_vc_disable_bta_irq(channel
);
2013 EXPORT_SYMBOL(dsi_vc_send_bta_sync
);
2015 static inline void dsi_vc_write_long_header(int channel
, u8 data_type
,
2021 WARN_ON(!dsi_bus_is_locked());
2023 /*data_id = data_type | channel << 6; */
2024 data_id
= data_type
| dsi
.vc
[channel
].dest_per
<< 6;
2026 val
= FLD_VAL(data_id
, 7, 0) | FLD_VAL(len
, 23, 8) |
2027 FLD_VAL(ecc
, 31, 24);
2029 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel
), val
);
2032 static inline void dsi_vc_write_long_payload(int channel
,
2033 u8 b1
, u8 b2
, u8 b3
, u8 b4
)
2037 val
= b4
<< 24 | b3
<< 16 | b2
<< 8 | b1
<< 0;
2039 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2040 b1, b2, b3, b4, val); */
2042 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel
), val
);
2045 static int dsi_vc_send_long(int channel
, u8 data_type
, u8
*data
, u16 len
,
2054 if (dsi
.debug_write
)
2055 DSSDBG("dsi_vc_send_long, %d bytes\n", len
);
2058 if (dsi
.vc
[channel
].fifo_size
* 32 * 4 < len
+ 4) {
2059 DSSERR("unable to send long packet: packet too long.\n");
2063 dsi_vc_config_l4(channel
);
2065 dsi_vc_write_long_header(channel
, data_type
, len
, ecc
);
2067 /*dsi_vc_print_status(0); */
2070 for (i
= 0; i
< len
>> 2; i
++) {
2071 if (dsi
.debug_write
)
2072 DSSDBG("\tsending full packet %d\n", i
);
2073 /*dsi_vc_print_status(0); */
2080 dsi_vc_write_long_payload(channel
, b1
, b2
, b3
, b4
);
2085 b1
= 0; b2
= 0; b3
= 0;
2087 if (dsi
.debug_write
)
2088 DSSDBG("\tsending remainder bytes %d\n", i
);
2105 dsi_vc_write_long_payload(channel
, b1
, b2
, b3
, 0);
2111 static int dsi_vc_send_short(int channel
, u8 data_type
, u16 data
, u8 ecc
)
2116 WARN_ON(!dsi_bus_is_locked());
2118 if (dsi
.debug_write
)
2119 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2121 data_type
, data
& 0xff, (data
>> 8) & 0xff);
2123 dsi_vc_config_l4(channel
);
2125 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel
)), 16, 16)) {
2126 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2130 data_id
= data_type
| dsi
.vc
[channel
].dest_per
<< 6;
2132 r
= (data_id
<< 0) | (data
<< 8) | (ecc
<< 24);
2134 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel
), r
);
2139 int dsi_vc_send_null(int channel
)
2141 u8 nullpkg
[] = {0, 0, 0, 0};
2142 return dsi_vc_send_long(channel
, DSI_DT_NULL_PACKET
, nullpkg
, 4, 0);
2144 EXPORT_SYMBOL(dsi_vc_send_null
);
2146 int dsi_vc_dcs_write_nosync(int channel
, u8
*data
, int len
)
2153 r
= dsi_vc_send_short(channel
, DSI_DT_DCS_SHORT_WRITE_0
,
2155 } else if (len
== 2) {
2156 r
= dsi_vc_send_short(channel
, DSI_DT_DCS_SHORT_WRITE_1
,
2157 data
[0] | (data
[1] << 8), 0);
2159 /* 0x39 = DCS Long Write */
2160 r
= dsi_vc_send_long(channel
, DSI_DT_DCS_LONG_WRITE
,
2166 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync
);
2168 int dsi_vc_dcs_write(int channel
, u8
*data
, int len
)
2172 r
= dsi_vc_dcs_write_nosync(channel
, data
, len
);
2176 r
= dsi_vc_send_bta_sync(channel
);
2180 EXPORT_SYMBOL(dsi_vc_dcs_write
);
2182 int dsi_vc_dcs_write_0(int channel
, u8 dcs_cmd
)
2184 return dsi_vc_dcs_write(channel
, &dcs_cmd
, 1);
2186 EXPORT_SYMBOL(dsi_vc_dcs_write_0
);
2188 int dsi_vc_dcs_write_1(int channel
, u8 dcs_cmd
, u8 param
)
2193 return dsi_vc_dcs_write(channel
, buf
, 2);
2195 EXPORT_SYMBOL(dsi_vc_dcs_write_1
);
2197 int dsi_vc_dcs_read(int channel
, u8 dcs_cmd
, u8
*buf
, int buflen
)
2204 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel
, dcs_cmd
);
2206 r
= dsi_vc_send_short(channel
, DSI_DT_DCS_READ
, dcs_cmd
, 0);
2210 r
= dsi_vc_send_bta_sync(channel
);
2214 /* RX_FIFO_NOT_EMPTY */
2215 if (REG_GET(DSI_VC_CTRL(channel
), 20, 20) == 0) {
2216 DSSERR("RX fifo empty when trying to read.\n");
2220 val
= dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel
));
2222 DSSDBG("\theader: %08x\n", val
);
2223 dt
= FLD_GET(val
, 5, 0);
2224 if (dt
== DSI_DT_RX_ACK_WITH_ERR
) {
2225 u16 err
= FLD_GET(val
, 23, 8);
2226 dsi_show_rx_ack_with_err(err
);
2229 } else if (dt
== DSI_DT_RX_SHORT_READ_1
) {
2230 u8 data
= FLD_GET(val
, 15, 8);
2232 DSSDBG("\tDCS short response, 1 byte: %02x\n", data
);
2240 } else if (dt
== DSI_DT_RX_SHORT_READ_2
) {
2241 u16 data
= FLD_GET(val
, 23, 8);
2243 DSSDBG("\tDCS short response, 2 byte: %04x\n", data
);
2248 buf
[0] = data
& 0xff;
2249 buf
[1] = (data
>> 8) & 0xff;
2252 } else if (dt
== DSI_DT_RX_DCS_LONG_READ
) {
2254 int len
= FLD_GET(val
, 23, 8);
2256 DSSDBG("\tDCS long response, len %d\n", len
);
2261 /* two byte checksum ends the packet, not included in len */
2262 for (w
= 0; w
< len
+ 2;) {
2264 val
= dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel
));
2266 DSSDBG("\t\t%02x %02x %02x %02x\n",
2270 (val
>> 24) & 0xff);
2272 for (b
= 0; b
< 4; ++b
) {
2274 buf
[w
] = (val
>> (b
* 8)) & 0xff;
2275 /* we discard the 2 byte checksum */
2283 DSSERR("\tunknown datatype 0x%02x\n", dt
);
2287 EXPORT_SYMBOL(dsi_vc_dcs_read
);
2289 int dsi_vc_dcs_read_1(int channel
, u8 dcs_cmd
, u8
*data
)
2293 r
= dsi_vc_dcs_read(channel
, dcs_cmd
, data
, 1);
2303 EXPORT_SYMBOL(dsi_vc_dcs_read_1
);
2305 int dsi_vc_set_max_rx_packet_size(int channel
, u16 len
)
2308 r
= dsi_vc_send_short(channel
, DSI_DT_SET_MAX_RET_PKG_SIZE
,
2314 r
= dsi_vc_send_bta_sync(channel
);
2318 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size
);
2320 static void dsi_set_lp_rx_timeout(unsigned long ns
)
2325 unsigned long ticks
;
2327 /* ticks in DSI_FCK */
2329 fck
= dsi_fclk_rate();
2330 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000;
2334 if (ticks
> 0x1fff) {
2335 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / 4;
2340 if (ticks
> 0x1fff) {
2341 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / 16;
2346 if (ticks
> 0x1fff) {
2347 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / (4 * 16);
2352 if (ticks
> 0x1fff) {
2353 DSSWARN("LP_TX_TO over limit, setting it to max\n");
2359 r
= dsi_read_reg(DSI_TIMING2
);
2360 r
= FLD_MOD(r
, 1, 15, 15); /* LP_RX_TO */
2361 r
= FLD_MOD(r
, x16
, 14, 14); /* LP_RX_TO_X16 */
2362 r
= FLD_MOD(r
, x4
, 13, 13); /* LP_RX_TO_X4 */
2363 r
= FLD_MOD(r
, ticks
, 12, 0); /* LP_RX_COUNTER */
2364 dsi_write_reg(DSI_TIMING2
, r
);
2366 DSSDBG("LP_RX_TO %lu ns (%#lx ticks%s%s)\n",
2367 (ticks
* (x16
? 16 : 1) * (x4
? 4 : 1) * 1000) /
2368 (fck
/ 1000 / 1000),
2369 ticks
, x4
? " x4" : "", x16
? " x16" : "");
2372 static void dsi_set_ta_timeout(unsigned long ns
)
2377 unsigned long ticks
;
2379 /* ticks in DSI_FCK */
2380 fck
= dsi_fclk_rate();
2381 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000;
2385 if (ticks
> 0x1fff) {
2386 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / 8;
2391 if (ticks
> 0x1fff) {
2392 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / 16;
2397 if (ticks
> 0x1fff) {
2398 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / (8 * 16);
2403 if (ticks
> 0x1fff) {
2404 DSSWARN("TA_TO over limit, setting it to max\n");
2410 r
= dsi_read_reg(DSI_TIMING1
);
2411 r
= FLD_MOD(r
, 1, 31, 31); /* TA_TO */
2412 r
= FLD_MOD(r
, x16
, 30, 30); /* TA_TO_X16 */
2413 r
= FLD_MOD(r
, x8
, 29, 29); /* TA_TO_X8 */
2414 r
= FLD_MOD(r
, ticks
, 28, 16); /* TA_TO_COUNTER */
2415 dsi_write_reg(DSI_TIMING1
, r
);
2417 DSSDBG("TA_TO %lu ns (%#lx ticks%s%s)\n",
2418 (ticks
* (x16
? 16 : 1) * (x8
? 8 : 1) * 1000) /
2419 (fck
/ 1000 / 1000),
2420 ticks
, x8
? " x8" : "", x16
? " x16" : "");
2423 static void dsi_set_stop_state_counter(unsigned long ns
)
2428 unsigned long ticks
;
2430 /* ticks in DSI_FCK */
2432 fck
= dsi_fclk_rate();
2433 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000;
2437 if (ticks
> 0x1fff) {
2438 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / 4;
2443 if (ticks
> 0x1fff) {
2444 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / 16;
2449 if (ticks
> 0x1fff) {
2450 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / (4 * 16);
2455 if (ticks
> 0x1fff) {
2456 DSSWARN("STOP_STATE_COUNTER_IO over limit, "
2457 "setting it to max\n");
2463 r
= dsi_read_reg(DSI_TIMING1
);
2464 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2465 r
= FLD_MOD(r
, x16
, 14, 14); /* STOP_STATE_X16_IO */
2466 r
= FLD_MOD(r
, x4
, 13, 13); /* STOP_STATE_X4_IO */
2467 r
= FLD_MOD(r
, ticks
, 12, 0); /* STOP_STATE_COUNTER_IO */
2468 dsi_write_reg(DSI_TIMING1
, r
);
2470 DSSDBG("STOP_STATE_COUNTER %lu ns (%#lx ticks%s%s)\n",
2471 (ticks
* (x16
? 16 : 1) * (x4
? 4 : 1) * 1000) /
2472 (fck
/ 1000 / 1000),
2473 ticks
, x4
? " x4" : "", x16
? " x16" : "");
2476 static void dsi_set_hs_tx_timeout(unsigned long ns
)
2481 unsigned long ticks
;
2483 /* ticks in TxByteClkHS */
2485 fck
= dsi_get_txbyteclkhs();
2486 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000;
2490 if (ticks
> 0x1fff) {
2491 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / 4;
2496 if (ticks
> 0x1fff) {
2497 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / 16;
2502 if (ticks
> 0x1fff) {
2503 ticks
= (fck
/ 1000 / 1000) * ns
/ 1000 / (4 * 16);
2508 if (ticks
> 0x1fff) {
2509 DSSWARN("HS_TX_TO over limit, setting it to max\n");
2515 r
= dsi_read_reg(DSI_TIMING2
);
2516 r
= FLD_MOD(r
, 1, 31, 31); /* HS_TX_TO */
2517 r
= FLD_MOD(r
, x16
, 30, 30); /* HS_TX_TO_X16 */
2518 r
= FLD_MOD(r
, x4
, 29, 29); /* HS_TX_TO_X8 (4 really) */
2519 r
= FLD_MOD(r
, ticks
, 28, 16); /* HS_TX_TO_COUNTER */
2520 dsi_write_reg(DSI_TIMING2
, r
);
2522 DSSDBG("HS_TX_TO %lu ns (%#lx ticks%s%s)\n",
2523 (ticks
* (x16
? 16 : 1) * (x4
? 4 : 1) * 1000) /
2524 (fck
/ 1000 / 1000),
2525 ticks
, x4
? " x4" : "", x16
? " x16" : "");
2527 static int dsi_proto_config(struct omap_dss_device
*dssdev
)
2532 dsi_config_tx_fifo(DSI_FIFO_SIZE_128
,
2537 dsi_config_rx_fifo(DSI_FIFO_SIZE_128
,
2542 /* XXX what values for the timeouts? */
2543 dsi_set_stop_state_counter(1000);
2544 dsi_set_ta_timeout(6400000);
2545 dsi_set_lp_rx_timeout(48000);
2546 dsi_set_hs_tx_timeout(1000000);
2548 switch (dssdev
->ctrl
.pixel_size
) {
2562 r
= dsi_read_reg(DSI_CTRL
);
2563 r
= FLD_MOD(r
, 1, 1, 1); /* CS_RX_EN */
2564 r
= FLD_MOD(r
, 1, 2, 2); /* ECC_RX_EN */
2565 r
= FLD_MOD(r
, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2566 r
= FLD_MOD(r
, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2567 r
= FLD_MOD(r
, buswidth
, 7, 6); /* VP_DATA_BUS_WIDTH */
2568 r
= FLD_MOD(r
, 0, 8, 8); /* VP_CLK_POL */
2569 r
= FLD_MOD(r
, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2570 r
= FLD_MOD(r
, 1, 14, 14); /* TRIGGER_RESET_MODE */
2571 r
= FLD_MOD(r
, 1, 19, 19); /* EOT_ENABLE */
2572 r
= FLD_MOD(r
, 1, 24, 24); /* DCS_CMD_ENABLE */
2573 r
= FLD_MOD(r
, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2575 dsi_write_reg(DSI_CTRL
, r
);
2577 dsi_vc_initial_config(0);
2579 /* set all vc targets to peripheral 0 */
2580 dsi
.vc
[0].dest_per
= 0;
2581 dsi
.vc
[1].dest_per
= 0;
2582 dsi
.vc
[2].dest_per
= 0;
2583 dsi
.vc
[3].dest_per
= 0;
2588 static void dsi_proto_timings(struct omap_dss_device
*dssdev
)
2590 unsigned tlpx
, tclk_zero
, tclk_prepare
, tclk_trail
;
2591 unsigned tclk_pre
, tclk_post
;
2592 unsigned ths_prepare
, ths_prepare_ths_zero
, ths_zero
;
2593 unsigned ths_trail
, ths_exit
;
2594 unsigned ddr_clk_pre
, ddr_clk_post
;
2595 unsigned enter_hs_mode_lat
, exit_hs_mode_lat
;
2599 r
= dsi_read_reg(DSI_DSIPHY_CFG0
);
2600 ths_prepare
= FLD_GET(r
, 31, 24);
2601 ths_prepare_ths_zero
= FLD_GET(r
, 23, 16);
2602 ths_zero
= ths_prepare_ths_zero
- ths_prepare
;
2603 ths_trail
= FLD_GET(r
, 15, 8);
2604 ths_exit
= FLD_GET(r
, 7, 0);
2606 r
= dsi_read_reg(DSI_DSIPHY_CFG1
);
2607 tlpx
= FLD_GET(r
, 22, 16) * 2;
2608 tclk_trail
= FLD_GET(r
, 15, 8);
2609 tclk_zero
= FLD_GET(r
, 7, 0);
2611 r
= dsi_read_reg(DSI_DSIPHY_CFG2
);
2612 tclk_prepare
= FLD_GET(r
, 7, 0);
2616 /* min 60ns + 52*UI */
2617 tclk_post
= ns2ddr(60) + 26;
2619 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2620 if (dssdev
->phy
.dsi
.data1_lane
!= 0 &&
2621 dssdev
->phy
.dsi
.data2_lane
!= 0)
2626 ddr_clk_pre
= DIV_ROUND_UP(tclk_pre
+ tlpx
+ tclk_zero
+ tclk_prepare
,
2628 ddr_clk_post
= DIV_ROUND_UP(tclk_post
+ ths_trail
, 4) + ths_eot
;
2630 BUG_ON(ddr_clk_pre
== 0 || ddr_clk_pre
> 255);
2631 BUG_ON(ddr_clk_post
== 0 || ddr_clk_post
> 255);
2633 r
= dsi_read_reg(DSI_CLK_TIMING
);
2634 r
= FLD_MOD(r
, ddr_clk_pre
, 15, 8);
2635 r
= FLD_MOD(r
, ddr_clk_post
, 7, 0);
2636 dsi_write_reg(DSI_CLK_TIMING
, r
);
2638 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2642 enter_hs_mode_lat
= 1 + DIV_ROUND_UP(tlpx
, 4) +
2643 DIV_ROUND_UP(ths_prepare
, 4) +
2644 DIV_ROUND_UP(ths_zero
+ 3, 4);
2646 exit_hs_mode_lat
= DIV_ROUND_UP(ths_trail
+ ths_exit
, 4) + 1 + ths_eot
;
2648 r
= FLD_VAL(enter_hs_mode_lat
, 31, 16) |
2649 FLD_VAL(exit_hs_mode_lat
, 15, 0);
2650 dsi_write_reg(DSI_VM_TIMING7
, r
);
2652 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2653 enter_hs_mode_lat
, exit_hs_mode_lat
);
2657 #define DSI_DECL_VARS \
2658 int __dsi_cb = 0; u32 __dsi_cv = 0;
2660 #define DSI_FLUSH(ch) \
2661 if (__dsi_cb > 0) { \
2662 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2663 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2664 __dsi_cb = __dsi_cv = 0; \
2667 #define DSI_PUSH(ch, data) \
2669 __dsi_cv |= (data) << (__dsi_cb * 8); \
2670 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2671 if (++__dsi_cb > 3) \
2675 static int dsi_update_screen_l4(struct omap_dss_device
*dssdev
,
2676 int x
, int y
, int w
, int h
)
2678 /* Note: supports only 24bit colors in 32bit container */
2680 int fifo_stalls
= 0;
2681 int max_dsi_packet_size
;
2682 int max_data_per_packet
;
2683 int max_pixels_per_packet
;
2685 int bytespp
= dssdev
->ctrl
.pixel_size
/ 8;
2691 struct omap_overlay
*ovl
;
2695 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2698 ovl
= dssdev
->manager
->overlays
[0];
2700 if (ovl
->info
.color_mode
!= OMAP_DSS_COLOR_RGB24U
)
2703 if (dssdev
->ctrl
.pixel_size
!= 24)
2706 scr_width
= ovl
->info
.screen_width
;
2707 data
= ovl
->info
.vaddr
;
2709 start_offset
= scr_width
* y
+ x
;
2710 horiz_inc
= scr_width
- w
;
2713 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2716 /* When using CPU, max long packet size is TX buffer size */
2717 max_dsi_packet_size
= dsi
.vc
[0].fifo_size
* 32 * 4;
2719 /* we seem to get better perf if we divide the tx fifo to half,
2720 and while the other half is being sent, we fill the other half
2721 max_dsi_packet_size /= 2; */
2723 max_data_per_packet
= max_dsi_packet_size
- 4 - 1;
2725 max_pixels_per_packet
= max_data_per_packet
/ bytespp
;
2727 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet
);
2729 pixels_left
= w
* h
;
2731 DSSDBG("total pixels %d\n", pixels_left
);
2733 data
+= start_offset
;
2735 while (pixels_left
> 0) {
2736 /* 0x2c = write_memory_start */
2737 /* 0x3c = write_memory_continue */
2738 u8 dcs_cmd
= first
? 0x2c : 0x3c;
2744 /* using fifo not empty */
2745 /* TX_FIFO_NOT_EMPTY */
2746 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2748 if (fifo_stalls
> 0xfffff) {
2749 DSSERR("fifo stalls overflow, pixels left %d\n",
2757 /* using fifo emptiness */
2758 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS
, 7, 0)+1)*4 <
2759 max_dsi_packet_size
) {
2761 if (fifo_stalls
> 0xfffff) {
2762 DSSERR("fifo stalls overflow, pixels left %d\n",
2769 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS
, 7, 0)+1)*4 == 0) {
2771 if (fifo_stalls
> 0xfffff) {
2772 DSSERR("fifo stalls overflow, pixels left %d\n",
2779 pixels
= min(max_pixels_per_packet
, pixels_left
);
2781 pixels_left
-= pixels
;
2783 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE
,
2784 1 + pixels
* bytespp
, 0);
2786 DSI_PUSH(0, dcs_cmd
);
2788 while (pixels
-- > 0) {
2789 u32 pix
= __raw_readl(data
++);
2791 DSI_PUSH(0, (pix
>> 16) & 0xff);
2792 DSI_PUSH(0, (pix
>> 8) & 0xff);
2793 DSI_PUSH(0, (pix
>> 0) & 0xff);
2796 if (current_x
== x
+w
) {
2808 static void dsi_update_screen_dispc(struct omap_dss_device
*dssdev
,
2809 u16 x
, u16 y
, u16 w
, u16 h
)
2815 unsigned packet_payload
;
2816 unsigned packet_len
;
2818 bool use_te_trigger
;
2819 const unsigned channel
= 0;
2820 /* line buffer is 1024 x 24bits */
2821 /* XXX: for some reason using full buffer size causes considerable TX
2822 * slowdown with update sizes that fill the whole buffer */
2823 const unsigned line_buf_size
= 1023 * 3;
2825 use_te_trigger
= dsi
.te_enabled
&& !dsi
.use_ext_te
;
2827 if (dsi
.update_mode
!= OMAP_DSS_UPDATE_AUTO
)
2828 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2831 bytespp
= dssdev
->ctrl
.pixel_size
/ 8;
2832 bytespl
= w
* bytespp
;
2833 bytespf
= bytespl
* h
;
2835 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2836 * number of lines in a packet. See errata about VP_CLK_RATIO */
2838 if (bytespf
< line_buf_size
)
2839 packet_payload
= bytespf
;
2841 packet_payload
= (line_buf_size
) / bytespl
* bytespl
;
2843 packet_len
= packet_payload
+ 1; /* 1 byte for DCS cmd */
2844 total_len
= (bytespf
/ packet_payload
) * packet_len
;
2846 if (bytespf
% packet_payload
)
2847 total_len
+= (bytespf
% packet_payload
) + 1;
2850 dsi_vc_print_status(1);
2852 l
= FLD_VAL(total_len
, 23, 0); /* TE_SIZE */
2853 dsi_write_reg(DSI_VC_TE(channel
), l
);
2855 dsi_vc_write_long_header(channel
, DSI_DT_DCS_LONG_WRITE
, packet_len
, 0);
2858 l
= FLD_MOD(l
, 1, 30, 30); /* TE_EN */
2860 l
= FLD_MOD(l
, 1, 31, 31); /* TE_START */
2861 dsi_write_reg(DSI_VC_TE(channel
), l
);
2863 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2864 * because DSS interrupts are not capable of waking up the CPU and the
2865 * framedone interrupt could be delayed for quite a long time. I think
2866 * the same goes for any DSS interrupts, but for some reason I have not
2867 * seen the problem anywhere else than here.
2869 dispc_disable_sidle();
2871 dss_start_update(dssdev
);
2873 if (use_te_trigger
) {
2874 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2875 * for TE is longer than the timer allows */
2876 REG_FLD_MOD(DSI_TIMING2
, 0, 15, 15); /* LP_RX_TO */
2878 dsi_vc_send_bta(channel
);
2880 #ifdef DSI_CATCH_MISSING_TE
2881 mod_timer(&dsi
.te_timer
, jiffies
+ msecs_to_jiffies(250));
2886 #ifdef DSI_CATCH_MISSING_TE
2887 static void dsi_te_timeout(unsigned long arg
)
2889 DSSERR("TE not received for 250ms!\n");
2893 static void dsi_framedone_irq_callback(void *data
, u32 mask
)
2895 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2896 * turns itself off. However, DSI still has the pixels in its buffers,
2897 * and is sending the data.
2900 /* SIDLEMODE back to smart-idle */
2901 dispc_enable_sidle();
2903 dsi
.framedone_received
= true;
2904 wake_up(&dsi
.waitqueue
);
2907 static void dsi_set_update_region(struct omap_dss_device
*dssdev
,
2908 u16 x
, u16 y
, u16 w
, u16 h
)
2910 spin_lock(&dsi
.update_lock
);
2911 if (dsi
.update_region
.dirty
) {
2912 dsi
.update_region
.x
= min(x
, dsi
.update_region
.x
);
2913 dsi
.update_region
.y
= min(y
, dsi
.update_region
.y
);
2914 dsi
.update_region
.w
= max(w
, dsi
.update_region
.w
);
2915 dsi
.update_region
.h
= max(h
, dsi
.update_region
.h
);
2917 dsi
.update_region
.x
= x
;
2918 dsi
.update_region
.y
= y
;
2919 dsi
.update_region
.w
= w
;
2920 dsi
.update_region
.h
= h
;
2923 dsi
.update_region
.device
= dssdev
;
2924 dsi
.update_region
.dirty
= true;
2926 spin_unlock(&dsi
.update_lock
);
2930 static int dsi_set_update_mode(struct omap_dss_device
*dssdev
,
2931 enum omap_dss_update_mode mode
)
2936 WARN_ON(!dsi_bus_is_locked());
2938 if (dsi
.update_mode
!= mode
) {
2939 dsi
.update_mode
= mode
;
2941 /* Mark the overlays dirty, and do apply(), so that we get the
2942 * overlays configured properly after update mode change. */
2943 for (i
= 0; i
< omap_dss_get_num_overlays(); ++i
) {
2944 struct omap_overlay
*ovl
;
2945 ovl
= omap_dss_get_overlay(i
);
2946 if (ovl
->manager
== dssdev
->manager
)
2947 ovl
->info_dirty
= true;
2950 r
= dssdev
->manager
->apply(dssdev
->manager
);
2952 if (dssdev
->state
== OMAP_DSS_DISPLAY_ACTIVE
&&
2953 mode
== OMAP_DSS_UPDATE_AUTO
) {
2956 DSSDBG("starting auto update\n");
2958 dssdev
->get_resolution(dssdev
, &w
, &h
);
2960 dsi_set_update_region(dssdev
, 0, 0, w
, h
);
2962 dsi_perf_mark_start_auto();
2964 wake_up(&dsi
.waitqueue
);
2971 static int dsi_set_te(struct omap_dss_device
*dssdev
, bool enable
)
2975 if (dssdev
->driver
->enable_te
) {
2976 r
= dssdev
->driver
->enable_te(dssdev
, enable
);
2977 /* XXX for some reason, DSI TE breaks if we don't wait here.
2978 * Panel bug? Needs more studying */
2985 static void dsi_handle_framedone(void)
2988 const int channel
= 0;
2989 bool use_te_trigger
;
2991 use_te_trigger
= dsi
.te_enabled
&& !dsi
.use_ext_te
;
2993 if (dsi
.update_mode
!= OMAP_DSS_UPDATE_AUTO
)
2994 DSSDBG("FRAMEDONE\n");
2996 if (use_te_trigger
) {
2997 /* enable LP_RX_TO again after the TE */
2998 REG_FLD_MOD(DSI_TIMING2
, 1, 15, 15); /* LP_RX_TO */
3001 /* Send BTA after the frame. We need this for the TE to work, as TE
3002 * trigger is only sent for BTAs without preceding packet. Thus we need
3003 * to BTA after the pixel packets so that next BTA will cause TE
3006 * This is not needed when TE is not in use, but we do it anyway to
3007 * make sure that the transfer has been completed. It would be more
3008 * optimal, but more complex, to wait only just before starting next
3010 r
= dsi_vc_send_bta_sync(channel
);
3012 DSSERR("BTA after framedone failed\n");
3014 /* RX_FIFO_NOT_EMPTY */
3015 if (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) {
3016 DSSERR("Received error during frame transfer:\n");
3017 dsi_vc_flush_receive_data(0);
3020 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3021 dispc_fake_vsync_irq();
3025 static int dsi_update_thread(void *data
)
3027 unsigned long timeout
;
3028 struct omap_dss_device
*device
;
3034 wait_event_interruptible(dsi
.waitqueue
,
3035 dsi
.update_mode
== OMAP_DSS_UPDATE_AUTO
||
3036 (dsi
.update_mode
== OMAP_DSS_UPDATE_MANUAL
&&
3037 dsi
.update_region
.dirty
== true) ||
3038 kthread_should_stop());
3040 if (kthread_should_stop())
3045 if (dsi
.update_mode
== OMAP_DSS_UPDATE_DISABLED
||
3046 kthread_should_stop()) {
3051 dsi_perf_mark_setup();
3053 if (dsi
.update_region
.dirty
) {
3054 spin_lock(&dsi
.update_lock
);
3055 dsi
.active_update_region
= dsi
.update_region
;
3056 dsi
.update_region
.dirty
= false;
3057 spin_unlock(&dsi
.update_lock
);
3060 device
= dsi
.active_update_region
.device
;
3061 x
= dsi
.active_update_region
.x
;
3062 y
= dsi
.active_update_region
.y
;
3063 w
= dsi
.active_update_region
.w
;
3064 h
= dsi
.active_update_region
.h
;
3066 if (device
->manager
->caps
& OMAP_DSS_OVL_MGR_CAP_DISPC
) {
3068 if (dsi
.update_mode
== OMAP_DSS_UPDATE_MANUAL
)
3069 dss_setup_partial_planes(device
,
3072 dispc_set_lcd_size(w
, h
);
3075 if (dsi
.active_update_region
.dirty
) {
3076 dsi
.active_update_region
.dirty
= false;
3077 /* XXX TODO we don't need to send the coords, if they
3078 * are the same that are already programmed to the
3079 * panel. That should speed up manual update a bit */
3080 device
->driver
->setup_update(device
, x
, y
, w
, h
);
3083 dsi_perf_mark_start();
3085 if (device
->manager
->caps
& OMAP_DSS_OVL_MGR_CAP_DISPC
) {
3086 dsi_vc_config_vp(0);
3088 if (dsi
.te_enabled
&& dsi
.use_ext_te
)
3089 device
->driver
->wait_for_te(device
);
3091 dsi
.framedone_received
= false;
3093 dsi_update_screen_dispc(device
, x
, y
, w
, h
);
3095 /* wait for framedone */
3096 timeout
= msecs_to_jiffies(1000);
3097 wait_event_timeout(dsi
.waitqueue
,
3098 dsi
.framedone_received
== true,
3101 if (!dsi
.framedone_received
) {
3102 DSSERR("framedone timeout\n");
3103 DSSERR("failed update %d,%d %dx%d\n",
3106 dispc_enable_sidle();
3107 dispc_enable_lcd_out(0);
3109 dsi_reset_tx_fifo(0);
3111 dsi_handle_framedone();
3112 dsi_perf_show("DISPC");
3115 dsi_update_screen_l4(device
, x
, y
, w
, h
);
3116 dsi_perf_show("L4");
3119 sched
= atomic_read(&dsi
.bus_lock
.count
) < 0;
3121 complete_all(&dsi
.update_completion
);
3125 /* XXX We need to give others chance to get the bus lock. Is
3126 * there a better way for this? */
3127 if (dsi
.update_mode
== OMAP_DSS_UPDATE_AUTO
&& sched
)
3128 schedule_timeout_interruptible(1);
3131 DSSDBG("update thread exiting\n");
3140 static int dsi_display_init_dispc(struct omap_dss_device
*dssdev
)
3144 r
= omap_dispc_register_isr(dsi_framedone_irq_callback
, NULL
,
3145 DISPC_IRQ_FRAMEDONE
);
3147 DSSERR("can't get FRAMEDONE irq\n");
3151 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT
);
3153 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI
);
3154 dispc_enable_fifohandcheck(1);
3156 dispc_set_tft_data_lines(dssdev
->ctrl
.pixel_size
);
3159 struct omap_video_timings timings
= {
3168 dispc_set_lcd_timings(&timings
);
3174 static void dsi_display_uninit_dispc(struct omap_dss_device
*dssdev
)
3176 omap_dispc_unregister_isr(dsi_framedone_irq_callback
, NULL
,
3177 DISPC_IRQ_FRAMEDONE
);
3180 static int dsi_configure_dsi_clocks(struct omap_dss_device
*dssdev
)
3182 struct dsi_clock_info cinfo
;
3185 /* we always use DSS2_FCK as input clock */
3186 cinfo
.use_dss2_fck
= true;
3187 cinfo
.regn
= dssdev
->phy
.dsi
.div
.regn
;
3188 cinfo
.regm
= dssdev
->phy
.dsi
.div
.regm
;
3189 cinfo
.regm3
= dssdev
->phy
.dsi
.div
.regm3
;
3190 cinfo
.regm4
= dssdev
->phy
.dsi
.div
.regm4
;
3191 r
= dsi_calc_clock_rates(&cinfo
);
3195 r
= dsi_pll_set_clock_div(&cinfo
);
3197 DSSERR("Failed to set dsi clocks\n");
3204 static int dsi_configure_dispc_clocks(struct omap_dss_device
*dssdev
)
3206 struct dispc_clock_info dispc_cinfo
;
3208 unsigned long long fck
;
3210 fck
= dsi_get_dsi1_pll_rate();
3212 dispc_cinfo
.lck_div
= dssdev
->phy
.dsi
.div
.lck_div
;
3213 dispc_cinfo
.pck_div
= dssdev
->phy
.dsi
.div
.pck_div
;
3215 r
= dispc_calc_clock_rates(fck
, &dispc_cinfo
);
3217 DSSERR("Failed to calc dispc clocks\n");
3221 r
= dispc_set_clock_div(&dispc_cinfo
);
3223 DSSERR("Failed to set dispc clocks\n");
3230 static int dsi_display_init_dsi(struct omap_dss_device
*dssdev
)
3234 _dsi_print_reset_status();
3236 r
= dsi_pll_init(dssdev
, true, true);
3240 r
= dsi_configure_dsi_clocks(dssdev
);
3244 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK
);
3245 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK
);
3249 r
= dsi_configure_dispc_clocks(dssdev
);
3253 r
= dsi_complexio_init(dssdev
);
3257 _dsi_print_reset_status();
3259 dsi_proto_timings(dssdev
);
3260 dsi_set_lp_clk_divisor(dssdev
);
3263 _dsi_print_reset_status();
3265 r
= dsi_proto_config(dssdev
);
3269 /* enable interface */
3270 dsi_vc_enable(0, 1);
3272 dsi_force_tx_stop_mode_io();
3274 if (dssdev
->driver
->enable
) {
3275 r
= dssdev
->driver
->enable(dssdev
);
3280 /* enable high-speed after initial config */
3281 omapdss_dsi_vc_enable_hs(0, 1);
3287 dsi_complexio_uninit();
3289 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK
);
3290 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK
);
3297 static void dsi_display_uninit_dsi(struct omap_dss_device
*dssdev
)
3299 if (dssdev
->driver
->disable
)
3300 dssdev
->driver
->disable(dssdev
);
3302 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK
);
3303 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK
);
3304 dsi_complexio_uninit();
3308 static int dsi_core_init(void)
3311 REG_FLD_MOD(DSI_SYSCONFIG
, 1, 0, 0);
3314 REG_FLD_MOD(DSI_SYSCONFIG
, 1, 2, 2);
3316 /* SIDLEMODE smart-idle */
3317 REG_FLD_MOD(DSI_SYSCONFIG
, 2, 4, 3);
3319 _dsi_initialize_irq();
3324 static int dsi_display_enable(struct omap_dss_device
*dssdev
)
3328 DSSDBG("dsi_display_enable\n");
3330 mutex_lock(&dsi
.lock
);
3333 r
= omap_dss_start_device(dssdev
);
3335 DSSERR("failed to start device\n");
3339 if (dssdev
->state
!= OMAP_DSS_DISPLAY_DISABLED
) {
3340 DSSERR("dssdev already enabled\n");
3346 dsi_enable_pll_clock(1);
3354 r
= dsi_display_init_dispc(dssdev
);
3358 r
= dsi_display_init_dsi(dssdev
);
3362 dssdev
->state
= OMAP_DSS_DISPLAY_ACTIVE
;
3364 dsi
.use_ext_te
= dssdev
->phy
.dsi
.ext_te
;
3365 r
= dsi_set_te(dssdev
, dsi
.te_enabled
);
3369 dsi_set_update_mode(dssdev
, dsi
.user_update_mode
);
3372 mutex_unlock(&dsi
.lock
);
3378 dsi_display_uninit_dsi(dssdev
);
3380 dsi_display_uninit_dispc(dssdev
);
3383 dsi_enable_pll_clock(0);
3385 omap_dss_stop_device(dssdev
);
3388 mutex_unlock(&dsi
.lock
);
3389 DSSDBG("dsi_display_enable FAILED\n");
3393 static void dsi_display_disable(struct omap_dss_device
*dssdev
)
3395 DSSDBG("dsi_display_disable\n");
3397 mutex_lock(&dsi
.lock
);
3400 if (dssdev
->state
== OMAP_DSS_DISPLAY_DISABLED
||
3401 dssdev
->state
== OMAP_DSS_DISPLAY_SUSPENDED
)
3404 dsi
.update_mode
= OMAP_DSS_UPDATE_DISABLED
;
3405 dssdev
->state
= OMAP_DSS_DISPLAY_DISABLED
;
3407 dsi_display_uninit_dispc(dssdev
);
3409 dsi_display_uninit_dsi(dssdev
);
3412 dsi_enable_pll_clock(0);
3414 omap_dss_stop_device(dssdev
);
3417 mutex_unlock(&dsi
.lock
);
3420 static int dsi_display_suspend(struct omap_dss_device
*dssdev
)
3422 DSSDBG("dsi_display_suspend\n");
3424 mutex_lock(&dsi
.lock
);
3427 if (dssdev
->state
== OMAP_DSS_DISPLAY_DISABLED
||
3428 dssdev
->state
== OMAP_DSS_DISPLAY_SUSPENDED
)
3431 dsi
.update_mode
= OMAP_DSS_UPDATE_DISABLED
;
3432 dssdev
->state
= OMAP_DSS_DISPLAY_SUSPENDED
;
3434 dsi_display_uninit_dispc(dssdev
);
3436 dsi_display_uninit_dsi(dssdev
);
3439 dsi_enable_pll_clock(0);
3442 mutex_unlock(&dsi
.lock
);
3447 static int dsi_display_resume(struct omap_dss_device
*dssdev
)
3451 DSSDBG("dsi_display_resume\n");
3453 mutex_lock(&dsi
.lock
);
3456 if (dssdev
->state
!= OMAP_DSS_DISPLAY_SUSPENDED
) {
3457 DSSERR("dssdev not suspended\n");
3463 dsi_enable_pll_clock(1);
3471 r
= dsi_display_init_dispc(dssdev
);
3475 r
= dsi_display_init_dsi(dssdev
);
3479 dssdev
->state
= OMAP_DSS_DISPLAY_ACTIVE
;
3481 r
= dsi_set_te(dssdev
, dsi
.te_enabled
);
3485 dsi_set_update_mode(dssdev
, dsi
.user_update_mode
);
3488 mutex_unlock(&dsi
.lock
);
3493 dsi_display_uninit_dispc(dssdev
);
3496 dsi_enable_pll_clock(0);
3499 mutex_unlock(&dsi
.lock
);
3500 DSSDBG("dsi_display_resume FAILED\n");
3504 static int dsi_display_update(struct omap_dss_device
*dssdev
,
3505 u16 x
, u16 y
, u16 w
, u16 h
)
3510 DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x
, y
, w
, h
);
3512 mutex_lock(&dsi
.lock
);
3514 if (dsi
.update_mode
!= OMAP_DSS_UPDATE_MANUAL
)
3517 if (dssdev
->state
!= OMAP_DSS_DISPLAY_ACTIVE
)
3520 dssdev
->get_resolution(dssdev
, &dw
, &dh
);
3522 if (x
> dw
|| y
> dh
)
3531 if (w
== 0 || h
== 0)
3539 dsi_set_update_region(dssdev
, x
, y
, w
, h
);
3541 wake_up(&dsi
.waitqueue
);
3544 mutex_unlock(&dsi
.lock
);
3549 static int dsi_display_sync(struct omap_dss_device
*dssdev
)
3553 DSSDBG("dsi_display_sync()\n");
3555 mutex_lock(&dsi
.lock
);
3558 if (dsi
.update_mode
== OMAP_DSS_UPDATE_MANUAL
&&
3559 dsi
.update_region
.dirty
) {
3560 INIT_COMPLETION(dsi
.update_completion
);
3567 mutex_unlock(&dsi
.lock
);
3570 wait_for_completion_interruptible(&dsi
.update_completion
);
3572 DSSDBG("dsi_display_sync() done\n");
3576 static int dsi_display_set_update_mode(struct omap_dss_device
*dssdev
,
3577 enum omap_dss_update_mode mode
)
3581 DSSDBGF("%d", mode
);
3583 mutex_lock(&dsi
.lock
);
3586 dsi
.user_update_mode
= mode
;
3587 r
= dsi_set_update_mode(dssdev
, mode
);
3590 mutex_unlock(&dsi
.lock
);
3595 static enum omap_dss_update_mode
dsi_display_get_update_mode(
3596 struct omap_dss_device
*dssdev
)
3598 return dsi
.update_mode
;
3602 static int dsi_display_enable_te(struct omap_dss_device
*dssdev
, bool enable
)
3606 DSSDBGF("%d", enable
);
3608 if (!dssdev
->driver
->enable_te
)
3613 dsi
.te_enabled
= enable
;
3615 if (dssdev
->state
!= OMAP_DSS_DISPLAY_ACTIVE
)
3618 r
= dsi_set_te(dssdev
, enable
);
3625 static int dsi_display_get_te(struct omap_dss_device
*dssdev
)
3627 return dsi
.te_enabled
;
3630 static int dsi_display_set_rotate(struct omap_dss_device
*dssdev
, u8 rotate
)
3633 DSSDBGF("%d", rotate
);
3635 if (!dssdev
->driver
->set_rotate
|| !dssdev
->driver
->get_rotate
)
3639 dssdev
->driver
->set_rotate(dssdev
, rotate
);
3640 if (dsi
.update_mode
== OMAP_DSS_UPDATE_AUTO
) {
3642 /* the display dimensions may have changed, so set a new
3644 dssdev
->get_resolution(dssdev
, &w
, &h
);
3645 dsi_set_update_region(dssdev
, 0, 0, w
, h
);
3652 static u8
dsi_display_get_rotate(struct omap_dss_device
*dssdev
)
3654 if (!dssdev
->driver
->set_rotate
|| !dssdev
->driver
->get_rotate
)
3657 return dssdev
->driver
->get_rotate(dssdev
);
3660 static int dsi_display_set_mirror(struct omap_dss_device
*dssdev
, bool mirror
)
3662 DSSDBGF("%d", mirror
);
3664 if (!dssdev
->driver
->set_mirror
|| !dssdev
->driver
->get_mirror
)
3668 dssdev
->driver
->set_mirror(dssdev
, mirror
);
3674 static bool dsi_display_get_mirror(struct omap_dss_device
*dssdev
)
3676 if (!dssdev
->driver
->set_mirror
|| !dssdev
->driver
->get_mirror
)
3679 return dssdev
->driver
->get_mirror(dssdev
);
3682 static int dsi_display_run_test(struct omap_dss_device
*dssdev
, int test_num
)
3686 if (dssdev
->state
!= OMAP_DSS_DISPLAY_ACTIVE
)
3689 DSSDBGF("%d", test_num
);
3693 /* run test first in low speed mode */
3694 omapdss_dsi_vc_enable_hs(0, 0);
3696 if (dssdev
->driver
->run_test
) {
3697 r
= dssdev
->driver
->run_test(dssdev
, test_num
);
3702 /* then in high speed */
3703 omapdss_dsi_vc_enable_hs(0, 1);
3705 if (dssdev
->driver
->run_test
) {
3706 r
= dssdev
->driver
->run_test(dssdev
, test_num
);
3712 omapdss_dsi_vc_enable_hs(0, 1);
3719 static int dsi_display_memory_read(struct omap_dss_device
*dssdev
,
3720 void *buf
, size_t size
,
3721 u16 x
, u16 y
, u16 w
, u16 h
)
3727 if (!dssdev
->driver
->memory_read
)
3730 if (dssdev
->state
!= OMAP_DSS_DISPLAY_ACTIVE
)
3735 r
= dssdev
->driver
->memory_read(dssdev
, buf
, size
,
3738 /* Memory read usually changes the update area. This will
3739 * force the next update to re-set the update area */
3740 dsi
.active_update_region
.dirty
= true;
3747 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane
,
3748 u32 fifo_size
, enum omap_burst_size
*burst_size
,
3749 u32
*fifo_low
, u32
*fifo_high
)
3751 unsigned burst_size_bytes
;
3753 *burst_size
= OMAP_DSS_BURST_16x32
;
3754 burst_size_bytes
= 16 * 32 / 8;
3756 *fifo_high
= fifo_size
- burst_size_bytes
;
3757 *fifo_low
= fifo_size
- burst_size_bytes
* 8;
3760 int dsi_init_display(struct omap_dss_device
*dssdev
)
3762 DSSDBG("DSI init\n");
3764 dssdev
->enable
= dsi_display_enable
;
3765 dssdev
->disable
= dsi_display_disable
;
3766 dssdev
->suspend
= dsi_display_suspend
;
3767 dssdev
->resume
= dsi_display_resume
;
3768 dssdev
->update
= dsi_display_update
;
3769 dssdev
->sync
= dsi_display_sync
;
3770 dssdev
->set_update_mode
= dsi_display_set_update_mode
;
3771 dssdev
->get_update_mode
= dsi_display_get_update_mode
;
3772 dssdev
->enable_te
= dsi_display_enable_te
;
3773 dssdev
->get_te
= dsi_display_get_te
;
3775 dssdev
->get_rotate
= dsi_display_get_rotate
;
3776 dssdev
->set_rotate
= dsi_display_set_rotate
;
3778 dssdev
->get_mirror
= dsi_display_get_mirror
;
3779 dssdev
->set_mirror
= dsi_display_set_mirror
;
3781 dssdev
->run_test
= dsi_display_run_test
;
3782 dssdev
->memory_read
= dsi_display_memory_read
;
3784 /* XXX these should be figured out dynamically */
3785 dssdev
->caps
= OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE
|
3786 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM
;
3788 dsi
.vc
[0].dssdev
= dssdev
;
3789 dsi
.vc
[1].dssdev
= dssdev
;
3794 int dsi_init(struct platform_device
*pdev
)
3798 struct sched_param param
= {
3799 .sched_priority
= MAX_USER_RT_PRIO
-1
3802 spin_lock_init(&dsi
.errors_lock
);
3805 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3806 spin_lock_init(&dsi
.irq_stats_lock
);
3807 dsi
.irq_stats
.last_reset
= jiffies
;
3810 init_completion(&dsi
.bta_completion
);
3811 init_completion(&dsi
.update_completion
);
3813 dsi
.thread
= kthread_create(dsi_update_thread
, NULL
, "dsi");
3814 if (IS_ERR(dsi
.thread
)) {
3815 DSSERR("cannot create kthread\n");
3816 r
= PTR_ERR(dsi
.thread
);
3819 sched_setscheduler(dsi
.thread
, SCHED_FIFO
, ¶m
);
3821 init_waitqueue_head(&dsi
.waitqueue
);
3822 spin_lock_init(&dsi
.update_lock
);
3824 mutex_init(&dsi
.lock
);
3825 mutex_init(&dsi
.bus_lock
);
3827 #ifdef DSI_CATCH_MISSING_TE
3828 init_timer(&dsi
.te_timer
);
3829 dsi
.te_timer
.function
= dsi_te_timeout
;
3830 dsi
.te_timer
.data
= 0;
3833 dsi
.update_mode
= OMAP_DSS_UPDATE_DISABLED
;
3834 dsi
.user_update_mode
= OMAP_DSS_UPDATE_DISABLED
;
3836 dsi
.base
= ioremap(DSI_BASE
, DSI_SZ_REGS
);
3838 DSSERR("can't ioremap DSI\n");
3843 dsi
.vdds_dsi_reg
= dss_get_vdds_dsi();
3844 if (IS_ERR(dsi
.vdds_dsi_reg
)) {
3846 DSSERR("can't get VDDS_DSI regulator\n");
3847 r
= PTR_ERR(dsi
.vdds_dsi_reg
);
3853 rev
= dsi_read_reg(DSI_REVISION
);
3854 printk(KERN_INFO
"OMAP DSI rev %d.%d\n",
3855 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
3859 wake_up_process(dsi
.thread
);
3865 kthread_stop(dsi
.thread
);
3872 kthread_stop(dsi
.thread
);
3876 DSSDBG("omap_dsi_exit\n");