2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/ioport.h>
37 #include <linux/cpufreq.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/clk.h>
41 #include <linux/err.h>
42 #include <linux/completion.h>
43 #include <linux/kthread.h>
44 #include <linux/freezer.h>
46 #include <asm/hardware.h>
49 #include <asm/div64.h>
50 #include <asm/arch/pxa-regs.h>
51 #include <asm/arch/pxa2xx-gpio.h>
52 #include <asm/arch/bitfield.h>
53 #include <asm/arch/pxafb.h>
56 * Complain if VAR is out of range.
62 /* Bits which should not be set in machine configuration structures */
63 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
64 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
65 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
67 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
68 LCCR3_PCD | LCCR3_BPP)
70 static void (*pxafb_backlight_power
)(int);
71 static void (*pxafb_lcd_power
)(int, struct fb_var_screeninfo
*);
73 static int pxafb_activate_var(struct fb_var_screeninfo
*var
,
75 static void set_ctrlr_state(struct pxafb_info
*fbi
, u_int state
);
77 static inline unsigned long
78 lcd_readl(struct pxafb_info
*fbi
, unsigned int off
)
80 return __raw_readl(fbi
->mmio_base
+ off
);
84 lcd_writel(struct pxafb_info
*fbi
, unsigned int off
, unsigned long val
)
86 __raw_writel(val
, fbi
->mmio_base
+ off
);
89 static inline void pxafb_schedule_work(struct pxafb_info
*fbi
, u_int state
)
93 local_irq_save(flags
);
95 * We need to handle two requests being made at the same time.
96 * There are two important cases:
97 * 1. When we are changing VT (C_REENABLE) while unblanking
98 * (C_ENABLE) We must perform the unblanking, which will
99 * do our REENABLE for us.
100 * 2. When we are blanking, but immediately unblank before
101 * we have blanked. We do the "REENABLE" thing here as
102 * well, just to be sure.
104 if (fbi
->task_state
== C_ENABLE
&& state
== C_REENABLE
)
106 if (fbi
->task_state
== C_DISABLE
&& state
== C_ENABLE
)
109 if (state
!= (u_int
)-1) {
110 fbi
->task_state
= state
;
111 schedule_work(&fbi
->task
);
113 local_irq_restore(flags
);
116 static inline u_int
chan_to_field(u_int chan
, struct fb_bitfield
*bf
)
119 chan
>>= 16 - bf
->length
;
120 return chan
<< bf
->offset
;
124 pxafb_setpalettereg(u_int regno
, u_int red
, u_int green
, u_int blue
,
125 u_int trans
, struct fb_info
*info
)
127 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
130 if (regno
>= fbi
->palette_size
)
133 if (fbi
->fb
.var
.grayscale
) {
134 fbi
->palette_cpu
[regno
] = ((blue
>> 8) & 0x00ff);
138 switch (fbi
->lccr4
& LCCR4_PAL_FOR_MASK
) {
139 case LCCR4_PAL_FOR_0
:
140 val
= ((red
>> 0) & 0xf800);
141 val
|= ((green
>> 5) & 0x07e0);
142 val
|= ((blue
>> 11) & 0x001f);
143 fbi
->palette_cpu
[regno
] = val
;
145 case LCCR4_PAL_FOR_1
:
146 val
= ((red
<< 8) & 0x00f80000);
147 val
|= ((green
>> 0) & 0x0000fc00);
148 val
|= ((blue
>> 8) & 0x000000f8);
149 ((u32
*)(fbi
->palette_cpu
))[regno
] = val
;
151 case LCCR4_PAL_FOR_2
:
152 val
= ((red
<< 8) & 0x00fc0000);
153 val
|= ((green
>> 0) & 0x0000fc00);
154 val
|= ((blue
>> 8) & 0x000000fc);
155 ((u32
*)(fbi
->palette_cpu
))[regno
] = val
;
163 pxafb_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
164 u_int trans
, struct fb_info
*info
)
166 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
171 * If inverse mode was selected, invert all the colours
172 * rather than the register number. The register number
173 * is what you poke into the framebuffer to produce the
174 * colour you requested.
176 if (fbi
->cmap_inverse
) {
178 green
= 0xffff - green
;
179 blue
= 0xffff - blue
;
183 * If greyscale is true, then we convert the RGB value
184 * to greyscale no matter what visual we are using.
186 if (fbi
->fb
.var
.grayscale
)
187 red
= green
= blue
= (19595 * red
+ 38470 * green
+
190 switch (fbi
->fb
.fix
.visual
) {
191 case FB_VISUAL_TRUECOLOR
:
193 * 16-bit True Colour. We encode the RGB value
194 * according to the RGB bitfield information.
197 u32
*pal
= fbi
->fb
.pseudo_palette
;
199 val
= chan_to_field(red
, &fbi
->fb
.var
.red
);
200 val
|= chan_to_field(green
, &fbi
->fb
.var
.green
);
201 val
|= chan_to_field(blue
, &fbi
->fb
.var
.blue
);
208 case FB_VISUAL_STATIC_PSEUDOCOLOR
:
209 case FB_VISUAL_PSEUDOCOLOR
:
210 ret
= pxafb_setpalettereg(regno
, red
, green
, blue
, trans
, info
);
218 * pxafb_bpp_to_lccr3():
219 * Convert a bits per pixel value to the correct bit pattern for LCCR3
221 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo
*var
)
224 switch (var
->bits_per_pixel
) {
225 case 1: ret
= LCCR3_1BPP
; break;
226 case 2: ret
= LCCR3_2BPP
; break;
227 case 4: ret
= LCCR3_4BPP
; break;
228 case 8: ret
= LCCR3_8BPP
; break;
229 case 16: ret
= LCCR3_16BPP
; break;
231 switch (var
->red
.length
+ var
->green
.length
+
232 var
->blue
.length
+ var
->transp
.length
) {
233 case 18: ret
= LCCR3_18BPP_P
| LCCR3_PDFOR_3
; break;
234 case 19: ret
= LCCR3_19BPP_P
; break;
238 switch (var
->red
.length
+ var
->green
.length
+
239 var
->blue
.length
+ var
->transp
.length
) {
240 case 18: ret
= LCCR3_18BPP
| LCCR3_PDFOR_3
; break;
241 case 19: ret
= LCCR3_19BPP
; break;
242 case 24: ret
= LCCR3_24BPP
| LCCR3_PDFOR_3
; break;
243 case 25: ret
= LCCR3_25BPP
; break;
250 #ifdef CONFIG_CPU_FREQ
252 * pxafb_display_dma_period()
253 * Calculate the minimum period (in picoseconds) between two DMA
254 * requests for the LCD controller. If we hit this, it means we're
255 * doing nothing but LCD DMA.
257 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo
*var
)
260 * Period = pixclock * bits_per_byte * bytes_per_transfer
261 * / memory_bits_per_pixel;
263 return var
->pixclock
* 8 * 16 / var
->bits_per_pixel
;
268 * Select the smallest mode that allows the desired resolution to be
269 * displayed. If desired parameters can be rounded up.
271 static struct pxafb_mode_info
*pxafb_getmode(struct pxafb_mach_info
*mach
,
272 struct fb_var_screeninfo
*var
)
274 struct pxafb_mode_info
*mode
= NULL
;
275 struct pxafb_mode_info
*modelist
= mach
->modes
;
276 unsigned int best_x
= 0xffffffff, best_y
= 0xffffffff;
279 for (i
= 0; i
< mach
->num_modes
; i
++) {
280 if (modelist
[i
].xres
>= var
->xres
&&
281 modelist
[i
].yres
>= var
->yres
&&
282 modelist
[i
].xres
< best_x
&&
283 modelist
[i
].yres
< best_y
&&
284 modelist
[i
].bpp
>= var
->bits_per_pixel
) {
285 best_x
= modelist
[i
].xres
;
286 best_y
= modelist
[i
].yres
;
294 static void pxafb_setmode(struct fb_var_screeninfo
*var
,
295 struct pxafb_mode_info
*mode
)
297 var
->xres
= mode
->xres
;
298 var
->yres
= mode
->yres
;
299 var
->bits_per_pixel
= mode
->bpp
;
300 var
->pixclock
= mode
->pixclock
;
301 var
->hsync_len
= mode
->hsync_len
;
302 var
->left_margin
= mode
->left_margin
;
303 var
->right_margin
= mode
->right_margin
;
304 var
->vsync_len
= mode
->vsync_len
;
305 var
->upper_margin
= mode
->upper_margin
;
306 var
->lower_margin
= mode
->lower_margin
;
307 var
->sync
= mode
->sync
;
308 var
->grayscale
= mode
->cmap_greyscale
;
309 var
->xres_virtual
= var
->xres
;
310 var
->yres_virtual
= var
->yres
;
315 * Get the video params out of 'var'. If a value doesn't fit, round it up,
316 * if it's too big, return -EINVAL.
318 * Round up in the following order: bits_per_pixel, xres,
319 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
320 * bitfields, horizontal timing, vertical timing.
322 static int pxafb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
324 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
325 struct pxafb_mach_info
*inf
= fbi
->dev
->platform_data
;
327 if (var
->xres
< MIN_XRES
)
328 var
->xres
= MIN_XRES
;
329 if (var
->yres
< MIN_YRES
)
330 var
->yres
= MIN_YRES
;
332 if (inf
->fixed_modes
) {
333 struct pxafb_mode_info
*mode
;
335 mode
= pxafb_getmode(inf
, var
);
338 pxafb_setmode(var
, mode
);
340 if (var
->xres
> inf
->modes
->xres
)
342 if (var
->yres
> inf
->modes
->yres
)
344 if (var
->bits_per_pixel
> inf
->modes
->bpp
)
349 max(var
->xres_virtual
, var
->xres
);
351 max(var
->yres_virtual
, var
->yres
);
354 * Setup the RGB parameters for this display.
356 * The pixel packing format is described on page 7-11 of the
357 * PXA2XX Developer's Manual.
359 if (var
->bits_per_pixel
== 16) {
360 var
->red
.offset
= 11; var
->red
.length
= 5;
361 var
->green
.offset
= 5; var
->green
.length
= 6;
362 var
->blue
.offset
= 0; var
->blue
.length
= 5;
363 var
->transp
.offset
= var
->transp
.length
= 0;
364 } else if (var
->bits_per_pixel
> 16) {
365 struct pxafb_mode_info
*mode
;
367 mode
= pxafb_getmode(inf
, var
);
371 switch (mode
->depth
) {
372 case 18: /* RGB666 */
373 var
->transp
.offset
= var
->transp
.length
= 0;
374 var
->red
.offset
= 12; var
->red
.length
= 6;
375 var
->green
.offset
= 6; var
->green
.length
= 6;
376 var
->blue
.offset
= 0; var
->blue
.length
= 6;
378 case 19: /* RGBT666 */
379 var
->transp
.offset
= 18; var
->transp
.length
= 1;
380 var
->red
.offset
= 12; var
->red
.length
= 6;
381 var
->green
.offset
= 6; var
->green
.length
= 6;
382 var
->blue
.offset
= 0; var
->blue
.length
= 6;
384 case 24: /* RGB888 */
385 var
->transp
.offset
= var
->transp
.length
= 0;
386 var
->red
.offset
= 16; var
->red
.length
= 8;
387 var
->green
.offset
= 8; var
->green
.length
= 8;
388 var
->blue
.offset
= 0; var
->blue
.length
= 8;
390 case 25: /* RGBT888 */
391 var
->transp
.offset
= 24; var
->transp
.length
= 1;
392 var
->red
.offset
= 16; var
->red
.length
= 8;
393 var
->green
.offset
= 8; var
->green
.length
= 8;
394 var
->blue
.offset
= 0; var
->blue
.length
= 8;
400 var
->red
.offset
= var
->green
.offset
= 0;
401 var
->blue
.offset
= var
->transp
.offset
= 0;
403 var
->green
.length
= 8;
404 var
->blue
.length
= 8;
405 var
->transp
.length
= 0;
408 #ifdef CONFIG_CPU_FREQ
409 pr_debug("pxafb: dma period = %d ps\n",
410 pxafb_display_dma_period(var
));
416 static inline void pxafb_set_truecolor(u_int is_true_color
)
418 /* do your machine-specific setup if needed */
423 * Set the user defined part of the display for the specified console
425 static int pxafb_set_par(struct fb_info
*info
)
427 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
428 struct fb_var_screeninfo
*var
= &info
->var
;
430 if (var
->bits_per_pixel
>= 16)
431 fbi
->fb
.fix
.visual
= FB_VISUAL_TRUECOLOR
;
432 else if (!fbi
->cmap_static
)
433 fbi
->fb
.fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
436 * Some people have weird ideas about wanting static
437 * pseudocolor maps. I suspect their user space
438 * applications are broken.
440 fbi
->fb
.fix
.visual
= FB_VISUAL_STATIC_PSEUDOCOLOR
;
443 fbi
->fb
.fix
.line_length
= var
->xres_virtual
*
444 var
->bits_per_pixel
/ 8;
445 if (var
->bits_per_pixel
>= 16)
446 fbi
->palette_size
= 0;
448 fbi
->palette_size
= var
->bits_per_pixel
== 1 ?
449 4 : 1 << var
->bits_per_pixel
;
451 fbi
->palette_cpu
= (u16
*)&fbi
->dma_buff
->palette
[0];
454 * Set (any) board control register to handle new color depth
456 pxafb_set_truecolor(fbi
->fb
.fix
.visual
== FB_VISUAL_TRUECOLOR
);
458 if (fbi
->fb
.var
.bits_per_pixel
>= 16)
459 fb_dealloc_cmap(&fbi
->fb
.cmap
);
461 fb_alloc_cmap(&fbi
->fb
.cmap
, 1<<fbi
->fb
.var
.bits_per_pixel
, 0);
463 pxafb_activate_var(var
, fbi
);
470 * Blank the display by setting all palette values to zero. Note, the
471 * 16 bpp mode does not really use the palette, so this will not
472 * blank the display in all modes.
474 static int pxafb_blank(int blank
, struct fb_info
*info
)
476 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
480 case FB_BLANK_POWERDOWN
:
481 case FB_BLANK_VSYNC_SUSPEND
:
482 case FB_BLANK_HSYNC_SUSPEND
:
483 case FB_BLANK_NORMAL
:
484 if (fbi
->fb
.fix
.visual
== FB_VISUAL_PSEUDOCOLOR
||
485 fbi
->fb
.fix
.visual
== FB_VISUAL_STATIC_PSEUDOCOLOR
)
486 for (i
= 0; i
< fbi
->palette_size
; i
++)
487 pxafb_setpalettereg(i
, 0, 0, 0, 0, info
);
489 pxafb_schedule_work(fbi
, C_DISABLE
);
490 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
493 case FB_BLANK_UNBLANK
:
494 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
495 if (fbi
->fb
.fix
.visual
== FB_VISUAL_PSEUDOCOLOR
||
496 fbi
->fb
.fix
.visual
== FB_VISUAL_STATIC_PSEUDOCOLOR
)
497 fb_set_cmap(&fbi
->fb
.cmap
, info
);
498 pxafb_schedule_work(fbi
, C_ENABLE
);
503 static int pxafb_mmap(struct fb_info
*info
,
504 struct vm_area_struct
*vma
)
506 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
507 unsigned long off
= vma
->vm_pgoff
<< PAGE_SHIFT
;
509 if (off
< info
->fix
.smem_len
) {
510 vma
->vm_pgoff
+= fbi
->video_offset
/ PAGE_SIZE
;
511 return dma_mmap_writecombine(fbi
->dev
, vma
, fbi
->map_cpu
,
512 fbi
->map_dma
, fbi
->map_size
);
517 static struct fb_ops pxafb_ops
= {
518 .owner
= THIS_MODULE
,
519 .fb_check_var
= pxafb_check_var
,
520 .fb_set_par
= pxafb_set_par
,
521 .fb_setcolreg
= pxafb_setcolreg
,
522 .fb_fillrect
= cfb_fillrect
,
523 .fb_copyarea
= cfb_copyarea
,
524 .fb_imageblit
= cfb_imageblit
,
525 .fb_blank
= pxafb_blank
,
526 .fb_mmap
= pxafb_mmap
,
530 * Calculate the PCD value from the clock rate (in picoseconds).
531 * We take account of the PPCR clock setting.
532 * From PXA Developer's Manual:
543 * LCLK = LCD/Memory Clock
546 * PixelClock here is in Hz while the pixclock argument given is the
547 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
549 * The function get_lclk_frequency_10khz returns LCLK in units of
550 * 10khz. Calling the result of this function lclk gives us the
553 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
554 * -------------------------------------- - 1
557 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
559 static inline unsigned int get_pcd(struct pxafb_info
*fbi
,
560 unsigned int pixclock
)
562 unsigned long long pcd
;
564 /* FIXME: Need to take into account Double Pixel Clock mode
565 * (DPC) bit? or perhaps set it based on the various clock
567 pcd
= (unsigned long long)(clk_get_rate(fbi
->clk
) / 10000);
569 do_div(pcd
, 100000000 * 2);
570 /* no need for this, since we should subtract 1 anyway. they cancel */
571 /* pcd += 1; */ /* make up for integer math truncations */
572 return (unsigned int)pcd
;
576 * Some touchscreens need hsync information from the video driver to
577 * function correctly. We export it here. Note that 'hsync_time' and
578 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
579 * of the hsync period in seconds.
581 static inline void set_hsync_time(struct pxafb_info
*fbi
, unsigned int pcd
)
585 if ((pcd
== 0) || (fbi
->fb
.var
.hsync_len
== 0)) {
590 htime
= clk_get_rate(fbi
->clk
) / (pcd
* fbi
->fb
.var
.hsync_len
);
592 fbi
->hsync_time
= htime
;
595 unsigned long pxafb_get_hsync_time(struct device
*dev
)
597 struct pxafb_info
*fbi
= dev_get_drvdata(dev
);
599 /* If display is blanked/suspended, hsync isn't active */
600 if (!fbi
|| (fbi
->state
!= C_ENABLE
))
603 return fbi
->hsync_time
;
605 EXPORT_SYMBOL(pxafb_get_hsync_time
);
607 static int setup_frame_dma(struct pxafb_info
*fbi
, int dma
, int pal
,
608 unsigned int offset
, size_t size
)
610 struct pxafb_dma_descriptor
*dma_desc
, *pal_desc
;
611 unsigned int dma_desc_off
, pal_desc_off
;
613 if (dma
< 0 || dma
>= DMA_MAX
)
616 dma_desc
= &fbi
->dma_buff
->dma_desc
[dma
];
617 dma_desc_off
= offsetof(struct pxafb_dma_buff
, dma_desc
[dma
]);
619 dma_desc
->fsadr
= fbi
->screen_dma
+ offset
;
621 dma_desc
->ldcmd
= size
;
623 if (pal
< 0 || pal
>= PAL_MAX
) {
624 dma_desc
->fdadr
= fbi
->dma_buff_phys
+ dma_desc_off
;
625 fbi
->fdadr
[dma
] = fbi
->dma_buff_phys
+ dma_desc_off
;
627 pal_desc
= &fbi
->dma_buff
->pal_desc
[pal
];
628 pal_desc_off
= offsetof(struct pxafb_dma_buff
, pal_desc
[pal
]);
630 pal_desc
->fsadr
= fbi
->dma_buff_phys
+ pal
* PALETTE_SIZE
;
633 if ((fbi
->lccr4
& LCCR4_PAL_FOR_MASK
) == LCCR4_PAL_FOR_0
)
634 pal_desc
->ldcmd
= fbi
->palette_size
* sizeof(u16
);
636 pal_desc
->ldcmd
= fbi
->palette_size
* sizeof(u32
);
638 pal_desc
->ldcmd
|= LDCMD_PAL
;
640 /* flip back and forth between palette and frame buffer */
641 pal_desc
->fdadr
= fbi
->dma_buff_phys
+ dma_desc_off
;
642 dma_desc
->fdadr
= fbi
->dma_buff_phys
+ pal_desc_off
;
643 fbi
->fdadr
[dma
] = fbi
->dma_buff_phys
+ dma_desc_off
;
649 #ifdef CONFIG_FB_PXA_SMARTPANEL
650 static int setup_smart_dma(struct pxafb_info
*fbi
)
652 struct pxafb_dma_descriptor
*dma_desc
;
653 unsigned long dma_desc_off
, cmd_buff_off
;
655 dma_desc
= &fbi
->dma_buff
->dma_desc
[DMA_CMD
];
656 dma_desc_off
= offsetof(struct pxafb_dma_buff
, dma_desc
[DMA_CMD
]);
657 cmd_buff_off
= offsetof(struct pxafb_dma_buff
, cmd_buff
);
659 dma_desc
->fdadr
= fbi
->dma_buff_phys
+ dma_desc_off
;
660 dma_desc
->fsadr
= fbi
->dma_buff_phys
+ cmd_buff_off
;
662 dma_desc
->ldcmd
= fbi
->n_smart_cmds
* sizeof(uint16_t);
664 fbi
->fdadr
[DMA_CMD
] = dma_desc
->fdadr
;
668 int pxafb_smart_flush(struct fb_info
*info
)
670 struct pxafb_info
*fbi
= container_of(info
, struct pxafb_info
, fb
);
674 /* disable controller until all registers are set up */
675 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
& ~LCCR0_ENB
);
677 /* 1. make it an even number of commands to align on 32-bit boundary
678 * 2. add the interrupt command to the end of the chain so we can
679 * keep track of the end of the transfer
682 while (fbi
->n_smart_cmds
& 1)
683 fbi
->smart_cmds
[fbi
->n_smart_cmds
++] = SMART_CMD_NOOP
;
685 fbi
->smart_cmds
[fbi
->n_smart_cmds
++] = SMART_CMD_INTERRUPT
;
686 fbi
->smart_cmds
[fbi
->n_smart_cmds
++] = SMART_CMD_WAIT_FOR_VSYNC
;
687 setup_smart_dma(fbi
);
689 /* continue to execute next command */
690 prsr
= lcd_readl(fbi
, PRSR
) | PRSR_ST_OK
| PRSR_CON_NT
;
691 lcd_writel(fbi
, PRSR
, prsr
);
693 /* stop the processor in case it executed "wait for sync" cmd */
694 lcd_writel(fbi
, CMDCR
, 0x0001);
696 /* don't send interrupts for fifo underruns on channel 6 */
697 lcd_writel(fbi
, LCCR5
, LCCR5_IUM(6));
699 lcd_writel(fbi
, LCCR1
, fbi
->reg_lccr1
);
700 lcd_writel(fbi
, LCCR2
, fbi
->reg_lccr2
);
701 lcd_writel(fbi
, LCCR3
, fbi
->reg_lccr3
);
702 lcd_writel(fbi
, FDADR0
, fbi
->fdadr
[0]);
703 lcd_writel(fbi
, FDADR6
, fbi
->fdadr
[6]);
706 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
| LCCR0_ENB
);
708 if (wait_for_completion_timeout(&fbi
->command_done
, HZ
/2) == 0) {
709 pr_warning("%s: timeout waiting for command done\n",
715 prsr
= lcd_readl(fbi
, PRSR
) & ~(PRSR_ST_OK
| PRSR_CON_NT
);
716 lcd_writel(fbi
, PRSR
, prsr
);
717 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
& ~LCCR0_ENB
);
718 lcd_writel(fbi
, FDADR6
, 0);
719 fbi
->n_smart_cmds
= 0;
723 int pxafb_smart_queue(struct fb_info
*info
, uint16_t *cmds
, int n_cmds
)
726 struct pxafb_info
*fbi
= container_of(info
, struct pxafb_info
, fb
);
728 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
729 for (i
= 0; i
< n_cmds
; i
++) {
730 if (fbi
->n_smart_cmds
== CMD_BUFF_SIZE
- 8)
731 pxafb_smart_flush(info
);
733 fbi
->smart_cmds
[fbi
->n_smart_cmds
++] = *cmds
++;
739 static unsigned int __smart_timing(unsigned time_ns
, unsigned long lcd_clk
)
741 unsigned int t
= (time_ns
* (lcd_clk
/ 1000000) / 1000);
742 return (t
== 0) ? 1 : t
;
745 static void setup_smart_timing(struct pxafb_info
*fbi
,
746 struct fb_var_screeninfo
*var
)
748 struct pxafb_mach_info
*inf
= fbi
->dev
->platform_data
;
749 struct pxafb_mode_info
*mode
= &inf
->modes
[0];
750 unsigned long lclk
= clk_get_rate(fbi
->clk
);
751 unsigned t1
, t2
, t3
, t4
;
753 t1
= max(mode
->a0csrd_set_hld
, mode
->a0cswr_set_hld
);
754 t2
= max(mode
->rd_pulse_width
, mode
->wr_pulse_width
);
755 t3
= mode
->op_hold_time
;
756 t4
= mode
->cmd_inh_time
;
759 LCCR1_DisWdth(var
->xres
) |
760 LCCR1_BegLnDel(__smart_timing(t1
, lclk
)) |
761 LCCR1_EndLnDel(__smart_timing(t2
, lclk
)) |
762 LCCR1_HorSnchWdth(__smart_timing(t3
, lclk
));
764 fbi
->reg_lccr2
= LCCR2_DisHght(var
->yres
);
765 fbi
->reg_lccr3
= LCCR3_PixClkDiv(__smart_timing(t4
, lclk
));
767 /* FIXME: make this configurable */
771 static int pxafb_smart_thread(void *arg
)
773 struct pxafb_info
*fbi
= arg
;
774 struct pxafb_mach_info
*inf
= fbi
->dev
->platform_data
;
776 if (!fbi
|| !inf
->smart_update
) {
777 pr_err("%s: not properly initialized, thread terminated\n",
782 pr_debug("%s(): task starting\n", __func__
);
785 while (!kthread_should_stop()) {
790 if (fbi
->state
== C_ENABLE
) {
791 inf
->smart_update(&fbi
->fb
);
792 complete(&fbi
->refresh_done
);
795 set_current_state(TASK_INTERRUPTIBLE
);
796 schedule_timeout(30 * HZ
/ 1000);
799 pr_debug("%s(): task ending\n", __func__
);
803 static int pxafb_smart_init(struct pxafb_info
*fbi
)
805 fbi
->smart_thread
= kthread_run(pxafb_smart_thread
, fbi
,
807 if (IS_ERR(fbi
->smart_thread
)) {
808 printk(KERN_ERR
"%s: unable to create kernel thread\n",
810 return PTR_ERR(fbi
->smart_thread
);
815 int pxafb_smart_queue(struct fb_info
*info
, uint16_t *cmds
, int n_cmds
)
820 int pxafb_smart_flush(struct fb_info
*info
)
824 #endif /* CONFIG_FB_SMART_PANEL */
826 static void setup_parallel_timing(struct pxafb_info
*fbi
,
827 struct fb_var_screeninfo
*var
)
829 unsigned int lines_per_panel
, pcd
= get_pcd(fbi
, var
->pixclock
);
832 LCCR1_DisWdth(var
->xres
) +
833 LCCR1_HorSnchWdth(var
->hsync_len
) +
834 LCCR1_BegLnDel(var
->left_margin
) +
835 LCCR1_EndLnDel(var
->right_margin
);
838 * If we have a dual scan LCD, we need to halve
839 * the YRES parameter.
841 lines_per_panel
= var
->yres
;
842 if ((fbi
->lccr0
& LCCR0_SDS
) == LCCR0_Dual
)
843 lines_per_panel
/= 2;
846 LCCR2_DisHght(lines_per_panel
) +
847 LCCR2_VrtSnchWdth(var
->vsync_len
) +
848 LCCR2_BegFrmDel(var
->upper_margin
) +
849 LCCR2_EndFrmDel(var
->lower_margin
);
851 fbi
->reg_lccr3
= fbi
->lccr3
|
852 (var
->sync
& FB_SYNC_HOR_HIGH_ACT
?
853 LCCR3_HorSnchH
: LCCR3_HorSnchL
) |
854 (var
->sync
& FB_SYNC_VERT_HIGH_ACT
?
855 LCCR3_VrtSnchH
: LCCR3_VrtSnchL
);
858 fbi
->reg_lccr3
|= LCCR3_PixClkDiv(pcd
);
859 set_hsync_time(fbi
, pcd
);
864 * pxafb_activate_var():
865 * Configures LCD Controller based on entries in var parameter.
866 * Settings are only written to the controller if changes were made.
868 static int pxafb_activate_var(struct fb_var_screeninfo
*var
,
869 struct pxafb_info
*fbi
)
875 if (!(fbi
->lccr0
& LCCR0_LCDT
)) {
876 if (var
->xres
< 16 || var
->xres
> 1024)
877 printk(KERN_ERR
"%s: invalid xres %d\n",
878 fbi
->fb
.fix
.id
, var
->xres
);
879 switch (var
->bits_per_pixel
) {
889 printk(KERN_ERR
"%s: invalid bit depth %d\n",
890 fbi
->fb
.fix
.id
, var
->bits_per_pixel
);
894 if (var
->hsync_len
< 1 || var
->hsync_len
> 64)
895 printk(KERN_ERR
"%s: invalid hsync_len %d\n",
896 fbi
->fb
.fix
.id
, var
->hsync_len
);
897 if (var
->left_margin
< 1 || var
->left_margin
> 255)
898 printk(KERN_ERR
"%s: invalid left_margin %d\n",
899 fbi
->fb
.fix
.id
, var
->left_margin
);
900 if (var
->right_margin
< 1 || var
->right_margin
> 255)
901 printk(KERN_ERR
"%s: invalid right_margin %d\n",
902 fbi
->fb
.fix
.id
, var
->right_margin
);
903 if (var
->yres
< 1 || var
->yres
> 1024)
904 printk(KERN_ERR
"%s: invalid yres %d\n",
905 fbi
->fb
.fix
.id
, var
->yres
);
906 if (var
->vsync_len
< 1 || var
->vsync_len
> 64)
907 printk(KERN_ERR
"%s: invalid vsync_len %d\n",
908 fbi
->fb
.fix
.id
, var
->vsync_len
);
909 if (var
->upper_margin
< 0 || var
->upper_margin
> 255)
910 printk(KERN_ERR
"%s: invalid upper_margin %d\n",
911 fbi
->fb
.fix
.id
, var
->upper_margin
);
912 if (var
->lower_margin
< 0 || var
->lower_margin
> 255)
913 printk(KERN_ERR
"%s: invalid lower_margin %d\n",
914 fbi
->fb
.fix
.id
, var
->lower_margin
);
917 /* Update shadow copy atomically */
918 local_irq_save(flags
);
920 #ifdef CONFIG_FB_PXA_SMARTPANEL
921 if (fbi
->lccr0
& LCCR0_LCDT
)
922 setup_smart_timing(fbi
, var
);
925 setup_parallel_timing(fbi
, var
);
927 fbi
->reg_lccr0
= fbi
->lccr0
|
928 (LCCR0_LDM
| LCCR0_SFM
| LCCR0_IUM
| LCCR0_EFM
|
929 LCCR0_QDM
| LCCR0_BM
| LCCR0_OUM
);
931 fbi
->reg_lccr3
|= pxafb_bpp_to_lccr3(var
);
933 nbytes
= var
->yres
* fbi
->fb
.fix
.line_length
;
935 if ((fbi
->lccr0
& LCCR0_SDS
) == LCCR0_Dual
) {
937 setup_frame_dma(fbi
, DMA_LOWER
, PAL_NONE
, nbytes
, nbytes
);
940 if ((var
->bits_per_pixel
>= 16) || (fbi
->lccr0
& LCCR0_LCDT
))
941 setup_frame_dma(fbi
, DMA_BASE
, PAL_NONE
, 0, nbytes
);
943 setup_frame_dma(fbi
, DMA_BASE
, PAL_BASE
, 0, nbytes
);
945 fbi
->reg_lccr4
= lcd_readl(fbi
, LCCR4
) & ~LCCR4_PAL_FOR_MASK
;
946 fbi
->reg_lccr4
|= (fbi
->lccr4
& LCCR4_PAL_FOR_MASK
);
947 local_irq_restore(flags
);
950 * Only update the registers if the controller is enabled
951 * and something has changed.
953 if ((lcd_readl(fbi
, LCCR0
) != fbi
->reg_lccr0
) ||
954 (lcd_readl(fbi
, LCCR1
) != fbi
->reg_lccr1
) ||
955 (lcd_readl(fbi
, LCCR2
) != fbi
->reg_lccr2
) ||
956 (lcd_readl(fbi
, LCCR3
) != fbi
->reg_lccr3
) ||
957 (lcd_readl(fbi
, FDADR0
) != fbi
->fdadr
[0]) ||
958 (lcd_readl(fbi
, FDADR1
) != fbi
->fdadr
[1]))
959 pxafb_schedule_work(fbi
, C_REENABLE
);
965 * NOTE! The following functions are purely helpers for set_ctrlr_state.
966 * Do not call them directly; set_ctrlr_state does the correct serialisation
967 * to ensure that things happen in the right way 100% of time time.
970 static inline void __pxafb_backlight_power(struct pxafb_info
*fbi
, int on
)
972 pr_debug("pxafb: backlight o%s\n", on
? "n" : "ff");
974 if (pxafb_backlight_power
)
975 pxafb_backlight_power(on
);
978 static inline void __pxafb_lcd_power(struct pxafb_info
*fbi
, int on
)
980 pr_debug("pxafb: LCD power o%s\n", on
? "n" : "ff");
983 pxafb_lcd_power(on
, &fbi
->fb
.var
);
986 static void pxafb_setup_gpio(struct pxafb_info
*fbi
)
989 unsigned int lccr0
= fbi
->lccr0
;
992 * setup is based on type of panel supported
995 /* 4 bit interface */
996 if ((lccr0
& LCCR0_CMS
) == LCCR0_Mono
&&
997 (lccr0
& LCCR0_SDS
) == LCCR0_Sngl
&&
998 (lccr0
& LCCR0_DPD
) == LCCR0_4PixMono
)
1001 /* 8 bit interface */
1002 else if (((lccr0
& LCCR0_CMS
) == LCCR0_Mono
&&
1003 ((lccr0
& LCCR0_SDS
) == LCCR0_Dual
||
1004 (lccr0
& LCCR0_DPD
) == LCCR0_8PixMono
)) ||
1005 ((lccr0
& LCCR0_CMS
) == LCCR0_Color
&&
1006 (lccr0
& LCCR0_PAS
) == LCCR0_Pas
&&
1007 (lccr0
& LCCR0_SDS
) == LCCR0_Sngl
))
1010 /* 16 bit interface */
1011 else if ((lccr0
& LCCR0_CMS
) == LCCR0_Color
&&
1012 ((lccr0
& LCCR0_SDS
) == LCCR0_Dual
||
1013 (lccr0
& LCCR0_PAS
) == LCCR0_Act
))
1017 printk(KERN_ERR
"pxafb_setup_gpio: unable to determine "
1018 "bits per pixel\n");
1022 for (gpio
= 58; ldd_bits
; gpio
++, ldd_bits
--)
1023 pxa_gpio_mode(gpio
| GPIO_ALT_FN_2_OUT
);
1024 /* 18 bit interface */
1025 if (fbi
->fb
.var
.bits_per_pixel
> 16) {
1026 pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT
);
1027 pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT
);
1029 pxa_gpio_mode(GPIO74_LCD_FCLK_MD
);
1030 pxa_gpio_mode(GPIO75_LCD_LCLK_MD
);
1031 pxa_gpio_mode(GPIO76_LCD_PCLK_MD
);
1032 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD
);
1035 static void pxafb_enable_controller(struct pxafb_info
*fbi
)
1037 pr_debug("pxafb: Enabling LCD controller\n");
1038 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi
->fdadr
[0]);
1039 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi
->fdadr
[1]);
1040 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi
->reg_lccr0
);
1041 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi
->reg_lccr1
);
1042 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi
->reg_lccr2
);
1043 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi
->reg_lccr3
);
1045 /* enable LCD controller clock */
1046 clk_enable(fbi
->clk
);
1048 if (fbi
->lccr0
& LCCR0_LCDT
)
1051 /* Sequence from 11.7.10 */
1052 lcd_writel(fbi
, LCCR3
, fbi
->reg_lccr3
);
1053 lcd_writel(fbi
, LCCR2
, fbi
->reg_lccr2
);
1054 lcd_writel(fbi
, LCCR1
, fbi
->reg_lccr1
);
1055 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
& ~LCCR0_ENB
);
1057 lcd_writel(fbi
, FDADR0
, fbi
->fdadr
[0]);
1058 lcd_writel(fbi
, FDADR1
, fbi
->fdadr
[1]);
1059 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
| LCCR0_ENB
);
1062 static void pxafb_disable_controller(struct pxafb_info
*fbi
)
1066 #ifdef CONFIG_FB_PXA_SMARTPANEL
1067 if (fbi
->lccr0
& LCCR0_LCDT
) {
1068 wait_for_completion_timeout(&fbi
->refresh_done
,
1074 /* Clear LCD Status Register */
1075 lcd_writel(fbi
, LCSR
, 0xffffffff);
1077 lccr0
= lcd_readl(fbi
, LCCR0
) & ~LCCR0_LDM
;
1078 lcd_writel(fbi
, LCCR0
, lccr0
);
1079 lcd_writel(fbi
, LCCR0
, lccr0
| LCCR0_DIS
);
1081 wait_for_completion_timeout(&fbi
->disable_done
, 200 * HZ
/ 1000);
1083 /* disable LCD controller clock */
1084 clk_disable(fbi
->clk
);
1088 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1090 static irqreturn_t
pxafb_handle_irq(int irq
, void *dev_id
)
1092 struct pxafb_info
*fbi
= dev_id
;
1093 unsigned int lccr0
, lcsr
= lcd_readl(fbi
, LCSR
);
1095 if (lcsr
& LCSR_LDD
) {
1096 lccr0
= lcd_readl(fbi
, LCCR0
);
1097 lcd_writel(fbi
, LCCR0
, lccr0
| LCCR0_LDM
);
1098 complete(&fbi
->disable_done
);
1101 #ifdef CONFIG_FB_PXA_SMARTPANEL
1102 if (lcsr
& LCSR_CMD_INT
)
1103 complete(&fbi
->command_done
);
1106 lcd_writel(fbi
, LCSR
, lcsr
);
1111 * This function must be called from task context only, since it will
1112 * sleep when disabling the LCD controller, or if we get two contending
1113 * processes trying to alter state.
1115 static void set_ctrlr_state(struct pxafb_info
*fbi
, u_int state
)
1119 down(&fbi
->ctrlr_sem
);
1121 old_state
= fbi
->state
;
1124 * Hack around fbcon initialisation.
1126 if (old_state
== C_STARTUP
&& state
== C_REENABLE
)
1130 case C_DISABLE_CLKCHANGE
:
1132 * Disable controller for clock change. If the
1133 * controller is already disabled, then do nothing.
1135 if (old_state
!= C_DISABLE
&& old_state
!= C_DISABLE_PM
) {
1137 /* TODO __pxafb_lcd_power(fbi, 0); */
1138 pxafb_disable_controller(fbi
);
1145 * Disable controller
1147 if (old_state
!= C_DISABLE
) {
1149 __pxafb_backlight_power(fbi
, 0);
1150 __pxafb_lcd_power(fbi
, 0);
1151 if (old_state
!= C_DISABLE_CLKCHANGE
)
1152 pxafb_disable_controller(fbi
);
1156 case C_ENABLE_CLKCHANGE
:
1158 * Enable the controller after clock change. Only
1159 * do this if we were disabled for the clock change.
1161 if (old_state
== C_DISABLE_CLKCHANGE
) {
1162 fbi
->state
= C_ENABLE
;
1163 pxafb_enable_controller(fbi
);
1164 /* TODO __pxafb_lcd_power(fbi, 1); */
1170 * Re-enable the controller only if it was already
1171 * enabled. This is so we reprogram the control
1174 if (old_state
== C_ENABLE
) {
1175 __pxafb_lcd_power(fbi
, 0);
1176 pxafb_disable_controller(fbi
);
1177 pxafb_setup_gpio(fbi
);
1178 pxafb_enable_controller(fbi
);
1179 __pxafb_lcd_power(fbi
, 1);
1185 * Re-enable the controller after PM. This is not
1186 * perfect - think about the case where we were doing
1187 * a clock change, and we suspended half-way through.
1189 if (old_state
!= C_DISABLE_PM
)
1195 * Power up the LCD screen, enable controller, and
1196 * turn on the backlight.
1198 if (old_state
!= C_ENABLE
) {
1199 fbi
->state
= C_ENABLE
;
1200 pxafb_setup_gpio(fbi
);
1201 pxafb_enable_controller(fbi
);
1202 __pxafb_lcd_power(fbi
, 1);
1203 __pxafb_backlight_power(fbi
, 1);
1207 up(&fbi
->ctrlr_sem
);
1211 * Our LCD controller task (which is called when we blank or unblank)
1214 static void pxafb_task(struct work_struct
*work
)
1216 struct pxafb_info
*fbi
=
1217 container_of(work
, struct pxafb_info
, task
);
1218 u_int state
= xchg(&fbi
->task_state
, -1);
1220 set_ctrlr_state(fbi
, state
);
1223 #ifdef CONFIG_CPU_FREQ
1225 * CPU clock speed change handler. We need to adjust the LCD timing
1226 * parameters when the CPU clock is adjusted by the power management
1229 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1232 pxafb_freq_transition(struct notifier_block
*nb
, unsigned long val
, void *data
)
1234 struct pxafb_info
*fbi
= TO_INF(nb
, freq_transition
);
1235 /* TODO struct cpufreq_freqs *f = data; */
1239 case CPUFREQ_PRECHANGE
:
1240 set_ctrlr_state(fbi
, C_DISABLE_CLKCHANGE
);
1243 case CPUFREQ_POSTCHANGE
:
1244 pcd
= get_pcd(fbi
, fbi
->fb
.var
.pixclock
);
1245 set_hsync_time(fbi
, pcd
);
1246 fbi
->reg_lccr3
= (fbi
->reg_lccr3
& ~0xff) |
1247 LCCR3_PixClkDiv(pcd
);
1248 set_ctrlr_state(fbi
, C_ENABLE_CLKCHANGE
);
1255 pxafb_freq_policy(struct notifier_block
*nb
, unsigned long val
, void *data
)
1257 struct pxafb_info
*fbi
= TO_INF(nb
, freq_policy
);
1258 struct fb_var_screeninfo
*var
= &fbi
->fb
.var
;
1259 struct cpufreq_policy
*policy
= data
;
1262 case CPUFREQ_ADJUST
:
1263 case CPUFREQ_INCOMPATIBLE
:
1264 pr_debug("min dma period: %d ps, "
1265 "new clock %d kHz\n", pxafb_display_dma_period(var
),
1267 /* TODO: fill in min/max values */
1276 * Power management hooks. Note that we won't be called from IRQ context,
1277 * unlike the blank functions above, so we may sleep.
1279 static int pxafb_suspend(struct platform_device
*dev
, pm_message_t state
)
1281 struct pxafb_info
*fbi
= platform_get_drvdata(dev
);
1283 set_ctrlr_state(fbi
, C_DISABLE_PM
);
1287 static int pxafb_resume(struct platform_device
*dev
)
1289 struct pxafb_info
*fbi
= platform_get_drvdata(dev
);
1291 set_ctrlr_state(fbi
, C_ENABLE_PM
);
1295 #define pxafb_suspend NULL
1296 #define pxafb_resume NULL
1300 * pxafb_map_video_memory():
1301 * Allocates the DRAM memory for the frame buffer. This buffer is
1302 * remapped into a non-cached, non-buffered, memory region to
1303 * allow palette and pixel writes to occur without flushing the
1304 * cache. Once this area is remapped, all virtual memory
1305 * access to the video memory should occur at the new region.
1307 static int __devinit
pxafb_map_video_memory(struct pxafb_info
*fbi
)
1310 * We reserve one page for the palette, plus the size
1311 * of the framebuffer.
1313 fbi
->video_offset
= PAGE_ALIGN(sizeof(struct pxafb_dma_buff
));
1314 fbi
->map_size
= PAGE_ALIGN(fbi
->fb
.fix
.smem_len
+ fbi
->video_offset
);
1315 fbi
->map_cpu
= dma_alloc_writecombine(fbi
->dev
, fbi
->map_size
,
1316 &fbi
->map_dma
, GFP_KERNEL
);
1319 /* prevent initial garbage on screen */
1320 memset(fbi
->map_cpu
, 0, fbi
->map_size
);
1321 fbi
->fb
.screen_base
= fbi
->map_cpu
+ fbi
->video_offset
;
1322 fbi
->screen_dma
= fbi
->map_dma
+ fbi
->video_offset
;
1325 * FIXME: this is actually the wrong thing to place in
1326 * smem_start. But fbdev suffers from the problem that
1327 * it needs an API which doesn't exist (in this case,
1328 * dma_writecombine_mmap)
1330 fbi
->fb
.fix
.smem_start
= fbi
->screen_dma
;
1331 fbi
->palette_size
= fbi
->fb
.var
.bits_per_pixel
== 8 ? 256 : 16;
1333 fbi
->dma_buff
= (void *) fbi
->map_cpu
;
1334 fbi
->dma_buff_phys
= fbi
->map_dma
;
1335 fbi
->palette_cpu
= (u16
*) fbi
->dma_buff
->palette
;
1337 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", fbi
->palette_size
*sizeof(u16
));
1339 #ifdef CONFIG_FB_PXA_SMARTPANEL
1340 fbi
->smart_cmds
= (uint16_t *) fbi
->dma_buff
->cmd_buff
;
1341 fbi
->n_smart_cmds
= 0;
1345 return fbi
->map_cpu
? 0 : -ENOMEM
;
1348 static void pxafb_decode_mode_info(struct pxafb_info
*fbi
,
1349 struct pxafb_mode_info
*modes
,
1350 unsigned int num_modes
)
1352 unsigned int i
, smemlen
;
1354 pxafb_setmode(&fbi
->fb
.var
, &modes
[0]);
1356 for (i
= 0; i
< num_modes
; i
++) {
1357 smemlen
= modes
[i
].xres
* modes
[i
].yres
* modes
[i
].bpp
/ 8;
1358 if (smemlen
> fbi
->fb
.fix
.smem_len
)
1359 fbi
->fb
.fix
.smem_len
= smemlen
;
1363 static void pxafb_decode_mach_info(struct pxafb_info
*fbi
,
1364 struct pxafb_mach_info
*inf
)
1366 unsigned int lcd_conn
= inf
->lcd_conn
;
1368 fbi
->cmap_inverse
= inf
->cmap_inverse
;
1369 fbi
->cmap_static
= inf
->cmap_static
;
1371 switch (lcd_conn
& 0xf) {
1372 case LCD_TYPE_MONO_STN
:
1373 fbi
->lccr0
= LCCR0_CMS
;
1375 case LCD_TYPE_MONO_DSTN
:
1376 fbi
->lccr0
= LCCR0_CMS
| LCCR0_SDS
;
1378 case LCD_TYPE_COLOR_STN
:
1381 case LCD_TYPE_COLOR_DSTN
:
1382 fbi
->lccr0
= LCCR0_SDS
;
1384 case LCD_TYPE_COLOR_TFT
:
1385 fbi
->lccr0
= LCCR0_PAS
;
1387 case LCD_TYPE_SMART_PANEL
:
1388 fbi
->lccr0
= LCCR0_LCDT
| LCCR0_PAS
;
1391 /* fall back to backward compatibility way */
1392 fbi
->lccr0
= inf
->lccr0
;
1393 fbi
->lccr3
= inf
->lccr3
;
1394 fbi
->lccr4
= inf
->lccr4
;
1398 if (lcd_conn
== LCD_MONO_STN_8BPP
)
1399 fbi
->lccr0
|= LCCR0_DPD
;
1401 fbi
->lccr3
= LCCR3_Acb((inf
->lcd_conn
>> 10) & 0xff);
1402 fbi
->lccr3
|= (lcd_conn
& LCD_BIAS_ACTIVE_LOW
) ? LCCR3_OEP
: 0;
1403 fbi
->lccr3
|= (lcd_conn
& LCD_PCLK_EDGE_FALL
) ? LCCR3_PCP
: 0;
1406 pxafb_decode_mode_info(fbi
, inf
->modes
, inf
->num_modes
);
1409 static struct pxafb_info
* __devinit
pxafb_init_fbinfo(struct device
*dev
)
1411 struct pxafb_info
*fbi
;
1413 struct pxafb_mach_info
*inf
= dev
->platform_data
;
1415 /* Alloc the pxafb_info and pseudo_palette in one step */
1416 fbi
= kmalloc(sizeof(struct pxafb_info
) + sizeof(u32
) * 16, GFP_KERNEL
);
1420 memset(fbi
, 0, sizeof(struct pxafb_info
));
1423 fbi
->clk
= clk_get(dev
, "LCDCLK");
1424 if (IS_ERR(fbi
->clk
)) {
1429 strcpy(fbi
->fb
.fix
.id
, PXA_NAME
);
1431 fbi
->fb
.fix
.type
= FB_TYPE_PACKED_PIXELS
;
1432 fbi
->fb
.fix
.type_aux
= 0;
1433 fbi
->fb
.fix
.xpanstep
= 0;
1434 fbi
->fb
.fix
.ypanstep
= 0;
1435 fbi
->fb
.fix
.ywrapstep
= 0;
1436 fbi
->fb
.fix
.accel
= FB_ACCEL_NONE
;
1438 fbi
->fb
.var
.nonstd
= 0;
1439 fbi
->fb
.var
.activate
= FB_ACTIVATE_NOW
;
1440 fbi
->fb
.var
.height
= -1;
1441 fbi
->fb
.var
.width
= -1;
1442 fbi
->fb
.var
.accel_flags
= 0;
1443 fbi
->fb
.var
.vmode
= FB_VMODE_NONINTERLACED
;
1445 fbi
->fb
.fbops
= &pxafb_ops
;
1446 fbi
->fb
.flags
= FBINFO_DEFAULT
;
1450 addr
= addr
+ sizeof(struct pxafb_info
);
1451 fbi
->fb
.pseudo_palette
= addr
;
1453 fbi
->state
= C_STARTUP
;
1454 fbi
->task_state
= (u_char
)-1;
1456 pxafb_decode_mach_info(fbi
, inf
);
1458 init_waitqueue_head(&fbi
->ctrlr_wait
);
1459 INIT_WORK(&fbi
->task
, pxafb_task
);
1460 init_MUTEX(&fbi
->ctrlr_sem
);
1461 init_completion(&fbi
->disable_done
);
1462 #ifdef CONFIG_FB_PXA_SMARTPANEL
1463 init_completion(&fbi
->command_done
);
1464 init_completion(&fbi
->refresh_done
);
1470 #ifdef CONFIG_FB_PXA_PARAMETERS
1471 static int __devinit
parse_opt_mode(struct device
*dev
, const char *this_opt
)
1473 struct pxafb_mach_info
*inf
= dev
->platform_data
;
1475 const char *name
= this_opt
+5;
1476 unsigned int namelen
= strlen(name
);
1477 int res_specified
= 0, bpp_specified
= 0;
1478 unsigned int xres
= 0, yres
= 0, bpp
= 0;
1479 int yres_specified
= 0;
1481 for (i
= namelen
-1; i
>= 0; i
--) {
1485 if (!bpp_specified
&& !yres_specified
) {
1486 bpp
= simple_strtoul(&name
[i
+1], NULL
, 0);
1492 if (!yres_specified
) {
1493 yres
= simple_strtoul(&name
[i
+1], NULL
, 0);
1504 if (i
< 0 && yres_specified
) {
1505 xres
= simple_strtoul(name
, NULL
, 0);
1509 if (res_specified
) {
1510 dev_info(dev
, "overriding resolution: %dx%d\n", xres
, yres
);
1511 inf
->modes
[0].xres
= xres
; inf
->modes
[0].yres
= yres
;
1520 inf
->modes
[0].bpp
= bpp
;
1521 dev_info(dev
, "overriding bit depth: %d\n", bpp
);
1524 dev_err(dev
, "Depth %d is not valid\n", bpp
);
1530 static int __devinit
parse_opt(struct device
*dev
, char *this_opt
)
1532 struct pxafb_mach_info
*inf
= dev
->platform_data
;
1533 struct pxafb_mode_info
*mode
= &inf
->modes
[0];
1538 if (!strncmp(this_opt
, "mode:", 5)) {
1539 return parse_opt_mode(dev
, this_opt
);
1540 } else if (!strncmp(this_opt
, "pixclock:", 9)) {
1541 mode
->pixclock
= simple_strtoul(this_opt
+9, NULL
, 0);
1542 sprintf(s
, "pixclock: %ld\n", mode
->pixclock
);
1543 } else if (!strncmp(this_opt
, "left:", 5)) {
1544 mode
->left_margin
= simple_strtoul(this_opt
+5, NULL
, 0);
1545 sprintf(s
, "left: %u\n", mode
->left_margin
);
1546 } else if (!strncmp(this_opt
, "right:", 6)) {
1547 mode
->right_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1548 sprintf(s
, "right: %u\n", mode
->right_margin
);
1549 } else if (!strncmp(this_opt
, "upper:", 6)) {
1550 mode
->upper_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1551 sprintf(s
, "upper: %u\n", mode
->upper_margin
);
1552 } else if (!strncmp(this_opt
, "lower:", 6)) {
1553 mode
->lower_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1554 sprintf(s
, "lower: %u\n", mode
->lower_margin
);
1555 } else if (!strncmp(this_opt
, "hsynclen:", 9)) {
1556 mode
->hsync_len
= simple_strtoul(this_opt
+9, NULL
, 0);
1557 sprintf(s
, "hsynclen: %u\n", mode
->hsync_len
);
1558 } else if (!strncmp(this_opt
, "vsynclen:", 9)) {
1559 mode
->vsync_len
= simple_strtoul(this_opt
+9, NULL
, 0);
1560 sprintf(s
, "vsynclen: %u\n", mode
->vsync_len
);
1561 } else if (!strncmp(this_opt
, "hsync:", 6)) {
1562 if (simple_strtoul(this_opt
+6, NULL
, 0) == 0) {
1563 sprintf(s
, "hsync: Active Low\n");
1564 mode
->sync
&= ~FB_SYNC_HOR_HIGH_ACT
;
1566 sprintf(s
, "hsync: Active High\n");
1567 mode
->sync
|= FB_SYNC_HOR_HIGH_ACT
;
1569 } else if (!strncmp(this_opt
, "vsync:", 6)) {
1570 if (simple_strtoul(this_opt
+6, NULL
, 0) == 0) {
1571 sprintf(s
, "vsync: Active Low\n");
1572 mode
->sync
&= ~FB_SYNC_VERT_HIGH_ACT
;
1574 sprintf(s
, "vsync: Active High\n");
1575 mode
->sync
|= FB_SYNC_VERT_HIGH_ACT
;
1577 } else if (!strncmp(this_opt
, "dpc:", 4)) {
1578 if (simple_strtoul(this_opt
+4, NULL
, 0) == 0) {
1579 sprintf(s
, "double pixel clock: false\n");
1580 inf
->lccr3
&= ~LCCR3_DPC
;
1582 sprintf(s
, "double pixel clock: true\n");
1583 inf
->lccr3
|= LCCR3_DPC
;
1585 } else if (!strncmp(this_opt
, "outputen:", 9)) {
1586 if (simple_strtoul(this_opt
+9, NULL
, 0) == 0) {
1587 sprintf(s
, "output enable: active low\n");
1588 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_OEP
) | LCCR3_OutEnL
;
1590 sprintf(s
, "output enable: active high\n");
1591 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_OEP
) | LCCR3_OutEnH
;
1593 } else if (!strncmp(this_opt
, "pixclockpol:", 12)) {
1594 if (simple_strtoul(this_opt
+12, NULL
, 0) == 0) {
1595 sprintf(s
, "pixel clock polarity: falling edge\n");
1596 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_PCP
) | LCCR3_PixFlEdg
;
1598 sprintf(s
, "pixel clock polarity: rising edge\n");
1599 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_PCP
) | LCCR3_PixRsEdg
;
1601 } else if (!strncmp(this_opt
, "color", 5)) {
1602 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_CMS
) | LCCR0_Color
;
1603 } else if (!strncmp(this_opt
, "mono", 4)) {
1604 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_CMS
) | LCCR0_Mono
;
1605 } else if (!strncmp(this_opt
, "active", 6)) {
1606 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_PAS
) | LCCR0_Act
;
1607 } else if (!strncmp(this_opt
, "passive", 7)) {
1608 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_PAS
) | LCCR0_Pas
;
1609 } else if (!strncmp(this_opt
, "single", 6)) {
1610 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_SDS
) | LCCR0_Sngl
;
1611 } else if (!strncmp(this_opt
, "dual", 4)) {
1612 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_SDS
) | LCCR0_Dual
;
1613 } else if (!strncmp(this_opt
, "4pix", 4)) {
1614 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_DPD
) | LCCR0_4PixMono
;
1615 } else if (!strncmp(this_opt
, "8pix", 4)) {
1616 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_DPD
) | LCCR0_8PixMono
;
1618 dev_err(dev
, "unknown option: %s\n", this_opt
);
1623 dev_info(dev
, "override %s", s
);
1628 static int __devinit
pxafb_parse_options(struct device
*dev
, char *options
)
1633 if (!options
|| !*options
)
1636 dev_dbg(dev
, "options are \"%s\"\n", options
? options
: "null");
1638 /* could be made table driven or similar?... */
1639 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
1640 ret
= parse_opt(dev
, this_opt
);
1647 static char g_options
[256] __devinitdata
= "";
1650 static int __init
pxafb_setup_options(void)
1652 char *options
= NULL
;
1654 if (fb_get_options("pxafb", &options
))
1658 strlcpy(g_options
, options
, sizeof(g_options
));
1663 #define pxafb_setup_options() (0)
1665 module_param_string(options
, g_options
, sizeof(g_options
), 0);
1666 MODULE_PARM_DESC(options
, "LCD parameters (see Documentation/fb/pxafb.txt)");
1670 #define pxafb_parse_options(...) (0)
1671 #define pxafb_setup_options() (0)
1674 static int __devinit
pxafb_probe(struct platform_device
*dev
)
1676 struct pxafb_info
*fbi
;
1677 struct pxafb_mach_info
*inf
;
1681 dev_dbg(&dev
->dev
, "pxafb_probe\n");
1683 inf
= dev
->dev
.platform_data
;
1689 ret
= pxafb_parse_options(&dev
->dev
, g_options
);
1694 /* Check for various illegal bit-combinations. Currently only
1695 * a warning is given. */
1697 if (inf
->lccr0
& LCCR0_INVALID_CONFIG_MASK
)
1698 dev_warn(&dev
->dev
, "machine LCCR0 setting contains "
1699 "illegal bits: %08x\n",
1700 inf
->lccr0
& LCCR0_INVALID_CONFIG_MASK
);
1701 if (inf
->lccr3
& LCCR3_INVALID_CONFIG_MASK
)
1702 dev_warn(&dev
->dev
, "machine LCCR3 setting contains "
1703 "illegal bits: %08x\n",
1704 inf
->lccr3
& LCCR3_INVALID_CONFIG_MASK
);
1705 if (inf
->lccr0
& LCCR0_DPD
&&
1706 ((inf
->lccr0
& LCCR0_PAS
) != LCCR0_Pas
||
1707 (inf
->lccr0
& LCCR0_SDS
) != LCCR0_Sngl
||
1708 (inf
->lccr0
& LCCR0_CMS
) != LCCR0_Mono
))
1709 dev_warn(&dev
->dev
, "Double Pixel Data (DPD) mode is "
1710 "only valid in passive mono"
1711 " single panel mode\n");
1712 if ((inf
->lccr0
& LCCR0_PAS
) == LCCR0_Act
&&
1713 (inf
->lccr0
& LCCR0_SDS
) == LCCR0_Dual
)
1714 dev_warn(&dev
->dev
, "Dual panel only valid in passive mode\n");
1715 if ((inf
->lccr0
& LCCR0_PAS
) == LCCR0_Pas
&&
1716 (inf
->modes
->upper_margin
|| inf
->modes
->lower_margin
))
1717 dev_warn(&dev
->dev
, "Upper and lower margins must be 0 in "
1721 dev_dbg(&dev
->dev
, "got a %dx%dx%d LCD\n",
1725 if (inf
->modes
->xres
== 0 ||
1726 inf
->modes
->yres
== 0 ||
1727 inf
->modes
->bpp
== 0) {
1728 dev_err(&dev
->dev
, "Invalid resolution or bit depth\n");
1732 pxafb_backlight_power
= inf
->pxafb_backlight_power
;
1733 pxafb_lcd_power
= inf
->pxafb_lcd_power
;
1734 fbi
= pxafb_init_fbinfo(&dev
->dev
);
1736 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1737 dev_err(&dev
->dev
, "Failed to initialize framebuffer device\n");
1742 r
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
1744 dev_err(&dev
->dev
, "no I/O memory resource defined\n");
1749 r
= request_mem_region(r
->start
, r
->end
- r
->start
+ 1, dev
->name
);
1751 dev_err(&dev
->dev
, "failed to request I/O memory\n");
1756 fbi
->mmio_base
= ioremap(r
->start
, r
->end
- r
->start
+ 1);
1757 if (fbi
->mmio_base
== NULL
) {
1758 dev_err(&dev
->dev
, "failed to map I/O memory\n");
1760 goto failed_free_res
;
1763 /* Initialize video memory */
1764 ret
= pxafb_map_video_memory(fbi
);
1766 dev_err(&dev
->dev
, "Failed to allocate video RAM: %d\n", ret
);
1768 goto failed_free_io
;
1771 irq
= platform_get_irq(dev
, 0);
1773 dev_err(&dev
->dev
, "no IRQ defined\n");
1775 goto failed_free_mem
;
1778 ret
= request_irq(irq
, pxafb_handle_irq
, IRQF_DISABLED
, "LCD", fbi
);
1780 dev_err(&dev
->dev
, "request_irq failed: %d\n", ret
);
1782 goto failed_free_mem
;
1785 #ifdef CONFIG_FB_PXA_SMARTPANEL
1786 ret
= pxafb_smart_init(fbi
);
1788 dev_err(&dev
->dev
, "failed to initialize smartpanel\n");
1789 goto failed_free_irq
;
1793 * This makes sure that our colour bitfield
1794 * descriptors are correctly initialised.
1796 ret
= pxafb_check_var(&fbi
->fb
.var
, &fbi
->fb
);
1798 dev_err(&dev
->dev
, "failed to get suitable mode\n");
1799 goto failed_free_irq
;
1802 ret
= pxafb_set_par(&fbi
->fb
);
1804 dev_err(&dev
->dev
, "Failed to set parameters\n");
1805 goto failed_free_irq
;
1808 platform_set_drvdata(dev
, fbi
);
1810 ret
= register_framebuffer(&fbi
->fb
);
1813 "Failed to register framebuffer device: %d\n", ret
);
1814 goto failed_free_cmap
;
1817 #ifdef CONFIG_CPU_FREQ
1818 fbi
->freq_transition
.notifier_call
= pxafb_freq_transition
;
1819 fbi
->freq_policy
.notifier_call
= pxafb_freq_policy
;
1820 cpufreq_register_notifier(&fbi
->freq_transition
,
1821 CPUFREQ_TRANSITION_NOTIFIER
);
1822 cpufreq_register_notifier(&fbi
->freq_policy
,
1823 CPUFREQ_POLICY_NOTIFIER
);
1827 * Ok, now enable the LCD controller
1829 set_ctrlr_state(fbi
, C_ENABLE
);
1834 if (fbi
->fb
.cmap
.len
)
1835 fb_dealloc_cmap(&fbi
->fb
.cmap
);
1839 dma_free_writecombine(&dev
->dev
, fbi
->map_size
,
1840 fbi
->map_cpu
, fbi
->map_dma
);
1842 iounmap(fbi
->mmio_base
);
1844 release_mem_region(r
->start
, r
->end
- r
->start
+ 1);
1847 platform_set_drvdata(dev
, NULL
);
1853 static int __devexit
pxafb_remove(struct platform_device
*dev
)
1855 struct pxafb_info
*fbi
= platform_get_drvdata(dev
);
1858 struct fb_info
*info
;
1865 unregister_framebuffer(info
);
1867 pxafb_disable_controller(fbi
);
1869 if (fbi
->fb
.cmap
.len
)
1870 fb_dealloc_cmap(&fbi
->fb
.cmap
);
1872 irq
= platform_get_irq(dev
, 0);
1875 dma_free_writecombine(&dev
->dev
, fbi
->map_size
,
1876 fbi
->map_cpu
, fbi
->map_dma
);
1878 iounmap(fbi
->mmio_base
);
1880 r
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
1881 release_mem_region(r
->start
, r
->end
- r
->start
+ 1);
1889 static struct platform_driver pxafb_driver
= {
1890 .probe
= pxafb_probe
,
1891 .remove
= pxafb_remove
,
1892 .suspend
= pxafb_suspend
,
1893 .resume
= pxafb_resume
,
1895 .owner
= THIS_MODULE
,
1896 .name
= "pxa2xx-fb",
1900 static int __init
pxafb_init(void)
1902 if (pxafb_setup_options())
1905 return platform_driver_register(&pxafb_driver
);
1908 static void __exit
pxafb_exit(void)
1910 platform_driver_unregister(&pxafb_driver
);
1913 module_init(pxafb_init
);
1914 module_exit(pxafb_exit
);
1916 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1917 MODULE_LICENSE("GPL");