2 * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
4 * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file COPYING in the main directory of this
8 * archive for more details.
12 #ifndef __SAVAGEFB_H__
13 #define __SAVAGEFB_H__
15 #include <linux/i2c.h>
16 #include <linux/i2c-algo-bit.h>
17 #include <linux/mutex.h>
18 #include <video/vga.h>
22 # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
25 # define SavagePrintRegs(...)
29 #define PCI_CHIP_SAVAGE4 0x8a22
30 #define PCI_CHIP_SAVAGE3D 0x8a20
31 #define PCI_CHIP_SAVAGE3D_MV 0x8a21
32 #define PCI_CHIP_SAVAGE2000 0x9102
33 #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
34 #define PCI_CHIP_SAVAGE_MX 0x8c11
35 #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
36 #define PCI_CHIP_SAVAGE_IX 0x8c13
37 #define PCI_CHIP_PROSAVAGE_PM 0x8a25
38 #define PCI_CHIP_PROSAVAGE_KM 0x8a26
39 #define PCI_CHIP_S3TWISTER_P 0x8d01
40 #define PCI_CHIP_S3TWISTER_K 0x8d02
41 #define PCI_CHIP_PROSAVAGE_DDR 0x8d03
42 #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
43 #define PCI_CHIP_SUPSAV_MX128 0x8c22
44 #define PCI_CHIP_SUPSAV_MX64 0x8c24
45 #define PCI_CHIP_SUPSAV_MX64C 0x8c26
46 #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
47 #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
48 #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
49 #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
50 #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
51 #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
54 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
56 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
58 #define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR))
60 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
62 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR))
64 /* Chip tags. These are used to group the adapters into
81 #define BIOS_BSIZE 1024
82 #define BIOS_BASE 0xc0000
84 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
85 #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
86 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
87 #define SAVAGE_NEWMMIO_VGABASE 0x8000
89 #define BASE_FREQ 14318
90 #define HALF_BASE_FREQ 7159
92 #define FIFO_CONTROL_REG 0x8200
93 #define MIU_CONTROL_REG 0x8204
94 #define STREAMS_TIMEOUT_REG 0x8208
95 #define MISC_TIMEOUT_REG 0x820c
97 #define MONO_PAT_0 0xa4e8
98 #define MONO_PAT_1 0xa4ec
100 #define MAXFIFO 0x7f00
102 #define BCI_CMD_NOP 0x40000000
103 #define BCI_CMD_SETREG 0x96000000
104 #define BCI_CMD_RECT 0x48000000
105 #define BCI_CMD_RECT_XP 0x01000000
106 #define BCI_CMD_RECT_YP 0x02000000
107 #define BCI_CMD_SEND_COLOR 0x00008000
108 #define BCI_CMD_DEST_GBD 0x00000000
109 #define BCI_CMD_SRC_GBD 0x00000020
110 #define BCI_CMD_SRC_SOLID 0x00000000
111 #define BCI_CMD_SRC_MONO 0x00000060
112 #define BCI_CMD_CLIP_NEW 0x00006000
113 #define BCI_CMD_CLIP_LR 0x00004000
115 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
116 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
117 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
118 #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
119 #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
121 #define BCI_GBD1 0xE0
122 #define BCI_GBD2 0xE1
124 #define BCI_BUFFER_OFFSET 0x10000
125 #define BCI_SIZE 0x4000
127 #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
129 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
130 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
131 #define BCI_CMD_SEND_COLOR 0x00008000
139 unsigned int HDisplay
;
140 unsigned int HSyncStart
;
141 unsigned int HSyncEnd
;
143 unsigned int HAdjusted
;
144 unsigned int VDisplay
;
145 unsigned int VSyncStart
;
146 unsigned int VSyncEnd
;
154 unsigned char MiscOutReg
; /* Misc */
155 unsigned char CRTC
[25]; /* Crtc Controller */
156 unsigned char Sequencer
[5]; /* Video Sequencer */
157 unsigned char Graphics
[9]; /* Video Graphics */
158 unsigned char Attribute
[21]; /* Video Attribute */
160 unsigned int mode
, refresh
;
161 unsigned char SR08
, SR0E
, SR0F
;
162 unsigned char SR10
, SR11
, SR12
, SR13
, SR15
, SR18
, SR29
, SR30
;
163 unsigned char SR54
[8];
165 unsigned char CR31
, CR32
, CR33
, CR34
, CR36
, CR3A
, CR3B
, CR3C
;
166 unsigned char CR40
, CR41
, CR42
, CR43
, CR45
;
167 unsigned char CR50
, CR51
, CR53
, CR55
, CR58
, CR5B
, CR5D
, CR5E
;
168 unsigned char CR60
, CR63
, CR65
, CR66
, CR67
, CR68
, CR69
, CR6D
, CR6F
;
169 unsigned char CR86
, CR88
;
170 unsigned char CR90
, CR91
, CRB0
;
171 unsigned int STREAMS
[22]; /* yuck, streams regs */
172 unsigned int MMPR0
, MMPR1
, MMPR2
, MMPR3
;
174 /* --------------------------------------------------------------------- */
176 #define NR_PALETTE 256
181 struct savagefb_i2c_chan
{
182 struct savagefb_par
*par
;
183 struct i2c_adapter adapter
;
184 struct i2c_algo_bit_data algo
;
185 volatile u8 __iomem
*ioaddr
;
189 struct savagefb_par
{
190 struct pci_dev
*pcidev
;
192 struct savagefb_i2c_chan chan
;
193 struct savage_reg state
;
194 struct savage_reg save
;
195 struct savage_reg initial
;
196 struct vgastate vgastate
;
197 struct mutex open_lock
;
199 u32 pseudo_palette
[16];
211 int MCLK
, REFCLK
, LCDclk
;
227 volatile u32 __iomem
*bci_base
;
228 unsigned int bci_ptr
;
233 void (*SavageWaitIdle
) (struct savagefb_par
*par
);
234 void (*SavageWaitFifo
) (struct savagefb_par
*par
, int space
);
236 int HorizScaleFactor
;
239 int SavagePanelWidth
;
240 int SavagePanelHeight
;
243 u16 red
, green
, blue
, transp
;
244 } palette
[NR_PALETTE
];
250 #define BCI_BD_BW_DISABLE 0x10000000
251 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
252 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
256 static inline u8
savage_in8(u32 addr
, struct savagefb_par
*par
)
258 return readb(par
->mmio
.vbase
+ addr
);
261 static inline u16
savage_in16(u32 addr
, struct savagefb_par
*par
)
263 return readw(par
->mmio
.vbase
+ addr
);
266 static inline u32
savage_in32(u32 addr
, struct savagefb_par
*par
)
268 return readl(par
->mmio
.vbase
+ addr
);
271 static inline void savage_out8(u32 addr
, u8 val
, struct savagefb_par
*par
)
273 writeb(val
, par
->mmio
.vbase
+ addr
);
276 static inline void savage_out16(u32 addr
, u16 val
, struct savagefb_par
*par
)
278 writew(val
, par
->mmio
.vbase
+ addr
);
281 static inline void savage_out32(u32 addr
, u32 val
, struct savagefb_par
*par
)
283 writel(val
, par
->mmio
.vbase
+ addr
);
286 static inline u8
vga_in8(int addr
, struct savagefb_par
*par
)
288 return savage_in8(0x8000 + addr
, par
);
291 static inline u16
vga_in16(int addr
, struct savagefb_par
*par
)
293 return savage_in16(0x8000 + addr
, par
);
296 static inline u8
vga_in32(int addr
, struct savagefb_par
*par
)
298 return savage_in32(0x8000 + addr
, par
);
301 static inline void vga_out8(int addr
, u8 val
, struct savagefb_par
*par
)
303 savage_out8(0x8000 + addr
, val
, par
);
306 static inline void vga_out16(int addr
, u16 val
, struct savagefb_par
*par
)
308 savage_out16(0x8000 + addr
, val
, par
);
311 static inline void vga_out32(int addr
, u32 val
, struct savagefb_par
*par
)
313 savage_out32(0x8000 + addr
, val
, par
);
316 static inline u8
VGArCR (u8 index
, struct savagefb_par
*par
)
318 vga_out8(0x3d4, index
, par
);
319 return vga_in8(0x3d5, par
);
322 static inline u8
VGArGR (u8 index
, struct savagefb_par
*par
)
324 vga_out8(0x3ce, index
, par
);
325 return vga_in8(0x3cf, par
);
328 static inline u8
VGArSEQ (u8 index
, struct savagefb_par
*par
)
330 vga_out8(0x3c4, index
, par
);
331 return vga_in8(0x3c5, par
);
334 static inline void VGAwCR(u8 index
, u8 val
, struct savagefb_par
*par
)
336 vga_out8(0x3d4, index
, par
);
337 vga_out8(0x3d5, val
, par
);
340 static inline void VGAwGR(u8 index
, u8 val
, struct savagefb_par
*par
)
342 vga_out8(0x3ce, index
, par
);
343 vga_out8(0x3cf, val
, par
);
346 static inline void VGAwSEQ(u8 index
, u8 val
, struct savagefb_par
*par
)
348 vga_out8(0x3c4, index
, par
);
349 vga_out8 (0x3c5, val
, par
);
352 static inline void VGAenablePalette(struct savagefb_par
*par
)
356 tmp
= vga_in8(0x3da, par
);
357 vga_out8(0x3c0, 0x00, par
);
358 par
->paletteEnabled
= 1;
361 static inline void VGAdisablePalette(struct savagefb_par
*par
)
365 tmp
= vga_in8(0x3da, par
);
366 vga_out8(0x3c0, 0x20, par
);
367 par
->paletteEnabled
= 0;
370 static inline void VGAwATTR(u8 index
, u8 value
, struct savagefb_par
*par
)
374 if (par
->paletteEnabled
)
379 tmp
= vga_in8(0x3da, par
);
380 vga_out8(0x3c0, index
, par
);
381 vga_out8 (0x3c0, value
, par
);
384 static inline void VGAwMISC(u8 value
, struct savagefb_par
*par
)
386 vga_out8(0x3c2, value
, par
);
389 #ifndef CONFIG_FB_SAVAGE_ACCEL
390 #define savagefb_set_clip(x)
393 static inline void VerticalRetraceWait(struct savagefb_par
*par
)
395 vga_out8(0x3d4, 0x17, par
);
396 if (vga_in8(0x3d5, par
) & 0x80) {
397 while ((vga_in8(0x3da, par
) & 0x08) == 0x08);
398 while ((vga_in8(0x3da, par
) & 0x08) == 0x00);
402 extern int savagefb_probe_i2c_connector(struct fb_info
*info
,
404 extern void savagefb_create_i2c_busses(struct fb_info
*info
);
405 extern void savagefb_delete_i2c_busses(struct fb_info
*info
);
406 extern int savagefb_sync(struct fb_info
*info
);
407 extern void savagefb_copyarea(struct fb_info
*info
,
408 const struct fb_copyarea
*region
);
409 extern void savagefb_fillrect(struct fb_info
*info
,
410 const struct fb_fillrect
*rect
);
411 extern void savagefb_imageblit(struct fb_info
*info
,
412 const struct fb_image
*image
);
415 #endif /* __SAVAGEFB_H__ */
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