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tdfxfb: move I2C functionality into the tdfxfb
[deliverable/linux.git] / drivers / video / tdfxfb.c
1 /*
2 *
3 * tdfxfb.c
4 *
5 * Author: Hannu Mallat <hmallat@cc.hut.fi>
6 *
7 * Copyright © 1999 Hannu Mallat
8 * All rights reserved
9 *
10 * Created : Thu Sep 23 18:17:43 1999, hmallat
11 * Last modified: Tue Nov 2 21:19:47 1999, hmallat
12 *
13 * I2C part copied from the i2c-voodoo3.c driver by:
14 * Frodo Looijaard <frodol@dds.nl>,
15 * Philip Edelbrock <phil@netroedge.com>,
16 * Ralph Metzler <rjkm@thp.uni-koeln.de>, and
17 * Mark D. Studebaker <mdsxyz123@yahoo.com>
18 *
19 * Lots of the information here comes from the Daryll Strauss' Banshee
20 * patches to the XF86 server, and the rest comes from the 3dfx
21 * Banshee specification. I'm very much indebted to Daryll for his
22 * work on the X server.
23 *
24 * Voodoo3 support was contributed Harold Oga. Lots of additions
25 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
26 * Kesmarki. Thanks guys!
27 *
28 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
29 * behave very differently from the Voodoo3/4/5. For anyone wanting to
30 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
31 * located at http://www.sourceforge.net/projects/sstfb).
32 *
33 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
34 * I do wish the next version is a bit more complete. Without the XF86
35 * patches I couldn't have gotten even this far... for instance, the
36 * extensions to the VGA register set go completely unmentioned in the
37 * spec! Also, lots of references are made to the 'SST core', but no
38 * spec is publicly available, AFAIK.
39 *
40 * The structure of this driver comes pretty much from the Permedia
41 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
42 *
43 * TODO:
44 * - multihead support (basically need to support an array of fb_infos)
45 * - support other architectures (PPC, Alpha); does the fact that the VGA
46 * core can be accessed only thru I/O (not memory mapped) complicate
47 * things?
48 *
49 * Version history:
50 *
51 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
52 *
53 * 0.1.3 (released 1999-11-02) added Attila's panning support, code
54 * reorg, hwcursor address page size alignment
55 * (for mmaping both frame buffer and regs),
56 * and my changes to get rid of hardcoded
57 * VGA i/o register locations (uses PCI
58 * configuration info now)
59 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
60 * improvements
61 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
62 * 0.1.0 (released 1999-10-06) initial version
63 *
64 */
65
66 #include <linux/module.h>
67 #include <linux/kernel.h>
68 #include <linux/errno.h>
69 #include <linux/string.h>
70 #include <linux/mm.h>
71 #include <linux/slab.h>
72 #include <linux/fb.h>
73 #include <linux/init.h>
74 #include <linux/pci.h>
75 #include <asm/io.h>
76
77 #include <video/tdfx.h>
78
79 #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b)
80
81 #ifdef CONFIG_MTRR
82 #include <asm/mtrr.h>
83 #else
84 /* duplicate asm/mtrr.h defines to work on archs without mtrr */
85 #define MTRR_TYPE_WRCOMB 1
86
87 static inline int mtrr_add(unsigned long base, unsigned long size,
88 unsigned int type, char increment)
89 {
90 return -ENODEV;
91 }
92 static inline int mtrr_del(int reg, unsigned long base,
93 unsigned long size)
94 {
95 return -ENODEV;
96 }
97 #endif
98
99 #define BANSHEE_MAX_PIXCLOCK 270000
100 #define VOODOO3_MAX_PIXCLOCK 300000
101 #define VOODOO5_MAX_PIXCLOCK 350000
102
103 static struct fb_fix_screeninfo tdfx_fix __devinitdata = {
104 .type = FB_TYPE_PACKED_PIXELS,
105 .visual = FB_VISUAL_PSEUDOCOLOR,
106 .ypanstep = 1,
107 .ywrapstep = 1,
108 .accel = FB_ACCEL_3DFX_BANSHEE
109 };
110
111 static struct fb_var_screeninfo tdfx_var __devinitdata = {
112 /* "640x480, 8 bpp @ 60 Hz */
113 .xres = 640,
114 .yres = 480,
115 .xres_virtual = 640,
116 .yres_virtual = 1024,
117 .bits_per_pixel = 8,
118 .red = {0, 8, 0},
119 .blue = {0, 8, 0},
120 .green = {0, 8, 0},
121 .activate = FB_ACTIVATE_NOW,
122 .height = -1,
123 .width = -1,
124 .accel_flags = FB_ACCELF_TEXT,
125 .pixclock = 39722,
126 .left_margin = 40,
127 .right_margin = 24,
128 .upper_margin = 32,
129 .lower_margin = 11,
130 .hsync_len = 96,
131 .vsync_len = 2,
132 .vmode = FB_VMODE_NONINTERLACED
133 };
134
135 /*
136 * PCI driver prototypes
137 */
138 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
139 const struct pci_device_id *id);
140 static void __devexit tdfxfb_remove(struct pci_dev *pdev);
141
142 static struct pci_device_id tdfxfb_id_table[] = {
143 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
145 0xff0000, 0 },
146 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
147 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
148 0xff0000, 0 },
149 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
150 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
151 0xff0000, 0 },
152 { 0, }
153 };
154
155 static struct pci_driver tdfxfb_driver = {
156 .name = "tdfxfb",
157 .id_table = tdfxfb_id_table,
158 .probe = tdfxfb_probe,
159 .remove = __devexit_p(tdfxfb_remove),
160 };
161
162 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
163
164 /*
165 * Driver data
166 */
167 static int nopan;
168 static int nowrap = 1; /* not implemented (yet) */
169 static int hwcursor = 1;
170 static char *mode_option __devinitdata;
171 /* mtrr option */
172 static int nomtrr __devinitdata;
173
174 /* -------------------------------------------------------------------------
175 * Hardware-specific funcions
176 * ------------------------------------------------------------------------- */
177
178 static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
179 {
180 return inb(par->iobase + reg - 0x300);
181 }
182
183 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
184 {
185 outb(val, par->iobase + reg - 0x300);
186 }
187
188 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
189 {
190 vga_outb(par, GRA_I, idx);
191 wmb();
192 vga_outb(par, GRA_D, val);
193 wmb();
194 }
195
196 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
197 {
198 vga_outb(par, SEQ_I, idx);
199 wmb();
200 vga_outb(par, SEQ_D, val);
201 wmb();
202 }
203
204 static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
205 {
206 vga_outb(par, SEQ_I, idx);
207 mb();
208 return vga_inb(par, SEQ_D);
209 }
210
211 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
212 {
213 vga_outb(par, CRT_I, idx);
214 wmb();
215 vga_outb(par, CRT_D, val);
216 wmb();
217 }
218
219 static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
220 {
221 vga_outb(par, CRT_I, idx);
222 mb();
223 return vga_inb(par, CRT_D);
224 }
225
226 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
227 {
228 unsigned char tmp;
229
230 tmp = vga_inb(par, IS1_R);
231 vga_outb(par, ATT_IW, idx);
232 vga_outb(par, ATT_IW, val);
233 }
234
235 static inline void vga_disable_video(struct tdfx_par *par)
236 {
237 unsigned char s;
238
239 s = seq_inb(par, 0x01) | 0x20;
240 seq_outb(par, 0x00, 0x01);
241 seq_outb(par, 0x01, s);
242 seq_outb(par, 0x00, 0x03);
243 }
244
245 static inline void vga_enable_video(struct tdfx_par *par)
246 {
247 unsigned char s;
248
249 s = seq_inb(par, 0x01) & 0xdf;
250 seq_outb(par, 0x00, 0x01);
251 seq_outb(par, 0x01, s);
252 seq_outb(par, 0x00, 0x03);
253 }
254
255 static inline void vga_enable_palette(struct tdfx_par *par)
256 {
257 vga_inb(par, IS1_R);
258 mb();
259 vga_outb(par, ATT_IW, 0x20);
260 }
261
262 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
263 {
264 return readl(par->regbase_virt + reg);
265 }
266
267 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
268 {
269 writel(val, par->regbase_virt + reg);
270 }
271
272 static inline void banshee_make_room(struct tdfx_par *par, int size)
273 {
274 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
275 * won't quit if you ask for more. */
276 while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
277 cpu_relax();
278 }
279
280 static int banshee_wait_idle(struct fb_info *info)
281 {
282 struct tdfx_par *par = info->par;
283 int i = 0;
284
285 banshee_make_room(par, 1);
286 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
287
288 do {
289 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
290 i++;
291 } while (i < 3);
292
293 return 0;
294 }
295
296 /*
297 * Set the color of a palette entry in 8bpp mode
298 */
299 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
300 {
301 banshee_make_room(par, 2);
302 tdfx_outl(par, DACADDR, regno);
303 /* read after write makes it working */
304 tdfx_inl(par, DACADDR);
305 tdfx_outl(par, DACDATA, c);
306 }
307
308 static u32 do_calc_pll(int freq, int *freq_out)
309 {
310 int m, n, k, best_m, best_n, best_k, best_error;
311 int fref = 14318;
312
313 best_error = freq;
314 best_n = best_m = best_k = 0;
315
316 for (k = 3; k >= 0; k--) {
317 for (m = 63; m >= 0; m--) {
318 /*
319 * Estimate value of n that produces target frequency
320 * with current m and k
321 */
322 int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
323
324 /* Search neighborhood of estimated n */
325 for (n = max(0, n_estimated);
326 n <= min(255, n_estimated + 1);
327 n++) {
328 /*
329 * Calculate PLL freqency with current m, k and
330 * estimated n
331 */
332 int f = (fref * (n + 2) / (m + 2)) >> k;
333 int error = abs(f - freq);
334
335 /*
336 * If this is the closest we've come to the
337 * target frequency then remember n, m and k
338 */
339 if (error < best_error) {
340 best_error = error;
341 best_n = n;
342 best_m = m;
343 best_k = k;
344 }
345 }
346 }
347 }
348
349 n = best_n;
350 m = best_m;
351 k = best_k;
352 *freq_out = (fref * (n + 2) / (m + 2)) >> k;
353
354 return (n << 8) | (m << 2) | k;
355 }
356
357 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
358 {
359 struct tdfx_par *par = info->par;
360 int i;
361
362 banshee_wait_idle(info);
363
364 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
365
366 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
367
368 banshee_make_room(par, 3);
369 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
370 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
371 #if 0
372 tdfx_outl(par, PLLCTRL1, reg->mempll);
373 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
374 #endif
375 tdfx_outl(par, PLLCTRL0, reg->vidpll);
376
377 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
378
379 for (i = 0; i < 5; i++)
380 seq_outb(par, i, reg->seq[i]);
381
382 for (i = 0; i < 25; i++)
383 crt_outb(par, i, reg->crt[i]);
384
385 for (i = 0; i < 9; i++)
386 gra_outb(par, i, reg->gra[i]);
387
388 for (i = 0; i < 21; i++)
389 att_outb(par, i, reg->att[i]);
390
391 crt_outb(par, 0x1a, reg->ext[0]);
392 crt_outb(par, 0x1b, reg->ext[1]);
393
394 vga_enable_palette(par);
395 vga_enable_video(par);
396
397 banshee_make_room(par, 9);
398 tdfx_outl(par, VGAINIT0, reg->vgainit0);
399 tdfx_outl(par, DACMODE, reg->dacmode);
400 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
401 tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
402
403 tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
404 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
405 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
406 tdfx_outl(par, VGAINIT1, reg->vgainit1);
407 tdfx_outl(par, MISCINIT0, reg->miscinit0);
408
409 banshee_make_room(par, 8);
410 tdfx_outl(par, SRCBASE, reg->startaddr);
411 tdfx_outl(par, DSTBASE, reg->startaddr);
412 tdfx_outl(par, COMMANDEXTRA_2D, 0);
413 tdfx_outl(par, CLIP0MIN, 0);
414 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
415 tdfx_outl(par, CLIP1MIN, 0);
416 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
417 tdfx_outl(par, SRCXY, 0);
418
419 banshee_wait_idle(info);
420 }
421
422 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
423 {
424 u32 draminit0 = tdfx_inl(par, DRAMINIT0);
425 u32 draminit1 = tdfx_inl(par, DRAMINIT1);
426 u32 miscinit1;
427 int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
428 int chip_size; /* in MB */
429 int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
430
431 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
432 /* Banshee/Voodoo3 */
433 chip_size = 2;
434 if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE))
435 chip_size = 1;
436 } else {
437 /* Voodoo4/5 */
438 has_sgram = 0;
439 chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK;
440 chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT);
441 }
442
443 /* disable block writes for SDRAM */
444 miscinit1 = tdfx_inl(par, MISCINIT1);
445 miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
446 miscinit1 |= MISCINIT1_CLUT_INV;
447
448 banshee_make_room(par, 1);
449 tdfx_outl(par, MISCINIT1, miscinit1);
450 return num_chips * chip_size * 1024l * 1024;
451 }
452
453 /* ------------------------------------------------------------------------- */
454
455 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
456 {
457 struct tdfx_par *par = info->par;
458 u32 lpitch;
459
460 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
461 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
462 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
463 return -EINVAL;
464 }
465
466 if (var->xres != var->xres_virtual)
467 var->xres_virtual = var->xres;
468
469 if (var->yres > var->yres_virtual)
470 var->yres_virtual = var->yres;
471
472 if (var->xoffset) {
473 DPRINTK("xoffset not supported\n");
474 return -EINVAL;
475 }
476 var->yoffset = 0;
477
478 /*
479 * Banshee doesn't support interlace, but Voodoo4/5 and probably
480 * Voodoo3 do.
481 * no direct information about device id now?
482 * use max_pixclock for this...
483 */
484 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
485 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
486 DPRINTK("interlace not supported\n");
487 return -EINVAL;
488 }
489
490 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
491 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
492
493 if (var->xres < 320 || var->xres > 2048) {
494 DPRINTK("width not supported: %u\n", var->xres);
495 return -EINVAL;
496 }
497
498 if (var->yres < 200 || var->yres > 2048) {
499 DPRINTK("height not supported: %u\n", var->yres);
500 return -EINVAL;
501 }
502
503 if (lpitch * var->yres_virtual > info->fix.smem_len) {
504 var->yres_virtual = info->fix.smem_len / lpitch;
505 if (var->yres_virtual < var->yres) {
506 DPRINTK("no memory for screen (%ux%ux%u)\n",
507 var->xres, var->yres_virtual,
508 var->bits_per_pixel);
509 return -EINVAL;
510 }
511 }
512
513 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
514 DPRINTK("pixclock too high (%ldKHz)\n",
515 PICOS2KHZ(var->pixclock));
516 return -EINVAL;
517 }
518
519 var->transp.offset = 0;
520 var->transp.length = 0;
521 switch (var->bits_per_pixel) {
522 case 8:
523 var->red.length = 8;
524 var->red.offset = 0;
525 var->green = var->red;
526 var->blue = var->red;
527 break;
528 case 16:
529 var->red.offset = 11;
530 var->red.length = 5;
531 var->green.offset = 5;
532 var->green.length = 6;
533 var->blue.offset = 0;
534 var->blue.length = 5;
535 break;
536 case 32:
537 var->transp.offset = 24;
538 var->transp.length = 8;
539 case 24:
540 var->red.offset = 16;
541 var->green.offset = 8;
542 var->blue.offset = 0;
543 var->red.length = var->green.length = var->blue.length = 8;
544 break;
545 }
546 var->width = -1;
547 var->height = -1;
548
549 var->accel_flags = FB_ACCELF_TEXT;
550
551 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
552 var->xres, var->yres, var->bits_per_pixel);
553 return 0;
554 }
555
556 static int tdfxfb_set_par(struct fb_info *info)
557 {
558 struct tdfx_par *par = info->par;
559 u32 hdispend = info->var.xres;
560 u32 hsyncsta = hdispend + info->var.right_margin;
561 u32 hsyncend = hsyncsta + info->var.hsync_len;
562 u32 htotal = hsyncend + info->var.left_margin;
563 u32 hd, hs, he, ht, hbs, hbe;
564 u32 vd, vs, ve, vt, vbs, vbe;
565 struct banshee_reg reg;
566 int fout, freq;
567 u32 wd;
568 u32 cpp = (info->var.bits_per_pixel + 7) >> 3;
569
570 memset(&reg, 0, sizeof(reg));
571
572 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
573 VIDCFG_CURS_X11 |
574 ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) |
575 (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
576
577 /* PLL settings */
578 freq = PICOS2KHZ(info->var.pixclock);
579
580 reg.vidcfg &= ~VIDCFG_2X;
581
582 if (freq > par->max_pixclock / 2) {
583 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
584 reg.dacmode |= DACMODE_2X;
585 reg.vidcfg |= VIDCFG_2X;
586 hdispend >>= 1;
587 hsyncsta >>= 1;
588 hsyncend >>= 1;
589 htotal >>= 1;
590 }
591
592 wd = (hdispend >> 3) - 1;
593 hd = wd;
594 hs = (hsyncsta >> 3) - 1;
595 he = (hsyncend >> 3) - 1;
596 ht = (htotal >> 3) - 1;
597 hbs = hd;
598 hbe = ht;
599
600 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
601 vd = (info->var.yres << 1) - 1;
602 vs = vd + (info->var.lower_margin << 1);
603 ve = vs + (info->var.vsync_len << 1);
604 vt = ve + (info->var.upper_margin << 1) - 1;
605 reg.screensize = info->var.xres | (info->var.yres << 13);
606 reg.vidcfg |= VIDCFG_HALF_MODE;
607 reg.crt[0x09] = 0x80;
608 } else {
609 vd = info->var.yres - 1;
610 vs = vd + info->var.lower_margin;
611 ve = vs + info->var.vsync_len;
612 vt = ve + info->var.upper_margin - 1;
613 reg.screensize = info->var.xres | (info->var.yres << 12);
614 reg.vidcfg &= ~VIDCFG_HALF_MODE;
615 }
616 vbs = vd;
617 vbe = vt;
618
619 /* this is all pretty standard VGA register stuffing */
620 reg.misc[0x00] = 0x0f |
621 (info->var.xres < 400 ? 0xa0 :
622 info->var.xres < 480 ? 0x60 :
623 info->var.xres < 768 ? 0xe0 : 0x20);
624
625 reg.gra[0x05] = 0x40;
626 reg.gra[0x06] = 0x05;
627 reg.gra[0x07] = 0x0f;
628 reg.gra[0x08] = 0xff;
629
630 reg.att[0x00] = 0x00;
631 reg.att[0x01] = 0x01;
632 reg.att[0x02] = 0x02;
633 reg.att[0x03] = 0x03;
634 reg.att[0x04] = 0x04;
635 reg.att[0x05] = 0x05;
636 reg.att[0x06] = 0x06;
637 reg.att[0x07] = 0x07;
638 reg.att[0x08] = 0x08;
639 reg.att[0x09] = 0x09;
640 reg.att[0x0a] = 0x0a;
641 reg.att[0x0b] = 0x0b;
642 reg.att[0x0c] = 0x0c;
643 reg.att[0x0d] = 0x0d;
644 reg.att[0x0e] = 0x0e;
645 reg.att[0x0f] = 0x0f;
646 reg.att[0x10] = 0x41;
647 reg.att[0x12] = 0x0f;
648
649 reg.seq[0x00] = 0x03;
650 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
651 reg.seq[0x02] = 0x0f;
652 reg.seq[0x03] = 0x00;
653 reg.seq[0x04] = 0x0e;
654
655 reg.crt[0x00] = ht - 4;
656 reg.crt[0x01] = hd;
657 reg.crt[0x02] = hbs;
658 reg.crt[0x03] = 0x80 | (hbe & 0x1f);
659 reg.crt[0x04] = hs;
660 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
661 reg.crt[0x06] = vt;
662 reg.crt[0x07] = ((vs & 0x200) >> 2) |
663 ((vd & 0x200) >> 3) |
664 ((vt & 0x200) >> 4) | 0x10 |
665 ((vbs & 0x100) >> 5) |
666 ((vs & 0x100) >> 6) |
667 ((vd & 0x100) >> 7) |
668 ((vt & 0x100) >> 8);
669 reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
670 reg.crt[0x10] = vs;
671 reg.crt[0x11] = (ve & 0x0f) | 0x20;
672 reg.crt[0x12] = vd;
673 reg.crt[0x13] = wd;
674 reg.crt[0x15] = vbs;
675 reg.crt[0x16] = vbe + 1;
676 reg.crt[0x17] = 0xc3;
677 reg.crt[0x18] = 0xff;
678
679 /* Banshee's nonvga stuff */
680 reg.ext[0x00] = (((ht & 0x100) >> 8) |
681 ((hd & 0x100) >> 6) |
682 ((hbs & 0x100) >> 4) |
683 ((hbe & 0x40) >> 1) |
684 ((hs & 0x100) >> 2) |
685 ((he & 0x20) << 2));
686 reg.ext[0x01] = (((vt & 0x400) >> 10) |
687 ((vd & 0x400) >> 8) |
688 ((vbs & 0x400) >> 6) |
689 ((vbe & 0x400) >> 4));
690
691 reg.vgainit0 = VGAINIT0_8BIT_DAC |
692 VGAINIT0_EXT_ENABLE |
693 VGAINIT0_WAKEUP_3C3 |
694 VGAINIT0_ALT_READBACK |
695 VGAINIT0_EXTSHIFTOUT;
696 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
697
698 if (hwcursor)
699 reg.curspataddr = info->fix.smem_len;
700
701 reg.cursloc = 0;
702
703 reg.cursc0 = 0;
704 reg.cursc1 = 0xffffff;
705
706 reg.stride = info->var.xres * cpp;
707 reg.startaddr = info->var.yoffset * reg.stride
708 + info->var.xoffset * cpp;
709
710 reg.vidpll = do_calc_pll(freq, &fout);
711 #if 0
712 reg.mempll = do_calc_pll(..., &fout);
713 reg.gfxpll = do_calc_pll(..., &fout);
714 #endif
715
716 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
717 reg.vidcfg |= VIDCFG_INTERLACE;
718 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
719
720 #if defined(__BIG_ENDIAN)
721 switch (info->var.bits_per_pixel) {
722 case 8:
723 case 24:
724 reg.miscinit0 &= ~(1 << 30);
725 reg.miscinit0 &= ~(1 << 31);
726 break;
727 case 16:
728 reg.miscinit0 |= (1 << 30);
729 reg.miscinit0 |= (1 << 31);
730 break;
731 case 32:
732 reg.miscinit0 |= (1 << 30);
733 reg.miscinit0 &= ~(1 << 31);
734 break;
735 }
736 #endif
737 do_write_regs(info, &reg);
738
739 /* Now change fb_fix_screeninfo according to changes in par */
740 info->fix.line_length = reg.stride;
741 info->fix.visual = (info->var.bits_per_pixel == 8)
742 ? FB_VISUAL_PSEUDOCOLOR
743 : FB_VISUAL_TRUECOLOR;
744 DPRINTK("Graphics mode is now set at %dx%d depth %d\n",
745 info->var.xres, info->var.yres, info->var.bits_per_pixel);
746 return 0;
747 }
748
749 /* A handy macro shamelessly pinched from matroxfb */
750 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
751
752 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
753 unsigned blue, unsigned transp,
754 struct fb_info *info)
755 {
756 struct tdfx_par *par = info->par;
757 u32 rgbcol;
758
759 if (regno >= info->cmap.len || regno > 255)
760 return 1;
761
762 /* grayscale works only partially under directcolor */
763 if (info->var.grayscale) {
764 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
765 blue = (red * 77 + green * 151 + blue * 28) >> 8;
766 green = blue;
767 red = blue;
768 }
769
770 switch (info->fix.visual) {
771 case FB_VISUAL_PSEUDOCOLOR:
772 rgbcol = (((u32)red & 0xff00) << 8) |
773 (((u32)green & 0xff00) << 0) |
774 (((u32)blue & 0xff00) >> 8);
775 do_setpalentry(par, regno, rgbcol);
776 break;
777 /* Truecolor has no hardware color palettes. */
778 case FB_VISUAL_TRUECOLOR:
779 if (regno < 16) {
780 rgbcol = (CNVT_TOHW(red, info->var.red.length) <<
781 info->var.red.offset) |
782 (CNVT_TOHW(green, info->var.green.length) <<
783 info->var.green.offset) |
784 (CNVT_TOHW(blue, info->var.blue.length) <<
785 info->var.blue.offset) |
786 (CNVT_TOHW(transp, info->var.transp.length) <<
787 info->var.transp.offset);
788 par->palette[regno] = rgbcol;
789 }
790
791 break;
792 default:
793 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
794 break;
795 }
796
797 return 0;
798 }
799
800 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
801 static int tdfxfb_blank(int blank, struct fb_info *info)
802 {
803 struct tdfx_par *par = info->par;
804 int vgablank = 1;
805 u32 dacmode = tdfx_inl(par, DACMODE);
806
807 dacmode &= ~(BIT(1) | BIT(3));
808
809 switch (blank) {
810 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
811 vgablank = 0;
812 break;
813 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
814 break;
815 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
816 dacmode |= BIT(3);
817 break;
818 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
819 dacmode |= BIT(1);
820 break;
821 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
822 dacmode |= BIT(1) | BIT(3);
823 break;
824 }
825
826 banshee_make_room(par, 1);
827 tdfx_outl(par, DACMODE, dacmode);
828 if (vgablank)
829 vga_disable_video(par);
830 else
831 vga_enable_video(par);
832 return 0;
833 }
834
835 /*
836 * Set the starting position of the visible screen to var->yoffset
837 */
838 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
839 struct fb_info *info)
840 {
841 struct tdfx_par *par = info->par;
842 u32 addr = var->yoffset * info->fix.line_length;
843
844 if (nopan || var->xoffset)
845 return -EINVAL;
846
847 banshee_make_room(par, 1);
848 tdfx_outl(par, VIDDESKSTART, addr);
849
850 return 0;
851 }
852
853 #ifdef CONFIG_FB_3DFX_ACCEL
854 /*
855 * FillRect 2D command (solidfill or invert (via ROP_XOR))
856 */
857 static void tdfxfb_fillrect(struct fb_info *info,
858 const struct fb_fillrect *rect)
859 {
860 struct tdfx_par *par = info->par;
861 u32 bpp = info->var.bits_per_pixel;
862 u32 stride = info->fix.line_length;
863 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
864 int tdfx_rop;
865 u32 dx = rect->dx;
866 u32 dy = rect->dy;
867 u32 dstbase = 0;
868
869 if (rect->rop == ROP_COPY)
870 tdfx_rop = TDFX_ROP_COPY;
871 else
872 tdfx_rop = TDFX_ROP_XOR;
873
874 /* asume always rect->height < 4096 */
875 if (dy + rect->height > 4095) {
876 dstbase = stride * dy;
877 dy = 0;
878 }
879 /* asume always rect->width < 4096 */
880 if (dx + rect->width > 4095) {
881 dstbase += dx * bpp >> 3;
882 dx = 0;
883 }
884 banshee_make_room(par, 6);
885 tdfx_outl(par, DSTFORMAT, fmt);
886 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
887 tdfx_outl(par, COLORFORE, rect->color);
888 } else { /* FB_VISUAL_TRUECOLOR */
889 tdfx_outl(par, COLORFORE, par->palette[rect->color]);
890 }
891 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
892 tdfx_outl(par, DSTBASE, dstbase);
893 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
894 tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
895 }
896
897 /*
898 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
899 */
900 static void tdfxfb_copyarea(struct fb_info *info,
901 const struct fb_copyarea *area)
902 {
903 struct tdfx_par *par = info->par;
904 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
905 u32 bpp = info->var.bits_per_pixel;
906 u32 stride = info->fix.line_length;
907 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
908 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
909 u32 dstbase = 0;
910 u32 srcbase = 0;
911
912 /* asume always area->height < 4096 */
913 if (sy + area->height > 4095) {
914 srcbase = stride * sy;
915 sy = 0;
916 }
917 /* asume always area->width < 4096 */
918 if (sx + area->width > 4095) {
919 srcbase += sx * bpp >> 3;
920 sx = 0;
921 }
922 /* asume always area->height < 4096 */
923 if (dy + area->height > 4095) {
924 dstbase = stride * dy;
925 dy = 0;
926 }
927 /* asume always area->width < 4096 */
928 if (dx + area->width > 4095) {
929 dstbase += dx * bpp >> 3;
930 dx = 0;
931 }
932
933 if (area->sx <= area->dx) {
934 /* -X */
935 blitcmd |= BIT(14);
936 sx += area->width - 1;
937 dx += area->width - 1;
938 }
939 if (area->sy <= area->dy) {
940 /* -Y */
941 blitcmd |= BIT(15);
942 sy += area->height - 1;
943 dy += area->height - 1;
944 }
945
946 banshee_make_room(par, 8);
947
948 tdfx_outl(par, SRCFORMAT, fmt);
949 tdfx_outl(par, DSTFORMAT, fmt);
950 tdfx_outl(par, COMMAND_2D, blitcmd);
951 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
952 tdfx_outl(par, DSTXY, dx | (dy << 16));
953 tdfx_outl(par, SRCBASE, srcbase);
954 tdfx_outl(par, DSTBASE, dstbase);
955 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
956 }
957
958 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
959 {
960 struct tdfx_par *par = info->par;
961 int size = image->height * ((image->width * image->depth + 7) >> 3);
962 int fifo_free;
963 int i, stride = info->fix.line_length;
964 u32 bpp = info->var.bits_per_pixel;
965 u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
966 u8 *chardata = (u8 *) image->data;
967 u32 srcfmt;
968 u32 dx = image->dx;
969 u32 dy = image->dy;
970 u32 dstbase = 0;
971
972 if (image->depth != 1) {
973 #ifdef BROKEN_CODE
974 banshee_make_room(par, 6 + ((size + 3) >> 2));
975 srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) |
976 0x400000;
977 #else
978 cfb_imageblit(info, image);
979 #endif
980 return;
981 }
982 banshee_make_room(par, 9);
983 switch (info->fix.visual) {
984 case FB_VISUAL_PSEUDOCOLOR:
985 tdfx_outl(par, COLORFORE, image->fg_color);
986 tdfx_outl(par, COLORBACK, image->bg_color);
987 break;
988 case FB_VISUAL_TRUECOLOR:
989 default:
990 tdfx_outl(par, COLORFORE,
991 par->palette[image->fg_color]);
992 tdfx_outl(par, COLORBACK,
993 par->palette[image->bg_color]);
994 }
995 #ifdef __BIG_ENDIAN
996 srcfmt = 0x400000 | BIT(20);
997 #else
998 srcfmt = 0x400000;
999 #endif
1000 /* asume always image->height < 4096 */
1001 if (dy + image->height > 4095) {
1002 dstbase = stride * dy;
1003 dy = 0;
1004 }
1005 /* asume always image->width < 4096 */
1006 if (dx + image->width > 4095) {
1007 dstbase += dx * bpp >> 3;
1008 dx = 0;
1009 }
1010
1011 tdfx_outl(par, DSTBASE, dstbase);
1012 tdfx_outl(par, SRCXY, 0);
1013 tdfx_outl(par, DSTXY, dx | (dy << 16));
1014 tdfx_outl(par, COMMAND_2D,
1015 COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
1016 tdfx_outl(par, SRCFORMAT, srcfmt);
1017 tdfx_outl(par, DSTFORMAT, dstfmt);
1018 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
1019
1020 /* A count of how many free FIFO entries we've requested.
1021 * When this goes negative, we need to request more. */
1022 fifo_free = 0;
1023
1024 /* Send four bytes at a time of data */
1025 for (i = (size >> 2); i > 0; i--) {
1026 if (--fifo_free < 0) {
1027 fifo_free = 31;
1028 banshee_make_room(par, fifo_free);
1029 }
1030 tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
1031 chardata += 4;
1032 }
1033
1034 /* Send the leftovers now */
1035 banshee_make_room(par, 3);
1036 switch (size % 4) {
1037 case 0:
1038 break;
1039 case 1:
1040 tdfx_outl(par, LAUNCH_2D, *chardata);
1041 break;
1042 case 2:
1043 tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
1044 break;
1045 case 3:
1046 tdfx_outl(par, LAUNCH_2D,
1047 *(u16 *)chardata | (chardata[3] << 24));
1048 break;
1049 }
1050 }
1051 #endif /* CONFIG_FB_3DFX_ACCEL */
1052
1053 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1054 {
1055 struct tdfx_par *par = info->par;
1056 u32 vidcfg;
1057
1058 if (!hwcursor)
1059 return -EINVAL; /* just to force soft_cursor() call */
1060
1061 /* Too large of a cursor or wrong bpp :-( */
1062 if (cursor->image.width > 64 ||
1063 cursor->image.height > 64 ||
1064 cursor->image.depth > 1)
1065 return -EINVAL;
1066
1067 vidcfg = tdfx_inl(par, VIDPROCCFG);
1068 if (cursor->enable)
1069 tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
1070 else
1071 tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
1072
1073 /*
1074 * If the cursor is not be changed this means either we want the
1075 * current cursor state (if enable is set) or we want to query what
1076 * we can do with the cursor (if enable is not set)
1077 */
1078 if (!cursor->set)
1079 return 0;
1080
1081 /* fix cursor color - XFree86 forgets to restore it properly */
1082 if (cursor->set & FB_CUR_SETCMAP) {
1083 struct fb_cmap cmap = info->cmap;
1084 u32 bg_idx = cursor->image.bg_color;
1085 u32 fg_idx = cursor->image.fg_color;
1086 unsigned long bg_color, fg_color;
1087
1088 fg_color = (((u32)cmap.red[fg_idx] & 0xff00) << 8) |
1089 (((u32)cmap.green[fg_idx] & 0xff00) << 0) |
1090 (((u32)cmap.blue[fg_idx] & 0xff00) >> 8);
1091 bg_color = (((u32)cmap.red[bg_idx] & 0xff00) << 8) |
1092 (((u32)cmap.green[bg_idx] & 0xff00) << 0) |
1093 (((u32)cmap.blue[bg_idx] & 0xff00) >> 8);
1094 banshee_make_room(par, 2);
1095 tdfx_outl(par, HWCURC0, bg_color);
1096 tdfx_outl(par, HWCURC1, fg_color);
1097 }
1098
1099 if (cursor->set & FB_CUR_SETPOS) {
1100 int x = cursor->image.dx;
1101 int y = cursor->image.dy - info->var.yoffset;
1102
1103 x += 63;
1104 y += 63;
1105 banshee_make_room(par, 1);
1106 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1107 }
1108 if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
1109 /*
1110 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1111 * The reason is so the card can fetch 8 words at a time
1112 * and are stored on chip for use for the next 8 scanlines.
1113 * This reduces the number of times for access to draw the
1114 * cursor for each screen refresh.
1115 * Each pattern is a bitmap of 64 bit wide and 64 bit high
1116 * (total of 8192 bits or 1024 bytes). The two patterns are
1117 * stored in such a way that pattern 0 always resides in the
1118 * lower half (least significant 64 bits) of a 128 bit word
1119 * and pattern 1 the upper half. If you examine the data of
1120 * the cursor image the graphics card uses then from the
1121 * begining you see line one of pattern 0, line one of
1122 * pattern 1, line two of pattern 0, line two of pattern 1,
1123 * etc etc. The linear stride for the cursor is always 16 bytes
1124 * (128 bits) which is the maximum cursor width times two for
1125 * the two monochrome patterns.
1126 */
1127 u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len;
1128 u8 *bitmap = (u8 *)cursor->image.data;
1129 u8 *mask = (u8 *)cursor->mask;
1130 int i;
1131
1132 fb_memset(cursorbase, 0, 1024);
1133
1134 for (i = 0; i < cursor->image.height; i++) {
1135 int h = 0;
1136 int j = (cursor->image.width + 7) >> 3;
1137
1138 for (; j > 0; j--) {
1139 u8 data = *mask ^ *bitmap;
1140 if (cursor->rop == ROP_COPY)
1141 data = *mask & *bitmap;
1142 /* Pattern 0. Copy the cursor mask to it */
1143 fb_writeb(*mask, cursorbase + h);
1144 mask++;
1145 /* Pattern 1. Copy the cursor bitmap to it */
1146 fb_writeb(data, cursorbase + h + 8);
1147 bitmap++;
1148 h++;
1149 }
1150 cursorbase += 16;
1151 }
1152 }
1153 return 0;
1154 }
1155
1156 static struct fb_ops tdfxfb_ops = {
1157 .owner = THIS_MODULE,
1158 .fb_check_var = tdfxfb_check_var,
1159 .fb_set_par = tdfxfb_set_par,
1160 .fb_setcolreg = tdfxfb_setcolreg,
1161 .fb_blank = tdfxfb_blank,
1162 .fb_pan_display = tdfxfb_pan_display,
1163 .fb_sync = banshee_wait_idle,
1164 .fb_cursor = tdfxfb_cursor,
1165 #ifdef CONFIG_FB_3DFX_ACCEL
1166 .fb_fillrect = tdfxfb_fillrect,
1167 .fb_copyarea = tdfxfb_copyarea,
1168 .fb_imageblit = tdfxfb_imageblit,
1169 #else
1170 .fb_fillrect = cfb_fillrect,
1171 .fb_copyarea = cfb_copyarea,
1172 .fb_imageblit = cfb_imageblit,
1173 #endif
1174 };
1175
1176 #ifdef CONFIG_FB_3DFX_I2C
1177 /* The voo GPIO registers don't have individual masks for each bit
1178 so we always have to read before writing. */
1179
1180 static void tdfxfb_i2c_setscl(void *data, int val)
1181 {
1182 struct tdfxfb_i2c_chan *chan = data;
1183 struct tdfx_par *par = chan->par;
1184 unsigned int r;
1185
1186 r = tdfx_inl(par, VIDSERPARPORT);
1187 if (val)
1188 r |= I2C_SCL_OUT;
1189 else
1190 r &= ~I2C_SCL_OUT;
1191 tdfx_outl(par, VIDSERPARPORT, r);
1192 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1193 }
1194
1195 static void tdfxfb_i2c_setsda(void *data, int val)
1196 {
1197 struct tdfxfb_i2c_chan *chan = data;
1198 struct tdfx_par *par = chan->par;
1199 unsigned int r;
1200
1201 r = tdfx_inl(par, VIDSERPARPORT);
1202 if (val)
1203 r |= I2C_SDA_OUT;
1204 else
1205 r &= ~I2C_SDA_OUT;
1206 tdfx_outl(par, VIDSERPARPORT, r);
1207 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1208 }
1209
1210 /* The GPIO pins are open drain, so the pins always remain outputs.
1211 We rely on the i2c-algo-bit routines to set the pins high before
1212 reading the input from other chips. */
1213
1214 static int tdfxfb_i2c_getscl(void *data)
1215 {
1216 struct tdfxfb_i2c_chan *chan = data;
1217 struct tdfx_par *par = chan->par;
1218
1219 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
1220 }
1221
1222 static int tdfxfb_i2c_getsda(void *data)
1223 {
1224 struct tdfxfb_i2c_chan *chan = data;
1225 struct tdfx_par *par = chan->par;
1226
1227 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
1228 }
1229
1230 static void tdfxfb_ddc_setscl(void *data, int val)
1231 {
1232 struct tdfxfb_i2c_chan *chan = data;
1233 struct tdfx_par *par = chan->par;
1234 unsigned int r;
1235
1236 r = tdfx_inl(par, VIDSERPARPORT);
1237 if (val)
1238 r |= DDC_SCL_OUT;
1239 else
1240 r &= ~DDC_SCL_OUT;
1241 tdfx_outl(par, VIDSERPARPORT, r);
1242 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1243 }
1244
1245 static void tdfxfb_ddc_setsda(void *data, int val)
1246 {
1247 struct tdfxfb_i2c_chan *chan = data;
1248 struct tdfx_par *par = chan->par;
1249 unsigned int r;
1250
1251 r = tdfx_inl(par, VIDSERPARPORT);
1252 if (val)
1253 r |= DDC_SDA_OUT;
1254 else
1255 r &= ~DDC_SDA_OUT;
1256 tdfx_outl(par, VIDSERPARPORT, r);
1257 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1258 }
1259
1260 static int tdfxfb_ddc_getscl(void *data)
1261 {
1262 struct tdfxfb_i2c_chan *chan = data;
1263 struct tdfx_par *par = chan->par;
1264
1265 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
1266 }
1267
1268 static int tdfxfb_ddc_getsda(void *data)
1269 {
1270 struct tdfxfb_i2c_chan *chan = data;
1271 struct tdfx_par *par = chan->par;
1272
1273 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));
1274 }
1275
1276 static int __devinit tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan,
1277 const char *name, struct device *dev)
1278 {
1279 int rc;
1280
1281 strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name));
1282 chan->adapter.owner = THIS_MODULE;
1283 chan->adapter.class = I2C_CLASS_DDC;
1284 chan->adapter.algo_data = &chan->algo;
1285 chan->adapter.dev.parent = dev;
1286 chan->algo.setsda = tdfxfb_ddc_setsda;
1287 chan->algo.setscl = tdfxfb_ddc_setscl;
1288 chan->algo.getsda = tdfxfb_ddc_getsda;
1289 chan->algo.getscl = tdfxfb_ddc_getscl;
1290 chan->algo.udelay = 10;
1291 chan->algo.timeout = msecs_to_jiffies(500);
1292 chan->algo.data = chan;
1293
1294 i2c_set_adapdata(&chan->adapter, chan);
1295
1296 rc = i2c_bit_add_bus(&chan->adapter);
1297 if (rc == 0)
1298 DPRINTK("I2C bus %s registered.\n", name);
1299 else
1300 chan->par = NULL;
1301
1302 return rc;
1303 }
1304
1305 static int __devinit tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan,
1306 const char *name, struct device *dev)
1307 {
1308 int rc;
1309
1310 strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name));
1311 chan->adapter.owner = THIS_MODULE;
1312 chan->adapter.class = I2C_CLASS_TV_ANALOG;
1313 chan->adapter.algo_data = &chan->algo;
1314 chan->adapter.dev.parent = dev;
1315 chan->algo.setsda = tdfxfb_i2c_setsda;
1316 chan->algo.setscl = tdfxfb_i2c_setscl;
1317 chan->algo.getsda = tdfxfb_i2c_getsda;
1318 chan->algo.getscl = tdfxfb_i2c_getscl;
1319 chan->algo.udelay = 10;
1320 chan->algo.timeout = msecs_to_jiffies(500);
1321 chan->algo.data = chan;
1322
1323 i2c_set_adapdata(&chan->adapter, chan);
1324
1325 rc = i2c_bit_add_bus(&chan->adapter);
1326 if (rc == 0)
1327 DPRINTK("I2C bus %s registered.\n", name);
1328 else
1329 chan->par = NULL;
1330
1331 return rc;
1332 }
1333
1334 static void __devinit tdfxfb_create_i2c_busses(struct fb_info *info)
1335 {
1336 struct tdfx_par *par = info->par;
1337
1338 tdfx_outl(par, VIDINFORMAT, 0x8160);
1339 tdfx_outl(par, VIDSERPARPORT, 0xcffc0020);
1340
1341 par->chan[0].par = par;
1342 par->chan[1].par = par;
1343
1344 tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->dev);
1345 tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->dev);
1346 }
1347
1348 static void tdfxfb_delete_i2c_busses(struct tdfx_par *par)
1349 {
1350 if (par->chan[0].par)
1351 i2c_del_adapter(&par->chan[0].adapter);
1352 par->chan[0].par = NULL;
1353
1354 if (par->chan[1].par)
1355 i2c_del_adapter(&par->chan[1].adapter);
1356 par->chan[1].par = NULL;
1357 }
1358 #endif /* CONFIG_FB_3DFX_I2C */
1359
1360 /**
1361 * tdfxfb_probe - Device Initializiation
1362 *
1363 * @pdev: PCI Device to initialize
1364 * @id: PCI Device ID
1365 *
1366 * Initializes and allocates resources for PCI device @pdev.
1367 *
1368 */
1369 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1370 const struct pci_device_id *id)
1371 {
1372 struct tdfx_par *default_par;
1373 struct fb_info *info;
1374 int err, lpitch;
1375
1376 err = pci_enable_device(pdev);
1377 if (err) {
1378 printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err);
1379 return err;
1380 }
1381
1382 info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
1383
1384 if (!info)
1385 return -ENOMEM;
1386
1387 default_par = info->par;
1388 info->fix = tdfx_fix;
1389
1390 /* Configure the default fb_fix_screeninfo first */
1391 switch (pdev->device) {
1392 case PCI_DEVICE_ID_3DFX_BANSHEE:
1393 strcpy(info->fix.id, "3Dfx Banshee");
1394 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1395 break;
1396 case PCI_DEVICE_ID_3DFX_VOODOO3:
1397 strcpy(info->fix.id, "3Dfx Voodoo3");
1398 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1399 break;
1400 case PCI_DEVICE_ID_3DFX_VOODOO5:
1401 strcpy(info->fix.id, "3Dfx Voodoo5");
1402 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1403 break;
1404 }
1405
1406 info->fix.mmio_start = pci_resource_start(pdev, 0);
1407 info->fix.mmio_len = pci_resource_len(pdev, 0);
1408 if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len,
1409 "tdfx regbase")) {
1410 printk(KERN_ERR "tdfxfb: Can't reserve regbase\n");
1411 goto out_err;
1412 }
1413
1414 default_par->regbase_virt =
1415 ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
1416 if (!default_par->regbase_virt) {
1417 printk(KERN_ERR "fb: Can't remap %s register area.\n",
1418 info->fix.id);
1419 goto out_err_regbase;
1420 }
1421
1422 info->fix.smem_start = pci_resource_start(pdev, 1);
1423 info->fix.smem_len = do_lfb_size(default_par, pdev->device);
1424 if (!info->fix.smem_len) {
1425 printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id);
1426 goto out_err_regbase;
1427 }
1428
1429 if (!request_mem_region(info->fix.smem_start,
1430 pci_resource_len(pdev, 1), "tdfx smem")) {
1431 printk(KERN_ERR "tdfxfb: Can't reserve smem\n");
1432 goto out_err_regbase;
1433 }
1434
1435 info->screen_base = ioremap_nocache(info->fix.smem_start,
1436 info->fix.smem_len);
1437 if (!info->screen_base) {
1438 printk(KERN_ERR "fb: Can't remap %s framebuffer.\n",
1439 info->fix.id);
1440 goto out_err_screenbase;
1441 }
1442
1443 default_par->iobase = pci_resource_start(pdev, 2);
1444
1445 if (!request_region(pci_resource_start(pdev, 2),
1446 pci_resource_len(pdev, 2), "tdfx iobase")) {
1447 printk(KERN_ERR "tdfxfb: Can't reserve iobase\n");
1448 goto out_err_screenbase;
1449 }
1450
1451 printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id,
1452 info->fix.smem_len >> 10);
1453
1454 default_par->mtrr_handle = -1;
1455 if (!nomtrr)
1456 default_par->mtrr_handle =
1457 mtrr_add(info->fix.smem_start, info->fix.smem_len,
1458 MTRR_TYPE_WRCOMB, 1);
1459
1460 info->fix.ypanstep = nopan ? 0 : 1;
1461 info->fix.ywrapstep = nowrap ? 0 : 1;
1462
1463 info->fbops = &tdfxfb_ops;
1464 info->pseudo_palette = default_par->palette;
1465 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1466 #ifdef CONFIG_FB_3DFX_ACCEL
1467 info->flags |= FBINFO_HWACCEL_FILLRECT |
1468 FBINFO_HWACCEL_COPYAREA |
1469 FBINFO_HWACCEL_IMAGEBLIT |
1470 FBINFO_READS_FAST;
1471 #endif
1472 /* reserve 8192 bits for cursor */
1473 /* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */
1474 if (hwcursor)
1475 info->fix.smem_len = (info->fix.smem_len - 1024) &
1476 (PAGE_MASK << 1);
1477 #ifdef CONFIG_FB_3DFX_I2C
1478 tdfxfb_create_i2c_busses(info);
1479 #endif
1480 if (!mode_option)
1481 mode_option = "640x480@60";
1482
1483 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1484 if (!err || err == 4)
1485 info->var = tdfx_var;
1486
1487 /* maximize virtual vertical length */
1488 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1489 info->var.yres_virtual = info->fix.smem_len / lpitch;
1490 if (info->var.yres_virtual < info->var.yres)
1491 goto out_err_iobase;
1492
1493 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1494 printk(KERN_ERR "tdfxfb: Can't allocate color map\n");
1495 goto out_err_iobase;
1496 }
1497
1498 if (register_framebuffer(info) < 0) {
1499 printk(KERN_ERR "tdfxfb: can't register framebuffer\n");
1500 fb_dealloc_cmap(&info->cmap);
1501 goto out_err_iobase;
1502 }
1503 /*
1504 * Our driver data
1505 */
1506 pci_set_drvdata(pdev, info);
1507 return 0;
1508
1509 out_err_iobase:
1510 #ifdef CONFIG_FB_3DFX_I2C
1511 tdfxfb_delete_i2c_busses(default_par);
1512 #endif
1513 if (default_par->mtrr_handle >= 0)
1514 mtrr_del(default_par->mtrr_handle, info->fix.smem_start,
1515 info->fix.smem_len);
1516 release_mem_region(pci_resource_start(pdev, 2),
1517 pci_resource_len(pdev, 2));
1518 out_err_screenbase:
1519 if (info->screen_base)
1520 iounmap(info->screen_base);
1521 release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1));
1522 out_err_regbase:
1523 /*
1524 * Cleanup after anything that was remapped/allocated.
1525 */
1526 if (default_par->regbase_virt)
1527 iounmap(default_par->regbase_virt);
1528 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1529 out_err:
1530 framebuffer_release(info);
1531 return -ENXIO;
1532 }
1533
1534 #ifndef MODULE
1535 static void __init tdfxfb_setup(char *options)
1536 {
1537 char *this_opt;
1538
1539 if (!options || !*options)
1540 return;
1541
1542 while ((this_opt = strsep(&options, ",")) != NULL) {
1543 if (!*this_opt)
1544 continue;
1545 if (!strcmp(this_opt, "nopan")) {
1546 nopan = 1;
1547 } else if (!strcmp(this_opt, "nowrap")) {
1548 nowrap = 1;
1549 } else if (!strncmp(this_opt, "hwcursor=", 9)) {
1550 hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1551 #ifdef CONFIG_MTRR
1552 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1553 nomtrr = 1;
1554 #endif
1555 } else {
1556 mode_option = this_opt;
1557 }
1558 }
1559 }
1560 #endif
1561
1562 /**
1563 * tdfxfb_remove - Device removal
1564 *
1565 * @pdev: PCI Device to cleanup
1566 *
1567 * Releases all resources allocated during the course of the driver's
1568 * lifetime for the PCI device @pdev.
1569 *
1570 */
1571 static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1572 {
1573 struct fb_info *info = pci_get_drvdata(pdev);
1574 struct tdfx_par *par = info->par;
1575
1576 unregister_framebuffer(info);
1577 #ifdef CONFIG_FB_3DFX_I2C
1578 tdfxfb_delete_i2c_busses(par);
1579 #endif
1580 if (par->mtrr_handle >= 0)
1581 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1582 info->fix.smem_len);
1583 iounmap(par->regbase_virt);
1584 iounmap(info->screen_base);
1585
1586 /* Clean up after reserved regions */
1587 release_region(pci_resource_start(pdev, 2),
1588 pci_resource_len(pdev, 2));
1589 release_mem_region(pci_resource_start(pdev, 1),
1590 pci_resource_len(pdev, 1));
1591 release_mem_region(pci_resource_start(pdev, 0),
1592 pci_resource_len(pdev, 0));
1593 pci_set_drvdata(pdev, NULL);
1594 fb_dealloc_cmap(&info->cmap);
1595 framebuffer_release(info);
1596 }
1597
1598 static int __init tdfxfb_init(void)
1599 {
1600 #ifndef MODULE
1601 char *option = NULL;
1602
1603 if (fb_get_options("tdfxfb", &option))
1604 return -ENODEV;
1605
1606 tdfxfb_setup(option);
1607 #endif
1608 return pci_register_driver(&tdfxfb_driver);
1609 }
1610
1611 static void __exit tdfxfb_exit(void)
1612 {
1613 pci_unregister_driver(&tdfxfb_driver);
1614 }
1615
1616 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1617 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1618 MODULE_LICENSE("GPL");
1619
1620 module_param(hwcursor, int, 0644);
1621 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1622 "(1=enable, 0=disable, default=1)");
1623 module_param(mode_option, charp, 0);
1624 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1625 #ifdef CONFIG_MTRR
1626 module_param(nomtrr, bool, 0);
1627 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)");
1628 #endif
1629
1630 module_init(tdfxfb_init);
1631 module_exit(tdfxfb_exit);
Linux kernel - Deliverables
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