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[PATCH] tgafb: Fix the PCI ID table
[deliverable/linux.git] / drivers / video / tgafb.c
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/fb.h>
24 #include <linux/pci.h>
25 #include <linux/selection.h>
26 #include <linux/bitrev.h>
27 #include <asm/io.h>
28 #include <video/tgafb.h>
29
30 /*
31 * Local functions.
32 */
33
34 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
35 static int tgafb_set_par(struct fb_info *);
36 static void tgafb_set_pll(struct tga_par *, int);
37 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
38 unsigned, struct fb_info *);
39 static int tgafb_blank(int, struct fb_info *);
40 static void tgafb_init_fix(struct fb_info *);
41
42 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
43 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
44 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
45
46 static int __devinit tgafb_pci_register(struct pci_dev *,
47 const struct pci_device_id *);
48 static void __devexit tgafb_pci_unregister(struct pci_dev *);
49
50 static const char *mode_option = "640x480@60";
51
52
53 /*
54 * Frame buffer operations
55 */
56
57 static struct fb_ops tgafb_ops = {
58 .owner = THIS_MODULE,
59 .fb_check_var = tgafb_check_var,
60 .fb_set_par = tgafb_set_par,
61 .fb_setcolreg = tgafb_setcolreg,
62 .fb_blank = tgafb_blank,
63 .fb_fillrect = tgafb_fillrect,
64 .fb_copyarea = tgafb_copyarea,
65 .fb_imageblit = tgafb_imageblit,
66 };
67
68
69 /*
70 * PCI registration operations
71 */
72
73 static struct pci_device_id const tgafb_pci_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) },
75 { }
76 };
77 MODULE_DEVICE_TABLE(pci, tgafb_pci_table);
78
79 static struct pci_driver tgafb_driver = {
80 .name = "tgafb",
81 .id_table = tgafb_pci_table,
82 .probe = tgafb_pci_register,
83 .remove = __devexit_p(tgafb_pci_unregister),
84 };
85
86
87 /**
88 * tgafb_check_var - Optional function. Validates a var passed in.
89 * @var: frame buffer variable screen structure
90 * @info: frame buffer structure that represents a single frame buffer
91 */
92 static int
93 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
94 {
95 struct tga_par *par = (struct tga_par *)info->par;
96
97 if (par->tga_type == TGA_TYPE_8PLANE) {
98 if (var->bits_per_pixel != 8)
99 return -EINVAL;
100 } else {
101 if (var->bits_per_pixel != 32)
102 return -EINVAL;
103 }
104 var->red.length = var->green.length = var->blue.length = 8;
105 if (var->bits_per_pixel == 32) {
106 var->red.offset = 16;
107 var->green.offset = 8;
108 var->blue.offset = 0;
109 }
110
111 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
112 return -EINVAL;
113 if (var->nonstd)
114 return -EINVAL;
115 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
116 return -EINVAL;
117 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
118 return -EINVAL;
119
120 /* Some of the acceleration routines assume the line width is
121 a multiple of 64 bytes. */
122 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
123 return -EINVAL;
124
125 return 0;
126 }
127
128 /**
129 * tgafb_set_par - Optional function. Alters the hardware state.
130 * @info: frame buffer structure that represents a single frame buffer
131 */
132 static int
133 tgafb_set_par(struct fb_info *info)
134 {
135 static unsigned int const deep_presets[4] = {
136 0x00014000,
137 0x0001440d,
138 0xffffffff,
139 0x0001441d
140 };
141 static unsigned int const rasterop_presets[4] = {
142 0x00000003,
143 0x00000303,
144 0xffffffff,
145 0x00000303
146 };
147 static unsigned int const mode_presets[4] = {
148 0x00000000,
149 0x00000300,
150 0xffffffff,
151 0x00000300
152 };
153 static unsigned int const base_addr_presets[4] = {
154 0x00000000,
155 0x00000001,
156 0xffffffff,
157 0x00000001
158 };
159
160 struct tga_par *par = (struct tga_par *) info->par;
161 u32 htimings, vtimings, pll_freq;
162 u8 tga_type;
163 int i;
164
165 /* Encode video timings. */
166 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
167 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
168 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
169 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
170 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
171 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
172 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
173 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
174 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
175
176 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
177 htimings |= TGA_HORIZ_POLARITY;
178 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
179 vtimings |= TGA_VERT_POLARITY;
180
181 par->htimings = htimings;
182 par->vtimings = vtimings;
183
184 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
185
186 /* Store other useful values in par. */
187 par->xres = info->var.xres;
188 par->yres = info->var.yres;
189 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
190 par->bits_per_pixel = info->var.bits_per_pixel;
191
192 tga_type = par->tga_type;
193
194 /* First, disable video. */
195 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
196
197 /* Write the DEEP register. */
198 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
199 continue;
200 mb();
201 TGA_WRITE_REG(par, deep_presets[tga_type] |
202 (par->sync_on_green ? 0x0 : 0x00010000),
203 TGA_DEEP_REG);
204 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
205 continue;
206 mb();
207
208 /* Write some more registers. */
209 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
210 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
211 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
212
213 /* Calculate & write the PLL. */
214 tgafb_set_pll(par, pll_freq);
215
216 /* Write some more registers. */
217 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
218 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
219
220 /* Init video timing regs. */
221 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
222 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
223
224 /* Initalise RAMDAC. */
225 if (tga_type == TGA_TYPE_8PLANE) {
226
227 /* Init BT485 RAMDAC registers. */
228 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
229 BT485_CMD_0);
230 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
231 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
232 BT485_WRITE(par, 0x40, BT485_CMD_1);
233 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
234 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
235
236 /* Fill palette registers. */
237 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
238 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
239
240 #ifdef CONFIG_HW_CONSOLE
241 for (i = 0; i < 16; i++) {
242 int j = color_table[i];
243
244 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
245 TGA_RAMDAC_REG);
246 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
247 TGA_RAMDAC_REG);
248 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
249 TGA_RAMDAC_REG);
250 }
251 for (i = 0; i < 240 * 3; i += 4) {
252 #else
253 for (i = 0; i < 256 * 3; i += 4) {
254 #endif
255 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
256 TGA_RAMDAC_REG);
257 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
258 TGA_RAMDAC_REG);
259 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
260 TGA_RAMDAC_REG);
261 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
262 TGA_RAMDAC_REG);
263 }
264
265 } else { /* 24-plane or 24plusZ */
266
267 /* Init BT463 RAMDAC registers. */
268 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
269 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
270 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
271 (par->sync_on_green ? 0xc0 : 0x40));
272
273 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
274 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
275 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
276 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
277
278 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
279 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
280 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
281 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
282
283 /* Fill the palette. */
284 BT463_LOAD_ADDR(par, 0x0000);
285 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
286
287 #ifdef CONFIG_HW_CONSOLE
288 for (i = 0; i < 16; i++) {
289 int j = color_table[i];
290
291 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
292 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
293 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
294 }
295 for (i = 0; i < 512 * 3; i += 4) {
296 #else
297 for (i = 0; i < 528 * 3; i += 4) {
298 #endif
299 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
300 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
301 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
302 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
303 }
304
305 /* Fill window type table after start of vertical retrace. */
306 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
307 continue;
308 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
309 mb();
310 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
311 continue;
312 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
313
314 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
315 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
316
317 for (i = 0; i < 16; i++) {
318 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
319 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
320 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
321 }
322
323 }
324
325 /* Finally, enable video scan (and pray for the monitor... :-) */
326 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
327
328 return 0;
329 }
330
331 #define DIFFCHECK(X) \
332 do { \
333 if (m <= 0x3f) { \
334 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
335 if (delta < 0) \
336 delta = -delta; \
337 if (delta < min_diff) \
338 min_diff = delta, vm = m, va = a, vr = r; \
339 } \
340 } while (0)
341
342 static void
343 tgafb_set_pll(struct tga_par *par, int f)
344 {
345 int n, shift, base, min_diff, target;
346 int r,a,m,vm = 34, va = 1, vr = 30;
347
348 for (r = 0 ; r < 12 ; r++)
349 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
350
351 if (f > TGA_PLL_MAX_FREQ)
352 f = TGA_PLL_MAX_FREQ;
353
354 if (f >= TGA_PLL_MAX_FREQ / 2)
355 shift = 0;
356 else if (f >= TGA_PLL_MAX_FREQ / 4)
357 shift = 1;
358 else
359 shift = 2;
360
361 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
362 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
363
364 for (r = 0 ; r < 10 ; r++)
365 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
366
367 if (f <= 120000) {
368 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
369 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
370 }
371 else if (f <= 200000) {
372 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
373 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
374 }
375 else {
376 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
377 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
378 }
379
380 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
381 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
382 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
383 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
384 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
385 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
386
387 target = (f << shift) / TGA_PLL_BASE_FREQ;
388 min_diff = TGA_PLL_MAX_FREQ;
389
390 r = 7 / target;
391 if (!r) r = 1;
392
393 base = target * r;
394 while (base < 449) {
395 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
396 m = ((n + 3) / 7) - 1;
397 a = 0;
398 DIFFCHECK((m + 1) * 7);
399 m++;
400 DIFFCHECK((m + 1) * 7);
401 m = (n / 6) - 1;
402 if ((a = n % 6))
403 DIFFCHECK(n);
404 }
405 r++;
406 base += target;
407 }
408
409 vr--;
410
411 for (r = 0; r < 8; r++)
412 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
413 for (r = 0; r < 8 ; r++)
414 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
415 for (r = 0; r < 7 ; r++)
416 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
417 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
418 }
419
420
421 /**
422 * tgafb_setcolreg - Optional function. Sets a color register.
423 * @regno: boolean, 0 copy local, 1 get_user() function
424 * @red: frame buffer colormap structure
425 * @green: The green value which can be up to 16 bits wide
426 * @blue: The blue value which can be up to 16 bits wide.
427 * @transp: If supported the alpha value which can be up to 16 bits wide.
428 * @info: frame buffer info structure
429 */
430 static int
431 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
432 unsigned transp, struct fb_info *info)
433 {
434 struct tga_par *par = (struct tga_par *) info->par;
435
436 if (regno > 255)
437 return 1;
438 red >>= 8;
439 green >>= 8;
440 blue >>= 8;
441
442 if (par->tga_type == TGA_TYPE_8PLANE) {
443 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
444 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
445 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
446 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
447 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
448 } else {
449 if (regno < 16) {
450 u32 value = (regno << 16) | (regno << 8) | regno;
451 ((u32 *)info->pseudo_palette)[regno] = value;
452 }
453 BT463_LOAD_ADDR(par, regno);
454 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
455 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
456 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
457 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
458 }
459
460 return 0;
461 }
462
463
464 /**
465 * tgafb_blank - Optional function. Blanks the display.
466 * @blank_mode: the blank mode we want.
467 * @info: frame buffer structure that represents a single frame buffer
468 */
469 static int
470 tgafb_blank(int blank, struct fb_info *info)
471 {
472 struct tga_par *par = (struct tga_par *) info->par;
473 u32 vhcr, vvcr, vvvr;
474 unsigned long flags;
475
476 local_irq_save(flags);
477
478 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
479 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
480 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
481 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
482
483 switch (blank) {
484 case FB_BLANK_UNBLANK: /* Unblanking */
485 if (par->vesa_blanked) {
486 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
487 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
488 par->vesa_blanked = 0;
489 }
490 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
491 break;
492
493 case FB_BLANK_NORMAL: /* Normal blanking */
494 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
495 TGA_VALID_REG);
496 break;
497
498 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
499 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
500 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
501 par->vesa_blanked = 1;
502 break;
503
504 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
505 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
506 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
507 par->vesa_blanked = 1;
508 break;
509
510 case FB_BLANK_POWERDOWN: /* Poweroff */
511 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
512 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
513 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
514 par->vesa_blanked = 1;
515 break;
516 }
517
518 local_irq_restore(flags);
519 return 0;
520 }
521
522
523 /*
524 * Acceleration.
525 */
526
527 /**
528 * tgafb_imageblit - REQUIRED function. Can use generic routines if
529 * non acclerated hardware and packed pixel based.
530 * Copies a image from system memory to the screen.
531 *
532 * @info: frame buffer structure that represents a single frame buffer
533 * @image: structure defining the image.
534 */
535 static void
536 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
537 {
538 struct tga_par *par = (struct tga_par *) info->par;
539 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
540 unsigned long rincr, line_length, shift, pos, is8bpp;
541 unsigned long i, j;
542 const unsigned char *data;
543 void __iomem *regs_base;
544 void __iomem *fb_base;
545
546 dx = image->dx;
547 dy = image->dy;
548 width = image->width;
549 height = image->height;
550 vxres = info->var.xres_virtual;
551 vyres = info->var.yres_virtual;
552 line_length = info->fix.line_length;
553 rincr = (width + 7) / 8;
554
555 /* Crop the image to the screen. */
556 if (dx > vxres || dy > vyres)
557 return;
558 if (dx + width > vxres)
559 width = vxres - dx;
560 if (dy + height > vyres)
561 height = vyres - dy;
562
563 /* For copies that aren't pixel expansion, there's little we
564 can do better than the generic code. */
565 /* ??? There is a DMA write mode; I wonder if that could be
566 made to pull the data from the image buffer... */
567 if (image->depth > 1) {
568 cfb_imageblit(info, image);
569 return;
570 }
571
572 regs_base = par->tga_regs_base;
573 fb_base = par->tga_fb_base;
574 is8bpp = info->var.bits_per_pixel == 8;
575
576 /* Expand the color values to fill 32-bits. */
577 /* ??? Would be nice to notice colour changes elsewhere, so
578 that we can do this only when necessary. */
579 fgcolor = image->fg_color;
580 bgcolor = image->bg_color;
581 if (is8bpp) {
582 fgcolor |= fgcolor << 8;
583 fgcolor |= fgcolor << 16;
584 bgcolor |= bgcolor << 8;
585 bgcolor |= bgcolor << 16;
586 } else {
587 if (fgcolor < 16)
588 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
589 if (bgcolor < 16)
590 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
591 }
592 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
593 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
594
595 /* Acquire proper alignment; set up the PIXELMASK register
596 so that we only write the proper character cell. */
597 pos = dy * line_length;
598 if (is8bpp) {
599 pos += dx;
600 shift = pos & 3;
601 pos &= -4;
602 } else {
603 pos += dx * 4;
604 shift = (pos & 7) >> 2;
605 pos &= -8;
606 }
607
608 data = (const unsigned char *) image->data;
609
610 /* Enable opaque stipple mode. */
611 __raw_writel((is8bpp
612 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
613 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
614 regs_base + TGA_MODE_REG);
615
616 if (width + shift <= 32) {
617 unsigned long bwidth;
618
619 /* Handle common case of imaging a single character, in
620 a font less than 32 pixels wide. */
621
622 pixelmask = (1 << width) - 1;
623 pixelmask <<= shift;
624 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
625 wmb();
626
627 bwidth = (width + 7) / 8;
628
629 for (i = 0; i < height; ++i) {
630 u32 mask = 0;
631
632 /* The image data is bit big endian; we need
633 little endian. */
634 for (j = 0; j < bwidth; ++j)
635 mask |= bitrev8(data[j]) << (j * 8);
636
637 __raw_writel(mask << shift, fb_base + pos);
638
639 pos += line_length;
640 data += rincr;
641 }
642 wmb();
643 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
644 } else if (shift == 0) {
645 unsigned long pos0 = pos;
646 const unsigned char *data0 = data;
647 unsigned long bincr = (is8bpp ? 8 : 8*4);
648 unsigned long bwidth;
649
650 /* Handle another common case in which accel_putcs
651 generates a large bitmap, which happens to be aligned.
652 Allow the tail to be misaligned. This case is
653 interesting because we've not got to hold partial
654 bytes across the words being written. */
655
656 wmb();
657
658 bwidth = (width / 8) & -4;
659 for (i = 0; i < height; ++i) {
660 for (j = 0; j < bwidth; j += 4) {
661 u32 mask = 0;
662 mask |= bitrev8(data[j+0]) << (0 * 8);
663 mask |= bitrev8(data[j+1]) << (1 * 8);
664 mask |= bitrev8(data[j+2]) << (2 * 8);
665 mask |= bitrev8(data[j+3]) << (3 * 8);
666 __raw_writel(mask, fb_base + pos + j*bincr);
667 }
668 pos += line_length;
669 data += rincr;
670 }
671 wmb();
672
673 pixelmask = (1ul << (width & 31)) - 1;
674 if (pixelmask) {
675 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
676 wmb();
677
678 pos = pos0 + bwidth*bincr;
679 data = data0 + bwidth;
680 bwidth = ((width & 31) + 7) / 8;
681
682 for (i = 0; i < height; ++i) {
683 u32 mask = 0;
684 for (j = 0; j < bwidth; ++j)
685 mask |= bitrev8(data[j]) << (j * 8);
686 __raw_writel(mask, fb_base + pos);
687 pos += line_length;
688 data += rincr;
689 }
690 wmb();
691 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
692 }
693 } else {
694 unsigned long pos0 = pos;
695 const unsigned char *data0 = data;
696 unsigned long bincr = (is8bpp ? 8 : 8*4);
697 unsigned long bwidth;
698
699 /* Finally, handle the generic case of misaligned start.
700 Here we split the write into 16-bit spans. This allows
701 us to use only one pixel mask, instead of four as would
702 be required by writing 24-bit spans. */
703
704 pixelmask = 0xffff << shift;
705 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
706 wmb();
707
708 bwidth = (width / 8) & -2;
709 for (i = 0; i < height; ++i) {
710 for (j = 0; j < bwidth; j += 2) {
711 u32 mask = 0;
712 mask |= bitrev8(data[j+0]) << (0 * 8);
713 mask |= bitrev8(data[j+1]) << (1 * 8);
714 mask <<= shift;
715 __raw_writel(mask, fb_base + pos + j*bincr);
716 }
717 pos += line_length;
718 data += rincr;
719 }
720 wmb();
721
722 pixelmask = ((1ul << (width & 15)) - 1) << shift;
723 if (pixelmask) {
724 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
725 wmb();
726
727 pos = pos0 + bwidth*bincr;
728 data = data0 + bwidth;
729 bwidth = (width & 15) > 8;
730
731 for (i = 0; i < height; ++i) {
732 u32 mask = bitrev8(data[0]);
733 if (bwidth)
734 mask |= bitrev8(data[1]) << 8;
735 mask <<= shift;
736 __raw_writel(mask, fb_base + pos);
737 pos += line_length;
738 data += rincr;
739 }
740 wmb();
741 }
742 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
743 }
744
745 /* Disable opaque stipple mode. */
746 __raw_writel((is8bpp
747 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
748 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
749 regs_base + TGA_MODE_REG);
750 }
751
752 /**
753 * tgafb_fillrect - REQUIRED function. Can use generic routines if
754 * non acclerated hardware and packed pixel based.
755 * Draws a rectangle on the screen.
756 *
757 * @info: frame buffer structure that represents a single frame buffer
758 * @rect: structure defining the rectagle and operation.
759 */
760 static void
761 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
762 {
763 struct tga_par *par = (struct tga_par *) info->par;
764 int is8bpp = info->var.bits_per_pixel == 8;
765 u32 dx, dy, width, height, vxres, vyres, color;
766 unsigned long pos, align, line_length, i, j;
767 void __iomem *regs_base;
768 void __iomem *fb_base;
769
770 dx = rect->dx;
771 dy = rect->dy;
772 width = rect->width;
773 height = rect->height;
774 vxres = info->var.xres_virtual;
775 vyres = info->var.yres_virtual;
776 line_length = info->fix.line_length;
777 regs_base = par->tga_regs_base;
778 fb_base = par->tga_fb_base;
779
780 /* Crop the rectangle to the screen. */
781 if (dx > vxres || dy > vyres || !width || !height)
782 return;
783 if (dx + width > vxres)
784 width = vxres - dx;
785 if (dy + height > vyres)
786 height = vyres - dy;
787
788 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
789
790 /* ??? We could implement ROP_XOR with opaque fill mode
791 and a RasterOp setting of GXxor, but as far as I can
792 tell, this mode is not actually used in the kernel.
793 Thus I am ignoring it for now. */
794 if (rect->rop != ROP_COPY) {
795 cfb_fillrect(info, rect);
796 return;
797 }
798
799 /* Expand the color value to fill 8 pixels. */
800 color = rect->color;
801 if (is8bpp) {
802 color |= color << 8;
803 color |= color << 16;
804 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
805 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
806 } else {
807 if (color < 16)
808 color = ((u32 *)info->pseudo_palette)[color];
809 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
810 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
811 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
812 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
813 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
814 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
815 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
816 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
817 }
818
819 /* The DATA register holds the fill mask for block fill mode.
820 Since we're not stippling, this is all ones. */
821 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
822
823 /* Enable block fill mode. */
824 __raw_writel((is8bpp
825 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
826 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
827 regs_base + TGA_MODE_REG);
828 wmb();
829
830 /* We can fill 2k pixels per operation. Notice blocks that fit
831 the width of the screen so that we can take advantage of this
832 and fill more than one line per write. */
833 if (width == line_length)
834 width *= height, height = 1;
835
836 /* The write into the frame buffer must be aligned to 4 bytes,
837 but we are allowed to encode the offset within the word in
838 the data word written. */
839 align = (pos & 3) << 16;
840 pos &= -4;
841
842 if (width <= 2048) {
843 u32 data;
844
845 data = (width - 1) | align;
846
847 for (i = 0; i < height; ++i) {
848 __raw_writel(data, fb_base + pos);
849 pos += line_length;
850 }
851 } else {
852 unsigned long Bpp = (is8bpp ? 1 : 4);
853 unsigned long nwidth = width & -2048;
854 u32 fdata, ldata;
855
856 fdata = (2048 - 1) | align;
857 ldata = ((width & 2047) - 1) | align;
858
859 for (i = 0; i < height; ++i) {
860 for (j = 0; j < nwidth; j += 2048)
861 __raw_writel(fdata, fb_base + pos + j*Bpp);
862 if (j < width)
863 __raw_writel(ldata, fb_base + pos + j*Bpp);
864 pos += line_length;
865 }
866 }
867 wmb();
868
869 /* Disable block fill mode. */
870 __raw_writel((is8bpp
871 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
872 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
873 regs_base + TGA_MODE_REG);
874 }
875
876 /**
877 * tgafb_copyarea - REQUIRED function. Can use generic routines if
878 * non acclerated hardware and packed pixel based.
879 * Copies on area of the screen to another area.
880 *
881 * @info: frame buffer structure that represents a single frame buffer
882 * @area: structure defining the source and destination.
883 */
884
885 /* Handle the special case of copying entire lines, e.g. during scrolling.
886 We can avoid a lot of needless computation in this case. In the 8bpp
887 case we need to use the COPY64 registers instead of mask writes into
888 the frame buffer to achieve maximum performance. */
889
890 static inline void
891 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
892 u32 height, u32 width)
893 {
894 struct tga_par *par = (struct tga_par *) info->par;
895 void __iomem *tga_regs = par->tga_regs_base;
896 unsigned long dpos, spos, i, n64;
897
898 /* Set up the MODE and PIXELSHIFT registers. */
899 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
900 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
901 wmb();
902
903 n64 = (height * width) / 64;
904
905 if (sy < dy) {
906 spos = (sy + height) * width;
907 dpos = (dy + height) * width;
908
909 for (i = 0; i < n64; ++i) {
910 spos -= 64;
911 dpos -= 64;
912 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
913 wmb();
914 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
915 wmb();
916 }
917 } else {
918 spos = sy * width;
919 dpos = dy * width;
920
921 for (i = 0; i < n64; ++i) {
922 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
923 wmb();
924 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
925 wmb();
926 spos += 64;
927 dpos += 64;
928 }
929 }
930
931 /* Reset the MODE register to normal. */
932 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
933 }
934
935 static inline void
936 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
937 u32 height, u32 width)
938 {
939 struct tga_par *par = (struct tga_par *) info->par;
940 void __iomem *tga_regs = par->tga_regs_base;
941 void __iomem *tga_fb = par->tga_fb_base;
942 void __iomem *src;
943 void __iomem *dst;
944 unsigned long i, n16;
945
946 /* Set up the MODE and PIXELSHIFT registers. */
947 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
948 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
949 wmb();
950
951 n16 = (height * width) / 16;
952
953 if (sy < dy) {
954 src = tga_fb + (sy + height) * width * 4;
955 dst = tga_fb + (dy + height) * width * 4;
956
957 for (i = 0; i < n16; ++i) {
958 src -= 64;
959 dst -= 64;
960 __raw_writel(0xffff, src);
961 wmb();
962 __raw_writel(0xffff, dst);
963 wmb();
964 }
965 } else {
966 src = tga_fb + sy * width * 4;
967 dst = tga_fb + dy * width * 4;
968
969 for (i = 0; i < n16; ++i) {
970 __raw_writel(0xffff, src);
971 wmb();
972 __raw_writel(0xffff, dst);
973 wmb();
974 src += 64;
975 dst += 64;
976 }
977 }
978
979 /* Reset the MODE register to normal. */
980 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
981 }
982
983 /* The general case of forward copy in 8bpp mode. */
984 static inline void
985 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
986 u32 height, u32 width, u32 line_length)
987 {
988 struct tga_par *par = (struct tga_par *) info->par;
989 unsigned long i, copied, left;
990 unsigned long dpos, spos, dalign, salign, yincr;
991 u32 smask_first, dmask_first, dmask_last;
992 int pixel_shift, need_prime, need_second;
993 unsigned long n64, n32, xincr_first;
994 void __iomem *tga_regs;
995 void __iomem *tga_fb;
996
997 yincr = line_length;
998 if (dy > sy) {
999 dy += height - 1;
1000 sy += height - 1;
1001 yincr = -yincr;
1002 }
1003
1004 /* Compute the offsets and alignments in the frame buffer.
1005 More than anything else, these control how we do copies. */
1006 dpos = dy * line_length + dx;
1007 spos = sy * line_length + sx;
1008 dalign = dpos & 7;
1009 salign = spos & 7;
1010 dpos &= -8;
1011 spos &= -8;
1012
1013 /* Compute the value for the PIXELSHIFT register. This controls
1014 both non-co-aligned source and destination and copy direction. */
1015 if (dalign >= salign)
1016 pixel_shift = dalign - salign;
1017 else
1018 pixel_shift = 8 - (salign - dalign);
1019
1020 /* Figure out if we need an additional priming step for the
1021 residue register. */
1022 need_prime = (salign > dalign);
1023 if (need_prime)
1024 dpos -= 8;
1025
1026 /* Begin by copying the leading unaligned destination. Copy enough
1027 to make the next destination address 32-byte aligned. */
1028 copied = 32 - (dalign + (dpos & 31));
1029 if (copied == 32)
1030 copied = 0;
1031 xincr_first = (copied + 7) & -8;
1032 smask_first = dmask_first = (1ul << copied) - 1;
1033 smask_first <<= salign;
1034 dmask_first <<= dalign + need_prime*8;
1035 if (need_prime && copied > 24)
1036 copied -= 8;
1037 left = width - copied;
1038
1039 /* Care for small copies. */
1040 if (copied > width) {
1041 u32 t;
1042 t = (1ul << width) - 1;
1043 t <<= dalign + need_prime*8;
1044 dmask_first &= t;
1045 left = 0;
1046 }
1047
1048 /* Attempt to use 64-byte copies. This is only possible if the
1049 source and destination are co-aligned at 64 bytes. */
1050 n64 = need_second = 0;
1051 if ((dpos & 63) == (spos & 63)
1052 && (height == 1 || line_length % 64 == 0)) {
1053 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1054 need_second = (dpos + xincr_first) & 63;
1055 if ((need_second & 32) != need_second)
1056 printk(KERN_ERR "tgafb: need_second wrong\n");
1057 if (left >= need_second + 64) {
1058 left -= need_second;
1059 n64 = left / 64;
1060 left %= 64;
1061 } else
1062 need_second = 0;
1063 }
1064
1065 /* Copy trailing full 32-byte sections. This will be the main
1066 loop if the 64 byte loop can't be used. */
1067 n32 = left / 32;
1068 left %= 32;
1069
1070 /* Copy the trailing unaligned destination. */
1071 dmask_last = (1ul << left) - 1;
1072
1073 tga_regs = par->tga_regs_base;
1074 tga_fb = par->tga_fb_base;
1075
1076 /* Set up the MODE and PIXELSHIFT registers. */
1077 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1078 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1079 wmb();
1080
1081 for (i = 0; i < height; ++i) {
1082 unsigned long j;
1083 void __iomem *sfb;
1084 void __iomem *dfb;
1085
1086 sfb = tga_fb + spos;
1087 dfb = tga_fb + dpos;
1088 if (dmask_first) {
1089 __raw_writel(smask_first, sfb);
1090 wmb();
1091 __raw_writel(dmask_first, dfb);
1092 wmb();
1093 sfb += xincr_first;
1094 dfb += xincr_first;
1095 }
1096
1097 if (need_second) {
1098 __raw_writel(0xffffffff, sfb);
1099 wmb();
1100 __raw_writel(0xffffffff, dfb);
1101 wmb();
1102 sfb += 32;
1103 dfb += 32;
1104 }
1105
1106 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1107 printk(KERN_ERR
1108 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1109 sfb, dfb);
1110
1111 for (j = 0; j < n64; ++j) {
1112 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1113 wmb();
1114 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1115 wmb();
1116 sfb += 64;
1117 dfb += 64;
1118 }
1119
1120 for (j = 0; j < n32; ++j) {
1121 __raw_writel(0xffffffff, sfb);
1122 wmb();
1123 __raw_writel(0xffffffff, dfb);
1124 wmb();
1125 sfb += 32;
1126 dfb += 32;
1127 }
1128
1129 if (dmask_last) {
1130 __raw_writel(0xffffffff, sfb);
1131 wmb();
1132 __raw_writel(dmask_last, dfb);
1133 wmb();
1134 }
1135
1136 spos += yincr;
1137 dpos += yincr;
1138 }
1139
1140 /* Reset the MODE register to normal. */
1141 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1142 }
1143
1144 /* The (almost) general case of backward copy in 8bpp mode. */
1145 static inline void
1146 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1147 u32 height, u32 width, u32 line_length,
1148 const struct fb_copyarea *area)
1149 {
1150 struct tga_par *par = (struct tga_par *) info->par;
1151 unsigned long i, left, yincr;
1152 unsigned long depos, sepos, dealign, sealign;
1153 u32 mask_first, mask_last;
1154 unsigned long n32;
1155 void __iomem *tga_regs;
1156 void __iomem *tga_fb;
1157
1158 yincr = line_length;
1159 if (dy > sy) {
1160 dy += height - 1;
1161 sy += height - 1;
1162 yincr = -yincr;
1163 }
1164
1165 /* Compute the offsets and alignments in the frame buffer.
1166 More than anything else, these control how we do copies. */
1167 depos = dy * line_length + dx + width;
1168 sepos = sy * line_length + sx + width;
1169 dealign = depos & 7;
1170 sealign = sepos & 7;
1171
1172 /* ??? The documentation appears to be incorrect (or very
1173 misleading) wrt how pixel shifting works in backward copy
1174 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1175 Do handle the common case of co-aligned backward copies,
1176 but frob everything else back on generic code. */
1177 if (dealign != sealign) {
1178 cfb_copyarea(info, area);
1179 return;
1180 }
1181
1182 /* We begin the copy with the trailing pixels of the
1183 unaligned destination. */
1184 mask_first = (1ul << dealign) - 1;
1185 left = width - dealign;
1186
1187 /* Care for small copies. */
1188 if (dealign > width) {
1189 mask_first ^= (1ul << (dealign - width)) - 1;
1190 left = 0;
1191 }
1192
1193 /* Next copy full words at a time. */
1194 n32 = left / 32;
1195 left %= 32;
1196
1197 /* Finally copy the unaligned head of the span. */
1198 mask_last = -1 << (32 - left);
1199
1200 tga_regs = par->tga_regs_base;
1201 tga_fb = par->tga_fb_base;
1202
1203 /* Set up the MODE and PIXELSHIFT registers. */
1204 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1205 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1206 wmb();
1207
1208 for (i = 0; i < height; ++i) {
1209 unsigned long j;
1210 void __iomem *sfb;
1211 void __iomem *dfb;
1212
1213 sfb = tga_fb + sepos;
1214 dfb = tga_fb + depos;
1215 if (mask_first) {
1216 __raw_writel(mask_first, sfb);
1217 wmb();
1218 __raw_writel(mask_first, dfb);
1219 wmb();
1220 }
1221
1222 for (j = 0; j < n32; ++j) {
1223 sfb -= 32;
1224 dfb -= 32;
1225 __raw_writel(0xffffffff, sfb);
1226 wmb();
1227 __raw_writel(0xffffffff, dfb);
1228 wmb();
1229 }
1230
1231 if (mask_last) {
1232 sfb -= 32;
1233 dfb -= 32;
1234 __raw_writel(mask_last, sfb);
1235 wmb();
1236 __raw_writel(mask_last, dfb);
1237 wmb();
1238 }
1239
1240 sepos += yincr;
1241 depos += yincr;
1242 }
1243
1244 /* Reset the MODE register to normal. */
1245 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1246 }
1247
1248 static void
1249 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1250 {
1251 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1252 unsigned long line_length, bpp;
1253
1254 dx = area->dx;
1255 dy = area->dy;
1256 width = area->width;
1257 height = area->height;
1258 sx = area->sx;
1259 sy = area->sy;
1260 vxres = info->var.xres_virtual;
1261 vyres = info->var.yres_virtual;
1262 line_length = info->fix.line_length;
1263
1264 /* The top left corners must be in the virtual screen. */
1265 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1266 return;
1267
1268 /* Clip the destination. */
1269 if (dx + width > vxres)
1270 width = vxres - dx;
1271 if (dy + height > vyres)
1272 height = vyres - dy;
1273
1274 /* The source must be completely inside the virtual screen. */
1275 if (sx + width > vxres || sy + height > vyres)
1276 return;
1277
1278 bpp = info->var.bits_per_pixel;
1279
1280 /* Detect copies of the entire line. */
1281 if (width * (bpp >> 3) == line_length) {
1282 if (bpp == 8)
1283 copyarea_line_8bpp(info, dy, sy, height, width);
1284 else
1285 copyarea_line_32bpp(info, dy, sy, height, width);
1286 }
1287
1288 /* ??? The documentation is unclear to me exactly how the pixelshift
1289 register works in 32bpp mode. Since I don't have hardware to test,
1290 give up for now and fall back on the generic routines. */
1291 else if (bpp == 32)
1292 cfb_copyarea(info, area);
1293
1294 /* Detect overlapping source and destination that requires
1295 a backward copy. */
1296 else if (dy == sy && dx > sx && dx < sx + width)
1297 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1298 width, line_length, area);
1299 else
1300 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1301 width, line_length);
1302 }
1303
1304
1305 /*
1306 * Initialisation
1307 */
1308
1309 static void
1310 tgafb_init_fix(struct fb_info *info)
1311 {
1312 struct tga_par *par = (struct tga_par *)info->par;
1313 u8 tga_type = par->tga_type;
1314 const char *tga_type_name;
1315
1316 switch (tga_type) {
1317 case TGA_TYPE_8PLANE:
1318 tga_type_name = "Digital ZLXp-E1";
1319 break;
1320 case TGA_TYPE_24PLANE:
1321 tga_type_name = "Digital ZLXp-E2";
1322 break;
1323 case TGA_TYPE_24PLUSZ:
1324 tga_type_name = "Digital ZLXp-E3";
1325 break;
1326 default:
1327 tga_type_name = "Unknown";
1328 break;
1329 }
1330
1331 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1332
1333 info->fix.type = FB_TYPE_PACKED_PIXELS;
1334 info->fix.type_aux = 0;
1335 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1336 ? FB_VISUAL_PSEUDOCOLOR
1337 : FB_VISUAL_DIRECTCOLOR);
1338
1339 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1340 info->fix.smem_start = (size_t) par->tga_fb_base;
1341 info->fix.smem_len = info->fix.line_length * par->yres;
1342 info->fix.mmio_start = (size_t) par->tga_regs_base;
1343 info->fix.mmio_len = 512;
1344
1345 info->fix.xpanstep = 0;
1346 info->fix.ypanstep = 0;
1347 info->fix.ywrapstep = 0;
1348
1349 info->fix.accel = FB_ACCEL_DEC_TGA;
1350 }
1351
1352 static __devinit int
1353 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1354 {
1355 static unsigned int const fb_offset_presets[4] = {
1356 TGA_8PLANE_FB_OFFSET,
1357 TGA_24PLANE_FB_OFFSET,
1358 0xffffffff,
1359 TGA_24PLUSZ_FB_OFFSET
1360 };
1361
1362 void __iomem *mem_base;
1363 unsigned long bar0_start, bar0_len;
1364 struct fb_info *info;
1365 struct tga_par *par;
1366 u8 tga_type;
1367 int ret;
1368
1369 /* Enable device in PCI config. */
1370 if (pci_enable_device(pdev)) {
1371 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1372 return -ENODEV;
1373 }
1374
1375 /* Allocate the fb and par structures. */
1376 info = framebuffer_alloc(sizeof(struct tga_par), &pdev->dev);
1377 if (!info) {
1378 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1379 return -ENOMEM;
1380 }
1381
1382 par = info->par;
1383 pci_set_drvdata(pdev, info);
1384
1385 /* Request the mem regions. */
1386 bar0_start = pci_resource_start(pdev, 0);
1387 bar0_len = pci_resource_len(pdev, 0);
1388 ret = -ENODEV;
1389 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1390 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1391 goto err0;
1392 }
1393
1394 /* Map the framebuffer. */
1395 mem_base = ioremap(bar0_start, bar0_len);
1396 if (!mem_base) {
1397 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1398 goto err1;
1399 }
1400
1401 /* Grab info about the card. */
1402 tga_type = (readl(mem_base) >> 12) & 0x0f;
1403 par->pdev = pdev;
1404 par->tga_mem_base = mem_base;
1405 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1406 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1407 par->tga_type = tga_type;
1408 pci_read_config_byte(pdev, PCI_REVISION_ID, &par->tga_chip_rev);
1409
1410 /* Setup framebuffer. */
1411 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1412 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1413 info->fbops = &tgafb_ops;
1414 info->screen_base = par->tga_fb_base;
1415 info->pseudo_palette = (void *)(par + 1);
1416
1417 /* This should give a reasonable default video mode. */
1418
1419 ret = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL,
1420 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1421 if (ret == 0 || ret == 4) {
1422 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1423 ret = -EINVAL;
1424 goto err1;
1425 }
1426
1427 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1428 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1429 ret = -ENOMEM;
1430 goto err1;
1431 }
1432
1433 tgafb_set_par(info);
1434 tgafb_init_fix(info);
1435
1436 if (register_framebuffer(info) < 0) {
1437 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1438 ret = -EINVAL;
1439 goto err1;
1440 }
1441
1442 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1443 par->tga_chip_rev);
1444 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1445 pdev->bus->number, PCI_SLOT(pdev->devfn),
1446 PCI_FUNC(pdev->devfn));
1447 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1448 info->node, info->fix.id, bar0_start);
1449
1450 return 0;
1451
1452 err1:
1453 if (mem_base)
1454 iounmap(mem_base);
1455 release_mem_region(bar0_start, bar0_len);
1456 err0:
1457 framebuffer_release(info);
1458 return ret;
1459 }
1460
1461 static void __devexit
1462 tgafb_pci_unregister(struct pci_dev *pdev)
1463 {
1464 struct fb_info *info = pci_get_drvdata(pdev);
1465 struct tga_par *par = info->par;
1466
1467 if (!info)
1468 return;
1469 unregister_framebuffer(info);
1470 fb_dealloc_cmap(&info->cmap);
1471 iounmap(par->tga_mem_base);
1472 release_mem_region(pci_resource_start(pdev, 0),
1473 pci_resource_len(pdev, 0));
1474 framebuffer_release(info);
1475 }
1476
1477 static void __devexit
1478 tgafb_exit(void)
1479 {
1480 pci_unregister_driver(&tgafb_driver);
1481 }
1482
1483 #ifndef MODULE
1484 static int __devinit
1485 tgafb_setup(char *arg)
1486 {
1487 char *this_opt;
1488
1489 if (arg && *arg) {
1490 while ((this_opt = strsep(&arg, ","))) {
1491 if (!*this_opt)
1492 continue;
1493 if (!strncmp(this_opt, "mode:", 5))
1494 mode_option = this_opt+5;
1495 else
1496 printk(KERN_ERR
1497 "tgafb: unknown parameter %s\n",
1498 this_opt);
1499 }
1500 }
1501
1502 return 0;
1503 }
1504 #endif /* !MODULE */
1505
1506 static int __devinit
1507 tgafb_init(void)
1508 {
1509 #ifndef MODULE
1510 char *option = NULL;
1511
1512 if (fb_get_options("tgafb", &option))
1513 return -ENODEV;
1514 tgafb_setup(option);
1515 #endif
1516 return pci_register_driver(&tgafb_driver);
1517 }
1518
1519 /*
1520 * Modularisation
1521 */
1522
1523 module_init(tgafb_init);
1524 module_exit(tgafb_exit);
1525
1526 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1527 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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