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86050e79b8923c566afdc421c904b5256f54ab3a
[deliverable/linux.git] / drivers / video / via / hw.c
1 /*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include "global.h"
23
24 static const struct pci_device_id_info pciidlist[] = {
25 {PCI_VIA_VENDOR_ID, UNICHROME_CLE266_DID, UNICHROME_CLE266},
26 {PCI_VIA_VENDOR_ID, UNICHROME_PM800_DID, UNICHROME_PM800},
27 {PCI_VIA_VENDOR_ID, UNICHROME_K400_DID, UNICHROME_K400},
28 {PCI_VIA_VENDOR_ID, UNICHROME_K800_DID, UNICHROME_K800},
29 {PCI_VIA_VENDOR_ID, UNICHROME_CN700_DID, UNICHROME_CN700},
30 {PCI_VIA_VENDOR_ID, UNICHROME_P4M890_DID, UNICHROME_P4M890},
31 {PCI_VIA_VENDOR_ID, UNICHROME_K8M890_DID, UNICHROME_K8M890},
32 {PCI_VIA_VENDOR_ID, UNICHROME_CX700_DID, UNICHROME_CX700},
33 {PCI_VIA_VENDOR_ID, UNICHROME_P4M900_DID, UNICHROME_P4M900},
34 {PCI_VIA_VENDOR_ID, UNICHROME_CN750_DID, UNICHROME_CN750},
35 {PCI_VIA_VENDOR_ID, UNICHROME_VX800_DID, UNICHROME_VX800},
36 {0, 0, 0}
37 };
38
39 struct offset offset_reg = {
40 /* IGA1 Offset Register */
41 {IGA1_OFFSET_REG_NUM, {{CR13, 0, 7}, {CR35, 5, 7} } },
42 /* IGA2 Offset Register */
43 {IGA2_OFFSET_REG_NUM, {{CR66, 0, 7}, {CR67, 0, 1} } }
44 };
45
46 static struct pll_map pll_value[] = {
47 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M},
48 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M},
49 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M},
50 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M},
51 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M},
52 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M},
53 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M},
54 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M},
55 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M},
56 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M},
57 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M},
58 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, CX700_45_250M},
59 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, CX700_46_000M},
60 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, CX700_46_996M},
61 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, CX700_48_000M},
62 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, CX700_48_875M},
63 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M},
64 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M},
65 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, CX700_52_977M},
66 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M},
67 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M},
68 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, CX700_61_500M},
69 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M},
70 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, CX700_65_178M},
71 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, CX700_66_750M},
72 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M},
73 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, CX700_69_924M},
74 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, CX700_70_159M},
75 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, CX700_72_000M},
76 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M},
77 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M},
78 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, CX700_83_375M},
79 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M},
80 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, CX700_84_750M},
81 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M},
82 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, CX700_88_750M},
83 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M},
84 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, CX700_97_750M},
85 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
86 CX700_101_000M},
87 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
88 CX700_106_500M},
89 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
90 CX700_108_000M},
91 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
92 CX700_113_309M},
93 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
94 CX700_118_840M},
95 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
96 CX700_119_000M},
97 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
98 CX700_121_750M},
99 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
100 CX700_125_104M},
101 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
102 CX700_133_308M},
103 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
104 CX700_135_000M},
105 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
106 CX700_136_700M},
107 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
108 CX700_138_400M},
109 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
110 CX700_146_760M},
111 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
112 CX700_153_920M},
113 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
114 CX700_156_000M},
115 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
116 CX700_157_500M},
117 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
118 CX700_162_000M},
119 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
120 CX700_187_000M},
121 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
122 CX700_193_295M},
123 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
124 CX700_202_500M},
125 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
126 CX700_204_000M},
127 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
128 CX700_218_500M},
129 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
130 CX700_234_000M},
131 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
132 CX700_267_250M},
133 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
134 CX700_297_500M},
135 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M},
136 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
137 CX700_172_798M},
138 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
139 CX700_122_614M},
140 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, CX700_74_270M},
141 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
142 CX700_148_500M}
143 };
144
145 static struct fifo_depth_select display_fifo_depth_reg = {
146 /* IGA1 FIFO Depth_Select */
147 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
148 /* IGA2 FIFO Depth_Select */
149 {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
150 {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
151 };
152
153 static struct fifo_threshold_select fifo_threshold_select_reg = {
154 /* IGA1 FIFO Threshold Select */
155 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
156 /* IGA2 FIFO Threshold Select */
157 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
158 };
159
160 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
161 /* IGA1 FIFO High Threshold Select */
162 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
163 /* IGA2 FIFO High Threshold Select */
164 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
165 };
166
167 static struct display_queue_expire_num display_queue_expire_num_reg = {
168 /* IGA1 Display Queue Expire Num */
169 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
170 /* IGA2 Display Queue Expire Num */
171 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
172 };
173
174 /* Definition Fetch Count Registers*/
175 static struct fetch_count fetch_count_reg = {
176 /* IGA1 Fetch Count Register */
177 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
178 /* IGA2 Fetch Count Register */
179 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
180 };
181
182 static struct iga1_crtc_timing iga1_crtc_reg = {
183 /* IGA1 Horizontal Total */
184 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
185 /* IGA1 Horizontal Addressable Video */
186 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
187 /* IGA1 Horizontal Blank Start */
188 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
189 /* IGA1 Horizontal Blank End */
190 {IGA1_HOR_BLANK_END_REG_NUM,
191 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
192 /* IGA1 Horizontal Sync Start */
193 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
194 /* IGA1 Horizontal Sync End */
195 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
196 /* IGA1 Vertical Total */
197 {IGA1_VER_TOTAL_REG_NUM,
198 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
199 /* IGA1 Vertical Addressable Video */
200 {IGA1_VER_ADDR_REG_NUM,
201 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
202 /* IGA1 Vertical Blank Start */
203 {IGA1_VER_BLANK_START_REG_NUM,
204 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
205 /* IGA1 Vertical Blank End */
206 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
207 /* IGA1 Vertical Sync Start */
208 {IGA1_VER_SYNC_START_REG_NUM,
209 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
210 /* IGA1 Vertical Sync End */
211 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
212 };
213
214 static struct iga2_crtc_timing iga2_crtc_reg = {
215 /* IGA2 Horizontal Total */
216 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
217 /* IGA2 Horizontal Addressable Video */
218 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
219 /* IGA2 Horizontal Blank Start */
220 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
221 /* IGA2 Horizontal Blank End */
222 {IGA2_HOR_BLANK_END_REG_NUM,
223 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
224 /* IGA2 Horizontal Sync Start */
225 {IGA2_HOR_SYNC_START_REG_NUM,
226 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
227 /* IGA2 Horizontal Sync End */
228 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
229 /* IGA2 Vertical Total */
230 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
231 /* IGA2 Vertical Addressable Video */
232 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
233 /* IGA2 Vertical Blank Start */
234 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
235 /* IGA2 Vertical Blank End */
236 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
237 /* IGA2 Vertical Sync Start */
238 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
239 /* IGA2 Vertical Sync End */
240 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
241 };
242
243 static struct rgbLUT palLUT_table[] = {
244 /* {R,G,B} */
245 /* Index 0x00~0x03 */
246 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
247 0x2A,
248 0x2A},
249 /* Index 0x04~0x07 */
250 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
251 0x2A,
252 0x2A},
253 /* Index 0x08~0x0B */
254 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
255 0x3F,
256 0x3F},
257 /* Index 0x0C~0x0F */
258 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
259 0x3F,
260 0x3F},
261 /* Index 0x10~0x13 */
262 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
263 0x0B,
264 0x0B},
265 /* Index 0x14~0x17 */
266 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
267 0x18,
268 0x18},
269 /* Index 0x18~0x1B */
270 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
271 0x28,
272 0x28},
273 /* Index 0x1C~0x1F */
274 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
275 0x3F,
276 0x3F},
277 /* Index 0x20~0x23 */
278 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
279 0x00,
280 0x3F},
281 /* Index 0x24~0x27 */
282 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
283 0x00,
284 0x10},
285 /* Index 0x28~0x2B */
286 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
287 0x2F,
288 0x00},
289 /* Index 0x2C~0x2F */
290 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
291 0x3F,
292 0x00},
293 /* Index 0x30~0x33 */
294 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
295 0x3F,
296 0x2F},
297 /* Index 0x34~0x37 */
298 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
299 0x10,
300 0x3F},
301 /* Index 0x38~0x3B */
302 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
303 0x1F,
304 0x3F},
305 /* Index 0x3C~0x3F */
306 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
307 0x1F,
308 0x27},
309 /* Index 0x40~0x43 */
310 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
311 0x3F,
312 0x1F},
313 /* Index 0x44~0x47 */
314 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
315 0x3F,
316 0x1F},
317 /* Index 0x48~0x4B */
318 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
319 0x3F,
320 0x37},
321 /* Index 0x4C~0x4F */
322 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
323 0x27,
324 0x3F},
325 /* Index 0x50~0x53 */
326 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
327 0x2D,
328 0x3F},
329 /* Index 0x54~0x57 */
330 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
331 0x2D,
332 0x31},
333 /* Index 0x58~0x5B */
334 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
335 0x3A,
336 0x2D},
337 /* Index 0x5C~0x5F */
338 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
339 0x3F,
340 0x2D},
341 /* Index 0x60~0x63 */
342 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
343 0x3F,
344 0x3A},
345 /* Index 0x64~0x67 */
346 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
347 0x31,
348 0x3F},
349 /* Index 0x68~0x6B */
350 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
351 0x00,
352 0x1C},
353 /* Index 0x6C~0x6F */
354 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
355 0x00,
356 0x07},
357 /* Index 0x70~0x73 */
358 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
359 0x15,
360 0x00},
361 /* Index 0x74~0x77 */
362 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
363 0x1C,
364 0x00},
365 /* Index 0x78~0x7B */
366 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
367 0x1C,
368 0x15},
369 /* Index 0x7C~0x7F */
370 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
371 0x07,
372 0x1C},
373 /* Index 0x80~0x83 */
374 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
375 0x0E,
376 0x1C},
377 /* Index 0x84~0x87 */
378 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
379 0x0E,
380 0x11},
381 /* Index 0x88~0x8B */
382 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
383 0x18,
384 0x0E},
385 /* Index 0x8C~0x8F */
386 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
387 0x1C,
388 0x0E},
389 /* Index 0x90~0x93 */
390 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
391 0x1C,
392 0x18},
393 /* Index 0x94~0x97 */
394 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
395 0x11,
396 0x1C},
397 /* Index 0x98~0x9B */
398 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
399 0x14,
400 0x1C},
401 /* Index 0x9C~0x9F */
402 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
403 0x14,
404 0x16},
405 /* Index 0xA0~0xA3 */
406 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
407 0x1A,
408 0x14},
409 /* Index 0xA4~0xA7 */
410 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
411 0x1C,
412 0x14},
413 /* Index 0xA8~0xAB */
414 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
415 0x1C,
416 0x1A},
417 /* Index 0xAC~0xAF */
418 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
419 0x16,
420 0x1C},
421 /* Index 0xB0~0xB3 */
422 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
423 0x00,
424 0x10},
425 /* Index 0xB4~0xB7 */
426 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
427 0x00,
428 0x04},
429 /* Index 0xB8~0xBB */
430 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
431 0x0C,
432 0x00},
433 /* Index 0xBC~0xBF */
434 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
435 0x10,
436 0x00},
437 /* Index 0xC0~0xC3 */
438 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
439 0x10,
440 0x0C},
441 /* Index 0xC4~0xC7 */
442 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
443 0x04,
444 0x10},
445 /* Index 0xC8~0xCB */
446 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
447 0x08,
448 0x10},
449 /* Index 0xCC~0xCF */
450 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
451 0x08,
452 0x0A},
453 /* Index 0xD0~0xD3 */
454 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
455 0x0E,
456 0x08},
457 /* Index 0xD4~0xD7 */
458 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
459 0x10,
460 0x08},
461 /* Index 0xD8~0xDB */
462 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
463 0x10,
464 0x0E},
465 /* Index 0xDC~0xDF */
466 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
467 0x0A,
468 0x10},
469 /* Index 0xE0~0xE3 */
470 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
471 0x0B,
472 0x10},
473 /* Index 0xE4~0xE7 */
474 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
475 0x0B,
476 0x0C},
477 /* Index 0xE8~0xEB */
478 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
479 0x0F,
480 0x0B},
481 /* Index 0xEC~0xEF */
482 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
483 0x10,
484 0x0B},
485 /* Index 0xF0~0xF3 */
486 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
487 0x10,
488 0x0F},
489 /* Index 0xF4~0xF7 */
490 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
491 0x0C,
492 0x10},
493 /* Index 0xF8~0xFB */
494 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
495 0x00,
496 0x00},
497 /* Index 0xFC~0xFF */
498 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
499 0x00,
500 0x00}
501 };
502
503 static void set_crt_output_path(int set_iga);
504 static void dvi_patch_skew_dvp0(void);
505 static void dvi_patch_skew_dvp1(void);
506 static void dvi_patch_skew_dvp_low(void);
507 static void set_dvi_output_path(int set_iga, int output_interface);
508 static void set_lcd_output_path(int set_iga, int output_interface);
509 static int search_mode_setting(int ModeInfoIndex);
510 static void load_fix_bit_crtc_reg(void);
511 static void init_gfx_chip_info(void);
512 static void init_tmds_chip_info(void);
513 static void init_lvds_chip_info(void);
514 static void device_screen_off(void);
515 static void device_screen_on(void);
516 static void set_display_channel(void);
517 static void device_off(void);
518 static void device_on(void);
519 static void enable_second_display_channel(void);
520 static void disable_second_display_channel(void);
521 static int get_fb_size_from_pci(void);
522
523 void viafb_write_reg(u8 index, u16 io_port, u8 data)
524 {
525 outb(index, io_port);
526 outb(data, io_port + 1);
527 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
528 }
529 u8 viafb_read_reg(int io_port, u8 index)
530 {
531 outb(index, io_port);
532 return inb(io_port + 1);
533 }
534
535 void viafb_lock_crt(void)
536 {
537 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
538 }
539
540 void viafb_unlock_crt(void)
541 {
542 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
543 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
544 }
545
546 void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
547 {
548 u8 tmp;
549
550 outb(index, io_port);
551 tmp = inb(io_port + 1);
552 outb((data & mask) | (tmp & (~mask)), io_port + 1);
553 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
554 }
555
556 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
557 {
558 outb(index, LUT_INDEX_WRITE);
559 outb(r, LUT_DATA);
560 outb(g, LUT_DATA);
561 outb(b, LUT_DATA);
562 }
563
564 /*Set IGA path for each device*/
565 void viafb_set_iga_path(void)
566 {
567
568 if (viafb_SAMM_ON == 1) {
569 if (viafb_CRT_ON) {
570 if (viafb_primary_dev == CRT_Device)
571 viaparinfo->crt_setting_info->iga_path = IGA1;
572 else
573 viaparinfo->crt_setting_info->iga_path = IGA2;
574 }
575
576 if (viafb_DVI_ON) {
577 if (viafb_primary_dev == DVI_Device)
578 viaparinfo->tmds_setting_info->iga_path = IGA1;
579 else
580 viaparinfo->tmds_setting_info->iga_path = IGA2;
581 }
582
583 if (viafb_LCD_ON) {
584 if (viafb_primary_dev == LCD_Device) {
585 if (viafb_dual_fb &&
586 (viaparinfo->chip_info->gfx_chip_name ==
587 UNICHROME_CLE266)) {
588 viaparinfo->
589 lvds_setting_info->iga_path = IGA2;
590 viaparinfo->
591 crt_setting_info->iga_path = IGA1;
592 viaparinfo->
593 tmds_setting_info->iga_path = IGA1;
594 } else
595 viaparinfo->
596 lvds_setting_info->iga_path = IGA1;
597 } else {
598 viaparinfo->lvds_setting_info->iga_path = IGA2;
599 }
600 }
601 if (viafb_LCD2_ON) {
602 if (LCD2_Device == viafb_primary_dev)
603 viaparinfo->lvds_setting_info2->iga_path = IGA1;
604 else
605 viaparinfo->lvds_setting_info2->iga_path = IGA2;
606 }
607 } else {
608 viafb_SAMM_ON = 0;
609
610 if (viafb_CRT_ON && viafb_LCD_ON) {
611 viaparinfo->crt_setting_info->iga_path = IGA1;
612 viaparinfo->lvds_setting_info->iga_path = IGA2;
613 } else if (viafb_CRT_ON && viafb_DVI_ON) {
614 viaparinfo->crt_setting_info->iga_path = IGA1;
615 viaparinfo->tmds_setting_info->iga_path = IGA2;
616 } else if (viafb_LCD_ON && viafb_DVI_ON) {
617 viaparinfo->tmds_setting_info->iga_path = IGA1;
618 viaparinfo->lvds_setting_info->iga_path = IGA2;
619 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
620 viaparinfo->lvds_setting_info->iga_path = IGA2;
621 viaparinfo->lvds_setting_info2->iga_path = IGA2;
622 } else if (viafb_CRT_ON) {
623 viaparinfo->crt_setting_info->iga_path = IGA1;
624 } else if (viafb_LCD_ON) {
625 viaparinfo->lvds_setting_info->iga_path = IGA2;
626 } else if (viafb_DVI_ON) {
627 viaparinfo->tmds_setting_info->iga_path = IGA1;
628 }
629 }
630 }
631
632 void viafb_set_primary_address(u32 addr)
633 {
634 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
635 viafb_write_reg(CR0D, VIACR, addr & 0xFF);
636 viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
637 viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
638 viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
639 }
640
641 void viafb_set_secondary_address(u32 addr)
642 {
643 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
644 /* secondary display supports only quadword aligned memory */
645 viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
646 viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
647 viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
648 viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
649 }
650
651 void viafb_set_output_path(int device, int set_iga, int output_interface)
652 {
653 switch (device) {
654 case DEVICE_CRT:
655 set_crt_output_path(set_iga);
656 break;
657 case DEVICE_DVI:
658 set_dvi_output_path(set_iga, output_interface);
659 break;
660 case DEVICE_LCD:
661 set_lcd_output_path(set_iga, output_interface);
662 break;
663 }
664 }
665
666 static void set_crt_output_path(int set_iga)
667 {
668 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
669
670 switch (set_iga) {
671 case IGA1:
672 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
673 break;
674 case IGA2:
675 case IGA1_IGA2:
676 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
677 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
678 if (set_iga == IGA1_IGA2)
679 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
680 break;
681 }
682 }
683
684 static void dvi_patch_skew_dvp0(void)
685 {
686 /* Reset data driving first: */
687 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
688 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
689
690 switch (viaparinfo->chip_info->gfx_chip_name) {
691 case UNICHROME_P4M890:
692 {
693 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
694 (viaparinfo->tmds_setting_info->v_active ==
695 1200))
696 viafb_write_reg_mask(CR96, VIACR, 0x03,
697 BIT0 + BIT1 + BIT2);
698 else
699 viafb_write_reg_mask(CR96, VIACR, 0x07,
700 BIT0 + BIT1 + BIT2);
701 break;
702 }
703
704 case UNICHROME_P4M900:
705 {
706 viafb_write_reg_mask(CR96, VIACR, 0x07,
707 BIT0 + BIT1 + BIT2 + BIT3);
708 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
709 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
710 break;
711 }
712
713 default:
714 {
715 break;
716 }
717 }
718 }
719
720 static void dvi_patch_skew_dvp1(void)
721 {
722 switch (viaparinfo->chip_info->gfx_chip_name) {
723 case UNICHROME_CX700:
724 {
725 break;
726 }
727
728 default:
729 {
730 break;
731 }
732 }
733 }
734
735 static void dvi_patch_skew_dvp_low(void)
736 {
737 switch (viaparinfo->chip_info->gfx_chip_name) {
738 case UNICHROME_K8M890:
739 {
740 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
741 break;
742 }
743
744 case UNICHROME_P4M900:
745 {
746 viafb_write_reg_mask(CR99, VIACR, 0x08,
747 BIT0 + BIT1 + BIT2 + BIT3);
748 break;
749 }
750
751 case UNICHROME_P4M890:
752 {
753 viafb_write_reg_mask(CR99, VIACR, 0x0F,
754 BIT0 + BIT1 + BIT2 + BIT3);
755 break;
756 }
757
758 default:
759 {
760 break;
761 }
762 }
763 }
764
765 static void set_dvi_output_path(int set_iga, int output_interface)
766 {
767 switch (output_interface) {
768 case INTERFACE_DVP0:
769 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
770
771 if (set_iga == IGA1) {
772 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
773 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
774 BIT5 + BIT7);
775 } else {
776 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
777 viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
778 BIT5 + BIT7);
779 }
780
781 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
782
783 dvi_patch_skew_dvp0();
784 break;
785
786 case INTERFACE_DVP1:
787 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
788 if (set_iga == IGA1)
789 viafb_write_reg_mask(CR93, VIACR, 0x21,
790 BIT0 + BIT5 + BIT7);
791 else
792 viafb_write_reg_mask(CR93, VIACR, 0xA1,
793 BIT0 + BIT5 + BIT7);
794 } else {
795 if (set_iga == IGA1)
796 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
797 else
798 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
799 }
800
801 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
802 dvi_patch_skew_dvp1();
803 break;
804 case INTERFACE_DFP_HIGH:
805 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
806 if (set_iga == IGA1) {
807 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
808 viafb_write_reg_mask(CR97, VIACR, 0x03,
809 BIT0 + BIT1 + BIT4);
810 } else {
811 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
812 viafb_write_reg_mask(CR97, VIACR, 0x13,
813 BIT0 + BIT1 + BIT4);
814 }
815 }
816 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
817 break;
818
819 case INTERFACE_DFP_LOW:
820 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
821 break;
822
823 if (set_iga == IGA1) {
824 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
825 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
826 } else {
827 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
828 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
829 }
830
831 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
832 dvi_patch_skew_dvp_low();
833 break;
834
835 case INTERFACE_TMDS:
836 if (set_iga == IGA1)
837 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
838 else
839 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
840 break;
841 }
842
843 if (set_iga == IGA2) {
844 enable_second_display_channel();
845 /* Disable LCD Scaling */
846 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
847 }
848 }
849
850 static void set_lcd_output_path(int set_iga, int output_interface)
851 {
852 DEBUG_MSG(KERN_INFO
853 "set_lcd_output_path, iga:%d,out_interface:%d\n",
854 set_iga, output_interface);
855 switch (set_iga) {
856 case IGA1:
857 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
858 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
859
860 disable_second_display_channel();
861 break;
862
863 case IGA2:
864 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
865 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
866
867 enable_second_display_channel();
868 break;
869
870 case IGA1_IGA2:
871 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
872 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
873
874 disable_second_display_channel();
875 break;
876 }
877
878 switch (output_interface) {
879 case INTERFACE_DVP0:
880 if (set_iga == IGA1) {
881 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
882 } else {
883 viafb_write_reg(CR91, VIACR, 0x00);
884 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
885 }
886 break;
887
888 case INTERFACE_DVP1:
889 if (set_iga == IGA1)
890 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
891 else {
892 viafb_write_reg(CR91, VIACR, 0x00);
893 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
894 }
895 break;
896
897 case INTERFACE_DFP_HIGH:
898 if (set_iga == IGA1)
899 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
900 else {
901 viafb_write_reg(CR91, VIACR, 0x00);
902 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
903 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
904 }
905 break;
906
907 case INTERFACE_DFP_LOW:
908 if (set_iga == IGA1)
909 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
910 else {
911 viafb_write_reg(CR91, VIACR, 0x00);
912 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
913 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
914 }
915
916 break;
917
918 case INTERFACE_DFP:
919 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
920 || (UNICHROME_P4M890 ==
921 viaparinfo->chip_info->gfx_chip_name))
922 viafb_write_reg_mask(CR97, VIACR, 0x84,
923 BIT7 + BIT2 + BIT1 + BIT0);
924 if (set_iga == IGA1) {
925 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
926 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
927 } else {
928 viafb_write_reg(CR91, VIACR, 0x00);
929 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
930 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
931 }
932 break;
933
934 case INTERFACE_LVDS0:
935 case INTERFACE_LVDS0LVDS1:
936 if (set_iga == IGA1)
937 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
938 else
939 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
940
941 break;
942
943 case INTERFACE_LVDS1:
944 if (set_iga == IGA1)
945 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
946 else
947 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
948 break;
949 }
950 }
951
952 /* Search Mode Index */
953 static int search_mode_setting(int ModeInfoIndex)
954 {
955 int i = 0;
956
957 while ((i < NUM_TOTAL_MODETABLE) &&
958 (ModeInfoIndex != CLE266Modes[i].ModeIndex))
959 i++;
960 if (i >= NUM_TOTAL_MODETABLE)
961 i = 0;
962 return i;
963
964 }
965
966 struct VideoModeTable *viafb_get_modetbl_pointer(int Index)
967 {
968 struct VideoModeTable *TmpTbl = NULL;
969 TmpTbl = &CLE266Modes[search_mode_setting(Index)];
970 return TmpTbl;
971 }
972
973 struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index)
974 {
975 struct VideoModeTable *TmpTbl = NULL;
976 int i = 0;
977 while ((i < NUM_TOTAL_CEA_MODES) &&
978 (Index != CEA_HDMI_Modes[i].ModeIndex))
979 i++;
980 if ((i < NUM_TOTAL_CEA_MODES))
981 TmpTbl = &CEA_HDMI_Modes[i];
982 else {
983 /*Still use general timing if don't find CEA timing */
984 i = 0;
985 while ((i < NUM_TOTAL_MODETABLE) &&
986 (Index != CLE266Modes[i].ModeIndex))
987 i++;
988 if (i >= NUM_TOTAL_MODETABLE)
989 i = 0;
990 TmpTbl = &CLE266Modes[i];
991 }
992 return TmpTbl;
993 }
994
995 static void load_fix_bit_crtc_reg(void)
996 {
997 /* always set to 1 */
998 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
999 /* line compare should set all bits = 1 (extend modes) */
1000 viafb_write_reg(CR18, VIACR, 0xff);
1001 /* line compare should set all bits = 1 (extend modes) */
1002 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1003 /* line compare should set all bits = 1 (extend modes) */
1004 viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1005 /* line compare should set all bits = 1 (extend modes) */
1006 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1007 /* line compare should set all bits = 1 (extend modes) */
1008 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1009 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1010 /* extend mode always set to e3h */
1011 viafb_write_reg(CR17, VIACR, 0xe3);
1012 /* extend mode always set to 0h */
1013 viafb_write_reg(CR08, VIACR, 0x00);
1014 /* extend mode always set to 0h */
1015 viafb_write_reg(CR14, VIACR, 0x00);
1016
1017 /* If K8M800, enable Prefetch Mode. */
1018 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1019 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1020 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1021 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1022 && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1023 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1024
1025 }
1026
1027 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1028 struct io_register *reg,
1029 int io_type)
1030 {
1031 int reg_mask;
1032 int bit_num = 0;
1033 int data;
1034 int i, j;
1035 int shift_next_reg;
1036 int start_index, end_index, cr_index;
1037 u16 get_bit;
1038
1039 for (i = 0; i < viafb_load_reg_num; i++) {
1040 reg_mask = 0;
1041 data = 0;
1042 start_index = reg[i].start_bit;
1043 end_index = reg[i].end_bit;
1044 cr_index = reg[i].io_addr;
1045
1046 shift_next_reg = bit_num;
1047 for (j = start_index; j <= end_index; j++) {
1048 /*if (bit_num==8) timing_value = timing_value >>8; */
1049 reg_mask = reg_mask | (BIT0 << j);
1050 get_bit = (timing_value & (BIT0 << bit_num));
1051 data =
1052 data | ((get_bit >> shift_next_reg) << start_index);
1053 bit_num++;
1054 }
1055 if (io_type == VIACR)
1056 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1057 else
1058 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1059 }
1060
1061 }
1062
1063 /* Write Registers */
1064 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1065 {
1066 int i;
1067 unsigned char RegTemp;
1068
1069 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1070
1071 for (i = 0; i < ItemNum; i++) {
1072 outb(RegTable[i].index, RegTable[i].port);
1073 RegTemp = inb(RegTable[i].port + 1);
1074 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1075 outb(RegTemp, RegTable[i].port + 1);
1076 }
1077 }
1078
1079 void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga)
1080 {
1081 int reg_value;
1082 int viafb_load_reg_num;
1083 struct io_register *reg;
1084
1085 switch (set_iga) {
1086 case IGA1_IGA2:
1087 case IGA1:
1088 reg_value = IGA1_OFFSET_FORMULA(h_addr, bpp_byte);
1089 viafb_load_reg_num = offset_reg.iga1_offset_reg.reg_num;
1090 reg = offset_reg.iga1_offset_reg.reg;
1091 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1092 if (set_iga == IGA1)
1093 break;
1094 case IGA2:
1095 reg_value = IGA2_OFFSET_FORMULA(h_addr, bpp_byte);
1096 viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
1097 reg = offset_reg.iga2_offset_reg.reg;
1098 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1099 break;
1100 }
1101 }
1102
1103 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1104 {
1105 int reg_value;
1106 int viafb_load_reg_num;
1107 struct io_register *reg = NULL;
1108
1109 switch (set_iga) {
1110 case IGA1_IGA2:
1111 case IGA1:
1112 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1113 viafb_load_reg_num = fetch_count_reg.
1114 iga1_fetch_count_reg.reg_num;
1115 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1116 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1117 if (set_iga == IGA1)
1118 break;
1119 case IGA2:
1120 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1121 viafb_load_reg_num = fetch_count_reg.
1122 iga2_fetch_count_reg.reg_num;
1123 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1124 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1125 break;
1126 }
1127
1128 }
1129
1130 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1131 {
1132 int reg_value;
1133 int viafb_load_reg_num;
1134 struct io_register *reg = NULL;
1135 int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1136 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1137 int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1138 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1139
1140 if (set_iga == IGA1) {
1141 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1142 iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1143 iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1144 iga1_fifo_high_threshold =
1145 K800_IGA1_FIFO_HIGH_THRESHOLD;
1146 /* If resolution > 1280x1024, expire length = 64, else
1147 expire length = 128 */
1148 if ((hor_active > 1280) && (ver_active > 1024))
1149 iga1_display_queue_expire_num = 16;
1150 else
1151 iga1_display_queue_expire_num =
1152 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1153
1154 }
1155
1156 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1157 iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1158 iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1159 iga1_fifo_high_threshold =
1160 P880_IGA1_FIFO_HIGH_THRESHOLD;
1161 iga1_display_queue_expire_num =
1162 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1163
1164 /* If resolution > 1280x1024, expire length = 64, else
1165 expire length = 128 */
1166 if ((hor_active > 1280) && (ver_active > 1024))
1167 iga1_display_queue_expire_num = 16;
1168 else
1169 iga1_display_queue_expire_num =
1170 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1171 }
1172
1173 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1174 iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1175 iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1176 iga1_fifo_high_threshold =
1177 CN700_IGA1_FIFO_HIGH_THRESHOLD;
1178
1179 /* If resolution > 1280x1024, expire length = 64,
1180 else expire length = 128 */
1181 if ((hor_active > 1280) && (ver_active > 1024))
1182 iga1_display_queue_expire_num = 16;
1183 else
1184 iga1_display_queue_expire_num =
1185 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1186 }
1187
1188 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1189 iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1190 iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1191 iga1_fifo_high_threshold =
1192 CX700_IGA1_FIFO_HIGH_THRESHOLD;
1193 iga1_display_queue_expire_num =
1194 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1195 }
1196
1197 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1198 iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1199 iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1200 iga1_fifo_high_threshold =
1201 K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1202 iga1_display_queue_expire_num =
1203 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1204 }
1205
1206 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1207 iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1208 iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1209 iga1_fifo_high_threshold =
1210 P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1211 iga1_display_queue_expire_num =
1212 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1213 }
1214
1215 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1216 iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1217 iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1218 iga1_fifo_high_threshold =
1219 P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1220 iga1_display_queue_expire_num =
1221 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1222 }
1223
1224 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1225 iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1226 iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1227 iga1_fifo_high_threshold =
1228 VX800_IGA1_FIFO_HIGH_THRESHOLD;
1229 iga1_display_queue_expire_num =
1230 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1231 }
1232
1233 /* Set Display FIFO Depath Select */
1234 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1235 viafb_load_reg_num =
1236 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1237 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1238 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1239
1240 /* Set Display FIFO Threshold Select */
1241 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1242 viafb_load_reg_num =
1243 fifo_threshold_select_reg.
1244 iga1_fifo_threshold_select_reg.reg_num;
1245 reg =
1246 fifo_threshold_select_reg.
1247 iga1_fifo_threshold_select_reg.reg;
1248 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1249
1250 /* Set FIFO High Threshold Select */
1251 reg_value =
1252 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1253 viafb_load_reg_num =
1254 fifo_high_threshold_select_reg.
1255 iga1_fifo_high_threshold_select_reg.reg_num;
1256 reg =
1257 fifo_high_threshold_select_reg.
1258 iga1_fifo_high_threshold_select_reg.reg;
1259 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1260
1261 /* Set Display Queue Expire Num */
1262 reg_value =
1263 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1264 (iga1_display_queue_expire_num);
1265 viafb_load_reg_num =
1266 display_queue_expire_num_reg.
1267 iga1_display_queue_expire_num_reg.reg_num;
1268 reg =
1269 display_queue_expire_num_reg.
1270 iga1_display_queue_expire_num_reg.reg;
1271 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1272
1273 } else {
1274 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1275 iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1276 iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1277 iga2_fifo_high_threshold =
1278 K800_IGA2_FIFO_HIGH_THRESHOLD;
1279
1280 /* If resolution > 1280x1024, expire length = 64,
1281 else expire length = 128 */
1282 if ((hor_active > 1280) && (ver_active > 1024))
1283 iga2_display_queue_expire_num = 16;
1284 else
1285 iga2_display_queue_expire_num =
1286 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1287 }
1288
1289 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1290 iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1291 iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1292 iga2_fifo_high_threshold =
1293 P880_IGA2_FIFO_HIGH_THRESHOLD;
1294
1295 /* If resolution > 1280x1024, expire length = 64,
1296 else expire length = 128 */
1297 if ((hor_active > 1280) && (ver_active > 1024))
1298 iga2_display_queue_expire_num = 16;
1299 else
1300 iga2_display_queue_expire_num =
1301 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1302 }
1303
1304 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1305 iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1306 iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1307 iga2_fifo_high_threshold =
1308 CN700_IGA2_FIFO_HIGH_THRESHOLD;
1309
1310 /* If resolution > 1280x1024, expire length = 64,
1311 else expire length = 128 */
1312 if ((hor_active > 1280) && (ver_active > 1024))
1313 iga2_display_queue_expire_num = 16;
1314 else
1315 iga2_display_queue_expire_num =
1316 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1317 }
1318
1319 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1320 iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1321 iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1322 iga2_fifo_high_threshold =
1323 CX700_IGA2_FIFO_HIGH_THRESHOLD;
1324 iga2_display_queue_expire_num =
1325 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1326 }
1327
1328 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1329 iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1330 iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1331 iga2_fifo_high_threshold =
1332 K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1333 iga2_display_queue_expire_num =
1334 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1335 }
1336
1337 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1338 iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1339 iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1340 iga2_fifo_high_threshold =
1341 P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1342 iga2_display_queue_expire_num =
1343 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1344 }
1345
1346 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1347 iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1348 iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1349 iga2_fifo_high_threshold =
1350 P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1351 iga2_display_queue_expire_num =
1352 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1353 }
1354
1355 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1356 iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1357 iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1358 iga2_fifo_high_threshold =
1359 VX800_IGA2_FIFO_HIGH_THRESHOLD;
1360 iga2_display_queue_expire_num =
1361 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1362 }
1363
1364 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1365 /* Set Display FIFO Depath Select */
1366 reg_value =
1367 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1368 - 1;
1369 /* Patch LCD in IGA2 case */
1370 viafb_load_reg_num =
1371 display_fifo_depth_reg.
1372 iga2_fifo_depth_select_reg.reg_num;
1373 reg =
1374 display_fifo_depth_reg.
1375 iga2_fifo_depth_select_reg.reg;
1376 viafb_load_reg(reg_value,
1377 viafb_load_reg_num, reg, VIACR);
1378 } else {
1379
1380 /* Set Display FIFO Depath Select */
1381 reg_value =
1382 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1383 viafb_load_reg_num =
1384 display_fifo_depth_reg.
1385 iga2_fifo_depth_select_reg.reg_num;
1386 reg =
1387 display_fifo_depth_reg.
1388 iga2_fifo_depth_select_reg.reg;
1389 viafb_load_reg(reg_value,
1390 viafb_load_reg_num, reg, VIACR);
1391 }
1392
1393 /* Set Display FIFO Threshold Select */
1394 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1395 viafb_load_reg_num =
1396 fifo_threshold_select_reg.
1397 iga2_fifo_threshold_select_reg.reg_num;
1398 reg =
1399 fifo_threshold_select_reg.
1400 iga2_fifo_threshold_select_reg.reg;
1401 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1402
1403 /* Set FIFO High Threshold Select */
1404 reg_value =
1405 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1406 viafb_load_reg_num =
1407 fifo_high_threshold_select_reg.
1408 iga2_fifo_high_threshold_select_reg.reg_num;
1409 reg =
1410 fifo_high_threshold_select_reg.
1411 iga2_fifo_high_threshold_select_reg.reg;
1412 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1413
1414 /* Set Display Queue Expire Num */
1415 reg_value =
1416 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1417 (iga2_display_queue_expire_num);
1418 viafb_load_reg_num =
1419 display_queue_expire_num_reg.
1420 iga2_display_queue_expire_num_reg.reg_num;
1421 reg =
1422 display_queue_expire_num_reg.
1423 iga2_display_queue_expire_num_reg.reg;
1424 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1425
1426 }
1427
1428 }
1429
1430 u32 viafb_get_clk_value(int clk)
1431 {
1432 int i;
1433
1434 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1435 if (clk == pll_value[i].clk) {
1436 switch (viaparinfo->chip_info->gfx_chip_name) {
1437 case UNICHROME_CLE266:
1438 case UNICHROME_K400:
1439 return pll_value[i].cle266_pll;
1440
1441 case UNICHROME_K800:
1442 case UNICHROME_PM800:
1443 case UNICHROME_CN700:
1444 return pll_value[i].k800_pll;
1445
1446 case UNICHROME_CX700:
1447 case UNICHROME_K8M890:
1448 case UNICHROME_P4M890:
1449 case UNICHROME_P4M900:
1450 case UNICHROME_VX800:
1451 return pll_value[i].cx700_pll;
1452 }
1453 }
1454 }
1455
1456 DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1457 return 0;
1458 }
1459
1460 /* Set VCLK*/
1461 void viafb_set_vclock(u32 CLK, int set_iga)
1462 {
1463 unsigned char RegTemp;
1464
1465 /* H.W. Reset : ON */
1466 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1467
1468 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1469 /* Change D,N FOR VCLK */
1470 switch (viaparinfo->chip_info->gfx_chip_name) {
1471 case UNICHROME_CLE266:
1472 case UNICHROME_K400:
1473 viafb_write_reg(SR46, VIASR, CLK / 0x100);
1474 viafb_write_reg(SR47, VIASR, CLK % 0x100);
1475 break;
1476
1477 case UNICHROME_K800:
1478 case UNICHROME_PM800:
1479 case UNICHROME_CN700:
1480 case UNICHROME_CX700:
1481 case UNICHROME_K8M890:
1482 case UNICHROME_P4M890:
1483 case UNICHROME_P4M900:
1484 case UNICHROME_VX800:
1485 viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1486 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1487 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1488 DEBUG_MSG(KERN_INFO "\nSR45=%x",
1489 (CLK & 0xFFFF) / 0x100);
1490 viafb_write_reg(SR46, VIASR, CLK % 0x100);
1491 DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1492 break;
1493 }
1494 }
1495
1496 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1497 /* Change D,N FOR LCK */
1498 switch (viaparinfo->chip_info->gfx_chip_name) {
1499 case UNICHROME_CLE266:
1500 case UNICHROME_K400:
1501 viafb_write_reg(SR44, VIASR, CLK / 0x100);
1502 viafb_write_reg(SR45, VIASR, CLK % 0x100);
1503 break;
1504
1505 case UNICHROME_K800:
1506 case UNICHROME_PM800:
1507 case UNICHROME_CN700:
1508 case UNICHROME_CX700:
1509 case UNICHROME_K8M890:
1510 case UNICHROME_P4M890:
1511 case UNICHROME_P4M900:
1512 case UNICHROME_VX800:
1513 viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1514 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1515 viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1516 break;
1517 }
1518 }
1519
1520 /* H.W. Reset : OFF */
1521 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1522
1523 /* Reset PLL */
1524 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1525 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1526 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1527 }
1528
1529 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1530 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1531 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1532 }
1533
1534 /* Fire! */
1535 RegTemp = inb(VIARMisc);
1536 outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1537 }
1538
1539 void viafb_load_crtc_timing(struct display_timing device_timing,
1540 int set_iga)
1541 {
1542 int i;
1543 int viafb_load_reg_num = 0;
1544 int reg_value = 0;
1545 struct io_register *reg = NULL;
1546
1547 viafb_unlock_crt();
1548
1549 for (i = 0; i < 12; i++) {
1550 if (set_iga == IGA1) {
1551 switch (i) {
1552 case H_TOTAL_INDEX:
1553 reg_value =
1554 IGA1_HOR_TOTAL_FORMULA(device_timing.
1555 hor_total);
1556 viafb_load_reg_num =
1557 iga1_crtc_reg.hor_total.reg_num;
1558 reg = iga1_crtc_reg.hor_total.reg;
1559 break;
1560 case H_ADDR_INDEX:
1561 reg_value =
1562 IGA1_HOR_ADDR_FORMULA(device_timing.
1563 hor_addr);
1564 viafb_load_reg_num =
1565 iga1_crtc_reg.hor_addr.reg_num;
1566 reg = iga1_crtc_reg.hor_addr.reg;
1567 break;
1568 case H_BLANK_START_INDEX:
1569 reg_value =
1570 IGA1_HOR_BLANK_START_FORMULA
1571 (device_timing.hor_blank_start);
1572 viafb_load_reg_num =
1573 iga1_crtc_reg.hor_blank_start.reg_num;
1574 reg = iga1_crtc_reg.hor_blank_start.reg;
1575 break;
1576 case H_BLANK_END_INDEX:
1577 reg_value =
1578 IGA1_HOR_BLANK_END_FORMULA
1579 (device_timing.hor_blank_start,
1580 device_timing.hor_blank_end);
1581 viafb_load_reg_num =
1582 iga1_crtc_reg.hor_blank_end.reg_num;
1583 reg = iga1_crtc_reg.hor_blank_end.reg;
1584 break;
1585 case H_SYNC_START_INDEX:
1586 reg_value =
1587 IGA1_HOR_SYNC_START_FORMULA
1588 (device_timing.hor_sync_start);
1589 viafb_load_reg_num =
1590 iga1_crtc_reg.hor_sync_start.reg_num;
1591 reg = iga1_crtc_reg.hor_sync_start.reg;
1592 break;
1593 case H_SYNC_END_INDEX:
1594 reg_value =
1595 IGA1_HOR_SYNC_END_FORMULA
1596 (device_timing.hor_sync_start,
1597 device_timing.hor_sync_end);
1598 viafb_load_reg_num =
1599 iga1_crtc_reg.hor_sync_end.reg_num;
1600 reg = iga1_crtc_reg.hor_sync_end.reg;
1601 break;
1602 case V_TOTAL_INDEX:
1603 reg_value =
1604 IGA1_VER_TOTAL_FORMULA(device_timing.
1605 ver_total);
1606 viafb_load_reg_num =
1607 iga1_crtc_reg.ver_total.reg_num;
1608 reg = iga1_crtc_reg.ver_total.reg;
1609 break;
1610 case V_ADDR_INDEX:
1611 reg_value =
1612 IGA1_VER_ADDR_FORMULA(device_timing.
1613 ver_addr);
1614 viafb_load_reg_num =
1615 iga1_crtc_reg.ver_addr.reg_num;
1616 reg = iga1_crtc_reg.ver_addr.reg;
1617 break;
1618 case V_BLANK_START_INDEX:
1619 reg_value =
1620 IGA1_VER_BLANK_START_FORMULA
1621 (device_timing.ver_blank_start);
1622 viafb_load_reg_num =
1623 iga1_crtc_reg.ver_blank_start.reg_num;
1624 reg = iga1_crtc_reg.ver_blank_start.reg;
1625 break;
1626 case V_BLANK_END_INDEX:
1627 reg_value =
1628 IGA1_VER_BLANK_END_FORMULA
1629 (device_timing.ver_blank_start,
1630 device_timing.ver_blank_end);
1631 viafb_load_reg_num =
1632 iga1_crtc_reg.ver_blank_end.reg_num;
1633 reg = iga1_crtc_reg.ver_blank_end.reg;
1634 break;
1635 case V_SYNC_START_INDEX:
1636 reg_value =
1637 IGA1_VER_SYNC_START_FORMULA
1638 (device_timing.ver_sync_start);
1639 viafb_load_reg_num =
1640 iga1_crtc_reg.ver_sync_start.reg_num;
1641 reg = iga1_crtc_reg.ver_sync_start.reg;
1642 break;
1643 case V_SYNC_END_INDEX:
1644 reg_value =
1645 IGA1_VER_SYNC_END_FORMULA
1646 (device_timing.ver_sync_start,
1647 device_timing.ver_sync_end);
1648 viafb_load_reg_num =
1649 iga1_crtc_reg.ver_sync_end.reg_num;
1650 reg = iga1_crtc_reg.ver_sync_end.reg;
1651 break;
1652
1653 }
1654 }
1655
1656 if (set_iga == IGA2) {
1657 switch (i) {
1658 case H_TOTAL_INDEX:
1659 reg_value =
1660 IGA2_HOR_TOTAL_FORMULA(device_timing.
1661 hor_total);
1662 viafb_load_reg_num =
1663 iga2_crtc_reg.hor_total.reg_num;
1664 reg = iga2_crtc_reg.hor_total.reg;
1665 break;
1666 case H_ADDR_INDEX:
1667 reg_value =
1668 IGA2_HOR_ADDR_FORMULA(device_timing.
1669 hor_addr);
1670 viafb_load_reg_num =
1671 iga2_crtc_reg.hor_addr.reg_num;
1672 reg = iga2_crtc_reg.hor_addr.reg;
1673 break;
1674 case H_BLANK_START_INDEX:
1675 reg_value =
1676 IGA2_HOR_BLANK_START_FORMULA
1677 (device_timing.hor_blank_start);
1678 viafb_load_reg_num =
1679 iga2_crtc_reg.hor_blank_start.reg_num;
1680 reg = iga2_crtc_reg.hor_blank_start.reg;
1681 break;
1682 case H_BLANK_END_INDEX:
1683 reg_value =
1684 IGA2_HOR_BLANK_END_FORMULA
1685 (device_timing.hor_blank_start,
1686 device_timing.hor_blank_end);
1687 viafb_load_reg_num =
1688 iga2_crtc_reg.hor_blank_end.reg_num;
1689 reg = iga2_crtc_reg.hor_blank_end.reg;
1690 break;
1691 case H_SYNC_START_INDEX:
1692 reg_value =
1693 IGA2_HOR_SYNC_START_FORMULA
1694 (device_timing.hor_sync_start);
1695 if (UNICHROME_CN700 <=
1696 viaparinfo->chip_info->gfx_chip_name)
1697 viafb_load_reg_num =
1698 iga2_crtc_reg.hor_sync_start.
1699 reg_num;
1700 else
1701 viafb_load_reg_num = 3;
1702 reg = iga2_crtc_reg.hor_sync_start.reg;
1703 break;
1704 case H_SYNC_END_INDEX:
1705 reg_value =
1706 IGA2_HOR_SYNC_END_FORMULA
1707 (device_timing.hor_sync_start,
1708 device_timing.hor_sync_end);
1709 viafb_load_reg_num =
1710 iga2_crtc_reg.hor_sync_end.reg_num;
1711 reg = iga2_crtc_reg.hor_sync_end.reg;
1712 break;
1713 case V_TOTAL_INDEX:
1714 reg_value =
1715 IGA2_VER_TOTAL_FORMULA(device_timing.
1716 ver_total);
1717 viafb_load_reg_num =
1718 iga2_crtc_reg.ver_total.reg_num;
1719 reg = iga2_crtc_reg.ver_total.reg;
1720 break;
1721 case V_ADDR_INDEX:
1722 reg_value =
1723 IGA2_VER_ADDR_FORMULA(device_timing.
1724 ver_addr);
1725 viafb_load_reg_num =
1726 iga2_crtc_reg.ver_addr.reg_num;
1727 reg = iga2_crtc_reg.ver_addr.reg;
1728 break;
1729 case V_BLANK_START_INDEX:
1730 reg_value =
1731 IGA2_VER_BLANK_START_FORMULA
1732 (device_timing.ver_blank_start);
1733 viafb_load_reg_num =
1734 iga2_crtc_reg.ver_blank_start.reg_num;
1735 reg = iga2_crtc_reg.ver_blank_start.reg;
1736 break;
1737 case V_BLANK_END_INDEX:
1738 reg_value =
1739 IGA2_VER_BLANK_END_FORMULA
1740 (device_timing.ver_blank_start,
1741 device_timing.ver_blank_end);
1742 viafb_load_reg_num =
1743 iga2_crtc_reg.ver_blank_end.reg_num;
1744 reg = iga2_crtc_reg.ver_blank_end.reg;
1745 break;
1746 case V_SYNC_START_INDEX:
1747 reg_value =
1748 IGA2_VER_SYNC_START_FORMULA
1749 (device_timing.ver_sync_start);
1750 viafb_load_reg_num =
1751 iga2_crtc_reg.ver_sync_start.reg_num;
1752 reg = iga2_crtc_reg.ver_sync_start.reg;
1753 break;
1754 case V_SYNC_END_INDEX:
1755 reg_value =
1756 IGA2_VER_SYNC_END_FORMULA
1757 (device_timing.ver_sync_start,
1758 device_timing.ver_sync_end);
1759 viafb_load_reg_num =
1760 iga2_crtc_reg.ver_sync_end.reg_num;
1761 reg = iga2_crtc_reg.ver_sync_end.reg;
1762 break;
1763
1764 }
1765 }
1766 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1767 }
1768
1769 viafb_lock_crt();
1770 }
1771
1772 void viafb_set_color_depth(int bpp_byte, int set_iga)
1773 {
1774 if (set_iga == IGA1) {
1775 switch (bpp_byte) {
1776 case MODE_8BPP:
1777 viafb_write_reg_mask(SR15, VIASR, 0x22, 0x7E);
1778 break;
1779 case MODE_16BPP:
1780 viafb_write_reg_mask(SR15, VIASR, 0xB6, 0xFE);
1781 break;
1782 case MODE_32BPP:
1783 viafb_write_reg_mask(SR15, VIASR, 0xAE, 0xFE);
1784 break;
1785 }
1786 } else {
1787 switch (bpp_byte) {
1788 case MODE_8BPP:
1789 viafb_write_reg_mask(CR67, VIACR, 0x00, BIT6 + BIT7);
1790 break;
1791 case MODE_16BPP:
1792 viafb_write_reg_mask(CR67, VIACR, 0x40, BIT6 + BIT7);
1793 break;
1794 case MODE_32BPP:
1795 viafb_write_reg_mask(CR67, VIACR, 0xC0, BIT6 + BIT7);
1796 break;
1797 }
1798 }
1799 }
1800
1801 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1802 int mode_index, int bpp_byte, int set_iga)
1803 {
1804 struct VideoModeTable *video_mode;
1805 struct display_timing crt_reg;
1806 int i;
1807 int index = 0;
1808 int h_addr, v_addr;
1809 u32 pll_D_N;
1810
1811 video_mode = &CLE266Modes[search_mode_setting(mode_index)];
1812
1813 for (i = 0; i < video_mode->mode_array; i++) {
1814 index = i;
1815
1816 if (crt_table[i].refresh_rate == viaparinfo->
1817 crt_setting_info->refresh_rate)
1818 break;
1819 }
1820
1821 crt_reg = crt_table[index].crtc;
1822
1823 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1824 /* So we would delete border. */
1825 if ((viafb_LCD_ON | viafb_DVI_ON) && (mode_index == VIA_RES_640X480)
1826 && (viaparinfo->crt_setting_info->refresh_rate == 60)) {
1827 /* The border is 8 pixels. */
1828 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1829
1830 /* Blanking time should add left and right borders. */
1831 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1832 }
1833
1834 h_addr = crt_reg.hor_addr;
1835 v_addr = crt_reg.ver_addr;
1836
1837 /* update polarity for CRT timing */
1838 if (crt_table[index].h_sync_polarity == NEGATIVE) {
1839 if (crt_table[index].v_sync_polarity == NEGATIVE)
1840 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1841 (BIT6 + BIT7), VIAWMisc);
1842 else
1843 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1844 VIAWMisc);
1845 } else {
1846 if (crt_table[index].v_sync_polarity == NEGATIVE)
1847 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1848 VIAWMisc);
1849 else
1850 outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1851 }
1852
1853 if (set_iga == IGA1) {
1854 viafb_unlock_crt();
1855 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
1856 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1857 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1858 }
1859
1860 switch (set_iga) {
1861 case IGA1:
1862 viafb_load_crtc_timing(crt_reg, IGA1);
1863 break;
1864 case IGA2:
1865 viafb_load_crtc_timing(crt_reg, IGA2);
1866 break;
1867 }
1868
1869 load_fix_bit_crtc_reg();
1870 viafb_lock_crt();
1871 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1872 viafb_load_offset_reg(h_addr, bpp_byte, set_iga);
1873 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1874
1875 /* load FIFO */
1876 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1877 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1878 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1879
1880 /* load SR Register About Memory and Color part */
1881 viafb_set_color_depth(bpp_byte, set_iga);
1882
1883 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1884 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1885 viafb_set_vclock(pll_D_N, set_iga);
1886
1887 }
1888
1889 void viafb_init_chip_info(void)
1890 {
1891 init_gfx_chip_info();
1892 init_tmds_chip_info();
1893 init_lvds_chip_info();
1894
1895 viaparinfo->crt_setting_info->iga_path = IGA1;
1896 viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1897
1898 /*Set IGA path for each device */
1899 viafb_set_iga_path();
1900
1901 viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1902 viaparinfo->lvds_setting_info->get_lcd_size_method =
1903 GET_LCD_SIZE_BY_USER_SETTING;
1904 viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1905 viaparinfo->lvds_setting_info2->display_method =
1906 viaparinfo->lvds_setting_info->display_method;
1907 viaparinfo->lvds_setting_info2->lcd_mode =
1908 viaparinfo->lvds_setting_info->lcd_mode;
1909 }
1910
1911 void viafb_update_device_setting(int hres, int vres,
1912 int bpp, int vmode_refresh, int flag)
1913 {
1914 if (flag == 0) {
1915 viaparinfo->crt_setting_info->h_active = hres;
1916 viaparinfo->crt_setting_info->v_active = vres;
1917 viaparinfo->crt_setting_info->bpp = bpp;
1918 viaparinfo->crt_setting_info->refresh_rate =
1919 vmode_refresh;
1920
1921 viaparinfo->tmds_setting_info->h_active = hres;
1922 viaparinfo->tmds_setting_info->v_active = vres;
1923 viaparinfo->tmds_setting_info->bpp = bpp;
1924 viaparinfo->tmds_setting_info->refresh_rate =
1925 vmode_refresh;
1926
1927 viaparinfo->lvds_setting_info->h_active = hres;
1928 viaparinfo->lvds_setting_info->v_active = vres;
1929 viaparinfo->lvds_setting_info->bpp = bpp;
1930 viaparinfo->lvds_setting_info->refresh_rate =
1931 vmode_refresh;
1932 viaparinfo->lvds_setting_info2->h_active = hres;
1933 viaparinfo->lvds_setting_info2->v_active = vres;
1934 viaparinfo->lvds_setting_info2->bpp = bpp;
1935 viaparinfo->lvds_setting_info2->refresh_rate =
1936 vmode_refresh;
1937 } else {
1938
1939 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1940 viaparinfo->tmds_setting_info->h_active = hres;
1941 viaparinfo->tmds_setting_info->v_active = vres;
1942 viaparinfo->tmds_setting_info->bpp = bpp;
1943 viaparinfo->tmds_setting_info->refresh_rate =
1944 vmode_refresh;
1945 }
1946
1947 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1948 viaparinfo->lvds_setting_info->h_active = hres;
1949 viaparinfo->lvds_setting_info->v_active = vres;
1950 viaparinfo->lvds_setting_info->bpp = bpp;
1951 viaparinfo->lvds_setting_info->refresh_rate =
1952 vmode_refresh;
1953 }
1954 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1955 viaparinfo->lvds_setting_info2->h_active = hres;
1956 viaparinfo->lvds_setting_info2->v_active = vres;
1957 viaparinfo->lvds_setting_info2->bpp = bpp;
1958 viaparinfo->lvds_setting_info2->refresh_rate =
1959 vmode_refresh;
1960 }
1961 }
1962 }
1963
1964 static void init_gfx_chip_info(void)
1965 {
1966 struct pci_dev *pdev = NULL;
1967 u32 i;
1968 u8 tmp;
1969
1970 /* Indentify GFX Chip Name */
1971 for (i = 0; pciidlist[i].vendor != 0; i++) {
1972 pdev = pci_get_device(pciidlist[i].vendor,
1973 pciidlist[i].device, 0);
1974 if (pdev)
1975 break;
1976 }
1977
1978 if (!pciidlist[i].vendor)
1979 return ;
1980
1981 viaparinfo->chip_info->gfx_chip_name = pciidlist[i].chip_index;
1982
1983 /* Check revision of CLE266 Chip */
1984 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1985 /* CR4F only define in CLE266.CX chip */
1986 tmp = viafb_read_reg(VIACR, CR4F);
1987 viafb_write_reg(CR4F, VIACR, 0x55);
1988 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1989 viaparinfo->chip_info->gfx_chip_revision =
1990 CLE266_REVISION_AX;
1991 else
1992 viaparinfo->chip_info->gfx_chip_revision =
1993 CLE266_REVISION_CX;
1994 /* restore orignal CR4F value */
1995 viafb_write_reg(CR4F, VIACR, tmp);
1996 }
1997
1998 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1999 tmp = viafb_read_reg(VIASR, SR43);
2000 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2001 if (tmp & 0x02) {
2002 viaparinfo->chip_info->gfx_chip_revision =
2003 CX700_REVISION_700M2;
2004 } else if (tmp & 0x40) {
2005 viaparinfo->chip_info->gfx_chip_revision =
2006 CX700_REVISION_700M;
2007 } else {
2008 viaparinfo->chip_info->gfx_chip_revision =
2009 CX700_REVISION_700;
2010 }
2011 }
2012
2013 pci_dev_put(pdev);
2014 }
2015
2016 static void init_tmds_chip_info(void)
2017 {
2018 viafb_tmds_trasmitter_identify();
2019
2020 if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2021 output_interface) {
2022 switch (viaparinfo->chip_info->gfx_chip_name) {
2023 case UNICHROME_CX700:
2024 {
2025 /* we should check support by hardware layout.*/
2026 if ((viafb_display_hardware_layout ==
2027 HW_LAYOUT_DVI_ONLY)
2028 || (viafb_display_hardware_layout ==
2029 HW_LAYOUT_LCD_DVI)) {
2030 viaparinfo->chip_info->tmds_chip_info.
2031 output_interface = INTERFACE_TMDS;
2032 } else {
2033 viaparinfo->chip_info->tmds_chip_info.
2034 output_interface =
2035 INTERFACE_NONE;
2036 }
2037 break;
2038 }
2039 case UNICHROME_K8M890:
2040 case UNICHROME_P4M900:
2041 case UNICHROME_P4M890:
2042 /* TMDS on PCIE, we set DFPLOW as default. */
2043 viaparinfo->chip_info->tmds_chip_info.output_interface =
2044 INTERFACE_DFP_LOW;
2045 break;
2046 default:
2047 {
2048 /* set DVP1 default for DVI */
2049 viaparinfo->chip_info->tmds_chip_info
2050 .output_interface = INTERFACE_DVP1;
2051 }
2052 }
2053 }
2054
2055 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2056 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2057 viaparinfo->tmds_setting_info->get_dvi_size_method =
2058 GET_DVI_SIZE_BY_VGA_BIOS;
2059 viafb_init_dvi_size();
2060 }
2061
2062 static void init_lvds_chip_info(void)
2063 {
2064 if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2065 viaparinfo->lvds_setting_info->get_lcd_size_method =
2066 GET_LCD_SIZE_BY_VGA_BIOS;
2067 else
2068 viaparinfo->lvds_setting_info->get_lcd_size_method =
2069 GET_LCD_SIZE_BY_USER_SETTING;
2070
2071 viafb_lvds_trasmitter_identify();
2072 viafb_init_lcd_size();
2073 viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2074 viaparinfo->lvds_setting_info);
2075 if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2076 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2077 lvds_chip_info2, viaparinfo->lvds_setting_info2);
2078 }
2079 /*If CX700,two singel LCD, we need to reassign
2080 LCD interface to different LVDS port */
2081 if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2082 && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2083 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2084 lvds_chip_name) && (INTEGRATED_LVDS ==
2085 viaparinfo->chip_info->
2086 lvds_chip_info2.lvds_chip_name)) {
2087 viaparinfo->chip_info->lvds_chip_info.output_interface =
2088 INTERFACE_LVDS0;
2089 viaparinfo->chip_info->lvds_chip_info2.
2090 output_interface =
2091 INTERFACE_LVDS1;
2092 }
2093 }
2094
2095 DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2096 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2097 DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2098 viaparinfo->chip_info->lvds_chip_info.output_interface);
2099 DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2100 viaparinfo->chip_info->lvds_chip_info.output_interface);
2101 }
2102
2103 void viafb_init_dac(int set_iga)
2104 {
2105 int i;
2106 u8 tmp;
2107
2108 if (set_iga == IGA1) {
2109 /* access Primary Display's LUT */
2110 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2111 /* turn off LCK */
2112 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2113 for (i = 0; i < 256; i++) {
2114 write_dac_reg(i, palLUT_table[i].red,
2115 palLUT_table[i].green,
2116 palLUT_table[i].blue);
2117 }
2118 /* turn on LCK */
2119 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2120 } else {
2121 tmp = viafb_read_reg(VIACR, CR6A);
2122 /* access Secondary Display's LUT */
2123 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2124 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2125 for (i = 0; i < 256; i++) {
2126 write_dac_reg(i, palLUT_table[i].red,
2127 palLUT_table[i].green,
2128 palLUT_table[i].blue);
2129 }
2130 /* set IGA1 DAC for default */
2131 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2132 viafb_write_reg(CR6A, VIACR, tmp);
2133 }
2134 }
2135
2136 static void device_screen_off(void)
2137 {
2138 /* turn off CRT screen (IGA1) */
2139 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2140 }
2141
2142 static void device_screen_on(void)
2143 {
2144 /* turn on CRT screen (IGA1) */
2145 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2146 }
2147
2148 static void set_display_channel(void)
2149 {
2150 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2151 is keeped on lvds_setting_info2 */
2152 if (viafb_LCD2_ON &&
2153 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2154 /* For dual channel LCD: */
2155 /* Set to Dual LVDS channel. */
2156 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2157 } else if (viafb_LCD_ON && viafb_DVI_ON) {
2158 /* For LCD+DFP: */
2159 /* Set to LVDS1 + TMDS channel. */
2160 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2161 } else if (viafb_DVI_ON) {
2162 /* Set to single TMDS channel. */
2163 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2164 } else if (viafb_LCD_ON) {
2165 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2166 /* For dual channel LCD: */
2167 /* Set to Dual LVDS channel. */
2168 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2169 } else {
2170 /* Set to LVDS0 + LVDS1 channel. */
2171 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2172 }
2173 }
2174 }
2175
2176 int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2177 int vmode_index1, int hor_res1, int ver_res1, int video_bpp1)
2178 {
2179 int i, j;
2180 int port;
2181 u8 value, index, mask;
2182 struct VideoModeTable *vmode_tbl;
2183 struct crt_mode_table *crt_timing;
2184 struct VideoModeTable *vmode_tbl1 = NULL;
2185 struct crt_mode_table *crt_timing1 = NULL;
2186
2187 DEBUG_MSG(KERN_INFO "Set Mode!!\n");
2188 DEBUG_MSG(KERN_INFO
2189 "vmode_index=%d hor_res=%d ver_res=%d video_bpp=%d\n",
2190 vmode_index, hor_res, ver_res, video_bpp);
2191
2192 device_screen_off();
2193 vmode_tbl = &CLE266Modes[search_mode_setting(vmode_index)];
2194 crt_timing = vmode_tbl->crtc;
2195
2196 if (viafb_SAMM_ON == 1) {
2197 vmode_tbl1 = &CLE266Modes[search_mode_setting(vmode_index1)];
2198 crt_timing1 = vmode_tbl1->crtc;
2199 }
2200
2201 inb(VIAStatus);
2202 outb(0x00, VIAAR);
2203
2204 /* Write Common Setting for Video Mode */
2205 switch (viaparinfo->chip_info->gfx_chip_name) {
2206 case UNICHROME_CLE266:
2207 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2208 break;
2209
2210 case UNICHROME_K400:
2211 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2212 break;
2213
2214 case UNICHROME_K800:
2215 case UNICHROME_PM800:
2216 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2217 break;
2218
2219 case UNICHROME_CN700:
2220 case UNICHROME_K8M890:
2221 case UNICHROME_P4M890:
2222 case UNICHROME_P4M900:
2223 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2224 break;
2225
2226 case UNICHROME_CX700:
2227 case UNICHROME_VX800:
2228 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2229 break;
2230 }
2231
2232 device_off();
2233
2234 /* Fill VPIT Parameters */
2235 /* Write Misc Register */
2236 outb(VPIT.Misc, VIAWMisc);
2237
2238 /* Write Sequencer */
2239 for (i = 1; i <= StdSR; i++) {
2240 outb(i, VIASR);
2241 outb(VPIT.SR[i - 1], VIASR + 1);
2242 }
2243
2244 viafb_set_primary_address(0);
2245 viafb_set_secondary_address(viafb_SAMM_ON ? viafb_second_offset : 0);
2246 viafb_set_iga_path();
2247
2248 /* Write CRTC */
2249 viafb_fill_crtc_timing(crt_timing, vmode_index, video_bpp / 8, IGA1);
2250
2251 /* Write Graphic Controller */
2252 for (i = 0; i < StdGR; i++) {
2253 outb(i, VIAGR);
2254 outb(VPIT.GR[i], VIAGR + 1);
2255 }
2256
2257 /* Write Attribute Controller */
2258 for (i = 0; i < StdAR; i++) {
2259 inb(VIAStatus);
2260 outb(i, VIAAR);
2261 outb(VPIT.AR[i], VIAAR);
2262 }
2263
2264 inb(VIAStatus);
2265 outb(0x20, VIAAR);
2266
2267 /* Update Patch Register */
2268
2269 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2270 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)) {
2271 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2272 if (res_patch_table[i].mode_index == vmode_index) {
2273 for (j = 0;
2274 j < res_patch_table[i].table_length; j++) {
2275 index =
2276 res_patch_table[i].
2277 io_reg_table[j].index;
2278 port =
2279 res_patch_table[i].
2280 io_reg_table[j].port;
2281 value =
2282 res_patch_table[i].
2283 io_reg_table[j].value;
2284 mask =
2285 res_patch_table[i].
2286 io_reg_table[j].mask;
2287 viafb_write_reg_mask(index, port, value,
2288 mask);
2289 }
2290 }
2291 }
2292 }
2293
2294 if (viafb_SAMM_ON == 1) {
2295 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2296 || (viaparinfo->chip_info->gfx_chip_name ==
2297 UNICHROME_K400)) {
2298 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2299 if (res_patch_table[i].mode_index ==
2300 vmode_index1) {
2301 for (j = 0;
2302 j <
2303 res_patch_table[i].
2304 table_length; j++) {
2305 index =
2306 res_patch_table[i].
2307 io_reg_table[j].index;
2308 port =
2309 res_patch_table[i].
2310 io_reg_table[j].port;
2311 value =
2312 res_patch_table[i].
2313 io_reg_table[j].value;
2314 mask =
2315 res_patch_table[i].
2316 io_reg_table[j].mask;
2317 viafb_write_reg_mask(index,
2318 port, value, mask);
2319 }
2320 }
2321 }
2322 }
2323 }
2324
2325 /* Update Refresh Rate Setting */
2326
2327 /* Clear On Screen */
2328
2329 /* CRT set mode */
2330 if (viafb_CRT_ON) {
2331 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2332 IGA2)) {
2333 viafb_fill_crtc_timing(crt_timing1, vmode_index1,
2334 video_bpp1 / 8,
2335 viaparinfo->crt_setting_info->iga_path);
2336 } else {
2337 viafb_fill_crtc_timing(crt_timing, vmode_index,
2338 video_bpp / 8,
2339 viaparinfo->crt_setting_info->iga_path);
2340 }
2341
2342 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2343
2344 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2345 to 8 alignment (1368),there is several pixels (2 pixels)
2346 on right side of screen. */
2347 if (hor_res % 8) {
2348 viafb_unlock_crt();
2349 viafb_write_reg(CR02, VIACR,
2350 viafb_read_reg(VIACR, CR02) - 1);
2351 viafb_lock_crt();
2352 }
2353 }
2354
2355 if (viafb_DVI_ON) {
2356 if (viafb_SAMM_ON &&
2357 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2358 viafb_dvi_set_mode(viafb_get_mode_index
2359 (viaparinfo->tmds_setting_info->h_active,
2360 viaparinfo->tmds_setting_info->
2361 v_active),
2362 video_bpp1, viaparinfo->
2363 tmds_setting_info->iga_path);
2364 } else {
2365 viafb_dvi_set_mode(viafb_get_mode_index
2366 (viaparinfo->tmds_setting_info->h_active,
2367 viaparinfo->
2368 tmds_setting_info->v_active),
2369 video_bpp, viaparinfo->
2370 tmds_setting_info->iga_path);
2371 }
2372 }
2373
2374 if (viafb_LCD_ON) {
2375 if (viafb_SAMM_ON &&
2376 (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2377 viaparinfo->lvds_setting_info->bpp = video_bpp1;
2378 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2379 lvds_setting_info,
2380 &viaparinfo->chip_info->lvds_chip_info);
2381 } else {
2382 /* IGA1 doesn't have LCD scaling, so set it center. */
2383 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2384 viaparinfo->lvds_setting_info->display_method =
2385 LCD_CENTERING;
2386 }
2387 viaparinfo->lvds_setting_info->bpp = video_bpp;
2388 viafb_lcd_set_mode(crt_timing, viaparinfo->
2389 lvds_setting_info,
2390 &viaparinfo->chip_info->lvds_chip_info);
2391 }
2392 }
2393 if (viafb_LCD2_ON) {
2394 if (viafb_SAMM_ON &&
2395 (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2396 viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2397 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2398 lvds_setting_info2,
2399 &viaparinfo->chip_info->lvds_chip_info2);
2400 } else {
2401 /* IGA1 doesn't have LCD scaling, so set it center. */
2402 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2403 viaparinfo->lvds_setting_info2->display_method =
2404 LCD_CENTERING;
2405 }
2406 viaparinfo->lvds_setting_info2->bpp = video_bpp;
2407 viafb_lcd_set_mode(crt_timing, viaparinfo->
2408 lvds_setting_info2,
2409 &viaparinfo->chip_info->lvds_chip_info2);
2410 }
2411 }
2412
2413 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2414 && (viafb_LCD_ON || viafb_DVI_ON))
2415 set_display_channel();
2416
2417 /* If set mode normally, save resolution information for hot-plug . */
2418 if (!viafb_hotplug) {
2419 viafb_hotplug_Xres = hor_res;
2420 viafb_hotplug_Yres = ver_res;
2421 viafb_hotplug_bpp = video_bpp;
2422 viafb_hotplug_refresh = viafb_refresh;
2423
2424 if (viafb_DVI_ON)
2425 viafb_DeviceStatus = DVI_Device;
2426 else
2427 viafb_DeviceStatus = CRT_Device;
2428 }
2429 device_on();
2430
2431 if (viafb_SAMM_ON == 1)
2432 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2433
2434 device_screen_on();
2435 return 1;
2436 }
2437
2438 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2439 {
2440 int i;
2441
2442 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2443 if ((hres == res_map_refresh_tbl[i].hres)
2444 && (vres == res_map_refresh_tbl[i].vres)
2445 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2446 return res_map_refresh_tbl[i].pixclock;
2447 }
2448 return RES_640X480_60HZ_PIXCLOCK;
2449
2450 }
2451
2452 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2453 {
2454 #define REFRESH_TOLERANCE 3
2455 int i, nearest = -1, diff = REFRESH_TOLERANCE;
2456 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2457 if ((hres == res_map_refresh_tbl[i].hres)
2458 && (vres == res_map_refresh_tbl[i].vres)
2459 && (diff > (abs(long_refresh -
2460 res_map_refresh_tbl[i].vmode_refresh)))) {
2461 diff = abs(long_refresh - res_map_refresh_tbl[i].
2462 vmode_refresh);
2463 nearest = i;
2464 }
2465 }
2466 #undef REFRESH_TOLERANCE
2467 if (nearest > 0)
2468 return res_map_refresh_tbl[nearest].vmode_refresh;
2469 return 60;
2470 }
2471
2472 static void device_off(void)
2473 {
2474 viafb_crt_disable();
2475 viafb_dvi_disable();
2476 viafb_lcd_disable();
2477 }
2478
2479 static void device_on(void)
2480 {
2481 if (viafb_CRT_ON == 1)
2482 viafb_crt_enable();
2483 if (viafb_DVI_ON == 1)
2484 viafb_dvi_enable();
2485 if (viafb_LCD_ON == 1)
2486 viafb_lcd_enable();
2487 }
2488
2489 void viafb_crt_disable(void)
2490 {
2491 viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2492 }
2493
2494 void viafb_crt_enable(void)
2495 {
2496 viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2497 }
2498
2499 void viafb_get_mmio_info(unsigned long *mmio_base, u32 *mmio_len)
2500 {
2501 struct pci_dev *pdev = NULL;
2502 u32 vendor, device;
2503 u32 i;
2504
2505 for (i = 0; pciidlist[i].vendor != 0; i++)
2506 if (viaparinfo->chip_info->gfx_chip_name ==
2507 pciidlist[i].chip_index)
2508 break;
2509
2510 if (!pciidlist[i].vendor)
2511 return ;
2512
2513 vendor = pciidlist[i].vendor;
2514 device = pciidlist[i].device;
2515
2516 pdev = pci_get_device(vendor, device, NULL);
2517
2518 if (!pdev) {
2519 *mmio_base = 0;
2520 *mmio_len = 0;
2521 return ;
2522 }
2523
2524 *mmio_base = pci_resource_start(pdev, 1);
2525 *mmio_len = pci_resource_len(pdev, 1);
2526
2527 pci_dev_put(pdev);
2528 }
2529
2530 static void enable_second_display_channel(void)
2531 {
2532 /* to enable second display channel. */
2533 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2534 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2535 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2536 }
2537
2538 static void disable_second_display_channel(void)
2539 {
2540 /* to disable second display channel. */
2541 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2542 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2543 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2544 }
2545
2546 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len)
2547 {
2548 struct pci_dev *pdev = NULL;
2549 u32 vendor, device;
2550 u32 i;
2551
2552 for (i = 0; pciidlist[i].vendor != 0; i++)
2553 if (viaparinfo->chip_info->gfx_chip_name ==
2554 pciidlist[i].chip_index)
2555 break;
2556
2557 if (!pciidlist[i].vendor)
2558 return ;
2559
2560 vendor = pciidlist[i].vendor;
2561 device = pciidlist[i].device;
2562
2563 pdev = pci_get_device(vendor, device, NULL);
2564
2565 if (!pdev) {
2566 *fb_base = viafb_read_reg(VIASR, SR30) << 24;
2567 *fb_len = viafb_get_memsize();
2568 DEBUG_MSG(KERN_INFO "Get FB info from SR30!\n");
2569 DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
2570 DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
2571 return ;
2572 }
2573
2574 *fb_base = (unsigned int)pci_resource_start(pdev, 0);
2575 *fb_len = get_fb_size_from_pci();
2576 DEBUG_MSG(KERN_INFO "Get FB info from PCI system!\n");
2577 DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
2578 DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
2579
2580 pci_dev_put(pdev);
2581 }
2582
2583 static int get_fb_size_from_pci(void)
2584 {
2585 unsigned long configid, deviceid, FBSize = 0;
2586 int VideoMemSize;
2587 int DeviceFound = false;
2588
2589 for (configid = 0x80000000; configid < 0x80010800; configid += 0x100) {
2590 outl(configid, (unsigned long)0xCF8);
2591 deviceid = (inl((unsigned long)0xCFC) >> 16) & 0xffff;
2592
2593 switch (deviceid) {
2594 case CLE266:
2595 case KM400:
2596 outl(configid + 0xE0, (unsigned long)0xCF8);
2597 FBSize = inl((unsigned long)0xCFC);
2598 DeviceFound = true; /* Found device id */
2599 break;
2600
2601 case CN400_FUNCTION3:
2602 case CN700_FUNCTION3:
2603 case CX700_FUNCTION3:
2604 case KM800_FUNCTION3:
2605 case KM890_FUNCTION3:
2606 case P4M890_FUNCTION3:
2607 case P4M900_FUNCTION3:
2608 case VX800_FUNCTION3:
2609 /*case CN750_FUNCTION3: */
2610 outl(configid + 0xA0, (unsigned long)0xCF8);
2611 FBSize = inl((unsigned long)0xCFC);
2612 DeviceFound = true; /* Found device id */
2613 break;
2614
2615 default:
2616 break;
2617 }
2618
2619 if (DeviceFound)
2620 break;
2621 }
2622
2623 DEBUG_MSG(KERN_INFO "Device ID = %lx\n", deviceid);
2624
2625 FBSize = FBSize & 0x00007000;
2626 DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2627
2628 if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2629 switch (FBSize) {
2630 case 0x00004000:
2631 VideoMemSize = (16 << 20); /*16M */
2632 break;
2633
2634 case 0x00005000:
2635 VideoMemSize = (32 << 20); /*32M */
2636 break;
2637
2638 case 0x00006000:
2639 VideoMemSize = (64 << 20); /*64M */
2640 break;
2641
2642 default:
2643 VideoMemSize = (32 << 20); /*32M */
2644 break;
2645 }
2646 } else {
2647 switch (FBSize) {
2648 case 0x00001000:
2649 VideoMemSize = (8 << 20); /*8M */
2650 break;
2651
2652 case 0x00002000:
2653 VideoMemSize = (16 << 20); /*16M */
2654 break;
2655
2656 case 0x00003000:
2657 VideoMemSize = (32 << 20); /*32M */
2658 break;
2659
2660 case 0x00004000:
2661 VideoMemSize = (64 << 20); /*64M */
2662 break;
2663
2664 case 0x00005000:
2665 VideoMemSize = (128 << 20); /*128M */
2666 break;
2667
2668 case 0x00006000:
2669 VideoMemSize = (256 << 20); /*256M */
2670 break;
2671
2672 default:
2673 VideoMemSize = (32 << 20); /*32M */
2674 break;
2675 }
2676 }
2677
2678 return VideoMemSize;
2679 }
2680
2681 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2682 *p_gfx_dpa_setting)
2683 {
2684 switch (output_interface) {
2685 case INTERFACE_DVP0:
2686 {
2687 /* DVP0 Clock Polarity and Adjust: */
2688 viafb_write_reg_mask(CR96, VIACR,
2689 p_gfx_dpa_setting->DVP0, 0x0F);
2690
2691 /* DVP0 Clock and Data Pads Driving: */
2692 viafb_write_reg_mask(SR1E, VIASR,
2693 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2694 viafb_write_reg_mask(SR2A, VIASR,
2695 p_gfx_dpa_setting->DVP0ClockDri_S1,
2696 BIT4);
2697 viafb_write_reg_mask(SR1B, VIASR,
2698 p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2699 viafb_write_reg_mask(SR2A, VIASR,
2700 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2701 break;
2702 }
2703
2704 case INTERFACE_DVP1:
2705 {
2706 /* DVP1 Clock Polarity and Adjust: */
2707 viafb_write_reg_mask(CR9B, VIACR,
2708 p_gfx_dpa_setting->DVP1, 0x0F);
2709
2710 /* DVP1 Clock and Data Pads Driving: */
2711 viafb_write_reg_mask(SR65, VIASR,
2712 p_gfx_dpa_setting->DVP1Driving, 0x0F);
2713 break;
2714 }
2715
2716 case INTERFACE_DFP_HIGH:
2717 {
2718 viafb_write_reg_mask(CR97, VIACR,
2719 p_gfx_dpa_setting->DFPHigh, 0x0F);
2720 break;
2721 }
2722
2723 case INTERFACE_DFP_LOW:
2724 {
2725 viafb_write_reg_mask(CR99, VIACR,
2726 p_gfx_dpa_setting->DFPLow, 0x0F);
2727 break;
2728 }
2729
2730 case INTERFACE_DFP:
2731 {
2732 viafb_write_reg_mask(CR97, VIACR,
2733 p_gfx_dpa_setting->DFPHigh, 0x0F);
2734 viafb_write_reg_mask(CR99, VIACR,
2735 p_gfx_dpa_setting->DFPLow, 0x0F);
2736 break;
2737 }
2738 }
2739 }
2740
2741 void viafb_memory_pitch_patch(struct fb_info *info)
2742 {
2743 if (info->var.xres != info->var.xres_virtual) {
2744 viafb_load_offset_reg(info->var.xres_virtual,
2745 info->var.bits_per_pixel >> 3, IGA1);
2746
2747 if (viafb_SAMM_ON) {
2748 viafb_load_offset_reg(viafb_second_virtual_xres,
2749 viafb_bpp1 >> 3,
2750 IGA2);
2751 } else {
2752 viafb_load_offset_reg(info->var.xres_virtual,
2753 info->var.bits_per_pixel >> 3, IGA2);
2754 }
2755
2756 }
2757 }
2758
2759 /*According var's xres, yres fill var's other timing information*/
2760 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2761 int mode_index)
2762 {
2763 struct VideoModeTable *vmode_tbl = NULL;
2764 struct crt_mode_table *crt_timing = NULL;
2765 struct display_timing crt_reg;
2766 int i = 0, index = 0;
2767 vmode_tbl = &CLE266Modes[search_mode_setting(mode_index)];
2768 crt_timing = vmode_tbl->crtc;
2769 for (i = 0; i < vmode_tbl->mode_array; i++) {
2770 index = i;
2771 if (crt_timing[i].refresh_rate == refresh)
2772 break;
2773 }
2774
2775 crt_reg = crt_timing[index].crtc;
2776 switch (var->bits_per_pixel) {
2777 case 8:
2778 var->red.offset = 0;
2779 var->green.offset = 0;
2780 var->blue.offset = 0;
2781 var->red.length = 6;
2782 var->green.length = 6;
2783 var->blue.length = 6;
2784 break;
2785 case 16:
2786 var->red.offset = 11;
2787 var->green.offset = 5;
2788 var->blue.offset = 0;
2789 var->red.length = 5;
2790 var->green.length = 6;
2791 var->blue.length = 5;
2792 break;
2793 case 32:
2794 var->red.offset = 16;
2795 var->green.offset = 8;
2796 var->blue.offset = 0;
2797 var->red.length = 8;
2798 var->green.length = 8;
2799 var->blue.length = 8;
2800 break;
2801 default:
2802 /* never happed, put here to keep consistent */
2803 break;
2804 }
2805
2806 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2807 var->left_margin =
2808 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2809 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2810 var->hsync_len = crt_reg.hor_sync_end;
2811 var->upper_margin =
2812 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2813 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2814 var->vsync_len = crt_reg.ver_sync_end;
2815 }
Linux kernel - Deliverables
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