2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * Derived from ca91c042.c by Michael Wyrick
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/module.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/pci.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/poll.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/time.h>
31 #include <linux/uaccess.h>
32 #include <linux/vme.h>
34 #include "../vme_bridge.h"
35 #include "vme_ca91cx42.h"
37 static int ca91cx42_probe(struct pci_dev
*, const struct pci_device_id
*);
38 static void ca91cx42_remove(struct pci_dev
*);
40 /* Module parameters */
43 static const char driver_name
[] = "vme_ca91cx42";
45 static const struct pci_device_id ca91cx42_ids
[] = {
46 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA
, PCI_DEVICE_ID_TUNDRA_CA91C142
) },
50 static struct pci_driver ca91cx42_driver
= {
52 .id_table
= ca91cx42_ids
,
53 .probe
= ca91cx42_probe
,
54 .remove
= ca91cx42_remove
,
57 static u32
ca91cx42_DMA_irqhandler(struct ca91cx42_driver
*bridge
)
59 wake_up(&bridge
->dma_queue
);
61 return CA91CX42_LINT_DMA
;
64 static u32
ca91cx42_LM_irqhandler(struct ca91cx42_driver
*bridge
, u32 stat
)
69 for (i
= 0; i
< 4; i
++) {
70 if (stat
& CA91CX42_LINT_LM
[i
]) {
71 /* We only enable interrupts if the callback is set */
72 bridge
->lm_callback
[i
](i
);
73 serviced
|= CA91CX42_LINT_LM
[i
];
80 /* XXX This needs to be split into 4 queues */
81 static u32
ca91cx42_MB_irqhandler(struct ca91cx42_driver
*bridge
, int mbox_mask
)
83 wake_up(&bridge
->mbox_queue
);
85 return CA91CX42_LINT_MBOX
;
88 static u32
ca91cx42_IACK_irqhandler(struct ca91cx42_driver
*bridge
)
90 wake_up(&bridge
->iack_queue
);
92 return CA91CX42_LINT_SW_IACK
;
95 static u32
ca91cx42_VERR_irqhandler(struct vme_bridge
*ca91cx42_bridge
)
98 struct ca91cx42_driver
*bridge
;
100 bridge
= ca91cx42_bridge
->driver_priv
;
102 val
= ioread32(bridge
->base
+ DGCS
);
104 if (!(val
& 0x00000800)) {
105 dev_err(ca91cx42_bridge
->parent
, "ca91cx42_VERR_irqhandler DMA "
106 "Read Error DGCS=%08X\n", val
);
109 return CA91CX42_LINT_VERR
;
112 static u32
ca91cx42_LERR_irqhandler(struct vme_bridge
*ca91cx42_bridge
)
115 struct ca91cx42_driver
*bridge
;
117 bridge
= ca91cx42_bridge
->driver_priv
;
119 val
= ioread32(bridge
->base
+ DGCS
);
121 if (!(val
& 0x00000800))
122 dev_err(ca91cx42_bridge
->parent
, "ca91cx42_LERR_irqhandler DMA "
123 "Read Error DGCS=%08X\n", val
);
125 return CA91CX42_LINT_LERR
;
129 static u32
ca91cx42_VIRQ_irqhandler(struct vme_bridge
*ca91cx42_bridge
,
132 int vec
, i
, serviced
= 0;
133 struct ca91cx42_driver
*bridge
;
135 bridge
= ca91cx42_bridge
->driver_priv
;
138 for (i
= 7; i
> 0; i
--) {
139 if (stat
& (1 << i
)) {
140 vec
= ioread32(bridge
->base
+
141 CA91CX42_V_STATID
[i
]) & 0xff;
143 vme_irq_handler(ca91cx42_bridge
, i
, vec
);
145 serviced
|= (1 << i
);
152 static irqreturn_t
ca91cx42_irqhandler(int irq
, void *ptr
)
154 u32 stat
, enable
, serviced
= 0;
155 struct vme_bridge
*ca91cx42_bridge
;
156 struct ca91cx42_driver
*bridge
;
158 ca91cx42_bridge
= ptr
;
160 bridge
= ca91cx42_bridge
->driver_priv
;
162 enable
= ioread32(bridge
->base
+ LINT_EN
);
163 stat
= ioread32(bridge
->base
+ LINT_STAT
);
165 /* Only look at unmasked interrupts */
171 if (stat
& CA91CX42_LINT_DMA
)
172 serviced
|= ca91cx42_DMA_irqhandler(bridge
);
173 if (stat
& (CA91CX42_LINT_LM0
| CA91CX42_LINT_LM1
| CA91CX42_LINT_LM2
|
175 serviced
|= ca91cx42_LM_irqhandler(bridge
, stat
);
176 if (stat
& CA91CX42_LINT_MBOX
)
177 serviced
|= ca91cx42_MB_irqhandler(bridge
, stat
);
178 if (stat
& CA91CX42_LINT_SW_IACK
)
179 serviced
|= ca91cx42_IACK_irqhandler(bridge
);
180 if (stat
& CA91CX42_LINT_VERR
)
181 serviced
|= ca91cx42_VERR_irqhandler(ca91cx42_bridge
);
182 if (stat
& CA91CX42_LINT_LERR
)
183 serviced
|= ca91cx42_LERR_irqhandler(ca91cx42_bridge
);
184 if (stat
& (CA91CX42_LINT_VIRQ1
| CA91CX42_LINT_VIRQ2
|
185 CA91CX42_LINT_VIRQ3
| CA91CX42_LINT_VIRQ4
|
186 CA91CX42_LINT_VIRQ5
| CA91CX42_LINT_VIRQ6
|
187 CA91CX42_LINT_VIRQ7
))
188 serviced
|= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge
, stat
);
190 /* Clear serviced interrupts */
191 iowrite32(serviced
, bridge
->base
+ LINT_STAT
);
196 static int ca91cx42_irq_init(struct vme_bridge
*ca91cx42_bridge
)
199 struct pci_dev
*pdev
;
200 struct ca91cx42_driver
*bridge
;
202 bridge
= ca91cx42_bridge
->driver_priv
;
205 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
, dev
);
207 INIT_LIST_HEAD(&ca91cx42_bridge
->vme_error_handlers
);
209 mutex_init(&ca91cx42_bridge
->irq_mtx
);
211 /* Disable interrupts from PCI to VME */
212 iowrite32(0, bridge
->base
+ VINT_EN
);
214 /* Disable PCI interrupts */
215 iowrite32(0, bridge
->base
+ LINT_EN
);
216 /* Clear Any Pending PCI Interrupts */
217 iowrite32(0x00FFFFFF, bridge
->base
+ LINT_STAT
);
219 result
= request_irq(pdev
->irq
, ca91cx42_irqhandler
, IRQF_SHARED
,
220 driver_name
, ca91cx42_bridge
);
222 dev_err(&pdev
->dev
, "Can't get assigned pci irq vector %02X\n",
227 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
228 iowrite32(0, bridge
->base
+ LINT_MAP0
);
229 iowrite32(0, bridge
->base
+ LINT_MAP1
);
230 iowrite32(0, bridge
->base
+ LINT_MAP2
);
232 /* Enable DMA, mailbox & LM Interrupts */
233 tmp
= CA91CX42_LINT_MBOX3
| CA91CX42_LINT_MBOX2
| CA91CX42_LINT_MBOX1
|
234 CA91CX42_LINT_MBOX0
| CA91CX42_LINT_SW_IACK
|
235 CA91CX42_LINT_VERR
| CA91CX42_LINT_LERR
| CA91CX42_LINT_DMA
;
237 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
242 static void ca91cx42_irq_exit(struct ca91cx42_driver
*bridge
,
243 struct pci_dev
*pdev
)
245 struct vme_bridge
*ca91cx42_bridge
;
247 /* Disable interrupts from PCI to VME */
248 iowrite32(0, bridge
->base
+ VINT_EN
);
250 /* Disable PCI interrupts */
251 iowrite32(0, bridge
->base
+ LINT_EN
);
252 /* Clear Any Pending PCI Interrupts */
253 iowrite32(0x00FFFFFF, bridge
->base
+ LINT_STAT
);
255 ca91cx42_bridge
= container_of((void *)bridge
, struct vme_bridge
,
257 free_irq(pdev
->irq
, ca91cx42_bridge
);
260 static int ca91cx42_iack_received(struct ca91cx42_driver
*bridge
, int level
)
264 tmp
= ioread32(bridge
->base
+ LINT_STAT
);
266 if (tmp
& (1 << level
))
273 * Set up an VME interrupt
275 static void ca91cx42_irq_set(struct vme_bridge
*ca91cx42_bridge
, int level
,
279 struct pci_dev
*pdev
;
281 struct ca91cx42_driver
*bridge
;
283 bridge
= ca91cx42_bridge
->driver_priv
;
285 /* Enable IRQ level */
286 tmp
= ioread32(bridge
->base
+ LINT_EN
);
289 tmp
&= ~CA91CX42_LINT_VIRQ
[level
];
291 tmp
|= CA91CX42_LINT_VIRQ
[level
];
293 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
295 if ((state
== 0) && (sync
!= 0)) {
296 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
,
299 synchronize_irq(pdev
->irq
);
303 static int ca91cx42_irq_generate(struct vme_bridge
*ca91cx42_bridge
, int level
,
307 struct ca91cx42_driver
*bridge
;
309 bridge
= ca91cx42_bridge
->driver_priv
;
311 /* Universe can only generate even vectors */
315 mutex_lock(&bridge
->vme_int
);
317 tmp
= ioread32(bridge
->base
+ VINT_EN
);
320 iowrite32(statid
<< 24, bridge
->base
+ STATID
);
322 /* Assert VMEbus IRQ */
323 tmp
= tmp
| (1 << (level
+ 24));
324 iowrite32(tmp
, bridge
->base
+ VINT_EN
);
327 wait_event_interruptible(bridge
->iack_queue
,
328 ca91cx42_iack_received(bridge
, level
));
330 /* Return interrupt to low state */
331 tmp
= ioread32(bridge
->base
+ VINT_EN
);
332 tmp
= tmp
& ~(1 << (level
+ 24));
333 iowrite32(tmp
, bridge
->base
+ VINT_EN
);
335 mutex_unlock(&bridge
->vme_int
);
340 static int ca91cx42_slave_set(struct vme_slave_resource
*image
, int enabled
,
341 unsigned long long vme_base
, unsigned long long size
,
342 dma_addr_t pci_base
, u32 aspace
, u32 cycle
)
344 unsigned int i
, addr
= 0, granularity
;
345 unsigned int temp_ctl
= 0;
346 unsigned int vme_bound
, pci_offset
;
347 struct vme_bridge
*ca91cx42_bridge
;
348 struct ca91cx42_driver
*bridge
;
350 ca91cx42_bridge
= image
->parent
;
352 bridge
= ca91cx42_bridge
->driver_priv
;
358 addr
|= CA91CX42_VSI_CTL_VAS_A16
;
361 addr
|= CA91CX42_VSI_CTL_VAS_A24
;
364 addr
|= CA91CX42_VSI_CTL_VAS_A32
;
367 addr
|= CA91CX42_VSI_CTL_VAS_USER1
;
370 addr
|= CA91CX42_VSI_CTL_VAS_USER2
;
377 dev_err(ca91cx42_bridge
->parent
, "Invalid address space\n");
383 * Bound address is a valid address for the window, adjust
386 vme_bound
= vme_base
+ size
;
387 pci_offset
= pci_base
- vme_base
;
389 if ((i
== 0) || (i
== 4))
390 granularity
= 0x1000;
392 granularity
= 0x10000;
394 if (vme_base
& (granularity
- 1)) {
395 dev_err(ca91cx42_bridge
->parent
, "Invalid VME base "
399 if (vme_bound
& (granularity
- 1)) {
400 dev_err(ca91cx42_bridge
->parent
, "Invalid VME bound "
404 if (pci_offset
& (granularity
- 1)) {
405 dev_err(ca91cx42_bridge
->parent
, "Invalid PCI Offset "
410 /* Disable while we are mucking around */
411 temp_ctl
= ioread32(bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
412 temp_ctl
&= ~CA91CX42_VSI_CTL_EN
;
413 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
416 iowrite32(vme_base
, bridge
->base
+ CA91CX42_VSI_BS
[i
]);
417 iowrite32(vme_bound
, bridge
->base
+ CA91CX42_VSI_BD
[i
]);
418 iowrite32(pci_offset
, bridge
->base
+ CA91CX42_VSI_TO
[i
]);
420 /* Setup address space */
421 temp_ctl
&= ~CA91CX42_VSI_CTL_VAS_M
;
424 /* Setup cycle types */
425 temp_ctl
&= ~(CA91CX42_VSI_CTL_PGM_M
| CA91CX42_VSI_CTL_SUPER_M
);
426 if (cycle
& VME_SUPER
)
427 temp_ctl
|= CA91CX42_VSI_CTL_SUPER_SUPR
;
428 if (cycle
& VME_USER
)
429 temp_ctl
|= CA91CX42_VSI_CTL_SUPER_NPRIV
;
430 if (cycle
& VME_PROG
)
431 temp_ctl
|= CA91CX42_VSI_CTL_PGM_PGM
;
432 if (cycle
& VME_DATA
)
433 temp_ctl
|= CA91CX42_VSI_CTL_PGM_DATA
;
435 /* Write ctl reg without enable */
436 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
439 temp_ctl
|= CA91CX42_VSI_CTL_EN
;
441 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
446 static int ca91cx42_slave_get(struct vme_slave_resource
*image
, int *enabled
,
447 unsigned long long *vme_base
, unsigned long long *size
,
448 dma_addr_t
*pci_base
, u32
*aspace
, u32
*cycle
)
450 unsigned int i
, granularity
= 0, ctl
= 0;
451 unsigned long long vme_bound
, pci_offset
;
452 struct ca91cx42_driver
*bridge
;
454 bridge
= image
->parent
->driver_priv
;
458 if ((i
== 0) || (i
== 4))
459 granularity
= 0x1000;
461 granularity
= 0x10000;
464 ctl
= ioread32(bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
466 *vme_base
= ioread32(bridge
->base
+ CA91CX42_VSI_BS
[i
]);
467 vme_bound
= ioread32(bridge
->base
+ CA91CX42_VSI_BD
[i
]);
468 pci_offset
= ioread32(bridge
->base
+ CA91CX42_VSI_TO
[i
]);
470 *pci_base
= (dma_addr_t
)vme_base
+ pci_offset
;
471 *size
= (unsigned long long)((vme_bound
- *vme_base
) + granularity
);
477 if (ctl
& CA91CX42_VSI_CTL_EN
)
480 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A16
)
482 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A24
)
484 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A32
)
486 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_USER1
)
488 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_USER2
)
491 if (ctl
& CA91CX42_VSI_CTL_SUPER_SUPR
)
493 if (ctl
& CA91CX42_VSI_CTL_SUPER_NPRIV
)
495 if (ctl
& CA91CX42_VSI_CTL_PGM_PGM
)
497 if (ctl
& CA91CX42_VSI_CTL_PGM_DATA
)
504 * Allocate and map PCI Resource
506 static int ca91cx42_alloc_resource(struct vme_master_resource
*image
,
507 unsigned long long size
)
509 unsigned long long existing_size
;
511 struct pci_dev
*pdev
;
512 struct vme_bridge
*ca91cx42_bridge
;
514 ca91cx42_bridge
= image
->parent
;
516 /* Find pci_dev container of dev */
517 if (ca91cx42_bridge
->parent
== NULL
) {
518 dev_err(ca91cx42_bridge
->parent
, "Dev entry NULL\n");
521 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
, dev
);
523 existing_size
= (unsigned long long)(image
->bus_resource
.end
-
524 image
->bus_resource
.start
);
526 /* If the existing size is OK, return */
527 if (existing_size
== (size
- 1))
530 if (existing_size
!= 0) {
531 iounmap(image
->kern_base
);
532 image
->kern_base
= NULL
;
533 kfree(image
->bus_resource
.name
);
534 release_resource(&image
->bus_resource
);
535 memset(&image
->bus_resource
, 0, sizeof(struct resource
));
538 if (image
->bus_resource
.name
== NULL
) {
539 image
->bus_resource
.name
= kmalloc(VMENAMSIZ
+3, GFP_ATOMIC
);
540 if (image
->bus_resource
.name
== NULL
) {
541 dev_err(ca91cx42_bridge
->parent
, "Unable to allocate "
542 "memory for resource name\n");
548 sprintf((char *)image
->bus_resource
.name
, "%s.%d",
549 ca91cx42_bridge
->name
, image
->number
);
551 image
->bus_resource
.start
= 0;
552 image
->bus_resource
.end
= (unsigned long)size
;
553 image
->bus_resource
.flags
= IORESOURCE_MEM
;
555 retval
= pci_bus_alloc_resource(pdev
->bus
,
556 &image
->bus_resource
, size
, 0x10000, PCIBIOS_MIN_MEM
,
559 dev_err(ca91cx42_bridge
->parent
, "Failed to allocate mem "
560 "resource for window %d size 0x%lx start 0x%lx\n",
561 image
->number
, (unsigned long)size
,
562 (unsigned long)image
->bus_resource
.start
);
566 image
->kern_base
= ioremap_nocache(
567 image
->bus_resource
.start
, size
);
568 if (image
->kern_base
== NULL
) {
569 dev_err(ca91cx42_bridge
->parent
, "Failed to remap resource\n");
577 release_resource(&image
->bus_resource
);
579 kfree(image
->bus_resource
.name
);
580 memset(&image
->bus_resource
, 0, sizeof(struct resource
));
586 * Free and unmap PCI Resource
588 static void ca91cx42_free_resource(struct vme_master_resource
*image
)
590 iounmap(image
->kern_base
);
591 image
->kern_base
= NULL
;
592 release_resource(&image
->bus_resource
);
593 kfree(image
->bus_resource
.name
);
594 memset(&image
->bus_resource
, 0, sizeof(struct resource
));
598 static int ca91cx42_master_set(struct vme_master_resource
*image
, int enabled
,
599 unsigned long long vme_base
, unsigned long long size
, u32 aspace
,
600 u32 cycle
, u32 dwidth
)
603 unsigned int i
, granularity
= 0;
604 unsigned int temp_ctl
= 0;
605 unsigned long long pci_bound
, vme_offset
, pci_base
;
606 struct vme_bridge
*ca91cx42_bridge
;
607 struct ca91cx42_driver
*bridge
;
609 ca91cx42_bridge
= image
->parent
;
611 bridge
= ca91cx42_bridge
->driver_priv
;
615 if ((i
== 0) || (i
== 4))
616 granularity
= 0x1000;
618 granularity
= 0x10000;
620 /* Verify input data */
621 if (vme_base
& (granularity
- 1)) {
622 dev_err(ca91cx42_bridge
->parent
, "Invalid VME Window "
627 if (size
& (granularity
- 1)) {
628 dev_err(ca91cx42_bridge
->parent
, "Invalid VME Window "
634 spin_lock(&image
->lock
);
637 * Let's allocate the resource here rather than further up the stack as
638 * it avoids pushing loads of bus dependent stuff up the stack
640 retval
= ca91cx42_alloc_resource(image
, size
);
642 spin_unlock(&image
->lock
);
643 dev_err(ca91cx42_bridge
->parent
, "Unable to allocate memory "
644 "for resource name\n");
649 pci_base
= (unsigned long long)image
->bus_resource
.start
;
652 * Bound address is a valid address for the window, adjust
653 * according to window granularity.
655 pci_bound
= pci_base
+ size
;
656 vme_offset
= vme_base
- pci_base
;
658 /* Disable while we are mucking around */
659 temp_ctl
= ioread32(bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
660 temp_ctl
&= ~CA91CX42_LSI_CTL_EN
;
661 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
663 /* Setup cycle types */
664 temp_ctl
&= ~CA91CX42_LSI_CTL_VCT_M
;
666 temp_ctl
|= CA91CX42_LSI_CTL_VCT_BLT
;
667 if (cycle
& VME_MBLT
)
668 temp_ctl
|= CA91CX42_LSI_CTL_VCT_MBLT
;
670 /* Setup data width */
671 temp_ctl
&= ~CA91CX42_LSI_CTL_VDW_M
;
674 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D8
;
677 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D16
;
680 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D32
;
683 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D64
;
686 spin_unlock(&image
->lock
);
687 dev_err(ca91cx42_bridge
->parent
, "Invalid data width\n");
693 /* Setup address space */
694 temp_ctl
&= ~CA91CX42_LSI_CTL_VAS_M
;
697 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A16
;
700 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A24
;
703 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A32
;
706 temp_ctl
|= CA91CX42_LSI_CTL_VAS_CRCSR
;
709 temp_ctl
|= CA91CX42_LSI_CTL_VAS_USER1
;
712 temp_ctl
|= CA91CX42_LSI_CTL_VAS_USER2
;
718 spin_unlock(&image
->lock
);
719 dev_err(ca91cx42_bridge
->parent
, "Invalid address space\n");
725 temp_ctl
&= ~(CA91CX42_LSI_CTL_PGM_M
| CA91CX42_LSI_CTL_SUPER_M
);
726 if (cycle
& VME_SUPER
)
727 temp_ctl
|= CA91CX42_LSI_CTL_SUPER_SUPR
;
728 if (cycle
& VME_PROG
)
729 temp_ctl
|= CA91CX42_LSI_CTL_PGM_PGM
;
732 iowrite32(pci_base
, bridge
->base
+ CA91CX42_LSI_BS
[i
]);
733 iowrite32(pci_bound
, bridge
->base
+ CA91CX42_LSI_BD
[i
]);
734 iowrite32(vme_offset
, bridge
->base
+ CA91CX42_LSI_TO
[i
]);
736 /* Write ctl reg without enable */
737 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
740 temp_ctl
|= CA91CX42_LSI_CTL_EN
;
742 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
744 spin_unlock(&image
->lock
);
749 ca91cx42_free_resource(image
);
755 static int __ca91cx42_master_get(struct vme_master_resource
*image
,
756 int *enabled
, unsigned long long *vme_base
, unsigned long long *size
,
757 u32
*aspace
, u32
*cycle
, u32
*dwidth
)
760 unsigned long long pci_base
, pci_bound
, vme_offset
;
761 struct ca91cx42_driver
*bridge
;
763 bridge
= image
->parent
->driver_priv
;
767 ctl
= ioread32(bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
769 pci_base
= ioread32(bridge
->base
+ CA91CX42_LSI_BS
[i
]);
770 vme_offset
= ioread32(bridge
->base
+ CA91CX42_LSI_TO
[i
]);
771 pci_bound
= ioread32(bridge
->base
+ CA91CX42_LSI_BD
[i
]);
773 *vme_base
= pci_base
+ vme_offset
;
774 *size
= (unsigned long long)(pci_bound
- pci_base
);
781 if (ctl
& CA91CX42_LSI_CTL_EN
)
784 /* Setup address space */
785 switch (ctl
& CA91CX42_LSI_CTL_VAS_M
) {
786 case CA91CX42_LSI_CTL_VAS_A16
:
789 case CA91CX42_LSI_CTL_VAS_A24
:
792 case CA91CX42_LSI_CTL_VAS_A32
:
795 case CA91CX42_LSI_CTL_VAS_CRCSR
:
798 case CA91CX42_LSI_CTL_VAS_USER1
:
801 case CA91CX42_LSI_CTL_VAS_USER2
:
806 /* XXX Not sure howto check for MBLT */
807 /* Setup cycle types */
808 if (ctl
& CA91CX42_LSI_CTL_VCT_BLT
)
813 if (ctl
& CA91CX42_LSI_CTL_SUPER_SUPR
)
818 if (ctl
& CA91CX42_LSI_CTL_PGM_PGM
)
823 /* Setup data width */
824 switch (ctl
& CA91CX42_LSI_CTL_VDW_M
) {
825 case CA91CX42_LSI_CTL_VDW_D8
:
828 case CA91CX42_LSI_CTL_VDW_D16
:
831 case CA91CX42_LSI_CTL_VDW_D32
:
834 case CA91CX42_LSI_CTL_VDW_D64
:
842 static int ca91cx42_master_get(struct vme_master_resource
*image
, int *enabled
,
843 unsigned long long *vme_base
, unsigned long long *size
, u32
*aspace
,
844 u32
*cycle
, u32
*dwidth
)
848 spin_lock(&image
->lock
);
850 retval
= __ca91cx42_master_get(image
, enabled
, vme_base
, size
, aspace
,
853 spin_unlock(&image
->lock
);
858 static ssize_t
ca91cx42_master_read(struct vme_master_resource
*image
,
859 void *buf
, size_t count
, loff_t offset
)
862 void __iomem
*addr
= image
->kern_base
+ offset
;
863 unsigned int done
= 0;
864 unsigned int count32
;
869 spin_lock(&image
->lock
);
871 /* The following code handles VME address alignment. We cannot use
872 * memcpy_xxx here because it may cut data transfers in to 8-bit
873 * cycles when D16 or D32 cycles are required on the VME bus.
874 * On the other hand, the bridge itself assures that the maximum data
875 * cycle configured for the transfer is used and splits it
876 * automatically for non-aligned addresses, so we don't want the
877 * overhead of needlessly forcing small transfers for the entire cycle.
879 if ((uintptr_t)addr
& 0x1) {
880 *(u8
*)buf
= ioread8(addr
);
885 if ((uintptr_t)(addr
+ done
) & 0x2) {
886 if ((count
- done
) < 2) {
887 *(u8
*)(buf
+ done
) = ioread8(addr
+ done
);
891 *(u16
*)(buf
+ done
) = ioread16(addr
+ done
);
896 count32
= (count
- done
) & ~0x3;
897 while (done
< count32
) {
898 *(u32
*)(buf
+ done
) = ioread32(addr
+ done
);
902 if ((count
- done
) & 0x2) {
903 *(u16
*)(buf
+ done
) = ioread16(addr
+ done
);
906 if ((count
- done
) & 0x1) {
907 *(u8
*)(buf
+ done
) = ioread8(addr
+ done
);
912 spin_unlock(&image
->lock
);
917 static ssize_t
ca91cx42_master_write(struct vme_master_resource
*image
,
918 void *buf
, size_t count
, loff_t offset
)
921 void __iomem
*addr
= image
->kern_base
+ offset
;
922 unsigned int done
= 0;
923 unsigned int count32
;
928 spin_lock(&image
->lock
);
930 /* Here we apply for the same strategy we do in master_read
931 * function in order to assure the correct cycles.
933 if ((uintptr_t)addr
& 0x1) {
934 iowrite8(*(u8
*)buf
, addr
);
939 if ((uintptr_t)(addr
+ done
) & 0x2) {
940 if ((count
- done
) < 2) {
941 iowrite8(*(u8
*)(buf
+ done
), addr
+ done
);
945 iowrite16(*(u16
*)(buf
+ done
), addr
+ done
);
950 count32
= (count
- done
) & ~0x3;
951 while (done
< count32
) {
952 iowrite32(*(u32
*)(buf
+ done
), addr
+ done
);
956 if ((count
- done
) & 0x2) {
957 iowrite16(*(u16
*)(buf
+ done
), addr
+ done
);
960 if ((count
- done
) & 0x1) {
961 iowrite8(*(u8
*)(buf
+ done
), addr
+ done
);
967 spin_unlock(&image
->lock
);
972 static unsigned int ca91cx42_master_rmw(struct vme_master_resource
*image
,
973 unsigned int mask
, unsigned int compare
, unsigned int swap
,
979 struct ca91cx42_driver
*bridge
;
982 bridge
= image
->parent
->driver_priv
;
983 dev
= image
->parent
->parent
;
985 /* Find the PCI address that maps to the desired VME address */
988 /* Locking as we can only do one of these at a time */
989 mutex_lock(&bridge
->vme_rmw
);
992 spin_lock(&image
->lock
);
994 pci_addr
= (uintptr_t)image
->kern_base
+ offset
;
996 /* Address must be 4-byte aligned */
997 if (pci_addr
& 0x3) {
998 dev_err(dev
, "RMW Address not 4-byte aligned\n");
1003 /* Ensure RMW Disabled whilst configuring */
1004 iowrite32(0, bridge
->base
+ SCYC_CTL
);
1006 /* Configure registers */
1007 iowrite32(mask
, bridge
->base
+ SCYC_EN
);
1008 iowrite32(compare
, bridge
->base
+ SCYC_CMP
);
1009 iowrite32(swap
, bridge
->base
+ SCYC_SWP
);
1010 iowrite32(pci_addr
, bridge
->base
+ SCYC_ADDR
);
1013 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW
, bridge
->base
+ SCYC_CTL
);
1015 /* Kick process off with a read to the required address. */
1016 result
= ioread32(image
->kern_base
+ offset
);
1019 iowrite32(0, bridge
->base
+ SCYC_CTL
);
1022 spin_unlock(&image
->lock
);
1024 mutex_unlock(&bridge
->vme_rmw
);
1029 static int ca91cx42_dma_list_add(struct vme_dma_list
*list
,
1030 struct vme_dma_attr
*src
, struct vme_dma_attr
*dest
, size_t count
)
1032 struct ca91cx42_dma_entry
*entry
, *prev
;
1033 struct vme_dma_pci
*pci_attr
;
1034 struct vme_dma_vme
*vme_attr
;
1035 dma_addr_t desc_ptr
;
1039 dev
= list
->parent
->parent
->parent
;
1041 /* XXX descriptor must be aligned on 64-bit boundaries */
1042 entry
= kmalloc(sizeof(struct ca91cx42_dma_entry
), GFP_KERNEL
);
1043 if (entry
== NULL
) {
1044 dev_err(dev
, "Failed to allocate memory for dma resource "
1050 /* Test descriptor alignment */
1051 if ((unsigned long)&entry
->descriptor
& CA91CX42_DCPP_M
) {
1052 dev_err(dev
, "Descriptor not aligned to 16 byte boundary as "
1053 "required: %p\n", &entry
->descriptor
);
1058 memset(&entry
->descriptor
, 0, sizeof(struct ca91cx42_dma_descriptor
));
1060 if (dest
->type
== VME_DMA_VME
) {
1061 entry
->descriptor
.dctl
|= CA91CX42_DCTL_L2V
;
1062 vme_attr
= dest
->private;
1063 pci_attr
= src
->private;
1065 vme_attr
= src
->private;
1066 pci_attr
= dest
->private;
1069 /* Check we can do fulfill required attributes */
1070 if ((vme_attr
->aspace
& ~(VME_A16
| VME_A24
| VME_A32
| VME_USER1
|
1073 dev_err(dev
, "Unsupported cycle type\n");
1078 if ((vme_attr
->cycle
& ~(VME_SCT
| VME_BLT
| VME_SUPER
| VME_USER
|
1079 VME_PROG
| VME_DATA
)) != 0) {
1081 dev_err(dev
, "Unsupported cycle type\n");
1086 /* Check to see if we can fulfill source and destination */
1087 if (!(((src
->type
== VME_DMA_PCI
) && (dest
->type
== VME_DMA_VME
)) ||
1088 ((src
->type
== VME_DMA_VME
) && (dest
->type
== VME_DMA_PCI
)))) {
1090 dev_err(dev
, "Cannot perform transfer with this "
1091 "source-destination combination\n");
1096 /* Setup cycle types */
1097 if (vme_attr
->cycle
& VME_BLT
)
1098 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VCT_BLT
;
1100 /* Setup data width */
1101 switch (vme_attr
->dwidth
) {
1103 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D8
;
1106 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D16
;
1109 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D32
;
1112 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D64
;
1115 dev_err(dev
, "Invalid data width\n");
1119 /* Setup address space */
1120 switch (vme_attr
->aspace
) {
1122 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A16
;
1125 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A24
;
1128 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A32
;
1131 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_USER1
;
1134 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_USER2
;
1137 dev_err(dev
, "Invalid address space\n");
1142 if (vme_attr
->cycle
& VME_SUPER
)
1143 entry
->descriptor
.dctl
|= CA91CX42_DCTL_SUPER_SUPR
;
1144 if (vme_attr
->cycle
& VME_PROG
)
1145 entry
->descriptor
.dctl
|= CA91CX42_DCTL_PGM_PGM
;
1147 entry
->descriptor
.dtbc
= count
;
1148 entry
->descriptor
.dla
= pci_attr
->address
;
1149 entry
->descriptor
.dva
= vme_attr
->address
;
1150 entry
->descriptor
.dcpp
= CA91CX42_DCPP_NULL
;
1153 list_add_tail(&entry
->list
, &list
->entries
);
1155 /* Fill out previous descriptors "Next Address" */
1156 if (entry
->list
.prev
!= &list
->entries
) {
1157 prev
= list_entry(entry
->list
.prev
, struct ca91cx42_dma_entry
,
1159 /* We need the bus address for the pointer */
1160 desc_ptr
= virt_to_bus(&entry
->descriptor
);
1161 prev
->descriptor
.dcpp
= desc_ptr
& ~CA91CX42_DCPP_M
;
1175 static int ca91cx42_dma_busy(struct vme_bridge
*ca91cx42_bridge
)
1178 struct ca91cx42_driver
*bridge
;
1180 bridge
= ca91cx42_bridge
->driver_priv
;
1182 tmp
= ioread32(bridge
->base
+ DGCS
);
1184 if (tmp
& CA91CX42_DGCS_ACT
)
1190 static int ca91cx42_dma_list_exec(struct vme_dma_list
*list
)
1192 struct vme_dma_resource
*ctrlr
;
1193 struct ca91cx42_dma_entry
*entry
;
1195 dma_addr_t bus_addr
;
1198 struct ca91cx42_driver
*bridge
;
1200 ctrlr
= list
->parent
;
1202 bridge
= ctrlr
->parent
->driver_priv
;
1203 dev
= ctrlr
->parent
->parent
;
1205 mutex_lock(&ctrlr
->mtx
);
1207 if (!(list_empty(&ctrlr
->running
))) {
1209 * XXX We have an active DMA transfer and currently haven't
1210 * sorted out the mechanism for "pending" DMA transfers.
1213 /* Need to add to pending here */
1214 mutex_unlock(&ctrlr
->mtx
);
1217 list_add(&list
->list
, &ctrlr
->running
);
1220 /* Get first bus address and write into registers */
1221 entry
= list_first_entry(&list
->entries
, struct ca91cx42_dma_entry
,
1224 bus_addr
= virt_to_bus(&entry
->descriptor
);
1226 mutex_unlock(&ctrlr
->mtx
);
1228 iowrite32(0, bridge
->base
+ DTBC
);
1229 iowrite32(bus_addr
& ~CA91CX42_DCPP_M
, bridge
->base
+ DCPP
);
1231 /* Start the operation */
1232 val
= ioread32(bridge
->base
+ DGCS
);
1234 /* XXX Could set VMEbus On and Off Counters here */
1235 val
&= (CA91CX42_DGCS_VON_M
| CA91CX42_DGCS_VOFF_M
);
1237 val
|= (CA91CX42_DGCS_CHAIN
| CA91CX42_DGCS_STOP
| CA91CX42_DGCS_HALT
|
1238 CA91CX42_DGCS_DONE
| CA91CX42_DGCS_LERR
| CA91CX42_DGCS_VERR
|
1239 CA91CX42_DGCS_PERR
);
1241 iowrite32(val
, bridge
->base
+ DGCS
);
1243 val
|= CA91CX42_DGCS_GO
;
1245 iowrite32(val
, bridge
->base
+ DGCS
);
1247 retval
= wait_event_interruptible(bridge
->dma_queue
,
1248 ca91cx42_dma_busy(ctrlr
->parent
));
1251 val
= ioread32(bridge
->base
+ DGCS
);
1252 iowrite32(val
| CA91CX42_DGCS_STOP_REQ
, bridge
->base
+ DGCS
);
1253 /* Wait for the operation to abort */
1254 wait_event(bridge
->dma_queue
,
1255 ca91cx42_dma_busy(ctrlr
->parent
));
1261 * Read status register, this register is valid until we kick off a
1264 val
= ioread32(bridge
->base
+ DGCS
);
1266 if (val
& (CA91CX42_DGCS_LERR
| CA91CX42_DGCS_VERR
|
1267 CA91CX42_DGCS_PERR
)) {
1269 dev_err(dev
, "ca91c042: DMA Error. DGCS=%08X\n", val
);
1270 val
= ioread32(bridge
->base
+ DCTL
);
1275 /* Remove list from running list */
1276 mutex_lock(&ctrlr
->mtx
);
1277 list_del(&list
->list
);
1278 mutex_unlock(&ctrlr
->mtx
);
1284 static int ca91cx42_dma_list_empty(struct vme_dma_list
*list
)
1286 struct list_head
*pos
, *temp
;
1287 struct ca91cx42_dma_entry
*entry
;
1289 /* detach and free each entry */
1290 list_for_each_safe(pos
, temp
, &list
->entries
) {
1292 entry
= list_entry(pos
, struct ca91cx42_dma_entry
, list
);
1300 * All 4 location monitors reside at the same base - this is therefore a
1301 * system wide configuration.
1303 * This does not enable the LM monitor - that should be done when the first
1304 * callback is attached and disabled when the last callback is removed.
1306 static int ca91cx42_lm_set(struct vme_lm_resource
*lm
,
1307 unsigned long long lm_base
, u32 aspace
, u32 cycle
)
1309 u32 temp_base
, lm_ctl
= 0;
1311 struct ca91cx42_driver
*bridge
;
1314 bridge
= lm
->parent
->driver_priv
;
1315 dev
= lm
->parent
->parent
;
1317 /* Check the alignment of the location monitor */
1318 temp_base
= (u32
)lm_base
;
1319 if (temp_base
& 0xffff) {
1320 dev_err(dev
, "Location monitor must be aligned to 64KB "
1325 mutex_lock(&lm
->mtx
);
1327 /* If we already have a callback attached, we can't move it! */
1328 for (i
= 0; i
< lm
->monitors
; i
++) {
1329 if (bridge
->lm_callback
[i
] != NULL
) {
1330 mutex_unlock(&lm
->mtx
);
1331 dev_err(dev
, "Location monitor callback attached, "
1339 lm_ctl
|= CA91CX42_LM_CTL_AS_A16
;
1342 lm_ctl
|= CA91CX42_LM_CTL_AS_A24
;
1345 lm_ctl
|= CA91CX42_LM_CTL_AS_A32
;
1348 mutex_unlock(&lm
->mtx
);
1349 dev_err(dev
, "Invalid address space\n");
1354 if (cycle
& VME_SUPER
)
1355 lm_ctl
|= CA91CX42_LM_CTL_SUPR
;
1356 if (cycle
& VME_USER
)
1357 lm_ctl
|= CA91CX42_LM_CTL_NPRIV
;
1358 if (cycle
& VME_PROG
)
1359 lm_ctl
|= CA91CX42_LM_CTL_PGM
;
1360 if (cycle
& VME_DATA
)
1361 lm_ctl
|= CA91CX42_LM_CTL_DATA
;
1363 iowrite32(lm_base
, bridge
->base
+ LM_BS
);
1364 iowrite32(lm_ctl
, bridge
->base
+ LM_CTL
);
1366 mutex_unlock(&lm
->mtx
);
1371 /* Get configuration of the callback monitor and return whether it is enabled
1374 static int ca91cx42_lm_get(struct vme_lm_resource
*lm
,
1375 unsigned long long *lm_base
, u32
*aspace
, u32
*cycle
)
1377 u32 lm_ctl
, enabled
= 0;
1378 struct ca91cx42_driver
*bridge
;
1380 bridge
= lm
->parent
->driver_priv
;
1382 mutex_lock(&lm
->mtx
);
1384 *lm_base
= (unsigned long long)ioread32(bridge
->base
+ LM_BS
);
1385 lm_ctl
= ioread32(bridge
->base
+ LM_CTL
);
1387 if (lm_ctl
& CA91CX42_LM_CTL_EN
)
1390 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A16
)
1392 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A24
)
1394 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A32
)
1398 if (lm_ctl
& CA91CX42_LM_CTL_SUPR
)
1399 *cycle
|= VME_SUPER
;
1400 if (lm_ctl
& CA91CX42_LM_CTL_NPRIV
)
1402 if (lm_ctl
& CA91CX42_LM_CTL_PGM
)
1404 if (lm_ctl
& CA91CX42_LM_CTL_DATA
)
1407 mutex_unlock(&lm
->mtx
);
1413 * Attach a callback to a specific location monitor.
1415 * Callback will be passed the monitor triggered.
1417 static int ca91cx42_lm_attach(struct vme_lm_resource
*lm
, int monitor
,
1418 void (*callback
)(int))
1421 struct ca91cx42_driver
*bridge
;
1424 bridge
= lm
->parent
->driver_priv
;
1425 dev
= lm
->parent
->parent
;
1427 mutex_lock(&lm
->mtx
);
1429 /* Ensure that the location monitor is configured - need PGM or DATA */
1430 lm_ctl
= ioread32(bridge
->base
+ LM_CTL
);
1431 if ((lm_ctl
& (CA91CX42_LM_CTL_PGM
| CA91CX42_LM_CTL_DATA
)) == 0) {
1432 mutex_unlock(&lm
->mtx
);
1433 dev_err(dev
, "Location monitor not properly configured\n");
1437 /* Check that a callback isn't already attached */
1438 if (bridge
->lm_callback
[monitor
] != NULL
) {
1439 mutex_unlock(&lm
->mtx
);
1440 dev_err(dev
, "Existing callback attached\n");
1444 /* Attach callback */
1445 bridge
->lm_callback
[monitor
] = callback
;
1447 /* Enable Location Monitor interrupt */
1448 tmp
= ioread32(bridge
->base
+ LINT_EN
);
1449 tmp
|= CA91CX42_LINT_LM
[monitor
];
1450 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
1452 /* Ensure that global Location Monitor Enable set */
1453 if ((lm_ctl
& CA91CX42_LM_CTL_EN
) == 0) {
1454 lm_ctl
|= CA91CX42_LM_CTL_EN
;
1455 iowrite32(lm_ctl
, bridge
->base
+ LM_CTL
);
1458 mutex_unlock(&lm
->mtx
);
1464 * Detach a callback function forn a specific location monitor.
1466 static int ca91cx42_lm_detach(struct vme_lm_resource
*lm
, int monitor
)
1469 struct ca91cx42_driver
*bridge
;
1471 bridge
= lm
->parent
->driver_priv
;
1473 mutex_lock(&lm
->mtx
);
1475 /* Disable Location Monitor and ensure previous interrupts are clear */
1476 tmp
= ioread32(bridge
->base
+ LINT_EN
);
1477 tmp
&= ~CA91CX42_LINT_LM
[monitor
];
1478 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
1480 iowrite32(CA91CX42_LINT_LM
[monitor
],
1481 bridge
->base
+ LINT_STAT
);
1483 /* Detach callback */
1484 bridge
->lm_callback
[monitor
] = NULL
;
1486 /* If all location monitors disabled, disable global Location Monitor */
1487 if ((tmp
& (CA91CX42_LINT_LM0
| CA91CX42_LINT_LM1
| CA91CX42_LINT_LM2
|
1488 CA91CX42_LINT_LM3
)) == 0) {
1489 tmp
= ioread32(bridge
->base
+ LM_CTL
);
1490 tmp
&= ~CA91CX42_LM_CTL_EN
;
1491 iowrite32(tmp
, bridge
->base
+ LM_CTL
);
1494 mutex_unlock(&lm
->mtx
);
1499 static int ca91cx42_slot_get(struct vme_bridge
*ca91cx42_bridge
)
1502 struct ca91cx42_driver
*bridge
;
1504 bridge
= ca91cx42_bridge
->driver_priv
;
1507 slot
= ioread32(bridge
->base
+ VCSR_BS
);
1508 slot
= ((slot
& CA91CX42_VCSR_BS_SLOT_M
) >> 27);
1516 static void *ca91cx42_alloc_consistent(struct device
*parent
, size_t size
,
1519 struct pci_dev
*pdev
;
1521 /* Find pci_dev container of dev */
1522 pdev
= container_of(parent
, struct pci_dev
, dev
);
1524 return pci_alloc_consistent(pdev
, size
, dma
);
1527 static void ca91cx42_free_consistent(struct device
*parent
, size_t size
,
1528 void *vaddr
, dma_addr_t dma
)
1530 struct pci_dev
*pdev
;
1532 /* Find pci_dev container of dev */
1533 pdev
= container_of(parent
, struct pci_dev
, dev
);
1535 pci_free_consistent(pdev
, size
, vaddr
, dma
);
1539 * Configure CR/CSR space
1541 * Access to the CR/CSR can be configured at power-up. The location of the
1542 * CR/CSR registers in the CR/CSR address space is determined by the boards
1543 * Auto-ID or Geographic address. This function ensures that the window is
1544 * enabled at an offset consistent with the boards geopgraphic address.
1546 static int ca91cx42_crcsr_init(struct vme_bridge
*ca91cx42_bridge
,
1547 struct pci_dev
*pdev
)
1549 unsigned int crcsr_addr
;
1551 struct ca91cx42_driver
*bridge
;
1553 bridge
= ca91cx42_bridge
->driver_priv
;
1555 slot
= ca91cx42_slot_get(ca91cx42_bridge
);
1557 /* Write CSR Base Address if slot ID is supplied as a module param */
1559 iowrite32(geoid
<< 27, bridge
->base
+ VCSR_BS
);
1561 dev_info(&pdev
->dev
, "CR/CSR Offset: %d\n", slot
);
1563 dev_err(&pdev
->dev
, "Slot number is unset, not configuring "
1568 /* Allocate mem for CR/CSR image */
1569 bridge
->crcsr_kernel
= pci_zalloc_consistent(pdev
, VME_CRCSR_BUF_SIZE
,
1570 &bridge
->crcsr_bus
);
1571 if (bridge
->crcsr_kernel
== NULL
) {
1572 dev_err(&pdev
->dev
, "Failed to allocate memory for CR/CSR "
1577 crcsr_addr
= slot
* (512 * 1024);
1578 iowrite32(bridge
->crcsr_bus
- crcsr_addr
, bridge
->base
+ VCSR_TO
);
1580 tmp
= ioread32(bridge
->base
+ VCSR_CTL
);
1581 tmp
|= CA91CX42_VCSR_CTL_EN
;
1582 iowrite32(tmp
, bridge
->base
+ VCSR_CTL
);
1587 static void ca91cx42_crcsr_exit(struct vme_bridge
*ca91cx42_bridge
,
1588 struct pci_dev
*pdev
)
1591 struct ca91cx42_driver
*bridge
;
1593 bridge
= ca91cx42_bridge
->driver_priv
;
1595 /* Turn off CR/CSR space */
1596 tmp
= ioread32(bridge
->base
+ VCSR_CTL
);
1597 tmp
&= ~CA91CX42_VCSR_CTL_EN
;
1598 iowrite32(tmp
, bridge
->base
+ VCSR_CTL
);
1601 iowrite32(0, bridge
->base
+ VCSR_TO
);
1603 pci_free_consistent(pdev
, VME_CRCSR_BUF_SIZE
, bridge
->crcsr_kernel
,
1607 static int ca91cx42_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1611 struct list_head
*pos
= NULL
, *n
;
1612 struct vme_bridge
*ca91cx42_bridge
;
1613 struct ca91cx42_driver
*ca91cx42_device
;
1614 struct vme_master_resource
*master_image
;
1615 struct vme_slave_resource
*slave_image
;
1616 struct vme_dma_resource
*dma_ctrlr
;
1617 struct vme_lm_resource
*lm
;
1619 /* We want to support more than one of each bridge so we need to
1620 * dynamically allocate the bridge structure
1622 ca91cx42_bridge
= kzalloc(sizeof(struct vme_bridge
), GFP_KERNEL
);
1624 if (ca91cx42_bridge
== NULL
) {
1625 dev_err(&pdev
->dev
, "Failed to allocate memory for device "
1631 ca91cx42_device
= kzalloc(sizeof(struct ca91cx42_driver
), GFP_KERNEL
);
1633 if (ca91cx42_device
== NULL
) {
1634 dev_err(&pdev
->dev
, "Failed to allocate memory for device "
1640 ca91cx42_bridge
->driver_priv
= ca91cx42_device
;
1642 /* Enable the device */
1643 retval
= pci_enable_device(pdev
);
1645 dev_err(&pdev
->dev
, "Unable to enable device\n");
1650 retval
= pci_request_regions(pdev
, driver_name
);
1652 dev_err(&pdev
->dev
, "Unable to reserve resources\n");
1656 /* map registers in BAR 0 */
1657 ca91cx42_device
->base
= ioremap_nocache(pci_resource_start(pdev
, 0),
1659 if (!ca91cx42_device
->base
) {
1660 dev_err(&pdev
->dev
, "Unable to remap CRG region\n");
1665 /* Check to see if the mapping worked out */
1666 data
= ioread32(ca91cx42_device
->base
+ CA91CX42_PCI_ID
) & 0x0000FFFF;
1667 if (data
!= PCI_VENDOR_ID_TUNDRA
) {
1668 dev_err(&pdev
->dev
, "PCI_ID check failed\n");
1673 /* Initialize wait queues & mutual exclusion flags */
1674 init_waitqueue_head(&ca91cx42_device
->dma_queue
);
1675 init_waitqueue_head(&ca91cx42_device
->iack_queue
);
1676 mutex_init(&ca91cx42_device
->vme_int
);
1677 mutex_init(&ca91cx42_device
->vme_rmw
);
1679 ca91cx42_bridge
->parent
= &pdev
->dev
;
1680 strcpy(ca91cx42_bridge
->name
, driver_name
);
1683 retval
= ca91cx42_irq_init(ca91cx42_bridge
);
1685 dev_err(&pdev
->dev
, "Chip Initialization failed.\n");
1689 /* Add master windows to list */
1690 INIT_LIST_HEAD(&ca91cx42_bridge
->master_resources
);
1691 for (i
= 0; i
< CA91C142_MAX_MASTER
; i
++) {
1692 master_image
= kmalloc(sizeof(struct vme_master_resource
),
1694 if (master_image
== NULL
) {
1695 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1696 "master resource structure\n");
1700 master_image
->parent
= ca91cx42_bridge
;
1701 spin_lock_init(&master_image
->lock
);
1702 master_image
->locked
= 0;
1703 master_image
->number
= i
;
1704 master_image
->address_attr
= VME_A16
| VME_A24
| VME_A32
|
1705 VME_CRCSR
| VME_USER1
| VME_USER2
;
1706 master_image
->cycle_attr
= VME_SCT
| VME_BLT
| VME_MBLT
|
1707 VME_SUPER
| VME_USER
| VME_PROG
| VME_DATA
;
1708 master_image
->width_attr
= VME_D8
| VME_D16
| VME_D32
| VME_D64
;
1709 memset(&master_image
->bus_resource
, 0,
1710 sizeof(struct resource
));
1711 master_image
->kern_base
= NULL
;
1712 list_add_tail(&master_image
->list
,
1713 &ca91cx42_bridge
->master_resources
);
1716 /* Add slave windows to list */
1717 INIT_LIST_HEAD(&ca91cx42_bridge
->slave_resources
);
1718 for (i
= 0; i
< CA91C142_MAX_SLAVE
; i
++) {
1719 slave_image
= kmalloc(sizeof(struct vme_slave_resource
),
1721 if (slave_image
== NULL
) {
1722 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1723 "slave resource structure\n");
1727 slave_image
->parent
= ca91cx42_bridge
;
1728 mutex_init(&slave_image
->mtx
);
1729 slave_image
->locked
= 0;
1730 slave_image
->number
= i
;
1731 slave_image
->address_attr
= VME_A24
| VME_A32
| VME_USER1
|
1734 /* Only windows 0 and 4 support A16 */
1735 if (i
== 0 || i
== 4)
1736 slave_image
->address_attr
|= VME_A16
;
1738 slave_image
->cycle_attr
= VME_SCT
| VME_BLT
| VME_MBLT
|
1739 VME_SUPER
| VME_USER
| VME_PROG
| VME_DATA
;
1740 list_add_tail(&slave_image
->list
,
1741 &ca91cx42_bridge
->slave_resources
);
1744 /* Add dma engines to list */
1745 INIT_LIST_HEAD(&ca91cx42_bridge
->dma_resources
);
1746 for (i
= 0; i
< CA91C142_MAX_DMA
; i
++) {
1747 dma_ctrlr
= kmalloc(sizeof(struct vme_dma_resource
),
1749 if (dma_ctrlr
== NULL
) {
1750 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1751 "dma resource structure\n");
1755 dma_ctrlr
->parent
= ca91cx42_bridge
;
1756 mutex_init(&dma_ctrlr
->mtx
);
1757 dma_ctrlr
->locked
= 0;
1758 dma_ctrlr
->number
= i
;
1759 dma_ctrlr
->route_attr
= VME_DMA_VME_TO_MEM
|
1761 INIT_LIST_HEAD(&dma_ctrlr
->pending
);
1762 INIT_LIST_HEAD(&dma_ctrlr
->running
);
1763 list_add_tail(&dma_ctrlr
->list
,
1764 &ca91cx42_bridge
->dma_resources
);
1767 /* Add location monitor to list */
1768 INIT_LIST_HEAD(&ca91cx42_bridge
->lm_resources
);
1769 lm
= kmalloc(sizeof(struct vme_lm_resource
), GFP_KERNEL
);
1771 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1772 "location monitor resource structure\n");
1776 lm
->parent
= ca91cx42_bridge
;
1777 mutex_init(&lm
->mtx
);
1781 list_add_tail(&lm
->list
, &ca91cx42_bridge
->lm_resources
);
1783 ca91cx42_bridge
->slave_get
= ca91cx42_slave_get
;
1784 ca91cx42_bridge
->slave_set
= ca91cx42_slave_set
;
1785 ca91cx42_bridge
->master_get
= ca91cx42_master_get
;
1786 ca91cx42_bridge
->master_set
= ca91cx42_master_set
;
1787 ca91cx42_bridge
->master_read
= ca91cx42_master_read
;
1788 ca91cx42_bridge
->master_write
= ca91cx42_master_write
;
1789 ca91cx42_bridge
->master_rmw
= ca91cx42_master_rmw
;
1790 ca91cx42_bridge
->dma_list_add
= ca91cx42_dma_list_add
;
1791 ca91cx42_bridge
->dma_list_exec
= ca91cx42_dma_list_exec
;
1792 ca91cx42_bridge
->dma_list_empty
= ca91cx42_dma_list_empty
;
1793 ca91cx42_bridge
->irq_set
= ca91cx42_irq_set
;
1794 ca91cx42_bridge
->irq_generate
= ca91cx42_irq_generate
;
1795 ca91cx42_bridge
->lm_set
= ca91cx42_lm_set
;
1796 ca91cx42_bridge
->lm_get
= ca91cx42_lm_get
;
1797 ca91cx42_bridge
->lm_attach
= ca91cx42_lm_attach
;
1798 ca91cx42_bridge
->lm_detach
= ca91cx42_lm_detach
;
1799 ca91cx42_bridge
->slot_get
= ca91cx42_slot_get
;
1800 ca91cx42_bridge
->alloc_consistent
= ca91cx42_alloc_consistent
;
1801 ca91cx42_bridge
->free_consistent
= ca91cx42_free_consistent
;
1803 data
= ioread32(ca91cx42_device
->base
+ MISC_CTL
);
1804 dev_info(&pdev
->dev
, "Board is%s the VME system controller\n",
1805 (data
& CA91CX42_MISC_CTL_SYSCON
) ? "" : " not");
1806 dev_info(&pdev
->dev
, "Slot ID is %d\n",
1807 ca91cx42_slot_get(ca91cx42_bridge
));
1809 if (ca91cx42_crcsr_init(ca91cx42_bridge
, pdev
))
1810 dev_err(&pdev
->dev
, "CR/CSR configuration failed.\n");
1812 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1815 retval
= vme_register_bridge(ca91cx42_bridge
);
1817 dev_err(&pdev
->dev
, "Chip Registration failed.\n");
1821 pci_set_drvdata(pdev
, ca91cx42_bridge
);
1826 ca91cx42_crcsr_exit(ca91cx42_bridge
, pdev
);
1828 /* resources are stored in link list */
1829 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->lm_resources
) {
1830 lm
= list_entry(pos
, struct vme_lm_resource
, list
);
1835 /* resources are stored in link list */
1836 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->dma_resources
) {
1837 dma_ctrlr
= list_entry(pos
, struct vme_dma_resource
, list
);
1842 /* resources are stored in link list */
1843 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->slave_resources
) {
1844 slave_image
= list_entry(pos
, struct vme_slave_resource
, list
);
1849 /* resources are stored in link list */
1850 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->master_resources
) {
1851 master_image
= list_entry(pos
, struct vme_master_resource
,
1854 kfree(master_image
);
1857 ca91cx42_irq_exit(ca91cx42_device
, pdev
);
1860 iounmap(ca91cx42_device
->base
);
1862 pci_release_regions(pdev
);
1864 pci_disable_device(pdev
);
1866 kfree(ca91cx42_device
);
1868 kfree(ca91cx42_bridge
);
1874 static void ca91cx42_remove(struct pci_dev
*pdev
)
1876 struct list_head
*pos
= NULL
, *n
;
1877 struct vme_master_resource
*master_image
;
1878 struct vme_slave_resource
*slave_image
;
1879 struct vme_dma_resource
*dma_ctrlr
;
1880 struct vme_lm_resource
*lm
;
1881 struct ca91cx42_driver
*bridge
;
1882 struct vme_bridge
*ca91cx42_bridge
= pci_get_drvdata(pdev
);
1884 bridge
= ca91cx42_bridge
->driver_priv
;
1888 iowrite32(0, bridge
->base
+ LINT_EN
);
1890 /* Turn off the windows */
1891 iowrite32(0x00800000, bridge
->base
+ LSI0_CTL
);
1892 iowrite32(0x00800000, bridge
->base
+ LSI1_CTL
);
1893 iowrite32(0x00800000, bridge
->base
+ LSI2_CTL
);
1894 iowrite32(0x00800000, bridge
->base
+ LSI3_CTL
);
1895 iowrite32(0x00800000, bridge
->base
+ LSI4_CTL
);
1896 iowrite32(0x00800000, bridge
->base
+ LSI5_CTL
);
1897 iowrite32(0x00800000, bridge
->base
+ LSI6_CTL
);
1898 iowrite32(0x00800000, bridge
->base
+ LSI7_CTL
);
1899 iowrite32(0x00F00000, bridge
->base
+ VSI0_CTL
);
1900 iowrite32(0x00F00000, bridge
->base
+ VSI1_CTL
);
1901 iowrite32(0x00F00000, bridge
->base
+ VSI2_CTL
);
1902 iowrite32(0x00F00000, bridge
->base
+ VSI3_CTL
);
1903 iowrite32(0x00F00000, bridge
->base
+ VSI4_CTL
);
1904 iowrite32(0x00F00000, bridge
->base
+ VSI5_CTL
);
1905 iowrite32(0x00F00000, bridge
->base
+ VSI6_CTL
);
1906 iowrite32(0x00F00000, bridge
->base
+ VSI7_CTL
);
1908 vme_unregister_bridge(ca91cx42_bridge
);
1910 ca91cx42_crcsr_exit(ca91cx42_bridge
, pdev
);
1912 /* resources are stored in link list */
1913 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->lm_resources
) {
1914 lm
= list_entry(pos
, struct vme_lm_resource
, list
);
1919 /* resources are stored in link list */
1920 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->dma_resources
) {
1921 dma_ctrlr
= list_entry(pos
, struct vme_dma_resource
, list
);
1926 /* resources are stored in link list */
1927 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->slave_resources
) {
1928 slave_image
= list_entry(pos
, struct vme_slave_resource
, list
);
1933 /* resources are stored in link list */
1934 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->master_resources
) {
1935 master_image
= list_entry(pos
, struct vme_master_resource
,
1938 kfree(master_image
);
1941 ca91cx42_irq_exit(bridge
, pdev
);
1943 iounmap(bridge
->base
);
1945 pci_release_regions(pdev
);
1947 pci_disable_device(pdev
);
1949 kfree(ca91cx42_bridge
);
1952 module_pci_driver(ca91cx42_driver
);
1954 MODULE_PARM_DESC(geoid
, "Override geographical addressing");
1955 module_param(geoid
, int, 0);
1957 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1958 MODULE_LICENSE("GPL");