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[WATCHDOG] iTCO_wdt.c init & exit fixes
[deliverable/linux.git] / drivers / watchdog / iTCO_wdt.c
1 /*
2 * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
3 *
4 * (c) Copyright 2006-2007 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * 82801AA (ICH) : document number 290655-003, 290677-014,
18 * 82801AB (ICHO) : document number 290655-003, 290677-014,
19 * 82801BA (ICH2) : document number 290687-002, 298242-027,
20 * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
21 * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
22 * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
23 * 82801DB (ICH4) : document number 290744-001, 290745-020,
24 * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
25 * 82801E (C-ICH) : document number 273599-001, 273645-002,
26 * 82801EB (ICH5) : document number 252516-001, 252517-003,
27 * 82801ER (ICH5R) : document number 252516-001, 252517-003,
28 * 82801FB (ICH6) : document number 301473-002, 301474-007,
29 * 82801FR (ICH6R) : document number 301473-002, 301474-007,
30 * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
31 * 82801FW (ICH6W) : document number 301473-001, 301474-007,
32 * 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
33 * 82801GB (ICH7) : document number 307013-002, 307014-009,
34 * 82801GR (ICH7R) : document number 307013-002, 307014-009,
35 * 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
36 * 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
37 * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
38 * 82801HB (ICH8) : document number 313056-002, 313057-004,
39 * 82801HR (ICH8R) : document number 313056-002, 313057-004,
40 * 82801HH (ICH8DH) : document number 313056-002, 313057-004,
41 * 82801HO (ICH8DO) : document number 313056-002, 313057-004,
42 * 82801IB (ICH9) : document number 316972-001, 316973-001,
43 * 82801IR (ICH9R) : document number 316972-001, 316973-001,
44 * 82801IH (ICH9DH) : document number 316972-001, 316973-001,
45 * 6300ESB (6300ESB) : document number 300641-003, 300884-010,
46 * 631xESB (631xESB) : document number 313082-001, 313075-005,
47 * 632xESB (632xESB) : document number 313082-001, 313075-005
48 */
49
50 /*
51 * Includes, defines, variables, module parameters, ...
52 */
53
54 /* Module and version information */
55 #define DRV_NAME "iTCO_wdt"
56 #define DRV_VERSION "1.02"
57 #define DRV_RELDATE "26-Jul-2007"
58 #define PFX DRV_NAME ": "
59
60 /* Includes */
61 #include <linux/module.h> /* For module specific items */
62 #include <linux/moduleparam.h> /* For new moduleparam's */
63 #include <linux/types.h> /* For standard types (like size_t) */
64 #include <linux/errno.h> /* For the -ENODEV/... values */
65 #include <linux/kernel.h> /* For printk/panic/... */
66 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */
67 #include <linux/watchdog.h> /* For the watchdog specific items */
68 #include <linux/init.h> /* For __init/__exit/... */
69 #include <linux/fs.h> /* For file operations */
70 #include <linux/platform_device.h> /* For platform_driver framework */
71 #include <linux/pci.h> /* For pci functions */
72 #include <linux/ioport.h> /* For io-port access */
73 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
74
75 #include <asm/uaccess.h> /* For copy_to_user/put_user/... */
76 #include <asm/io.h> /* For inb/outb/... */
77
78 /* TCO related info */
79 enum iTCO_chipsets {
80 TCO_ICH = 0, /* ICH */
81 TCO_ICH0, /* ICH0 */
82 TCO_ICH2, /* ICH2 */
83 TCO_ICH2M, /* ICH2-M */
84 TCO_ICH3, /* ICH3-S */
85 TCO_ICH3M, /* ICH3-M */
86 TCO_ICH4, /* ICH4 */
87 TCO_ICH4M, /* ICH4-M */
88 TCO_CICH, /* C-ICH */
89 TCO_ICH5, /* ICH5 & ICH5R */
90 TCO_6300ESB, /* 6300ESB */
91 TCO_ICH6, /* ICH6 & ICH6R */
92 TCO_ICH6M, /* ICH6-M */
93 TCO_ICH6W, /* ICH6W & ICH6RW */
94 TCO_ICH7, /* ICH7 & ICH7R */
95 TCO_ICH7M, /* ICH7-M */
96 TCO_ICH7MDH, /* ICH7-M DH */
97 TCO_ICH8, /* ICH8 & ICH8R */
98 TCO_ICH8DH, /* ICH8DH */
99 TCO_ICH8DO, /* ICH8DO */
100 TCO_ICH9, /* ICH9 */
101 TCO_ICH9R, /* ICH9R */
102 TCO_ICH9DH, /* ICH9DH */
103 TCO_631XESB, /* 631xESB/632xESB */
104 };
105
106 static struct {
107 char *name;
108 unsigned int iTCO_version;
109 } iTCO_chipset_info[] __devinitdata = {
110 {"ICH", 1},
111 {"ICH0", 1},
112 {"ICH2", 1},
113 {"ICH2-M", 1},
114 {"ICH3-S", 1},
115 {"ICH3-M", 1},
116 {"ICH4", 1},
117 {"ICH4-M", 1},
118 {"C-ICH", 1},
119 {"ICH5 or ICH5R", 1},
120 {"6300ESB", 1},
121 {"ICH6 or ICH6R", 2},
122 {"ICH6-M", 2},
123 {"ICH6W or ICH6RW", 2},
124 {"ICH7 or ICH7R", 2},
125 {"ICH7-M", 2},
126 {"ICH7-M DH", 2},
127 {"ICH8 or ICH8R", 2},
128 {"ICH8DH", 2},
129 {"ICH8DO", 2},
130 {"ICH9", 2},
131 {"ICH9R", 2},
132 {"ICH9DH", 2},
133 {"631xESB/632xESB", 2},
134 {NULL,0}
135 };
136
137 #define ITCO_PCI_DEVICE(dev, data) \
138 .vendor = PCI_VENDOR_ID_INTEL, \
139 .device = dev, \
140 .subvendor = PCI_ANY_ID, \
141 .subdevice = PCI_ANY_ID, \
142 .class = 0, \
143 .class_mask = 0, \
144 .driver_data = data
145
146 /*
147 * This data only exists for exporting the supported PCI ids
148 * via MODULE_DEVICE_TABLE. We do not actually register a
149 * pci_driver, because the I/O Controller Hub has also other
150 * functions that probably will be registered by other drivers.
151 */
152 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
153 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH )},
154 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0 )},
155 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2 )},
156 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M )},
157 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3 )},
158 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M )},
159 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4 )},
160 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M )},
161 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH )},
162 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5 )},
163 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
164 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6 )},
165 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M )},
166 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W )},
167 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7 )},
168 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M )},
169 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
170 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8 )},
171 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH )},
172 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO )},
173 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9 )},
174 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R )},
175 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH )},
176 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
177 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
178 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
179 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
180 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
181 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
182 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
183 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
184 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
185 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
186 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
187 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
188 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
189 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
190 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
191 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
192 { 0, }, /* End of list */
193 };
194 MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl);
195
196 /* Address definitions for the TCO */
197 #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */
198 #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */
199
200 #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */
201 #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
202 #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
203 #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
204 #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
205 #define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
206 #define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
207 #define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
208 #define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
209
210 /* internal variables */
211 static unsigned long is_active;
212 static char expect_release;
213 static struct { /* this is private data for the iTCO_wdt device */
214 unsigned int iTCO_version; /* TCO version/generation */
215 unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
216 unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */
217 spinlock_t io_lock; /* the lock for io operations */
218 struct pci_dev *pdev; /* the PCI-device */
219 } iTCO_wdt_private;
220
221 static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */
222
223 /* module parameters */
224 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
225 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
226 module_param(heartbeat, int, 0);
227 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
228
229 static int nowayout = WATCHDOG_NOWAYOUT;
230 module_param(nowayout, int, 0);
231 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
232
233 /* iTCO Vendor Specific Support hooks */
234 #ifdef CONFIG_ITCO_VENDOR_SUPPORT
235 extern void iTCO_vendor_pre_start(unsigned long, unsigned int);
236 extern void iTCO_vendor_pre_stop(unsigned long);
237 extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int);
238 extern void iTCO_vendor_pre_set_heartbeat(unsigned int);
239 extern int iTCO_vendor_check_noreboot_on(void);
240 #else
241 #define iTCO_vendor_pre_start(acpibase, heartbeat) {}
242 #define iTCO_vendor_pre_stop(acpibase) {}
243 #define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {}
244 #define iTCO_vendor_pre_set_heartbeat(heartbeat) {}
245 #define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */
246 #endif
247
248 /*
249 * Some TCO specific functions
250 */
251
252 static inline unsigned int seconds_to_ticks(int seconds)
253 {
254 /* the internal timer is stored as ticks which decrement
255 * every 0.6 seconds */
256 return (seconds * 10) / 6;
257 }
258
259 static void iTCO_wdt_set_NO_REBOOT_bit(void)
260 {
261 u32 val32;
262
263 /* Set the NO_REBOOT bit: this disables reboots */
264 if (iTCO_wdt_private.iTCO_version == 2) {
265 val32 = readl(iTCO_wdt_private.gcs);
266 val32 |= 0x00000020;
267 writel(val32, iTCO_wdt_private.gcs);
268 } else if (iTCO_wdt_private.iTCO_version == 1) {
269 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
270 val32 |= 0x00000002;
271 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
272 }
273 }
274
275 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
276 {
277 int ret = 0;
278 u32 val32;
279
280 /* Unset the NO_REBOOT bit: this enables reboots */
281 if (iTCO_wdt_private.iTCO_version == 2) {
282 val32 = readl(iTCO_wdt_private.gcs);
283 val32 &= 0xffffffdf;
284 writel(val32, iTCO_wdt_private.gcs);
285
286 val32 = readl(iTCO_wdt_private.gcs);
287 if (val32 & 0x00000020)
288 ret = -EIO;
289 } else if (iTCO_wdt_private.iTCO_version == 1) {
290 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
291 val32 &= 0xfffffffd;
292 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
293
294 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
295 if (val32 & 0x00000002)
296 ret = -EIO;
297 }
298
299 return ret; /* returns: 0 = OK, -EIO = Error */
300 }
301
302 static int iTCO_wdt_start(void)
303 {
304 unsigned int val;
305
306 spin_lock(&iTCO_wdt_private.io_lock);
307
308 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
309
310 /* disable chipset's NO_REBOOT bit */
311 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
312 spin_unlock(&iTCO_wdt_private.io_lock);
313 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
314 return -EIO;
315 }
316
317 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
318 val = inw(TCO1_CNT);
319 val &= 0xf7ff;
320 outw(val, TCO1_CNT);
321 val = inw(TCO1_CNT);
322 spin_unlock(&iTCO_wdt_private.io_lock);
323
324 if (val & 0x0800)
325 return -1;
326 return 0;
327 }
328
329 static int iTCO_wdt_stop(void)
330 {
331 unsigned int val;
332
333 spin_lock(&iTCO_wdt_private.io_lock);
334
335 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
336
337 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
338 val = inw(TCO1_CNT);
339 val |= 0x0800;
340 outw(val, TCO1_CNT);
341 val = inw(TCO1_CNT);
342
343 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
344 iTCO_wdt_set_NO_REBOOT_bit();
345
346 spin_unlock(&iTCO_wdt_private.io_lock);
347
348 if ((val & 0x0800) == 0)
349 return -1;
350 return 0;
351 }
352
353 static int iTCO_wdt_keepalive(void)
354 {
355 spin_lock(&iTCO_wdt_private.io_lock);
356
357 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
358
359 /* Reload the timer by writing to the TCO Timer Counter register */
360 if (iTCO_wdt_private.iTCO_version == 2) {
361 outw(0x01, TCO_RLD);
362 } else if (iTCO_wdt_private.iTCO_version == 1) {
363 outb(0x01, TCO_RLD);
364 }
365
366 spin_unlock(&iTCO_wdt_private.io_lock);
367 return 0;
368 }
369
370 static int iTCO_wdt_set_heartbeat(int t)
371 {
372 unsigned int val16;
373 unsigned char val8;
374 unsigned int tmrval;
375
376 tmrval = seconds_to_ticks(t);
377 /* from the specs: */
378 /* "Values of 0h-3h are ignored and should not be attempted" */
379 if (tmrval < 0x04)
380 return -EINVAL;
381 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
382 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
383 return -EINVAL;
384
385 iTCO_vendor_pre_set_heartbeat(tmrval);
386
387 /* Write new heartbeat to watchdog */
388 if (iTCO_wdt_private.iTCO_version == 2) {
389 spin_lock(&iTCO_wdt_private.io_lock);
390 val16 = inw(TCOv2_TMR);
391 val16 &= 0xfc00;
392 val16 |= tmrval;
393 outw(val16, TCOv2_TMR);
394 val16 = inw(TCOv2_TMR);
395 spin_unlock(&iTCO_wdt_private.io_lock);
396
397 if ((val16 & 0x3ff) != tmrval)
398 return -EINVAL;
399 } else if (iTCO_wdt_private.iTCO_version == 1) {
400 spin_lock(&iTCO_wdt_private.io_lock);
401 val8 = inb(TCOv1_TMR);
402 val8 &= 0xc0;
403 val8 |= (tmrval & 0xff);
404 outb(val8, TCOv1_TMR);
405 val8 = inb(TCOv1_TMR);
406 spin_unlock(&iTCO_wdt_private.io_lock);
407
408 if ((val8 & 0x3f) != tmrval)
409 return -EINVAL;
410 }
411
412 heartbeat = t;
413 return 0;
414 }
415
416 static int iTCO_wdt_get_timeleft (int *time_left)
417 {
418 unsigned int val16;
419 unsigned char val8;
420
421 /* read the TCO Timer */
422 if (iTCO_wdt_private.iTCO_version == 2) {
423 spin_lock(&iTCO_wdt_private.io_lock);
424 val16 = inw(TCO_RLD);
425 val16 &= 0x3ff;
426 spin_unlock(&iTCO_wdt_private.io_lock);
427
428 *time_left = (val16 * 6) / 10;
429 } else if (iTCO_wdt_private.iTCO_version == 1) {
430 spin_lock(&iTCO_wdt_private.io_lock);
431 val8 = inb(TCO_RLD);
432 val8 &= 0x3f;
433 spin_unlock(&iTCO_wdt_private.io_lock);
434
435 *time_left = (val8 * 6) / 10;
436 } else
437 return -EINVAL;
438 return 0;
439 }
440
441 /*
442 * /dev/watchdog handling
443 */
444
445 static int iTCO_wdt_open (struct inode *inode, struct file *file)
446 {
447 /* /dev/watchdog can only be opened once */
448 if (test_and_set_bit(0, &is_active))
449 return -EBUSY;
450
451 /*
452 * Reload and activate timer
453 */
454 iTCO_wdt_keepalive();
455 iTCO_wdt_start();
456 return nonseekable_open(inode, file);
457 }
458
459 static int iTCO_wdt_release (struct inode *inode, struct file *file)
460 {
461 /*
462 * Shut off the timer.
463 */
464 if (expect_release == 42) {
465 iTCO_wdt_stop();
466 } else {
467 printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n");
468 iTCO_wdt_keepalive();
469 }
470 clear_bit(0, &is_active);
471 expect_release = 0;
472 return 0;
473 }
474
475 static ssize_t iTCO_wdt_write (struct file *file, const char __user *data,
476 size_t len, loff_t * ppos)
477 {
478 /* See if we got the magic character 'V' and reload the timer */
479 if (len) {
480 if (!nowayout) {
481 size_t i;
482
483 /* note: just in case someone wrote the magic character
484 * five months ago... */
485 expect_release = 0;
486
487 /* scan to see whether or not we got the magic character */
488 for (i = 0; i != len; i++) {
489 char c;
490 if (get_user(c, data+i))
491 return -EFAULT;
492 if (c == 'V')
493 expect_release = 42;
494 }
495 }
496
497 /* someone wrote to us, we should reload the timer */
498 iTCO_wdt_keepalive();
499 }
500 return len;
501 }
502
503 static int iTCO_wdt_ioctl (struct inode *inode, struct file *file,
504 unsigned int cmd, unsigned long arg)
505 {
506 int new_options, retval = -EINVAL;
507 int new_heartbeat;
508 void __user *argp = (void __user *)arg;
509 int __user *p = argp;
510 static struct watchdog_info ident = {
511 .options = WDIOF_SETTIMEOUT |
512 WDIOF_KEEPALIVEPING |
513 WDIOF_MAGICCLOSE,
514 .firmware_version = 0,
515 .identity = DRV_NAME,
516 };
517
518 switch (cmd) {
519 case WDIOC_GETSUPPORT:
520 return copy_to_user(argp, &ident,
521 sizeof (ident)) ? -EFAULT : 0;
522
523 case WDIOC_GETSTATUS:
524 case WDIOC_GETBOOTSTATUS:
525 return put_user(0, p);
526
527 case WDIOC_KEEPALIVE:
528 iTCO_wdt_keepalive();
529 return 0;
530
531 case WDIOC_SETOPTIONS:
532 {
533 if (get_user(new_options, p))
534 return -EFAULT;
535
536 if (new_options & WDIOS_DISABLECARD) {
537 iTCO_wdt_stop();
538 retval = 0;
539 }
540
541 if (new_options & WDIOS_ENABLECARD) {
542 iTCO_wdt_keepalive();
543 iTCO_wdt_start();
544 retval = 0;
545 }
546
547 return retval;
548 }
549
550 case WDIOC_SETTIMEOUT:
551 {
552 if (get_user(new_heartbeat, p))
553 return -EFAULT;
554
555 if (iTCO_wdt_set_heartbeat(new_heartbeat))
556 return -EINVAL;
557
558 iTCO_wdt_keepalive();
559 /* Fall */
560 }
561
562 case WDIOC_GETTIMEOUT:
563 return put_user(heartbeat, p);
564
565 case WDIOC_GETTIMELEFT:
566 {
567 int time_left;
568
569 if (iTCO_wdt_get_timeleft(&time_left))
570 return -EINVAL;
571
572 return put_user(time_left, p);
573 }
574
575 default:
576 return -ENOTTY;
577 }
578 }
579
580 /*
581 * Kernel Interfaces
582 */
583
584 static const struct file_operations iTCO_wdt_fops = {
585 .owner = THIS_MODULE,
586 .llseek = no_llseek,
587 .write = iTCO_wdt_write,
588 .ioctl = iTCO_wdt_ioctl,
589 .open = iTCO_wdt_open,
590 .release = iTCO_wdt_release,
591 };
592
593 static struct miscdevice iTCO_wdt_miscdev = {
594 .minor = WATCHDOG_MINOR,
595 .name = "watchdog",
596 .fops = &iTCO_wdt_fops,
597 };
598
599 /*
600 * Init & exit routines
601 */
602
603 static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent, struct platform_device *dev)
604 {
605 int ret;
606 u32 base_address;
607 unsigned long RCBA;
608 unsigned long val32;
609
610 /*
611 * Find the ACPI/PM base I/O address which is the base
612 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
613 * ACPIBASE is bits [15:7] from 0x40-0x43
614 */
615 pci_read_config_dword(pdev, 0x40, &base_address);
616 base_address &= 0x0000ff80;
617 if (base_address == 0x00000000) {
618 /* Something's wrong here, ACPIBASE has to be set */
619 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
620 pci_dev_put(pdev);
621 return -ENODEV;
622 }
623 iTCO_wdt_private.iTCO_version = iTCO_chipset_info[ent->driver_data].iTCO_version;
624 iTCO_wdt_private.ACPIBASE = base_address;
625 iTCO_wdt_private.pdev = pdev;
626
627 /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */
628 /* To get access to it you have to read RCBA from PCI Config space 0xf0
629 and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */
630 if (iTCO_wdt_private.iTCO_version == 2) {
631 pci_read_config_dword(pdev, 0xf0, &base_address);
632 RCBA = base_address & 0xffffc000;
633 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4);
634 }
635
636 /* Check chipset's NO_REBOOT bit */
637 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
638 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
639 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
640 goto out;
641 }
642
643 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
644 iTCO_wdt_set_NO_REBOOT_bit();
645
646 /* Set the TCO_EN bit in SMI_EN register */
647 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
648 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
649 SMI_EN );
650 ret = -EIO;
651 goto out;
652 }
653 val32 = inl(SMI_EN);
654 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
655 outl(val32, SMI_EN);
656 release_region(SMI_EN, 4);
657
658 /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */
659 if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) {
660 printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n",
661 TCOBASE);
662 ret = -EIO;
663 goto out;
664 }
665
666 printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
667 iTCO_chipset_info[ent->driver_data].name,
668 iTCO_chipset_info[ent->driver_data].iTCO_version,
669 TCOBASE);
670
671 /* Clear out the (probably old) status */
672 outb(0, TCO1_STS);
673 outb(3, TCO2_STS);
674
675 /* Make sure the watchdog is not running */
676 iTCO_wdt_stop();
677
678 /* Check that the heartbeat value is within it's range ; if not reset to the default */
679 if (iTCO_wdt_set_heartbeat(heartbeat)) {
680 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
681 printk(KERN_INFO PFX "heartbeat value must be 2<heartbeat<39 (TCO v1) or 613 (TCO v2), using %d\n",
682 heartbeat);
683 }
684
685 ret = misc_register(&iTCO_wdt_miscdev);
686 if (ret != 0) {
687 printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
688 WATCHDOG_MINOR, ret);
689 goto unreg_region;
690 }
691
692 printk (KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
693 heartbeat, nowayout);
694
695 return 0;
696
697 unreg_region:
698 release_region (TCOBASE, 0x20);
699 out:
700 if (iTCO_wdt_private.iTCO_version == 2)
701 iounmap(iTCO_wdt_private.gcs);
702 pci_dev_put(iTCO_wdt_private.pdev);
703 iTCO_wdt_private.ACPIBASE = 0;
704 return ret;
705 }
706
707 static void __devexit iTCO_wdt_cleanup(void)
708 {
709 /* Stop the timer before we leave */
710 if (!nowayout)
711 iTCO_wdt_stop();
712
713 /* Deregister */
714 misc_deregister(&iTCO_wdt_miscdev);
715 release_region(TCOBASE, 0x20);
716 if (iTCO_wdt_private.iTCO_version == 2)
717 iounmap(iTCO_wdt_private.gcs);
718 pci_dev_put(iTCO_wdt_private.pdev);
719 iTCO_wdt_private.ACPIBASE = 0;
720 }
721
722 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
723 {
724 int found = 0;
725 struct pci_dev *pdev = NULL;
726 const struct pci_device_id *ent;
727
728 spin_lock_init(&iTCO_wdt_private.io_lock);
729
730 for_each_pci_dev(pdev) {
731 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
732 if (ent) {
733 if (!(iTCO_wdt_init(pdev, ent, dev))) {
734 found++;
735 break;
736 }
737 }
738 }
739
740 if (!found) {
741 printk(KERN_INFO PFX "No card detected\n");
742 return -ENODEV;
743 }
744
745 return 0;
746 }
747
748 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
749 {
750 if (iTCO_wdt_private.ACPIBASE)
751 iTCO_wdt_cleanup();
752
753 return 0;
754 }
755
756 static void iTCO_wdt_shutdown(struct platform_device *dev)
757 {
758 iTCO_wdt_stop();
759 }
760
761 #define iTCO_wdt_suspend NULL
762 #define iTCO_wdt_resume NULL
763
764 static struct platform_driver iTCO_wdt_driver = {
765 .probe = iTCO_wdt_probe,
766 .remove = __devexit_p(iTCO_wdt_remove),
767 .shutdown = iTCO_wdt_shutdown,
768 .suspend = iTCO_wdt_suspend,
769 .resume = iTCO_wdt_resume,
770 .driver = {
771 .owner = THIS_MODULE,
772 .name = DRV_NAME,
773 },
774 };
775
776 static int __init iTCO_wdt_init_module(void)
777 {
778 int err;
779
780 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n",
781 DRV_VERSION, DRV_RELDATE);
782
783 err = platform_driver_register(&iTCO_wdt_driver);
784 if (err)
785 return err;
786
787 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0);
788 if (IS_ERR(iTCO_wdt_platform_device)) {
789 err = PTR_ERR(iTCO_wdt_platform_device);
790 goto unreg_platform_driver;
791 }
792
793 return 0;
794
795 unreg_platform_driver:
796 platform_driver_unregister(&iTCO_wdt_driver);
797 return err;
798 }
799
800 static void __exit iTCO_wdt_cleanup_module(void)
801 {
802 platform_device_unregister(iTCO_wdt_platform_device);
803 platform_driver_unregister(&iTCO_wdt_driver);
804 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
805 }
806
807 module_init(iTCO_wdt_init_module);
808 module_exit(iTCO_wdt_cleanup_module);
809
810 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
811 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
812 MODULE_VERSION(DRV_VERSION);
813 MODULE_LICENSE("GPL");
814 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Linux kernel - Deliverables
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