RISC-V: Disassemble x0 based addresses as 0.
[deliverable/binutils-gdb.git] / gas / ChangeLog
1 2018-01-09 Jim Wilson <jimw@sifive.com>
2
3 * testsuite/gas/riscv/auipc-x0.d: New.
4 * testsuite/gas/riscv/auipc-x0.s: New.
5
6 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
7
8 * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
9 in Arm execution state, and Armv6T2 and above in Thumb execution
10 state.
11 * testsuite/gas/arm/csdb.s: New.
12 * testsuite/gas/arm/csdb.d: New.
13 * testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
14 * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
15
16 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
17
18 * testsuite/gas/aarch64/system.d: Update expected results to expect
19 CSDB for hint 0x14.
20
21 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
22
23 PR gas/22681
24 * testsuite/gas/i386/i386.exp: Run x86-64-movd and
25 x86-64-movd-intel.
26 * testsuite/gas/i386/x86-64-movd-intel.d: New file.
27 * testsuite/gas/i386/x86-64-movd.d: Likewise.
28 * testsuite/gas/i386/x86-64-movd.s: Likewise.
29
30 2018-01-08 Nick Clifton <nickc@redhat.com>
31
32 PR 22553
33 * doc/c-i386.texi (i386-Directives): Document the .largecomm
34 directive.
35
36 2018-01-04 Jim Wilson <jimw@sifive.com>
37
38 * testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
39 * testsuite/gas/riscv/priv-reg.d: Likewise.
40
41 2018-01-03 Alan Modra <amodra@gmail.com>
42
43 Update year range in copyright notice of all files.
44
45 2018-01-02 Nick Clifton <nickc@redhat.com>
46
47 PR 18119
48 * config/tc-arm.c (do_mrs): Fix test of bits 16-19 in non-banked
49 version of ARM MRS instruction.
50
51 For older changes see ChangeLog-2017
52 \f
53 Copyright (C) 2018 Free Software Foundation, Inc.
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