1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007, 2008
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii (ptr, reg, offset, w, op)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst (i, reg, aop, w, m)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp (reg, offset, w)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op (dst, src, opc)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc (t, b, offset)
81 #define UJUMP(offset) \
82 bfin_gen_ujump (offset)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl (prgfunc, poprnd)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg (reg, w)
93 #define CALLA(addr, s) \
94 bfin_gen_calla (addr, s)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage (r, framesize)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd (dst, src, op)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp (dst, src, op)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik (i, op)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim (i, m, op, br)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op (src0, src1, dst, opc)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op (dst, src, opc)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag (x, y, opc, i, g)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv (src, dst, t)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl (reg, a, op)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match(expr, bits, sign, mul, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match (expr, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match (expr, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match (expr, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match (expr, 24, 0, 2, 1))
155 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
161 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
163 static void notethat (char *format, ...);
165 char *current_inputline;
167 int yyerror (char *msg);
169 void error (char *format, ...)
172 static char buffer[2000];
174 va_start (ap, format);
175 vsprintf (buffer, format, ap);
178 as_bad ("%s", buffer);
187 else if (yytext[0] != ';')
188 error ("%s. Input text was %s.", msg, yytext);
196 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
198 int val = EXPR_VALUE (expr);
199 if (expr->type != Expr_Node_Constant)
201 if (val < from || val > to)
203 return (val & mask) == 0;
206 extern int yylex (void);
208 #define imm3(x) EXPR_VALUE (x)
209 #define imm4(x) EXPR_VALUE (x)
210 #define uimm4(x) EXPR_VALUE (x)
211 #define imm5(x) EXPR_VALUE (x)
212 #define uimm5(x) EXPR_VALUE (x)
213 #define imm6(x) EXPR_VALUE (x)
214 #define imm7(x) EXPR_VALUE (x)
215 #define imm16(x) EXPR_VALUE (x)
216 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
217 #define uimm16(x) EXPR_VALUE (x)
219 /* Return true if a value is inside a range. */
220 #define IN_RANGE(x, low, high) \
221 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
223 /* Auxiliary functions. */
226 neg_value (Expr_Node *expr)
228 expr->value.i_value = -expr->value.i_value;
232 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
234 if (!IS_DREG (*reg1))
236 yyerror ("Dregs expected");
240 if (reg1->regno != 1 && reg1->regno != 3)
242 yyerror ("Bad register pair");
246 if (imm7 (reg2) != reg1->regno - 1)
248 yyerror ("Bad register pair");
257 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
259 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
260 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
261 return yyerror ("Source multiplication register mismatch");
267 /* Check mac option. */
270 check_macfunc_option (Macfunc *a, Opt_mode *opt)
272 /* Default option is always valid. */
276 if ((a->w == 1 && a->P == 1
277 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
278 && opt->mod != M_S2RND && opt->mod != M_ISS2)
279 || (a->w == 1 && a->P == 0
280 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
281 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
282 && opt->mod != M_ISS2 && opt->mod != M_IH)
283 || (a->w == 0 && a->P == 0
284 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
290 /* Check (vector) mac funcs and ops. */
293 check_macfuncs (Macfunc *aa, Opt_mode *opa,
294 Macfunc *ab, Opt_mode *opb)
296 /* Variables for swapping. */
300 /* The option mode should be put at the end of the second instruction
301 of the vector except M, which should follow MAC1 instruction. */
303 return yyerror ("Bad opt mode");
305 /* If a0macfunc comes before a1macfunc, swap them. */
309 /* (M) is not allowed here. */
311 return yyerror ("(M) not allowed with A0MAC");
313 return yyerror ("Vector AxMACs can't be same");
315 mtmp = *aa; *aa = *ab; *ab = mtmp;
316 otmp = *opa; *opa = *opb; *opb = otmp;
321 return yyerror ("(M) not allowed with A0MAC");
323 return yyerror ("Vector AxMACs can't be same");
326 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
327 assignment_or_macfuncs. */
328 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
329 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
331 if (check_multiply_halfregs (aa, ab) < 0)
336 /* Only one of the assign_macfuncs has a half reg multiply
337 Evil trick: Just 'OR' their source register codes:
338 We can do that, because we know they were initialized to 0
339 in the rules that don't use multiply_halfregs. */
340 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
341 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
344 if (aa->w == ab->w && aa->P != ab->P)
346 return yyerror ("macfuncs must differ");
347 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
348 return yyerror ("Destination Dregs must differ by one");
351 /* Make sure mod flags get ORed, too. */
352 opb->mod |= opa->mod;
355 if (check_macfunc_option (aa, opb) < 0
356 && check_macfunc_option (ab, opb) < 0)
357 return yyerror ("bad option");
359 /* Make sure first macfunc has got both P flags ORed. */
367 is_group1 (INSTR_T x)
369 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
370 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
377 is_group2 (INSTR_T x)
379 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
380 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
381 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
382 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
383 || (x->value == 0x0000))
389 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
391 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
392 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
393 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
395 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
396 yyerror ("resource conflict in multi-issue instruction");
398 /* Anomaly 05000074 */
399 if (ENABLE_AC_05000074
400 && (dsp32->value & 0xf780) == 0xc680
401 && ((dsp16_grp1->value & 0xfe40) == 0x9240
402 || (dsp16_grp1->value & 0xfe08) == 0xba08
403 || (dsp16_grp1->value & 0xfc00) == 0xbc00))
404 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
405 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
407 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
419 struct { int r0; int s0; int x0; int aop; } modcodes;
420 struct { int r0; } r0;
427 /* Vector Specific. */
428 %token BYTEOP16P BYTEOP16M
429 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
430 %token BYTEUNPACK BYTEPACK
433 %token ALIGN8 ALIGN16 ALIGN24
435 %token EXTRACT DEPOSIT EXPADJ SEARCH
436 %token ONES SIGN SIGNBITS
444 %token CCREG BYTE_DREG
445 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
446 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
451 %token RTI RTS RTX RTN RTE
462 %token JUMP JUMP_DOT_S JUMP_DOT_L
469 %token NOT TILDA BANG
475 %token MINUS PLUS STAR SLASH
479 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
480 %token _MINUS_MINUS _PLUS_PLUS
482 /* Shift/rotate ops. */
483 %token SHIFT LSHIFT ASHIFT BXORSHIFT
484 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
486 %token LESS_LESS GREATER_GREATER
487 %token _GREATER_GREATER_GREATER
488 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
491 /* In place operators. */
492 %token ASSIGN _STAR_ASSIGN
493 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
494 %token _MINUS_ASSIGN _PLUS_ASSIGN
496 /* Assignments, comparisons. */
497 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
502 %token FLUSHINV FLUSH
503 %token IFLUSH PREFETCH
520 %token R RND RNDL RNDH RND12 RND20
525 %token BITTGL BITCLR BITSET BITTST BITMUX
528 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
530 /* Semantic auxiliaries. */
533 %token COLON SEMICOLON
534 %token RPAREN LPAREN LBRACK RBRACK
538 %token GOT GOT17M4 FUNCDESC_GOT17M4
548 %type <modcodes> byteop_mod
550 %type <reg> a_plusassign
551 %type <reg> a_minusassign
552 %type <macfunc> multiply_halfregs
553 %type <macfunc> assign_macfunc
554 %type <macfunc> a_macfunc
558 %type <modcodes> vsmod
559 %type <modcodes> ccstat
562 %type <reg> reg_with_postinc
563 %type <reg> reg_with_predec
567 %type <symbol> SYMBOL
570 %type <reg> BYTE_DREG
571 %type <reg> REG_A_DOUBLE_ZERO
572 %type <reg> REG_A_DOUBLE_ONE
574 %type <reg> STATUS_REG
578 %type <modcodes> smod
579 %type <modcodes> b3_op
580 %type <modcodes> rnd_op
581 %type <modcodes> post_op
583 %type <r0> iu_or_nothing
584 %type <r0> plus_minus
588 %type <modcodes> amod0
589 %type <modcodes> amod1
590 %type <modcodes> amod2
592 %type <r0> w32_or_nothing
596 %type <expr> got_or_expr
598 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
600 /* Precedence rules. */
604 %left LESS_LESS GREATER_GREATER
606 %left STAR SLASH PERCENT
617 if (insn == (INSTR_T) 0)
618 return NO_INSN_GENERATED;
619 else if (insn == (INSTR_T) - 1)
620 return SEMANTIC_ERROR;
622 return INSN_GENERATED;
627 /* Parallel instructions. */
628 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
630 if (($1->value & 0xf800) == 0xc000)
632 if (is_group1 ($3) && is_group2 ($5))
633 $$ = gen_multi_instr_1 ($1, $3, $5);
634 else if (is_group2 ($3) && is_group1 ($5))
635 $$ = gen_multi_instr_1 ($1, $5, $3);
637 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
639 else if (($3->value & 0xf800) == 0xc000)
641 if (is_group1 ($1) && is_group2 ($5))
642 $$ = gen_multi_instr_1 ($3, $1, $5);
643 else if (is_group2 ($1) && is_group1 ($5))
644 $$ = gen_multi_instr_1 ($3, $5, $1);
646 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
648 else if (($5->value & 0xf800) == 0xc000)
650 if (is_group1 ($1) && is_group2 ($3))
651 $$ = gen_multi_instr_1 ($5, $1, $3);
652 else if (is_group2 ($1) && is_group1 ($3))
653 $$ = gen_multi_instr_1 ($5, $3, $1);
655 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
658 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
661 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
663 if (($1->value & 0xf800) == 0xc000)
666 $$ = gen_multi_instr_1 ($1, $3, 0);
667 else if (is_group2 ($3))
668 $$ = gen_multi_instr_1 ($1, 0, $3);
670 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
672 else if (($3->value & 0xf800) == 0xc000)
675 $$ = gen_multi_instr_1 ($3, $1, 0);
676 else if (is_group2 ($1))
677 $$ = gen_multi_instr_1 ($3, 0, $1);
679 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
681 else if (is_group1 ($1) && is_group2 ($3))
682 $$ = gen_multi_instr_1 (0, $1, $3);
683 else if (is_group2 ($1) && is_group1 ($3))
684 $$ = gen_multi_instr_1 (0, $3, $1);
686 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
701 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
703 | assign_macfunc opt_mode
707 int h00, h10, h01, h11;
709 if (check_macfunc_option (&$1, &$2) < 0)
710 return yyerror ("bad option");
715 return yyerror ("(m) not allowed with a0 unit");
734 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
735 &$1.dst, op0, &$1.s0, &$1.s1, w0);
741 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
745 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
747 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
754 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
755 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
756 dst, $4.op, &$1.s0, &$1.s1, $4.w);
763 notethat ("dsp32alu: DISALGNEXCPT\n");
764 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
766 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
768 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
770 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
771 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
774 return yyerror ("Register mismatch");
776 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
778 if (!IS_A1 ($4) && IS_A1 ($5))
780 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
781 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
784 return yyerror ("Register mismatch");
786 | A_ZERO_DOT_H ASSIGN HALF_REG
788 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
789 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
791 | A_ONE_DOT_H ASSIGN HALF_REG
793 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
794 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
796 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
797 COLON expr COMMA REG COLON expr RPAREN aligndir
799 if (!IS_DREG ($2) || !IS_DREG ($4))
800 return yyerror ("Dregs expected");
801 else if (!valid_dreg_pair (&$9, $11))
802 return yyerror ("Bad dreg pair");
803 else if (!valid_dreg_pair (&$13, $15))
804 return yyerror ("Bad dreg pair");
807 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
808 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
812 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
813 REG COLON expr RPAREN aligndir
815 if (!IS_DREG ($2) || !IS_DREG($4))
816 return yyerror ("Dregs expected");
817 else if (!valid_dreg_pair (&$9, $11))
818 return yyerror ("Bad dreg pair");
819 else if (!valid_dreg_pair (&$13, $15))
820 return yyerror ("Bad dreg pair");
823 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
824 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
828 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
830 if (!IS_DREG ($2) || !IS_DREG ($4))
831 return yyerror ("Dregs expected");
832 else if (!valid_dreg_pair (&$8, $10))
833 return yyerror ("Bad dreg pair");
836 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
837 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
840 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
842 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
844 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
845 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
848 return yyerror ("Register mismatch");
850 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
851 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
853 if (IS_DREG ($1) && IS_DREG ($7))
855 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
856 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
859 return yyerror ("Register mismatch");
863 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
865 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
866 && IS_A1 ($9) && !IS_A1 ($11))
868 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
869 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
872 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
873 && !IS_A1 ($9) && IS_A1 ($11))
875 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
876 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
879 return yyerror ("Register mismatch");
882 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
885 return yyerror ("Operators must differ");
887 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
888 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
890 notethat ("dsp32alu: dregs = dregs + dregs,"
891 "dregs = dregs - dregs (amod1)\n");
892 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
895 return yyerror ("Register mismatch");
898 /* Bar Operations. */
900 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
902 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
903 return yyerror ("Differing source registers");
905 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
906 return yyerror ("Dregs expected");
909 if ($4.r0 == 1 && $10.r0 == 2)
911 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
912 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
914 else if ($4.r0 == 0 && $10.r0 == 3)
916 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
917 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
920 return yyerror ("Bar operand mismatch");
923 | REG ASSIGN ABS REG vmod
927 if (IS_DREG ($1) && IS_DREG ($4))
931 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
936 /* Vector version of ABS. */
937 notethat ("dsp32alu: dregs = ABS dregs\n");
940 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
943 return yyerror ("Dregs expected");
947 notethat ("dsp32alu: Ax = ABS Ax\n");
948 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
950 | A_ZERO_DOT_L ASSIGN HALF_REG
954 notethat ("dsp32alu: A0.l = reg_half\n");
955 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
958 return yyerror ("A0.l = Rx.l expected");
960 | A_ONE_DOT_L ASSIGN HALF_REG
964 notethat ("dsp32alu: A1.l = reg_half\n");
965 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
968 return yyerror ("A1.l = Rx.l expected");
971 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
973 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
975 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
976 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
979 return yyerror ("Dregs expected");
982 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
985 return yyerror ("Dregs expected");
986 else if (!valid_dreg_pair (&$5, $7))
987 return yyerror ("Bad dreg pair");
988 else if (!valid_dreg_pair (&$9, $11))
989 return yyerror ("Bad dreg pair");
992 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
993 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
996 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
999 return yyerror ("Dregs expected");
1000 else if (!valid_dreg_pair (&$5, $7))
1001 return yyerror ("Bad dreg pair");
1002 else if (!valid_dreg_pair (&$9, $11))
1003 return yyerror ("Bad dreg pair");
1006 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1007 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1011 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1015 return yyerror ("Dregs expected");
1016 else if (!valid_dreg_pair (&$5, $7))
1017 return yyerror ("Bad dreg pair");
1018 else if (!valid_dreg_pair (&$9, $11))
1019 return yyerror ("Bad dreg pair");
1022 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1023 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1027 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1031 return yyerror ("Dregs expected");
1032 else if (!valid_dreg_pair (&$5, $7))
1033 return yyerror ("Bad dreg pair");
1034 else if (!valid_dreg_pair (&$9, $11))
1035 return yyerror ("Bad dreg pair");
1038 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1039 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
1043 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1047 return yyerror ("Dregs expected");
1048 else if (!valid_dreg_pair (&$5, $7))
1049 return yyerror ("Bad dreg pair");
1050 else if (!valid_dreg_pair (&$9, $11))
1051 return yyerror ("Bad dreg pair");
1054 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1055 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1059 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1061 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1063 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1064 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1067 return yyerror ("Dregs expected");
1070 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1071 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1073 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1075 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1076 "SIGN (dregs_hi) * dregs_hi + "
1077 "SIGN (dregs_lo) * dregs_lo \n");
1079 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1082 return yyerror ("Dregs expected");
1084 | REG ASSIGN REG plus_minus REG amod1
1086 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1090 /* No saturation flag specified, generate the 16 bit variant. */
1091 notethat ("COMP3op: dregs = dregs +- dregs\n");
1092 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1096 /* Saturation flag specified, generate the 32 bit variant. */
1097 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1098 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1102 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1104 notethat ("COMP3op: pregs = pregs + pregs\n");
1105 $$ = COMP3OP (&$1, &$3, &$5, 5);
1108 return yyerror ("Dregs expected");
1110 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1114 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1121 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1122 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1125 return yyerror ("Dregs expected");
1128 | a_assign MINUS REG_A
1130 notethat ("dsp32alu: Ax = - Ax\n");
1131 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1133 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1135 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1136 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1137 $6.s0, $6.x0, HL2 ($3, $5));
1139 | a_assign a_assign expr
1141 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1143 notethat ("dsp32alu: A1 = A0 = 0\n");
1144 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1147 return yyerror ("Bad value, 0 expected");
1151 | a_assign REG_A LPAREN S RPAREN
1153 if (REG_SAME ($1, $2))
1155 notethat ("dsp32alu: Ax = Ax (S)\n");
1156 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1159 return yyerror ("Registers must be equal");
1162 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1166 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1167 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1170 return yyerror ("Dregs expected");
1173 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1175 if (IS_DREG ($3) && IS_DREG ($5))
1177 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1178 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1181 return yyerror ("Dregs expected");
1184 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1186 if (IS_DREG ($3) && IS_DREG ($5))
1188 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1189 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1192 return yyerror ("Dregs expected");
1197 if (!REG_SAME ($1, $2))
1199 notethat ("dsp32alu: An = Am\n");
1200 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1203 return yyerror ("Accu reg arguments must differ");
1210 notethat ("dsp32alu: An = dregs\n");
1211 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1214 return yyerror ("Dregs expected");
1217 | REG ASSIGN HALF_REG xpmod
1221 if ($1.regno == REG_A0x && IS_DREG ($3))
1223 notethat ("dsp32alu: A0.x = dregs_lo\n");
1224 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1226 else if ($1.regno == REG_A1x && IS_DREG ($3))
1228 notethat ("dsp32alu: A1.x = dregs_lo\n");
1229 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1231 else if (IS_DREG ($1) && IS_DREG ($3))
1233 notethat ("ALU2op: dregs = dregs_lo\n");
1234 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1237 return yyerror ("Register mismatch");
1240 return yyerror ("Low reg expected");
1243 | HALF_REG ASSIGN expr
1245 notethat ("LDIMMhalf: pregs_half = imm16\n");
1247 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1248 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1249 return yyerror ("Wrong register for load immediate");
1251 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1252 return yyerror ("Constant out of range");
1254 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1259 notethat ("dsp32alu: An = 0\n");
1262 return yyerror ("0 expected");
1264 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1267 | REG ASSIGN expr xpmod1
1269 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1270 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1271 return yyerror ("Wrong register for load immediate");
1275 /* 7 bit immediate value if possible.
1276 We will check for that constant value for efficiency
1277 If it goes to reloc, it will be 16 bit. */
1278 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1280 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1281 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1283 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1285 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1286 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1290 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1291 return yyerror ("Immediate value out of range");
1293 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1295 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1300 /* (z) There is no 7 bit zero extended instruction.
1301 If the expr is a relocation, generate it. */
1303 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1304 return yyerror ("Immediate value out of range");
1306 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1308 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1312 | HALF_REG ASSIGN REG
1315 return yyerror ("Low reg expected");
1317 if (IS_DREG ($1) && $3.regno == REG_A0x)
1319 notethat ("dsp32alu: dregs_lo = A0.x\n");
1320 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1322 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1324 notethat ("dsp32alu: dregs_lo = A1.x\n");
1325 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1328 return yyerror ("Register mismatch");
1331 | REG ASSIGN REG op_bar_op REG amod0
1333 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1335 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1336 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1339 return yyerror ("Register mismatch");
1342 | REG ASSIGN BYTE_DREG xpmod
1344 if (IS_DREG ($1) && IS_DREG ($3))
1346 notethat ("ALU2op: dregs = dregs_byte\n");
1347 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1350 return yyerror ("Register mismatch");
1353 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1355 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1357 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1358 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1361 return yyerror ("Register mismatch");
1364 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1366 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1368 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1369 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1372 return yyerror ("Register mismatch");
1375 | a_minusassign REG_A w32_or_nothing
1377 if (!IS_A1 ($1) && IS_A1 ($2))
1379 notethat ("dsp32alu: A0 -= A1\n");
1380 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1383 return yyerror ("Register mismatch");
1386 | REG _MINUS_ASSIGN expr
1388 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1390 notethat ("dagMODik: iregs -= 4\n");
1391 $$ = DAGMODIK (&$1, 3);
1393 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1395 notethat ("dagMODik: iregs -= 2\n");
1396 $$ = DAGMODIK (&$1, 1);
1399 return yyerror ("Register or value mismatch");
1402 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1404 if (IS_IREG ($1) && IS_MREG ($3))
1406 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1408 $$ = DAGMODIM (&$1, &$3, 0, 1);
1410 else if (IS_PREG ($1) && IS_PREG ($3))
1412 notethat ("PTR2op: pregs += pregs (BREV )\n");
1413 $$ = PTR2OP (&$1, &$3, 5);
1416 return yyerror ("Register mismatch");
1419 | REG _MINUS_ASSIGN REG
1421 if (IS_IREG ($1) && IS_MREG ($3))
1423 notethat ("dagMODim: iregs -= mregs\n");
1424 $$ = DAGMODIM (&$1, &$3, 1, 0);
1426 else if (IS_PREG ($1) && IS_PREG ($3))
1428 notethat ("PTR2op: pregs -= pregs\n");
1429 $$ = PTR2OP (&$1, &$3, 0);
1432 return yyerror ("Register mismatch");
1435 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1437 if (!IS_A1 ($1) && IS_A1 ($3))
1439 notethat ("dsp32alu: A0 += A1 (W32)\n");
1440 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1443 return yyerror ("Register mismatch");
1446 | REG _PLUS_ASSIGN REG
1448 if (IS_IREG ($1) && IS_MREG ($3))
1450 notethat ("dagMODim: iregs += mregs\n");
1451 $$ = DAGMODIM (&$1, &$3, 0, 0);
1454 return yyerror ("iregs += mregs expected");
1457 | REG _PLUS_ASSIGN expr
1461 if (EXPR_VALUE ($3) == 4)
1463 notethat ("dagMODik: iregs += 4\n");
1464 $$ = DAGMODIK (&$1, 2);
1466 else if (EXPR_VALUE ($3) == 2)
1468 notethat ("dagMODik: iregs += 2\n");
1469 $$ = DAGMODIK (&$1, 0);
1472 return yyerror ("iregs += [ 2 | 4 ");
1474 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1476 notethat ("COMPI2opP: pregs += imm7\n");
1477 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1479 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1481 notethat ("COMPI2opD: dregs += imm7\n");
1482 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1484 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1485 return yyerror ("Immediate value out of range");
1487 return yyerror ("Register mismatch");
1490 | REG _STAR_ASSIGN REG
1492 if (IS_DREG ($1) && IS_DREG ($3))
1494 notethat ("ALU2op: dregs *= dregs\n");
1495 $$ = ALU2OP (&$1, &$3, 3);
1498 return yyerror ("Register mismatch");
1501 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1503 if (!valid_dreg_pair (&$3, $5))
1504 return yyerror ("Bad dreg pair");
1505 else if (!valid_dreg_pair (&$7, $9))
1506 return yyerror ("Bad dreg pair");
1509 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1510 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1514 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1516 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1518 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1519 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1522 return yyerror ("Register mismatch");
1525 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1527 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1528 && REG_SAME ($1, $4))
1530 if (EXPR_VALUE ($9) == 1)
1532 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1533 $$ = ALU2OP (&$1, &$6, 4);
1535 else if (EXPR_VALUE ($9) == 2)
1537 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1538 $$ = ALU2OP (&$1, &$6, 5);
1541 return yyerror ("Bad shift value");
1543 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1544 && REG_SAME ($1, $4))
1546 if (EXPR_VALUE ($9) == 1)
1548 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1549 $$ = PTR2OP (&$1, &$6, 6);
1551 else if (EXPR_VALUE ($9) == 2)
1553 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1554 $$ = PTR2OP (&$1, &$6, 7);
1557 return yyerror ("Bad shift value");
1560 return yyerror ("Register mismatch");
1564 | REG ASSIGN REG BAR REG
1566 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1568 notethat ("COMP3op: dregs = dregs | dregs\n");
1569 $$ = COMP3OP (&$1, &$3, &$5, 3);
1572 return yyerror ("Dregs expected");
1574 | REG ASSIGN REG CARET REG
1576 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1578 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1579 $$ = COMP3OP (&$1, &$3, &$5, 4);
1582 return yyerror ("Dregs expected");
1584 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1586 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1588 if (EXPR_VALUE ($8) == 1)
1590 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1591 $$ = COMP3OP (&$1, &$3, &$6, 6);
1593 else if (EXPR_VALUE ($8) == 2)
1595 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1596 $$ = COMP3OP (&$1, &$3, &$6, 7);
1599 return yyerror ("Bad shift value");
1602 return yyerror ("Dregs expected");
1604 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1606 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1608 notethat ("CCflag: CC = A0 == A1\n");
1609 $$ = CCFLAG (0, 0, 5, 0, 0);
1612 return yyerror ("AREGs are in bad order or same");
1614 | CCREG ASSIGN REG_A LESS_THAN REG_A
1616 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1618 notethat ("CCflag: CC = A0 < A1\n");
1619 $$ = CCFLAG (0, 0, 6, 0, 0);
1622 return yyerror ("AREGs are in bad order or same");
1624 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1626 if (REG_CLASS($3) == REG_CLASS($5))
1628 notethat ("CCflag: CC = dpregs < dpregs\n");
1629 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1632 return yyerror ("Compare only of same register class");
1634 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1636 if (($6.r0 == 1 && IS_IMM ($5, 3))
1637 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1639 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1640 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1643 return yyerror ("Bad constant value");
1645 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1647 if (REG_CLASS($3) == REG_CLASS($5))
1649 notethat ("CCflag: CC = dpregs == dpregs\n");
1650 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1653 return yyerror ("Compare only of same register class");
1655 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1659 notethat ("CCflag: CC = dpregs == imm3\n");
1660 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1663 return yyerror ("Bad constant range");
1665 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1667 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1669 notethat ("CCflag: CC = A0 <= A1\n");
1670 $$ = CCFLAG (0, 0, 7, 0, 0);
1673 return yyerror ("AREGs are in bad order or same");
1675 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1677 if (REG_CLASS($3) == REG_CLASS($5))
1679 notethat ("CCflag: CC = pregs <= pregs (..)\n");
1680 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1681 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1684 return yyerror ("Compare only of same register class");
1686 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1688 if (($6.r0 == 1 && IS_IMM ($5, 3))
1689 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1693 notethat ("CCflag: CC = dregs <= (u)imm3\n");
1695 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 0);
1697 else if (IS_PREG ($3))
1699 notethat ("CCflag: CC = pregs <= (u)imm3\n");
1701 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 1);
1704 return yyerror ("Dreg or Preg expected");
1707 return yyerror ("Bad constant value");
1710 | REG ASSIGN REG AMPERSAND REG
1712 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1714 notethat ("COMP3op: dregs = dregs & dregs\n");
1715 $$ = COMP3OP (&$1, &$3, &$5, 2);
1718 return yyerror ("Dregs expected");
1723 notethat ("CC2stat operation\n");
1724 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1729 if (IS_ALLREG ($1) && IS_ALLREG ($3))
1731 notethat ("REGMV: allregs = allregs\n");
1732 $$ = bfin_gen_regmv (&$3, &$1);
1735 return yyerror ("Register mismatch");
1742 notethat ("CC2dreg: CC = dregs\n");
1743 $$ = bfin_gen_cc2dreg (1, &$3);
1746 return yyerror ("Register mismatch");
1753 notethat ("CC2dreg: dregs = CC\n");
1754 $$ = bfin_gen_cc2dreg (0, &$1);
1757 return yyerror ("Register mismatch");
1760 | CCREG _ASSIGN_BANG CCREG
1762 notethat ("CC2dreg: CC =! CC\n");
1763 $$ = bfin_gen_cc2dreg (3, 0);
1768 | HALF_REG ASSIGN multiply_halfregs opt_mode
1770 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1772 if (!IS_H ($1) && $4.MM)
1773 return yyerror ("(M) not allowed with MAC0");
1775 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1776 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1777 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1778 return yyerror ("bad option.");
1782 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1783 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1784 &$1, 0, &$3.s0, &$3.s1, 0);
1788 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1789 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1790 &$1, 0, &$3.s0, &$3.s1, 1);
1794 | REG ASSIGN multiply_halfregs opt_mode
1796 /* Odd registers can use (M). */
1798 return yyerror ("Dreg expected");
1800 if (IS_EVEN ($1) && $4.MM)
1801 return yyerror ("(M) not allowed with MAC0");
1803 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1804 && $4.mod != M_S2RND && $4.mod != M_ISS2)
1805 return yyerror ("bad option");
1809 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1811 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1812 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1813 &$1, 0, &$3.s0, &$3.s1, 0);
1817 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1818 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1819 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1820 &$1, 0, &$3.s0, &$3.s1, 1);
1824 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1825 HALF_REG ASSIGN multiply_halfregs opt_mode
1827 if (!IS_DREG ($1) || !IS_DREG ($6))
1828 return yyerror ("Dregs expected");
1830 if (!IS_HCOMPL($1, $6))
1831 return yyerror ("Dest registers mismatch");
1833 if (check_multiply_halfregs (&$3, &$8) < 0)
1836 if ((!IS_H ($1) && $4.MM)
1837 || (!IS_H ($6) && $9.MM))
1838 return yyerror ("(M) not allowed with MAC0");
1840 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1841 "dregs_lo = multiply_halfregs opt_mode\n");
1844 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1845 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1846 &$1, 0, &$3.s0, &$3.s1, 1);
1848 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1849 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1850 &$1, 0, &$3.s0, &$3.s1, 1);
1853 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1855 if (!IS_DREG ($1) || !IS_DREG ($6))
1856 return yyerror ("Dregs expected");
1858 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1859 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1860 return yyerror ("Dest registers mismatch");
1862 if (check_multiply_halfregs (&$3, &$8) < 0)
1865 if ((IS_EVEN ($1) && $4.MM)
1866 || (IS_EVEN ($6) && $9.MM))
1867 return yyerror ("(M) not allowed with MAC0");
1869 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1870 "dregs = multiply_halfregs opt_mode\n");
1873 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1874 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1875 &$1, 0, &$3.s0, &$3.s1, 1);
1877 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1878 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1879 &$1, 0, &$3.s0, &$3.s1, 1);
1884 | a_assign ASHIFT REG_A BY HALF_REG
1886 if (!REG_SAME ($1, $3))
1887 return yyerror ("Aregs must be same");
1889 if (IS_DREG ($5) && !IS_H ($5))
1891 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1892 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1895 return yyerror ("Dregs expected");
1898 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1900 if (IS_DREG ($6) && !IS_H ($6))
1902 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1903 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1906 return yyerror ("Dregs expected");
1909 | a_assign REG_A LESS_LESS expr
1911 if (!REG_SAME ($1, $2))
1912 return yyerror ("Aregs must be same");
1914 if (IS_UIMM ($4, 5))
1916 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1917 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1920 return yyerror ("Bad shift value");
1923 | REG ASSIGN REG LESS_LESS expr vsmod
1925 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1930 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1931 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1935 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1936 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1939 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1941 if (EXPR_VALUE ($5) == 2)
1943 notethat ("PTR2op: pregs = pregs << 2\n");
1944 $$ = PTR2OP (&$1, &$3, 1);
1946 else if (EXPR_VALUE ($5) == 1)
1948 notethat ("COMP3op: pregs = pregs << 1\n");
1949 $$ = COMP3OP (&$1, &$3, &$3, 5);
1952 return yyerror ("Bad shift value");
1955 return yyerror ("Bad shift value or register");
1957 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1959 if (IS_UIMM ($5, 4))
1963 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
1964 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1968 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1969 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1973 return yyerror ("Bad shift value");
1975 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1979 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1984 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1985 "dregs_lo (V, .)\n");
1991 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1993 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1996 return yyerror ("Dregs expected");
2000 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2002 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2004 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2005 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2008 return yyerror ("Bad shift value or register");
2012 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2014 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2016 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2017 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2019 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2021 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2022 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2025 return yyerror ("Bad shift value or register");
2030 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2032 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2034 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2035 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2038 return yyerror ("Register mismatch");
2041 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2043 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2045 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2046 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2049 return yyerror ("Register mismatch");
2052 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2054 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2056 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2057 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2060 return yyerror ("Register mismatch");
2063 | a_assign REG_A _GREATER_GREATER_GREATER expr
2065 if (!REG_SAME ($1, $2))
2066 return yyerror ("Aregs must be same");
2068 if (IS_UIMM ($4, 5))
2070 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2071 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2074 return yyerror ("Shift value range error");
2076 | a_assign LSHIFT REG_A BY HALF_REG
2078 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2080 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2081 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2084 return yyerror ("Register mismatch");
2087 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2089 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2091 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2092 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2095 return yyerror ("Register mismatch");
2098 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2100 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2102 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2103 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2106 return yyerror ("Register mismatch");
2109 | REG ASSIGN SHIFT REG BY HALF_REG
2111 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2113 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2114 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2117 return yyerror ("Register mismatch");
2120 | a_assign REG_A GREATER_GREATER expr
2122 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2124 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2125 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2128 return yyerror ("Accu register expected");
2131 | REG ASSIGN REG GREATER_GREATER expr vmod
2135 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2137 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2138 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2141 return yyerror ("Register mismatch");
2145 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2147 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2148 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2150 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2152 notethat ("PTR2op: pregs = pregs >> 2\n");
2153 $$ = PTR2OP (&$1, &$3, 3);
2155 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2157 notethat ("PTR2op: pregs = pregs >> 1\n");
2158 $$ = PTR2OP (&$1, &$3, 4);
2161 return yyerror ("Register mismatch");
2164 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2166 if (IS_UIMM ($5, 5))
2168 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2169 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2172 return yyerror ("Register mismatch");
2174 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2176 if (IS_UIMM ($5, 5))
2178 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2179 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2180 $6.s0, HL2 ($1, $3));
2183 return yyerror ("Register or modifier mismatch");
2187 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2189 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2194 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2195 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2199 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2200 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2204 return yyerror ("Register mismatch");
2207 | HALF_REG ASSIGN ONES REG
2209 if (IS_DREG_L ($1) && IS_DREG ($4))
2211 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2212 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2215 return yyerror ("Register mismatch");
2218 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2220 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2222 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2223 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2226 return yyerror ("Register mismatch");
2229 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2232 && $7.regno == REG_A0
2233 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2235 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2236 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2239 return yyerror ("Register mismatch");
2242 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2245 && $7.regno == REG_A0
2246 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2248 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2249 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2252 return yyerror ("Register mismatch");
2255 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2257 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2259 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2260 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2263 return yyerror ("Register mismatch");
2266 | a_assign ROT REG_A BY HALF_REG
2268 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2270 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2271 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2274 return yyerror ("Register mismatch");
2277 | REG ASSIGN ROT REG BY HALF_REG
2279 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2281 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2282 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2285 return yyerror ("Register mismatch");
2288 | a_assign ROT REG_A BY expr
2292 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2293 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2296 return yyerror ("Register mismatch");
2299 | REG ASSIGN ROT REG BY expr
2301 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2303 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2306 return yyerror ("Register mismatch");
2309 | HALF_REG ASSIGN SIGNBITS REG_A
2313 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2314 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2317 return yyerror ("Register mismatch");
2320 | HALF_REG ASSIGN SIGNBITS REG
2322 if (IS_DREG_L ($1) && IS_DREG ($4))
2324 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2325 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2328 return yyerror ("Register mismatch");
2331 | HALF_REG ASSIGN SIGNBITS HALF_REG
2335 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2336 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2339 return yyerror ("Register mismatch");
2342 /* The ASR bit is just inverted here. */
2343 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2345 if (IS_DREG_L ($1) && IS_DREG ($5))
2347 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2348 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2351 return yyerror ("Register mismatch");
2354 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2356 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2358 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2359 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2362 return yyerror ("Register mismatch");
2365 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2367 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2369 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2370 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2373 return yyerror ("Register mismatch");
2376 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2378 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2380 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2381 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2384 return yyerror ("Dregs expected");
2388 /* LOGI2op: BITCLR (dregs, uimm5). */
2389 | BITCLR LPAREN REG COMMA expr RPAREN
2391 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2393 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2394 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2397 return yyerror ("Register mismatch");
2400 /* LOGI2op: BITSET (dregs, uimm5). */
2401 | BITSET LPAREN REG COMMA expr RPAREN
2403 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2405 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2406 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2409 return yyerror ("Register mismatch");
2412 /* LOGI2op: BITTGL (dregs, uimm5). */
2413 | BITTGL LPAREN REG COMMA expr RPAREN
2415 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2417 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2418 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2421 return yyerror ("Register mismatch");
2424 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2426 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2428 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2429 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2432 return yyerror ("Register mismatch or value error");
2435 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2437 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2439 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2440 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2443 return yyerror ("Register mismatch or value error");
2446 | IF BANG CCREG REG ASSIGN REG
2448 if ((IS_DREG ($4) || IS_PREG ($4))
2449 && (IS_DREG ($6) || IS_PREG ($6)))
2451 notethat ("ccMV: IF ! CC gregs = gregs\n");
2452 $$ = CCMV (&$6, &$4, 0);
2455 return yyerror ("Register mismatch");
2458 | IF CCREG REG ASSIGN REG
2460 if ((IS_DREG ($5) || IS_PREG ($5))
2461 && (IS_DREG ($3) || IS_PREG ($3)))
2463 notethat ("ccMV: IF CC gregs = gregs\n");
2464 $$ = CCMV (&$5, &$3, 1);
2467 return yyerror ("Register mismatch");
2470 | IF BANG CCREG JUMP expr
2472 if (IS_PCREL10 ($5))
2474 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2475 $$ = BRCC (0, 0, $5);
2478 return yyerror ("Bad jump offset");
2481 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2483 if (IS_PCREL10 ($5))
2485 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2486 $$ = BRCC (0, 1, $5);
2489 return yyerror ("Bad jump offset");
2492 | IF CCREG JUMP expr
2494 if (IS_PCREL10 ($4))
2496 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2497 $$ = BRCC (1, 0, $4);
2500 return yyerror ("Bad jump offset");
2503 | IF CCREG JUMP expr LPAREN BP RPAREN
2505 if (IS_PCREL10 ($4))
2507 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2508 $$ = BRCC (1, 1, $4);
2511 return yyerror ("Bad jump offset");
2515 notethat ("ProgCtrl: NOP\n");
2516 $$ = PROGCTRL (0, 0);
2521 notethat ("ProgCtrl: RTS\n");
2522 $$ = PROGCTRL (1, 0);
2527 notethat ("ProgCtrl: RTI\n");
2528 $$ = PROGCTRL (1, 1);
2533 notethat ("ProgCtrl: RTX\n");
2534 $$ = PROGCTRL (1, 2);
2539 notethat ("ProgCtrl: RTN\n");
2540 $$ = PROGCTRL (1, 3);
2545 notethat ("ProgCtrl: RTE\n");
2546 $$ = PROGCTRL (1, 4);
2551 notethat ("ProgCtrl: IDLE\n");
2552 $$ = PROGCTRL (2, 0);
2557 notethat ("ProgCtrl: CSYNC\n");
2558 $$ = PROGCTRL (2, 3);
2563 notethat ("ProgCtrl: SSYNC\n");
2564 $$ = PROGCTRL (2, 4);
2569 notethat ("ProgCtrl: EMUEXCPT\n");
2570 $$ = PROGCTRL (2, 5);
2577 notethat ("ProgCtrl: CLI dregs\n");
2578 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2581 return yyerror ("Dreg expected for CLI");
2588 notethat ("ProgCtrl: STI dregs\n");
2589 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2592 return yyerror ("Dreg expected for STI");
2595 | JUMP LPAREN REG RPAREN
2599 notethat ("ProgCtrl: JUMP (pregs )\n");
2600 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2603 return yyerror ("Bad register for indirect jump");
2606 | CALL LPAREN REG RPAREN
2610 notethat ("ProgCtrl: CALL (pregs )\n");
2611 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2614 return yyerror ("Bad register for indirect call");
2617 | CALL LPAREN PC PLUS REG RPAREN
2621 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2622 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2625 return yyerror ("Bad register for indirect call");
2628 | JUMP LPAREN PC PLUS REG RPAREN
2632 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2633 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2636 return yyerror ("Bad register for indirect jump");
2641 if (IS_UIMM ($2, 4))
2643 notethat ("ProgCtrl: RAISE uimm4\n");
2644 $$ = PROGCTRL (9, uimm4 ($2));
2647 return yyerror ("Bad value for RAISE");
2652 notethat ("ProgCtrl: EMUEXCPT\n");
2653 $$ = PROGCTRL (10, uimm4 ($2));
2656 | TESTSET LPAREN REG RPAREN
2660 notethat ("ProgCtrl: TESTSET (pregs )\n");
2661 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2664 return yyerror ("Preg expected");
2669 if (IS_PCREL12 ($2))
2671 notethat ("UJUMP: JUMP pcrel12\n");
2675 return yyerror ("Bad value for relative jump");
2680 if (IS_PCREL12 ($2))
2682 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2686 return yyerror ("Bad value for relative jump");
2691 if (IS_PCREL24 ($2))
2693 notethat ("CALLa: jump.l pcrel24\n");
2697 return yyerror ("Bad value for long jump");
2702 if (IS_PCREL24 ($2))
2704 notethat ("CALLa: jump.l pcrel24\n");
2708 return yyerror ("Bad value for long jump");
2713 if (IS_PCREL24 ($2))
2715 notethat ("CALLa: CALL pcrel25m2\n");
2719 return yyerror ("Bad call address");
2723 if (IS_PCREL24 ($2))
2725 notethat ("CALLa: CALL pcrel25m2\n");
2729 return yyerror ("Bad call address");
2733 /* ALU2op: DIVQ (dregs, dregs). */
2734 | DIVQ LPAREN REG COMMA REG RPAREN
2736 if (IS_DREG ($3) && IS_DREG ($5))
2737 $$ = ALU2OP (&$3, &$5, 8);
2739 return yyerror ("Bad registers for DIVQ");
2742 | DIVS LPAREN REG COMMA REG RPAREN
2744 if (IS_DREG ($3) && IS_DREG ($5))
2745 $$ = ALU2OP (&$3, &$5, 9);
2747 return yyerror ("Bad registers for DIVS");
2750 | REG ASSIGN MINUS REG vsmod
2752 if (IS_DREG ($1) && IS_DREG ($4))
2754 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2756 notethat ("ALU2op: dregs = - dregs\n");
2757 $$ = ALU2OP (&$1, &$4, 14);
2759 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2761 notethat ("dsp32alu: dregs = - dregs (.)\n");
2762 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2766 notethat ("dsp32alu: dregs = - dregs (.)\n");
2767 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2771 return yyerror ("Dregs expected");
2774 | REG ASSIGN TILDA REG
2776 if (IS_DREG ($1) && IS_DREG ($4))
2778 notethat ("ALU2op: dregs = ~dregs\n");
2779 $$ = ALU2OP (&$1, &$4, 15);
2782 return yyerror ("Dregs expected");
2785 | REG _GREATER_GREATER_ASSIGN REG
2787 if (IS_DREG ($1) && IS_DREG ($3))
2789 notethat ("ALU2op: dregs >>= dregs\n");
2790 $$ = ALU2OP (&$1, &$3, 1);
2793 return yyerror ("Dregs expected");
2796 | REG _GREATER_GREATER_ASSIGN expr
2798 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2800 notethat ("LOGI2op: dregs >>= uimm5\n");
2801 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2804 return yyerror ("Dregs expected or value error");
2807 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2809 if (IS_DREG ($1) && IS_DREG ($3))
2811 notethat ("ALU2op: dregs >>>= dregs\n");
2812 $$ = ALU2OP (&$1, &$3, 0);
2815 return yyerror ("Dregs expected");
2818 | REG _LESS_LESS_ASSIGN REG
2820 if (IS_DREG ($1) && IS_DREG ($3))
2822 notethat ("ALU2op: dregs <<= dregs\n");
2823 $$ = ALU2OP (&$1, &$3, 2);
2826 return yyerror ("Dregs expected");
2829 | REG _LESS_LESS_ASSIGN expr
2831 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2833 notethat ("LOGI2op: dregs <<= uimm5\n");
2834 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2837 return yyerror ("Dregs expected or const value error");
2841 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2843 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2845 notethat ("LOGI2op: dregs >>>= uimm5\n");
2846 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2849 return yyerror ("Dregs expected");
2852 /* Cache Control. */
2854 | FLUSH LBRACK REG RBRACK
2856 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2858 $$ = CACTRL (&$3, 0, 2);
2860 return yyerror ("Bad register(s) for FLUSH");
2863 | FLUSH reg_with_postinc
2867 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2868 $$ = CACTRL (&$2, 1, 2);
2871 return yyerror ("Bad register(s) for FLUSH");
2874 | FLUSHINV LBRACK REG RBRACK
2878 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2879 $$ = CACTRL (&$3, 0, 1);
2882 return yyerror ("Bad register(s) for FLUSH");
2885 | FLUSHINV reg_with_postinc
2889 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2890 $$ = CACTRL (&$2, 1, 1);
2893 return yyerror ("Bad register(s) for FLUSH");
2896 /* CaCTRL: IFLUSH [pregs]. */
2897 | IFLUSH LBRACK REG RBRACK
2901 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2902 $$ = CACTRL (&$3, 0, 3);
2905 return yyerror ("Bad register(s) for FLUSH");
2908 | IFLUSH reg_with_postinc
2912 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2913 $$ = CACTRL (&$2, 1, 3);
2916 return yyerror ("Bad register(s) for FLUSH");
2919 | PREFETCH LBRACK REG RBRACK
2923 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2924 $$ = CACTRL (&$3, 0, 0);
2927 return yyerror ("Bad register(s) for PREFETCH");
2930 | PREFETCH reg_with_postinc
2934 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2935 $$ = CACTRL (&$2, 1, 0);
2938 return yyerror ("Bad register(s) for PREFETCH");
2942 /* LDST: B [ pregs <post_op> ] = dregs. */
2944 | B LBRACK REG post_op RBRACK ASSIGN REG
2946 if (IS_PREG ($3) && IS_DREG ($7))
2948 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2949 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2952 return yyerror ("Register mismatch");
2955 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2956 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2958 if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 1) && IS_DREG ($8))
2960 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2963 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2966 return yyerror ("Register mismatch or const size wrong");
2970 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
2971 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2973 if (IS_PREG ($3) && IS_URANGE (4, $5, $4.r0, 2) && IS_DREG ($8))
2975 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
2976 $$ = LDSTII (&$3, &$8, $5, 1, 1);
2978 else if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 2) && IS_DREG ($8))
2980 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
2983 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, $5);
2986 return yyerror ("Bad register(s) or wrong constant size");
2989 /* LDST: W [ pregs <post_op> ] = dregs. */
2990 | W LBRACK REG post_op RBRACK ASSIGN REG
2992 if (IS_PREG ($3) && IS_DREG ($7))
2994 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
2995 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
2998 return yyerror ("Bad register(s) for STORE");
3001 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3005 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3006 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3008 else if ($4.x0 == 2 && IS_PREG ($3) && IS_DREG ($7))
3010 notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
3011 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3015 return yyerror ("Bad register(s) for STORE");
3018 /* LDSTiiFP: [ FP - const ] = dpregs. */
3019 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3021 Expr_Node *tmp = $4;
3022 int ispreg = IS_PREG ($7);
3025 return yyerror ("Preg expected for indirect");
3027 if (!IS_DREG ($7) && !ispreg)
3028 return yyerror ("Bad source register for STORE");
3031 tmp = unary (Expr_Op_Type_NEG, tmp);
3033 if (in_range_p (tmp, 0, 63, 3))
3035 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3036 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3038 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3040 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3041 tmp = unary (Expr_Op_Type_NEG, tmp);
3042 $$ = LDSTIIFP (tmp, &$7, 1);
3044 else if (in_range_p (tmp, -131072, 131071, 3))
3046 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3047 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1: 0, tmp);
3050 return yyerror ("Displacement out of range for store");
3053 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3055 if (IS_DREG ($1) && IS_PREG ($5) && IS_URANGE (4, $7, $6.r0, 2))
3057 notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
3058 $$ = LDSTII (&$5, &$1, $7, 0, 1 << $9.r0);
3060 else if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 2))
3062 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3065 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, $7);
3068 return yyerror ("Bad register or constant for LOAD");
3071 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3075 notethat ("dspLDST: dregs_half = W [ iregs ]\n");
3076 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3078 else if ($6.x0 == 2 && IS_DREG ($1) && IS_PREG ($5))
3080 notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
3081 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3084 return yyerror ("Bad register or post_op for LOAD");
3088 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3090 if (IS_DREG ($1) && IS_PREG ($5))
3092 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3093 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3096 return yyerror ("Bad register for LOAD");
3099 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3101 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3103 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3104 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3107 return yyerror ("Bad register for LOAD");
3110 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3112 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3114 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3115 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3118 return yyerror ("Bad register for LOAD");
3121 | LBRACK REG post_op RBRACK ASSIGN REG
3123 if (IS_IREG ($2) && IS_DREG ($6))
3125 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3126 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3128 else if (IS_PREG ($2) && IS_DREG ($6))
3130 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3131 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3133 else if (IS_PREG ($2) && IS_PREG ($6))
3135 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3136 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3139 return yyerror ("Bad register for STORE");
3142 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3145 return yyerror ("Expected Dreg for last argument");
3147 if (IS_IREG ($2) && IS_MREG ($4))
3149 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3150 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3152 else if (IS_PREG ($2) && IS_PREG ($4))
3154 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3155 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3158 return yyerror ("Bad register for STORE");
3161 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3164 return yyerror ("Expect Dreg as last argument");
3165 if (IS_PREG ($3) && IS_PREG ($5))
3167 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3168 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3171 return yyerror ("Bad register for STORE");
3174 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3176 if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 1))
3178 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3182 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, $7);
3185 return yyerror ("Bad register or value for LOAD");
3188 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3190 if (IS_DREG ($1) && IS_PREG ($5))
3192 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3194 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3197 return yyerror ("Bad register for LOAD");
3200 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3202 if (IS_DREG ($1) && IS_IREG ($4) && IS_MREG ($6))
3204 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3205 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3207 else if (IS_DREG ($1) && IS_PREG ($4) && IS_PREG ($6))
3209 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3210 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3213 return yyerror ("Bad register for LOAD");
3216 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3218 Expr_Node *tmp = $6;
3219 int ispreg = IS_PREG ($1);
3220 int isgot = IS_RELOC($6);
3223 return yyerror ("Preg expected for indirect");
3225 if (!IS_DREG ($1) && !ispreg)
3226 return yyerror ("Bad destination register for LOAD");
3228 if (tmp->type == Expr_Node_Reloc
3229 && strcmp (tmp->value.s_value,
3230 "_current_shared_library_p5_offset_") != 0)
3231 return yyerror ("Plain symbol used as offset");
3234 tmp = unary (Expr_Op_Type_NEG, tmp);
3237 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3238 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3240 else if (in_range_p (tmp, 0, 63, 3))
3242 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3243 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3245 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3247 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3248 tmp = unary (Expr_Op_Type_NEG, tmp);
3249 $$ = LDSTIIFP (tmp, &$1, 0);
3251 else if (in_range_p (tmp, -131072, 131071, 3))
3253 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3254 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3258 return yyerror ("Displacement out of range for load");
3261 | REG ASSIGN LBRACK REG post_op RBRACK
3263 if (IS_DREG ($1) && IS_IREG ($4))
3265 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3266 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3268 else if (IS_DREG ($1) && IS_PREG ($4))
3270 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3271 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3273 else if (IS_PREG ($1) && IS_PREG ($4))
3275 if (REG_SAME ($1, $4) && $5.x0 != 2)
3276 return yyerror ("Pregs can't be same");
3278 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3279 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3281 else if ($4.regno == REG_SP && IS_ALLREG ($1) && $5.x0 == 0)
3283 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3284 $$ = PUSHPOPREG (&$1, 0);
3287 return yyerror ("Bad register or value");
3291 /* PushPopMultiple. */
3292 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3294 if ($1.regno != REG_SP)
3295 yyerror ("Stack Pointer expected");
3296 if ($4.regno == REG_R7
3297 && IN_RANGE ($6, 0, 7)
3298 && $8.regno == REG_P5
3299 && IN_RANGE ($10, 0, 5))
3301 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3302 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3305 return yyerror ("Bad register for PushPopMultiple");
3308 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3310 if ($1.regno != REG_SP)
3311 yyerror ("Stack Pointer expected");
3313 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3315 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3316 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3318 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3320 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3321 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3324 return yyerror ("Bad register for PushPopMultiple");
3327 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3329 if ($11.regno != REG_SP)
3330 yyerror ("Stack Pointer expected");
3331 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3332 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3334 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3335 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3338 return yyerror ("Bad register range for PushPopMultiple");
3341 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3343 if ($7.regno != REG_SP)
3344 yyerror ("Stack Pointer expected");
3346 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3348 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3349 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3351 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3353 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3354 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3357 return yyerror ("Bad register range for PushPopMultiple");
3360 | reg_with_predec ASSIGN REG
3362 if ($1.regno != REG_SP)
3363 yyerror ("Stack Pointer expected");
3367 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3368 $$ = PUSHPOPREG (&$3, 1);
3371 return yyerror ("Bad register for PushPopReg");
3378 if (IS_URANGE (16, $2, 0, 4))
3379 $$ = LINKAGE (0, uimm16s4 ($2));
3381 return yyerror ("Bad constant for LINK");
3386 notethat ("linkage: UNLINK\n");
3387 $$ = LINKAGE (1, 0);
3393 | LSETUP LPAREN expr COMMA expr RPAREN REG
3395 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3397 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3398 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3401 return yyerror ("Bad register or values for LSETUP");
3404 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3406 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3407 && IS_PREG ($9) && IS_CREG ($7))
3409 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3410 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3413 return yyerror ("Bad register or values for LSETUP");
3416 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3418 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3419 && IS_PREG ($9) && IS_CREG ($7)
3420 && EXPR_VALUE ($11) == 1)
3422 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3423 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3426 return yyerror ("Bad register or values for LSETUP");
3433 return yyerror ("Invalid expression in loop statement");
3435 return yyerror ("Invalid loop counter register");
3436 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3438 | LOOP expr REG ASSIGN REG
3440 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3442 notethat ("Loop: LOOP expr counters = pregs\n");
3443 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3446 return yyerror ("Bad register or values for LOOP");
3448 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3450 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3452 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3453 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3456 return yyerror ("Bad register or values for LOOP");
3462 notethat ("pseudoDEBUG: DBG\n");
3463 $$ = bfin_gen_pseudodbg (3, 7, 0);
3467 notethat ("pseudoDEBUG: DBG REG_A\n");
3468 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3472 notethat ("pseudoDEBUG: DBG allregs\n");
3473 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3476 | DBGCMPLX LPAREN REG RPAREN
3479 return yyerror ("Dregs expected");
3480 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3481 $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3486 notethat ("psedoDEBUG: DBGHALT\n");
3487 $$ = bfin_gen_pseudodbg (3, 5, 0);
3490 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3492 notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3493 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3496 | DBGAH LPAREN REG COMMA expr RPAREN
3498 notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3499 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3502 | DBGAL LPAREN REG COMMA expr RPAREN
3504 notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3505 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3513 /* Register rules. */
3515 REG_A: REG_A_DOUBLE_ZERO
3533 | LPAREN M COMMA MMOD RPAREN
3538 | LPAREN MMOD COMMA M RPAREN
3543 | LPAREN MMOD RPAREN
3555 asr_asl: LPAREN ASL RPAREN
3636 | LPAREN asr_asl_0 RPAREN
3648 | LPAREN asr_asl_0 COMMA sco RPAREN
3654 | LPAREN sco COMMA asr_asl_0 RPAREN
3714 | LPAREN V COMMA S RPAREN
3719 | LPAREN S COMMA V RPAREN
3781 | LPAREN MMOD RPAREN
3784 return yyerror ("Bad modifier");
3788 | LPAREN MMOD COMMA R RPAREN
3791 return yyerror ("Bad modifier");
3795 | LPAREN R COMMA MMOD RPAREN
3798 return yyerror ("Bad modifier");
3825 | LPAREN MMOD RPAREN
3830 return yyerror ("Only (W32) allowed");
3838 | LPAREN MMOD RPAREN
3843 return yyerror ("(IU) expected");
3847 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3853 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3905 $$.r0 = 1; /* HL. */
3908 $$.aop = 0; /* aop. */
3913 $$.r0 = 1; /* HL. */
3916 $$.aop = 1; /* aop. */
3919 | LPAREN RNDL RPAREN
3921 $$.r0 = 0; /* HL. */
3924 $$.aop = 0; /* aop. */
3929 $$.r0 = 0; /* HL. */
3935 | LPAREN RNDH COMMA R RPAREN
3937 $$.r0 = 1; /* HL. */
3940 $$.aop = 0; /* aop. */
3942 | LPAREN TH COMMA R RPAREN
3944 $$.r0 = 1; /* HL. */
3947 $$.aop = 1; /* aop. */
3949 | LPAREN RNDL COMMA R RPAREN
3951 $$.r0 = 0; /* HL. */
3954 $$.aop = 0; /* aop. */
3957 | LPAREN TL COMMA R RPAREN
3959 $$.r0 = 0; /* HL. */
3962 $$.aop = 1; /* aop. */
3970 $$.x0 = 0; /* HL. */
3975 $$.x0 = 1; /* HL. */
3977 | LPAREN LO COMMA R RPAREN
3980 $$.x0 = 0; /* HL. */
3982 | LPAREN HI COMMA R RPAREN
3985 $$.x0 = 1; /* HL. */
4003 /* Assignments, Macfuncs. */
4029 if (IS_A1 ($3) && IS_EVEN ($1))
4030 return yyerror ("Cannot move A1 to even register");
4031 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4032 return yyerror ("Cannot move A0 to odd register");
4048 | REG ASSIGN LPAREN a_macfunc RPAREN
4050 if ($4.n && IS_EVEN ($1))
4051 return yyerror ("Cannot move A1 to even register");
4052 else if (!$4.n && !IS_EVEN ($1))
4053 return yyerror ("Cannot move A0 to odd register");
4061 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4063 if ($4.n && !IS_H ($1))
4064 return yyerror ("Cannot move A1 to low half of register");
4065 else if (!$4.n && IS_H ($1))
4066 return yyerror ("Cannot move A0 to high half of register");
4074 | HALF_REG ASSIGN REG_A
4076 if (IS_A1 ($3) && !IS_H ($1))
4077 return yyerror ("Cannot move A1 to low half of register");
4078 else if (!IS_A1 ($3) && IS_H ($1))
4079 return yyerror ("Cannot move A0 to high half of register");
4092 a_assign multiply_halfregs
4099 | a_plusassign multiply_halfregs
4106 | a_minusassign multiply_halfregs
4116 HALF_REG STAR HALF_REG
4118 if (IS_DREG ($1) && IS_DREG ($3))
4124 return yyerror ("Dregs expected");
4148 CCREG cc_op STATUS_REG
4160 | STATUS_REG cc_op CCREG
4174 /* Expressions and Symbols. */
4178 Expr_Node_Value val;
4179 val.s_value = S_GET_NAME($1);
4180 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4186 { $$ = BFD_RELOC_BFIN_GOT; }
4188 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4190 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4193 got: symbol AT any_gotrel
4195 Expr_Node_Value val;
4197 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4220 Expr_Node_Value val;
4222 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4228 | LPAREN expr_1 RPAREN
4234 $$ = unary (Expr_Op_Type_COMP, $2);
4236 | MINUS expr_1 %prec TILDA
4238 $$ = unary (Expr_Op_Type_NEG, $2);
4248 expr_1: expr_1 STAR expr_1
4250 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4252 | expr_1 SLASH expr_1
4254 $$ = binary (Expr_Op_Type_Div, $1, $3);
4256 | expr_1 PERCENT expr_1
4258 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4260 | expr_1 PLUS expr_1
4262 $$ = binary (Expr_Op_Type_Add, $1, $3);
4264 | expr_1 MINUS expr_1
4266 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4268 | expr_1 LESS_LESS expr_1
4270 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4272 | expr_1 GREATER_GREATER expr_1
4274 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4276 | expr_1 AMPERSAND expr_1
4278 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4280 | expr_1 CARET expr_1
4282 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4286 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4298 mkexpr (int x, SYMBOL_T s)
4300 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4307 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4309 long umax = (1L << sz) - 1;
4310 long min = -1L << (sz - 1);
4311 long max = (1L << (sz - 1)) - 1;
4313 long v = EXPR_VALUE (expr);
4317 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4328 if (v >= min && v <= max) return 1;
4331 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4335 if (v <= umax && v >= 0)
4338 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4343 /* Return the expression structure that allows symbol operations.
4344 If the left and right children are constants, do the operation. */
4346 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4348 Expr_Node_Value val;
4350 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4354 case Expr_Op_Type_Add:
4355 x->value.i_value += y->value.i_value;
4357 case Expr_Op_Type_Sub:
4358 x->value.i_value -= y->value.i_value;
4360 case Expr_Op_Type_Mult:
4361 x->value.i_value *= y->value.i_value;
4363 case Expr_Op_Type_Div:
4364 if (y->value.i_value == 0)
4365 error ("Illegal Expression: Division by zero.");
4367 x->value.i_value /= y->value.i_value;
4369 case Expr_Op_Type_Mod:
4370 x->value.i_value %= y->value.i_value;
4372 case Expr_Op_Type_Lshift:
4373 x->value.i_value <<= y->value.i_value;
4375 case Expr_Op_Type_Rshift:
4376 x->value.i_value >>= y->value.i_value;
4378 case Expr_Op_Type_BAND:
4379 x->value.i_value &= y->value.i_value;
4381 case Expr_Op_Type_BOR:
4382 x->value.i_value |= y->value.i_value;
4384 case Expr_Op_Type_BXOR:
4385 x->value.i_value ^= y->value.i_value;
4387 case Expr_Op_Type_LAND:
4388 x->value.i_value = x->value.i_value && y->value.i_value;
4390 case Expr_Op_Type_LOR:
4391 x->value.i_value = x->value.i_value || y->value.i_value;
4395 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4399 /* Canonicalize order to EXPR OP CONSTANT. */
4400 if (x->type == Expr_Node_Constant)
4406 /* Canonicalize subtraction of const to addition of negated const. */
4407 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4409 op = Expr_Op_Type_Add;
4410 y->value.i_value = -y->value.i_value;
4412 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4413 && x->Right_Child->type == Expr_Node_Constant)
4415 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4417 x->Right_Child->value.i_value += y->value.i_value;
4422 /* Create a new expression structure. */
4424 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4428 unary (Expr_Op_Type op, Expr_Node *x)
4430 if (x->type == Expr_Node_Constant)
4434 case Expr_Op_Type_NEG:
4435 x->value.i_value = -x->value.i_value;
4437 case Expr_Op_Type_COMP:
4438 x->value.i_value = ~x->value.i_value;
4441 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4447 /* Create a new expression structure. */
4448 Expr_Node_Value val;
4450 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4454 int debug_codeselection = 0;
4456 notethat (char *format, ...)
4459 va_start (ap, format);
4460 if (debug_codeselection)
4462 vfprintf (errorf, format, ap);
4468 main (int argc, char **argv)