gas/config/bfin-parse.y

   1 /* bfin-parse.y  ADI Blackfin parser
   2    Copyright 2005, 2006, 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21 %{
  22
  23 #include "as.h"
  24 #include <obstack.h>
  25
  26 #include "bfin-aux.h"  /* Opcode generating auxiliaries.  */
  27 #include "libbfd.h"
  28 #include "elf/common.h"
  29 #include "elf/bfin.h"
  30
  31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
  32         bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
  33
  34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
  35         bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
  36                            dst, src0, src1, w0)
  37
  38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
  39         bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
  40                             dst, src0, src1, w0)
  41
  42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls)  \
  43         bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
  44
  45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls)  \
  46         bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
  47
  48 #define LDIMMHALF_R(reg, h, s, z, hword) \
  49         bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
  50
  51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
  52         bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
  53
  54 #define LDSTIDXI(ptr, reg, w, sz, z, offset)  \
  55         bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
  56
  57 #define LDST(ptr, reg, aop, sz, z, w)  \
  58         bfin_gen_ldst (ptr, reg, aop, sz, z, w)
  59
  60 #define LDSTII(ptr, reg, offset, w, op)  \
  61         bfin_gen_ldstii (ptr, reg, offset, w, op)
  62
  63 #define DSPLDST(i, m, reg, aop, w) \
  64         bfin_gen_dspldst (i, reg, aop, w, m)
  65
  66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
  67         bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
  68
  69 #define LDSTIIFP(offset, reg, w)  \
  70         bfin_gen_ldstiifp (reg, offset, w)
  71
  72 #define LOGI2OP(dst, src, opc) \
  73         bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
  74
  75 #define ALU2OP(dst, src, opc)  \
  76         bfin_gen_alu2op (dst, src, opc)
  77
  78 #define BRCC(t, b, offset) \
  79         bfin_gen_brcc (t, b, offset)
  80
  81 #define UJUMP(offset) \
  82         bfin_gen_ujump (offset)
  83
  84 #define PROGCTRL(prgfunc, poprnd) \
  85         bfin_gen_progctrl (prgfunc, poprnd)
  86
  87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
  88         bfin_gen_pushpopmultiple (dr, pr, d, p, w)
  89
  90 #define PUSHPOPREG(reg, w) \
  91         bfin_gen_pushpopreg (reg, w)
  92
  93 #define CALLA(addr, s)  \
  94         bfin_gen_calla (addr, s)
  95
  96 #define LINKAGE(r, framesize) \
  97         bfin_gen_linkage (r, framesize)
  98
  99 #define COMPI2OPD(dst, src, op)  \
 100         bfin_gen_compi2opd (dst, src, op)
 101
 102 #define COMPI2OPP(dst, src, op)  \
 103         bfin_gen_compi2opp (dst, src, op)
 104
 105 #define DAGMODIK(i, op)  \
 106         bfin_gen_dagmodik (i, op)
 107
 108 #define DAGMODIM(i, m, op, br)  \
 109         bfin_gen_dagmodim (i, m, op, br)
 110
 111 #define COMP3OP(dst, src0, src1, opc)   \
 112         bfin_gen_comp3op (src0, src1, dst, opc)
 113
 114 #define PTR2OP(dst, src, opc)   \
 115         bfin_gen_ptr2op (dst, src, opc)
 116
 117 #define CCFLAG(x, y, opc, i, g)  \
 118         bfin_gen_ccflag (x, y, opc, i, g)
 119
 120 #define CCMV(src, dst, t) \
 121         bfin_gen_ccmv (src, dst, t)
 122
 123 #define CACTRL(reg, a, op) \
 124         bfin_gen_cactrl (reg, a, op)
 125
 126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
 127         bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
 128
 129 #define HL2(r1, r0)  (IS_H (r1) << 1 | IS_H (r0))
 130 #define IS_RANGE(bits, expr, sign, mul)    \
 131         value_match(expr, bits, sign, mul, 1)
 132 #define IS_URANGE(bits, expr, sign, mul)    \
 133         value_match(expr, bits, sign, mul, 0)
 134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
 135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
 136 #define IS_IMM(expr, bits)  value_match (expr, bits, 0, 1, 1)
 137 #define IS_UIMM(expr, bits)  value_match (expr, bits, 0, 1, 0)
 138
 139 #define IS_PCREL4(expr) \
 140         (value_match (expr, 4, 0, 2, 0))
 141
 142 #define IS_LPPCREL10(expr) \
 143         (value_match (expr, 10, 0, 2, 0))
 144
 145 #define IS_PCREL10(expr) \
 146         (value_match (expr, 10, 0, 2, 1))
 147
 148 #define IS_PCREL12(expr) \
 149         (value_match (expr, 12, 0, 2, 1))
 150
 151 #define IS_PCREL24(expr) \
 152         (value_match (expr, 24, 0, 2, 1))
 153
 154
 155 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
 156
 157 extern FILE *errorf;
 158 extern INSTR_T insn;
 159
 160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
 161 static Expr_Node *unary  (Expr_Op_Type, Expr_Node *);
 162
 163 static void notethat (char *format, ...);
 164
 165 char *current_inputline;
 166 extern char *yytext;
 167 int yyerror (char *msg);
 168
 169 void error (char *format, ...)
 170 {
 171     va_list ap;
 172     static char buffer[2000];
 173
 174     va_start (ap, format);
 175     vsprintf (buffer, format, ap);
 176     va_end (ap);
 177
 178     as_bad ("%s", buffer);
 179 }
 180
 181 int
 182 yyerror (char *msg)
 183 {
 184   if (msg[0] == '\0')
 185     error ("%s", msg);
 186
 187   else if (yytext[0] != ';')
 188     error ("%s. Input text was %s.", msg, yytext);
 189   else
 190     error ("%s.", msg);
 191
 192   return -1;
 193 }
 194
 195 static int
 196 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
 197 {
 198   int val = EXPR_VALUE (expr);
 199   if (expr->type != Expr_Node_Constant)
 200     return 0;
 201   if (val < from || val > to)
 202     return 0;
 203   return (val & mask) == 0;
 204 }
 205
 206 extern int yylex (void);
 207
 208 #define imm3(x) EXPR_VALUE (x)
 209 #define imm4(x) EXPR_VALUE (x)
 210 #define uimm4(x) EXPR_VALUE (x)
 211 #define imm5(x) EXPR_VALUE (x)
 212 #define uimm5(x) EXPR_VALUE (x)
 213 #define imm6(x) EXPR_VALUE (x)
 214 #define imm7(x) EXPR_VALUE (x)
 215 #define imm16(x) EXPR_VALUE (x)
 216 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
 217 #define uimm16(x) EXPR_VALUE (x)
 218
 219 /* Return true if a value is inside a range.  */
 220 #define IN_RANGE(x, low, high) \
 221   (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
 222
 223 /* Auxiliary functions.  */
 224
 225 static int
 226 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
 227 {
 228   if (!IS_DREG (*reg1))
 229     {
 230       yyerror ("Dregs expected");
 231       return 0;
 232     }
 233
 234   if (reg1->regno != 1 && reg1->regno != 3)
 235     {
 236       yyerror ("Bad register pair");
 237       return 0;
 238     }
 239
 240   if (imm7 (reg2) != reg1->regno - 1)
 241     {
 242       yyerror ("Bad register pair");
 243       return 0;
 244     }
 245
 246   reg1->regno--;
 247   return 1;
 248 }
 249
 250 static int
 251 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
 252 {
 253   if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
 254       || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
 255     return yyerror ("Source multiplication register mismatch");
 256
 257   return 0;
 258 }
 259
 260
 261 /* Check mac option.  */
 262
 263 static int
 264 check_macfunc_option (Macfunc *a, Opt_mode *opt)
 265 {
 266   /* Default option is always valid.  */
 267   if (opt->mod == 0)
 268     return 0;
 269
 270   if ((a->w == 1 && a->P == 1
 271        && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
 272        && opt->mod != M_S2RND && opt->mod != M_ISS2)
 273       || (a->w == 1 && a->P == 0
 274           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
 275           && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
 276           && opt->mod != M_ISS2 && opt->mod != M_IH)
 277       || (a->w == 0 && a->P == 0
 278           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
 279     return -1;
 280
 281   return 0;
 282 }
 283
 284 /* Check (vector) mac funcs and ops.  */
 285
 286 static int
 287 check_macfuncs (Macfunc *aa, Opt_mode *opa,
 288                 Macfunc *ab, Opt_mode *opb)
 289 {
 290   /* Variables for swapping.  */
 291   Macfunc mtmp;
 292   Opt_mode otmp;
 293
 294   /* The option mode should be put at the end of the second instruction
 295      of the vector except M, which should follow MAC1 instruction.  */
 296   if (opa->mod != 0)
 297     return yyerror ("Bad opt mode");
 298
 299   /* If a0macfunc comes before a1macfunc, swap them.  */
 300
 301   if (aa->n == 0)
 302     {
 303       /*  (M) is not allowed here.  */
 304       if (opa->MM != 0)
 305         return yyerror ("(M) not allowed with A0MAC");
 306       if (ab->n != 1)
 307         return yyerror ("Vector AxMACs can't be same");
 308
 309       mtmp = *aa; *aa = *ab; *ab = mtmp;
 310       otmp = *opa; *opa = *opb; *opb = otmp;
 311     }
 312   else
 313     {
 314       if (opb->MM != 0)
 315         return yyerror ("(M) not allowed with A0MAC");
 316       if (ab->n != 0)
 317         return yyerror ("Vector AxMACs can't be same");
 318     }
 319
 320   /*  If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
 321   assignment_or_macfuncs.  */
 322   if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
 323       && (ab->op == 0 || ab->op == 1 || ab->op == 2))
 324     {
 325       if (check_multiply_halfregs (aa, ab) < 0)
 326         return -1;
 327     }
 328   else
 329     {
 330       /*  Only one of the assign_macfuncs has a half reg multiply
 331       Evil trick: Just 'OR' their source register codes:
 332       We can do that, because we know they were initialized to 0
 333       in the rules that don't use multiply_halfregs.  */
 334       aa->s0.regno |= (ab->s0.regno & CODE_MASK);
 335       aa->s1.regno |= (ab->s1.regno & CODE_MASK);
 336     }
 337
 338   if (aa->w == ab->w  && aa->P != ab->P)
 339     {
 340       return yyerror ("macfuncs must differ");
 341       if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
 342         return yyerror ("Destination Dregs must differ by one");
 343     }
 344
 345   /* Make sure mod flags get ORed, too.  */
 346   opb->mod |= opa->mod;
 347
 348   /* Check option.  */
 349   if (check_macfunc_option (aa, opb) < 0
 350       && check_macfunc_option (ab, opb) < 0)
 351     return yyerror ("bad option");
 352
 353   /* Make sure first macfunc has got both P flags ORed.  */
 354   aa->P |= ab->P;
 355
 356   return 0;
 357 }
 358
 359
 360 static int
 361 is_group1 (INSTR_T x)
 362 {
 363   /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii.  */
 364   if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
 365     return 1;
 366
 367   return 0;
 368 }
 369
 370 static int
 371 is_group2 (INSTR_T x)
 372 {
 373   if ((((x->value & 0xfc00) == 0x9c00)  /* dspLDST.  */
 374        && !((x->value & 0xfde0) == 0x9c60)  /* dagMODim.  */
 375        && !((x->value & 0xfde0) == 0x9ce0)  /* dagMODim with bit rev.  */
 376        && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik.  */
 377       || (x->value == 0x0000))
 378     return 1;
 379   return 0;
 380 }
 381
 382 static INSTR_T
 383 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
 384 {
 385   int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
 386   int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
 387   int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
 388
 389   if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
 390     yyerror ("resource conflict in multi-issue instruction");
 391
 392   /* Anomaly 05000074 */
 393   if (ENABLE_AC_05000074
 394       && (dsp32->value & 0xf780) == 0xc680
 395       && ((dsp16_grp1->value & 0xfe40) == 0x9240
 396           || (dsp16_grp1->value & 0xfe08) == 0xba08
 397           || (dsp16_grp1->value & 0xfc00) == 0xbc00))
 398     yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
 399 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
 400
 401   return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
 402 }
 403
 404 %}
 405
 406 %union {
 407   INSTR_T instr;
 408   Expr_Node *expr;
 409   SYMBOL_T symbol;
 410   long value;
 411   Register reg;
 412   Macfunc macfunc;
 413   struct { int r0; int s0; int x0; int aop; } modcodes;
 414   struct { int r0; } r0;
 415   Opt_mode mod;
 416 }
 417
 418
 419 /* Tokens.  */
 420
 421 /* Vector Specific.  */
 422 %token BYTEOP16P BYTEOP16M
 423 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
 424 %token BYTEUNPACK BYTEPACK
 425 %token PACK
 426 %token SAA
 427 %token ALIGN8 ALIGN16 ALIGN24
 428 %token VIT_MAX
 429 %token EXTRACT DEPOSIT EXPADJ SEARCH
 430 %token ONES SIGN SIGNBITS
 431
 432 /* Stack.  */
 433 %token LINK UNLINK
 434
 435 /* Registers.  */
 436 %token REG
 437 %token PC
 438 %token CCREG BYTE_DREG
 439 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
 440 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
 441 %token HALF_REG
 442
 443 /* Progctrl.  */
 444 %token NOP
 445 %token RTI RTS RTX RTN RTE
 446 %token HLT IDLE
 447 %token STI CLI
 448 %token CSYNC SSYNC
 449 %token EMUEXCPT
 450 %token RAISE EXCPT
 451 %token LSETUP
 452 %token LOOP
 453 %token LOOP_BEGIN
 454 %token LOOP_END
 455 %token DISALGNEXCPT
 456 %token JUMP JUMP_DOT_S JUMP_DOT_L
 457 %token CALL
 458
 459 /* Emulator only.  */
 460 %token ABORT
 461
 462 /* Operators.  */
 463 %token NOT TILDA BANG
 464 %token AMPERSAND BAR
 465 %token PERCENT
 466 %token CARET
 467 %token BXOR
 468
 469 %token MINUS PLUS STAR SLASH
 470 %token NEG
 471 %token MIN MAX ABS
 472 %token DOUBLE_BAR
 473 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
 474 %token _MINUS_MINUS _PLUS_PLUS
 475
 476 /* Shift/rotate ops.  */
 477 %token SHIFT LSHIFT ASHIFT BXORSHIFT
 478 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
 479 %token ROT
 480 %token LESS_LESS GREATER_GREATER
 481 %token _GREATER_GREATER_GREATER
 482 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
 483 %token DIVS DIVQ
 484
 485 /* In place operators.  */
 486 %token ASSIGN _STAR_ASSIGN
 487 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
 488 %token _MINUS_ASSIGN _PLUS_ASSIGN
 489
 490 /* Assignments, comparisons.  */
 491 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
 492 %token GE LT LE GT
 493 %token LESS_THAN
 494
 495 /* Cache.  */
 496 %token FLUSHINV FLUSH
 497 %token IFLUSH PREFETCH
 498
 499 /* Misc.  */
 500 %token PRNT
 501 %token OUTC
 502 %token WHATREG
 503 %token TESTSET
 504
 505 /* Modifiers.  */
 506 %token ASL ASR
 507 %token B W
 508 %token NS S CO SCO
 509 %token TH TL
 510 %token BP
 511 %token BREV
 512 %token X Z
 513 %token M MMOD
 514 %token R RND RNDL RNDH RND12 RND20
 515 %token V
 516 %token LO HI
 517
 518 /* Bit ops.  */
 519 %token BITTGL BITCLR BITSET BITTST BITMUX
 520
 521 /* Debug.  */
 522 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
 523
 524 /* Semantic auxiliaries.  */
 525
 526 %token IF COMMA BY
 527 %token COLON SEMICOLON
 528 %token RPAREN LPAREN LBRACK RBRACK
 529 %token STATUS_REG
 530 %token MNOP
 531 %token SYMBOL NUMBER
 532 %token GOT GOT17M4 FUNCDESC_GOT17M4
 533 %token AT PLTPC
 534
 535 /* Types.  */
 536 %type <instr> asm
 537 %type <value> MMOD
 538 %type <mod> opt_mode
 539
 540 %type <value> NUMBER
 541 %type <r0> aligndir
 542 %type <modcodes> byteop_mod
 543 %type <reg> a_assign
 544 %type <reg> a_plusassign
 545 %type <reg> a_minusassign
 546 %type <macfunc> multiply_halfregs
 547 %type <macfunc> assign_macfunc
 548 %type <macfunc> a_macfunc
 549 %type <expr> expr_1
 550 %type <instr> asm_1
 551 %type <r0> vmod
 552 %type <modcodes> vsmod
 553 %type <modcodes> ccstat
 554 %type <r0> cc_op
 555 %type <reg> CCREG
 556 %type <reg> reg_with_postinc
 557 %type <reg> reg_with_predec
 558
 559 %type <r0> searchmod
 560 %type <expr> symbol
 561 %type <symbol> SYMBOL
 562 %type <expr> eterm
 563 %type <reg> REG
 564 %type <reg> BYTE_DREG
 565 %type <reg> REG_A_DOUBLE_ZERO
 566 %type <reg> REG_A_DOUBLE_ONE
 567 %type <reg> REG_A
 568 %type <reg> STATUS_REG
 569 %type <expr> expr
 570 %type <r0> xpmod
 571 %type <r0> xpmod1
 572 %type <modcodes> smod
 573 %type <modcodes> b3_op
 574 %type <modcodes> rnd_op
 575 %type <modcodes> post_op
 576 %type <reg> HALF_REG
 577 %type <r0> iu_or_nothing
 578 %type <r0> plus_minus
 579 %type <r0> asr_asl
 580 %type <r0> asr_asl_0
 581 %type <modcodes> sco
 582 %type <modcodes> amod0
 583 %type <modcodes> amod1
 584 %type <modcodes> amod2
 585 %type <r0> op_bar_op
 586 %type <r0> w32_or_nothing
 587 %type <r0> c_align
 588 %type <r0> min_max
 589 %type <expr> got
 590 %type <expr> got_or_expr
 591 %type <expr> pltpc
 592 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
 593
 594 /* Precedence rules.  */
 595 %left BAR
 596 %left CARET
 597 %left AMPERSAND
 598 %left LESS_LESS GREATER_GREATER
 599 %left PLUS MINUS
 600 %left STAR SLASH PERCENT
 601
 602 %right ASSIGN
 603
 604 %right TILDA BANG
 605 %start statement
 606 %%
 607 statement:
 608         | asm
 609         {
 610           insn = $1;
 611           if (insn == (INSTR_T) 0)
 612             return NO_INSN_GENERATED;
 613           else if (insn == (INSTR_T) - 1)
 614             return SEMANTIC_ERROR;
 615           else
 616             return INSN_GENERATED;
 617         }
 618         ;
 619
 620 asm: asm_1 SEMICOLON
 621         /* Parallel instructions.  */
 622         | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
 623         {
 624           if (($1->value & 0xf800) == 0xc000)
 625             {
 626               if (is_group1 ($3) && is_group2 ($5))
 627                 $$ = gen_multi_instr_1 ($1, $3, $5);
 628               else if (is_group2 ($3) && is_group1 ($5))
 629                 $$ = gen_multi_instr_1 ($1, $5, $3);
 630               else
 631                 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
 632             }
 633           else if (($3->value & 0xf800) == 0xc000)
 634             {
 635               if (is_group1 ($1) && is_group2 ($5))
 636                 $$ = gen_multi_instr_1 ($3, $1, $5);
 637               else if (is_group2 ($1) && is_group1 ($5))
 638                 $$ = gen_multi_instr_1 ($3, $5, $1);
 639               else
 640                 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
 641             }
 642           else if (($5->value & 0xf800) == 0xc000)
 643             {
 644               if (is_group1 ($1) && is_group2 ($3))
 645                 $$ = gen_multi_instr_1 ($5, $1, $3);
 646               else if (is_group2 ($1) && is_group1 ($3))
 647                 $$ = gen_multi_instr_1 ($5, $3, $1);
 648               else
 649                 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
 650             }
 651           else
 652             error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
 653         }
 654
 655         | asm_1 DOUBLE_BAR asm_1 SEMICOLON
 656         {
 657           if (($1->value & 0xf800) == 0xc000)
 658             {
 659               if (is_group1 ($3))
 660                 $$ = gen_multi_instr_1 ($1, $3, 0);
 661               else if (is_group2 ($3))
 662                 $$ = gen_multi_instr_1 ($1, 0, $3);
 663               else
 664                 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
 665             }
 666           else if (($3->value & 0xf800) == 0xc000)
 667             {
 668               if (is_group1 ($1))
 669                 $$ = gen_multi_instr_1 ($3, $1, 0);
 670               else if (is_group2 ($1))
 671                 $$ = gen_multi_instr_1 ($3, 0, $1);
 672               else
 673                 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
 674             }
 675           else if (is_group1 ($1) && is_group2 ($3))
 676               $$ = gen_multi_instr_1 (0, $1, $3);
 677           else if (is_group2 ($1) && is_group1 ($3))
 678             $$ = gen_multi_instr_1 (0, $3, $1);
 679           else
 680             return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
 681         }
 682         | error
 683         {
 684         $$ = 0;
 685         yyerror ("");
 686         yyerrok;
 687         }
 688         ;
 689
 690 /* DSPMAC.  */
 691
 692 asm_1:
 693         MNOP
 694         {
 695           $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
 696         }
 697         | assign_macfunc opt_mode
 698         {
 699           int op0, op1;
 700           int w0 = 0, w1 = 0;
 701           int h00, h10, h01, h11;
 702
 703           if (check_macfunc_option (&$1, &$2) < 0)
 704             return yyerror ("bad option");
 705
 706           if ($1.n == 0)
 707             {
 708               if ($2.MM)
 709                 return yyerror ("(m) not allowed with a0 unit");
 710               op1 = 3;
 711               op0 = $1.op;
 712               w1 = 0;
 713               w0 = $1.w;
 714               h00 = IS_H ($1.s0);
 715               h10 = IS_H ($1.s1);
 716               h01 = h11 = 0;
 717             }
 718           else
 719             {
 720               op1 = $1.op;
 721               op0 = 3;
 722               w1 = $1.w;
 723               w0 = 0;
 724               h00 = h10 = 0;
 725               h01 = IS_H ($1.s0);
 726               h11 = IS_H ($1.s1);
 727             }
 728           $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
 729                          &$1.dst, op0, &$1.s0, &$1.s1, w0);
 730         }
 731
 732
 733 /* VECTOR MACs.  */
 734
 735         | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
 736         {
 737           Register *dst;
 738
 739           if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
 740             return -1;
 741           notethat ("assign_macfunc (.), assign_macfunc (.)\n");
 742
 743           if ($1.w)
 744             dst = &$1.dst;
 745           else
 746             dst = &$4.dst;
 747
 748           $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
 749                          IS_H ($1.s0),  IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
 750                          dst, $4.op, &$1.s0, &$1.s1, $4.w);
 751         }
 752
 753 /* DSPALU.  */
 754
 755         | DISALGNEXCPT
 756         {
 757           notethat ("dsp32alu: DISALGNEXCPT\n");
 758           $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
 759         }
 760         | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 761         {
 762           if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
 763             {
 764               notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
 765               $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
 766             }
 767           else
 768             return yyerror ("Register mismatch");
 769         }
 770         | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 771         {
 772           if (!IS_A1 ($4) && IS_A1 ($5))
 773             {
 774               notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
 775               $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
 776             }
 777           else
 778             return yyerror ("Register mismatch");
 779         }
 780         | A_ZERO_DOT_H ASSIGN HALF_REG
 781         {
 782           notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
 783           $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
 784         }
 785         | A_ONE_DOT_H ASSIGN HALF_REG
 786         {
 787           notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
 788           $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
 789         }
 790         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
 791           COLON expr COMMA REG COLON expr RPAREN aligndir
 792         {
 793           if (!IS_DREG ($2) || !IS_DREG ($4))
 794             return yyerror ("Dregs expected");
 795           else if (!valid_dreg_pair (&$9, $11))
 796             return yyerror ("Bad dreg pair");
 797           else if (!valid_dreg_pair (&$13, $15))
 798             return yyerror ("Bad dreg pair");
 799           else
 800             {
 801               notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
 802               $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
 803             }
 804         }
 805
 806         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
 807           REG COLON expr RPAREN aligndir
 808         {
 809           if (!IS_DREG ($2) || !IS_DREG ($4))
 810             return yyerror ("Dregs expected");
 811           else if (!valid_dreg_pair (&$9, $11))
 812             return yyerror ("Bad dreg pair");
 813           else if (!valid_dreg_pair (&$13, $15))
 814             return yyerror ("Bad dreg pair");
 815           else
 816             {
 817               notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
 818               $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
 819             }
 820         }
 821
 822         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
 823         {
 824           if (!IS_DREG ($2) || !IS_DREG ($4))
 825             return yyerror ("Dregs expected");
 826           else if (!valid_dreg_pair (&$8, $10))
 827             return yyerror ("Bad dreg pair");
 828           else
 829             {
 830               notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
 831               $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
 832             }
 833         }
 834         | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
 835         {
 836           if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
 837             {
 838               notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
 839               $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
 840             }
 841           else
 842             return yyerror ("Register mismatch");
 843         }
 844         | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
 845           REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
 846         {
 847           if (IS_DREG ($1) && IS_DREG ($7))
 848             {
 849               notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");
 850               $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
 851             }
 852           else
 853             return yyerror ("Register mismatch");
 854         }
 855
 856
 857         | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
 858         {
 859           if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 860               && IS_A1 ($9) && !IS_A1 ($11))
 861             {
 862               notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
 863               $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
 864
 865             }
 866           else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 867                    && !IS_A1 ($9) && IS_A1 ($11))
 868             {
 869               notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
 870               $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
 871             }
 872           else
 873             return yyerror ("Register mismatch");
 874         }
 875
 876         | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
 877         {
 878           if ($4.r0 == $10.r0)
 879             return yyerror ("Operators must differ");
 880
 881           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
 882               && REG_SAME ($3, $9) && REG_SAME ($5, $11))
 883             {
 884               notethat ("dsp32alu: dregs = dregs + dregs,"
 885                        "dregs = dregs - dregs (amod1)\n");
 886               $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
 887             }
 888           else
 889             return yyerror ("Register mismatch");
 890         }
 891
 892 /*  Bar Operations.  */
 893
 894         | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
 895         {
 896           if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
 897             return yyerror ("Differing source registers");
 898
 899           if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
 900             return yyerror ("Dregs expected");
 901
 902
 903           if ($4.r0 == 1 && $10.r0 == 2)
 904             {
 905               notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
 906               $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
 907             }
 908           else if ($4.r0 == 0 && $10.r0 == 3)
 909             {
 910               notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
 911               $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
 912             }
 913           else
 914             return yyerror ("Bar operand mismatch");
 915         }
 916
 917         | REG ASSIGN ABS REG vmod
 918         {
 919           int op;
 920
 921           if (IS_DREG ($1) && IS_DREG ($4))
 922             {
 923               if ($5.r0)
 924                 {
 925                   notethat ("dsp32alu: dregs = ABS dregs (v)\n");
 926                   op = 6;
 927                 }
 928               else
 929                 {
 930                   /* Vector version of ABS.  */
 931                   notethat ("dsp32alu: dregs = ABS dregs\n");
 932                   op = 7;
 933                 }
 934               $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
 935             }
 936           else
 937             return yyerror ("Dregs expected");
 938         }
 939         | a_assign ABS REG_A
 940         {
 941           notethat ("dsp32alu: Ax = ABS Ax\n");
 942           $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
 943         }
 944         | A_ZERO_DOT_L ASSIGN HALF_REG
 945         {
 946           if (IS_DREG_L ($3))
 947             {
 948               notethat ("dsp32alu: A0.l = reg_half\n");
 949               $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
 950             }
 951           else
 952             return yyerror ("A0.l = Rx.l expected");
 953         }
 954         | A_ONE_DOT_L ASSIGN HALF_REG
 955         {
 956           if (IS_DREG_L ($3))
 957             {
 958               notethat ("dsp32alu: A1.l = reg_half\n");
 959               $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
 960             }
 961           else
 962             return yyerror ("A1.l = Rx.l expected");
 963         }
 964
 965         | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
 966         {
 967           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
 968             {
 969               notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
 970               $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
 971             }
 972           else
 973             return yyerror ("Dregs expected");
 974         }
 975
 976         | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
 977         {
 978           if (!IS_DREG ($1))
 979             return yyerror ("Dregs expected");
 980           else if (!valid_dreg_pair (&$5, $7))
 981             return yyerror ("Bad dreg pair");
 982           else if (!valid_dreg_pair (&$9, $11))
 983             return yyerror ("Bad dreg pair");
 984           else
 985             {
 986               notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
 987               $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
 988             }
 989         }
 990         | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
 991         {
 992           if (!IS_DREG ($1))
 993             return yyerror ("Dregs expected");
 994           else if (!valid_dreg_pair (&$5, $7))
 995             return yyerror ("Bad dreg pair");
 996           else if (!valid_dreg_pair (&$9, $11))
 997             return yyerror ("Bad dreg pair");
 998           else
 999             {
1000               notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1001               $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1002             }
1003         }
1004
1005         | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1006           rnd_op
1007         {
1008           if (!IS_DREG ($1))
1009             return yyerror ("Dregs expected");
1010           else if (!valid_dreg_pair (&$5, $7))
1011             return yyerror ("Bad dreg pair");
1012           else if (!valid_dreg_pair (&$9, $11))
1013             return yyerror ("Bad dreg pair");
1014           else
1015             {
1016               notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1017               $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1018             }
1019         }
1020
1021         | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1022           rnd_op
1023         {
1024           if (!IS_DREG ($1))
1025             return yyerror ("Dregs expected");
1026           else if (!valid_dreg_pair (&$5, $7))
1027             return yyerror ("Bad dreg pair");
1028           else if (!valid_dreg_pair (&$9, $11))
1029             return yyerror ("Bad dreg pair");
1030           else
1031             {
1032               notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1033               $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
1034             }
1035         }
1036
1037         | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1038           b3_op
1039         {
1040           if (!IS_DREG ($1))
1041             return yyerror ("Dregs expected");
1042           else if (!valid_dreg_pair (&$5, $7))
1043             return yyerror ("Bad dreg pair");
1044           else if (!valid_dreg_pair (&$9, $11))
1045             return yyerror ("Bad dreg pair");
1046           else
1047             {
1048               notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1049               $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1050             }
1051         }
1052
1053         | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1054         {
1055           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1056             {
1057               notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1058               $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1059             }
1060           else
1061             return yyerror ("Dregs expected");
1062         }
1063
1064         | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1065           HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1066         {
1067           if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1068             {
1069               notethat ("dsp32alu:      dregs_hi = dregs_lo ="
1070                        "SIGN (dregs_hi) * dregs_hi + "
1071                        "SIGN (dregs_lo) * dregs_lo \n");
1072
1073                 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1074             }
1075           else
1076             return yyerror ("Dregs expected");
1077         }
1078         | REG ASSIGN REG plus_minus REG amod1
1079         {
1080           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1081             {
1082               if ($6.aop == 0)
1083                 {
1084                   /* No saturation flag specified, generate the 16 bit variant.  */
1085                   notethat ("COMP3op: dregs = dregs +- dregs\n");
1086                   $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1087                 }
1088               else
1089                 {
1090                  /* Saturation flag specified, generate the 32 bit variant.  */
1091                  notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1092                  $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1093                 }
1094             }
1095           else
1096             if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1097               {
1098                 notethat ("COMP3op: pregs = pregs + pregs\n");
1099                 $$ = COMP3OP (&$1, &$3, &$5, 5);
1100               }
1101             else
1102               return yyerror ("Dregs expected");
1103         }
1104         | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1105         {
1106           int op;
1107
1108           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1109             {
1110               if ($9.r0)
1111                 op = 6;
1112               else
1113                 op = 7;
1114
1115               notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1116               $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1117             }
1118           else
1119             return yyerror ("Dregs expected");
1120         }
1121
1122         | a_assign MINUS REG_A
1123         {
1124           notethat ("dsp32alu: Ax = - Ax\n");
1125           $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1126         }
1127         | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1128         {
1129           notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1130           $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1131                          $6.s0, $6.x0, HL2 ($3, $5));
1132         }
1133         | a_assign a_assign expr
1134         {
1135           if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1136             {
1137               notethat ("dsp32alu: A1 = A0 = 0\n");
1138               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1139             }
1140           else
1141             return yyerror ("Bad value, 0 expected");
1142         }
1143
1144         /* Saturating.  */
1145         | a_assign REG_A LPAREN S RPAREN
1146         {
1147           if (REG_SAME ($1, $2))
1148             {
1149               notethat ("dsp32alu: Ax = Ax (S)\n");
1150               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1151             }
1152           else
1153             return yyerror ("Registers must be equal");
1154         }
1155
1156         | HALF_REG ASSIGN REG LPAREN RND RPAREN
1157         {
1158           if (IS_DREG ($3))
1159             {
1160               notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1161               $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1162             }
1163           else
1164             return yyerror ("Dregs expected");
1165         }
1166
1167         | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1168         {
1169           if (IS_DREG ($3) && IS_DREG ($5))
1170             {
1171               notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1172               $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1173             }
1174           else
1175             return yyerror ("Dregs expected");
1176         }
1177
1178         | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1179         {
1180           if (IS_DREG ($3) && IS_DREG ($5))
1181             {
1182               notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1183               $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1184             }
1185           else
1186             return yyerror ("Dregs expected");
1187         }
1188
1189         | a_assign REG_A
1190         {
1191           if (!REG_SAME ($1, $2))
1192             {
1193               notethat ("dsp32alu: An = Am\n");
1194               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1195             }
1196           else
1197             return yyerror ("Accu reg arguments must differ");
1198         }
1199
1200         | a_assign REG
1201         {
1202           if (IS_DREG ($2))
1203             {
1204               notethat ("dsp32alu: An = dregs\n");
1205               $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1206             }
1207           else
1208             return yyerror ("Dregs expected");
1209         }
1210
1211         | REG ASSIGN HALF_REG xpmod
1212         {
1213           if (!IS_H ($3))
1214             {
1215               if ($1.regno == REG_A0x && IS_DREG ($3))
1216                 {
1217                   notethat ("dsp32alu: A0.x = dregs_lo\n");
1218                   $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1219                 }
1220               else if ($1.regno == REG_A1x && IS_DREG ($3))
1221                 {
1222                   notethat ("dsp32alu: A1.x = dregs_lo\n");
1223                   $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1224                 }
1225               else if (IS_DREG ($1) && IS_DREG ($3))
1226                 {
1227                   notethat ("ALU2op: dregs = dregs_lo\n");
1228                   $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1229                 }
1230               else
1231                 return yyerror ("Register mismatch");
1232             }
1233           else
1234             return yyerror ("Low reg expected");
1235         }
1236
1237         | HALF_REG ASSIGN expr
1238         {
1239           notethat ("LDIMMhalf: pregs_half = imm16\n");
1240
1241           if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1242               && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1243             return yyerror ("Wrong register for load immediate");
1244
1245           if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1246             return yyerror ("Constant out of range");
1247
1248           $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1249         }
1250
1251         | a_assign expr
1252         {
1253           notethat ("dsp32alu: An = 0\n");
1254
1255           if (imm7 ($2) != 0)
1256             return yyerror ("0 expected");
1257
1258           $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1259         }
1260
1261         | REG ASSIGN expr xpmod1
1262         {
1263           if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1264               && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1265             return yyerror ("Wrong register for load immediate");
1266
1267           if ($4.r0 == 0)
1268             {
1269               /* 7 bit immediate value if possible.
1270                  We will check for that constant value for efficiency
1271                  If it goes to reloc, it will be 16 bit.  */
1272               if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1273                 {
1274                   notethat ("COMPI2opD: dregs = imm7 (x) \n");
1275                   $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1276                 }
1277               else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1278                 {
1279                   notethat ("COMPI2opP: pregs = imm7 (x)\n");
1280                   $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1281                 }
1282               else
1283                 {
1284                   if (IS_CONST ($3) && !IS_IMM ($3, 16))
1285                     return yyerror ("Immediate value out of range");
1286
1287                   notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1288                   /* reg, H, S, Z.   */
1289                   $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1290                 }
1291             }
1292           else
1293             {
1294               /* (z) There is no 7 bit zero extended instruction.
1295               If the expr is a relocation, generate it.   */
1296
1297               if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1298                 return yyerror ("Immediate value out of range");
1299
1300               notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1301               /* reg, H, S, Z.  */
1302               $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1303             }
1304         }
1305
1306         | HALF_REG ASSIGN REG
1307         {
1308           if (IS_H ($1))
1309             return yyerror ("Low reg expected");
1310
1311           if (IS_DREG ($1) && $3.regno == REG_A0x)
1312             {
1313               notethat ("dsp32alu: dregs_lo = A0.x\n");
1314               $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1315             }
1316           else if (IS_DREG ($1) && $3.regno == REG_A1x)
1317             {
1318               notethat ("dsp32alu: dregs_lo = A1.x\n");
1319               $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1320             }
1321           else
1322             return yyerror ("Register mismatch");
1323         }
1324
1325         | REG ASSIGN REG op_bar_op REG amod0
1326         {
1327           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1328             {
1329               notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1330               $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1331             }
1332           else
1333             return yyerror ("Register mismatch");
1334         }
1335
1336         | REG ASSIGN BYTE_DREG xpmod
1337         {
1338           if (IS_DREG ($1) && IS_DREG ($3))
1339             {
1340               notethat ("ALU2op: dregs = dregs_byte\n");
1341               $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1342             }
1343           else
1344             return yyerror ("Register mismatch");
1345         }
1346
1347         | a_assign ABS REG_A COMMA a_assign ABS REG_A
1348         {
1349           if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1350             {
1351               notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1352               $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1353             }
1354           else
1355             return yyerror ("Register mismatch");
1356         }
1357
1358         | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1359         {
1360           if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1361             {
1362               notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1363               $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1364             }
1365           else
1366             return yyerror ("Register mismatch");
1367         }
1368
1369         | a_minusassign REG_A w32_or_nothing
1370         {
1371           if (!IS_A1 ($1) && IS_A1 ($2))
1372             {
1373               notethat ("dsp32alu: A0 -= A1\n");
1374               $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1375             }
1376           else
1377             return yyerror ("Register mismatch");
1378         }
1379
1380         | REG _MINUS_ASSIGN expr
1381         {
1382           if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1383             {
1384               notethat ("dagMODik: iregs -= 4\n");
1385               $$ = DAGMODIK (&$1, 3);
1386             }
1387           else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1388             {
1389               notethat ("dagMODik: iregs -= 2\n");
1390               $$ = DAGMODIK (&$1, 1);
1391             }
1392           else
1393             return yyerror ("Register or value mismatch");
1394         }
1395
1396         | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1397         {
1398           if (IS_IREG ($1) && IS_MREG ($3))
1399             {
1400               notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1401               /* i, m, op, br.  */
1402               $$ = DAGMODIM (&$1, &$3, 0, 1);
1403             }
1404           else if (IS_PREG ($1) && IS_PREG ($3))
1405             {
1406               notethat ("PTR2op: pregs += pregs (BREV )\n");
1407               $$ = PTR2OP (&$1, &$3, 5);
1408             }
1409           else
1410             return yyerror ("Register mismatch");
1411         }
1412
1413         | REG _MINUS_ASSIGN REG
1414         {
1415           if (IS_IREG ($1) && IS_MREG ($3))
1416             {
1417               notethat ("dagMODim: iregs -= mregs\n");
1418               $$ = DAGMODIM (&$1, &$3, 1, 0);
1419             }
1420           else if (IS_PREG ($1) && IS_PREG ($3))
1421             {
1422               notethat ("PTR2op: pregs -= pregs\n");
1423               $$ = PTR2OP (&$1, &$3, 0);
1424             }
1425           else
1426             return yyerror ("Register mismatch");
1427         }
1428
1429         | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1430         {
1431           if (!IS_A1 ($1) && IS_A1 ($3))
1432             {
1433               notethat ("dsp32alu: A0 += A1 (W32)\n");
1434               $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1435             }
1436           else
1437             return yyerror ("Register mismatch");
1438         }
1439
1440         | REG _PLUS_ASSIGN REG
1441         {
1442           if (IS_IREG ($1) && IS_MREG ($3))
1443             {
1444               notethat ("dagMODim: iregs += mregs\n");
1445               $$ = DAGMODIM (&$1, &$3, 0, 0);
1446             }
1447           else
1448             return yyerror ("iregs += mregs expected");
1449         }
1450
1451         | REG _PLUS_ASSIGN expr
1452         {
1453           if (IS_IREG ($1))
1454             {
1455               if (EXPR_VALUE ($3) == 4)
1456                 {
1457                   notethat ("dagMODik: iregs += 4\n");
1458                   $$ = DAGMODIK (&$1, 2);
1459                 }
1460               else if (EXPR_VALUE ($3) == 2)
1461                 {
1462                   notethat ("dagMODik: iregs += 2\n");
1463                   $$ = DAGMODIK (&$1, 0);
1464                 }
1465               else
1466                 return yyerror ("iregs += [ 2 | 4 ");
1467             }
1468           else if (IS_PREG ($1) && IS_IMM ($3, 7))
1469             {
1470               notethat ("COMPI2opP: pregs += imm7\n");
1471               $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1472             }
1473           else if (IS_DREG ($1) && IS_IMM ($3, 7))
1474             {
1475               notethat ("COMPI2opD: dregs += imm7\n");
1476               $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1477             }
1478           else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1479             return yyerror ("Immediate value out of range");
1480           else
1481             return yyerror ("Register mismatch");
1482         }
1483
1484         | REG _STAR_ASSIGN REG
1485         {
1486           if (IS_DREG ($1) && IS_DREG ($3))
1487             {
1488               notethat ("ALU2op: dregs *= dregs\n");
1489               $$ = ALU2OP (&$1, &$3, 3);
1490             }
1491           else
1492             return yyerror ("Register mismatch");
1493         }
1494
1495         | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1496         {
1497           if (!valid_dreg_pair (&$3, $5))
1498             return yyerror ("Bad dreg pair");
1499           else if (!valid_dreg_pair (&$7, $9))
1500             return yyerror ("Bad dreg pair");
1501           else
1502             {
1503               notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1504               $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1505             }
1506         }
1507
1508         | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1509         {
1510           if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1511             {
1512               notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1513               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1514             }
1515           else
1516             return yyerror ("Register mismatch");
1517         }
1518
1519         | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1520         {
1521           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1522               && REG_SAME ($1, $4))
1523             {
1524               if (EXPR_VALUE ($9) == 1)
1525                 {
1526                   notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1527                   $$ = ALU2OP (&$1, &$6, 4);
1528                 }
1529               else if (EXPR_VALUE ($9) == 2)
1530                 {
1531                   notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1532                   $$ = ALU2OP (&$1, &$6, 5);
1533                 }
1534               else
1535                 return yyerror ("Bad shift value");
1536             }
1537           else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1538                    && REG_SAME ($1, $4))
1539             {
1540               if (EXPR_VALUE ($9) == 1)
1541                 {
1542                   notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1543                   $$ = PTR2OP (&$1, &$6, 6);
1544                 }
1545               else if (EXPR_VALUE ($9) == 2)
1546                 {
1547                   notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1548                   $$ = PTR2OP (&$1, &$6, 7);
1549                 }
1550               else
1551                 return yyerror ("Bad shift value");
1552             }
1553           else
1554             return yyerror ("Register mismatch");
1555         }
1556
1557 /*  COMP3 CCFLAG.  */
1558         | REG ASSIGN REG BAR REG
1559         {
1560           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1561             {
1562               notethat ("COMP3op: dregs = dregs | dregs\n");
1563               $$ = COMP3OP (&$1, &$3, &$5, 3);
1564             }
1565           else
1566             return yyerror ("Dregs expected");
1567         }
1568         | REG ASSIGN REG CARET REG
1569         {
1570           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1571             {
1572               notethat ("COMP3op: dregs = dregs ^ dregs\n");
1573               $$ = COMP3OP (&$1, &$3, &$5, 4);
1574             }
1575           else
1576             return yyerror ("Dregs expected");
1577         }
1578         | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1579         {
1580           if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1581             {
1582               if (EXPR_VALUE ($8) == 1)
1583                 {
1584                   notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1585                   $$ = COMP3OP (&$1, &$3, &$6, 6);
1586                 }
1587               else if (EXPR_VALUE ($8) == 2)
1588                 {
1589                   notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1590                   $$ = COMP3OP (&$1, &$3, &$6, 7);
1591                 }
1592               else
1593                   return yyerror ("Bad shift value");
1594             }
1595           else
1596             return yyerror ("Dregs expected");
1597         }
1598         | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1599         {
1600           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1601             {
1602               notethat ("CCflag: CC = A0 == A1\n");
1603               $$ = CCFLAG (0, 0, 5, 0, 0);
1604             }
1605           else
1606             return yyerror ("AREGs are in bad order or same");
1607         }
1608         | CCREG ASSIGN REG_A LESS_THAN REG_A
1609         {
1610           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1611             {
1612               notethat ("CCflag: CC = A0 < A1\n");
1613               $$ = CCFLAG (0, 0, 6, 0, 0);
1614             }
1615           else
1616             return yyerror ("AREGs are in bad order or same");
1617         }
1618         | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1619         {
1620           if ((IS_DREG ($3) && IS_DREG ($5))
1621               || (IS_PREG ($3) && IS_PREG ($5)))
1622             {
1623               notethat ("CCflag: CC = dpregs < dpregs\n");
1624               $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1625             }
1626           else
1627             return yyerror ("Bad register in comparison");
1628         }
1629         | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1630         {
1631           if (!IS_DREG ($3) && !IS_PREG ($3))
1632             return yyerror ("Bad register in comparison");
1633
1634           if (($6.r0 == 1 && IS_IMM ($5, 3))
1635               || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1636             {
1637               notethat ("CCflag: CC = dpregs < (u)imm3\n");
1638               $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1639             }
1640           else
1641             return yyerror ("Bad constant value");
1642         }
1643         | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1644         {
1645           if ((IS_DREG ($3) && IS_DREG ($5))
1646               || (IS_PREG ($3) && IS_PREG ($3)))
1647             {
1648               notethat ("CCflag: CC = dpregs == dpregs\n");
1649               $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1650             }
1651           else
1652             return yyerror ("Bad register in comparison");
1653         }
1654         | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1655         {
1656           if (!IS_DREG ($3) && !IS_PREG ($3))
1657             return yyerror ("Bad register in comparison");
1658
1659           if (IS_IMM ($5, 3))
1660             {
1661               notethat ("CCflag: CC = dpregs == imm3\n");
1662               $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1663             }
1664           else
1665             return yyerror ("Bad constant range");
1666         }
1667         | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1668         {
1669           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1670             {
1671               notethat ("CCflag: CC = A0 <= A1\n");
1672               $$ = CCFLAG (0, 0, 7, 0, 0);
1673             }
1674           else
1675             return yyerror ("AREGs are in bad order or same");
1676         }
1677         | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1678         {
1679           if ((IS_DREG ($3) && IS_DREG ($5))
1680               || (IS_PREG ($3) && IS_PREG ($5)))
1681             {
1682               notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1683               $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1684                            1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1685             }
1686           else
1687             return yyerror ("Bad register in comparison");
1688         }
1689         | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1690         {
1691           if (!IS_DREG ($3) && !IS_PREG ($3))
1692             return yyerror ("Bad register in comparison");
1693
1694           if (($6.r0 == 1 && IS_IMM ($5, 3))
1695               || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1696             {
1697               notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1698               $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1699             }
1700           else
1701             return yyerror ("Bad constant value");
1702         }
1703
1704         | REG ASSIGN REG AMPERSAND REG
1705         {
1706           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1707             {
1708               notethat ("COMP3op: dregs = dregs & dregs\n");
1709               $$ = COMP3OP (&$1, &$3, &$5, 2);
1710             }
1711           else
1712             return yyerror ("Dregs expected");
1713         }
1714
1715         | ccstat
1716         {
1717           notethat ("CC2stat operation\n");
1718           $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1719         }
1720
1721         | REG ASSIGN REG
1722         {
1723           if (IS_ALLREG ($1) && IS_ALLREG ($3))
1724             {
1725               notethat ("REGMV: allregs = allregs\n");
1726               $$ = bfin_gen_regmv (&$3, &$1);
1727             }
1728           else
1729             return yyerror ("Register mismatch");
1730         }
1731
1732         | CCREG ASSIGN REG
1733         {
1734           if (IS_DREG ($3))
1735             {
1736               notethat ("CC2dreg: CC = dregs\n");
1737               $$ = bfin_gen_cc2dreg (1, &$3);
1738             }
1739           else
1740             return yyerror ("Register mismatch");
1741         }
1742
1743         | REG ASSIGN CCREG
1744         {
1745           if (IS_DREG ($1))
1746             {
1747               notethat ("CC2dreg: dregs = CC\n");
1748               $$ = bfin_gen_cc2dreg (0, &$1);
1749             }
1750           else
1751             return yyerror ("Register mismatch");
1752         }
1753
1754         | CCREG _ASSIGN_BANG CCREG
1755         {
1756           notethat ("CC2dreg: CC =! CC\n");
1757           $$ = bfin_gen_cc2dreg (3, 0);
1758         }
1759
1760 /* DSPMULT.  */
1761
1762         | HALF_REG ASSIGN multiply_halfregs opt_mode
1763         {
1764           notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1765
1766           if (!IS_H ($1) && $4.MM)
1767             return yyerror ("(M) not allowed with MAC0");
1768
1769           if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1770               && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1771               && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1772             return yyerror ("bad option.");
1773
1774           if (IS_H ($1))
1775             {
1776               $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1777                               IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1778                               &$1, 0, &$3.s0, &$3.s1, 0);
1779             }
1780           else
1781             {
1782               $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1783                               0, 0, IS_H ($3.s0), IS_H ($3.s1),
1784                               &$1, 0, &$3.s0, &$3.s1, 1);
1785             }
1786         }
1787
1788         | REG ASSIGN multiply_halfregs opt_mode
1789         {
1790           /* Odd registers can use (M).  */
1791           if (!IS_DREG ($1))
1792             return yyerror ("Dreg expected");
1793
1794           if (IS_EVEN ($1) && $4.MM)
1795             return yyerror ("(M) not allowed with MAC0");
1796
1797           if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1798               && $4.mod != M_S2RND && $4.mod != M_ISS2)
1799             return yyerror ("bad option");
1800
1801           if (!IS_EVEN ($1))
1802             {
1803               notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1804
1805               $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1806                               IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1807                               &$1, 0, &$3.s0, &$3.s1, 0);
1808             }
1809           else
1810             {
1811               notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1812               $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1813                               0, 0, IS_H ($3.s0), IS_H ($3.s1),
1814                               &$1,  0, &$3.s0, &$3.s1, 1);
1815             }
1816         }
1817
1818         | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1819           HALF_REG ASSIGN multiply_halfregs opt_mode
1820         {
1821           if (!IS_DREG ($1) || !IS_DREG ($6))
1822             return yyerror ("Dregs expected");
1823
1824           if (!IS_HCOMPL($1, $6))
1825             return yyerror ("Dest registers mismatch");
1826
1827           if (check_multiply_halfregs (&$3, &$8) < 0)
1828             return -1;
1829
1830           if ((!IS_H ($1) && $4.MM)
1831               || (!IS_H ($6) && $9.MM))
1832             return yyerror ("(M) not allowed with MAC0");
1833
1834           notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1835                     "dregs_lo = multiply_halfregs opt_mode\n");
1836
1837           if (IS_H ($1))
1838             $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1839                             IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1840                             &$1, 0, &$3.s0, &$3.s1, 1);
1841           else
1842             $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1843                             IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1844                             &$1, 0, &$3.s0, &$3.s1, 1);
1845         }
1846
1847         | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1848         {
1849           if (!IS_DREG ($1) || !IS_DREG ($6))
1850             return yyerror ("Dregs expected");
1851
1852           if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1853               || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1854             return yyerror ("Dest registers mismatch");
1855
1856           if (check_multiply_halfregs (&$3, &$8) < 0)
1857             return -1;
1858
1859           if ((IS_EVEN ($1) && $4.MM)
1860               || (IS_EVEN ($6) && $9.MM))
1861             return yyerror ("(M) not allowed with MAC0");
1862
1863           notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1864                    "dregs = multiply_halfregs opt_mode\n");
1865
1866           if (IS_EVEN ($1))
1867             $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1868                             IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1869                             &$1, 0, &$3.s0, &$3.s1, 1);
1870           else
1871             $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1872                             IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1873                             &$1, 0, &$3.s0, &$3.s1, 1);
1874         }
1875
1876 \f
1877 /* SHIFTs.  */
1878         | a_assign ASHIFT REG_A BY HALF_REG
1879         {
1880           if (!REG_SAME ($1, $3))
1881             return yyerror ("Aregs must be same");
1882
1883           if (IS_DREG ($5) && !IS_H ($5))
1884             {
1885               notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1886               $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1887             }
1888           else
1889             return yyerror ("Dregs expected");
1890         }
1891
1892         | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1893         {
1894           if (IS_DREG ($6) && !IS_H ($6))
1895             {
1896               notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1897               $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1898             }
1899           else
1900             return yyerror ("Dregs expected");
1901         }
1902
1903         | a_assign REG_A LESS_LESS expr
1904         {
1905           if (!REG_SAME ($1, $2))
1906             return yyerror ("Aregs must be same");
1907
1908           if (IS_UIMM ($4, 5))
1909             {
1910               notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1911               $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1912             }
1913           else
1914             return yyerror ("Bad shift value");
1915         }
1916
1917         | REG ASSIGN REG LESS_LESS expr vsmod
1918         {
1919           if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1920             {
1921               if ($6.r0)
1922                 {
1923                   /*  Vector?  */
1924                   notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1925                   $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1926                 }
1927               else
1928                 {
1929                   notethat ("dsp32shiftimm: dregs =  dregs << uimm5 (.)\n");
1930                   $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1931                 }
1932             }
1933           else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1934             {
1935               if (EXPR_VALUE ($5) == 2)
1936                 {
1937                   notethat ("PTR2op: pregs = pregs << 2\n");
1938                   $$ = PTR2OP (&$1, &$3, 1);
1939                 }
1940               else if (EXPR_VALUE ($5) == 1)
1941                 {
1942                   notethat ("COMP3op: pregs = pregs << 1\n");
1943                   $$ = COMP3OP (&$1, &$3, &$3, 5);
1944                 }
1945               else
1946                 return yyerror ("Bad shift value");
1947             }
1948           else
1949             return yyerror ("Bad shift value or register");
1950         }
1951         | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1952         {
1953           if (IS_UIMM ($5, 4))
1954             {
1955               if ($6.s0)
1956                 {
1957                   notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
1958                   $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1959                 }
1960               else
1961                 {
1962                   notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1963                   $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1964                 }
1965             }
1966           else
1967             return yyerror ("Bad shift value");
1968         }
1969         | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1970         {
1971           int op;
1972
1973           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1974             {
1975               if ($7.r0)
1976                 {
1977                   op = 1;
1978                   notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1979                            "dregs_lo (V, .)\n");
1980                 }
1981               else
1982                 {
1983
1984                   op = 2;
1985                   notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1986                 }
1987               $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1988             }
1989           else
1990             return yyerror ("Dregs expected");
1991         }
1992
1993 /*  EXPADJ.  */
1994         | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
1995         {
1996           if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1997             {
1998               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
1999               $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2000             }
2001           else
2002             return yyerror ("Bad shift value or register");
2003         }
2004
2005
2006         | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2007         {
2008           if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2009             {
2010               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2011               $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2012             }
2013           else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2014             {
2015               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2016               $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2017             }
2018           else
2019             return yyerror ("Bad shift value or register");
2020         }
2021
2022 /* DEPOSIT.  */
2023
2024         | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2025         {
2026           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2027             {
2028               notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2029               $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2030             }
2031           else
2032             return yyerror ("Register mismatch");
2033         }
2034
2035         | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2036         {
2037           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2038             {
2039               notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2040               $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2041             }
2042           else
2043             return yyerror ("Register mismatch");
2044         }
2045
2046         | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2047         {
2048           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2049             {
2050               notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2051               $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2052             }
2053           else
2054             return yyerror ("Register mismatch");
2055         }
2056
2057         | a_assign REG_A _GREATER_GREATER_GREATER expr
2058         {
2059           if (!REG_SAME ($1, $2))
2060             return yyerror ("Aregs must be same");
2061
2062           if (IS_UIMM ($4, 5))
2063             {
2064               notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2065               $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2066             }
2067           else
2068             return yyerror ("Shift value range error");
2069         }
2070         | a_assign LSHIFT REG_A BY HALF_REG
2071         {
2072           if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2073             {
2074               notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2075               $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2076             }
2077           else
2078             return yyerror ("Register mismatch");
2079         }
2080
2081         | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2082         {
2083           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2084             {
2085               notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2086               $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2087             }
2088           else
2089             return yyerror ("Register mismatch");
2090         }
2091
2092         | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2093         {
2094           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2095             {
2096               notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2097               $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2098             }
2099           else
2100             return yyerror ("Register mismatch");
2101         }
2102
2103         | REG ASSIGN SHIFT REG BY HALF_REG
2104         {
2105           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2106             {
2107               notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2108               $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2109             }
2110           else
2111             return yyerror ("Register mismatch");
2112         }
2113
2114         | a_assign REG_A GREATER_GREATER expr
2115         {
2116           if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2117             {
2118               notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2119               $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2120             }
2121           else
2122             return yyerror ("Accu register expected");
2123         }
2124
2125         | REG ASSIGN REG GREATER_GREATER expr vmod
2126         {
2127           if ($6.r0 == 1)
2128             {
2129               if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2130                 {
2131                   notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2132                   $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2133                 }
2134               else
2135                 return yyerror ("Register mismatch");
2136             }
2137           else
2138             {
2139               if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2140                 {
2141                   notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2142                   $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2143                 }
2144               else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2145                 {
2146                   notethat ("PTR2op: pregs = pregs >> 2\n");
2147                   $$ = PTR2OP (&$1, &$3, 3);
2148                 }
2149               else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2150                 {
2151                   notethat ("PTR2op: pregs = pregs >> 1\n");
2152                   $$ = PTR2OP (&$1, &$3, 4);
2153                 }
2154               else
2155                 return yyerror ("Register mismatch");
2156             }
2157         }
2158         | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2159         {
2160           if (IS_UIMM ($5, 5))
2161             {
2162               notethat ("dsp32shiftimm:  dregs_half =  dregs_half >> uimm5\n");
2163               $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2164             }
2165           else
2166             return yyerror ("Register mismatch");
2167         }
2168         | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2169         {
2170           if (IS_UIMM ($5, 5))
2171             {
2172               notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2173               $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2174                                   $6.s0, HL2 ($1, $3));
2175             }
2176           else
2177             return yyerror ("Register or modifier mismatch");
2178         }
2179
2180
2181         | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2182         {
2183           if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2184             {
2185               if ($6.r0)
2186                 {
2187                   /* Vector?  */
2188                   notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (V, .)\n");
2189                   $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2190                 }
2191               else
2192                 {
2193                   notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (.)\n");
2194                   $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2195                 }
2196             }
2197           else
2198             return yyerror ("Register mismatch");
2199         }
2200
2201         | HALF_REG ASSIGN ONES REG
2202         {
2203           if (IS_DREG_L ($1) && IS_DREG ($4))
2204             {
2205               notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2206               $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2207             }
2208           else
2209             return yyerror ("Register mismatch");
2210         }
2211
2212         | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2213         {
2214           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2215             {
2216               notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2217               $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2218             }
2219           else
2220             return yyerror ("Register mismatch");
2221         }
2222
2223         | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2224         {
2225           if (IS_DREG ($1)
2226               && $7.regno == REG_A0
2227               && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2228             {
2229               notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2230               $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2231             }
2232           else
2233             return yyerror ("Register mismatch");
2234         }
2235
2236         | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2237         {
2238           if (IS_DREG ($1)
2239               && $7.regno == REG_A0
2240               && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2241             {
2242               notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2243               $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2244             }
2245           else
2246             return yyerror ("Register mismatch");
2247         }
2248
2249         | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2250         {
2251           if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2252             {
2253               notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2254               $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2255             }
2256           else
2257             return yyerror ("Register mismatch");
2258         }
2259
2260         | a_assign ROT REG_A BY HALF_REG
2261         {
2262           if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2263             {
2264               notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2265               $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2266             }
2267           else
2268             return yyerror ("Register mismatch");
2269         }
2270
2271         | REG ASSIGN ROT REG BY HALF_REG
2272         {
2273           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2274             {
2275               notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2276               $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2277             }
2278           else
2279             return yyerror ("Register mismatch");
2280         }
2281
2282         | a_assign ROT REG_A BY expr
2283         {
2284           if (IS_IMM ($5, 6))
2285             {
2286               notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2287               $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2288             }
2289           else
2290             return yyerror ("Register mismatch");
2291         }
2292
2293         | REG ASSIGN ROT REG BY expr
2294         {
2295           if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2296             {
2297               $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2298             }
2299           else
2300             return yyerror ("Register mismatch");
2301         }
2302
2303         | HALF_REG ASSIGN SIGNBITS REG_A
2304         {
2305           if (IS_DREG_L ($1))
2306             {
2307               notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2308               $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2309             }
2310           else
2311             return yyerror ("Register mismatch");
2312         }
2313
2314         | HALF_REG ASSIGN SIGNBITS REG
2315         {
2316           if (IS_DREG_L ($1) && IS_DREG ($4))
2317             {
2318               notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2319               $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2320             }
2321           else
2322             return yyerror ("Register mismatch");
2323         }
2324
2325         | HALF_REG ASSIGN SIGNBITS HALF_REG
2326         {
2327           if (IS_DREG_L ($1))
2328             {
2329               notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2330               $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2331             }
2332           else
2333             return yyerror ("Register mismatch");
2334         }
2335
2336         /* The ASR bit is just inverted here. */
2337         | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2338         {
2339           if (IS_DREG_L ($1) && IS_DREG ($5))
2340             {
2341               notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2342               $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2343             }
2344           else
2345             return yyerror ("Register mismatch");
2346         }
2347
2348         | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2349         {
2350           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2351             {
2352               notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2353               $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2354             }
2355           else
2356             return yyerror ("Register mismatch");
2357         }
2358
2359         | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2360         {
2361           if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2362             {
2363               notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2364               $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2365             }
2366           else
2367             return yyerror ("Register mismatch");
2368         }
2369
2370         | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2371         {
2372           if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2373             {
2374               notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2375               $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2376             }
2377           else
2378             return yyerror ("Dregs expected");
2379         }
2380
2381
2382 /* LOGI2op:     BITCLR (dregs, uimm5).  */
2383         | BITCLR LPAREN REG COMMA expr RPAREN
2384         {
2385           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2386             {
2387               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2388               $$ = LOGI2OP ($3, uimm5 ($5), 4);
2389             }
2390           else
2391             return yyerror ("Register mismatch");
2392         }
2393
2394 /* LOGI2op:     BITSET (dregs, uimm5).  */
2395         | BITSET LPAREN REG COMMA expr RPAREN
2396         {
2397           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2398             {
2399               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2400               $$ = LOGI2OP ($3, uimm5 ($5), 2);
2401             }
2402           else
2403             return yyerror ("Register mismatch");
2404         }
2405
2406 /* LOGI2op:     BITTGL (dregs, uimm5).  */
2407         | BITTGL LPAREN REG COMMA expr RPAREN
2408         {
2409           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2410             {
2411               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2412               $$ = LOGI2OP ($3, uimm5 ($5), 3);
2413             }
2414           else
2415             return yyerror ("Register mismatch");
2416         }
2417
2418         | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2419         {
2420           if (IS_DREG ($5) && IS_UIMM ($7, 5))
2421             {
2422               notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2423               $$ = LOGI2OP ($5, uimm5 ($7), 0);
2424             }
2425           else
2426             return yyerror ("Register mismatch or value error");
2427         }
2428
2429         | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2430         {
2431           if (IS_DREG ($5) && IS_UIMM ($7, 5))
2432             {
2433               notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2434               $$ = LOGI2OP ($5, uimm5 ($7), 1);
2435             }
2436           else
2437             return yyerror ("Register mismatch or value error");
2438         }
2439
2440         | IF BANG CCREG REG ASSIGN REG
2441         {
2442           if ((IS_DREG ($4) || IS_PREG ($4))
2443               && (IS_DREG ($6) || IS_PREG ($6)))
2444             {
2445               notethat ("ccMV: IF ! CC gregs = gregs\n");
2446               $$ = CCMV (&$6, &$4, 0);
2447             }
2448           else
2449             return yyerror ("Register mismatch");
2450         }
2451
2452         | IF CCREG REG ASSIGN REG
2453         {
2454           if ((IS_DREG ($5) || IS_PREG ($5))
2455               && (IS_DREG ($3) || IS_PREG ($3)))
2456             {
2457               notethat ("ccMV: IF CC gregs = gregs\n");
2458               $$ = CCMV (&$5, &$3, 1);
2459             }
2460           else
2461             return yyerror ("Register mismatch");
2462         }
2463
2464         | IF BANG CCREG JUMP expr
2465         {
2466           if (IS_PCREL10 ($5))
2467             {
2468               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2469               $$ = BRCC (0, 0, $5);
2470             }
2471           else
2472             return yyerror ("Bad jump offset");
2473         }
2474
2475         | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2476         {
2477           if (IS_PCREL10 ($5))
2478             {
2479               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2480               $$ = BRCC (0, 1, $5);
2481             }
2482           else
2483             return yyerror ("Bad jump offset");
2484         }
2485
2486         | IF CCREG JUMP expr
2487         {
2488           if (IS_PCREL10 ($4))
2489             {
2490               notethat ("BRCC: IF CC JUMP  pcrel11m2\n");
2491               $$ = BRCC (1, 0, $4);
2492             }
2493           else
2494             return yyerror ("Bad jump offset");
2495         }
2496
2497         | IF CCREG JUMP expr LPAREN BP RPAREN
2498         {
2499           if (IS_PCREL10 ($4))
2500             {
2501               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2502               $$ = BRCC (1, 1, $4);
2503             }
2504           else
2505             return yyerror ("Bad jump offset");
2506         }
2507         | NOP
2508         {
2509           notethat ("ProgCtrl: NOP\n");
2510           $$ = PROGCTRL (0, 0);
2511         }
2512
2513         | RTS
2514         {
2515           notethat ("ProgCtrl: RTS\n");
2516           $$ = PROGCTRL (1, 0);
2517         }
2518
2519         | RTI
2520         {
2521           notethat ("ProgCtrl: RTI\n");
2522           $$ = PROGCTRL (1, 1);
2523         }
2524
2525         | RTX
2526         {
2527           notethat ("ProgCtrl: RTX\n");
2528           $$ = PROGCTRL (1, 2);
2529         }
2530
2531         | RTN
2532         {
2533           notethat ("ProgCtrl: RTN\n");
2534           $$ = PROGCTRL (1, 3);
2535         }
2536
2537         | RTE
2538         {
2539           notethat ("ProgCtrl: RTE\n");
2540           $$ = PROGCTRL (1, 4);
2541         }
2542
2543         | IDLE
2544         {
2545           notethat ("ProgCtrl: IDLE\n");
2546           $$ = PROGCTRL (2, 0);
2547         }
2548
2549         | CSYNC
2550         {
2551           notethat ("ProgCtrl: CSYNC\n");
2552           $$ = PROGCTRL (2, 3);
2553         }
2554
2555         | SSYNC
2556         {
2557           notethat ("ProgCtrl: SSYNC\n");
2558           $$ = PROGCTRL (2, 4);
2559         }
2560
2561         | EMUEXCPT
2562         {
2563           notethat ("ProgCtrl: EMUEXCPT\n");
2564           $$ = PROGCTRL (2, 5);
2565         }
2566
2567         | CLI REG
2568         {
2569           if (IS_DREG ($2))
2570             {
2571               notethat ("ProgCtrl: CLI dregs\n");
2572               $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2573             }
2574           else
2575             return yyerror ("Dreg expected for CLI");
2576         }
2577
2578         | STI REG
2579         {
2580           if (IS_DREG ($2))
2581             {
2582               notethat ("ProgCtrl: STI dregs\n");
2583               $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2584             }
2585           else
2586             return yyerror ("Dreg expected for STI");
2587         }
2588
2589         | JUMP LPAREN REG RPAREN
2590         {
2591           if (IS_PREG ($3))
2592             {
2593               notethat ("ProgCtrl: JUMP (pregs )\n");
2594               $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2595             }
2596           else
2597             return yyerror ("Bad register for indirect jump");
2598         }
2599
2600         | CALL LPAREN REG RPAREN
2601         {
2602           if (IS_PREG ($3))
2603             {
2604               notethat ("ProgCtrl: CALL (pregs )\n");
2605               $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2606             }
2607           else
2608             return yyerror ("Bad register for indirect call");
2609         }
2610
2611         | CALL LPAREN PC PLUS REG RPAREN
2612         {
2613           if (IS_PREG ($5))
2614             {
2615               notethat ("ProgCtrl: CALL (PC + pregs )\n");
2616               $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2617             }
2618           else
2619             return yyerror ("Bad register for indirect call");
2620         }
2621
2622         | JUMP LPAREN PC PLUS REG RPAREN
2623         {
2624           if (IS_PREG ($5))
2625             {
2626               notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2627               $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2628             }
2629           else
2630             return yyerror ("Bad register for indirect jump");
2631         }
2632
2633         | RAISE expr
2634         {
2635           if (IS_UIMM ($2, 4))
2636             {
2637               notethat ("ProgCtrl: RAISE uimm4\n");
2638               $$ = PROGCTRL (9, uimm4 ($2));
2639             }
2640           else
2641             return yyerror ("Bad value for RAISE");
2642         }
2643
2644         | EXCPT expr
2645         {
2646                 notethat ("ProgCtrl: EMUEXCPT\n");
2647                 $$ = PROGCTRL (10, uimm4 ($2));
2648         }
2649
2650         | TESTSET LPAREN REG RPAREN
2651         {
2652           if (IS_PREG ($3))
2653             {
2654               notethat ("ProgCtrl: TESTSET (pregs )\n");
2655               $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2656             }
2657           else
2658             return yyerror ("Preg expected");
2659         }
2660
2661         | JUMP expr
2662         {
2663           if (IS_PCREL12 ($2))
2664             {
2665               notethat ("UJUMP: JUMP pcrel12\n");
2666               $$ = UJUMP ($2);
2667             }
2668           else
2669             return yyerror ("Bad value for relative jump");
2670         }
2671
2672         | JUMP_DOT_S expr
2673         {
2674           if (IS_PCREL12 ($2))
2675             {
2676               notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2677               $$ = UJUMP($2);
2678             }
2679           else
2680             return yyerror ("Bad value for relative jump");
2681         }
2682
2683         | JUMP_DOT_L expr
2684         {
2685           if (IS_PCREL24 ($2))
2686             {
2687               notethat ("CALLa: jump.l pcrel24\n");
2688               $$ = CALLA ($2, 0);
2689             }
2690           else
2691             return yyerror ("Bad value for long jump");
2692         }
2693
2694         | JUMP_DOT_L pltpc
2695         {
2696           if (IS_PCREL24 ($2))
2697             {
2698               notethat ("CALLa: jump.l pcrel24\n");
2699               $$ = CALLA ($2, 2);
2700             }
2701           else
2702             return yyerror ("Bad value for long jump");
2703         }
2704
2705         | CALL expr
2706         {
2707           if (IS_PCREL24 ($2))
2708             {
2709               notethat ("CALLa: CALL pcrel25m2\n");
2710               $$ = CALLA ($2, 1);
2711             }
2712           else
2713             return yyerror ("Bad call address");
2714         }
2715         | CALL pltpc
2716         {
2717           if (IS_PCREL24 ($2))
2718             {
2719               notethat ("CALLa: CALL pcrel25m2\n");
2720               $$ = CALLA ($2, 2);
2721             }
2722           else
2723             return yyerror ("Bad call address");
2724         }
2725
2726 /* ALU2ops.  */
2727 /* ALU2op:      DIVQ (dregs, dregs).  */
2728         | DIVQ LPAREN REG COMMA REG RPAREN
2729         {
2730           if (IS_DREG ($3) && IS_DREG ($5))
2731             $$ = ALU2OP (&$3, &$5, 8);
2732           else
2733             return yyerror ("Bad registers for DIVQ");
2734         }
2735
2736         | DIVS LPAREN REG COMMA REG RPAREN
2737         {
2738           if (IS_DREG ($3) && IS_DREG ($5))
2739             $$ = ALU2OP (&$3, &$5, 9);
2740           else
2741             return yyerror ("Bad registers for DIVS");
2742         }
2743
2744         | REG ASSIGN MINUS REG vsmod
2745         {
2746           if (IS_DREG ($1) && IS_DREG ($4))
2747             {
2748               if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2749                 {
2750                   notethat ("ALU2op: dregs = - dregs\n");
2751                   $$ = ALU2OP (&$1, &$4, 14);
2752                 }
2753               else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2754                 {
2755                   notethat ("dsp32alu: dregs = - dregs (.)\n");
2756                   $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2757                 }
2758               else
2759                 {
2760                   notethat ("dsp32alu: dregs = - dregs (.)\n");
2761                   $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2762                 }
2763             }
2764           else
2765             return yyerror ("Dregs expected");
2766         }
2767
2768         | REG ASSIGN TILDA REG
2769         {
2770           if (IS_DREG ($1) && IS_DREG ($4))
2771             {
2772               notethat ("ALU2op: dregs = ~dregs\n");
2773               $$ = ALU2OP (&$1, &$4, 15);
2774             }
2775           else
2776             return yyerror ("Dregs expected");
2777         }
2778
2779         | REG _GREATER_GREATER_ASSIGN REG
2780         {
2781           if (IS_DREG ($1) && IS_DREG ($3))
2782             {
2783               notethat ("ALU2op: dregs >>= dregs\n");
2784               $$ = ALU2OP (&$1, &$3, 1);
2785             }
2786           else
2787             return yyerror ("Dregs expected");
2788         }
2789
2790         | REG _GREATER_GREATER_ASSIGN expr
2791         {
2792           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2793             {
2794               notethat ("LOGI2op: dregs >>= uimm5\n");
2795               $$ = LOGI2OP ($1, uimm5 ($3), 6);
2796             }
2797           else
2798             return yyerror ("Dregs expected or value error");
2799         }
2800
2801         | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2802         {
2803           if (IS_DREG ($1) && IS_DREG ($3))
2804             {
2805               notethat ("ALU2op: dregs >>>= dregs\n");
2806               $$ = ALU2OP (&$1, &$3, 0);
2807             }
2808           else
2809             return yyerror ("Dregs expected");
2810         }
2811
2812         | REG _LESS_LESS_ASSIGN REG
2813         {
2814           if (IS_DREG ($1) && IS_DREG ($3))
2815             {
2816               notethat ("ALU2op: dregs <<= dregs\n");
2817               $$ = ALU2OP (&$1, &$3, 2);
2818             }
2819           else
2820             return yyerror ("Dregs expected");
2821         }
2822
2823         | REG _LESS_LESS_ASSIGN expr
2824         {
2825           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2826             {
2827               notethat ("LOGI2op: dregs <<= uimm5\n");
2828               $$ = LOGI2OP ($1, uimm5 ($3), 7);
2829             }
2830           else
2831             return yyerror ("Dregs expected or const value error");
2832         }
2833
2834
2835         | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2836         {
2837           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2838             {
2839               notethat ("LOGI2op: dregs >>>= uimm5\n");
2840               $$ = LOGI2OP ($1, uimm5 ($3), 5);
2841             }
2842           else
2843             return yyerror ("Dregs expected");
2844         }
2845
2846 /* Cache Control.  */
2847
2848         | FLUSH LBRACK REG RBRACK
2849         {
2850           notethat ("CaCTRL: FLUSH [ pregs ]\n");
2851           if (IS_PREG ($3))
2852             $$ = CACTRL (&$3, 0, 2);
2853           else
2854             return yyerror ("Bad register(s) for FLUSH");
2855         }
2856
2857         | FLUSH reg_with_postinc
2858         {
2859           if (IS_PREG ($2))
2860             {
2861               notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2862               $$ = CACTRL (&$2, 1, 2);
2863             }
2864           else
2865             return yyerror ("Bad register(s) for FLUSH");
2866         }
2867
2868         | FLUSHINV LBRACK REG RBRACK
2869         {
2870           if (IS_PREG ($3))
2871             {
2872               notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2873               $$ = CACTRL (&$3, 0, 1);
2874             }
2875           else
2876             return yyerror ("Bad register(s) for FLUSH");
2877         }
2878
2879         | FLUSHINV reg_with_postinc
2880         {
2881           if (IS_PREG ($2))
2882             {
2883               notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2884               $$ = CACTRL (&$2, 1, 1);
2885             }
2886           else
2887             return yyerror ("Bad register(s) for FLUSH");
2888         }
2889
2890 /* CaCTRL:      IFLUSH [pregs].  */
2891         | IFLUSH LBRACK REG RBRACK
2892         {
2893           if (IS_PREG ($3))
2894             {
2895               notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2896               $$ = CACTRL (&$3, 0, 3);
2897             }
2898           else
2899             return yyerror ("Bad register(s) for FLUSH");
2900         }
2901
2902         | IFLUSH reg_with_postinc
2903         {
2904           if (IS_PREG ($2))
2905             {
2906               notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2907               $$ = CACTRL (&$2, 1, 3);
2908             }
2909           else
2910             return yyerror ("Bad register(s) for FLUSH");
2911         }
2912
2913         | PREFETCH LBRACK REG RBRACK
2914         {
2915           if (IS_PREG ($3))
2916             {
2917               notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2918               $$ = CACTRL (&$3, 0, 0);
2919             }
2920           else
2921             return yyerror ("Bad register(s) for PREFETCH");
2922         }
2923
2924         | PREFETCH reg_with_postinc
2925         {
2926           if (IS_PREG ($2))
2927             {
2928               notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2929               $$ = CACTRL (&$2, 1, 0);
2930             }
2931           else
2932             return yyerror ("Bad register(s) for PREFETCH");
2933         }
2934
2935 /* LOAD/STORE.  */
2936 /* LDST:        B [ pregs <post_op> ] = dregs.  */
2937
2938         | B LBRACK REG post_op RBRACK ASSIGN REG
2939         {
2940           if (!IS_DREG ($7))
2941             return yyerror ("Dreg expected for source operand");
2942           if (!IS_PREG ($3))
2943             return yyerror ("Preg expected in address");
2944
2945           notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2946           $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2947         }
2948
2949 /* LDSTidxI:    B [ pregs + imm16 ] = dregs.  */
2950         | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2951         {
2952           Expr_Node *tmp = $5;
2953
2954           if (!IS_DREG ($8))
2955             return yyerror ("Dreg expected for source operand");
2956           if (!IS_PREG ($3))
2957             return yyerror ("Preg expected in address");
2958
2959           if (IS_RELOC ($5))
2960             return yyerror ("Plain symbol used as offset");
2961
2962           if ($4.r0)
2963             tmp = unary (Expr_Op_Type_NEG, tmp);
2964
2965           if (in_range_p (tmp, -32768, 32767, 0))
2966             {
2967               notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2968               $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2969             }
2970           else
2971             return yyerror ("Displacement out of range");
2972         }
2973
2974
2975 /* LDSTii:      W [ pregs + uimm4s2 ] = dregs.  */
2976         | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2977         {
2978           Expr_Node *tmp = $5;
2979
2980           if (!IS_DREG ($8))
2981             return yyerror ("Dreg expected for source operand");
2982           if (!IS_PREG ($3))
2983             return yyerror ("Preg expected in address");
2984
2985           if ($4.r0)
2986             tmp = unary (Expr_Op_Type_NEG, tmp);
2987
2988           if (IS_RELOC ($5))
2989             return yyerror ("Plain symbol used as offset");
2990
2991           if (in_range_p (tmp, 0, 30, 1))
2992             {
2993               notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
2994               $$ = LDSTII (&$3, &$8, tmp, 1, 1);
2995             }
2996           else if (in_range_p (tmp, -65536, 65535, 1))
2997             {
2998               notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
2999               $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3000             }
3001           else
3002             return yyerror ("Displacement out of range");
3003         }
3004
3005 /* LDST:        W [ pregs <post_op> ] = dregs.  */
3006         | W LBRACK REG post_op RBRACK ASSIGN REG
3007         {
3008           if (!IS_DREG ($7))
3009             return yyerror ("Dreg expected for source operand");
3010           if (!IS_PREG ($3))
3011             return yyerror ("Preg expected in address");
3012
3013           notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3014           $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3015         }
3016
3017         | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3018         {
3019           if (!IS_DREG ($7))
3020             return yyerror ("Dreg expected for source operand");
3021           if ($4.x0 == 2)
3022             {
3023               if (!IS_IREG ($3) && !IS_PREG ($3))
3024                 return yyerror ("Ireg or Preg expected in address");
3025             }
3026           else if (!IS_IREG ($3))
3027             return yyerror ("Ireg expected in address");
3028
3029           if (IS_IREG ($3))
3030             {
3031               notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3032               $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3033             }
3034           else
3035             {
3036               notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3037               $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3038             }
3039         }
3040
3041 /* LDSTiiFP:    [ FP - const ] = dpregs.  */
3042         | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3043         {
3044           Expr_Node *tmp = $4;
3045           int ispreg = IS_PREG ($7);
3046
3047           if (!IS_PREG ($2))
3048             return yyerror ("Preg expected in address");
3049
3050           if (!IS_DREG ($7) && !ispreg)
3051             return yyerror ("Preg expected for source operand");
3052
3053           if ($3.r0)
3054             tmp = unary (Expr_Op_Type_NEG, tmp);
3055
3056           if (IS_RELOC ($4))
3057             return yyerror ("Plain symbol used as offset");
3058
3059           if (in_range_p (tmp, 0, 63, 3))
3060             {
3061               notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3062               $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3063             }
3064           else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3065             {
3066               notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3067               tmp = unary (Expr_Op_Type_NEG, tmp);
3068               $$ = LDSTIIFP (tmp, &$7, 1);
3069             }
3070           else if (in_range_p (tmp, -131072, 131071, 3))
3071             {
3072               notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3073               $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3074             }
3075           else
3076             return yyerror ("Displacement out of range");
3077         }
3078
3079         | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3080         {
3081           Expr_Node *tmp = $7;
3082           if (!IS_DREG ($1))
3083             return yyerror ("Dreg expected for destination operand");
3084           if (!IS_PREG ($5))
3085             return yyerror ("Preg expected in address");
3086
3087           if ($6.r0)
3088             tmp = unary (Expr_Op_Type_NEG, tmp);
3089
3090           if (IS_RELOC ($7))
3091             return yyerror ("Plain symbol used as offset");
3092
3093           if (in_range_p (tmp, 0, 30, 1))
3094             {
3095               notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3096               $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3097             }
3098           else if (in_range_p (tmp, -65536, 65535, 1))
3099             {
3100               notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3101               $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3102             }
3103           else
3104             return yyerror ("Displacement out of range");
3105         }
3106
3107         | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3108         {
3109           if (!IS_DREG ($1))
3110             return yyerror ("Dreg expected for source operand");
3111           if ($6.x0 == 2)
3112             {
3113               if (!IS_IREG ($5) && !IS_PREG ($5))
3114                 return yyerror ("Ireg or Preg expected in address");
3115             }
3116           else if (!IS_IREG ($5))
3117             return yyerror ("Ireg expected in address");
3118
3119           if (IS_IREG ($5))
3120             {
3121               notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3122               $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3123             }
3124           else
3125             {
3126               notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3127               $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3128             }
3129         }
3130
3131
3132         | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3133         {
3134           if (!IS_DREG ($1))
3135             return yyerror ("Dreg expected for destination operand");
3136           if (!IS_PREG ($5))
3137             return yyerror ("Preg expected in address");
3138
3139           notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3140           $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3141         }
3142
3143         | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3144         {
3145           if (!IS_DREG ($1))
3146             return yyerror ("Dreg expected for destination operand");
3147           if (!IS_PREG ($5) || !IS_PREG ($7))
3148             return yyerror ("Preg expected in address");
3149
3150           notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3151           $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3152         }
3153
3154         | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3155         {
3156           if (!IS_DREG ($1))
3157             return yyerror ("Dreg expected for destination operand");
3158           if (!IS_PREG ($5) || !IS_PREG ($7))
3159             return yyerror ("Preg expected in address");
3160
3161           notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3162           $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3163         }
3164
3165         | LBRACK REG post_op RBRACK ASSIGN REG
3166         {
3167           if (!IS_IREG ($2) && !IS_PREG ($2))
3168             return yyerror ("Ireg or Preg expected in address");
3169           else if (IS_IREG ($2) && !IS_DREG ($6))
3170             return yyerror ("Dreg expected for source operand");
3171           else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3172             return yyerror ("Dreg or Preg expected for source operand");
3173
3174           if (IS_IREG ($2))
3175             {
3176               notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3177               $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3178             }
3179           else if (IS_DREG ($6))
3180             {
3181               notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3182               $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3183             }
3184           else
3185             {
3186               notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3187               $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3188             }
3189         }
3190
3191         | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3192         {
3193           if (!IS_DREG ($7))
3194             return yyerror ("Dreg expected for source operand");
3195
3196           if (IS_IREG ($2) && IS_MREG ($4))
3197             {
3198               notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3199               $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3200             }
3201           else if (IS_PREG ($2) && IS_PREG ($4))
3202             {
3203               notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3204               $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3205             }
3206           else
3207             return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3208         }
3209
3210         | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3211         {
3212           if (!IS_DREG ($8))
3213             return yyerror ("Dreg expected for source operand");
3214
3215           if (IS_PREG ($3) && IS_PREG ($5))
3216             {
3217               notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3218               $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3219             }
3220           else
3221             return yyerror ("Preg ++ Preg expected in address");
3222         }
3223
3224         | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3225         {
3226           Expr_Node *tmp = $7;
3227           if (!IS_DREG ($1))
3228             return yyerror ("Dreg expected for destination operand");
3229           if (!IS_PREG ($5))
3230             return yyerror ("Preg expected in address");
3231
3232           if ($6.r0)
3233             tmp = unary (Expr_Op_Type_NEG, tmp);
3234
3235           if (IS_RELOC ($7))
3236             return yyerror ("Plain symbol used as offset");
3237
3238           if (in_range_p (tmp, -32768, 32767, 0))
3239             {
3240               notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3241                        $9.r0 ? 'X' : 'Z');
3242               $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3243             }
3244           else
3245             return yyerror ("Displacement out of range");
3246         }
3247
3248         | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3249         {
3250           if (!IS_DREG ($1))
3251             return yyerror ("Dreg expected for destination operand");
3252           if (!IS_PREG ($5))
3253             return yyerror ("Preg expected in address");
3254
3255           notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3256                     $8.r0 ? 'X' : 'Z');
3257           $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3258         }
3259
3260         | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3261         {
3262           if (!IS_DREG ($1))
3263             return yyerror ("Dreg expected for destination operand");
3264
3265           if (IS_IREG ($4) && IS_MREG ($6))
3266             {
3267               notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3268               $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3269             }
3270           else if (IS_PREG ($4) && IS_PREG ($6))
3271             {
3272               notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3273               $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3274             }
3275           else
3276             return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3277         }
3278
3279         | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3280         {
3281           Expr_Node *tmp = $6;
3282           int ispreg = IS_PREG ($1);
3283           int isgot = IS_RELOC($6);
3284
3285           if (!IS_PREG ($4))
3286             return yyerror ("Preg expected in address");
3287
3288           if (!IS_DREG ($1) && !ispreg)
3289             return yyerror ("Dreg or Preg expected for destination operand");
3290
3291           if (tmp->type == Expr_Node_Reloc
3292               && strcmp (tmp->value.s_value,
3293                          "_current_shared_library_p5_offset_") != 0)
3294             return yyerror ("Plain symbol used as offset");
3295
3296           if ($5.r0)
3297             tmp = unary (Expr_Op_Type_NEG, tmp);
3298
3299           if (isgot)
3300             {
3301               notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3302               $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3303             }
3304           else if (in_range_p (tmp, 0, 63, 3))
3305             {
3306               notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3307               $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3308             }
3309           else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3310             {
3311               notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3312               tmp = unary (Expr_Op_Type_NEG, tmp);
3313               $$ = LDSTIIFP (tmp, &$1, 0);
3314             }
3315           else if (in_range_p (tmp, -131072, 131071, 3))
3316             {
3317               notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3318               $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3319
3320             }
3321           else
3322             return yyerror ("Displacement out of range");
3323         }
3324
3325         | REG ASSIGN LBRACK REG post_op RBRACK
3326         {
3327           if (!IS_IREG ($4) && !IS_PREG ($4))
3328             return yyerror ("Ireg or Preg expected in address");
3329           else if (IS_IREG ($4) && !IS_DREG ($1))
3330             return yyerror ("Dreg expected in destination operand");
3331           else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3332                    && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3333             return yyerror ("Dreg or Preg expected in destination operand");
3334
3335           if (IS_IREG ($4))
3336             {
3337               notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3338               $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3339             }
3340           else if (IS_DREG ($1))
3341             {
3342               notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3343               $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3344             }
3345           else if (IS_PREG ($1))
3346             {
3347               if (REG_SAME ($1, $4) && $5.x0 != 2)
3348                 return yyerror ("Pregs can't be same");
3349
3350               notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3351               $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3352             }
3353           else
3354             {
3355               notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3356               $$ = PUSHPOPREG (&$1, 0);
3357             }
3358         }
3359
3360
3361 /*  PushPopMultiple.  */
3362         | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3363         {
3364           if ($1.regno != REG_SP)
3365             yyerror ("Stack Pointer expected");
3366           if ($4.regno == REG_R7
3367               && IN_RANGE ($6, 0, 7)
3368               && $8.regno == REG_P5
3369               && IN_RANGE ($10, 0, 5))
3370             {
3371               notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3372               $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3373             }
3374           else
3375             return yyerror ("Bad register for PushPopMultiple");
3376         }
3377
3378         | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3379         {
3380           if ($1.regno != REG_SP)
3381             yyerror ("Stack Pointer expected");
3382
3383           if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3384             {
3385               notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3386               $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3387             }
3388           else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3389             {
3390               notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3391               $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3392             }
3393           else
3394             return yyerror ("Bad register for PushPopMultiple");
3395         }
3396
3397         | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3398         {
3399           if ($11.regno != REG_SP)
3400             yyerror ("Stack Pointer expected");
3401           if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3402               && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3403             {
3404               notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3405               $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3406             }
3407           else
3408             return yyerror ("Bad register range for PushPopMultiple");
3409         }
3410
3411         | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3412         {
3413           if ($7.regno != REG_SP)
3414             yyerror ("Stack Pointer expected");
3415
3416           if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3417             {
3418               notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3419               $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3420             }
3421           else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3422             {
3423               notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3424               $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3425             }
3426           else
3427             return yyerror ("Bad register range for PushPopMultiple");
3428         }
3429
3430         | reg_with_predec ASSIGN REG
3431         {
3432           if ($1.regno != REG_SP)
3433             yyerror ("Stack Pointer expected");
3434
3435           if (IS_ALLREG ($3))
3436             {
3437               notethat ("PushPopReg: [ -- SP ] = allregs\n");
3438               $$ = PUSHPOPREG (&$3, 1);
3439             }
3440           else
3441             return yyerror ("Bad register for PushPopReg");
3442         }
3443
3444 /* Linkage.  */
3445
3446         | LINK expr
3447         {
3448           if (IS_URANGE (16, $2, 0, 4))
3449             $$ = LINKAGE (0, uimm16s4 ($2));
3450           else
3451             return yyerror ("Bad constant for LINK");
3452         }
3453
3454         | UNLINK
3455         {
3456                 notethat ("linkage: UNLINK\n");
3457                 $$ = LINKAGE (1, 0);
3458         }
3459
3460
3461 /* LSETUP.  */
3462
3463         | LSETUP LPAREN expr COMMA expr RPAREN REG
3464         {
3465           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3466             {
3467               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3468               $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3469             }
3470           else
3471             return yyerror ("Bad register or values for LSETUP");
3472
3473         }
3474         | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3475         {
3476           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3477               && IS_PREG ($9) && IS_CREG ($7))
3478             {
3479               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3480               $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3481             }
3482           else
3483             return yyerror ("Bad register or values for LSETUP");
3484         }
3485
3486         | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3487         {
3488           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3489               && IS_PREG ($9) && IS_CREG ($7)
3490               && EXPR_VALUE ($11) == 1)
3491             {
3492               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3493               $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3494             }
3495           else
3496             return yyerror ("Bad register or values for LSETUP");
3497         }
3498
3499 /* LOOP.  */
3500         | LOOP expr REG
3501         {
3502           if (!IS_RELOC ($2))
3503             return yyerror ("Invalid expression in loop statement");
3504           if (!IS_CREG ($3))
3505             return yyerror ("Invalid loop counter register");
3506         $$ = bfin_gen_loop ($2, &$3, 0, 0);
3507         }
3508         | LOOP expr REG ASSIGN REG
3509         {
3510           if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3511             {
3512               notethat ("Loop: LOOP expr counters = pregs\n");
3513               $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3514             }
3515           else
3516             return yyerror ("Bad register or values for LOOP");
3517         }
3518         | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3519         {
3520           if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3521             {
3522               notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3523               $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3524             }
3525           else
3526             return yyerror ("Bad register or values for LOOP");
3527         }
3528 /* pseudoDEBUG.  */
3529
3530         | DBG
3531         {
3532           notethat ("pseudoDEBUG: DBG\n");
3533           $$ = bfin_gen_pseudodbg (3, 7, 0);
3534         }
3535         | DBG REG_A
3536         {
3537           notethat ("pseudoDEBUG: DBG REG_A\n");
3538           $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3539         }
3540         | DBG REG
3541         {
3542           notethat ("pseudoDEBUG: DBG allregs\n");
3543           $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3544         }
3545
3546         | DBGCMPLX LPAREN REG RPAREN
3547         {
3548           if (!IS_DREG ($3))
3549             return yyerror ("Dregs expected");
3550           notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3551           $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3552         }
3553
3554         | DBGHALT
3555         {
3556           notethat ("psedoDEBUG: DBGHALT\n");
3557           $$ = bfin_gen_pseudodbg (3, 5, 0);
3558         }
3559
3560         | DBGA LPAREN HALF_REG COMMA expr RPAREN
3561         {
3562           notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3563           $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3564         }
3565
3566         | DBGAH LPAREN REG COMMA expr RPAREN
3567         {
3568           notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3569           $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3570         }
3571
3572         | DBGAL LPAREN REG COMMA expr RPAREN
3573         {
3574           notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3575           $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3576         }
3577
3578
3579 ;
3580
3581 /*  AUX RULES.  */
3582
3583 /*  Register rules.  */
3584
3585 REG_A:  REG_A_DOUBLE_ZERO
3586         {
3587         $$ = $1;
3588         }
3589         | REG_A_DOUBLE_ONE
3590         {
3591         $$ = $1;
3592         }
3593         ;
3594
3595
3596 /*  Modifiers. */
3597
3598 opt_mode:
3599         {
3600         $$.MM = 0;
3601         $$.mod = 0;
3602         }
3603         | LPAREN M COMMA MMOD RPAREN
3604         {
3605         $$.MM = 1;
3606         $$.mod = $4;
3607         }
3608         | LPAREN MMOD COMMA M RPAREN
3609         {
3610         $$.MM = 1;
3611         $$.mod = $2;
3612         }
3613         | LPAREN MMOD RPAREN
3614         {
3615         $$.MM = 0;
3616         $$.mod = $2;
3617         }
3618         | LPAREN M RPAREN
3619         {
3620         $$.MM = 1;
3621         $$.mod = 0;
3622         }
3623         ;
3624
3625 asr_asl: LPAREN ASL RPAREN
3626         {
3627         $$.r0 = 1;
3628         }
3629         | LPAREN ASR RPAREN
3630         {
3631         $$.r0 = 0;
3632         }
3633         ;
3634
3635 sco:
3636         {
3637         $$.s0 = 0;
3638         $$.x0 = 0;
3639         }
3640         | S
3641         {
3642         $$.s0 = 1;
3643         $$.x0 = 0;
3644         }
3645         | CO
3646         {
3647         $$.s0 = 0;
3648         $$.x0 = 1;
3649         }
3650         | SCO
3651         {
3652         $$.s0 = 1;
3653         $$.x0 = 1;
3654         }
3655         ;
3656
3657 asr_asl_0:
3658         ASL
3659         {
3660         $$.r0 = 1;
3661         }
3662         | ASR
3663         {
3664         $$.r0 = 0;
3665         }
3666         ;
3667
3668 amod0:
3669         {
3670         $$.s0 = 0;
3671         $$.x0 = 0;
3672         }
3673         | LPAREN sco RPAREN
3674         {
3675         $$.s0 = $2.s0;
3676         $$.x0 = $2.x0;
3677         }
3678         ;
3679
3680 amod1:
3681         {
3682         $$.s0 = 0;
3683         $$.x0 = 0;
3684         $$.aop = 0;
3685         }
3686         | LPAREN NS RPAREN
3687         {
3688         $$.s0 = 0;
3689         $$.x0 = 0;
3690         $$.aop = 1;
3691         }
3692         | LPAREN S RPAREN
3693         {
3694         $$.s0 = 1;
3695         $$.x0 = 0;
3696         $$.aop = 1;
3697         }
3698         ;
3699
3700 amod2:
3701         {
3702         $$.r0 = 0;
3703         $$.s0 = 0;
3704         $$.x0 = 0;
3705         }
3706         | LPAREN asr_asl_0 RPAREN
3707         {
3708         $$.r0 = 2 + $2.r0;
3709         $$.s0 = 0;
3710         $$.x0 = 0;
3711         }
3712         | LPAREN sco RPAREN
3713         {
3714         $$.r0 = 0;
3715         $$.s0 = $2.s0;
3716         $$.x0 = $2.x0;
3717         }
3718         | LPAREN asr_asl_0 COMMA sco RPAREN
3719         {
3720         $$.r0 = 2 + $2.r0;
3721         $$.s0 = $4.s0;
3722         $$.x0 = $4.x0;
3723         }
3724         | LPAREN sco COMMA asr_asl_0 RPAREN
3725         {
3726         $$.r0 = 2 + $4.r0;
3727         $$.s0 = $2.s0;
3728         $$.x0 = $2.x0;
3729         }
3730         ;
3731
3732 xpmod:
3733         {
3734         $$.r0 = 0;
3735         }
3736         | LPAREN Z RPAREN
3737         {
3738         $$.r0 = 0;
3739         }
3740         | LPAREN X RPAREN
3741         {
3742         $$.r0 = 1;
3743         }
3744         ;
3745
3746 xpmod1:
3747         {
3748         $$.r0 = 0;
3749         }
3750         | LPAREN X RPAREN
3751         {
3752         $$.r0 = 0;
3753         }
3754         | LPAREN Z RPAREN
3755         {
3756         $$.r0 = 1;
3757         }
3758         ;
3759
3760 vsmod:
3761         {
3762         $$.r0 = 0;
3763         $$.s0 = 0;
3764         $$.aop = 0;
3765         }
3766         | LPAREN NS RPAREN
3767         {
3768         $$.r0 = 0;
3769         $$.s0 = 0;
3770         $$.aop = 3;
3771         }
3772         | LPAREN S RPAREN
3773         {
3774         $$.r0 = 0;
3775         $$.s0 = 1;
3776         $$.aop = 3;
3777         }
3778         | LPAREN V RPAREN
3779         {
3780         $$.r0 = 1;
3781         $$.s0 = 0;
3782         $$.aop = 3;
3783         }
3784         | LPAREN V COMMA S RPAREN
3785         {
3786         $$.r0 = 1;
3787         $$.s0 = 1;
3788         }
3789         | LPAREN S COMMA V RPAREN
3790         {
3791         $$.r0 = 1;
3792         $$.s0 = 1;
3793         }
3794         ;
3795
3796 vmod:
3797         {
3798         $$.r0 = 0;
3799         }
3800         | LPAREN V RPAREN
3801         {
3802         $$.r0 = 1;
3803         }
3804         ;
3805
3806 smod:
3807         {
3808         $$.s0 = 0;
3809         }
3810         | LPAREN S RPAREN
3811         {
3812         $$.s0 = 1;
3813         }
3814         ;
3815
3816 searchmod:
3817           GE
3818         {
3819         $$.r0 = 1;
3820         }
3821         | GT
3822         {
3823         $$.r0 = 0;
3824         }
3825         | LE
3826         {
3827         $$.r0 = 3;
3828         }
3829         | LT
3830         {
3831         $$.r0 = 2;
3832         }
3833         ;
3834
3835 aligndir:
3836         {
3837         $$.r0 = 0;
3838         }
3839         | LPAREN R RPAREN
3840         {
3841         $$.r0 = 1;
3842         }
3843         ;
3844
3845 byteop_mod:
3846         LPAREN R RPAREN
3847         {
3848         $$.r0 = 0;
3849         $$.s0 = 1;
3850         }
3851         | LPAREN MMOD RPAREN
3852         {
3853         if ($2 != M_T)
3854           return yyerror ("Bad modifier");
3855         $$.r0 = 1;
3856         $$.s0 = 0;
3857         }
3858         | LPAREN MMOD COMMA R RPAREN
3859         {
3860         if ($2 != M_T)
3861           return yyerror ("Bad modifier");
3862         $$.r0 = 1;
3863         $$.s0 = 1;
3864         }
3865         | LPAREN R COMMA MMOD RPAREN
3866         {
3867         if ($4 != M_T)
3868           return yyerror ("Bad modifier");
3869         $$.r0 = 1;
3870         $$.s0 = 1;
3871         }
3872         ;
3873
3874
3875
3876 c_align:
3877         ALIGN8
3878         {
3879         $$.r0 = 0;
3880         }
3881         | ALIGN16
3882         {
3883         $$.r0 = 1;
3884         }
3885         | ALIGN24
3886         {
3887         $$.r0 = 2;
3888         }
3889         ;
3890
3891 w32_or_nothing:
3892         {
3893         $$.r0 = 0;
3894         }
3895         | LPAREN MMOD RPAREN
3896         {
3897           if ($2 == M_W32)
3898             $$.r0 = 1;
3899           else
3900             return yyerror ("Only (W32) allowed");
3901         }
3902         ;
3903
3904 iu_or_nothing:
3905         {
3906         $$.r0 = 1;
3907         }
3908         | LPAREN MMOD RPAREN
3909         {
3910           if ($2 == M_IU)
3911             $$.r0 = 3;
3912           else
3913             return yyerror ("(IU) expected");
3914         }
3915         ;
3916
3917 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3918         {
3919         $$ = $3;
3920         }
3921         ;
3922
3923 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3924         {
3925         $$ = $2;
3926         }
3927         ;
3928
3929 /* Operators.  */
3930
3931 min_max:
3932         MIN
3933         {
3934         $$.r0 = 1;
3935         }
3936         | MAX
3937         {
3938         $$.r0 = 0;
3939         }
3940         ;
3941
3942 op_bar_op:
3943         _PLUS_BAR_PLUS
3944         {
3945         $$.r0 = 0;
3946         }
3947         | _PLUS_BAR_MINUS
3948         {
3949         $$.r0 = 1;
3950         }
3951         | _MINUS_BAR_PLUS
3952         {
3953         $$.r0 = 2;
3954         }
3955         | _MINUS_BAR_MINUS
3956         {
3957         $$.r0 = 3;
3958         }
3959         ;
3960
3961 plus_minus:
3962         PLUS
3963         {
3964         $$.r0 = 0;
3965         }
3966         | MINUS
3967         {
3968         $$.r0 = 1;
3969         }
3970         ;
3971
3972 rnd_op:
3973         LPAREN RNDH RPAREN
3974         {
3975           $$.r0 = 1;    /* HL.  */
3976           $$.s0 = 0;    /* s.  */
3977           $$.x0 = 0;    /* x.  */
3978           $$.aop = 0;   /* aop.  */
3979         }
3980
3981         | LPAREN TH RPAREN
3982         {
3983           $$.r0 = 1;    /* HL.  */
3984           $$.s0 = 0;    /* s.  */
3985           $$.x0 = 0;    /* x.  */
3986           $$.aop = 1;   /* aop.  */
3987         }
3988
3989         | LPAREN RNDL RPAREN
3990         {
3991           $$.r0 = 0;    /* HL.  */
3992           $$.s0 = 0;    /* s.  */
3993           $$.x0 = 0;    /* x.  */
3994           $$.aop = 0;   /* aop.  */
3995         }
3996
3997         | LPAREN TL RPAREN
3998         {
3999           $$.r0 = 0;    /* HL.  */
4000           $$.s0 = 0;    /* s.  */
4001           $$.x0 = 0;    /* x.  */
4002           $$.aop = 1;
4003         }
4004
4005         | LPAREN RNDH COMMA R RPAREN
4006         {
4007           $$.r0 = 1;    /* HL.  */
4008           $$.s0 = 1;    /* s.  */
4009           $$.x0 = 0;    /* x.  */
4010           $$.aop = 0;   /* aop.  */
4011         }
4012         | LPAREN TH COMMA R RPAREN
4013         {
4014           $$.r0 = 1;    /* HL.  */
4015           $$.s0 = 1;    /* s.  */
4016           $$.x0 = 0;    /* x.  */
4017           $$.aop = 1;   /* aop.  */
4018         }
4019         | LPAREN RNDL COMMA R RPAREN
4020         {
4021           $$.r0 = 0;    /* HL.  */
4022           $$.s0 = 1;    /* s.  */
4023           $$.x0 = 0;    /* x.  */
4024           $$.aop = 0;   /* aop.  */
4025         }
4026
4027         | LPAREN TL COMMA R RPAREN
4028         {
4029           $$.r0 = 0;    /* HL.  */
4030           $$.s0 = 1;    /* s.  */
4031           $$.x0 = 0;    /* x.  */
4032           $$.aop = 1;   /* aop.  */
4033         }
4034         ;
4035
4036 b3_op:
4037         LPAREN LO RPAREN
4038         {
4039           $$.s0 = 0;    /* s.  */
4040           $$.x0 = 0;    /* HL.  */
4041         }
4042         | LPAREN HI RPAREN
4043         {
4044           $$.s0 = 0;    /* s.  */
4045           $$.x0 = 1;    /* HL.  */
4046         }
4047         | LPAREN LO COMMA R RPAREN
4048         {
4049           $$.s0 = 1;    /* s.  */
4050           $$.x0 = 0;    /* HL.  */
4051         }
4052         | LPAREN HI COMMA R RPAREN
4053         {
4054           $$.s0 = 1;    /* s.  */
4055           $$.x0 = 1;    /* HL.  */
4056         }
4057         ;
4058
4059 post_op:
4060         {
4061         $$.x0 = 2;
4062         }
4063         | _PLUS_PLUS
4064         {
4065         $$.x0 = 0;
4066         }
4067         | _MINUS_MINUS
4068         {
4069         $$.x0 = 1;
4070         }
4071         ;
4072
4073 /* Assignments, Macfuncs.  */
4074
4075 a_assign:
4076         REG_A ASSIGN
4077         {
4078         $$ = $1;
4079         }
4080         ;
4081
4082 a_minusassign:
4083         REG_A _MINUS_ASSIGN
4084         {
4085         $$ = $1;
4086         }
4087         ;
4088
4089 a_plusassign:
4090         REG_A _PLUS_ASSIGN
4091         {
4092         $$ = $1;
4093         }
4094         ;
4095
4096 assign_macfunc:
4097         REG ASSIGN REG_A
4098         {
4099           if (IS_A1 ($3) && IS_EVEN ($1))
4100             return yyerror ("Cannot move A1 to even register");
4101           else if (!IS_A1 ($3) && !IS_EVEN ($1))
4102             return yyerror ("Cannot move A0 to odd register");
4103
4104           $$.w = 1;
4105           $$.P = 1;
4106           $$.n = IS_A1 ($3);
4107           $$.op = 3;
4108           $$.dst = $1;
4109           $$.s0.regno = 0;
4110           $$.s1.regno = 0;
4111         }
4112         | a_macfunc
4113         {
4114           $$ = $1;
4115           $$.w = 0; $$.P = 0;
4116           $$.dst.regno = 0;
4117         }
4118         | REG ASSIGN LPAREN a_macfunc RPAREN
4119         {
4120           if ($4.n && IS_EVEN ($1))
4121             return yyerror ("Cannot move A1 to even register");
4122           else if (!$4.n && !IS_EVEN ($1))
4123             return yyerror ("Cannot move A0 to odd register");
4124
4125           $$ = $4;
4126           $$.w = 1;
4127           $$.P = 1;
4128           $$.dst = $1;
4129         }
4130
4131         | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4132         {
4133           if ($4.n && !IS_H ($1))
4134             return yyerror ("Cannot move A1 to low half of register");
4135           else if (!$4.n && IS_H ($1))
4136             return yyerror ("Cannot move A0 to high half of register");
4137
4138           $$ = $4;
4139           $$.w = 1;
4140           $$.P = 0;
4141           $$.dst = $1;
4142         }
4143
4144         | HALF_REG ASSIGN REG_A
4145         {
4146           if (IS_A1 ($3) && !IS_H ($1))
4147             return yyerror ("Cannot move A1 to low half of register");
4148           else if (!IS_A1 ($3) && IS_H ($1))
4149             return yyerror ("Cannot move A0 to high half of register");
4150
4151           $$.w = 1;
4152           $$.P = 0;
4153           $$.n = IS_A1 ($3);
4154           $$.op = 3;
4155           $$.dst = $1;
4156           $$.s0.regno = 0;
4157           $$.s1.regno = 0;
4158         }
4159         ;
4160
4161 a_macfunc:
4162         a_assign multiply_halfregs
4163         {
4164           $$.n = IS_A1 ($1);
4165           $$.op = 0;
4166           $$.s0 = $2.s0;
4167           $$.s1 = $2.s1;
4168         }
4169         | a_plusassign multiply_halfregs
4170         {
4171           $$.n = IS_A1 ($1);
4172           $$.op = 1;
4173           $$.s0 = $2.s0;
4174           $$.s1 = $2.s1;
4175         }
4176         | a_minusassign multiply_halfregs
4177         {
4178           $$.n = IS_A1 ($1);
4179           $$.op = 2;
4180           $$.s0 = $2.s0;
4181           $$.s1 = $2.s1;
4182         }
4183         ;
4184
4185 multiply_halfregs:
4186         HALF_REG STAR HALF_REG
4187         {
4188           if (IS_DREG ($1) && IS_DREG ($3))
4189             {
4190               $$.s0 = $1;
4191               $$.s1 = $3;
4192             }
4193           else
4194             return yyerror ("Dregs expected");
4195         }
4196         ;
4197
4198 cc_op:
4199         ASSIGN
4200         {
4201         $$.r0 = 0;
4202         }
4203         | _BAR_ASSIGN
4204         {
4205         $$.r0 = 1;
4206         }
4207         | _AMPERSAND_ASSIGN
4208         {
4209         $$.r0 = 2;
4210         }
4211         | _CARET_ASSIGN
4212         {
4213         $$.r0 = 3;
4214         }
4215         ;
4216
4217 ccstat:
4218         CCREG cc_op STATUS_REG
4219         {
4220         $$.r0 = $3.regno;
4221         $$.x0 = $2.r0;
4222         $$.s0 = 0;
4223         }
4224         | CCREG cc_op V
4225         {
4226         $$.r0 = 0x18;
4227         $$.x0 = $2.r0;
4228         $$.s0 = 0;
4229         }
4230         | STATUS_REG cc_op CCREG
4231         {
4232         $$.r0 = $1.regno;
4233         $$.x0 = $2.r0;
4234         $$.s0 = 1;
4235         }
4236         | V cc_op CCREG
4237         {
4238         $$.r0 = 0x18;
4239         $$.x0 = $2.r0;
4240         $$.s0 = 1;
4241         }
4242         ;
4243
4244 /* Expressions and Symbols.  */
4245
4246 symbol: SYMBOL
4247         {
4248         Expr_Node_Value val;
4249         val.s_value = S_GET_NAME($1);
4250         $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4251         }
4252         ;
4253
4254 any_gotrel:
4255         GOT
4256         { $$ = BFD_RELOC_BFIN_GOT; }
4257         | GOT17M4
4258         { $$ = BFD_RELOC_BFIN_GOT17M4; }
4259         | FUNCDESC_GOT17M4
4260         { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4261         ;
4262
4263 got:    symbol AT any_gotrel
4264         {
4265         Expr_Node_Value val;
4266         val.i_value = $3;
4267         $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4268         }
4269         ;
4270
4271 got_or_expr:    got
4272         {
4273         $$ = $1;
4274         }
4275         | expr
4276         {
4277         $$ = $1;
4278         }
4279         ;
4280
4281 pltpc :
4282         symbol AT PLTPC
4283         {
4284         $$ = $1;
4285         }
4286         ;
4287
4288 eterm: NUMBER
4289         {
4290         Expr_Node_Value val;
4291         val.i_value = $1;
4292         $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4293         }
4294         | symbol
4295         {
4296         $$ = $1;
4297         }
4298         | LPAREN expr_1 RPAREN
4299         {
4300         $$ = $2;
4301         }
4302         | TILDA expr_1
4303         {
4304         $$ = unary (Expr_Op_Type_COMP, $2);
4305         }
4306         | MINUS expr_1 %prec TILDA
4307         {
4308         $$ = unary (Expr_Op_Type_NEG, $2);
4309         }
4310         ;
4311
4312 expr: expr_1
4313         {
4314         $$ = $1;
4315         }
4316         ;
4317
4318 expr_1: expr_1 STAR expr_1
4319         {
4320         $$ = binary (Expr_Op_Type_Mult, $1, $3);
4321         }
4322         | expr_1 SLASH expr_1
4323         {
4324         $$ = binary (Expr_Op_Type_Div, $1, $3);
4325         }
4326         | expr_1 PERCENT expr_1
4327         {
4328         $$ = binary (Expr_Op_Type_Mod, $1, $3);
4329         }
4330         | expr_1 PLUS expr_1
4331         {
4332         $$ = binary (Expr_Op_Type_Add, $1, $3);
4333         }
4334         | expr_1 MINUS expr_1
4335         {
4336         $$ = binary (Expr_Op_Type_Sub, $1, $3);
4337         }
4338         | expr_1 LESS_LESS expr_1
4339         {
4340         $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4341         }
4342         | expr_1 GREATER_GREATER expr_1
4343         {
4344         $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4345         }
4346         | expr_1 AMPERSAND expr_1
4347         {
4348         $$ = binary (Expr_Op_Type_BAND, $1, $3);
4349         }
4350         | expr_1 CARET expr_1
4351         {
4352         $$ = binary (Expr_Op_Type_LOR, $1, $3);
4353         }
4354         | expr_1 BAR expr_1
4355         {
4356         $$ = binary (Expr_Op_Type_BOR, $1, $3);
4357         }
4358         | eterm
4359         {
4360         $$ = $1;
4361         }
4362         ;
4363
4364
4365 %%
4366
4367 EXPR_T
4368 mkexpr (int x, SYMBOL_T s)
4369 {
4370   EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4371   e->value = x;
4372   EXPR_SYMBOL(e) = s;
4373   return e;
4374 }
4375
4376 static int
4377 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4378 {
4379   long umax = (1L << sz) - 1;
4380   long min = -1L << (sz - 1);
4381   long max = (1L << (sz - 1)) - 1;
4382
4383   long v = EXPR_VALUE (expr);
4384
4385   if ((v % mul) != 0)
4386     {
4387       error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4388       return 0;
4389     }
4390
4391   v /= mul;
4392
4393   if (sign)
4394     v = -v;
4395
4396   if (issigned)
4397     {
4398       if (v >= min && v <= max) return 1;
4399
4400 #ifdef DEBUG
4401       fprintf(stderr, "signed value %lx out of range\n", v * mul);
4402 #endif
4403       return 0;
4404     }
4405   if (v <= umax && v >= 0)
4406     return 1;
4407 #ifdef DEBUG
4408   fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4409 #endif
4410   return 0;
4411 }
4412
4413 /* Return the expression structure that allows symbol operations.
4414    If the left and right children are constants, do the operation.  */
4415 static Expr_Node *
4416 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4417 {
4418   Expr_Node_Value val;
4419
4420   if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4421     {
4422       switch (op)
4423         {
4424         case Expr_Op_Type_Add:
4425           x->value.i_value += y->value.i_value;
4426           break;
4427         case Expr_Op_Type_Sub:
4428           x->value.i_value -= y->value.i_value;
4429           break;
4430         case Expr_Op_Type_Mult:
4431           x->value.i_value *= y->value.i_value;
4432           break;
4433         case Expr_Op_Type_Div:
4434           if (y->value.i_value == 0)
4435             error ("Illegal Expression:  Division by zero.");
4436           else
4437             x->value.i_value /= y->value.i_value;
4438           break;
4439         case Expr_Op_Type_Mod:
4440           x->value.i_value %= y->value.i_value;
4441           break;
4442         case Expr_Op_Type_Lshift:
4443           x->value.i_value <<= y->value.i_value;
4444           break;
4445         case Expr_Op_Type_Rshift:
4446           x->value.i_value >>= y->value.i_value;
4447           break;
4448         case Expr_Op_Type_BAND:
4449           x->value.i_value &= y->value.i_value;
4450           break;
4451         case Expr_Op_Type_BOR:
4452           x->value.i_value |= y->value.i_value;
4453           break;
4454         case Expr_Op_Type_BXOR:
4455           x->value.i_value ^= y->value.i_value;
4456           break;
4457         case Expr_Op_Type_LAND:
4458           x->value.i_value = x->value.i_value && y->value.i_value;
4459           break;
4460         case Expr_Op_Type_LOR:
4461           x->value.i_value = x->value.i_value || y->value.i_value;
4462           break;
4463
4464         default:
4465           error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4466         }
4467       return x;
4468     }
4469   /* Canonicalize order to EXPR OP CONSTANT.  */
4470   if (x->type == Expr_Node_Constant)
4471     {
4472       Expr_Node *t = x;
4473       x = y;
4474       y = t;
4475     }
4476   /* Canonicalize subtraction of const to addition of negated const.  */
4477   if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4478     {
4479       op = Expr_Op_Type_Add;
4480       y->value.i_value = -y->value.i_value;
4481     }
4482   if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4483       && x->Right_Child->type == Expr_Node_Constant)
4484     {
4485       if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4486         {
4487           x->Right_Child->value.i_value += y->value.i_value;
4488           return x;
4489         }
4490     }
4491
4492   /* Create a new expression structure.  */
4493   val.op_value = op;
4494   return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4495 }
4496
4497 static Expr_Node *
4498 unary (Expr_Op_Type op, Expr_Node *x)
4499 {
4500   if (x->type == Expr_Node_Constant)
4501     {
4502       switch (op)
4503         {
4504         case Expr_Op_Type_NEG:
4505           x->value.i_value = -x->value.i_value;
4506           break;
4507         case Expr_Op_Type_COMP:
4508           x->value.i_value = ~x->value.i_value;
4509           break;
4510         default:
4511           error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4512         }
4513       return x;
4514     }
4515   else
4516     {
4517       /* Create a new expression structure.  */
4518       Expr_Node_Value val;
4519       val.op_value = op;
4520       return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4521     }
4522 }
4523
4524 int debug_codeselection = 0;
4525 static void
4526 notethat (char *format, ...)
4527 {
4528   va_list ap;
4529   va_start (ap, format);
4530   if (debug_codeselection)
4531     {
4532       vfprintf (errorf, format, ap);
4533     }
4534   va_end (ap);
4535 }
4536
4537 #ifdef TEST
4538 main (int argc, char **argv)
4539 {
4540   yyparse();
4541 }
4542 #endif
4543