projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
* config/bfin-defs.h (IS_BREG, IS_LREG): New macros.
[deliverable/binutils-gdb.git] / gas / config / bfin-parse.y
1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21 %{
22
23 #include <stdio.h>
24 #include "bfin-aux.h"
25 #include <stdarg.h>
26 #include <obstack.h>
27
28 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
29 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
30
31 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
32 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
33 dst, src0, src1, w0)
34
35 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
36 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
37 dst, src0, src1, w0)
38
39 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
40 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
41
42 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
43 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
44
45 #define LDIMMHALF_R(reg, h, s, z, hword) \
46 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
47
48 #define LDIMMHALF_R5(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
50
51 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
52 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
53
54 #define LDST(ptr, reg, aop, sz, z, w) \
55 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
56
57 #define LDSTII(ptr, reg, offset, w, op) \
58 bfin_gen_ldstii (ptr, reg, offset, w, op)
59
60 #define DSPLDST(i, m, reg, aop, w) \
61 bfin_gen_dspldst (i, reg, aop, w, m)
62
63 #define LDSTPMOD(ptr, reg, idx, aop, w) \
64 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
65
66 #define LDSTIIFP(offset, reg, w) \
67 bfin_gen_ldstiifp (reg, offset, w)
68
69 #define LOGI2OP(dst, src, opc) \
70 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
71
72 #define ALU2OP(dst, src, opc) \
73 bfin_gen_alu2op (dst, src, opc)
74
75 #define BRCC(t, b, offset) \
76 bfin_gen_brcc (t, b, offset)
77
78 #define UJUMP(offset) \
79 bfin_gen_ujump (offset)
80
81 #define PROGCTRL(prgfunc, poprnd) \
82 bfin_gen_progctrl (prgfunc, poprnd)
83
84 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
85 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
86
87 #define PUSHPOPREG(reg, w) \
88 bfin_gen_pushpopreg (reg, w)
89
90 #define CALLA(addr, s) \
91 bfin_gen_calla (addr, s)
92
93 #define LINKAGE(r, framesize) \
94 bfin_gen_linkage (r, framesize)
95
96 #define COMPI2OPD(dst, src, op) \
97 bfin_gen_compi2opd (dst, src, op)
98
99 #define COMPI2OPP(dst, src, op) \
100 bfin_gen_compi2opp (dst, src, op)
101
102 #define DAGMODIK(i, op) \
103 bfin_gen_dagmodik (i, op)
104
105 #define DAGMODIM(i, m, op, br) \
106 bfin_gen_dagmodim (i, m, op, br)
107
108 #define COMP3OP(dst, src0, src1, opc) \
109 bfin_gen_comp3op (src0, src1, dst, opc)
110
111 #define PTR2OP(dst, src, opc) \
112 bfin_gen_ptr2op (dst, src, opc)
113
114 #define CCFLAG(x, y, opc, i, g) \
115 bfin_gen_ccflag (x, y, opc, i, g)
116
117 #define CCMV(src, dst, t) \
118 bfin_gen_ccmv (src, dst, t)
119
120 #define CACTRL(reg, a, op) \
121 bfin_gen_cactrl (reg, a, op)
122
123 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
124 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
125
126 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
127 #define IS_RANGE(bits, expr, sign, mul) \
128 value_match(expr, bits, sign, mul, 1)
129 #define IS_URANGE(bits, expr, sign, mul) \
130 value_match(expr, bits, sign, mul, 0)
131 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
132 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
133 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
134 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
135
136 #define IS_PCREL4(expr) \
137 (value_match (expr, 4, 0, 2, 0))
138
139 #define IS_LPPCREL10(expr) \
140 (value_match (expr, 10, 0, 2, 0))
141
142 #define IS_PCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 1))
144
145 #define IS_PCREL12(expr) \
146 (value_match (expr, 12, 0, 2, 1))
147
148 #define IS_PCREL24(expr) \
149 (value_match (expr, 24, 0, 2, 1))
150
151
152 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
153
154 extern FILE *errorf;
155 extern INSTR_T insn;
156
157 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
158 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
159
160 static void notethat (char *format, ...);
161
162 char *current_inputline;
163 extern char *yytext;
164 int yyerror (char *msg);
165
166 void error (char *format, ...)
167 {
168 va_list ap;
169 char buffer[2000];
170
171 va_start (ap, format);
172 vsprintf (buffer, format, ap);
173 va_end (ap);
174
175 as_bad (buffer);
176 }
177
178 int
179 yyerror (char *msg)
180 {
181 if (msg[0] == '\0')
182 error ("%s", msg);
183
184 else if (yytext[0] != ';')
185 error ("%s. Input text was %s.", msg, yytext);
186 else
187 error ("%s.", msg);
188
189 return -1;
190 }
191
192 static int
193 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
194 {
195 int val = EXPR_VALUE (expr);
196 if (expr->type != Expr_Node_Constant)
197 return 0;
198 if (val < from || val > to)
199 return 0;
200 return (val & mask) == 0;
201 }
202
203 extern int yylex (void);
204
205 #define imm3(x) EXPR_VALUE (x)
206 #define imm4(x) EXPR_VALUE (x)
207 #define uimm4(x) EXPR_VALUE (x)
208 #define imm5(x) EXPR_VALUE (x)
209 #define uimm5(x) EXPR_VALUE (x)
210 #define imm6(x) EXPR_VALUE (x)
211 #define imm7(x) EXPR_VALUE (x)
212 #define imm16(x) EXPR_VALUE (x)
213 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
214 #define uimm16(x) EXPR_VALUE (x)
215
216 /* Return true if a value is inside a range. */
217 #define IN_RANGE(x, low, high) \
218 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
219
220 /* Auxiliary functions. */
221
222 static void
223 neg_value (Expr_Node *expr)
224 {
225 expr->value.i_value = -expr->value.i_value;
226 }
227
228 static int
229 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
230 {
231 if (!IS_DREG (*reg1))
232 {
233 yyerror ("Dregs expected");
234 return 0;
235 }
236
237 if (reg1->regno != 1 && reg1->regno != 3)
238 {
239 yyerror ("Bad register pair");
240 return 0;
241 }
242
243 if (imm7 (reg2) != reg1->regno - 1)
244 {
245 yyerror ("Bad register pair");
246 return 0;
247 }
248
249 reg1->regno--;
250 return 1;
251 }
252
253 static int
254 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
255 {
256 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
257 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
258 return yyerror ("Source multiplication register mismatch");
259
260 return 0;
261 }
262
263
264 /* Check (vector) mac funcs and ops. */
265
266 static int
267 check_macfuncs (Macfunc *aa, Opt_mode *opa,
268 Macfunc *ab, Opt_mode *opb)
269 {
270 /* Variables for swapping. */
271 Macfunc mtmp;
272 Opt_mode otmp;
273
274 /* If a0macfunc comes before a1macfunc, swap them. */
275
276 if (aa->n == 0)
277 {
278 /* (M) is not allowed here. */
279 if (opa->MM != 0)
280 return yyerror ("(M) not allowed with A0MAC");
281 if (ab->n != 1)
282 return yyerror ("Vector AxMACs can't be same");
283
284 mtmp = *aa; *aa = *ab; *ab = mtmp;
285 otmp = *opa; *opa = *opb; *opb = otmp;
286 }
287 else
288 {
289 if (opb->MM != 0)
290 return yyerror ("(M) not allowed with A0MAC");
291 if (opa->mod != 0)
292 return yyerror ("Bad opt mode");
293 if (ab->n != 0)
294 return yyerror ("Vector AxMACs can't be same");
295 }
296
297 /* If both ops are != 3, we have multiply_halfregs in both
298 assignment_or_macfuncs. */
299 if (aa->op == ab->op && aa->op != 3)
300 {
301 if (check_multiply_halfregs (aa, ab) < 0)
302 return -1;
303 }
304 else
305 {
306 /* Only one of the assign_macfuncs has a half reg multiply
307 Evil trick: Just 'OR' their source register codes:
308 We can do that, because we know they were initialized to 0
309 in the rules that don't use multiply_halfregs. */
310 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
311 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
312 }
313
314 if (aa->w == ab->w && aa->P != ab->P)
315 {
316 return yyerror ("macfuncs must differ");
317 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
318 return yyerror ("Destination Dregs must differ by one");
319 }
320 /* We assign to full regs, thus obey even/odd rules. */
321 else if ((aa->w && aa->P && IS_EVEN (aa->dst))
322 || (ab->w && ab->P && !IS_EVEN (ab->dst)))
323 return yyerror ("Even/Odd register assignment mismatch");
324 /* We assign to half regs, thus obey hi/low rules. */
325 else if ( (aa->w && !aa->P && !IS_H (aa->dst))
326 || (ab->w && !aa->P && IS_H (ab->dst)))
327 return yyerror ("High/Low register assignment mismatch");
328
329 /* Make sure first macfunc has got both P flags ORed. */
330 aa->P |= ab->P;
331
332 /* Make sure mod flags get ORed, too. */
333 opb->mod |= opa->mod;
334 return 0;
335 }
336
337
338 static int
339 is_group1 (INSTR_T x)
340 {
341 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
342 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
343 return 1;
344
345 return 0;
346 }
347
348 static int
349 is_group2 (INSTR_T x)
350 {
351 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
352 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
353 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
354 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
355 || (x->value == 0x0000))
356 return 1;
357 return 0;
358 }
359
360 %}
361
362 %union {
363 INSTR_T instr;
364 Expr_Node *expr;
365 SYMBOL_T symbol;
366 long value;
367 Register reg;
368 Macfunc macfunc;
369 struct { int r0; int s0; int x0; int aop; } modcodes;
370 struct { int r0; } r0;
371 Opt_mode mod;
372 }
373
374
375 /* Tokens. */
376
377 /* Vector Specific. */
378 %token BYTEOP16P BYTEOP16M
379 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
380 %token BYTEUNPACK BYTEPACK
381 %token PACK
382 %token SAA
383 %token ALIGN8 ALIGN16 ALIGN24
384 %token VIT_MAX
385 %token EXTRACT DEPOSIT EXPADJ SEARCH
386 %token ONES SIGN SIGNBITS
387
388 /* Stack. */
389 %token LINK UNLINK
390
391 /* Registers. */
392 %token REG
393 %token PC
394 %token CCREG BYTE_DREG
395 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
396 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
397 %token HALF_REG
398
399 /* Progctrl. */
400 %token NOP
401 %token RTI RTS RTX RTN RTE
402 %token HLT IDLE
403 %token STI CLI
404 %token CSYNC SSYNC
405 %token EMUEXCPT
406 %token RAISE EXCPT
407 %token LSETUP
408 %token LOOP
409 %token LOOP_BEGIN
410 %token LOOP_END
411 %token DISALGNEXCPT
412 %token JUMP JUMP_DOT_S JUMP_DOT_L
413 %token CALL
414
415 /* Emulator only. */
416 %token ABORT
417
418 /* Operators. */
419 %token NOT TILDA BANG
420 %token AMPERSAND BAR
421 %token PERCENT
422 %token CARET
423 %token BXOR
424
425 %token MINUS PLUS STAR SLASH
426 %token NEG
427 %token MIN MAX ABS
428 %token DOUBLE_BAR
429 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
430 %token _MINUS_MINUS _PLUS_PLUS
431
432 /* Shift/rotate ops. */
433 %token SHIFT LSHIFT ASHIFT BXORSHIFT
434 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
435 %token ROT
436 %token LESS_LESS GREATER_GREATER
437 %token _GREATER_GREATER_GREATER
438 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
439 %token DIVS DIVQ
440
441 /* In place operators. */
442 %token ASSIGN _STAR_ASSIGN
443 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
444 %token _MINUS_ASSIGN _PLUS_ASSIGN
445
446 /* Assignments, comparisons. */
447 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
448 %token GE LT LE GT
449 %token LESS_THAN
450
451 /* Cache. */
452 %token FLUSHINV FLUSH
453 %token IFLUSH PREFETCH
454
455 /* Misc. */
456 %token PRNT
457 %token OUTC
458 %token WHATREG
459 %token TESTSET
460
461 /* Modifiers. */
462 %token ASL ASR
463 %token B W
464 %token NS S CO SCO
465 %token TH TL
466 %token BP
467 %token BREV
468 %token X Z
469 %token M MMOD
470 %token R RND RNDL RNDH RND12 RND20
471 %token V
472 %token LO HI
473
474 /* Bit ops. */
475 %token BITTGL BITCLR BITSET BITTST BITMUX
476
477 /* Debug. */
478 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
479
480 /* Semantic auxiliaries. */
481
482 %token IF COMMA BY
483 %token COLON SEMICOLON
484 %token RPAREN LPAREN LBRACK RBRACK
485 %token STATUS_REG
486 %token MNOP
487 %token SYMBOL NUMBER
488 %token GOT AT PLTPC
489
490 /* Types. */
491 %type <instr> asm
492 %type <value> MMOD
493 %type <mod> opt_mode
494
495 %type <value> NUMBER
496 %type <r0> aligndir
497 %type <modcodes> byteop_mod
498 %type <reg> a_assign
499 %type <reg> a_plusassign
500 %type <reg> a_minusassign
501 %type <macfunc> multiply_halfregs
502 %type <macfunc> assign_macfunc
503 %type <macfunc> a_macfunc
504 %type <expr> expr_1
505 %type <instr> asm_1
506 %type <r0> vmod
507 %type <modcodes> vsmod
508 %type <modcodes> ccstat
509 %type <r0> cc_op
510 %type <reg> CCREG
511 %type <reg> reg_with_postinc
512 %type <reg> reg_with_predec
513
514 %type <r0> searchmod
515 %type <expr> symbol
516 %type <symbol> SYMBOL
517 %type <expr> eterm
518 %type <reg> REG
519 %type <reg> BYTE_DREG
520 %type <reg> REG_A_DOUBLE_ZERO
521 %type <reg> REG_A_DOUBLE_ONE
522 %type <reg> REG_A
523 %type <reg> STATUS_REG
524 %type <expr> expr
525 %type <r0> xpmod
526 %type <r0> xpmod1
527 %type <modcodes> smod
528 %type <modcodes> b3_op
529 %type <modcodes> rnd_op
530 %type <modcodes> post_op
531 %type <reg> HALF_REG
532 %type <r0> iu_or_nothing
533 %type <r0> plus_minus
534 %type <r0> asr_asl
535 %type <r0> asr_asl_0
536 %type <modcodes> sco
537 %type <modcodes> amod0
538 %type <modcodes> amod1
539 %type <modcodes> amod2
540 %type <r0> op_bar_op
541 %type <r0> w32_or_nothing
542 %type <r0> c_align
543 %type <r0> min_max
544 %type <expr> got
545 %type <expr> got_or_expr
546 %type <expr> pltpc
547
548
549 /* Precedence rules. */
550 %left BAR
551 %left CARET
552 %left AMPERSAND
553 %left LESS_LESS GREATER_GREATER
554 %left PLUS MINUS
555 %left STAR SLASH PERCENT
556
557 %right ASSIGN
558
559 %right TILDA BANG
560 %start statement
561 %%
562 statement:
563 | asm
564 {
565 insn = $1;
566 if (insn == (INSTR_T) 0)
567 return NO_INSN_GENERATED;
568 else if (insn == (INSTR_T) - 1)
569 return SEMANTIC_ERROR;
570 else
571 return INSN_GENERATED;
572 }
573 ;
574
575 asm: asm_1 SEMICOLON
576 /* Parallel instructions. */
577 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
578 {
579 if (($1->value & 0xf800) == 0xc000)
580 {
581 if (is_group1 ($3) && is_group2 ($5))
582 $$ = bfin_gen_multi_instr ($1, $3, $5);
583 else if (is_group2 ($3) && is_group1 ($5))
584 $$ = bfin_gen_multi_instr ($1, $5, $3);
585 else
586 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
587 }
588 else if (($3->value & 0xf800) == 0xc000)
589 {
590 if (is_group1 ($1) && is_group2 ($5))
591 $$ = bfin_gen_multi_instr ($3, $1, $5);
592 else if (is_group2 ($1) && is_group1 ($5))
593 $$ = bfin_gen_multi_instr ($3, $5, $1);
594 else
595 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
596 }
597 else if (($5->value & 0xf800) == 0xc000)
598 {
599 if (is_group1 ($1) && is_group2 ($3))
600 $$ = bfin_gen_multi_instr ($5, $1, $3);
601 else if (is_group2 ($1) && is_group1 ($3))
602 $$ = bfin_gen_multi_instr ($5, $3, $1);
603 else
604 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
605 }
606 else
607 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
608 }
609
610 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
611 {
612 if (($1->value & 0xf800) == 0xc000)
613 {
614 if (is_group1 ($3))
615 $$ = bfin_gen_multi_instr ($1, $3, 0);
616 else if (is_group2 ($3))
617 $$ = bfin_gen_multi_instr ($1, 0, $3);
618 else
619 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
620 }
621 else if (($3->value & 0xf800) == 0xc000)
622 {
623 if (is_group1 ($1))
624 $$ = bfin_gen_multi_instr ($3, $1, 0);
625 else if (is_group2 ($1))
626 $$ = bfin_gen_multi_instr ($3, 0, $1);
627 else
628 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
629 }
630 else if (is_group1 ($1) && is_group2 ($3))
631 $$ = bfin_gen_multi_instr (0, $1, $3);
632 else if (is_group2 ($1) && is_group1 ($3))
633 $$ = bfin_gen_multi_instr (0, $3, $1);
634 else
635 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
636 }
637 | error
638 {
639 $$ = 0;
640 yyerror ("");
641 yyerrok;
642 }
643 ;
644
645 /* DSPMAC. */
646
647 asm_1:
648 MNOP
649 {
650 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
651 }
652 | assign_macfunc opt_mode
653 {
654 int op0, op1;
655 int w0 = 0, w1 = 0;
656 int h00, h10, h01, h11;
657
658 if ($1.n == 0)
659 {
660 if ($2.MM)
661 return yyerror ("(m) not allowed with a0 unit");
662 op1 = 3;
663 op0 = $1.op;
664 w1 = 0;
665 w0 = $1.w;
666 h00 = IS_H ($1.s0);
667 h10 = IS_H ($1.s1);
668 h01 = h11 = 0;
669 }
670 else
671 {
672 op1 = $1.op;
673 op0 = 3;
674 w1 = $1.w;
675 w0 = 0;
676 h00 = h10 = 0;
677 h01 = IS_H ($1.s0);
678 h11 = IS_H ($1.s1);
679 }
680 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
681 &$1.dst, op0, &$1.s0, &$1.s1, w0);
682 }
683
684
685 /* VECTOR MACs. */
686
687 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
688 {
689 Register *dst;
690
691 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
692 return -1;
693 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
694
695 if ($1.w)
696 dst = &$1.dst;
697 else
698 dst = &$4.dst;
699
700 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
701 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
702 dst, $4.op, &$1.s0, &$1.s1, $4.w);
703 }
704
705 /* DSPALU. */
706
707 | DISALGNEXCPT
708 {
709 notethat ("dsp32alu: DISALGNEXCPT\n");
710 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
711 }
712 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
713 {
714 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
715 {
716 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
717 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
718 }
719 else
720 return yyerror ("Register mismatch");
721 }
722 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
723 {
724 if (!IS_A1 ($4) && IS_A1 ($5))
725 {
726 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
727 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
728 }
729 else
730 return yyerror ("Register mismatch");
731 }
732 | A_ZERO_DOT_H ASSIGN HALF_REG
733 {
734 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
735 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
736 }
737 | A_ONE_DOT_H ASSIGN HALF_REG
738 {
739 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
740 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
741 }
742 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
743 COLON expr COMMA REG COLON expr RPAREN aligndir
744 {
745 if (!IS_DREG ($2) || !IS_DREG ($4))
746 return yyerror ("Dregs expected");
747 else if (!valid_dreg_pair (&$9, $11))
748 return yyerror ("Bad dreg pair");
749 else if (!valid_dreg_pair (&$13, $15))
750 return yyerror ("Bad dreg pair");
751 else
752 {
753 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
754 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
755 }
756 }
757
758 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
759 REG COLON expr RPAREN aligndir
760 {
761 if (!IS_DREG ($2) || !IS_DREG($4))
762 return yyerror ("Dregs expected");
763 else if (!valid_dreg_pair (&$9, $11))
764 return yyerror ("Bad dreg pair");
765 else if (!valid_dreg_pair (&$13, $15))
766 return yyerror ("Bad dreg pair");
767 else
768 {
769 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
770 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
771 }
772 }
773
774 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
775 {
776 if (!IS_DREG ($2) || !IS_DREG ($4))
777 return yyerror ("Dregs expected");
778 else if (!valid_dreg_pair (&$8, $10))
779 return yyerror ("Bad dreg pair");
780 else
781 {
782 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
783 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
784 }
785 }
786 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
787 {
788 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
789 {
790 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
791 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
792 }
793 else
794 return yyerror ("Register mismatch");
795 }
796 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
797 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
798 {
799 if (IS_DREG ($1) && IS_DREG ($7))
800 {
801 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
802 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
803 }
804 else
805 return yyerror ("Register mismatch");
806 }
807
808
809 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
810 {
811 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
812 && IS_A1 ($9) && !IS_A1 ($11))
813 {
814 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
815 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
816
817 }
818 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
819 && !IS_A1 ($9) && IS_A1 ($11))
820 {
821 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
822 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
823 }
824 else
825 return yyerror ("Register mismatch");
826 }
827
828 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
829 {
830 if ($4.r0 == $10.r0)
831 return yyerror ("Operators must differ");
832
833 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
834 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
835 {
836 notethat ("dsp32alu: dregs = dregs + dregs,"
837 "dregs = dregs - dregs (amod1)\n");
838 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
839 }
840 else
841 return yyerror ("Register mismatch");
842 }
843
844 /* Bar Operations. */
845
846 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
847 {
848 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
849 return yyerror ("Differing source registers");
850
851 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
852 return yyerror ("Dregs expected");
853
854
855 if ($4.r0 == 1 && $10.r0 == 2)
856 {
857 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
858 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
859 }
860 else if ($4.r0 == 0 && $10.r0 == 3)
861 {
862 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
863 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
864 }
865 else
866 return yyerror ("Bar operand mismatch");
867 }
868
869 | REG ASSIGN ABS REG vmod
870 {
871 int op;
872
873 if (IS_DREG ($1) && IS_DREG ($4))
874 {
875 if ($5.r0)
876 {
877 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
878 op = 6;
879 }
880 else
881 {
882 /* Vector version of ABS. */
883 notethat ("dsp32alu: dregs = ABS dregs\n");
884 op = 7;
885 }
886 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
887 }
888 else
889 return yyerror ("Dregs expected");
890 }
891 | a_assign ABS REG_A
892 {
893 notethat ("dsp32alu: Ax = ABS Ax\n");
894 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
895 }
896 | A_ZERO_DOT_L ASSIGN HALF_REG
897 {
898 if (IS_DREG_L ($3))
899 {
900 notethat ("dsp32alu: A0.l = reg_half\n");
901 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
902 }
903 else
904 return yyerror ("A0.l = Rx.l expected");
905 }
906 | A_ONE_DOT_L ASSIGN HALF_REG
907 {
908 if (IS_DREG_L ($3))
909 {
910 notethat ("dsp32alu: A1.l = reg_half\n");
911 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
912 }
913 else
914 return yyerror ("A1.l = Rx.l expected");
915 }
916
917 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
918 {
919 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
920 {
921 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
922 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
923 }
924 else
925 return yyerror ("Dregs expected");
926 }
927
928 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
929 {
930 if (!IS_DREG ($1))
931 return yyerror ("Dregs expected");
932 else if (!valid_dreg_pair (&$5, $7))
933 return yyerror ("Bad dreg pair");
934 else if (!valid_dreg_pair (&$9, $11))
935 return yyerror ("Bad dreg pair");
936 else
937 {
938 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
939 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
940 }
941 }
942 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
943 {
944 if (!IS_DREG ($1))
945 return yyerror ("Dregs expected");
946 else if (!valid_dreg_pair (&$5, $7))
947 return yyerror ("Bad dreg pair");
948 else if (!valid_dreg_pair (&$9, $11))
949 return yyerror ("Bad dreg pair");
950 else
951 {
952 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
953 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
954 }
955 }
956
957 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
958 rnd_op
959 {
960 if (!IS_DREG ($1))
961 return yyerror ("Dregs expected");
962 else if (!valid_dreg_pair (&$5, $7))
963 return yyerror ("Bad dreg pair");
964 else if (!valid_dreg_pair (&$9, $11))
965 return yyerror ("Bad dreg pair");
966 else
967 {
968 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
969 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
970 }
971 }
972
973 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
974 rnd_op
975 {
976 if (!IS_DREG ($1))
977 return yyerror ("Dregs expected");
978 else if (!valid_dreg_pair (&$5, $7))
979 return yyerror ("Bad dreg pair");
980 else if (!valid_dreg_pair (&$9, $11))
981 return yyerror ("Bad dreg pair");
982 else
983 {
984 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
985 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
986 }
987 }
988
989 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
990 b3_op
991 {
992 if (!IS_DREG ($1))
993 return yyerror ("Dregs expected");
994 else if (!valid_dreg_pair (&$5, $7))
995 return yyerror ("Bad dreg pair");
996 else if (!valid_dreg_pair (&$9, $11))
997 return yyerror ("Bad dreg pair");
998 else
999 {
1000 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1001 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1002 }
1003 }
1004
1005 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1006 {
1007 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1008 {
1009 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1010 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1011 }
1012 else
1013 return yyerror ("Dregs expected");
1014 }
1015
1016 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1017 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1018 {
1019 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1020 {
1021 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1022 "SIGN (dregs_hi) * dregs_hi + "
1023 "SIGN (dregs_lo) * dregs_lo \n");
1024
1025 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1026 }
1027 else
1028 return yyerror ("Dregs expected");
1029 }
1030 | REG ASSIGN REG plus_minus REG amod1
1031 {
1032 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1033 {
1034 if ($6.aop == 0)
1035 {
1036 /* No saturation flag specified, generate the 16 bit variant. */
1037 notethat ("COMP3op: dregs = dregs +- dregs\n");
1038 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1039 }
1040 else
1041 {
1042 /* Saturation flag specified, generate the 32 bit variant. */
1043 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1044 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1045 }
1046 }
1047 else
1048 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1049 {
1050 notethat ("COMP3op: pregs = pregs + pregs\n");
1051 $$ = COMP3OP (&$1, &$3, &$5, 5);
1052 }
1053 else
1054 return yyerror ("Dregs expected");
1055 }
1056 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1057 {
1058 int op;
1059
1060 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1061 {
1062 if ($9.r0)
1063 op = 6;
1064 else
1065 op = 7;
1066
1067 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1068 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1069 }
1070 else
1071 return yyerror ("Dregs expected");
1072 }
1073
1074 | a_assign MINUS REG_A
1075 {
1076 notethat ("dsp32alu: Ax = - Ax\n");
1077 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1078 }
1079 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1080 {
1081 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1082 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1083 $6.s0, $6.x0, HL2 ($3, $5));
1084 }
1085 | a_assign a_assign expr
1086 {
1087 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1088 {
1089 notethat ("dsp32alu: A1 = A0 = 0\n");
1090 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1091 }
1092 else
1093 return yyerror ("Bad value, 0 expected");
1094 }
1095
1096 /* Saturating. */
1097 | a_assign REG_A LPAREN S RPAREN
1098 {
1099 if (REG_SAME ($1, $2))
1100 {
1101 notethat ("dsp32alu: Ax = Ax (S)\n");
1102 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1103 }
1104 else
1105 return yyerror ("Registers must be equal");
1106 }
1107
1108 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1109 {
1110 if (IS_DREG ($3))
1111 {
1112 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1113 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1114 }
1115 else
1116 return yyerror ("Dregs expected");
1117 }
1118
1119 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1120 {
1121 if (IS_DREG ($3) && IS_DREG ($5))
1122 {
1123 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1124 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1125 }
1126 else
1127 return yyerror ("Dregs expected");
1128 }
1129
1130 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1131 {
1132 if (IS_DREG ($3) && IS_DREG ($5))
1133 {
1134 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1135 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1136 }
1137 else
1138 return yyerror ("Dregs expected");
1139 }
1140
1141 | a_assign REG_A
1142 {
1143 if (!REG_SAME ($1, $2))
1144 {
1145 notethat ("dsp32alu: An = Am\n");
1146 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1147 }
1148 else
1149 return yyerror ("Accu reg arguments must differ");
1150 }
1151
1152 | a_assign REG
1153 {
1154 if (IS_DREG ($2))
1155 {
1156 notethat ("dsp32alu: An = dregs\n");
1157 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1158 }
1159 else
1160 return yyerror ("Dregs expected");
1161 }
1162
1163 | REG ASSIGN HALF_REG xpmod
1164 {
1165 if (!IS_H ($3))
1166 {
1167 if ($1.regno == REG_A0x && IS_DREG ($3))
1168 {
1169 notethat ("dsp32alu: A0.x = dregs_lo\n");
1170 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1171 }
1172 else if ($1.regno == REG_A1x && IS_DREG ($3))
1173 {
1174 notethat ("dsp32alu: A1.x = dregs_lo\n");
1175 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1176 }
1177 else if (IS_DREG ($1) && IS_DREG ($3))
1178 {
1179 notethat ("ALU2op: dregs = dregs_lo\n");
1180 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1181 }
1182 else
1183 return yyerror ("Register mismatch");
1184 }
1185 else
1186 return yyerror ("Low reg expected");
1187 }
1188
1189 | HALF_REG ASSIGN expr
1190 {
1191 notethat ("LDIMMhalf: pregs_half = imm16\n");
1192
1193 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1194 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1195 return yyerror ("Wrong register for load immediate");
1196
1197 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1198 return yyerror ("Constant out of range");
1199
1200 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1201 }
1202
1203 | a_assign expr
1204 {
1205 notethat ("dsp32alu: An = 0\n");
1206
1207 if (imm7 ($2) != 0)
1208 return yyerror ("0 expected");
1209
1210 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1211 }
1212
1213 | REG ASSIGN expr xpmod1
1214 {
1215 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1216 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1217 return yyerror ("Wrong register for load immediate");
1218
1219 if ($4.r0 == 0)
1220 {
1221 /* 7 bit immediate value if possible.
1222 We will check for that constant value for efficiency
1223 If it goes to reloc, it will be 16 bit. */
1224 if (IS_CONST ($3) && IS_IMM ($3, 7) && (IS_DREG ($1) || IS_PREG ($1)))
1225 {
1226 /* if the expr is a relocation, generate it. */
1227 if (IS_DREG ($1) && IS_IMM ($3, 7))
1228 {
1229 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1230 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1231 }
1232 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1233 {
1234 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1235 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1236 }
1237 else
1238 return yyerror ("Bad register or value for assigment");
1239 }
1240 else
1241 {
1242 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1243 /* reg, H, S, Z. */
1244 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1245 }
1246 }
1247 else
1248 {
1249 /* (z) There is no 7 bit zero extended instruction.
1250 If the expr is a relocation, generate it. */
1251 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1252 /* reg, H, S, Z. */
1253 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1254 }
1255 }
1256
1257 | HALF_REG ASSIGN REG
1258 {
1259 if (IS_H ($1))
1260 return yyerror ("Low reg expected");
1261
1262 if (IS_DREG ($1) && $3.regno == REG_A0x)
1263 {
1264 notethat ("dsp32alu: dregs_lo = A0.x\n");
1265 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1266 }
1267 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1268 {
1269 notethat ("dsp32alu: dregs_lo = A1.x\n");
1270 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1271 }
1272 else
1273 return yyerror ("Register mismatch");
1274 }
1275
1276 | REG ASSIGN REG op_bar_op REG amod0
1277 {
1278 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1279 {
1280 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1281 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1282 }
1283 else
1284 return yyerror ("Register mismatch");
1285 }
1286
1287 | REG ASSIGN BYTE_DREG xpmod
1288 {
1289 if (IS_DREG ($1) && IS_DREG ($3))
1290 {
1291 notethat ("ALU2op: dregs = dregs_byte\n");
1292 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1293 }
1294 else
1295 return yyerror ("Register mismatch");
1296 }
1297
1298 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1299 {
1300 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1301 {
1302 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1303 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1304 }
1305 else
1306 return yyerror ("Register mismatch");
1307 }
1308
1309 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1310 {
1311 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1312 {
1313 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1314 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1315 }
1316 else
1317 return yyerror ("Register mismatch");
1318 }
1319
1320 | a_minusassign REG_A w32_or_nothing
1321 {
1322 if (!IS_A1 ($1) && IS_A1 ($2))
1323 {
1324 notethat ("dsp32alu: A0 -= A1\n");
1325 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1326 }
1327 else
1328 return yyerror ("Register mismatch");
1329 }
1330
1331 | REG _MINUS_ASSIGN expr
1332 {
1333 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1334 {
1335 notethat ("dagMODik: iregs -= 4\n");
1336 $$ = DAGMODIK (&$1, 3);
1337 }
1338 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1339 {
1340 notethat ("dagMODik: iregs -= 2\n");
1341 $$ = DAGMODIK (&$1, 1);
1342 }
1343 else
1344 return yyerror ("Register or value mismatch");
1345 }
1346
1347 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1348 {
1349 if (IS_IREG ($1) && IS_MREG ($3))
1350 {
1351 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1352 /* i, m, op, br. */
1353 $$ = DAGMODIM (&$1, &$3, 0, 1);
1354 }
1355 else if (IS_PREG ($1) && IS_PREG ($3))
1356 {
1357 notethat ("PTR2op: pregs += pregs (BREV )\n");
1358 $$ = PTR2OP (&$1, &$3, 5);
1359 }
1360 else
1361 return yyerror ("Register mismatch");
1362 }
1363
1364 | REG _MINUS_ASSIGN REG
1365 {
1366 if (IS_IREG ($1) && IS_MREG ($3))
1367 {
1368 notethat ("dagMODim: iregs -= mregs\n");
1369 $$ = DAGMODIM (&$1, &$3, 1, 0);
1370 }
1371 else if (IS_PREG ($1) && IS_PREG ($3))
1372 {
1373 notethat ("PTR2op: pregs -= pregs\n");
1374 $$ = PTR2OP (&$1, &$3, 0);
1375 }
1376 else
1377 return yyerror ("Register mismatch");
1378 }
1379
1380 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1381 {
1382 if (!IS_A1 ($1) && IS_A1 ($3))
1383 {
1384 notethat ("dsp32alu: A0 += A1 (W32)\n");
1385 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1386 }
1387 else
1388 return yyerror ("Register mismatch");
1389 }
1390
1391 | REG _PLUS_ASSIGN REG
1392 {
1393 if (IS_IREG ($1) && IS_MREG ($3))
1394 {
1395 notethat ("dagMODim: iregs += mregs\n");
1396 $$ = DAGMODIM (&$1, &$3, 0, 0);
1397 }
1398 else
1399 return yyerror ("iregs += mregs expected");
1400 }
1401
1402 | REG _PLUS_ASSIGN expr
1403 {
1404 if (IS_IREG ($1))
1405 {
1406 if (EXPR_VALUE ($3) == 4)
1407 {
1408 notethat ("dagMODik: iregs += 4\n");
1409 $$ = DAGMODIK (&$1, 2);
1410 }
1411 else if (EXPR_VALUE ($3) == 2)
1412 {
1413 notethat ("dagMODik: iregs += 2\n");
1414 $$ = DAGMODIK (&$1, 0);
1415 }
1416 else
1417 return yyerror ("iregs += [ 2 | 4 ");
1418 }
1419 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1420 {
1421 notethat ("COMPI2opP: pregs += imm7\n");
1422 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1423 }
1424 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1425 {
1426 notethat ("COMPI2opD: dregs += imm7\n");
1427 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1428 }
1429 else
1430 return yyerror ("Register mismatch");
1431 }
1432
1433 | REG _STAR_ASSIGN REG
1434 {
1435 if (IS_DREG ($1) && IS_DREG ($3))
1436 {
1437 notethat ("ALU2op: dregs *= dregs\n");
1438 $$ = ALU2OP (&$1, &$3, 3);
1439 }
1440 else
1441 return yyerror ("Register mismatch");
1442 }
1443
1444 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1445 {
1446 if (!valid_dreg_pair (&$3, $5))
1447 return yyerror ("Bad dreg pair");
1448 else if (!valid_dreg_pair (&$7, $9))
1449 return yyerror ("Bad dreg pair");
1450 else
1451 {
1452 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1453 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1454 }
1455 }
1456
1457 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1458 {
1459 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1460 {
1461 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1462 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1463 }
1464 else
1465 return yyerror ("Register mismatch");
1466 }
1467
1468 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1469 {
1470 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1471 && REG_SAME ($1, $4))
1472 {
1473 if (EXPR_VALUE ($9) == 1)
1474 {
1475 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1476 $$ = ALU2OP (&$1, &$6, 4);
1477 }
1478 else if (EXPR_VALUE ($9) == 2)
1479 {
1480 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1481 $$ = ALU2OP (&$1, &$6, 5);
1482 }
1483 else
1484 return yyerror ("Bad shift value");
1485 }
1486 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1487 && REG_SAME ($1, $4))
1488 {
1489 if (EXPR_VALUE ($9) == 1)
1490 {
1491 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1492 $$ = PTR2OP (&$1, &$6, 6);
1493 }
1494 else if (EXPR_VALUE ($9) == 2)
1495 {
1496 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1497 $$ = PTR2OP (&$1, &$6, 7);
1498 }
1499 else
1500 return yyerror ("Bad shift value");
1501 }
1502 else
1503 return yyerror ("Register mismatch");
1504 }
1505
1506 /* COMP3 CCFLAG. */
1507 | REG ASSIGN REG BAR REG
1508 {
1509 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1510 {
1511 notethat ("COMP3op: dregs = dregs | dregs\n");
1512 $$ = COMP3OP (&$1, &$3, &$5, 3);
1513 }
1514 else
1515 return yyerror ("Dregs expected");
1516 }
1517 | REG ASSIGN REG CARET REG
1518 {
1519 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1520 {
1521 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1522 $$ = COMP3OP (&$1, &$3, &$5, 4);
1523 }
1524 else
1525 return yyerror ("Dregs expected");
1526 }
1527 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1528 {
1529 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1530 {
1531 if (EXPR_VALUE ($8) == 1)
1532 {
1533 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1534 $$ = COMP3OP (&$1, &$3, &$6, 6);
1535 }
1536 else if (EXPR_VALUE ($8) == 2)
1537 {
1538 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1539 $$ = COMP3OP (&$1, &$3, &$6, 7);
1540 }
1541 else
1542 return yyerror ("Bad shift value");
1543 }
1544 else
1545 return yyerror ("Dregs expected");
1546 }
1547 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1548 {
1549 if (!REG_SAME ($3, $5))
1550 {
1551 notethat ("CCflag: CC = A0 == A1\n");
1552 $$ = CCFLAG (0, 0, 5, 0, 0);
1553 }
1554 else
1555 return yyerror ("CC register expected");
1556 }
1557 | CCREG ASSIGN REG_A LESS_THAN REG_A
1558 {
1559 if (!REG_SAME ($3, $5))
1560 {
1561 notethat ("CCflag: CC = A0 < A1\n");
1562 $$ = CCFLAG (0, 0, 6, 0, 0);
1563 }
1564 else
1565 return yyerror ("Register mismatch");
1566 }
1567 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1568 {
1569 if (REG_CLASS($3) == REG_CLASS($5))
1570 {
1571 notethat ("CCflag: CC = dpregs < dpregs\n");
1572 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1573 }
1574 else
1575 return yyerror ("Compare only of same register class");
1576 }
1577 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1578 {
1579 if (($6.r0 == 1 && IS_IMM ($5, 3))
1580 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1581 {
1582 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1583 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1584 }
1585 else
1586 return yyerror ("Bad constant value");
1587 }
1588 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1589 {
1590 if (REG_CLASS($3) == REG_CLASS($5))
1591 {
1592 notethat ("CCflag: CC = dpregs == dpregs\n");
1593 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1594 }
1595 }
1596 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1597 {
1598 if (IS_IMM ($5, 3))
1599 {
1600 notethat ("CCflag: CC = dpregs == imm3\n");
1601 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1602 }
1603 else
1604 return yyerror ("Bad constant range");
1605 }
1606 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1607 {
1608 if (!REG_SAME ($3, $5))
1609 {
1610 notethat ("CCflag: CC = A0 <= A1\n");
1611 $$ = CCFLAG (0, 0, 7, 0, 0);
1612 }
1613 else
1614 return yyerror ("CC register expected");
1615 }
1616 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1617 {
1618 if (REG_CLASS($3) == REG_CLASS($5))
1619 {
1620 notethat ("CCflag: CC = pregs <= pregs (..)\n");
1621 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1622 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1623 }
1624 else
1625 return yyerror ("Compare only of same register class");
1626 }
1627 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1628 {
1629 if (($6.r0 == 1 && IS_IMM ($5, 3))
1630 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1631 {
1632 if (IS_DREG ($3))
1633 {
1634 notethat ("CCflag: CC = dregs <= (u)imm3\n");
1635 /* x y opc I G */
1636 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 0);
1637 }
1638 else if (IS_PREG ($3))
1639 {
1640 notethat ("CCflag: CC = pregs <= (u)imm3\n");
1641 /* x y opc I G */
1642 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 1);
1643 }
1644 else
1645 return yyerror ("Dreg or Preg expected");
1646 }
1647 else
1648 return yyerror ("Bad constant value");
1649 }
1650
1651 | REG ASSIGN REG AMPERSAND REG
1652 {
1653 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1654 {
1655 notethat ("COMP3op: dregs = dregs & dregs\n");
1656 $$ = COMP3OP (&$1, &$3, &$5, 2);
1657 }
1658 else
1659 return yyerror ("Dregs expected");
1660 }
1661
1662 | ccstat
1663 {
1664 notethat ("CC2stat operation\n");
1665 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1666 }
1667
1668 | REG ASSIGN REG
1669 {
1670 if (IS_ALLREG ($1) && IS_ALLREG ($3))
1671 {
1672 notethat ("REGMV: allregs = allregs\n");
1673 $$ = bfin_gen_regmv (&$3, &$1);
1674 }
1675 else
1676 return yyerror ("Register mismatch");
1677 }
1678
1679 | CCREG ASSIGN REG
1680 {
1681 if (IS_DREG ($3))
1682 {
1683 notethat ("CC2dreg: CC = dregs\n");
1684 $$ = bfin_gen_cc2dreg (1, &$3);
1685 }
1686 else
1687 return yyerror ("Register mismatch");
1688 }
1689
1690 | REG ASSIGN CCREG
1691 {
1692 if (IS_DREG ($1))
1693 {
1694 notethat ("CC2dreg: dregs = CC\n");
1695 $$ = bfin_gen_cc2dreg (0, &$1);
1696 }
1697 else
1698 return yyerror ("Register mismatch");
1699 }
1700
1701 | CCREG _ASSIGN_BANG CCREG
1702 {
1703 notethat ("CC2dreg: CC =! CC\n");
1704 $$ = bfin_gen_cc2dreg (3, 0);
1705 }
1706
1707 /* DSPMULT. */
1708
1709 | HALF_REG ASSIGN multiply_halfregs opt_mode
1710 {
1711 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1712
1713 if (!IS_H ($1) && $4.MM)
1714 return yyerror ("(M) not allowed with MAC0");
1715
1716 if (IS_H ($1))
1717 {
1718 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1719 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1720 &$1, 0, &$3.s0, &$3.s1, 0);
1721 }
1722 else
1723 {
1724 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1725 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1726 &$1, 0, &$3.s0, &$3.s1, 1);
1727 }
1728 }
1729
1730 | REG ASSIGN multiply_halfregs opt_mode
1731 {
1732 /* Odd registers can use (M). */
1733 if (!IS_DREG ($1))
1734 return yyerror ("Dreg expected");
1735
1736 if (!IS_EVEN ($1))
1737 {
1738 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1739
1740 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1741 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1742 &$1, 0, &$3.s0, &$3.s1, 0);
1743 }
1744 else if ($4.MM == 0)
1745 {
1746 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1747 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1748 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1749 &$1, 0, &$3.s0, &$3.s1, 1);
1750 }
1751 else
1752 return yyerror ("Register or mode mismatch");
1753 }
1754
1755 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1756 HALF_REG ASSIGN multiply_halfregs opt_mode
1757 {
1758 if (!IS_DREG ($1) || !IS_DREG ($6))
1759 return yyerror ("Dregs expected");
1760
1761 if (check_multiply_halfregs (&$3, &$8) < 0)
1762 return -1;
1763
1764 if (IS_H ($1) && !IS_H ($6))
1765 {
1766 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1767 "dregs_lo = multiply_halfregs opt_mode\n");
1768 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1769 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1770 &$1, 0, &$3.s0, &$3.s1, 1);
1771 }
1772 else if (!IS_H ($1) && IS_H ($6) && $4.MM == 0)
1773 {
1774 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1775 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1776 &$1, 0, &$3.s0, &$3.s1, 1);
1777 }
1778 else
1779 return yyerror ("Multfunc Register or mode mismatch");
1780 }
1781
1782 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1783 {
1784 if (!IS_DREG ($1) || !IS_DREG ($6))
1785 return yyerror ("Dregs expected");
1786
1787 if (check_multiply_halfregs (&$3, &$8) < 0)
1788 return -1;
1789
1790 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1791 "dregs = multiply_halfregs opt_mode\n");
1792 if (IS_EVEN ($1))
1793 {
1794 if ($6.regno - $1.regno != 1 || $4.MM != 0)
1795 return yyerror ("Dest registers or mode mismatch");
1796
1797 /* op1 MM mmod */
1798 $$ = DSP32MULT (0, 0, $9.mod, 1, 1,
1799 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1800 &$1, 0, &$3.s0, &$3.s1, 1);
1801
1802 }
1803 else
1804 {
1805 if ($1.regno - $6.regno != 1)
1806 return yyerror ("Dest registers mismatch");
1807
1808 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1809 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1810 &$1, 0, &$3.s0, &$3.s1, 1);
1811 }
1812 }
1813
1814 \f
1815 /* SHIFTs. */
1816 | a_assign ASHIFT REG_A BY HALF_REG
1817 {
1818 if (!REG_SAME ($1, $3))
1819 return yyerror ("Aregs must be same");
1820
1821 if (IS_DREG ($5) && !IS_H ($5))
1822 {
1823 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1824 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1825 }
1826 else
1827 return yyerror ("Dregs expected");
1828 }
1829
1830 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1831 {
1832 if (IS_DREG ($6) && !IS_H ($6))
1833 {
1834 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1835 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1836 }
1837 else
1838 return yyerror ("Dregs expected");
1839 }
1840
1841 | a_assign REG_A LESS_LESS expr
1842 {
1843 if (!REG_SAME ($1, $2))
1844 return yyerror ("Aregs must be same");
1845
1846 if (IS_UIMM ($4, 5))
1847 {
1848 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1849 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1850 }
1851 else
1852 return yyerror ("Bad shift value");
1853 }
1854
1855 | REG ASSIGN REG LESS_LESS expr vsmod
1856 {
1857 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1858 {
1859 if ($6.r0)
1860 {
1861 /* Vector? */
1862 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1863 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1864 }
1865 else
1866 {
1867 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1868 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1869 }
1870 }
1871 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1872 {
1873 if (EXPR_VALUE ($5) == 2)
1874 {
1875 notethat ("PTR2op: pregs = pregs << 2\n");
1876 $$ = PTR2OP (&$1, &$3, 1);
1877 }
1878 else if (EXPR_VALUE ($5) == 1)
1879 {
1880 notethat ("COMP3op: pregs = pregs << 1\n");
1881 $$ = COMP3OP (&$1, &$3, &$3, 5);
1882 }
1883 else
1884 return yyerror ("Bad shift value");
1885 }
1886 else
1887 return yyerror ("Bad shift value or register");
1888 }
1889 | HALF_REG ASSIGN HALF_REG LESS_LESS expr
1890 {
1891 if (IS_UIMM ($5, 4))
1892 {
1893 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1894 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1895 }
1896 else
1897 return yyerror ("Bad shift value");
1898 }
1899 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1900 {
1901 if (IS_UIMM ($5, 4))
1902 {
1903 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1904 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1905 }
1906 else
1907 return yyerror ("Bad shift value");
1908 }
1909 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1910 {
1911 int op;
1912
1913 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1914 {
1915 if ($7.r0)
1916 {
1917 op = 1;
1918 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1919 "dregs_lo (V, .)\n");
1920 }
1921 else
1922 {
1923
1924 op = 2;
1925 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1926 }
1927 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1928 }
1929 else
1930 return yyerror ("Dregs expected");
1931 }
1932
1933 /* EXPADJ. */
1934 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
1935 {
1936 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1937 {
1938 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
1939 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
1940 }
1941 else
1942 return yyerror ("Bad shift value or register");
1943 }
1944
1945
1946 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
1947 {
1948 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1949 {
1950 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
1951 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
1952 }
1953 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
1954 {
1955 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
1956 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
1957 }
1958 else
1959 return yyerror ("Bad shift value or register");
1960 }
1961
1962 /* DEPOSIT. */
1963
1964 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
1965 {
1966 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1967 {
1968 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
1969 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
1970 }
1971 else
1972 return yyerror ("Register mismatch");
1973 }
1974
1975 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
1976 {
1977 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1978 {
1979 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
1980 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
1981 }
1982 else
1983 return yyerror ("Register mismatch");
1984 }
1985
1986 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
1987 {
1988 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
1989 {
1990 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
1991 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
1992 }
1993 else
1994 return yyerror ("Register mismatch");
1995 }
1996
1997 | a_assign REG_A _GREATER_GREATER_GREATER expr
1998 {
1999 if (!REG_SAME ($1, $2))
2000 return yyerror ("Aregs must be same");
2001
2002 if (IS_UIMM ($4, 5))
2003 {
2004 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2005 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2006 }
2007 else
2008 return yyerror ("Shift value range error");
2009 }
2010 | a_assign LSHIFT REG_A BY HALF_REG
2011 {
2012 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2013 {
2014 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2015 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2016 }
2017 else
2018 return yyerror ("Register mismatch");
2019 }
2020
2021 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2022 {
2023 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2024 {
2025 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2026 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2027 }
2028 else
2029 return yyerror ("Register mismatch");
2030 }
2031
2032 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2033 {
2034 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2035 {
2036 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2037 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2038 }
2039 else
2040 return yyerror ("Register mismatch");
2041 }
2042
2043 | REG ASSIGN SHIFT REG BY HALF_REG
2044 {
2045 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2046 {
2047 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2048 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2049 }
2050 else
2051 return yyerror ("Register mismatch");
2052 }
2053
2054 | a_assign REG_A GREATER_GREATER expr
2055 {
2056 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2057 {
2058 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2059 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2060 }
2061 else
2062 return yyerror ("Accu register expected");
2063 }
2064
2065 | REG ASSIGN REG GREATER_GREATER expr vmod
2066 {
2067 if ($6.r0 == 1)
2068 {
2069 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2070 {
2071 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2072 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2073 }
2074 else
2075 return yyerror ("Register mismatch");
2076 }
2077 else
2078 {
2079 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2080 {
2081 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2082 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2083 }
2084 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2085 {
2086 notethat ("PTR2op: pregs = pregs >> 2\n");
2087 $$ = PTR2OP (&$1, &$3, 3);
2088 }
2089 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2090 {
2091 notethat ("PTR2op: pregs = pregs >> 1\n");
2092 $$ = PTR2OP (&$1, &$3, 4);
2093 }
2094 else
2095 return yyerror ("Register mismatch");
2096 }
2097 }
2098 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2099 {
2100 if (IS_UIMM ($5, 5))
2101 {
2102 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2103 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2104 }
2105 else
2106 return yyerror ("Register mismatch");
2107 }
2108 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2109 {
2110 if (IS_UIMM ($5, 5))
2111 {
2112 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2113 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2114 $6.s0, HL2 ($1, $3));
2115 }
2116 else
2117 return yyerror ("Register or modifier mismatch");
2118 }
2119
2120
2121 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2122 {
2123 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2124 {
2125 if ($6.r0)
2126 {
2127 /* Vector? */
2128 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2129 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2130 }
2131 else
2132 {
2133 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2134 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2135 }
2136 }
2137 else
2138 return yyerror ("Register mismatch");
2139 }
2140
2141 | HALF_REG ASSIGN ONES REG
2142 {
2143 if (IS_DREG_L ($1) && IS_DREG ($4))
2144 {
2145 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2146 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2147 }
2148 else
2149 return yyerror ("Register mismatch");
2150 }
2151
2152 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2153 {
2154 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2155 {
2156 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2157 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2158 }
2159 else
2160 return yyerror ("Register mismatch");
2161 }
2162
2163 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2164 {
2165 if (IS_DREG ($1)
2166 && $7.regno == REG_A0
2167 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2168 {
2169 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2170 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2171 }
2172 else
2173 return yyerror ("Register mismatch");
2174 }
2175
2176 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2177 {
2178 if (IS_DREG ($1)
2179 && $7.regno == REG_A0
2180 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2181 {
2182 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2183 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2184 }
2185 else
2186 return yyerror ("Register mismatch");
2187 }
2188
2189 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2190 {
2191 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2192 {
2193 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2194 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2195 }
2196 else
2197 return yyerror ("Register mismatch");
2198 }
2199
2200 | a_assign ROT REG_A BY HALF_REG
2201 {
2202 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2203 {
2204 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2205 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2206 }
2207 else
2208 return yyerror ("Register mismatch");
2209 }
2210
2211 | REG ASSIGN ROT REG BY HALF_REG
2212 {
2213 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2214 {
2215 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2216 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2217 }
2218 else
2219 return yyerror ("Register mismatch");
2220 }
2221
2222 | a_assign ROT REG_A BY expr
2223 {
2224 if (IS_IMM ($5, 6))
2225 {
2226 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2227 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2228 }
2229 else
2230 return yyerror ("Register mismatch");
2231 }
2232
2233 | REG ASSIGN ROT REG BY expr
2234 {
2235 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2236 {
2237 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2238 }
2239 else
2240 return yyerror ("Register mismatch");
2241 }
2242
2243 | HALF_REG ASSIGN SIGNBITS REG_A
2244 {
2245 if (IS_DREG_L ($1))
2246 {
2247 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2248 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2249 }
2250 else
2251 return yyerror ("Register mismatch");
2252 }
2253
2254 | HALF_REG ASSIGN SIGNBITS REG
2255 {
2256 if (IS_DREG_L ($1) && IS_DREG ($4))
2257 {
2258 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2259 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2260 }
2261 else
2262 return yyerror ("Register mismatch");
2263 }
2264
2265 | HALF_REG ASSIGN SIGNBITS HALF_REG
2266 {
2267 if (IS_DREG_L ($1))
2268 {
2269 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2270 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2271 }
2272 else
2273 return yyerror ("Register mismatch");
2274 }
2275
2276 /* The ASR bit is just inverted here. */
2277 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2278 {
2279 if (IS_DREG_L ($1) && IS_DREG ($5))
2280 {
2281 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2282 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2283 }
2284 else
2285 return yyerror ("Register mismatch");
2286 }
2287
2288 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2289 {
2290 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2291 {
2292 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2293 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2294 }
2295 else
2296 return yyerror ("Register mismatch");
2297 }
2298
2299 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2300 {
2301 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2302 {
2303 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2304 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2305 }
2306 else
2307 return yyerror ("Register mismatch");
2308 }
2309
2310 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2311 {
2312 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2313 {
2314 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2315 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2316 }
2317 else
2318 return yyerror ("Dregs expected");
2319 }
2320
2321
2322 /* LOGI2op: BITCLR (dregs, uimm5). */
2323 | BITCLR LPAREN REG COMMA expr RPAREN
2324 {
2325 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2326 {
2327 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2328 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2329 }
2330 else
2331 return yyerror ("Register mismatch");
2332 }
2333
2334 /* LOGI2op: BITSET (dregs, uimm5). */
2335 | BITSET LPAREN REG COMMA expr RPAREN
2336 {
2337 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2338 {
2339 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2340 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2341 }
2342 else
2343 return yyerror ("Register mismatch");
2344 }
2345
2346 /* LOGI2op: BITTGL (dregs, uimm5). */
2347 | BITTGL LPAREN REG COMMA expr RPAREN
2348 {
2349 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2350 {
2351 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2352 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2353 }
2354 else
2355 return yyerror ("Register mismatch");
2356 }
2357
2358 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2359 {
2360 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2361 {
2362 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2363 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2364 }
2365 else
2366 return yyerror ("Register mismatch or value error");
2367 }
2368
2369 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2370 {
2371 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2372 {
2373 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2374 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2375 }
2376 else
2377 return yyerror ("Register mismatch or value error");
2378 }
2379
2380 | IF BANG CCREG REG ASSIGN REG
2381 {
2382 if ((IS_DREG ($4) || IS_PREG ($4))
2383 && (IS_DREG ($6) || IS_PREG ($6)))
2384 {
2385 notethat ("ccMV: IF ! CC gregs = gregs\n");
2386 $$ = CCMV (&$6, &$4, 0);
2387 }
2388 else
2389 return yyerror ("Register mismatch");
2390 }
2391
2392 | IF CCREG REG ASSIGN REG
2393 {
2394 if ((IS_DREG ($5) || IS_PREG ($5))
2395 && (IS_DREG ($3) || IS_PREG ($3)))
2396 {
2397 notethat ("ccMV: IF CC gregs = gregs\n");
2398 $$ = CCMV (&$5, &$3, 1);
2399 }
2400 else
2401 return yyerror ("Register mismatch");
2402 }
2403
2404 | IF BANG CCREG JUMP expr
2405 {
2406 if (IS_PCREL10 ($5))
2407 {
2408 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2409 $$ = BRCC (0, 0, $5);
2410 }
2411 else
2412 return yyerror ("Bad jump offset");
2413 }
2414
2415 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2416 {
2417 if (IS_PCREL10 ($5))
2418 {
2419 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2420 $$ = BRCC (0, 1, $5);
2421 }
2422 else
2423 return yyerror ("Bad jump offset");
2424 }
2425
2426 | IF CCREG JUMP expr
2427 {
2428 if (IS_PCREL10 ($4))
2429 {
2430 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2431 $$ = BRCC (1, 0, $4);
2432 }
2433 else
2434 return yyerror ("Bad jump offset");
2435 }
2436
2437 | IF CCREG JUMP expr LPAREN BP RPAREN
2438 {
2439 if (IS_PCREL10 ($4))
2440 {
2441 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2442 $$ = BRCC (1, 1, $4);
2443 }
2444 else
2445 return yyerror ("Bad jump offset");
2446 }
2447 | NOP
2448 {
2449 notethat ("ProgCtrl: NOP\n");
2450 $$ = PROGCTRL (0, 0);
2451 }
2452
2453 | RTS
2454 {
2455 notethat ("ProgCtrl: RTS\n");
2456 $$ = PROGCTRL (1, 0);
2457 }
2458
2459 | RTI
2460 {
2461 notethat ("ProgCtrl: RTI\n");
2462 $$ = PROGCTRL (1, 1);
2463 }
2464
2465 | RTX
2466 {
2467 notethat ("ProgCtrl: RTX\n");
2468 $$ = PROGCTRL (1, 2);
2469 }
2470
2471 | RTN
2472 {
2473 notethat ("ProgCtrl: RTN\n");
2474 $$ = PROGCTRL (1, 3);
2475 }
2476
2477 | RTE
2478 {
2479 notethat ("ProgCtrl: RTE\n");
2480 $$ = PROGCTRL (1, 4);
2481 }
2482
2483 | IDLE
2484 {
2485 notethat ("ProgCtrl: IDLE\n");
2486 $$ = PROGCTRL (2, 0);
2487 }
2488
2489 | CSYNC
2490 {
2491 notethat ("ProgCtrl: CSYNC\n");
2492 $$ = PROGCTRL (2, 3);
2493 }
2494
2495 | SSYNC
2496 {
2497 notethat ("ProgCtrl: SSYNC\n");
2498 $$ = PROGCTRL (2, 4);
2499 }
2500
2501 | EMUEXCPT
2502 {
2503 notethat ("ProgCtrl: EMUEXCPT\n");
2504 $$ = PROGCTRL (2, 5);
2505 }
2506
2507 | CLI REG
2508 {
2509 if (IS_DREG ($2))
2510 {
2511 notethat ("ProgCtrl: CLI dregs\n");
2512 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2513 }
2514 else
2515 return yyerror ("Dreg expected for CLI");
2516 }
2517
2518 | STI REG
2519 {
2520 if (IS_DREG ($2))
2521 {
2522 notethat ("ProgCtrl: STI dregs\n");
2523 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2524 }
2525 else
2526 return yyerror ("Dreg expected for STI");
2527 }
2528
2529 | JUMP LPAREN REG RPAREN
2530 {
2531 if (IS_PREG ($3))
2532 {
2533 notethat ("ProgCtrl: JUMP (pregs )\n");
2534 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2535 }
2536 else
2537 return yyerror ("Bad register for indirect jump");
2538 }
2539
2540 | CALL LPAREN REG RPAREN
2541 {
2542 if (IS_PREG ($3))
2543 {
2544 notethat ("ProgCtrl: CALL (pregs )\n");
2545 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2546 }
2547 else
2548 return yyerror ("Bad register for indirect call");
2549 }
2550
2551 | CALL LPAREN PC PLUS REG RPAREN
2552 {
2553 if (IS_PREG ($5))
2554 {
2555 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2556 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2557 }
2558 else
2559 return yyerror ("Bad register for indirect call");
2560 }
2561
2562 | JUMP LPAREN PC PLUS REG RPAREN
2563 {
2564 if (IS_PREG ($5))
2565 {
2566 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2567 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2568 }
2569 else
2570 return yyerror ("Bad register for indirect jump");
2571 }
2572
2573 | RAISE expr
2574 {
2575 if (IS_UIMM ($2, 4))
2576 {
2577 notethat ("ProgCtrl: RAISE uimm4\n");
2578 $$ = PROGCTRL (9, uimm4 ($2));
2579 }
2580 else
2581 return yyerror ("Bad value for RAISE");
2582 }
2583
2584 | EXCPT expr
2585 {
2586 notethat ("ProgCtrl: EMUEXCPT\n");
2587 $$ = PROGCTRL (10, uimm4 ($2));
2588 }
2589
2590 | TESTSET LPAREN REG RPAREN
2591 {
2592 if (IS_PREG ($3))
2593 {
2594 notethat ("ProgCtrl: TESTSET (pregs )\n");
2595 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2596 }
2597 else
2598 return yyerror ("Preg expected");
2599 }
2600
2601 | JUMP expr
2602 {
2603 if (IS_PCREL12 ($2))
2604 {
2605 notethat ("UJUMP: JUMP pcrel12\n");
2606 $$ = UJUMP ($2);
2607 }
2608 else
2609 return yyerror ("Bad value for relative jump");
2610 }
2611
2612 | JUMP_DOT_S expr
2613 {
2614 if (IS_PCREL12 ($2))
2615 {
2616 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2617 $$ = UJUMP($2);
2618 }
2619 else
2620 return yyerror ("Bad value for relative jump");
2621 }
2622
2623 | JUMP_DOT_L expr
2624 {
2625 if (IS_PCREL24 ($2))
2626 {
2627 notethat ("CALLa: jump.l pcrel24\n");
2628 $$ = CALLA ($2, 0);
2629 }
2630 else
2631 return yyerror ("Bad value for long jump");
2632 }
2633
2634 | JUMP_DOT_L pltpc
2635 {
2636 if (IS_PCREL24 ($2))
2637 {
2638 notethat ("CALLa: jump.l pcrel24\n");
2639 $$ = CALLA ($2, 2);
2640 }
2641 else
2642 return yyerror ("Bad value for long jump");
2643 }
2644
2645 | CALL expr
2646 {
2647 if (IS_PCREL24 ($2))
2648 {
2649 notethat ("CALLa: CALL pcrel25m2\n");
2650 $$ = CALLA ($2, 1);
2651 }
2652 else
2653 return yyerror ("Bad call address");
2654 }
2655 | CALL pltpc
2656 {
2657 if (IS_PCREL24 ($2))
2658 {
2659 notethat ("CALLa: CALL pcrel25m2\n");
2660 $$ = CALLA ($2, 2);
2661 }
2662 else
2663 return yyerror ("Bad call address");
2664 }
2665
2666 /* ALU2ops. */
2667 /* ALU2op: DIVQ (dregs, dregs). */
2668 | DIVQ LPAREN REG COMMA REG RPAREN
2669 {
2670 if (IS_DREG ($3) && IS_DREG ($5))
2671 $$ = ALU2OP (&$3, &$5, 8);
2672 else
2673 return yyerror ("Bad registers for DIVQ");
2674 }
2675
2676 | DIVS LPAREN REG COMMA REG RPAREN
2677 {
2678 if (IS_DREG ($3) && IS_DREG ($5))
2679 $$ = ALU2OP (&$3, &$5, 9);
2680 else
2681 return yyerror ("Bad registers for DIVS");
2682 }
2683
2684 | REG ASSIGN MINUS REG vsmod
2685 {
2686 if (IS_DREG ($1) && IS_DREG ($4))
2687 {
2688 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2689 {
2690 notethat ("ALU2op: dregs = - dregs\n");
2691 $$ = ALU2OP (&$1, &$4, 14);
2692 }
2693 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2694 {
2695 notethat ("dsp32alu: dregs = - dregs (.)\n");
2696 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2697 }
2698 else
2699 {
2700 notethat ("dsp32alu: dregs = - dregs (.)\n");
2701 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2702 }
2703 }
2704 else
2705 return yyerror ("Dregs expected");
2706 }
2707
2708 | REG ASSIGN TILDA REG
2709 {
2710 if (IS_DREG ($1) && IS_DREG ($4))
2711 {
2712 notethat ("ALU2op: dregs = ~dregs\n");
2713 $$ = ALU2OP (&$1, &$4, 15);
2714 }
2715 else
2716 return yyerror ("Dregs expected");
2717 }
2718
2719 | REG _GREATER_GREATER_ASSIGN REG
2720 {
2721 if (IS_DREG ($1) && IS_DREG ($3))
2722 {
2723 notethat ("ALU2op: dregs >>= dregs\n");
2724 $$ = ALU2OP (&$1, &$3, 1);
2725 }
2726 else
2727 return yyerror ("Dregs expected");
2728 }
2729
2730 | REG _GREATER_GREATER_ASSIGN expr
2731 {
2732 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2733 {
2734 notethat ("LOGI2op: dregs >>= uimm5\n");
2735 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2736 }
2737 else
2738 return yyerror ("Dregs expected or value error");
2739 }
2740
2741 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2742 {
2743 if (IS_DREG ($1) && IS_DREG ($3))
2744 {
2745 notethat ("ALU2op: dregs >>>= dregs\n");
2746 $$ = ALU2OP (&$1, &$3, 0);
2747 }
2748 else
2749 return yyerror ("Dregs expected");
2750 }
2751
2752 | REG _LESS_LESS_ASSIGN REG
2753 {
2754 if (IS_DREG ($1) && IS_DREG ($3))
2755 {
2756 notethat ("ALU2op: dregs <<= dregs\n");
2757 $$ = ALU2OP (&$1, &$3, 2);
2758 }
2759 else
2760 return yyerror ("Dregs expected");
2761 }
2762
2763 | REG _LESS_LESS_ASSIGN expr
2764 {
2765 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2766 {
2767 notethat ("LOGI2op: dregs <<= uimm5\n");
2768 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2769 }
2770 else
2771 return yyerror ("Dregs expected or const value error");
2772 }
2773
2774
2775 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2776 {
2777 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2778 {
2779 notethat ("LOGI2op: dregs >>>= uimm5\n");
2780 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2781 }
2782 else
2783 return yyerror ("Dregs expected");
2784 }
2785
2786 /* Cache Control. */
2787
2788 | FLUSH LBRACK REG RBRACK
2789 {
2790 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2791 if (IS_PREG ($3))
2792 $$ = CACTRL (&$3, 0, 2);
2793 else
2794 return yyerror ("Bad register(s) for FLUSH");
2795 }
2796
2797 | FLUSH reg_with_postinc
2798 {
2799 if (IS_PREG ($2))
2800 {
2801 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2802 $$ = CACTRL (&$2, 1, 2);
2803 }
2804 else
2805 return yyerror ("Bad register(s) for FLUSH");
2806 }
2807
2808 | FLUSHINV LBRACK REG RBRACK
2809 {
2810 if (IS_PREG ($3))
2811 {
2812 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2813 $$ = CACTRL (&$3, 0, 1);
2814 }
2815 else
2816 return yyerror ("Bad register(s) for FLUSH");
2817 }
2818
2819 | FLUSHINV reg_with_postinc
2820 {
2821 if (IS_PREG ($2))
2822 {
2823 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2824 $$ = CACTRL (&$2, 1, 1);
2825 }
2826 else
2827 return yyerror ("Bad register(s) for FLUSH");
2828 }
2829
2830 /* CaCTRL: IFLUSH [pregs]. */
2831 | IFLUSH LBRACK REG RBRACK
2832 {
2833 if (IS_PREG ($3))
2834 {
2835 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2836 $$ = CACTRL (&$3, 0, 3);
2837 }
2838 else
2839 return yyerror ("Bad register(s) for FLUSH");
2840 }
2841
2842 | IFLUSH reg_with_postinc
2843 {
2844 if (IS_PREG ($2))
2845 {
2846 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2847 $$ = CACTRL (&$2, 1, 3);
2848 }
2849 else
2850 return yyerror ("Bad register(s) for FLUSH");
2851 }
2852
2853 | PREFETCH LBRACK REG RBRACK
2854 {
2855 if (IS_PREG ($3))
2856 {
2857 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2858 $$ = CACTRL (&$3, 0, 0);
2859 }
2860 else
2861 return yyerror ("Bad register(s) for PREFETCH");
2862 }
2863
2864 | PREFETCH reg_with_postinc
2865 {
2866 if (IS_PREG ($2))
2867 {
2868 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2869 $$ = CACTRL (&$2, 1, 0);
2870 }
2871 else
2872 return yyerror ("Bad register(s) for PREFETCH");
2873 }
2874
2875 /* LOAD/STORE. */
2876 /* LDST: B [ pregs <post_op> ] = dregs. */
2877
2878 | B LBRACK REG post_op RBRACK ASSIGN REG
2879 {
2880 if (IS_PREG ($3) && IS_DREG ($7))
2881 {
2882 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2883 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2884 }
2885 else
2886 return yyerror ("Register mismatch");
2887 }
2888
2889 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2890 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2891 {
2892 if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 1) && IS_DREG ($8))
2893 {
2894 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2895 if ($4.r0)
2896 neg_value ($5);
2897 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2898 }
2899 else
2900 return yyerror ("Register mismatch or const size wrong");
2901 }
2902
2903
2904 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
2905 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2906 {
2907 if (IS_PREG ($3) && IS_URANGE (4, $5, $4.r0, 2) && IS_DREG ($8))
2908 {
2909 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
2910 $$ = LDSTII (&$3, &$8, $5, 1, 1);
2911 }
2912 else if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 2) && IS_DREG ($8))
2913 {
2914 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
2915 if ($4.r0)
2916 neg_value ($5);
2917 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, $5);
2918 }
2919 else
2920 return yyerror ("Bad register(s) or wrong constant size");
2921 }
2922
2923 /* LDST: W [ pregs <post_op> ] = dregs. */
2924 | W LBRACK REG post_op RBRACK ASSIGN REG
2925 {
2926 if (IS_PREG ($3) && IS_DREG ($7))
2927 {
2928 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
2929 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
2930 }
2931 else
2932 return yyerror ("Bad register(s) for STORE");
2933 }
2934
2935 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
2936 {
2937 if (IS_IREG ($3))
2938 {
2939 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
2940 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
2941 }
2942 else if ($4.x0 == 2 && IS_PREG ($3) && IS_DREG ($7))
2943 {
2944 notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
2945 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
2946
2947 }
2948 else
2949 return yyerror ("Bad register(s) for STORE");
2950 }
2951
2952 /* LDSTiiFP: [ FP - const ] = dpregs. */
2953 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
2954 {
2955 Expr_Node *tmp = $4;
2956 int ispreg = IS_PREG ($7);
2957
2958 if (!IS_PREG ($2))
2959 return yyerror ("Preg expected for indirect");
2960
2961 if (!IS_DREG ($7) && !ispreg)
2962 return yyerror ("Bad source register for STORE");
2963
2964 if ($3.r0)
2965 tmp = unary (Expr_Op_Type_NEG, tmp);
2966
2967 if (in_range_p (tmp, 0, 63, 3))
2968 {
2969 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
2970 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
2971 }
2972 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
2973 {
2974 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
2975 tmp = unary (Expr_Op_Type_NEG, tmp);
2976 $$ = LDSTIIFP (tmp, &$7, 1);
2977 }
2978 else if (in_range_p (tmp, -131072, 131071, 3))
2979 {
2980 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
2981 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1: 0, tmp);
2982 }
2983 else
2984 return yyerror ("Displacement out of range for store");
2985 }
2986
2987 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
2988 {
2989 if (IS_DREG ($1) && IS_PREG ($5) && IS_URANGE (4, $7, $6.r0, 2))
2990 {
2991 notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
2992 $$ = LDSTII (&$5, &$1, $7, 0, 1 << $9.r0);
2993 }
2994 else if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 2))
2995 {
2996 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
2997 if ($6.r0)
2998 neg_value ($7);
2999 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, $7);
3000 }
3001 else
3002 return yyerror ("Bad register or constant for LOAD");
3003 }
3004
3005 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3006 {
3007 if (IS_IREG ($5))
3008 {
3009 notethat ("dspLDST: dregs_half = W [ iregs ]\n");
3010 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3011 }
3012 else if ($6.x0 == 2 && IS_DREG ($1) && IS_PREG ($5))
3013 {
3014 notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
3015 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3016 }
3017 else
3018 return yyerror ("Bad register or post_op for LOAD");
3019 }
3020
3021
3022 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3023 {
3024 if (IS_DREG ($1) && IS_PREG ($5))
3025 {
3026 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3027 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3028 }
3029 else
3030 return yyerror ("Bad register for LOAD");
3031 }
3032
3033 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3034 {
3035 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3036 {
3037 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3038 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3039 }
3040 else
3041 return yyerror ("Bad register for LOAD");
3042 }
3043
3044 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3045 {
3046 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3047 {
3048 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3049 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3050 }
3051 else
3052 return yyerror ("Bad register for LOAD");
3053 }
3054
3055 | LBRACK REG post_op RBRACK ASSIGN REG
3056 {
3057 if (IS_IREG ($2) && IS_DREG ($6))
3058 {
3059 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3060 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3061 }
3062 else if (IS_PREG ($2) && IS_DREG ($6))
3063 {
3064 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3065 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3066 }
3067 else if (IS_PREG ($2) && IS_PREG ($6))
3068 {
3069 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3070 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3071 }
3072 else
3073 return yyerror ("Bad register for STORE");
3074 }
3075
3076 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3077 {
3078 if (! IS_DREG ($7))
3079 return yyerror ("Expected Dreg for last argument");
3080
3081 if (IS_IREG ($2) && IS_MREG ($4))
3082 {
3083 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3084 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3085 }
3086 else if (IS_PREG ($2) && IS_PREG ($4))
3087 {
3088 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3089 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3090 }
3091 else
3092 return yyerror ("Bad register for STORE");
3093 }
3094
3095 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3096 {
3097 if (!IS_DREG ($8))
3098 return yyerror ("Expect Dreg as last argument");
3099 if (IS_PREG ($3) && IS_PREG ($5))
3100 {
3101 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3102 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3103 }
3104 else
3105 return yyerror ("Bad register for STORE");
3106 }
3107
3108 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3109 {
3110 if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 1))
3111 {
3112 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3113 $9.r0 ? 'X' : 'Z');
3114 if ($6.r0)
3115 neg_value ($7);
3116 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, $7);
3117 }
3118 else
3119 return yyerror ("Bad register or value for LOAD");
3120 }
3121
3122 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3123 {
3124 if (IS_DREG ($1) && IS_PREG ($5))
3125 {
3126 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3127 $8.r0 ? 'X' : 'Z');
3128 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3129 }
3130 else
3131 return yyerror ("Bad register for LOAD");
3132 }
3133
3134 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3135 {
3136 if (IS_DREG ($1) && IS_IREG ($4) && IS_MREG ($6))
3137 {
3138 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3139 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3140 }
3141 else if (IS_DREG ($1) && IS_PREG ($4) && IS_PREG ($6))
3142 {
3143 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3144 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3145 }
3146 else
3147 return yyerror ("Bad register for LOAD");
3148 }
3149
3150 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3151 {
3152 Expr_Node *tmp = $6;
3153 int ispreg = IS_PREG ($1);
3154 int isgot = IS_RELOC($6);
3155
3156 if (!IS_PREG ($4))
3157 return yyerror ("Preg expected for indirect");
3158
3159 if (!IS_DREG ($1) && !ispreg)
3160 return yyerror ("Bad destination register for LOAD");
3161
3162 if ($5.r0)
3163 tmp = unary (Expr_Op_Type_NEG, tmp);
3164
3165 if(isgot){
3166 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3167 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3168 }
3169 else if (in_range_p (tmp, 0, 63, 3))
3170 {
3171 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3172 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3173 }
3174 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3175 {
3176 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3177 tmp = unary (Expr_Op_Type_NEG, tmp);
3178 $$ = LDSTIIFP (tmp, &$1, 0);
3179 }
3180 else if (in_range_p (tmp, -131072, 131071, 3))
3181 {
3182 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3183 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3184
3185 }
3186 else
3187 return yyerror ("Displacement out of range for load");
3188 }
3189
3190 | REG ASSIGN LBRACK REG post_op RBRACK
3191 {
3192 if (IS_DREG ($1) && IS_IREG ($4))
3193 {
3194 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3195 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3196 }
3197 else if (IS_DREG ($1) && IS_PREG ($4))
3198 {
3199 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3200 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3201 }
3202 else if (IS_PREG ($1) && IS_PREG ($4))
3203 {
3204 if (REG_SAME ($1, $4) && $5.x0 != 2)
3205 return yyerror ("Pregs can't be same");
3206
3207 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3208 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3209 }
3210 else if ($4.regno == REG_SP && IS_ALLREG ($1) && $5.x0 == 0)
3211 {
3212 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3213 $$ = PUSHPOPREG (&$1, 0);
3214 }
3215 else
3216 return yyerror ("Bad register or value");
3217 }
3218
3219
3220
3221 /* Expression Assignment. */
3222
3223 | expr ASSIGN expr
3224 {
3225 bfin_equals ($1);
3226 $$ = 0;
3227 }
3228
3229
3230 /* PushPopMultiple. */
3231 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3232 {
3233 if ($1.regno != REG_SP)
3234 yyerror ("Stack Pointer expected");
3235 if ($4.regno == REG_R7
3236 && IN_RANGE ($6, 0, 7)
3237 && $8.regno == REG_P5
3238 && IN_RANGE ($10, 0, 5))
3239 {
3240 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3241 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3242 }
3243 else
3244 return yyerror ("Bad register for PushPopMultiple");
3245 }
3246
3247 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3248 {
3249 if ($1.regno != REG_SP)
3250 yyerror ("Stack Pointer expected");
3251
3252 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3253 {
3254 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3255 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3256 }
3257 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3258 {
3259 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3260 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3261 }
3262 else
3263 return yyerror ("Bad register for PushPopMultiple");
3264 }
3265
3266 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3267 {
3268 if ($11.regno != REG_SP)
3269 yyerror ("Stack Pointer expected");
3270 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3271 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3272 {
3273 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3274 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3275 }
3276 else
3277 return yyerror ("Bad register range for PushPopMultiple");
3278 }
3279
3280 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3281 {
3282 if ($7.regno != REG_SP)
3283 yyerror ("Stack Pointer expected");
3284
3285 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3286 {
3287 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3288 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3289 }
3290 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3291 {
3292 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3293 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3294 }
3295 else
3296 return yyerror ("Bad register range for PushPopMultiple");
3297 }
3298
3299 | reg_with_predec ASSIGN REG
3300 {
3301 if ($1.regno != REG_SP)
3302 yyerror ("Stack Pointer expected");
3303
3304 if (IS_ALLREG ($3))
3305 {
3306 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3307 $$ = PUSHPOPREG (&$3, 1);
3308 }
3309 else
3310 return yyerror ("Bad register for PushPopReg");
3311 }
3312
3313 /* Linkage. */
3314
3315 | LINK expr
3316 {
3317 if (IS_URANGE (16, $2, 0, 4))
3318 $$ = LINKAGE (0, uimm16s4 ($2));
3319 else
3320 return yyerror ("Bad constant for LINK");
3321 }
3322
3323 | UNLINK
3324 {
3325 notethat ("linkage: UNLINK\n");
3326 $$ = LINKAGE (1, 0);
3327 }
3328
3329
3330 /* LSETUP. */
3331
3332 | LSETUP LPAREN expr COMMA expr RPAREN REG
3333 {
3334 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3335 {
3336 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3337 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3338 }
3339 else
3340 return yyerror ("Bad register or values for LSETUP");
3341
3342 }
3343 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3344 {
3345 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3346 && IS_PREG ($9) && IS_CREG ($7))
3347 {
3348 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3349 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3350 }
3351 else
3352 return yyerror ("Bad register or values for LSETUP");
3353 }
3354
3355 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3356 {
3357 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3358 && IS_PREG ($9) && IS_CREG ($7)
3359 && EXPR_VALUE ($11) == 1)
3360 {
3361 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3362 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3363 }
3364 else
3365 return yyerror ("Bad register or values for LSETUP");
3366 }
3367
3368 /* LOOP. */
3369 | LOOP expr REG
3370 {
3371 if (!IS_RELOC ($2))
3372 return yyerror ("Invalid expression in loop statement");
3373 if (!IS_CREG ($3))
3374 return yyerror ("Invalid loop counter register");
3375 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3376 }
3377 | LOOP expr REG ASSIGN REG
3378 {
3379 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3380 {
3381 notethat ("Loop: LOOP expr counters = pregs\n");
3382 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3383 }
3384 else
3385 return yyerror ("Bad register or values for LOOP");
3386 }
3387 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3388 {
3389 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3390 {
3391 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3392 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3393 }
3394 else
3395 return yyerror ("Bad register or values for LOOP");
3396 }
3397 /* pseudoDEBUG. */
3398
3399 | DBG
3400 {
3401 notethat ("pseudoDEBUG: DBG\n");
3402 $$ = bfin_gen_pseudodbg (3, 7, 0);
3403 }
3404 | DBG REG_A
3405 {
3406 notethat ("pseudoDEBUG: DBG REG_A\n");
3407 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3408 }
3409 | DBG REG
3410 {
3411 notethat ("pseudoDEBUG: DBG allregs\n");
3412 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3413 }
3414
3415 | DBGCMPLX LPAREN REG RPAREN
3416 {
3417 if (!IS_DREG ($3))
3418 return yyerror ("Dregs expected");
3419 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3420 $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3421 }
3422
3423 | DBGHALT
3424 {
3425 notethat ("psedoDEBUG: DBGHALT\n");
3426 $$ = bfin_gen_pseudodbg (3, 5, 0);
3427 }
3428
3429 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3430 {
3431 notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3432 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3433 }
3434
3435 | DBGAH LPAREN REG COMMA expr RPAREN
3436 {
3437 notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3438 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3439 }
3440
3441 | DBGAL LPAREN REG COMMA expr RPAREN
3442 {
3443 notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3444 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3445 }
3446
3447
3448 ;
3449
3450 /* AUX RULES. */
3451
3452 /* Register rules. */
3453
3454 REG_A: REG_A_DOUBLE_ZERO
3455 {
3456 $$ = $1;
3457 }
3458 | REG_A_DOUBLE_ONE
3459 {
3460 $$ = $1;
3461 }
3462 ;
3463
3464
3465 /* Modifiers. */
3466
3467 opt_mode:
3468 {
3469 $$.MM = 0;
3470 $$.mod = 0;
3471 }
3472 | LPAREN M COMMA MMOD RPAREN
3473 {
3474 $$.MM = 1;
3475 $$.mod = $4;
3476 }
3477 | LPAREN MMOD COMMA M RPAREN
3478 {
3479 $$.MM = 1;
3480 $$.mod = $2;
3481 }
3482 | LPAREN MMOD RPAREN
3483 {
3484 $$.MM = 0;
3485 $$.mod = $2;
3486 }
3487 | LPAREN M RPAREN
3488 {
3489 $$.MM = 1;
3490 $$.mod = 0;
3491 }
3492 ;
3493
3494 asr_asl: LPAREN ASL RPAREN
3495 {
3496 $$.r0 = 1;
3497 }
3498 | LPAREN ASR RPAREN
3499 {
3500 $$.r0 = 0;
3501 }
3502 ;
3503
3504 sco:
3505 {
3506 $$.s0 = 0;
3507 $$.x0 = 0;
3508 }
3509 | S
3510 {
3511 $$.s0 = 1;
3512 $$.x0 = 0;
3513 }
3514 | CO
3515 {
3516 $$.s0 = 0;
3517 $$.x0 = 1;
3518 }
3519 | SCO
3520 {
3521 $$.s0 = 1;
3522 $$.x0 = 1;
3523 }
3524 ;
3525
3526 asr_asl_0:
3527 ASL
3528 {
3529 $$.r0 = 1;
3530 }
3531 | ASR
3532 {
3533 $$.r0 = 0;
3534 }
3535 ;
3536
3537 amod0:
3538 {
3539 $$.s0 = 0;
3540 $$.x0 = 0;
3541 }
3542 | LPAREN sco RPAREN
3543 {
3544 $$.s0 = $2.s0;
3545 $$.x0 = $2.x0;
3546 }
3547 ;
3548
3549 amod1:
3550 {
3551 $$.s0 = 0;
3552 $$.x0 = 0;
3553 $$.aop = 0;
3554 }
3555 | LPAREN NS RPAREN
3556 {
3557 $$.s0 = 0;
3558 $$.x0 = 0;
3559 $$.aop = 1;
3560 }
3561 | LPAREN S RPAREN
3562 {
3563 $$.s0 = 1;
3564 $$.x0 = 0;
3565 $$.aop = 1;
3566 }
3567 ;
3568
3569 amod2:
3570 {
3571 $$.r0 = 0;
3572 $$.s0 = 0;
3573 $$.x0 = 0;
3574 }
3575 | LPAREN asr_asl_0 RPAREN
3576 {
3577 $$.r0 = 2 + $2.r0;
3578 $$.s0 = 0;
3579 $$.x0 = 0;
3580 }
3581 | LPAREN sco RPAREN
3582 {
3583 $$.r0 = 0;
3584 $$.s0 = $2.s0;
3585 $$.x0 = $2.x0;
3586 }
3587 | LPAREN asr_asl_0 COMMA sco RPAREN
3588 {
3589 $$.r0 = 2 + $2.r0;
3590 $$.s0 = $4.s0;
3591 $$.x0 = $4.x0;
3592 }
3593 | LPAREN sco COMMA asr_asl_0 RPAREN
3594 {
3595 $$.r0 = 2 + $4.r0;
3596 $$.s0 = $2.s0;
3597 $$.x0 = $2.x0;
3598 }
3599 ;
3600
3601 xpmod:
3602 {
3603 $$.r0 = 0;
3604 }
3605 | LPAREN Z RPAREN
3606 {
3607 $$.r0 = 0;
3608 }
3609 | LPAREN X RPAREN
3610 {
3611 $$.r0 = 1;
3612 }
3613 ;
3614
3615 xpmod1:
3616 {
3617 $$.r0 = 0;
3618 }
3619 | LPAREN X RPAREN
3620 {
3621 $$.r0 = 0;
3622 }
3623 | LPAREN Z RPAREN
3624 {
3625 $$.r0 = 1;
3626 }
3627 ;
3628
3629 vsmod:
3630 {
3631 $$.r0 = 0;
3632 $$.s0 = 0;
3633 $$.aop = 0;
3634 }
3635 | LPAREN NS RPAREN
3636 {
3637 $$.r0 = 0;
3638 $$.s0 = 0;
3639 $$.aop = 3;
3640 }
3641 | LPAREN S RPAREN
3642 {
3643 $$.r0 = 0;
3644 $$.s0 = 1;
3645 $$.aop = 3;
3646 }
3647 | LPAREN V RPAREN
3648 {
3649 $$.r0 = 1;
3650 $$.s0 = 0;
3651 $$.aop = 3;
3652 }
3653 | LPAREN V COMMA S RPAREN
3654 {
3655 $$.r0 = 1;
3656 $$.s0 = 1;
3657 }
3658 | LPAREN S COMMA V RPAREN
3659 {
3660 $$.r0 = 1;
3661 $$.s0 = 1;
3662 }
3663 ;
3664
3665 vmod:
3666 {
3667 $$.r0 = 0;
3668 }
3669 | LPAREN V RPAREN
3670 {
3671 $$.r0 = 1;
3672 }
3673 ;
3674
3675 smod:
3676 {
3677 $$.s0 = 0;
3678 }
3679 | LPAREN S RPAREN
3680 {
3681 $$.s0 = 1;
3682 }
3683 ;
3684
3685 searchmod:
3686 GE
3687 {
3688 $$.r0 = 1;
3689 }
3690 | GT
3691 {
3692 $$.r0 = 0;
3693 }
3694 | LE
3695 {
3696 $$.r0 = 3;
3697 }
3698 | LT
3699 {
3700 $$.r0 = 2;
3701 }
3702 ;
3703
3704 aligndir:
3705 {
3706 $$.r0 = 0;
3707 }
3708 | LPAREN R RPAREN
3709 {
3710 $$.r0 = 1;
3711 }
3712 ;
3713
3714 byteop_mod:
3715 LPAREN R RPAREN
3716 {
3717 $$.r0 = 0;
3718 $$.s0 = 1;
3719 }
3720 | LPAREN MMOD RPAREN
3721 {
3722 if ($2 != M_T)
3723 return yyerror ("Bad modifier");
3724 $$.r0 = 1;
3725 $$.s0 = 0;
3726 }
3727 | LPAREN MMOD COMMA R RPAREN
3728 {
3729 if ($2 != M_T)
3730 return yyerror ("Bad modifier");
3731 $$.r0 = 1;
3732 $$.s0 = 1;
3733 }
3734 | LPAREN R COMMA MMOD RPAREN
3735 {
3736 if ($4 != M_T)
3737 return yyerror ("Bad modifier");
3738 $$.r0 = 1;
3739 $$.s0 = 1;
3740 }
3741 ;
3742
3743
3744
3745 c_align:
3746 ALIGN8
3747 {
3748 $$.r0 = 0;
3749 }
3750 | ALIGN16
3751 {
3752 $$.r0 = 1;
3753 }
3754 | ALIGN24
3755 {
3756 $$.r0 = 2;
3757 }
3758 ;
3759
3760 w32_or_nothing:
3761 {
3762 $$.r0 = 0;
3763 }
3764 | LPAREN MMOD RPAREN
3765 {
3766 if ($2 == M_W32)
3767 $$.r0 = 1;
3768 else
3769 return yyerror ("Only (W32) allowed");
3770 }
3771 ;
3772
3773 iu_or_nothing:
3774 {
3775 $$.r0 = 1;
3776 }
3777 | LPAREN MMOD RPAREN
3778 {
3779 if ($2 == M_IU)
3780 $$.r0 = 3;
3781 else
3782 return yyerror ("(IU) expected");
3783 }
3784 ;
3785
3786 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3787 {
3788 $$ = $3;
3789 }
3790 ;
3791
3792 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3793 {
3794 $$ = $2;
3795 }
3796 ;
3797
3798 /* Operators. */
3799
3800 min_max:
3801 MIN
3802 {
3803 $$.r0 = 1;
3804 }
3805 | MAX
3806 {
3807 $$.r0 = 0;
3808 }
3809 ;
3810
3811 op_bar_op:
3812 _PLUS_BAR_PLUS
3813 {
3814 $$.r0 = 0;
3815 }
3816 | _PLUS_BAR_MINUS
3817 {
3818 $$.r0 = 1;
3819 }
3820 | _MINUS_BAR_PLUS
3821 {
3822 $$.r0 = 2;
3823 }
3824 | _MINUS_BAR_MINUS
3825 {
3826 $$.r0 = 3;
3827 }
3828 ;
3829
3830 plus_minus:
3831 PLUS
3832 {
3833 $$.r0 = 0;
3834 }
3835 | MINUS
3836 {
3837 $$.r0 = 1;
3838 }
3839 ;
3840
3841 rnd_op:
3842 LPAREN RNDH RPAREN
3843 {
3844 $$.r0 = 1; /* HL. */
3845 $$.s0 = 0; /* s. */
3846 $$.x0 = 0; /* x. */
3847 $$.aop = 0; /* aop. */
3848 }
3849
3850 | LPAREN TH RPAREN
3851 {
3852 $$.r0 = 1; /* HL. */
3853 $$.s0 = 0; /* s. */
3854 $$.x0 = 0; /* x. */
3855 $$.aop = 1; /* aop. */
3856 }
3857
3858 | LPAREN RNDL RPAREN
3859 {
3860 $$.r0 = 0; /* HL. */
3861 $$.s0 = 0; /* s. */
3862 $$.x0 = 0; /* x. */
3863 $$.aop = 0; /* aop. */
3864 }
3865
3866 | LPAREN TL RPAREN
3867 {
3868 $$.r0 = 0; /* HL. */
3869 $$.s0 = 0; /* s. */
3870 $$.x0 = 0; /* x. */
3871 $$.aop = 1;
3872 }
3873
3874 | LPAREN RNDH COMMA R RPAREN
3875 {
3876 $$.r0 = 1; /* HL. */
3877 $$.s0 = 1; /* s. */
3878 $$.x0 = 0; /* x. */
3879 $$.aop = 0; /* aop. */
3880 }
3881 | LPAREN TH COMMA R RPAREN
3882 {
3883 $$.r0 = 1; /* HL. */
3884 $$.s0 = 1; /* s. */
3885 $$.x0 = 0; /* x. */
3886 $$.aop = 1; /* aop. */
3887 }
3888 | LPAREN RNDL COMMA R RPAREN
3889 {
3890 $$.r0 = 0; /* HL. */
3891 $$.s0 = 1; /* s. */
3892 $$.x0 = 0; /* x. */
3893 $$.aop = 0; /* aop. */
3894 }
3895
3896 | LPAREN TL COMMA R RPAREN
3897 {
3898 $$.r0 = 0; /* HL. */
3899 $$.s0 = 1; /* s. */
3900 $$.x0 = 0; /* x. */
3901 $$.aop = 1; /* aop. */
3902 }
3903 ;
3904
3905 b3_op:
3906 LPAREN LO RPAREN
3907 {
3908 $$.s0 = 0; /* s. */
3909 $$.x0 = 0; /* HL. */
3910 }
3911 | LPAREN HI RPAREN
3912 {
3913 $$.s0 = 0; /* s. */
3914 $$.x0 = 1; /* HL. */
3915 }
3916 | LPAREN LO COMMA R RPAREN
3917 {
3918 $$.s0 = 1; /* s. */
3919 $$.x0 = 0; /* HL. */
3920 }
3921 | LPAREN HI COMMA R RPAREN
3922 {
3923 $$.s0 = 1; /* s. */
3924 $$.x0 = 1; /* HL. */
3925 }
3926 ;
3927
3928 post_op:
3929 {
3930 $$.x0 = 2;
3931 }
3932 | _PLUS_PLUS
3933 {
3934 $$.x0 = 0;
3935 }
3936 | _MINUS_MINUS
3937 {
3938 $$.x0 = 1;
3939 }
3940 ;
3941
3942 /* Assignments, Macfuncs. */
3943
3944 a_assign:
3945 REG_A ASSIGN
3946 {
3947 $$ = $1;
3948 }
3949 ;
3950
3951 a_minusassign:
3952 REG_A _MINUS_ASSIGN
3953 {
3954 $$ = $1;
3955 }
3956 ;
3957
3958 a_plusassign:
3959 REG_A _PLUS_ASSIGN
3960 {
3961 $$ = $1;
3962 }
3963 ;
3964
3965 assign_macfunc:
3966 REG ASSIGN REG_A
3967 {
3968 $$.w = 1;
3969 $$.P = 1;
3970 $$.n = IS_A1 ($3);
3971 $$.op = 3;
3972 $$.dst = $1;
3973 $$.s0.regno = 0;
3974 $$.s1.regno = 0;
3975
3976 if (IS_A1 ($3) && IS_EVEN ($1))
3977 return yyerror ("Cannot move A1 to even register");
3978 else if (!IS_A1 ($3) && !IS_EVEN ($1))
3979 return yyerror ("Cannot move A0 to odd register");
3980 }
3981 | a_macfunc
3982 {
3983 $$ = $1;
3984 $$.w = 0; $$.P = 0;
3985 $$.dst.regno = 0;
3986 }
3987 | REG ASSIGN LPAREN a_macfunc RPAREN
3988 {
3989 $$ = $4;
3990 $$.w = 1;
3991 $$.P = 1;
3992 $$.dst = $1;
3993 }
3994
3995 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
3996 {
3997 $$ = $4;
3998 $$.w = 1;
3999 $$.P = 0;
4000 $$.dst = $1;
4001 }
4002
4003 | HALF_REG ASSIGN REG_A
4004 {
4005 $$.w = 1;
4006 $$.P = 0;
4007 $$.n = IS_A1 ($3);
4008 $$.op = 3;
4009 $$.dst = $1;
4010 $$.s0.regno = 0;
4011 $$.s1.regno = 0;
4012
4013 if (IS_A1 ($3) && !IS_H ($1))
4014 return yyerror ("Cannot move A1 to low half of register");
4015 else if (!IS_A1 ($3) && IS_H ($1))
4016 return yyerror ("Cannot move A0 to high half of register");
4017 }
4018 ;
4019
4020 a_macfunc:
4021 a_assign multiply_halfregs
4022 {
4023 $$.n = IS_A1 ($1);
4024 $$.op = 0;
4025 $$.s0 = $2.s0;
4026 $$.s1 = $2.s1;
4027 }
4028 | a_plusassign multiply_halfregs
4029 {
4030 $$.n = IS_A1 ($1);
4031 $$.op = 1;
4032 $$.s0 = $2.s0;
4033 $$.s1 = $2.s1;
4034 }
4035 | a_minusassign multiply_halfregs
4036 {
4037 $$.n = IS_A1 ($1);
4038 $$.op = 2;
4039 $$.s0 = $2.s0;
4040 $$.s1 = $2.s1;
4041 }
4042 ;
4043
4044 multiply_halfregs:
4045 HALF_REG STAR HALF_REG
4046 {
4047 if (IS_DREG ($1) && IS_DREG ($3))
4048 {
4049 $$.s0 = $1;
4050 $$.s1 = $3;
4051 }
4052 else
4053 return yyerror ("Dregs expected");
4054 }
4055 ;
4056
4057 cc_op:
4058 ASSIGN
4059 {
4060 $$.r0 = 0;
4061 }
4062 | _BAR_ASSIGN
4063 {
4064 $$.r0 = 1;
4065 }
4066 | _AMPERSAND_ASSIGN
4067 {
4068 $$.r0 = 2;
4069 }
4070 | _CARET_ASSIGN
4071 {
4072 $$.r0 = 3;
4073 }
4074 ;
4075
4076 ccstat:
4077 CCREG cc_op STATUS_REG
4078 {
4079 $$.r0 = $3.regno;
4080 $$.x0 = $2.r0;
4081 $$.s0 = 0;
4082 }
4083 | CCREG cc_op V
4084 {
4085 $$.r0 = 0x18;
4086 $$.x0 = $2.r0;
4087 $$.s0 = 0;
4088 }
4089 | STATUS_REG cc_op CCREG
4090 {
4091 $$.r0 = $1.regno;
4092 $$.x0 = $2.r0;
4093 $$.s0 = 1;
4094 }
4095 | V cc_op CCREG
4096 {
4097 $$.r0 = 0x18;
4098 $$.x0 = $2.r0;
4099 $$.s0 = 1;
4100 }
4101 ;
4102
4103 /* Expressions and Symbols. */
4104
4105 symbol: SYMBOL
4106 {
4107 Expr_Node_Value val;
4108 val.s_value = S_GET_NAME($1);
4109 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4110 }
4111 ;
4112
4113 got: symbol AT GOT
4114 {
4115 $$ = $1;
4116 }
4117 ;
4118
4119 got_or_expr: got
4120 {
4121 $$ = $1;
4122 }
4123 | expr
4124 {
4125 $$ = $1;
4126 }
4127 ;
4128
4129 pltpc :
4130 symbol AT PLTPC
4131 {
4132 $$ = $1;
4133 }
4134 ;
4135
4136 eterm: NUMBER
4137 {
4138 Expr_Node_Value val;
4139 val.i_value = $1;
4140 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4141 }
4142 | symbol
4143 {
4144 $$ = $1;
4145 }
4146 | LPAREN expr_1 RPAREN
4147 {
4148 $$ = $2;
4149 }
4150 | TILDA expr_1
4151 {
4152 $$ = unary (Expr_Op_Type_COMP, $2);
4153 }
4154 | MINUS expr_1 %prec TILDA
4155 {
4156 $$ = unary (Expr_Op_Type_NEG, $2);
4157 }
4158 ;
4159
4160 expr: expr_1
4161 {
4162 $$ = $1;
4163 }
4164 ;
4165
4166 expr_1: expr_1 STAR expr_1
4167 {
4168 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4169 }
4170 | expr_1 SLASH expr_1
4171 {
4172 $$ = binary (Expr_Op_Type_Div, $1, $3);
4173 }
4174 | expr_1 PERCENT expr_1
4175 {
4176 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4177 }
4178 | expr_1 PLUS expr_1
4179 {
4180 $$ = binary (Expr_Op_Type_Add, $1, $3);
4181 }
4182 | expr_1 MINUS expr_1
4183 {
4184 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4185 }
4186 | expr_1 LESS_LESS expr_1
4187 {
4188 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4189 }
4190 | expr_1 GREATER_GREATER expr_1
4191 {
4192 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4193 }
4194 | expr_1 AMPERSAND expr_1
4195 {
4196 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4197 }
4198 | expr_1 CARET expr_1
4199 {
4200 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4201 }
4202 | expr_1 BAR expr_1
4203 {
4204 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4205 }
4206 | eterm
4207 {
4208 $$ = $1;
4209 }
4210 ;
4211
4212
4213 %%
4214
4215 EXPR_T
4216 mkexpr (int x, SYMBOL_T s)
4217 {
4218 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4219 e->value = x;
4220 EXPR_SYMBOL(e) = s;
4221 return e;
4222 }
4223
4224 static int
4225 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4226 {
4227 long umax = (1L << sz) - 1;
4228 long min = -1L << (sz - 1);
4229 long max = (1L << (sz - 1)) - 1;
4230
4231 long v = EXPR_VALUE (expr);
4232
4233 if ((v % mul) != 0)
4234 {
4235 error ("%s:%d: Value Error -- Must align to %d\n", __LINE__, __FILE__, mul);
4236 return 0;
4237 }
4238
4239 v /= mul;
4240
4241 if (sign)
4242 v = -v;
4243
4244 if (issigned)
4245 {
4246 if (v >= min && v <= max) return 1;
4247
4248 #ifdef DEBUG
4249 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4250 #endif
4251 return 0;
4252 }
4253 if (v <= umax && v >= 0)
4254 return 1;
4255 #ifdef DEBUG
4256 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4257 #endif
4258 return 0;
4259 }
4260
4261 /* Return the expression structure that allows symbol operations.
4262 If the left and right children are constants, do the operation. */
4263 static Expr_Node *
4264 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4265 {
4266 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4267 {
4268 switch (op)
4269 {
4270 case Expr_Op_Type_Add:
4271 x->value.i_value += y->value.i_value;
4272 break;
4273 case Expr_Op_Type_Sub:
4274 x->value.i_value -= y->value.i_value;
4275 break;
4276 case Expr_Op_Type_Mult:
4277 x->value.i_value *= y->value.i_value;
4278 break;
4279 case Expr_Op_Type_Div:
4280 if (y->value.i_value == 0)
4281 error ("Illegal Expression: Division by zero.");
4282 else
4283 x->value.i_value /= y->value.i_value;
4284 break;
4285 case Expr_Op_Type_Mod:
4286 x->value.i_value %= y->value.i_value;
4287 break;
4288 case Expr_Op_Type_Lshift:
4289 x->value.i_value <<= y->value.i_value;
4290 break;
4291 case Expr_Op_Type_Rshift:
4292 x->value.i_value >>= y->value.i_value;
4293 break;
4294 case Expr_Op_Type_BAND:
4295 x->value.i_value &= y->value.i_value;
4296 break;
4297 case Expr_Op_Type_BOR:
4298 x->value.i_value |= y->value.i_value;
4299 break;
4300 case Expr_Op_Type_BXOR:
4301 x->value.i_value ^= y->value.i_value;
4302 break;
4303 case Expr_Op_Type_LAND:
4304 x->value.i_value = x->value.i_value && y->value.i_value;
4305 break;
4306 case Expr_Op_Type_LOR:
4307 x->value.i_value = x->value.i_value || y->value.i_value;
4308 break;
4309
4310 default:
4311 error ("%s:%d: Internal compiler error\n", __LINE__, __FILE__);
4312 }
4313 return x;
4314 }
4315 else
4316 {
4317 /* Create a new expression structure. */
4318 Expr_Node_Value val;
4319 val.op_value = op;
4320 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4321 }
4322 }
4323
4324 static Expr_Node *
4325 unary (Expr_Op_Type op, Expr_Node *x)
4326 {
4327 if (x->type == Expr_Node_Constant)
4328 {
4329 switch (op)
4330 {
4331 case Expr_Op_Type_NEG:
4332 x->value.i_value = -x->value.i_value;
4333 break;
4334 case Expr_Op_Type_COMP:
4335 x->value.i_value = ~x->value.i_value;
4336 break;
4337 default:
4338 error ("%s:%d: Internal compiler error\n", __LINE__, __FILE__);
4339 }
4340 return x;
4341 }
4342 else
4343 {
4344 /* Create a new expression structure. */
4345 Expr_Node_Value val;
4346 val.op_value = op;
4347 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4348 }
4349 }
4350
4351 int debug_codeselection = 0;
4352 static void
4353 notethat (char *format, ...)
4354 {
4355 va_list ap;
4356 va_start (ap, format);
4357 if (debug_codeselection)
4358 {
4359 vfprintf (errorf, format, ap);
4360 }
4361 va_end (ap);
4362 }
4363
4364 #ifdef TEST
4365 main (int argc, char **argv)
4366 {
4367 yyparse();
4368 }
4369 #endif
4370
GDB Binutils - Deliverables
This page took 0.170944 seconds and 5 git commands to generate.