1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii (ptr, reg, offset, w, op)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst (i, reg, aop, w, m)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp (reg, offset, w)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op (dst, src, opc)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc (t, b, offset)
81 #define UJUMP(offset) \
82 bfin_gen_ujump (offset)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl (prgfunc, poprnd)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg (reg, w)
93 #define CALLA(addr, s) \
94 bfin_gen_calla (addr, s)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage (r, framesize)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd (dst, src, op)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp (dst, src, op)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik (i, op)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim (i, m, op, br)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op (src0, src1, dst, opc)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op (dst, src, opc)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag (x, y, opc, i, g)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv (src, dst, t)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl (reg, a, op)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match(expr, bits, sign, mul, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match (expr, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match (expr, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match (expr, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match (expr, 24, 0, 2, 1))
155 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
161 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
163 static void notethat (char *format, ...);
165 char *current_inputline;
167 int yyerror (char *msg);
169 void error (char *format, ...)
172 static char buffer[2000];
174 va_start (ap, format);
175 vsprintf (buffer, format, ap);
178 as_bad ("%s", buffer);
187 else if (yytext[0] != ';')
188 error ("%s. Input text was %s.", msg, yytext);
196 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
198 int val = EXPR_VALUE (expr);
199 if (expr->type != Expr_Node_Constant)
201 if (val < from || val > to)
203 return (val & mask) == 0;
206 extern int yylex (void);
208 #define imm3(x) EXPR_VALUE (x)
209 #define imm4(x) EXPR_VALUE (x)
210 #define uimm4(x) EXPR_VALUE (x)
211 #define imm5(x) EXPR_VALUE (x)
212 #define uimm5(x) EXPR_VALUE (x)
213 #define imm6(x) EXPR_VALUE (x)
214 #define imm7(x) EXPR_VALUE (x)
215 #define imm16(x) EXPR_VALUE (x)
216 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
217 #define uimm16(x) EXPR_VALUE (x)
219 /* Return true if a value is inside a range. */
220 #define IN_RANGE(x, low, high) \
221 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
223 /* Auxiliary functions. */
226 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
228 if (!IS_DREG (*reg1))
230 yyerror ("Dregs expected");
234 if (reg1->regno != 1 && reg1->regno != 3)
236 yyerror ("Bad register pair");
240 if (imm7 (reg2) != reg1->regno - 1)
242 yyerror ("Bad register pair");
251 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
253 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
254 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
255 return yyerror ("Source multiplication register mismatch");
261 /* Check mac option. */
264 check_macfunc_option (Macfunc *a, Opt_mode *opt)
266 /* Default option is always valid. */
270 if ((a->w == 1 && a->P == 1
271 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
272 && opt->mod != M_S2RND && opt->mod != M_ISS2)
273 || (a->w == 1 && a->P == 0
274 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
275 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
276 && opt->mod != M_ISS2 && opt->mod != M_IH)
277 || (a->w == 0 && a->P == 0
278 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
284 /* Check (vector) mac funcs and ops. */
287 check_macfuncs (Macfunc *aa, Opt_mode *opa,
288 Macfunc *ab, Opt_mode *opb)
290 /* Variables for swapping. */
294 /* The option mode should be put at the end of the second instruction
295 of the vector except M, which should follow MAC1 instruction. */
297 return yyerror ("Bad opt mode");
299 /* If a0macfunc comes before a1macfunc, swap them. */
303 /* (M) is not allowed here. */
305 return yyerror ("(M) not allowed with A0MAC");
307 return yyerror ("Vector AxMACs can't be same");
309 mtmp = *aa; *aa = *ab; *ab = mtmp;
310 otmp = *opa; *opa = *opb; *opb = otmp;
315 return yyerror ("(M) not allowed with A0MAC");
317 return yyerror ("Vector AxMACs can't be same");
320 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
321 assignment_or_macfuncs. */
322 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
323 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
325 if (check_multiply_halfregs (aa, ab) < 0)
330 /* Only one of the assign_macfuncs has a half reg multiply
331 Evil trick: Just 'OR' their source register codes:
332 We can do that, because we know they were initialized to 0
333 in the rules that don't use multiply_halfregs. */
334 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
335 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
338 if (aa->w == ab->w && aa->P != ab->P)
340 return yyerror ("macfuncs must differ");
341 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
342 return yyerror ("Destination Dregs must differ by one");
345 /* Make sure mod flags get ORed, too. */
346 opb->mod |= opa->mod;
349 if (check_macfunc_option (aa, opb) < 0
350 && check_macfunc_option (ab, opb) < 0)
351 return yyerror ("bad option");
353 /* Make sure first macfunc has got both P flags ORed. */
361 is_group1 (INSTR_T x)
363 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
364 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
371 is_group2 (INSTR_T x)
373 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
374 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
375 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
376 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
377 || (x->value == 0x0000))
383 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
385 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
386 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
387 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
389 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
390 yyerror ("resource conflict in multi-issue instruction");
392 /* Anomaly 05000074 */
393 if (ENABLE_AC_05000074
394 && (dsp32->value & 0xf780) == 0xc680
395 && ((dsp16_grp1->value & 0xfe40) == 0x9240
396 || (dsp16_grp1->value & 0xfe08) == 0xba08
397 || (dsp16_grp1->value & 0xfc00) == 0xbc00))
398 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
399 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
401 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
413 struct { int r0; int s0; int x0; int aop; } modcodes;
414 struct { int r0; } r0;
421 /* Vector Specific. */
422 %token BYTEOP16P BYTEOP16M
423 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
424 %token BYTEUNPACK BYTEPACK
427 %token ALIGN8 ALIGN16 ALIGN24
429 %token EXTRACT DEPOSIT EXPADJ SEARCH
430 %token ONES SIGN SIGNBITS
438 %token CCREG BYTE_DREG
439 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
440 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
445 %token RTI RTS RTX RTN RTE
456 %token JUMP JUMP_DOT_S JUMP_DOT_L
463 %token NOT TILDA BANG
469 %token MINUS PLUS STAR SLASH
473 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
474 %token _MINUS_MINUS _PLUS_PLUS
476 /* Shift/rotate ops. */
477 %token SHIFT LSHIFT ASHIFT BXORSHIFT
478 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
480 %token LESS_LESS GREATER_GREATER
481 %token _GREATER_GREATER_GREATER
482 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
485 /* In place operators. */
486 %token ASSIGN _STAR_ASSIGN
487 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
488 %token _MINUS_ASSIGN _PLUS_ASSIGN
490 /* Assignments, comparisons. */
491 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
496 %token FLUSHINV FLUSH
497 %token IFLUSH PREFETCH
514 %token R RND RNDL RNDH RND12 RND20
519 %token BITTGL BITCLR BITSET BITTST BITMUX
522 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
524 /* Semantic auxiliaries. */
527 %token COLON SEMICOLON
528 %token RPAREN LPAREN LBRACK RBRACK
532 %token GOT GOT17M4 FUNCDESC_GOT17M4
542 %type <modcodes> byteop_mod
544 %type <reg> a_plusassign
545 %type <reg> a_minusassign
546 %type <macfunc> multiply_halfregs
547 %type <macfunc> assign_macfunc
548 %type <macfunc> a_macfunc
552 %type <modcodes> vsmod
553 %type <modcodes> ccstat
556 %type <reg> reg_with_postinc
557 %type <reg> reg_with_predec
561 %type <symbol> SYMBOL
564 %type <reg> BYTE_DREG
565 %type <reg> REG_A_DOUBLE_ZERO
566 %type <reg> REG_A_DOUBLE_ONE
568 %type <reg> STATUS_REG
572 %type <modcodes> smod
573 %type <modcodes> b3_op
574 %type <modcodes> rnd_op
575 %type <modcodes> post_op
577 %type <r0> iu_or_nothing
578 %type <r0> plus_minus
582 %type <modcodes> amod0
583 %type <modcodes> amod1
584 %type <modcodes> amod2
586 %type <r0> w32_or_nothing
590 %type <expr> got_or_expr
592 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
594 /* Precedence rules. */
598 %left LESS_LESS GREATER_GREATER
600 %left STAR SLASH PERCENT
611 if (insn == (INSTR_T) 0)
612 return NO_INSN_GENERATED;
613 else if (insn == (INSTR_T) - 1)
614 return SEMANTIC_ERROR;
616 return INSN_GENERATED;
621 /* Parallel instructions. */
622 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
624 if (($1->value & 0xf800) == 0xc000)
626 if (is_group1 ($3) && is_group2 ($5))
627 $$ = gen_multi_instr_1 ($1, $3, $5);
628 else if (is_group2 ($3) && is_group1 ($5))
629 $$ = gen_multi_instr_1 ($1, $5, $3);
631 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
633 else if (($3->value & 0xf800) == 0xc000)
635 if (is_group1 ($1) && is_group2 ($5))
636 $$ = gen_multi_instr_1 ($3, $1, $5);
637 else if (is_group2 ($1) && is_group1 ($5))
638 $$ = gen_multi_instr_1 ($3, $5, $1);
640 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
642 else if (($5->value & 0xf800) == 0xc000)
644 if (is_group1 ($1) && is_group2 ($3))
645 $$ = gen_multi_instr_1 ($5, $1, $3);
646 else if (is_group2 ($1) && is_group1 ($3))
647 $$ = gen_multi_instr_1 ($5, $3, $1);
649 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
652 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
655 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
657 if (($1->value & 0xf800) == 0xc000)
660 $$ = gen_multi_instr_1 ($1, $3, 0);
661 else if (is_group2 ($3))
662 $$ = gen_multi_instr_1 ($1, 0, $3);
664 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
666 else if (($3->value & 0xf800) == 0xc000)
669 $$ = gen_multi_instr_1 ($3, $1, 0);
670 else if (is_group2 ($1))
671 $$ = gen_multi_instr_1 ($3, 0, $1);
673 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
675 else if (is_group1 ($1) && is_group2 ($3))
676 $$ = gen_multi_instr_1 (0, $1, $3);
677 else if (is_group2 ($1) && is_group1 ($3))
678 $$ = gen_multi_instr_1 (0, $3, $1);
680 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
695 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
697 | assign_macfunc opt_mode
701 int h00, h10, h01, h11;
703 if (check_macfunc_option (&$1, &$2) < 0)
704 return yyerror ("bad option");
709 return yyerror ("(m) not allowed with a0 unit");
728 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
729 &$1.dst, op0, &$1.s0, &$1.s1, w0);
735 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
739 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
741 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
748 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
749 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
750 dst, $4.op, &$1.s0, &$1.s1, $4.w);
757 notethat ("dsp32alu: DISALGNEXCPT\n");
758 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
760 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
762 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
764 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
765 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
768 return yyerror ("Register mismatch");
770 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
772 if (!IS_A1 ($4) && IS_A1 ($5))
774 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
775 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
778 return yyerror ("Register mismatch");
780 | A_ZERO_DOT_H ASSIGN HALF_REG
782 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
783 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
785 | A_ONE_DOT_H ASSIGN HALF_REG
787 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
788 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
790 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
791 COLON expr COMMA REG COLON expr RPAREN aligndir
793 if (!IS_DREG ($2) || !IS_DREG ($4))
794 return yyerror ("Dregs expected");
795 else if (!valid_dreg_pair (&$9, $11))
796 return yyerror ("Bad dreg pair");
797 else if (!valid_dreg_pair (&$13, $15))
798 return yyerror ("Bad dreg pair");
801 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
802 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
806 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
807 REG COLON expr RPAREN aligndir
809 if (!IS_DREG ($2) || !IS_DREG ($4))
810 return yyerror ("Dregs expected");
811 else if (!valid_dreg_pair (&$9, $11))
812 return yyerror ("Bad dreg pair");
813 else if (!valid_dreg_pair (&$13, $15))
814 return yyerror ("Bad dreg pair");
817 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
818 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
822 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
824 if (!IS_DREG ($2) || !IS_DREG ($4))
825 return yyerror ("Dregs expected");
826 else if (!valid_dreg_pair (&$8, $10))
827 return yyerror ("Bad dreg pair");
830 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
831 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
834 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
836 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
838 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
839 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
842 return yyerror ("Register mismatch");
844 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
845 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
847 if (IS_DREG ($1) && IS_DREG ($7))
849 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
850 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
853 return yyerror ("Register mismatch");
857 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
859 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
860 && IS_A1 ($9) && !IS_A1 ($11))
862 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
863 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
866 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
867 && !IS_A1 ($9) && IS_A1 ($11))
869 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
870 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
873 return yyerror ("Register mismatch");
876 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
879 return yyerror ("Operators must differ");
881 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
882 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
884 notethat ("dsp32alu: dregs = dregs + dregs,"
885 "dregs = dregs - dregs (amod1)\n");
886 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
889 return yyerror ("Register mismatch");
892 /* Bar Operations. */
894 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
896 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
897 return yyerror ("Differing source registers");
899 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
900 return yyerror ("Dregs expected");
903 if ($4.r0 == 1 && $10.r0 == 2)
905 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
906 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
908 else if ($4.r0 == 0 && $10.r0 == 3)
910 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
911 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
914 return yyerror ("Bar operand mismatch");
917 | REG ASSIGN ABS REG vmod
921 if (IS_DREG ($1) && IS_DREG ($4))
925 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
930 /* Vector version of ABS. */
931 notethat ("dsp32alu: dregs = ABS dregs\n");
934 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
937 return yyerror ("Dregs expected");
941 notethat ("dsp32alu: Ax = ABS Ax\n");
942 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
944 | A_ZERO_DOT_L ASSIGN HALF_REG
948 notethat ("dsp32alu: A0.l = reg_half\n");
949 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
952 return yyerror ("A0.l = Rx.l expected");
954 | A_ONE_DOT_L ASSIGN HALF_REG
958 notethat ("dsp32alu: A1.l = reg_half\n");
959 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
962 return yyerror ("A1.l = Rx.l expected");
965 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
967 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
969 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
970 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
973 return yyerror ("Dregs expected");
976 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
979 return yyerror ("Dregs expected");
980 else if (!valid_dreg_pair (&$5, $7))
981 return yyerror ("Bad dreg pair");
982 else if (!valid_dreg_pair (&$9, $11))
983 return yyerror ("Bad dreg pair");
986 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
987 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
990 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
993 return yyerror ("Dregs expected");
994 else if (!valid_dreg_pair (&$5, $7))
995 return yyerror ("Bad dreg pair");
996 else if (!valid_dreg_pair (&$9, $11))
997 return yyerror ("Bad dreg pair");
1000 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1001 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1005 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1009 return yyerror ("Dregs expected");
1010 else if (!valid_dreg_pair (&$5, $7))
1011 return yyerror ("Bad dreg pair");
1012 else if (!valid_dreg_pair (&$9, $11))
1013 return yyerror ("Bad dreg pair");
1016 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1017 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1021 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1025 return yyerror ("Dregs expected");
1026 else if (!valid_dreg_pair (&$5, $7))
1027 return yyerror ("Bad dreg pair");
1028 else if (!valid_dreg_pair (&$9, $11))
1029 return yyerror ("Bad dreg pair");
1032 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1033 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
1037 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1041 return yyerror ("Dregs expected");
1042 else if (!valid_dreg_pair (&$5, $7))
1043 return yyerror ("Bad dreg pair");
1044 else if (!valid_dreg_pair (&$9, $11))
1045 return yyerror ("Bad dreg pair");
1048 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1049 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1053 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1055 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1057 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1058 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1061 return yyerror ("Dregs expected");
1064 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1065 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1067 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1069 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1070 "SIGN (dregs_hi) * dregs_hi + "
1071 "SIGN (dregs_lo) * dregs_lo \n");
1073 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1076 return yyerror ("Dregs expected");
1078 | REG ASSIGN REG plus_minus REG amod1
1080 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1084 /* No saturation flag specified, generate the 16 bit variant. */
1085 notethat ("COMP3op: dregs = dregs +- dregs\n");
1086 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1090 /* Saturation flag specified, generate the 32 bit variant. */
1091 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1092 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1096 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1098 notethat ("COMP3op: pregs = pregs + pregs\n");
1099 $$ = COMP3OP (&$1, &$3, &$5, 5);
1102 return yyerror ("Dregs expected");
1104 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1108 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1115 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1116 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1119 return yyerror ("Dregs expected");
1122 | a_assign MINUS REG_A
1124 notethat ("dsp32alu: Ax = - Ax\n");
1125 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1127 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1129 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1130 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1131 $6.s0, $6.x0, HL2 ($3, $5));
1133 | a_assign a_assign expr
1135 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1137 notethat ("dsp32alu: A1 = A0 = 0\n");
1138 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1141 return yyerror ("Bad value, 0 expected");
1145 | a_assign REG_A LPAREN S RPAREN
1147 if (REG_SAME ($1, $2))
1149 notethat ("dsp32alu: Ax = Ax (S)\n");
1150 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1153 return yyerror ("Registers must be equal");
1156 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1160 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1161 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1164 return yyerror ("Dregs expected");
1167 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1169 if (IS_DREG ($3) && IS_DREG ($5))
1171 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1172 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1175 return yyerror ("Dregs expected");
1178 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1180 if (IS_DREG ($3) && IS_DREG ($5))
1182 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1183 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1186 return yyerror ("Dregs expected");
1191 if (!REG_SAME ($1, $2))
1193 notethat ("dsp32alu: An = Am\n");
1194 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1197 return yyerror ("Accu reg arguments must differ");
1204 notethat ("dsp32alu: An = dregs\n");
1205 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1208 return yyerror ("Dregs expected");
1211 | REG ASSIGN HALF_REG xpmod
1215 if ($1.regno == REG_A0x && IS_DREG ($3))
1217 notethat ("dsp32alu: A0.x = dregs_lo\n");
1218 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1220 else if ($1.regno == REG_A1x && IS_DREG ($3))
1222 notethat ("dsp32alu: A1.x = dregs_lo\n");
1223 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1225 else if (IS_DREG ($1) && IS_DREG ($3))
1227 notethat ("ALU2op: dregs = dregs_lo\n");
1228 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1231 return yyerror ("Register mismatch");
1234 return yyerror ("Low reg expected");
1237 | HALF_REG ASSIGN expr
1239 notethat ("LDIMMhalf: pregs_half = imm16\n");
1241 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1242 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1243 return yyerror ("Wrong register for load immediate");
1245 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1246 return yyerror ("Constant out of range");
1248 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1253 notethat ("dsp32alu: An = 0\n");
1256 return yyerror ("0 expected");
1258 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1261 | REG ASSIGN expr xpmod1
1263 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1264 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1265 return yyerror ("Wrong register for load immediate");
1269 /* 7 bit immediate value if possible.
1270 We will check for that constant value for efficiency
1271 If it goes to reloc, it will be 16 bit. */
1272 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1274 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1275 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1277 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1279 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1280 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1284 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1285 return yyerror ("Immediate value out of range");
1287 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1289 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1294 /* (z) There is no 7 bit zero extended instruction.
1295 If the expr is a relocation, generate it. */
1297 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1298 return yyerror ("Immediate value out of range");
1300 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1302 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1306 | HALF_REG ASSIGN REG
1309 return yyerror ("Low reg expected");
1311 if (IS_DREG ($1) && $3.regno == REG_A0x)
1313 notethat ("dsp32alu: dregs_lo = A0.x\n");
1314 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1316 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1318 notethat ("dsp32alu: dregs_lo = A1.x\n");
1319 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1322 return yyerror ("Register mismatch");
1325 | REG ASSIGN REG op_bar_op REG amod0
1327 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1329 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1330 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1333 return yyerror ("Register mismatch");
1336 | REG ASSIGN BYTE_DREG xpmod
1338 if (IS_DREG ($1) && IS_DREG ($3))
1340 notethat ("ALU2op: dregs = dregs_byte\n");
1341 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1344 return yyerror ("Register mismatch");
1347 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1349 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1351 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1352 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1355 return yyerror ("Register mismatch");
1358 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1360 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1362 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1363 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1366 return yyerror ("Register mismatch");
1369 | a_minusassign REG_A w32_or_nothing
1371 if (!IS_A1 ($1) && IS_A1 ($2))
1373 notethat ("dsp32alu: A0 -= A1\n");
1374 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1377 return yyerror ("Register mismatch");
1380 | REG _MINUS_ASSIGN expr
1382 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1384 notethat ("dagMODik: iregs -= 4\n");
1385 $$ = DAGMODIK (&$1, 3);
1387 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1389 notethat ("dagMODik: iregs -= 2\n");
1390 $$ = DAGMODIK (&$1, 1);
1393 return yyerror ("Register or value mismatch");
1396 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1398 if (IS_IREG ($1) && IS_MREG ($3))
1400 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1402 $$ = DAGMODIM (&$1, &$3, 0, 1);
1404 else if (IS_PREG ($1) && IS_PREG ($3))
1406 notethat ("PTR2op: pregs += pregs (BREV )\n");
1407 $$ = PTR2OP (&$1, &$3, 5);
1410 return yyerror ("Register mismatch");
1413 | REG _MINUS_ASSIGN REG
1415 if (IS_IREG ($1) && IS_MREG ($3))
1417 notethat ("dagMODim: iregs -= mregs\n");
1418 $$ = DAGMODIM (&$1, &$3, 1, 0);
1420 else if (IS_PREG ($1) && IS_PREG ($3))
1422 notethat ("PTR2op: pregs -= pregs\n");
1423 $$ = PTR2OP (&$1, &$3, 0);
1426 return yyerror ("Register mismatch");
1429 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1431 if (!IS_A1 ($1) && IS_A1 ($3))
1433 notethat ("dsp32alu: A0 += A1 (W32)\n");
1434 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1437 return yyerror ("Register mismatch");
1440 | REG _PLUS_ASSIGN REG
1442 if (IS_IREG ($1) && IS_MREG ($3))
1444 notethat ("dagMODim: iregs += mregs\n");
1445 $$ = DAGMODIM (&$1, &$3, 0, 0);
1448 return yyerror ("iregs += mregs expected");
1451 | REG _PLUS_ASSIGN expr
1455 if (EXPR_VALUE ($3) == 4)
1457 notethat ("dagMODik: iregs += 4\n");
1458 $$ = DAGMODIK (&$1, 2);
1460 else if (EXPR_VALUE ($3) == 2)
1462 notethat ("dagMODik: iregs += 2\n");
1463 $$ = DAGMODIK (&$1, 0);
1466 return yyerror ("iregs += [ 2 | 4 ");
1468 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1470 notethat ("COMPI2opP: pregs += imm7\n");
1471 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1473 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1475 notethat ("COMPI2opD: dregs += imm7\n");
1476 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1478 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1479 return yyerror ("Immediate value out of range");
1481 return yyerror ("Register mismatch");
1484 | REG _STAR_ASSIGN REG
1486 if (IS_DREG ($1) && IS_DREG ($3))
1488 notethat ("ALU2op: dregs *= dregs\n");
1489 $$ = ALU2OP (&$1, &$3, 3);
1492 return yyerror ("Register mismatch");
1495 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1497 if (!valid_dreg_pair (&$3, $5))
1498 return yyerror ("Bad dreg pair");
1499 else if (!valid_dreg_pair (&$7, $9))
1500 return yyerror ("Bad dreg pair");
1503 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1504 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1508 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1510 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1512 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1513 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1516 return yyerror ("Register mismatch");
1519 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1521 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1522 && REG_SAME ($1, $4))
1524 if (EXPR_VALUE ($9) == 1)
1526 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1527 $$ = ALU2OP (&$1, &$6, 4);
1529 else if (EXPR_VALUE ($9) == 2)
1531 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1532 $$ = ALU2OP (&$1, &$6, 5);
1535 return yyerror ("Bad shift value");
1537 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1538 && REG_SAME ($1, $4))
1540 if (EXPR_VALUE ($9) == 1)
1542 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1543 $$ = PTR2OP (&$1, &$6, 6);
1545 else if (EXPR_VALUE ($9) == 2)
1547 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1548 $$ = PTR2OP (&$1, &$6, 7);
1551 return yyerror ("Bad shift value");
1554 return yyerror ("Register mismatch");
1558 | REG ASSIGN REG BAR REG
1560 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1562 notethat ("COMP3op: dregs = dregs | dregs\n");
1563 $$ = COMP3OP (&$1, &$3, &$5, 3);
1566 return yyerror ("Dregs expected");
1568 | REG ASSIGN REG CARET REG
1570 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1572 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1573 $$ = COMP3OP (&$1, &$3, &$5, 4);
1576 return yyerror ("Dregs expected");
1578 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1580 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1582 if (EXPR_VALUE ($8) == 1)
1584 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1585 $$ = COMP3OP (&$1, &$3, &$6, 6);
1587 else if (EXPR_VALUE ($8) == 2)
1589 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1590 $$ = COMP3OP (&$1, &$3, &$6, 7);
1593 return yyerror ("Bad shift value");
1596 return yyerror ("Dregs expected");
1598 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1600 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1602 notethat ("CCflag: CC = A0 == A1\n");
1603 $$ = CCFLAG (0, 0, 5, 0, 0);
1606 return yyerror ("AREGs are in bad order or same");
1608 | CCREG ASSIGN REG_A LESS_THAN REG_A
1610 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1612 notethat ("CCflag: CC = A0 < A1\n");
1613 $$ = CCFLAG (0, 0, 6, 0, 0);
1616 return yyerror ("AREGs are in bad order or same");
1618 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1620 if ((IS_DREG ($3) && IS_DREG ($5))
1621 || (IS_PREG ($3) && IS_PREG ($5)))
1623 notethat ("CCflag: CC = dpregs < dpregs\n");
1624 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1627 return yyerror ("Bad register in comparison");
1629 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1631 if (!IS_DREG ($3) && !IS_PREG ($3))
1632 return yyerror ("Bad register in comparison");
1634 if (($6.r0 == 1 && IS_IMM ($5, 3))
1635 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1637 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1638 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1641 return yyerror ("Bad constant value");
1643 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1645 if ((IS_DREG ($3) && IS_DREG ($5))
1646 || (IS_PREG ($3) && IS_PREG ($5)))
1648 notethat ("CCflag: CC = dpregs == dpregs\n");
1649 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1652 return yyerror ("Bad register in comparison");
1654 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1656 if (!IS_DREG ($3) && !IS_PREG ($3))
1657 return yyerror ("Bad register in comparison");
1661 notethat ("CCflag: CC = dpregs == imm3\n");
1662 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1665 return yyerror ("Bad constant range");
1667 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1669 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1671 notethat ("CCflag: CC = A0 <= A1\n");
1672 $$ = CCFLAG (0, 0, 7, 0, 0);
1675 return yyerror ("AREGs are in bad order or same");
1677 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1679 if ((IS_DREG ($3) && IS_DREG ($5))
1680 || (IS_PREG ($3) && IS_PREG ($5)))
1682 notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1683 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1684 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1687 return yyerror ("Bad register in comparison");
1689 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1691 if (!IS_DREG ($3) && !IS_PREG ($3))
1692 return yyerror ("Bad register in comparison");
1694 if (($6.r0 == 1 && IS_IMM ($5, 3))
1695 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1697 notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1698 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1701 return yyerror ("Bad constant value");
1704 | REG ASSIGN REG AMPERSAND REG
1706 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1708 notethat ("COMP3op: dregs = dregs & dregs\n");
1709 $$ = COMP3OP (&$1, &$3, &$5, 2);
1712 return yyerror ("Dregs expected");
1717 notethat ("CC2stat operation\n");
1718 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1723 if ((IS_GENREG ($1) && IS_GENREG ($3))
1724 || (IS_GENREG ($1) && IS_DAGREG ($3))
1725 || (IS_DAGREG ($1) && IS_GENREG ($3))
1726 || (IS_DAGREG ($1) && IS_DAGREG ($3))
1727 || (IS_GENREG ($1) && $3.regno == REG_USP)
1728 || ($1.regno == REG_USP && IS_GENREG ($3))
1729 || (IS_DREG ($1) && IS_SYSREG ($3))
1730 || (IS_PREG ($1) && IS_SYSREG ($3))
1731 || (IS_SYSREG ($1) && IS_DREG ($3))
1732 || (IS_SYSREG ($1) && IS_PREG ($3))
1733 || (IS_SYSREG ($1) && $3.regno == REG_USP))
1735 $$ = bfin_gen_regmv (&$3, &$1);
1738 return yyerror ("Register mismatch");
1745 notethat ("CC2dreg: CC = dregs\n");
1746 $$ = bfin_gen_cc2dreg (1, &$3);
1749 return yyerror ("Register mismatch");
1756 notethat ("CC2dreg: dregs = CC\n");
1757 $$ = bfin_gen_cc2dreg (0, &$1);
1760 return yyerror ("Register mismatch");
1763 | CCREG _ASSIGN_BANG CCREG
1765 notethat ("CC2dreg: CC =! CC\n");
1766 $$ = bfin_gen_cc2dreg (3, 0);
1771 | HALF_REG ASSIGN multiply_halfregs opt_mode
1773 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1775 if (!IS_H ($1) && $4.MM)
1776 return yyerror ("(M) not allowed with MAC0");
1778 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1779 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1780 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1781 return yyerror ("bad option.");
1785 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1786 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1787 &$1, 0, &$3.s0, &$3.s1, 0);
1791 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1792 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1793 &$1, 0, &$3.s0, &$3.s1, 1);
1797 | REG ASSIGN multiply_halfregs opt_mode
1799 /* Odd registers can use (M). */
1801 return yyerror ("Dreg expected");
1803 if (IS_EVEN ($1) && $4.MM)
1804 return yyerror ("(M) not allowed with MAC0");
1806 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1807 && $4.mod != M_S2RND && $4.mod != M_ISS2)
1808 return yyerror ("bad option");
1812 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1814 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1815 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1816 &$1, 0, &$3.s0, &$3.s1, 0);
1820 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1821 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1822 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1823 &$1, 0, &$3.s0, &$3.s1, 1);
1827 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1828 HALF_REG ASSIGN multiply_halfregs opt_mode
1830 if (!IS_DREG ($1) || !IS_DREG ($6))
1831 return yyerror ("Dregs expected");
1833 if (!IS_HCOMPL($1, $6))
1834 return yyerror ("Dest registers mismatch");
1836 if (check_multiply_halfregs (&$3, &$8) < 0)
1839 if ((!IS_H ($1) && $4.MM)
1840 || (!IS_H ($6) && $9.MM))
1841 return yyerror ("(M) not allowed with MAC0");
1843 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1844 "dregs_lo = multiply_halfregs opt_mode\n");
1847 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1848 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1849 &$1, 0, &$3.s0, &$3.s1, 1);
1851 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1852 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1853 &$1, 0, &$3.s0, &$3.s1, 1);
1856 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1858 if (!IS_DREG ($1) || !IS_DREG ($6))
1859 return yyerror ("Dregs expected");
1861 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1862 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1863 return yyerror ("Dest registers mismatch");
1865 if (check_multiply_halfregs (&$3, &$8) < 0)
1868 if ((IS_EVEN ($1) && $4.MM)
1869 || (IS_EVEN ($6) && $9.MM))
1870 return yyerror ("(M) not allowed with MAC0");
1872 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1873 "dregs = multiply_halfregs opt_mode\n");
1876 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1877 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1878 &$1, 0, &$3.s0, &$3.s1, 1);
1880 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1881 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1882 &$1, 0, &$3.s0, &$3.s1, 1);
1887 | a_assign ASHIFT REG_A BY HALF_REG
1889 if (!REG_SAME ($1, $3))
1890 return yyerror ("Aregs must be same");
1892 if (IS_DREG ($5) && !IS_H ($5))
1894 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1895 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1898 return yyerror ("Dregs expected");
1901 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1903 if (IS_DREG ($6) && !IS_H ($6))
1905 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1906 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1909 return yyerror ("Dregs expected");
1912 | a_assign REG_A LESS_LESS expr
1914 if (!REG_SAME ($1, $2))
1915 return yyerror ("Aregs must be same");
1917 if (IS_UIMM ($4, 5))
1919 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1920 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1923 return yyerror ("Bad shift value");
1926 | REG ASSIGN REG LESS_LESS expr vsmod
1928 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1933 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1934 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1938 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1939 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1942 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1944 if (EXPR_VALUE ($5) == 2)
1946 notethat ("PTR2op: pregs = pregs << 2\n");
1947 $$ = PTR2OP (&$1, &$3, 1);
1949 else if (EXPR_VALUE ($5) == 1)
1951 notethat ("COMP3op: pregs = pregs << 1\n");
1952 $$ = COMP3OP (&$1, &$3, &$3, 5);
1955 return yyerror ("Bad shift value");
1958 return yyerror ("Bad shift value or register");
1960 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1962 if (IS_UIMM ($5, 4))
1966 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
1967 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1971 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1972 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1976 return yyerror ("Bad shift value");
1978 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1982 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1987 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1988 "dregs_lo (V, .)\n");
1994 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1996 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1999 return yyerror ("Dregs expected");
2003 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2005 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2007 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2008 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2011 return yyerror ("Bad shift value or register");
2015 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2017 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2019 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2020 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2022 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2024 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2025 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2028 return yyerror ("Bad shift value or register");
2033 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2035 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2037 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2038 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2041 return yyerror ("Register mismatch");
2044 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2046 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2048 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2049 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2052 return yyerror ("Register mismatch");
2055 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2057 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2059 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2060 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2063 return yyerror ("Register mismatch");
2066 | a_assign REG_A _GREATER_GREATER_GREATER expr
2068 if (!REG_SAME ($1, $2))
2069 return yyerror ("Aregs must be same");
2071 if (IS_UIMM ($4, 5))
2073 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2074 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2077 return yyerror ("Shift value range error");
2079 | a_assign LSHIFT REG_A BY HALF_REG
2081 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2083 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2084 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2087 return yyerror ("Register mismatch");
2090 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2092 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2094 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2095 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2098 return yyerror ("Register mismatch");
2101 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2103 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2105 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2106 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2109 return yyerror ("Register mismatch");
2112 | REG ASSIGN SHIFT REG BY HALF_REG
2114 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2116 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2117 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2120 return yyerror ("Register mismatch");
2123 | a_assign REG_A GREATER_GREATER expr
2125 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2127 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2128 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2131 return yyerror ("Accu register expected");
2134 | REG ASSIGN REG GREATER_GREATER expr vmod
2138 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2140 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2141 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2144 return yyerror ("Register mismatch");
2148 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2150 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2151 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2153 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2155 notethat ("PTR2op: pregs = pregs >> 2\n");
2156 $$ = PTR2OP (&$1, &$3, 3);
2158 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2160 notethat ("PTR2op: pregs = pregs >> 1\n");
2161 $$ = PTR2OP (&$1, &$3, 4);
2164 return yyerror ("Register mismatch");
2167 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2169 if (IS_UIMM ($5, 5))
2171 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2172 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2175 return yyerror ("Register mismatch");
2177 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2179 if (IS_UIMM ($5, 5))
2181 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2182 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2183 $6.s0, HL2 ($1, $3));
2186 return yyerror ("Register or modifier mismatch");
2190 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2192 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2197 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2198 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2202 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2203 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2207 return yyerror ("Register mismatch");
2210 | HALF_REG ASSIGN ONES REG
2212 if (IS_DREG_L ($1) && IS_DREG ($4))
2214 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2215 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2218 return yyerror ("Register mismatch");
2221 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2223 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2225 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2226 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2229 return yyerror ("Register mismatch");
2232 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2235 && $7.regno == REG_A0
2236 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2238 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2239 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2242 return yyerror ("Register mismatch");
2245 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2248 && $7.regno == REG_A0
2249 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2251 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2252 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2255 return yyerror ("Register mismatch");
2258 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2260 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2262 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2263 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2266 return yyerror ("Register mismatch");
2269 | a_assign ROT REG_A BY HALF_REG
2271 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2273 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2274 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2277 return yyerror ("Register mismatch");
2280 | REG ASSIGN ROT REG BY HALF_REG
2282 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2284 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2285 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2288 return yyerror ("Register mismatch");
2291 | a_assign ROT REG_A BY expr
2295 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2296 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2299 return yyerror ("Register mismatch");
2302 | REG ASSIGN ROT REG BY expr
2304 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2306 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2309 return yyerror ("Register mismatch");
2312 | HALF_REG ASSIGN SIGNBITS REG_A
2316 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2317 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2320 return yyerror ("Register mismatch");
2323 | HALF_REG ASSIGN SIGNBITS REG
2325 if (IS_DREG_L ($1) && IS_DREG ($4))
2327 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2328 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2331 return yyerror ("Register mismatch");
2334 | HALF_REG ASSIGN SIGNBITS HALF_REG
2338 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2339 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2342 return yyerror ("Register mismatch");
2345 /* The ASR bit is just inverted here. */
2346 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2348 if (IS_DREG_L ($1) && IS_DREG ($5))
2350 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2351 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2354 return yyerror ("Register mismatch");
2357 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2359 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2361 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2362 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2365 return yyerror ("Register mismatch");
2368 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2370 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2372 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2373 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2376 return yyerror ("Register mismatch");
2379 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2381 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2383 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2384 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2387 return yyerror ("Dregs expected");
2391 /* LOGI2op: BITCLR (dregs, uimm5). */
2392 | BITCLR LPAREN REG COMMA expr RPAREN
2394 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2396 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2397 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2400 return yyerror ("Register mismatch");
2403 /* LOGI2op: BITSET (dregs, uimm5). */
2404 | BITSET LPAREN REG COMMA expr RPAREN
2406 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2408 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2409 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2412 return yyerror ("Register mismatch");
2415 /* LOGI2op: BITTGL (dregs, uimm5). */
2416 | BITTGL LPAREN REG COMMA expr RPAREN
2418 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2420 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2421 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2424 return yyerror ("Register mismatch");
2427 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2429 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2431 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2432 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2435 return yyerror ("Register mismatch or value error");
2438 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2440 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2442 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2443 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2446 return yyerror ("Register mismatch or value error");
2449 | IF BANG CCREG REG ASSIGN REG
2451 if ((IS_DREG ($4) || IS_PREG ($4))
2452 && (IS_DREG ($6) || IS_PREG ($6)))
2454 notethat ("ccMV: IF ! CC gregs = gregs\n");
2455 $$ = CCMV (&$6, &$4, 0);
2458 return yyerror ("Register mismatch");
2461 | IF CCREG REG ASSIGN REG
2463 if ((IS_DREG ($5) || IS_PREG ($5))
2464 && (IS_DREG ($3) || IS_PREG ($3)))
2466 notethat ("ccMV: IF CC gregs = gregs\n");
2467 $$ = CCMV (&$5, &$3, 1);
2470 return yyerror ("Register mismatch");
2473 | IF BANG CCREG JUMP expr
2475 if (IS_PCREL10 ($5))
2477 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2478 $$ = BRCC (0, 0, $5);
2481 return yyerror ("Bad jump offset");
2484 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2486 if (IS_PCREL10 ($5))
2488 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2489 $$ = BRCC (0, 1, $5);
2492 return yyerror ("Bad jump offset");
2495 | IF CCREG JUMP expr
2497 if (IS_PCREL10 ($4))
2499 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2500 $$ = BRCC (1, 0, $4);
2503 return yyerror ("Bad jump offset");
2506 | IF CCREG JUMP expr LPAREN BP RPAREN
2508 if (IS_PCREL10 ($4))
2510 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2511 $$ = BRCC (1, 1, $4);
2514 return yyerror ("Bad jump offset");
2518 notethat ("ProgCtrl: NOP\n");
2519 $$ = PROGCTRL (0, 0);
2524 notethat ("ProgCtrl: RTS\n");
2525 $$ = PROGCTRL (1, 0);
2530 notethat ("ProgCtrl: RTI\n");
2531 $$ = PROGCTRL (1, 1);
2536 notethat ("ProgCtrl: RTX\n");
2537 $$ = PROGCTRL (1, 2);
2542 notethat ("ProgCtrl: RTN\n");
2543 $$ = PROGCTRL (1, 3);
2548 notethat ("ProgCtrl: RTE\n");
2549 $$ = PROGCTRL (1, 4);
2554 notethat ("ProgCtrl: IDLE\n");
2555 $$ = PROGCTRL (2, 0);
2560 notethat ("ProgCtrl: CSYNC\n");
2561 $$ = PROGCTRL (2, 3);
2566 notethat ("ProgCtrl: SSYNC\n");
2567 $$ = PROGCTRL (2, 4);
2572 notethat ("ProgCtrl: EMUEXCPT\n");
2573 $$ = PROGCTRL (2, 5);
2580 notethat ("ProgCtrl: CLI dregs\n");
2581 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2584 return yyerror ("Dreg expected for CLI");
2591 notethat ("ProgCtrl: STI dregs\n");
2592 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2595 return yyerror ("Dreg expected for STI");
2598 | JUMP LPAREN REG RPAREN
2602 notethat ("ProgCtrl: JUMP (pregs )\n");
2603 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2606 return yyerror ("Bad register for indirect jump");
2609 | CALL LPAREN REG RPAREN
2613 notethat ("ProgCtrl: CALL (pregs )\n");
2614 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2617 return yyerror ("Bad register for indirect call");
2620 | CALL LPAREN PC PLUS REG RPAREN
2624 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2625 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2628 return yyerror ("Bad register for indirect call");
2631 | JUMP LPAREN PC PLUS REG RPAREN
2635 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2636 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2639 return yyerror ("Bad register for indirect jump");
2644 if (IS_UIMM ($2, 4))
2646 notethat ("ProgCtrl: RAISE uimm4\n");
2647 $$ = PROGCTRL (9, uimm4 ($2));
2650 return yyerror ("Bad value for RAISE");
2655 notethat ("ProgCtrl: EMUEXCPT\n");
2656 $$ = PROGCTRL (10, uimm4 ($2));
2659 | TESTSET LPAREN REG RPAREN
2663 notethat ("ProgCtrl: TESTSET (pregs )\n");
2664 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2667 return yyerror ("Preg expected");
2672 if (IS_PCREL12 ($2))
2674 notethat ("UJUMP: JUMP pcrel12\n");
2678 return yyerror ("Bad value for relative jump");
2683 if (IS_PCREL12 ($2))
2685 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2689 return yyerror ("Bad value for relative jump");
2694 if (IS_PCREL24 ($2))
2696 notethat ("CALLa: jump.l pcrel24\n");
2700 return yyerror ("Bad value for long jump");
2705 if (IS_PCREL24 ($2))
2707 notethat ("CALLa: jump.l pcrel24\n");
2711 return yyerror ("Bad value for long jump");
2716 if (IS_PCREL24 ($2))
2718 notethat ("CALLa: CALL pcrel25m2\n");
2722 return yyerror ("Bad call address");
2726 if (IS_PCREL24 ($2))
2728 notethat ("CALLa: CALL pcrel25m2\n");
2732 return yyerror ("Bad call address");
2736 /* ALU2op: DIVQ (dregs, dregs). */
2737 | DIVQ LPAREN REG COMMA REG RPAREN
2739 if (IS_DREG ($3) && IS_DREG ($5))
2740 $$ = ALU2OP (&$3, &$5, 8);
2742 return yyerror ("Bad registers for DIVQ");
2745 | DIVS LPAREN REG COMMA REG RPAREN
2747 if (IS_DREG ($3) && IS_DREG ($5))
2748 $$ = ALU2OP (&$3, &$5, 9);
2750 return yyerror ("Bad registers for DIVS");
2753 | REG ASSIGN MINUS REG vsmod
2755 if (IS_DREG ($1) && IS_DREG ($4))
2757 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2759 notethat ("ALU2op: dregs = - dregs\n");
2760 $$ = ALU2OP (&$1, &$4, 14);
2762 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2764 notethat ("dsp32alu: dregs = - dregs (.)\n");
2765 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2769 notethat ("dsp32alu: dregs = - dregs (.)\n");
2770 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2774 return yyerror ("Dregs expected");
2777 | REG ASSIGN TILDA REG
2779 if (IS_DREG ($1) && IS_DREG ($4))
2781 notethat ("ALU2op: dregs = ~dregs\n");
2782 $$ = ALU2OP (&$1, &$4, 15);
2785 return yyerror ("Dregs expected");
2788 | REG _GREATER_GREATER_ASSIGN REG
2790 if (IS_DREG ($1) && IS_DREG ($3))
2792 notethat ("ALU2op: dregs >>= dregs\n");
2793 $$ = ALU2OP (&$1, &$3, 1);
2796 return yyerror ("Dregs expected");
2799 | REG _GREATER_GREATER_ASSIGN expr
2801 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2803 notethat ("LOGI2op: dregs >>= uimm5\n");
2804 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2807 return yyerror ("Dregs expected or value error");
2810 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2812 if (IS_DREG ($1) && IS_DREG ($3))
2814 notethat ("ALU2op: dregs >>>= dregs\n");
2815 $$ = ALU2OP (&$1, &$3, 0);
2818 return yyerror ("Dregs expected");
2821 | REG _LESS_LESS_ASSIGN REG
2823 if (IS_DREG ($1) && IS_DREG ($3))
2825 notethat ("ALU2op: dregs <<= dregs\n");
2826 $$ = ALU2OP (&$1, &$3, 2);
2829 return yyerror ("Dregs expected");
2832 | REG _LESS_LESS_ASSIGN expr
2834 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2836 notethat ("LOGI2op: dregs <<= uimm5\n");
2837 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2840 return yyerror ("Dregs expected or const value error");
2844 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2846 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2848 notethat ("LOGI2op: dregs >>>= uimm5\n");
2849 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2852 return yyerror ("Dregs expected");
2855 /* Cache Control. */
2857 | FLUSH LBRACK REG RBRACK
2859 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2861 $$ = CACTRL (&$3, 0, 2);
2863 return yyerror ("Bad register(s) for FLUSH");
2866 | FLUSH reg_with_postinc
2870 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2871 $$ = CACTRL (&$2, 1, 2);
2874 return yyerror ("Bad register(s) for FLUSH");
2877 | FLUSHINV LBRACK REG RBRACK
2881 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2882 $$ = CACTRL (&$3, 0, 1);
2885 return yyerror ("Bad register(s) for FLUSH");
2888 | FLUSHINV reg_with_postinc
2892 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2893 $$ = CACTRL (&$2, 1, 1);
2896 return yyerror ("Bad register(s) for FLUSH");
2899 /* CaCTRL: IFLUSH [pregs]. */
2900 | IFLUSH LBRACK REG RBRACK
2904 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2905 $$ = CACTRL (&$3, 0, 3);
2908 return yyerror ("Bad register(s) for FLUSH");
2911 | IFLUSH reg_with_postinc
2915 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2916 $$ = CACTRL (&$2, 1, 3);
2919 return yyerror ("Bad register(s) for FLUSH");
2922 | PREFETCH LBRACK REG RBRACK
2926 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2927 $$ = CACTRL (&$3, 0, 0);
2930 return yyerror ("Bad register(s) for PREFETCH");
2933 | PREFETCH reg_with_postinc
2937 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2938 $$ = CACTRL (&$2, 1, 0);
2941 return yyerror ("Bad register(s) for PREFETCH");
2945 /* LDST: B [ pregs <post_op> ] = dregs. */
2947 | B LBRACK REG post_op RBRACK ASSIGN REG
2950 return yyerror ("Dreg expected for source operand");
2952 return yyerror ("Preg expected in address");
2954 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2955 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2958 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2959 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2961 Expr_Node *tmp = $5;
2964 return yyerror ("Dreg expected for source operand");
2966 return yyerror ("Preg expected in address");
2969 return yyerror ("Plain symbol used as offset");
2972 tmp = unary (Expr_Op_Type_NEG, tmp);
2974 if (in_range_p (tmp, -32768, 32767, 0))
2976 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2977 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2980 return yyerror ("Displacement out of range");
2984 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
2985 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2987 Expr_Node *tmp = $5;
2990 return yyerror ("Dreg expected for source operand");
2992 return yyerror ("Preg expected in address");
2995 tmp = unary (Expr_Op_Type_NEG, tmp);
2998 return yyerror ("Plain symbol used as offset");
3000 if (in_range_p (tmp, 0, 30, 1))
3002 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3003 $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3005 else if (in_range_p (tmp, -65536, 65535, 1))
3007 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3008 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3011 return yyerror ("Displacement out of range");
3014 /* LDST: W [ pregs <post_op> ] = dregs. */
3015 | W LBRACK REG post_op RBRACK ASSIGN REG
3018 return yyerror ("Dreg expected for source operand");
3020 return yyerror ("Preg expected in address");
3022 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3023 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3026 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3029 return yyerror ("Dreg expected for source operand");
3032 if (!IS_IREG ($3) && !IS_PREG ($3))
3033 return yyerror ("Ireg or Preg expected in address");
3035 else if (!IS_IREG ($3))
3036 return yyerror ("Ireg expected in address");
3040 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3041 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3045 notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3046 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3050 /* LDSTiiFP: [ FP - const ] = dpregs. */
3051 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3053 Expr_Node *tmp = $4;
3054 int ispreg = IS_PREG ($7);
3057 return yyerror ("Preg expected in address");
3059 if (!IS_DREG ($7) && !ispreg)
3060 return yyerror ("Preg expected for source operand");
3063 tmp = unary (Expr_Op_Type_NEG, tmp);
3066 return yyerror ("Plain symbol used as offset");
3068 if (in_range_p (tmp, 0, 63, 3))
3070 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3071 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3073 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3075 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3076 tmp = unary (Expr_Op_Type_NEG, tmp);
3077 $$ = LDSTIIFP (tmp, &$7, 1);
3079 else if (in_range_p (tmp, -131072, 131071, 3))
3081 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3082 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3085 return yyerror ("Displacement out of range");
3088 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3090 Expr_Node *tmp = $7;
3092 return yyerror ("Dreg expected for destination operand");
3094 return yyerror ("Preg expected in address");
3097 tmp = unary (Expr_Op_Type_NEG, tmp);
3100 return yyerror ("Plain symbol used as offset");
3102 if (in_range_p (tmp, 0, 30, 1))
3104 notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3105 $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3107 else if (in_range_p (tmp, -65536, 65535, 1))
3109 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3110 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3113 return yyerror ("Displacement out of range");
3116 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3119 return yyerror ("Dreg expected for source operand");
3122 if (!IS_IREG ($5) && !IS_PREG ($5))
3123 return yyerror ("Ireg or Preg expected in address");
3125 else if (!IS_IREG ($5))
3126 return yyerror ("Ireg expected in address");
3130 notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3131 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3135 notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3136 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3141 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3144 return yyerror ("Dreg expected for destination operand");
3146 return yyerror ("Preg expected in address");
3148 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3149 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3152 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3155 return yyerror ("Dreg expected for destination operand");
3156 if (!IS_PREG ($5) || !IS_PREG ($7))
3157 return yyerror ("Preg expected in address");
3159 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3160 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3163 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3166 return yyerror ("Dreg expected for destination operand");
3167 if (!IS_PREG ($5) || !IS_PREG ($7))
3168 return yyerror ("Preg expected in address");
3170 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3171 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3174 | LBRACK REG post_op RBRACK ASSIGN REG
3176 if (!IS_IREG ($2) && !IS_PREG ($2))
3177 return yyerror ("Ireg or Preg expected in address");
3178 else if (IS_IREG ($2) && !IS_DREG ($6))
3179 return yyerror ("Dreg expected for source operand");
3180 else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3181 return yyerror ("Dreg or Preg expected for source operand");
3185 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3186 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3188 else if (IS_DREG ($6))
3190 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3191 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3195 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3196 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3200 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3203 return yyerror ("Dreg expected for source operand");
3205 if (IS_IREG ($2) && IS_MREG ($4))
3207 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3208 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3210 else if (IS_PREG ($2) && IS_PREG ($4))
3212 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3213 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3216 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3219 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3222 return yyerror ("Dreg expected for source operand");
3224 if (IS_PREG ($3) && IS_PREG ($5))
3226 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3227 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3230 return yyerror ("Preg ++ Preg expected in address");
3233 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3235 Expr_Node *tmp = $7;
3237 return yyerror ("Dreg expected for destination operand");
3239 return yyerror ("Preg expected in address");
3242 tmp = unary (Expr_Op_Type_NEG, tmp);
3245 return yyerror ("Plain symbol used as offset");
3247 if (in_range_p (tmp, -32768, 32767, 0))
3249 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3251 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3254 return yyerror ("Displacement out of range");
3257 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3260 return yyerror ("Dreg expected for destination operand");
3262 return yyerror ("Preg expected in address");
3264 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3266 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3269 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3272 return yyerror ("Dreg expected for destination operand");
3274 if (IS_IREG ($4) && IS_MREG ($6))
3276 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3277 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3279 else if (IS_PREG ($4) && IS_PREG ($6))
3281 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3282 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3285 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3288 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3290 Expr_Node *tmp = $6;
3291 int ispreg = IS_PREG ($1);
3292 int isgot = IS_RELOC($6);
3295 return yyerror ("Preg expected in address");
3297 if (!IS_DREG ($1) && !ispreg)
3298 return yyerror ("Dreg or Preg expected for destination operand");
3300 if (tmp->type == Expr_Node_Reloc
3301 && strcmp (tmp->value.s_value,
3302 "_current_shared_library_p5_offset_") != 0)
3303 return yyerror ("Plain symbol used as offset");
3306 tmp = unary (Expr_Op_Type_NEG, tmp);
3310 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3311 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3313 else if (in_range_p (tmp, 0, 63, 3))
3315 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3316 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3318 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3320 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3321 tmp = unary (Expr_Op_Type_NEG, tmp);
3322 $$ = LDSTIIFP (tmp, &$1, 0);
3324 else if (in_range_p (tmp, -131072, 131071, 3))
3326 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3327 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3331 return yyerror ("Displacement out of range");
3334 | REG ASSIGN LBRACK REG post_op RBRACK
3336 if (!IS_IREG ($4) && !IS_PREG ($4))
3337 return yyerror ("Ireg or Preg expected in address");
3338 else if (IS_IREG ($4) && !IS_DREG ($1))
3339 return yyerror ("Dreg expected in destination operand");
3340 else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3341 && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3342 return yyerror ("Dreg or Preg expected in destination operand");
3346 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3347 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3349 else if (IS_DREG ($1))
3351 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3352 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3354 else if (IS_PREG ($1))
3356 if (REG_SAME ($1, $4) && $5.x0 != 2)
3357 return yyerror ("Pregs can't be same");
3359 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3360 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3364 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3365 $$ = PUSHPOPREG (&$1, 0);
3370 /* PushPopMultiple. */
3371 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3373 if ($1.regno != REG_SP)
3374 yyerror ("Stack Pointer expected");
3375 if ($4.regno == REG_R7
3376 && IN_RANGE ($6, 0, 7)
3377 && $8.regno == REG_P5
3378 && IN_RANGE ($10, 0, 5))
3380 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3381 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3384 return yyerror ("Bad register for PushPopMultiple");
3387 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3389 if ($1.regno != REG_SP)
3390 yyerror ("Stack Pointer expected");
3392 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3394 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3395 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3397 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3399 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3400 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3403 return yyerror ("Bad register for PushPopMultiple");
3406 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3408 if ($11.regno != REG_SP)
3409 yyerror ("Stack Pointer expected");
3410 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3411 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3413 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3414 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3417 return yyerror ("Bad register range for PushPopMultiple");
3420 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3422 if ($7.regno != REG_SP)
3423 yyerror ("Stack Pointer expected");
3425 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3427 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3428 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3430 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3432 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3433 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3436 return yyerror ("Bad register range for PushPopMultiple");
3439 | reg_with_predec ASSIGN REG
3441 if ($1.regno != REG_SP)
3442 yyerror ("Stack Pointer expected");
3446 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3447 $$ = PUSHPOPREG (&$3, 1);
3450 return yyerror ("Bad register for PushPopReg");
3457 if (IS_URANGE (16, $2, 0, 4))
3458 $$ = LINKAGE (0, uimm16s4 ($2));
3460 return yyerror ("Bad constant for LINK");
3465 notethat ("linkage: UNLINK\n");
3466 $$ = LINKAGE (1, 0);
3472 | LSETUP LPAREN expr COMMA expr RPAREN REG
3474 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3476 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3477 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3480 return yyerror ("Bad register or values for LSETUP");
3483 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3485 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3486 && IS_PREG ($9) && IS_CREG ($7))
3488 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3489 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3492 return yyerror ("Bad register or values for LSETUP");
3495 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3497 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3498 && IS_PREG ($9) && IS_CREG ($7)
3499 && EXPR_VALUE ($11) == 1)
3501 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3502 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3505 return yyerror ("Bad register or values for LSETUP");
3512 return yyerror ("Invalid expression in loop statement");
3514 return yyerror ("Invalid loop counter register");
3515 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3517 | LOOP expr REG ASSIGN REG
3519 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3521 notethat ("Loop: LOOP expr counters = pregs\n");
3522 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3525 return yyerror ("Bad register or values for LOOP");
3527 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3529 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3531 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3532 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3535 return yyerror ("Bad register or values for LOOP");
3542 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3544 bfin_loop_beginend ($2, 1);
3552 return yyerror ("Invalid expression in LOOP_END statement");
3554 bfin_loop_beginend ($2, 0);
3562 notethat ("pseudoDEBUG: DBG\n");
3563 $$ = bfin_gen_pseudodbg (3, 7, 0);
3567 notethat ("pseudoDEBUG: DBG REG_A\n");
3568 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3572 notethat ("pseudoDEBUG: DBG allregs\n");
3573 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3576 | DBGCMPLX LPAREN REG RPAREN
3579 return yyerror ("Dregs expected");
3580 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3581 $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3586 notethat ("psedoDEBUG: DBGHALT\n");
3587 $$ = bfin_gen_pseudodbg (3, 5, 0);
3590 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3592 notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3593 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3596 | DBGAH LPAREN REG COMMA expr RPAREN
3598 notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3599 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3602 | DBGAL LPAREN REG COMMA expr RPAREN
3604 notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3605 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3613 /* Register rules. */
3615 REG_A: REG_A_DOUBLE_ZERO
3633 | LPAREN M COMMA MMOD RPAREN
3638 | LPAREN MMOD COMMA M RPAREN
3643 | LPAREN MMOD RPAREN
3655 asr_asl: LPAREN ASL RPAREN
3736 | LPAREN asr_asl_0 RPAREN
3748 | LPAREN asr_asl_0 COMMA sco RPAREN
3754 | LPAREN sco COMMA asr_asl_0 RPAREN
3814 | LPAREN V COMMA S RPAREN
3819 | LPAREN S COMMA V RPAREN
3881 | LPAREN MMOD RPAREN
3884 return yyerror ("Bad modifier");
3888 | LPAREN MMOD COMMA R RPAREN
3891 return yyerror ("Bad modifier");
3895 | LPAREN R COMMA MMOD RPAREN
3898 return yyerror ("Bad modifier");
3925 | LPAREN MMOD RPAREN
3930 return yyerror ("Only (W32) allowed");
3938 | LPAREN MMOD RPAREN
3943 return yyerror ("(IU) expected");
3947 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3953 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4005 $$.r0 = 1; /* HL. */
4008 $$.aop = 0; /* aop. */
4013 $$.r0 = 1; /* HL. */
4016 $$.aop = 1; /* aop. */
4019 | LPAREN RNDL RPAREN
4021 $$.r0 = 0; /* HL. */
4024 $$.aop = 0; /* aop. */
4029 $$.r0 = 0; /* HL. */
4035 | LPAREN RNDH COMMA R RPAREN
4037 $$.r0 = 1; /* HL. */
4040 $$.aop = 0; /* aop. */
4042 | LPAREN TH COMMA R RPAREN
4044 $$.r0 = 1; /* HL. */
4047 $$.aop = 1; /* aop. */
4049 | LPAREN RNDL COMMA R RPAREN
4051 $$.r0 = 0; /* HL. */
4054 $$.aop = 0; /* aop. */
4057 | LPAREN TL COMMA R RPAREN
4059 $$.r0 = 0; /* HL. */
4062 $$.aop = 1; /* aop. */
4070 $$.x0 = 0; /* HL. */
4075 $$.x0 = 1; /* HL. */
4077 | LPAREN LO COMMA R RPAREN
4080 $$.x0 = 0; /* HL. */
4082 | LPAREN HI COMMA R RPAREN
4085 $$.x0 = 1; /* HL. */
4103 /* Assignments, Macfuncs. */
4129 if (IS_A1 ($3) && IS_EVEN ($1))
4130 return yyerror ("Cannot move A1 to even register");
4131 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4132 return yyerror ("Cannot move A0 to odd register");
4148 | REG ASSIGN LPAREN a_macfunc RPAREN
4150 if ($4.n && IS_EVEN ($1))
4151 return yyerror ("Cannot move A1 to even register");
4152 else if (!$4.n && !IS_EVEN ($1))
4153 return yyerror ("Cannot move A0 to odd register");
4161 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4163 if ($4.n && !IS_H ($1))
4164 return yyerror ("Cannot move A1 to low half of register");
4165 else if (!$4.n && IS_H ($1))
4166 return yyerror ("Cannot move A0 to high half of register");
4174 | HALF_REG ASSIGN REG_A
4176 if (IS_A1 ($3) && !IS_H ($1))
4177 return yyerror ("Cannot move A1 to low half of register");
4178 else if (!IS_A1 ($3) && IS_H ($1))
4179 return yyerror ("Cannot move A0 to high half of register");
4192 a_assign multiply_halfregs
4199 | a_plusassign multiply_halfregs
4206 | a_minusassign multiply_halfregs
4216 HALF_REG STAR HALF_REG
4218 if (IS_DREG ($1) && IS_DREG ($3))
4224 return yyerror ("Dregs expected");
4248 CCREG cc_op STATUS_REG
4260 | STATUS_REG cc_op CCREG
4274 /* Expressions and Symbols. */
4278 Expr_Node_Value val;
4279 val.s_value = S_GET_NAME($1);
4280 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4286 { $$ = BFD_RELOC_BFIN_GOT; }
4288 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4290 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4293 got: symbol AT any_gotrel
4295 Expr_Node_Value val;
4297 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4320 Expr_Node_Value val;
4322 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4328 | LPAREN expr_1 RPAREN
4334 $$ = unary (Expr_Op_Type_COMP, $2);
4336 | MINUS expr_1 %prec TILDA
4338 $$ = unary (Expr_Op_Type_NEG, $2);
4348 expr_1: expr_1 STAR expr_1
4350 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4352 | expr_1 SLASH expr_1
4354 $$ = binary (Expr_Op_Type_Div, $1, $3);
4356 | expr_1 PERCENT expr_1
4358 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4360 | expr_1 PLUS expr_1
4362 $$ = binary (Expr_Op_Type_Add, $1, $3);
4364 | expr_1 MINUS expr_1
4366 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4368 | expr_1 LESS_LESS expr_1
4370 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4372 | expr_1 GREATER_GREATER expr_1
4374 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4376 | expr_1 AMPERSAND expr_1
4378 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4380 | expr_1 CARET expr_1
4382 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4386 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4398 mkexpr (int x, SYMBOL_T s)
4400 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4407 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4409 int umax = (1 << sz) - 1;
4410 int min = -1 << (sz - 1);
4411 int max = (1 << (sz - 1)) - 1;
4413 int v = (EXPR_VALUE (expr)) & 0xffffffff;
4417 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4428 if (v >= min && v <= max) return 1;
4431 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4435 if (v <= umax && v >= 0)
4438 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4443 /* Return the expression structure that allows symbol operations.
4444 If the left and right children are constants, do the operation. */
4446 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4448 Expr_Node_Value val;
4450 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4454 case Expr_Op_Type_Add:
4455 x->value.i_value += y->value.i_value;
4457 case Expr_Op_Type_Sub:
4458 x->value.i_value -= y->value.i_value;
4460 case Expr_Op_Type_Mult:
4461 x->value.i_value *= y->value.i_value;
4463 case Expr_Op_Type_Div:
4464 if (y->value.i_value == 0)
4465 error ("Illegal Expression: Division by zero.");
4467 x->value.i_value /= y->value.i_value;
4469 case Expr_Op_Type_Mod:
4470 x->value.i_value %= y->value.i_value;
4472 case Expr_Op_Type_Lshift:
4473 x->value.i_value <<= y->value.i_value;
4475 case Expr_Op_Type_Rshift:
4476 x->value.i_value >>= y->value.i_value;
4478 case Expr_Op_Type_BAND:
4479 x->value.i_value &= y->value.i_value;
4481 case Expr_Op_Type_BOR:
4482 x->value.i_value |= y->value.i_value;
4484 case Expr_Op_Type_BXOR:
4485 x->value.i_value ^= y->value.i_value;
4487 case Expr_Op_Type_LAND:
4488 x->value.i_value = x->value.i_value && y->value.i_value;
4490 case Expr_Op_Type_LOR:
4491 x->value.i_value = x->value.i_value || y->value.i_value;
4495 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4499 /* Canonicalize order to EXPR OP CONSTANT. */
4500 if (x->type == Expr_Node_Constant)
4506 /* Canonicalize subtraction of const to addition of negated const. */
4507 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4509 op = Expr_Op_Type_Add;
4510 y->value.i_value = -y->value.i_value;
4512 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4513 && x->Right_Child->type == Expr_Node_Constant)
4515 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4517 x->Right_Child->value.i_value += y->value.i_value;
4522 /* Create a new expression structure. */
4524 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4528 unary (Expr_Op_Type op, Expr_Node *x)
4530 if (x->type == Expr_Node_Constant)
4534 case Expr_Op_Type_NEG:
4535 x->value.i_value = -x->value.i_value;
4537 case Expr_Op_Type_COMP:
4538 x->value.i_value = ~x->value.i_value;
4541 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4547 /* Create a new expression structure. */
4548 Expr_Node_Value val;
4550 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4554 int debug_codeselection = 0;
4556 notethat (char *format, ...)
4559 va_start (ap, format);
4560 if (debug_codeselection)
4562 vfprintf (errorf, format, ap);
4568 main (int argc, char **argv)