gas/config/rx-parse.y

   1 /* rx-parse.y  Renesas RX parser
   2    Copyright 2008-2013 Free Software Foundation, Inc.
   3
   4    This file is part of GAS, the GNU Assembler.
   5
   6    GAS is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    GAS is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20 %{
  21
  22 #include "as.h"
  23 #include "safe-ctype.h"
  24 #include "rx-defs.h"
  25
  26 static int rx_lex (void);
  27
  28 #define COND_EQ 0
  29 #define COND_NE 1
  30
  31 #define MEMEX 0x06
  32
  33 #define BSIZE 0
  34 #define WSIZE 1
  35 #define LSIZE 2
  36
  37 /*                       .sb    .sw    .l     .uw   */
  38 static int sizemap[] = { BSIZE, WSIZE, LSIZE, WSIZE };
  39
  40 /* Ok, here are the rules for using these macros...
  41
  42    B*() is used to specify the base opcode bytes.  Fields to be filled
  43         in later, leave zero.  Call this first.
  44
  45    F() and FE() are used to fill in fields within the base opcode bytes.  You MUST
  46         call B*() before any F() or FE().
  47
  48    [UN]*O*(), PC*() appends operands to the end of the opcode.  You
  49         must call P() and B*() before any of these, so that the fixups
  50         have the right byte location.
  51         O = signed, UO = unsigned, NO = negated, PC = pcrel
  52
  53    IMM() adds an immediate and fills in the field for it.
  54    NIMM() same, but negates the immediate.
  55    NBIMM() same, but negates the immediate, for sbb.
  56    DSP() adds a displacement, and fills in the field for it.
  57
  58    Note that order is significant for the O, IMM, and DSP macros, as
  59    they append their data to the operand buffer in the order that you
  60    call them.
  61
  62    Use "disp" for displacements whenever possible; this handles the
  63    "0" case properly.  */
  64
  65 #define B1(b1)             rx_base1 (b1)
  66 #define B2(b1, b2)         rx_base2 (b1, b2)
  67 #define B3(b1, b2, b3)     rx_base3 (b1, b2, b3)
  68 #define B4(b1, b2, b3, b4) rx_base4 (b1, b2, b3, b4)
  69
  70 /* POS is bits from the MSB of the first byte to the LSB of the last byte.  */
  71 #define F(val,pos,sz)      rx_field (val, pos, sz)
  72 #define FE(exp,pos,sz)     rx_field (exp_val (exp), pos, sz);
  73
  74 #define O1(v)              rx_op (v, 1, RXREL_SIGNED); rx_range (v, -128, 255)
  75 #define O2(v)              rx_op (v, 2, RXREL_SIGNED); rx_range (v, -32768, 65536)
  76 #define O3(v)              rx_op (v, 3, RXREL_SIGNED); rx_range (v, -8388608, 16777216)
  77 #define O4(v)              rx_op (v, 4, RXREL_SIGNED)
  78
  79 #define UO1(v)             rx_op (v, 1, RXREL_UNSIGNED); rx_range (v, 0, 255)
  80 #define UO2(v)             rx_op (v, 2, RXREL_UNSIGNED); rx_range (v, 0, 65536)
  81 #define UO3(v)             rx_op (v, 3, RXREL_UNSIGNED); rx_range (v, 0, 16777216)
  82 #define UO4(v)             rx_op (v, 4, RXREL_UNSIGNED)
  83
  84 #define NO1(v)             rx_op (v, 1, RXREL_NEGATIVE)
  85 #define NO2(v)             rx_op (v, 2, RXREL_NEGATIVE)
  86 #define NO3(v)             rx_op (v, 3, RXREL_NEGATIVE)
  87 #define NO4(v)             rx_op (v, 4, RXREL_NEGATIVE)
  88
  89 #define PC1(v)             rx_op (v, 1, RXREL_PCREL)
  90 #define PC2(v)             rx_op (v, 2, RXREL_PCREL)
  91 #define PC3(v)             rx_op (v, 3, RXREL_PCREL)
  92
  93 #define IMM_(v,pos,size)   F (immediate (v, RXREL_SIGNED, pos, size), pos, 2); \
  94                            if (v.X_op != O_constant && v.X_op != O_big) rx_linkrelax_imm (pos)
  95 #define IMM(v,pos)         IMM_ (v, pos, 32)
  96 #define IMMW(v,pos)        IMM_ (v, pos, 16); rx_range (v, -32768, 65536)
  97 #define IMMB(v,pos)        IMM_ (v, pos, 8); rx_range (v, -128, 255)
  98 #define NIMM(v,pos)        F (immediate (v, RXREL_NEGATIVE, pos, 32), pos, 2)
  99 #define NBIMM(v,pos)       F (immediate (v, RXREL_NEGATIVE_BORROW, pos, 32), pos, 2)
 100 #define DSP(v,pos,msz)     if (!v.X_md) rx_relax (RX_RELAX_DISP, pos); \
 101                            else rx_linkrelax_dsp (pos); \
 102                            F (displacement (v, msz), pos, 2)
 103
 104 #define id24(a,b2,b3)      B3 (0xfb+a, b2, b3)
 105
 106 static void        rx_check_float_support (void);
 107 static int         rx_intop (expressionS, int, int);
 108 static int         rx_uintop (expressionS, int);
 109 static int         rx_disp3op (expressionS);
 110 static int         rx_disp5op (expressionS *, int);
 111 static int         rx_disp5op0 (expressionS *, int);
 112 static int         exp_val (expressionS exp);
 113 static expressionS zero_expr (void);
 114 static int         immediate (expressionS, int, int, int);
 115 static int         displacement (expressionS, int);
 116 static void        rtsd_immediate (expressionS);
 117 static void        rx_range (expressionS, int, int);
 118
 119 static int    need_flag = 0;
 120 static int    rx_in_brackets = 0;
 121 static int    rx_last_token = 0;
 122 static char * rx_init_start;
 123 static char * rx_last_exp_start = 0;
 124 static int    sub_op;
 125 static int    sub_op2;
 126
 127 #define YYDEBUG 1
 128 #define YYERROR_VERBOSE 1
 129
 130 %}
 131
 132 %name-prefix="rx_"
 133
 134 %union {
 135   int regno;
 136   expressionS exp;
 137 }
 138
 139 %type <regno> REG FLAG CREG BCND BMCND SCCND
 140 %type <regno> flag bwl bw memex
 141 %type <exp> EXPR disp
 142
 143 %token REG FLAG CREG
 144
 145 %token EXPR UNKNOWN_OPCODE IS_OPCODE
 146
 147 %token DOT_S DOT_B DOT_W DOT_L DOT_A DOT_UB DOT_UW
 148
 149 %token ABS ADC ADD AND_
 150 %token BCLR BCND BMCND BNOT BRA BRK BSET BSR BTST
 151 %token CLRPSW CMP
 152 %token DBT DIV DIVU
 153 %token EDIV EDIVU EMUL EMULU
 154 %token FADD FCMP FDIV FMUL FREIT FSUB FTOI
 155 %token INT ITOF
 156 %token JMP JSR
 157 %token MACHI MACLO MAX MIN MOV MOVU MUL MULHI MULLO MULU MVFACHI MVFACMI MVFACLO
 158 %token   MVFC MVTACHI MVTACLO MVTC MVTIPL
 159 %token NEG NOP NOT
 160 %token OR
 161 %token POP POPC POPM PUSH PUSHA PUSHC PUSHM
 162 %token RACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND RTE RTFI RTS RTSD
 163 %token SAT SATR SBB SCCND SCMPU SETPSW SHAR SHLL SHLR SMOVB SMOVF
 164 %token   SMOVU SSTR STNZ STOP STZ SUB SUNTIL SWHILE
 165 %token TST
 166 %token WAIT
 167 %token XCHG XOR
 168
 169 %%
 170 /* ====================================================================== */
 171
 172 statement :
 173
 174           UNKNOWN_OPCODE
 175           { as_bad (_("Unknown opcode: %s"), rx_init_start); }
 176
 177 /* ---------------------------------------------------------------------- */
 178
 179         | BRK
 180           { B1 (0x00); }
 181
 182         | DBT
 183           { B1 (0x01); }
 184
 185         | RTS
 186           { B1 (0x02); }
 187
 188         | NOP
 189           { B1 (0x03); }
 190
 191 /* ---------------------------------------------------------------------- */
 192
 193         | BRA EXPR
 194           { if (rx_disp3op ($2))
 195               { B1 (0x08); rx_disp3 ($2, 5); }
 196             else if (rx_intop ($2, 8, 8))
 197               { B1 (0x2e); PC1 ($2); }
 198             else if (rx_intop ($2, 16, 16))
 199               { B1 (0x38); PC2 ($2); }
 200             else if (rx_intop ($2, 24, 24))
 201               { B1 (0x04); PC3 ($2); }
 202             else
 203               { rx_relax (RX_RELAX_BRANCH, 0);
 204                 rx_linkrelax_branch ();
 205                 /* We'll convert this to a longer one later if needed.  */
 206                 B1 (0x08); rx_disp3 ($2, 5); } }
 207
 208         | BRA DOT_A EXPR
 209           { B1 (0x04); PC3 ($3); }
 210
 211         | BRA DOT_S EXPR
 212           { B1 (0x08); rx_disp3 ($3, 5); }
 213
 214 /* ---------------------------------------------------------------------- */
 215
 216         | BSR EXPR
 217           { if (rx_intop ($2, 16, 16))
 218               { B1 (0x39); PC2 ($2); }
 219             else if (rx_intop ($2, 24, 24))
 220               { B1 (0x05); PC3 ($2); }
 221             else
 222               { rx_relax (RX_RELAX_BRANCH, 0);
 223                 rx_linkrelax_branch ();
 224                 B1 (0x39); PC2 ($2); } }
 225         | BSR DOT_A EXPR
 226           { B1 (0x05), PC3 ($3); }
 227
 228 /* ---------------------------------------------------------------------- */
 229
 230         | BCND DOT_S EXPR
 231           { if ($1 == COND_EQ || $1 == COND_NE)
 232               { B1 ($1 == COND_EQ ? 0x10 : 0x18); rx_disp3 ($3, 5); }
 233             else
 234               as_bad (_("Only BEQ and BNE may have .S")); }
 235
 236 /* ---------------------------------------------------------------------- */
 237
 238         | BCND DOT_B EXPR
 239           { B1 (0x20); F ($1, 4, 4); PC1 ($3); }
 240
 241         | BRA DOT_B EXPR
 242           { B1 (0x2e), PC1 ($3); }
 243
 244 /* ---------------------------------------------------------------------- */
 245
 246         | BRA DOT_W EXPR
 247           { B1 (0x38), PC2 ($3); }
 248         | BSR DOT_W EXPR
 249           { B1 (0x39), PC2 ($3); }
 250         | BCND DOT_W EXPR
 251           { if ($1 == COND_EQ || $1 == COND_NE)
 252               { B1 ($1 == COND_EQ ? 0x3a : 0x3b); PC2 ($3); }
 253             else
 254               as_bad (_("Only BEQ and BNE may have .W")); }
 255         | BCND EXPR
 256           { if ($1 == COND_EQ || $1 == COND_NE)
 257               {
 258                 rx_relax (RX_RELAX_BRANCH, 0);
 259                 rx_linkrelax_branch ();
 260                 B1 ($1 == COND_EQ ? 0x10 : 0x18); rx_disp3 ($2, 5);
 261               }
 262             else
 263               {
 264                 rx_relax (RX_RELAX_BRANCH, 0);
 265                 /* This is because we might turn it into a
 266                    jump-over-jump long branch.  */
 267                 rx_linkrelax_branch ();
 268                 B1 (0x20); F ($1, 4, 4); PC1 ($2);
 269               } }
 270
 271 /* ---------------------------------------------------------------------- */
 272
 273         | MOV DOT_B '#' EXPR ',' disp '[' REG ']'
 274           /* rx_disp5op changes the value if it succeeds, so keep it last.  */
 275           { if ($8 <= 7 && rx_uintop ($4, 8) && rx_disp5op0 (&$6, BSIZE))
 276               { B2 (0x3c, 0); rx_field5s2 ($6); F ($8, 9, 3); O1 ($4); }
 277             else
 278               { B2 (0xf8, 0x04); F ($8, 8, 4); DSP ($6, 6, BSIZE); O1 ($4);
 279               if ($4.X_op != O_constant && $4.X_op != O_big) rx_linkrelax_imm (12); } }
 280
 281         | MOV DOT_W '#' EXPR ',' disp '[' REG ']'
 282           { if ($8 <= 7 && rx_uintop ($4, 8) && rx_disp5op0 (&$6, WSIZE))
 283               { B2 (0x3d, 0); rx_field5s2 ($6); F ($8, 9, 3); O1 ($4); }
 284             else
 285               { B2 (0xf8, 0x01); F ($8, 8, 4); DSP ($6, 6, WSIZE); IMMW ($4, 12); } }
 286
 287         | MOV DOT_L '#' EXPR ',' disp '[' REG ']'
 288           { if ($8 <= 7 && rx_uintop ($4, 8) && rx_disp5op0 (&$6, LSIZE))
 289               { B2 (0x3e, 0); rx_field5s2 ($6); F ($8, 9, 3); O1 ($4); }
 290             else
 291               { B2 (0xf8, 0x02); F ($8, 8, 4); DSP ($6, 6, LSIZE); IMM ($4, 12); } }
 292
 293 /* ---------------------------------------------------------------------- */
 294
 295         | RTSD '#' EXPR ',' REG '-' REG
 296           { B2 (0x3f, 0); F ($5, 8, 4); F ($7, 12, 4); rtsd_immediate ($3);
 297             if ($5 == 0)
 298               rx_error (_("RTSD cannot pop R0"));
 299             if ($5 > $7)
 300               rx_error (_("RTSD first reg must be <= second reg")); }
 301
 302 /* ---------------------------------------------------------------------- */
 303
 304         | CMP REG ',' REG
 305           { B2 (0x47, 0); F ($2, 8, 4); F ($4, 12, 4); }
 306
 307 /* ---------------------------------------------------------------------- */
 308
 309         | CMP disp '[' REG ']' DOT_UB ',' REG
 310           { B2 (0x44, 0); F ($4, 8, 4); F ($8, 12, 4); DSP ($2, 6, BSIZE); }
 311
 312         | CMP disp '[' REG ']' memex ',' REG
 313           { B3 (MEMEX, 0x04, 0); F ($6, 8, 2);  F ($4, 16, 4); F ($8, 20, 4); DSP ($2, 14, sizemap[$6]); }
 314
 315 /* ---------------------------------------------------------------------- */
 316
 317         | MOVU bw REG ',' REG
 318           { B2 (0x5b, 0x00); F ($2, 5, 1); F ($3, 8, 4); F ($5, 12, 4); }
 319
 320 /* ---------------------------------------------------------------------- */
 321
 322         | MOVU bw '[' REG ']' ',' REG
 323           { B2 (0x58, 0x00); F ($2, 5, 1); F ($4, 8, 4); F ($7, 12, 4); }
 324
 325         | MOVU bw EXPR '[' REG ']' ',' REG
 326           { if ($5 <= 7 && $8 <= 7 && rx_disp5op (&$3, $2))
 327               { B2 (0xb0, 0); F ($2, 4, 1); F ($5, 9, 3); F ($8, 13, 3); rx_field5s ($3); }
 328             else
 329               { B2 (0x58, 0x00); F ($2, 5, 1); F ($5, 8, 4); F ($8, 12, 4); DSP ($3, 6, $2); } }
 330
 331 /* ---------------------------------------------------------------------- */
 332
 333         | SUB '#' EXPR ',' REG
 334           { if (rx_uintop ($3, 4))
 335               { B2 (0x60, 0); FE ($3, 8, 4); F ($5, 12, 4); }
 336             else
 337               /* This is really an add, but we negate the immediate.  */
 338               { B2 (0x70, 0); F ($5, 8, 4); F ($5, 12, 4); NIMM ($3, 6); } }
 339
 340         | CMP '#' EXPR ',' REG
 341           { if (rx_uintop ($3, 4))
 342               { B2 (0x61, 0); FE ($3, 8, 4); F ($5, 12, 4); }
 343             else if (rx_uintop ($3, 8))
 344               { B2 (0x75, 0x50); F ($5, 12, 4); UO1 ($3); }
 345             else
 346               { B2 (0x74, 0x00); F ($5, 12, 4); IMM ($3, 6); } }
 347
 348         | ADD '#' EXPR ',' REG
 349           { if (rx_uintop ($3, 4))
 350               { B2 (0x62, 0); FE ($3, 8, 4); F ($5, 12, 4); }
 351             else
 352               { B2 (0x70, 0); F ($5, 8, 4); F ($5, 12, 4); IMM ($3, 6); } }
 353
 354         | MUL '#' EXPR ',' REG
 355           { if (rx_uintop ($3, 4))
 356               { B2 (0x63, 0); FE ($3, 8, 4); F ($5, 12, 4); }
 357             else
 358               { B2 (0x74, 0x10); F ($5, 12, 4); IMM ($3, 6); } }
 359
 360         | AND_ '#' EXPR ',' REG
 361           { if (rx_uintop ($3, 4))
 362               { B2 (0x64, 0); FE ($3, 8, 4); F ($5, 12, 4); }
 363             else
 364               { B2 (0x74, 0x20); F ($5, 12, 4); IMM ($3, 6); } }
 365
 366         | OR '#' EXPR ',' REG
 367           { if (rx_uintop ($3, 4))
 368               { B2 (0x65, 0); FE ($3, 8, 4); F ($5, 12, 4); }
 369             else
 370               { B2 (0x74, 0x30); F ($5, 12, 4); IMM ($3, 6); } }
 371
 372         | MOV DOT_L '#' EXPR ',' REG
 373           { if (rx_uintop ($4, 4))
 374               { B2 (0x66, 0); FE ($4, 8, 4); F ($6, 12, 4); }
 375             else if (rx_uintop ($4, 8))
 376               { B2 (0x75, 0x40); F ($6, 12, 4); UO1 ($4); }
 377             else
 378               { B2 (0xfb, 0x02); F ($6, 8, 4); IMM ($4, 12); } }
 379
 380         | MOV '#' EXPR ',' REG
 381           { if (rx_uintop ($3, 4))
 382               { B2 (0x66, 0); FE ($3, 8, 4); F ($5, 12, 4); }
 383             else if (rx_uintop ($3, 8))
 384               { B2 (0x75, 0x40); F ($5, 12, 4); UO1 ($3); }
 385             else
 386               { B2 (0xfb, 0x02); F ($5, 8, 4); IMM ($3, 12); } }
 387
 388 /* ---------------------------------------------------------------------- */
 389
 390         | RTSD '#' EXPR
 391           { B1 (0x67); rtsd_immediate ($3); }
 392
 393 /* ---------------------------------------------------------------------- */
 394
 395         | SHLR { sub_op = 0; } op_shift
 396         | SHAR { sub_op = 1; } op_shift
 397         | SHLL { sub_op = 2; } op_shift
 398
 399 /* ---------------------------------------------------------------------- */
 400
 401         | PUSHM REG '-' REG
 402           {
 403             if ($2 == $4)
 404               { B2 (0x7e, 0x80); F (LSIZE, 10, 2); F ($2, 12, 4); }
 405             else
 406              { B2 (0x6e, 0); F ($2, 8, 4); F ($4, 12, 4); }
 407             if ($2 == 0)
 408               rx_error (_("PUSHM cannot push R0"));
 409             if ($2 > $4)
 410               rx_error (_("PUSHM first reg must be <= second reg")); }
 411
 412 /* ---------------------------------------------------------------------- */
 413
 414         | POPM REG '-' REG
 415           {
 416             if ($2 == $4)
 417               { B2 (0x7e, 0xb0); F ($2, 12, 4); }
 418             else
 419               { B2 (0x6f, 0); F ($2, 8, 4); F ($4, 12, 4); }
 420             if ($2 == 0)
 421               rx_error (_("POPM cannot pop R0"));
 422             if ($2 > $4)
 423               rx_error (_("POPM first reg must be <= second reg")); }
 424
 425 /* ---------------------------------------------------------------------- */
 426
 427         | ADD '#' EXPR ',' REG ',' REG
 428           { B2 (0x70, 0x00); F ($5, 8, 4); F ($7, 12, 4); IMM ($3, 6); }
 429
 430 /* ---------------------------------------------------------------------- */
 431
 432         | INT '#' EXPR
 433           { B2(0x75, 0x60), UO1 ($3); }
 434
 435 /* ---------------------------------------------------------------------- */
 436
 437         | BSET '#' EXPR ',' REG
 438           { B2 (0x78, 0); FE ($3, 7, 5); F ($5, 12, 4); }
 439         | BCLR '#' EXPR ',' REG
 440           { B2 (0x7a, 0); FE ($3, 7, 5); F ($5, 12, 4); }
 441
 442 /* ---------------------------------------------------------------------- */
 443
 444         | BTST '#' EXPR ',' REG
 445           { B2 (0x7c, 0x00); FE ($3, 7, 5); F ($5, 12, 4); }
 446
 447 /* ---------------------------------------------------------------------- */
 448
 449         | SAT REG
 450           { B2 (0x7e, 0x30); F ($2, 12, 4); }
 451         | RORC REG
 452           { B2 (0x7e, 0x40); F ($2, 12, 4); }
 453         | ROLC REG
 454           { B2 (0x7e, 0x50); F ($2, 12, 4); }
 455
 456 /* ---------------------------------------------------------------------- */
 457
 458         | PUSH bwl REG
 459           { B2 (0x7e, 0x80); F ($2, 10, 2); F ($3, 12, 4); }
 460
 461 /* ---------------------------------------------------------------------- */
 462
 463         | POP REG
 464           { B2 (0x7e, 0xb0); F ($2, 12, 4); }
 465
 466 /* ---------------------------------------------------------------------- */
 467
 468         | PUSHC CREG
 469           { if ($2 < 16)
 470               { B2 (0x7e, 0xc0); F ($2, 12, 4); }
 471             else
 472               as_bad (_("PUSHC can only push the first 16 control registers")); }
 473
 474 /* ---------------------------------------------------------------------- */
 475
 476         | POPC CREG
 477           { if ($2 < 16)
 478               { B2 (0x7e, 0xe0); F ($2, 12, 4); }
 479             else
 480               as_bad (_("POPC can only pop the first 16 control registers")); }
 481
 482 /* ---------------------------------------------------------------------- */
 483
 484         | SETPSW flag
 485           { B2 (0x7f, 0xa0); F ($2, 12, 4); }
 486         | CLRPSW flag
 487           { B2 (0x7f, 0xb0); F ($2, 12, 4); }
 488
 489 /* ---------------------------------------------------------------------- */
 490
 491         | JMP REG
 492           { B2 (0x7f, 0x00); F ($2, 12, 4); }
 493         | JSR REG
 494           { B2 (0x7f, 0x10); F ($2, 12, 4); }
 495         | BRA opt_l REG
 496           { B2 (0x7f, 0x40); F ($3, 12, 4); }
 497         | BSR opt_l REG
 498           { B2 (0x7f, 0x50); F ($3, 12, 4); }
 499
 500 /* ---------------------------------------------------------------------- */
 501
 502         | SCMPU
 503           { B2 (0x7f, 0x83); }
 504         | SMOVU
 505           { B2 (0x7f, 0x87); }
 506         | SMOVB
 507           { B2 (0x7f, 0x8b); }
 508         | SMOVF
 509           { B2 (0x7f, 0x8f); }
 510
 511 /* ---------------------------------------------------------------------- */
 512
 513         | SUNTIL bwl
 514           { B2 (0x7f, 0x80); F ($2, 14, 2); }
 515         | SWHILE bwl
 516           { B2 (0x7f, 0x84); F ($2, 14, 2); }
 517         | SSTR bwl
 518           { B2 (0x7f, 0x88); F ($2, 14, 2); }
 519
 520 /* ---------------------------------------------------------------------- */
 521
 522         | RMPA bwl
 523           { B2 (0x7f, 0x8c); F ($2, 14, 2); }
 524
 525 /* ---------------------------------------------------------------------- */
 526
 527         | RTFI
 528           { B2 (0x7f, 0x94); }
 529         | RTE
 530           { B2 (0x7f, 0x95); }
 531         | WAIT
 532           { B2 (0x7f, 0x96); }
 533         | SATR
 534           { B2 (0x7f, 0x93); }
 535
 536 /* ---------------------------------------------------------------------- */
 537
 538         | MVTIPL '#' EXPR
 539           { B3 (0x75, 0x70, 0x00); FE ($3, 20, 4); }
 540
 541 /* ---------------------------------------------------------------------- */
 542
 543         /* rx_disp5op changes the value if it succeeds, so keep it last.  */
 544         | MOV bwl REG ',' EXPR '[' REG ']'
 545           { if ($3 <= 7 && $7 <= 7 && rx_disp5op (&$5, $2))
 546               { B2 (0x80, 0); F ($2, 2, 2); F ($7, 9, 3); F ($3, 13, 3); rx_field5s ($5); }
 547             else
 548               { B2 (0xc3, 0x00); F ($2, 2, 2); F ($7, 8, 4); F ($3, 12, 4); DSP ($5, 4, $2); }}
 549
 550 /* ---------------------------------------------------------------------- */
 551
 552         | MOV bwl EXPR '[' REG ']' ',' REG
 553           { if ($5 <= 7 && $8 <= 7 && rx_disp5op (&$3, $2))
 554               { B2 (0x88, 0); F ($2, 2, 2); F ($5, 9, 3); F ($8, 13, 3); rx_field5s ($3); }
 555             else
 556               { B2 (0xcc, 0x00); F ($2, 2, 2); F ($5, 8, 4); F ($8, 12, 4); DSP ($3, 6, $2); } }
 557
 558 /* ---------------------------------------------------------------------- */
 559
 560         /* MOV a,b - if a is a reg and b is mem, src and dest are
 561            swapped.  */
 562
 563         /* We don't use "disp" here because it causes a shift/reduce
 564            conflict with the other displacement-less patterns.  */
 565
 566         | MOV bwl REG ',' '[' REG ']'
 567           { B2 (0xc3, 0x00); F ($2, 2, 2); F ($6, 8, 4); F ($3, 12, 4); }
 568
 569 /* ---------------------------------------------------------------------- */
 570
 571         | MOV bwl '[' REG ']' ',' disp '[' REG ']'
 572           { B2 (0xc0, 0); F ($2, 2, 2); F ($4, 8, 4); F ($9, 12, 4); DSP ($7, 4, $2); }
 573
 574 /* ---------------------------------------------------------------------- */
 575
 576         | MOV bwl EXPR '[' REG ']' ',' disp '[' REG ']'
 577           { B2 (0xc0, 0x00); F ($2, 2, 2); F ($5, 8, 4); F ($10, 12, 4); DSP ($3, 6, $2); DSP ($8, 4, $2); }
 578
 579 /* ---------------------------------------------------------------------- */
 580
 581         | MOV bwl REG ',' REG
 582           { B2 (0xcf, 0x00); F ($2, 2, 2); F ($3, 8, 4); F ($5, 12, 4); }
 583
 584 /* ---------------------------------------------------------------------- */
 585
 586         | MOV bwl '[' REG ']' ',' REG
 587           { B2 (0xcc, 0x00); F ($2, 2, 2); F ($4, 8, 4); F ($7, 12, 4); }
 588
 589 /* ---------------------------------------------------------------------- */
 590
 591         | BSET '#' EXPR ',' disp '[' REG ']' DOT_B
 592           { B2 (0xf0, 0x00); F ($7, 8, 4); FE ($3, 13, 3); DSP ($5, 6, BSIZE); }
 593         | BCLR '#' EXPR ',' disp '[' REG ']' DOT_B
 594           { B2 (0xf0, 0x08); F ($7, 8, 4); FE ($3, 13, 3); DSP ($5, 6, BSIZE); }
 595         | BTST '#' EXPR ',' disp '[' REG ']' DOT_B
 596           { B2 (0xf4, 0x00); F ($7, 8, 4); FE ($3, 13, 3); DSP ($5, 6, BSIZE); }
 597
 598 /* ---------------------------------------------------------------------- */
 599
 600         | PUSH bwl disp '[' REG ']'
 601           { B2 (0xf4, 0x08); F ($2, 14, 2); F ($5, 8, 4); DSP ($3, 6, $2); }
 602
 603 /* ---------------------------------------------------------------------- */
 604
 605         | SBB   { sub_op = 0; } op_dp20_rm_l
 606         | NEG   { sub_op = 1; sub_op2 = 1; } op_dp20_rr
 607         | ADC   { sub_op = 2; } op_dp20_rim_l
 608         | ABS   { sub_op = 3; sub_op2 = 2; } op_dp20_rr
 609         | MAX   { sub_op = 4; } op_dp20_rim
 610         | MIN   { sub_op = 5; } op_dp20_rim
 611         | EMUL  { sub_op = 6; } op_dp20_i
 612         | EMULU { sub_op = 7; } op_dp20_i
 613         | DIV   { sub_op = 8; } op_dp20_rim
 614         | DIVU  { sub_op = 9; } op_dp20_rim
 615         | TST   { sub_op = 12; } op_dp20_rim
 616         | XOR   { sub_op = 13; } op_dp20_rim
 617         | NOT   { sub_op = 14; sub_op2 = 0; } op_dp20_rr
 618         | STZ   { sub_op = 14; } op_dp20_i
 619         | STNZ  { sub_op = 15; } op_dp20_i
 620
 621 /* ---------------------------------------------------------------------- */
 622
 623         | EMUL  { sub_op = 6; } op_xchg
 624         | EMULU { sub_op = 7; } op_xchg
 625         | XCHG  { sub_op = 16; } op_xchg
 626         | ITOF  { sub_op = 17; } op_xchg
 627
 628 /* ---------------------------------------------------------------------- */
 629
 630         | BSET REG ',' REG
 631           { id24 (1, 0x63, 0x00); F ($4, 16, 4); F ($2, 20, 4); }
 632         | BCLR REG ',' REG
 633           { id24 (1, 0x67, 0x00); F ($4, 16, 4); F ($2, 20, 4); }
 634         | BTST REG ',' REG
 635           { id24 (1, 0x6b, 0x00); F ($4, 16, 4); F ($2, 20, 4); }
 636         | BNOT REG ',' REG
 637           { id24 (1, 0x6f, 0x00); F ($4, 16, 4); F ($2, 20, 4); }
 638
 639         | BSET REG ',' disp '[' REG ']' DOT_B
 640           { id24 (1, 0x60, 0x00); F ($6, 16, 4); F ($2, 20, 4); DSP ($4, 14, BSIZE); }
 641         | BCLR REG ',' disp '[' REG ']' DOT_B
 642           { id24 (1, 0x64, 0x00); F ($6, 16, 4); F ($2, 20, 4); DSP ($4, 14, BSIZE); }
 643         | BTST REG ',' disp '[' REG ']' DOT_B
 644           { id24 (1, 0x68, 0x00); F ($6, 16, 4); F ($2, 20, 4); DSP ($4, 14, BSIZE); }
 645         | BNOT REG ',' disp '[' REG ']' DOT_B
 646           { id24 (1, 0x6c, 0x00); F ($6, 16, 4); F ($2, 20, 4); DSP ($4, 14, BSIZE); }
 647
 648 /* ---------------------------------------------------------------------- */
 649
 650         | FSUB  { sub_op = 0; } float2_op
 651         | FCMP  { sub_op = 1; } float2_op
 652         | FADD  { sub_op = 2; } float2_op
 653         | FMUL  { sub_op = 3; } float2_op
 654         | FDIV  { sub_op = 4; } float2_op
 655         | FTOI  { sub_op = 5; } float2_op_ni
 656         | ROUND { sub_op = 6; } float2_op_ni
 657
 658 /* ---------------------------------------------------------------------- */
 659
 660         | SCCND DOT_L REG
 661           { id24 (1, 0xdb, 0x00); F ($1, 20, 4); F ($3, 16, 4); }
 662         | SCCND bwl disp '[' REG ']'
 663           { id24 (1, 0xd0, 0x00); F ($1, 20, 4); F ($2, 12, 2); F ($5, 16, 4); DSP ($3, 14, $2); }
 664
 665 /* ---------------------------------------------------------------------- */
 666
 667         | BMCND '#' EXPR ',' disp '[' REG ']' DOT_B
 668           { id24 (1, 0xe0, 0x00); F ($1, 20, 4); FE ($3, 11, 3);
 669               F ($7, 16, 4); DSP ($5, 14, BSIZE); }
 670
 671 /* ---------------------------------------------------------------------- */
 672
 673         | BNOT '#' EXPR ',' disp '[' REG ']' DOT_B
 674           { id24 (1, 0xe0, 0x0f); FE ($3, 11, 3); F ($7, 16, 4);
 675               DSP ($5, 14, BSIZE); }
 676
 677 /* ---------------------------------------------------------------------- */
 678
 679         | MULHI REG ',' REG
 680           { id24 (2, 0x00, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
 681         | MULLO REG ',' REG
 682           { id24 (2, 0x01, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
 683         | MACHI REG ',' REG
 684           { id24 (2, 0x04, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
 685         | MACLO REG ',' REG
 686           { id24 (2, 0x05, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
 687
 688 /* ---------------------------------------------------------------------- */
 689
 690         /* We don't have syntax for these yet.  */
 691         | MVTACHI REG
 692           { id24 (2, 0x17, 0x00); F ($2, 20, 4); }
 693         | MVTACLO REG
 694           { id24 (2, 0x17, 0x10); F ($2, 20, 4); }
 695         | MVFACHI REG
 696           { id24 (2, 0x1f, 0x00); F ($2, 20, 4); }
 697         | MVFACMI REG
 698           { id24 (2, 0x1f, 0x20); F ($2, 20, 4); }
 699         | MVFACLO REG
 700           { id24 (2, 0x1f, 0x10); F ($2, 20, 4); }
 701
 702         | RACW '#' EXPR
 703           { id24 (2, 0x18, 0x00);
 704             if (rx_uintop ($3, 4) && $3.X_add_number == 1)
 705               ;
 706             else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
 707               F (1, 19, 1);
 708             else
 709               as_bad (_("RACW expects #1 or #2"));}
 710
 711 /* ---------------------------------------------------------------------- */
 712
 713         | MOV bwl REG ',' '[' REG '+' ']'
 714           { id24 (2, 0x20, 0); F ($2, 14, 2); F ($6, 16, 4); F ($3, 20, 4); }
 715         | MOV bwl REG ',' '[' '-' REG ']'
 716           { id24 (2, 0x24, 0); F ($2, 14, 2); F ($7, 16, 4); F ($3, 20, 4); }
 717
 718 /* ---------------------------------------------------------------------- */
 719
 720         | MOV bwl '[' REG '+' ']' ',' REG
 721           { id24 (2, 0x28, 0); F ($2, 14, 2); F ($4, 16, 4); F ($8, 20, 4); }
 722         | MOV bwl '[' '-' REG ']' ',' REG
 723           { id24 (2, 0x2c, 0); F ($2, 14, 2); F ($5, 16, 4); F ($8, 20, 4); }
 724
 725 /* ---------------------------------------------------------------------- */
 726
 727         | MOVU bw '[' REG '+' ']' ','  REG
 728           { id24 (2, 0x38, 0); F ($2, 15, 1); F ($4, 16, 4); F ($8, 20, 4); }
 729         | MOVU bw '[' '-' REG ']' ',' REG
 730           { id24 (2, 0x3c, 0); F ($2, 15, 1); F ($5, 16, 4); F ($8, 20, 4); }
 731
 732 /* ---------------------------------------------------------------------- */
 733
 734         | ROTL { sub_op = 6; } op_shift_rot
 735         | ROTR { sub_op = 4; } op_shift_rot
 736         | REVW { sub_op = 5; } op_shift_rot
 737         | REVL { sub_op = 7; } op_shift_rot
 738
 739 /* ---------------------------------------------------------------------- */
 740
 741         | MVTC REG ',' CREG
 742           { id24 (2, 0x68, 0x00); F ($4 % 16, 20, 4); F ($4 / 16, 15, 1);
 743             F ($2, 16, 4); }
 744
 745 /* ---------------------------------------------------------------------- */
 746
 747         | MVFC CREG ',' REG
 748           { id24 (2, 0x6a, 0); F ($2, 15, 5); F ($4, 20, 4); }
 749
 750 /* ---------------------------------------------------------------------- */
 751
 752         | ROTL '#' EXPR ',' REG
 753           { id24 (2, 0x6e, 0); FE ($3, 15, 5); F ($5, 20, 4); }
 754         | ROTR '#' EXPR ',' REG
 755           { id24 (2, 0x6c, 0); FE ($3, 15, 5); F ($5, 20, 4); }
 756
 757 /* ---------------------------------------------------------------------- */
 758
 759         | MVTC '#' EXPR ',' CREG
 760           { id24 (2, 0x73, 0x00); F ($5, 19, 5); IMM ($3, 12); }
 761
 762 /* ---------------------------------------------------------------------- */
 763
 764         | BMCND '#' EXPR ',' REG
 765           { id24 (2, 0xe0, 0x00); F ($1, 16, 4); FE ($3, 11, 5);
 766               F ($5, 20, 4); }
 767
 768 /* ---------------------------------------------------------------------- */
 769
 770         | BNOT '#' EXPR ',' REG
 771           { id24 (2, 0xe0, 0xf0); FE ($3, 11, 5); F ($5, 20, 4); }
 772
 773 /* ---------------------------------------------------------------------- */
 774
 775         | MOV bwl REG ',' '[' REG ',' REG ']'
 776           { id24 (3, 0x00, 0); F ($2, 10, 2); F ($6, 12, 4); F ($8, 16, 4); F ($3, 20, 4); }
 777
 778         | MOV bwl '[' REG ',' REG ']' ',' REG
 779           { id24 (3, 0x40, 0); F ($2, 10, 2); F ($4, 12, 4); F ($6, 16, 4); F ($9, 20, 4); }
 780
 781         | MOVU bw '[' REG ',' REG ']' ',' REG
 782           { id24 (3, 0xc0, 0); F ($2, 10, 2); F ($4, 12, 4); F ($6, 16, 4); F ($9, 20, 4); }
 783
 784 /* ---------------------------------------------------------------------- */
 785
 786         | SUB { sub_op = 0; } op_subadd
 787         | ADD { sub_op = 2; } op_subadd
 788         | MUL { sub_op = 3; } op_subadd
 789         | AND_ { sub_op = 4; } op_subadd
 790         | OR  { sub_op = 5; } op_subadd
 791
 792 /* ---------------------------------------------------------------------- */
 793 /* There is no SBB #imm so we fake it with ADC.  */
 794
 795         | SBB '#' EXPR ',' REG
 796           { id24 (2, 0x70, 0x20); F ($5, 20, 4); NBIMM ($3, 12); }
 797
 798 /* ---------------------------------------------------------------------- */
 799
 800         ;
 801
 802 /* ====================================================================== */
 803
 804 op_subadd
 805         : REG ',' REG
 806           { B2 (0x43 + (sub_op<<2), 0); F ($1, 8, 4); F ($3, 12, 4); }
 807         | disp '[' REG ']' DOT_UB ',' REG
 808           { B2 (0x40 + (sub_op<<2), 0); F ($3, 8, 4); F ($7, 12, 4); DSP ($1, 6, BSIZE); }
 809         | disp '[' REG ']' memex ',' REG
 810           { B3 (MEMEX, sub_op<<2, 0); F ($5, 8, 2); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, sizemap[$5]); }
 811         | REG ',' REG ',' REG
 812           { id24 (4, sub_op<<4, 0), F ($5, 12, 4), F ($1, 16, 4), F ($3, 20, 4); }
 813         ;
 814
 815 /* sbb, neg, adc, abs, max, min, div, divu, tst, not, xor, stz, stnz, emul, emulu */
 816
 817 op_dp20_rm_l
 818         : REG ',' REG
 819           { id24 (1, 0x03 + (sub_op<<2), 0x00); F ($1, 16, 4); F ($3, 20, 4); }
 820         | disp '[' REG ']' opt_l ',' REG
 821           { B4 (MEMEX, 0xa0, 0x00 + sub_op, 0x00);
 822           F ($3, 24, 4); F ($7, 28, 4); DSP ($1, 14, LSIZE); }
 823         ;
 824
 825 /* neg, adc, abs, max, min, div, divu, tst, not, xor, stz, stnz, emul, emulu */
 826
 827 op_dp20_rm
 828         : REG ',' REG
 829           { id24 (1, 0x03 + (sub_op<<2), 0x00); F ($1, 16, 4); F ($3, 20, 4); }
 830         | disp '[' REG ']' DOT_UB ',' REG
 831           { id24 (1, 0x00 + (sub_op<<2), 0x00); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, BSIZE); }
 832         | disp '[' REG ']' memex ',' REG
 833           { B4 (MEMEX, 0x20 + ($5 << 6), 0x00 + sub_op, 0x00);
 834           F ($3, 24, 4); F ($7, 28, 4); DSP ($1, 14, sizemap[$5]); }
 835         ;
 836
 837 op_dp20_i
 838         : '#' EXPR ',' REG
 839           { id24 (2, 0x70, sub_op<<4); F ($4, 20, 4); IMM ($2, 12); }
 840         ;
 841
 842 op_dp20_rim
 843         : op_dp20_rm
 844         | op_dp20_i
 845         ;
 846
 847 op_dp20_rim_l
 848         : op_dp20_rm_l
 849         | op_dp20_i
 850         ;
 851
 852 op_dp20_rr
 853         : REG ',' REG
 854           { id24 (1, 0x03 + (sub_op<<2), 0x00); F ($1, 16, 4); F ($3, 20, 4); }
 855         | REG
 856           { B2 (0x7e, sub_op2 << 4); F ($1, 12, 4); }
 857         ;
 858
 859 /* xchg, itof, emul, emulu */
 860 op_xchg
 861         : REG ',' REG
 862           { id24 (1, 0x03 + (sub_op<<2), 0); F ($1, 16, 4); F ($3, 20, 4); }
 863         | disp '[' REG ']' DOT_UB ',' REG
 864           { id24 (1, 0x00 + (sub_op<<2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, BSIZE); }
 865         | disp '[' REG ']' memex ',' REG
 866           { B4 (MEMEX, 0x20, 0x00 + sub_op, 0); F ($5, 8, 2); F ($3, 24, 4); F ($7, 28, 4);
 867             DSP ($1, 14, sizemap[$5]); }
 868         ;
 869
 870 /* 000:SHLR, 001:SHAR, 010:SHLL, 011:-, 100:ROTR, 101:REVW, 110:ROTL, 111:REVL */
 871 op_shift_rot
 872         : REG ',' REG
 873           { id24 (2, 0x60 + sub_op, 0); F ($1, 16, 4); F ($3, 20, 4); }
 874         ;
 875 op_shift
 876         : '#' EXPR ',' REG
 877           { B2 (0x68 + (sub_op<<1), 0); FE ($2, 7, 5); F ($4, 12, 4); }
 878         | '#' EXPR ',' REG ',' REG
 879           { id24 (2, 0x80 + (sub_op << 5), 0); FE ($2, 11, 5); F ($4, 16, 4); F ($6, 20, 4); }
 880         | op_shift_rot
 881         ;
 882
 883
 884 float2_op
 885         : '#' EXPR ',' REG
 886         { rx_check_float_support (); id24 (2, 0x72, sub_op << 4); F ($4, 20, 4); O4 ($2); }
 887         | float2_op_ni
 888         ;
 889 float2_op_ni
 890         : REG ',' REG
 891           { rx_check_float_support (); id24 (1, 0x83 + (sub_op << 2), 0); F ($1, 16, 4); F ($3, 20, 4); }
 892         | disp '[' REG ']' opt_l ',' REG
 893           { rx_check_float_support (); id24 (1, 0x80 + (sub_op << 2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, LSIZE); }
 894         ;
 895
 896 /* ====================================================================== */
 897
 898 disp    :      { $$ = zero_expr (); }
 899         | EXPR { $$ = $1; }
 900         ;
 901
 902 flag    : { need_flag = 1; } FLAG { need_flag = 0; $$ = $2; }
 903         ;
 904
 905 /* DOT_UB is not listed here, it's handled with a separate pattern.  */
 906 /* Use sizemap[$n] to get LSIZE etc.  */
 907 memex   : DOT_B  { $$ = 0; }
 908         | DOT_W  { $$ = 1; }
 909         |        { $$ = 2; }
 910         | DOT_L  { $$ = 2; }
 911         | DOT_UW { $$ = 3; }
 912         ;
 913
 914 bwl     :       { $$ = LSIZE; }
 915         | DOT_B { $$ = BSIZE; }
 916         | DOT_W { $$ = WSIZE; }
 917         | DOT_L { $$ = LSIZE; }
 918         ;
 919
 920 bw      :       { $$ = 1; }
 921         | DOT_B { $$ = 0; }
 922         | DOT_W { $$ = 1; }
 923         ;
 924
 925 opt_l   :       {}
 926         | DOT_L {}
 927         ;
 928
 929 %%
 930 /* ====================================================================== */
 931
 932 static struct
 933 {
 934   const char * string;
 935   int          token;
 936   int          val;
 937 }
 938 token_table[] =
 939 {
 940   { "r0", REG, 0 },
 941   { "r1", REG, 1 },
 942   { "r2", REG, 2 },
 943   { "r3", REG, 3 },
 944   { "r4", REG, 4 },
 945   { "r5", REG, 5 },
 946   { "r6", REG, 6 },
 947   { "r7", REG, 7 },
 948   { "r8", REG, 8 },
 949   { "r9", REG, 9 },
 950   { "r10", REG, 10 },
 951   { "r11", REG, 11 },
 952   { "r12", REG, 12 },
 953   { "r13", REG, 13 },
 954   { "r14", REG, 14 },
 955   { "r15", REG, 15 },
 956
 957   { "psw", CREG, 0 },
 958   { "pc", CREG, 1 },
 959   { "usp", CREG, 2 },
 960   { "fpsw", CREG, 3 },
 961   /* reserved */
 962   /* reserved */
 963   /* reserved */
 964   { "wr", CREG, 7 },
 965
 966   { "bpsw", CREG, 8 },
 967   { "bpc", CREG, 9 },
 968   { "isp", CREG, 10 },
 969   { "fintv", CREG, 11 },
 970   { "intb", CREG, 12 },
 971
 972   { "pbp", CREG, 16 },
 973   { "pben", CREG, 17 },
 974
 975   { "bbpsw", CREG, 24 },
 976   { "bbpc", CREG, 25 },
 977
 978   { ".s", DOT_S, 0 },
 979   { ".b", DOT_B, 0 },
 980   { ".w", DOT_W, 0 },
 981   { ".l", DOT_L, 0 },
 982   { ".a", DOT_A , 0},
 983   { ".ub", DOT_UB, 0 },
 984   { ".uw", DOT_UW , 0},
 985
 986   { "c", FLAG, 0 },
 987   { "z", FLAG, 1 },
 988   { "s", FLAG, 2 },
 989   { "o", FLAG, 3 },
 990   { "i", FLAG, 8 },
 991   { "u", FLAG, 9 },
 992
 993 #define OPC(x) { #x, x, IS_OPCODE }
 994   OPC(ABS),
 995   OPC(ADC),
 996   OPC(ADD),
 997   { "and", AND_, IS_OPCODE },
 998   OPC(BCLR),
 999   OPC(BCND),
1000   OPC(BMCND),
1001   OPC(BNOT),
1002   OPC(BRA),
1003   OPC(BRK),
1004   OPC(BSET),
1005   OPC(BSR),
1006   OPC(BTST),
1007   OPC(CLRPSW),
1008   OPC(CMP),
1009   OPC(DBT),
1010   OPC(DIV),
1011   OPC(DIVU),
1012   OPC(EDIV),
1013   OPC(EDIVU),
1014   OPC(EMUL),
1015   OPC(EMULU),
1016   OPC(FADD),
1017   OPC(FCMP),
1018   OPC(FDIV),
1019   OPC(FMUL),
1020   OPC(FREIT),
1021   OPC(FSUB),
1022   OPC(FTOI),
1023   OPC(INT),
1024   OPC(ITOF),
1025   OPC(JMP),
1026   OPC(JSR),
1027   OPC(MVFACHI),
1028   OPC(MVFACMI),
1029   OPC(MVFACLO),
1030   OPC(MVFC),
1031   OPC(MVTACHI),
1032   OPC(MVTACLO),
1033   OPC(MVTC),
1034   OPC(MVTIPL),
1035   OPC(MACHI),
1036   OPC(MACLO),
1037   OPC(MAX),
1038   OPC(MIN),
1039   OPC(MOV),
1040   OPC(MOVU),
1041   OPC(MUL),
1042   OPC(MULHI),
1043   OPC(MULLO),
1044   OPC(MULU),
1045   OPC(NEG),
1046   OPC(NOP),
1047   OPC(NOT),
1048   OPC(OR),
1049   OPC(POP),
1050   OPC(POPC),
1051   OPC(POPM),
1052   OPC(PUSH),
1053   OPC(PUSHA),
1054   OPC(PUSHC),
1055   OPC(PUSHM),
1056   OPC(RACW),
1057   OPC(REIT),
1058   OPC(REVL),
1059   OPC(REVW),
1060   OPC(RMPA),
1061   OPC(ROLC),
1062   OPC(RORC),
1063   OPC(ROTL),
1064   OPC(ROTR),
1065   OPC(ROUND),
1066   OPC(RTE),
1067   OPC(RTFI),
1068   OPC(RTS),
1069   OPC(RTSD),
1070   OPC(SAT),
1071   OPC(SATR),
1072   OPC(SBB),
1073   OPC(SCCND),
1074   OPC(SCMPU),
1075   OPC(SETPSW),
1076   OPC(SHAR),
1077   OPC(SHLL),
1078   OPC(SHLR),
1079   OPC(SMOVB),
1080   OPC(SMOVF),
1081   OPC(SMOVU),
1082   OPC(SSTR),
1083   OPC(STNZ),
1084   OPC(STOP),
1085   OPC(STZ),
1086   OPC(SUB),
1087   OPC(SUNTIL),
1088   OPC(SWHILE),
1089   OPC(TST),
1090   OPC(WAIT),
1091   OPC(XCHG),
1092   OPC(XOR),
1093 };
1094
1095 #define NUM_TOKENS (sizeof (token_table) / sizeof (token_table[0]))
1096
1097 static struct
1098 {
1099   char * string;
1100   int    token;
1101 }
1102 condition_opcode_table[] =
1103 {
1104   { "b", BCND },
1105   { "bm", BMCND },
1106   { "sc", SCCND },
1107 };
1108
1109 #define NUM_CONDITION_OPCODES (sizeof (condition_opcode_table) / sizeof (condition_opcode_table[0]))
1110
1111 static struct
1112 {
1113   char * string;
1114   int    val;
1115 }
1116 condition_table[] =
1117 {
1118   { "z", 0 },
1119   { "eq", 0 },
1120   { "geu",  2 },
1121   { "c",  2 },
1122   { "gtu", 4 },
1123   { "pz", 6 },
1124   { "ge", 8 },
1125   { "gt", 10 },
1126   { "o",  12},
1127   /* always = 14 */
1128   { "nz", 1 },
1129   { "ne", 1 },
1130   { "ltu", 3 },
1131   { "nc", 3 },
1132   { "leu", 5 },
1133   { "n", 7 },
1134   { "lt", 9 },
1135   { "le", 11 },
1136   { "no", 13 }
1137   /* never = 15 */
1138 };
1139
1140 #define NUM_CONDITIONS (sizeof (condition_table) / sizeof (condition_table[0]))
1141
1142 void
1143 rx_lex_init (char * beginning, char * ending)
1144 {
1145   rx_init_start = beginning;
1146   rx_lex_start = beginning;
1147   rx_lex_end = ending;
1148   rx_in_brackets = 0;
1149   rx_last_token = 0;
1150
1151   setbuf (stdout, 0);
1152 }
1153
1154 static int
1155 check_condition (char * base)
1156 {
1157   char * cp;
1158   unsigned int i;
1159
1160   if ((unsigned) (rx_lex_end - rx_lex_start) < strlen (base) + 1)
1161     return 0;
1162   if (memcmp (rx_lex_start, base, strlen (base)))
1163     return 0;
1164   cp = rx_lex_start + strlen (base);
1165   for (i = 0; i < NUM_CONDITIONS; i ++)
1166     {
1167       if (strcasecmp (cp, condition_table[i].string) == 0)
1168         {
1169           rx_lval.regno = condition_table[i].val;
1170           return 1;
1171         }
1172     }
1173   return 0;
1174 }
1175
1176 static int
1177 rx_lex (void)
1178 {
1179   unsigned int ci;
1180   char * save_input_pointer;
1181
1182   while (ISSPACE (*rx_lex_start)
1183          && rx_lex_start != rx_lex_end)
1184     rx_lex_start ++;
1185
1186   rx_last_exp_start = rx_lex_start;
1187
1188   if (rx_lex_start == rx_lex_end)
1189     return 0;
1190
1191   if (ISALPHA (*rx_lex_start)
1192       || (rx_pid_register != -1 && memcmp (rx_lex_start, "%pidreg", 7) == 0)
1193       || (rx_gp_register != -1 && memcmp (rx_lex_start, "%gpreg", 6) == 0)
1194       || (*rx_lex_start == '.' && ISALPHA (rx_lex_start[1])))
1195     {
1196       unsigned int i;
1197       char * e;
1198       char save;
1199
1200       for (e = rx_lex_start + 1;
1201            e < rx_lex_end && ISALNUM (*e);
1202            e ++)
1203         ;
1204       save = *e;
1205       *e = 0;
1206
1207       if (strcmp (rx_lex_start, "%pidreg") == 0)
1208         {
1209           {
1210             rx_lval.regno = rx_pid_register;
1211             *e = save;
1212             rx_lex_start = e;
1213             rx_last_token = REG;
1214             return REG;
1215           }
1216         }
1217
1218       if (strcmp (rx_lex_start, "%gpreg") == 0)
1219         {
1220           {
1221             rx_lval.regno = rx_gp_register;
1222             *e = save;
1223             rx_lex_start = e;
1224             rx_last_token = REG;
1225             return REG;
1226           }
1227         }
1228
1229       if (rx_last_token == 0)
1230         for (ci = 0; ci < NUM_CONDITION_OPCODES; ci ++)
1231           if (check_condition (condition_opcode_table[ci].string))
1232             {
1233               *e = save;
1234               rx_lex_start = e;
1235               rx_last_token = condition_opcode_table[ci].token;
1236               return condition_opcode_table[ci].token;
1237             }
1238
1239       for (i = 0; i < NUM_TOKENS; i++)
1240         if (strcasecmp (rx_lex_start, token_table[i].string) == 0
1241             && !(token_table[i].val == IS_OPCODE && rx_last_token != 0)
1242             && !(token_table[i].token == FLAG && !need_flag))
1243           {
1244             rx_lval.regno = token_table[i].val;
1245             *e = save;
1246             rx_lex_start = e;
1247             rx_last_token = token_table[i].token;
1248             return token_table[i].token;
1249           }
1250       *e = save;
1251     }
1252
1253   if (rx_last_token == 0)
1254     {
1255       rx_last_token = UNKNOWN_OPCODE;
1256       return UNKNOWN_OPCODE;
1257     }
1258
1259   if (rx_last_token == UNKNOWN_OPCODE)
1260     return 0;
1261
1262   if (*rx_lex_start == '[')
1263     rx_in_brackets = 1;
1264   if (*rx_lex_start == ']')
1265     rx_in_brackets = 0;
1266
1267   if (rx_in_brackets
1268       || rx_last_token == REG
1269       || strchr ("[],#", *rx_lex_start))
1270     {
1271       rx_last_token = *rx_lex_start;
1272       return *rx_lex_start ++;
1273     }
1274
1275   save_input_pointer = input_line_pointer;
1276   input_line_pointer = rx_lex_start;
1277   rx_lval.exp.X_md = 0;
1278   expression (&rx_lval.exp);
1279
1280   /* We parse but ignore any :<size> modifier on expressions.  */
1281   if (*input_line_pointer == ':')
1282     {
1283       char *cp;
1284
1285       for (cp  = input_line_pointer + 1; *cp && cp < rx_lex_end; cp++)
1286         if (!ISDIGIT (*cp))
1287           break;
1288       if (cp > input_line_pointer+1)
1289         input_line_pointer = cp;
1290     }
1291
1292   rx_lex_start = input_line_pointer;
1293   input_line_pointer = save_input_pointer;
1294   rx_last_token = EXPR;
1295   return EXPR;
1296 }
1297
1298 int
1299 rx_error (const char * str)
1300 {
1301   int len;
1302
1303   len = rx_last_exp_start - rx_init_start;
1304
1305   as_bad ("%s", rx_init_start);
1306   as_bad ("%*s^ %s", len, "", str);
1307   return 0;
1308 }
1309
1310 static int
1311 rx_intop (expressionS exp, int nbits, int opbits)
1312 {
1313   long v;
1314   long mask, msb;
1315
1316   if (exp.X_op == O_big && nbits == 32)
1317       return 1;
1318   if (exp.X_op != O_constant)
1319     return 0;
1320   v = exp.X_add_number;
1321
1322   msb = 1UL << (opbits - 1);
1323   mask = (1UL << opbits) - 1;
1324
1325   if ((v & msb) && ! (v & ~mask))
1326     v -= 1UL << opbits;
1327
1328   switch (nbits)
1329     {
1330     case 4:
1331       return -0x8 <= v && v <= 0x7;
1332     case 5:
1333       return -0x10 <= v && v <= 0x17;
1334     case 8:
1335       return -0x80 <= v && v <= 0x7f;
1336     case 16:
1337       return -0x8000 <= v && v <= 0x7fff;
1338     case 24:
1339       return -0x800000 <= v && v <= 0x7fffff;
1340     case 32:
1341       return 1;
1342     default:
1343       printf ("rx_intop passed %d\n", nbits);
1344       abort ();
1345     }
1346   return 1;
1347 }
1348
1349 static int
1350 rx_uintop (expressionS exp, int nbits)
1351 {
1352   unsigned long v;
1353
1354   if (exp.X_op != O_constant)
1355     return 0;
1356   v = exp.X_add_number;
1357
1358   switch (nbits)
1359     {
1360     case 4:
1361       return v <= 0xf;
1362     case 8:
1363       return v <= 0xff;
1364     case 16:
1365       return v <= 0xffff;
1366     case 24:
1367       return v <= 0xffffff;
1368     default:
1369       printf ("rx_uintop passed %d\n", nbits);
1370       abort ();
1371     }
1372   return 1;
1373 }
1374
1375 static int
1376 rx_disp3op (expressionS exp)
1377 {
1378   unsigned long v;
1379
1380   if (exp.X_op != O_constant)
1381     return 0;
1382   v = exp.X_add_number;
1383   if (v < 3 || v > 10)
1384     return 0;
1385   return 1;
1386 }
1387
1388 static int
1389 rx_disp5op (expressionS * exp, int msize)
1390 {
1391   long v;
1392
1393   if (exp->X_op != O_constant)
1394     return 0;
1395   v = exp->X_add_number;
1396
1397   switch (msize)
1398     {
1399     case BSIZE:
1400       if (0 < v && v <= 31)
1401         return 1;
1402       break;
1403     case WSIZE:
1404       if (v & 1)
1405         return 0;
1406       if (0 < v && v <= 63)
1407         {
1408           exp->X_add_number >>= 1;
1409           return 1;
1410         }
1411       break;
1412     case LSIZE:
1413       if (v & 3)
1414         return 0;
1415       if (0 < v && v <= 127)
1416         {
1417           exp->X_add_number >>= 2;
1418           return 1;
1419         }
1420       break;
1421     }
1422   return 0;
1423 }
1424
1425 /* Just like the above, but allows a zero displacement.  */
1426
1427 static int
1428 rx_disp5op0 (expressionS * exp, int msize)
1429 {
1430   if (exp->X_op != O_constant)
1431     return 0;
1432   if (exp->X_add_number == 0)
1433     return 1;
1434   return rx_disp5op (exp, msize);
1435 }
1436
1437 static int
1438 exp_val (expressionS exp)
1439 {
1440   if (exp.X_op != O_constant)
1441   {
1442     rx_error (_("constant expected"));
1443     return 0;
1444   }
1445   return exp.X_add_number;
1446 }
1447
1448 static expressionS
1449 zero_expr (void)
1450 {
1451   /* Static, so program load sets it to all zeros, which is what we want.  */
1452   static expressionS zero;
1453   zero.X_op = O_constant;
1454   return zero;
1455 }
1456
1457 static int
1458 immediate (expressionS exp, int type, int pos, int bits)
1459 {
1460   /* We will emit constants ourself here, so negate them.  */
1461   if (type == RXREL_NEGATIVE && exp.X_op == O_constant)
1462     exp.X_add_number = - exp.X_add_number;
1463   if (type == RXREL_NEGATIVE_BORROW)
1464     {
1465       if (exp.X_op == O_constant)
1466         exp.X_add_number = - exp.X_add_number - 1;
1467       else
1468         rx_error (_("sbb cannot use symbolic immediates"));
1469     }
1470
1471   if (rx_intop (exp, 8, bits))
1472     {
1473       rx_op (exp, 1, type);
1474       return 1;
1475     }
1476   else if (rx_intop (exp, 16, bits))
1477     {
1478       rx_op (exp, 2, type);
1479       return 2;
1480     }
1481   else if (rx_uintop (exp, 16) && bits == 16)
1482     {
1483       rx_op (exp, 2, type);
1484       return 2;
1485     }
1486   else if (rx_intop (exp, 24, bits))
1487     {
1488       rx_op (exp, 3, type);
1489       return 3;
1490     }
1491   else if (rx_intop (exp, 32, bits))
1492     {
1493       rx_op (exp, 4, type);
1494       return 0;
1495     }
1496   else if (type == RXREL_SIGNED)
1497     {
1498       /* This is a symbolic immediate, we will relax it later.  */
1499       rx_relax (RX_RELAX_IMM, pos);
1500       rx_op (exp, linkrelax ? 4 : 1, type);
1501       return 1;
1502     }
1503   else
1504     {
1505       /* Let the linker deal with it.  */
1506       rx_op (exp, 4, type);
1507       return 0;
1508     }
1509 }
1510
1511 static int
1512 displacement (expressionS exp, int msize)
1513 {
1514   int val;
1515   int vshift = 0;
1516
1517   if (exp.X_op == O_symbol
1518       && exp.X_md)
1519     {
1520       switch (exp.X_md)
1521         {
1522         case BFD_RELOC_GPREL16:
1523           switch (msize)
1524             {
1525             case BSIZE:
1526               exp.X_md = BFD_RELOC_RX_GPRELB;
1527               break;
1528             case WSIZE:
1529               exp.X_md = BFD_RELOC_RX_GPRELW;
1530               break;
1531             case LSIZE:
1532               exp.X_md = BFD_RELOC_RX_GPRELL;
1533               break;
1534             }
1535           O2 (exp);
1536           return 2;
1537         }
1538     }
1539
1540   if (exp.X_op == O_subtract)
1541     {
1542       exp.X_md = BFD_RELOC_RX_DIFF;
1543       O2 (exp);
1544       return 2;
1545     }
1546
1547   if (exp.X_op != O_constant)
1548     {
1549       rx_error (_("displacements must be constants"));
1550       return -1;
1551     }
1552   val = exp.X_add_number;
1553
1554   if (val == 0)
1555     return 0;
1556
1557   switch (msize)
1558     {
1559     case BSIZE:
1560       break;
1561     case WSIZE:
1562       if (val & 1)
1563         rx_error (_("word displacement not word-aligned"));
1564       vshift = 1;
1565       break;
1566     case LSIZE:
1567       if (val & 3)
1568         rx_error (_("long displacement not long-aligned"));
1569       vshift = 2;
1570       break;
1571     default:
1572       as_bad (_("displacement with unknown size (internal bug?)\n"));
1573       break;
1574     }
1575
1576   val >>= vshift;
1577   exp.X_add_number = val;
1578
1579   if (0 <= val && val <= 255 )
1580     {
1581       O1 (exp);
1582       return 1;
1583     }
1584
1585   if (0 <= val && val <= 65535)
1586     {
1587       O2 (exp);
1588       return 2;
1589     }
1590   if (val < 0)
1591     rx_error (_("negative displacements not allowed"));
1592   else
1593     rx_error (_("displacement too large"));
1594   return -1;
1595 }
1596
1597 static void
1598 rtsd_immediate (expressionS exp)
1599 {
1600   int val;
1601
1602   if (exp.X_op != O_constant)
1603     {
1604       rx_error (_("rtsd size must be constant"));
1605       return;
1606     }
1607   val = exp.X_add_number;
1608   if (val & 3)
1609     rx_error (_("rtsd size must be multiple of 4"));
1610
1611   if (val < 0 || val > 1020)
1612     rx_error (_("rtsd size must be 0..1020"));
1613
1614   val >>= 2;
1615   exp.X_add_number = val;
1616   O1 (exp);
1617 }
1618
1619 static void
1620 rx_range (expressionS exp, int minv, int maxv)
1621 {
1622   int val;
1623
1624   if (exp.X_op != O_constant)
1625     return;
1626
1627   val = exp.X_add_number;
1628   if (val < minv || val > maxv)
1629     as_warn (_("Value %d out of range %d..%d"), val, minv, maxv);
1630 }
1631
1632 static void
1633 rx_check_float_support (void)
1634 {
1635   if (rx_cpu == RX100 || rx_cpu == RX200)
1636     rx_error (_("target CPU type does not support floating point instructions"));
1637 }