1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
91 /* Bits for DEFINED field in vector_type_el. */
93 #define NTA_HASINDEX 2
94 #define NTA_HASVARWIDTH 4
98 enum vector_el_type type
;
99 unsigned char defined
;
104 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
108 bfd_reloc_code_real_type type
;
111 enum aarch64_opnd opnd
;
113 unsigned need_libopcodes_p
: 1;
116 struct aarch64_instruction
118 /* libopcodes structure for instruction intermediate representation. */
120 /* Record assembly errors found during the parsing. */
123 enum aarch64_operand_error_kind kind
;
126 /* The condition that appears in the assembly line. */
128 /* Relocation information (including the GAS internal fixup). */
130 /* Need to generate an immediate in the literal pool. */
131 unsigned gen_lit_pool
: 1;
134 typedef struct aarch64_instruction aarch64_instruction
;
136 static aarch64_instruction inst
;
138 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
139 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
141 /* Diagnostics inline function utilites.
143 These are lightweight utlities which should only be called by parse_operands
144 and other parsers. GAS processes each assembly line by parsing it against
145 instruction template(s), in the case of multiple templates (for the same
146 mnemonic name), those templates are tried one by one until one succeeds or
147 all fail. An assembly line may fail a few templates before being
148 successfully parsed; an error saved here in most cases is not a user error
149 but an error indicating the current template is not the right template.
150 Therefore it is very important that errors can be saved at a low cost during
151 the parsing; we don't want to slow down the whole parsing by recording
152 non-user errors in detail.
154 Remember that the objective is to help GAS pick up the most approapriate
155 error message in the case of multiple templates, e.g. FMOV which has 8
161 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
162 inst
.parsing_error
.error
= NULL
;
165 static inline bfd_boolean
168 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
171 static inline const char *
172 get_error_message (void)
174 return inst
.parsing_error
.error
;
177 static inline enum aarch64_operand_error_kind
178 get_error_kind (void)
180 return inst
.parsing_error
.kind
;
184 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
186 inst
.parsing_error
.kind
= kind
;
187 inst
.parsing_error
.error
= error
;
191 set_recoverable_error (const char *error
)
193 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
196 /* Use the DESC field of the corresponding aarch64_operand entry to compose
197 the error message. */
199 set_default_error (void)
201 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
205 set_syntax_error (const char *error
)
207 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
211 set_first_syntax_error (const char *error
)
214 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
218 set_fatal_syntax_error (const char *error
)
220 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
223 /* Number of littlenums required to hold an extended precision number. */
224 #define MAX_LITTLENUMS 6
226 /* Return value for certain parsers when the parsing fails; those parsers
227 return the information of the parsed result, e.g. register number, on
229 #define PARSE_FAIL -1
231 /* This is an invalid condition code that means no conditional field is
233 #define COND_ALWAYS 0x10
237 const char *template;
243 const char *template;
250 bfd_reloc_code_real_type reloc
;
253 /* Macros to define the register types and masks for the purpose
256 #undef AARCH64_REG_TYPES
257 #define AARCH64_REG_TYPES \
258 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
259 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
260 BASIC_REG_TYPE(SP_32) /* wsp */ \
261 BASIC_REG_TYPE(SP_64) /* sp */ \
262 BASIC_REG_TYPE(Z_32) /* wzr */ \
263 BASIC_REG_TYPE(Z_64) /* xzr */ \
264 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
265 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
266 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
267 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
268 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
269 BASIC_REG_TYPE(CN) /* c[0-7] */ \
270 BASIC_REG_TYPE(VN) /* v[0-31] */ \
271 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
272 BASIC_REG_TYPE(PN) /* p[0-15] */ \
273 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
274 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
275 /* Typecheck: same, plus SVE registers. */ \
276 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
278 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
279 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
280 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
281 /* Typecheck: same, plus SVE registers. */ \
282 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
283 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
285 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
286 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
287 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
288 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
289 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
292 /* Typecheck: any [BHSDQ]P FP. */ \
293 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
294 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
295 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
296 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
298 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
299 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
300 /* Any integer register; used for error messages only. */ \
301 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
302 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
303 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
304 /* Pseudo type to mark the end of the enumerator sequence. */ \
307 #undef BASIC_REG_TYPE
308 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
309 #undef MULTI_REG_TYPE
310 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
312 /* Register type enumerators. */
313 typedef enum aarch64_reg_type_
315 /* A list of REG_TYPE_*. */
319 #undef BASIC_REG_TYPE
320 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
322 #define REG_TYPE(T) (1 << REG_TYPE_##T)
323 #undef MULTI_REG_TYPE
324 #define MULTI_REG_TYPE(T,V) V,
326 /* Structure for a hash table entry for a register. */
330 unsigned char number
;
331 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
332 unsigned char builtin
;
335 /* Values indexed by aarch64_reg_type to assist the type checking. */
336 static const unsigned reg_type_masks
[] =
341 #undef BASIC_REG_TYPE
343 #undef MULTI_REG_TYPE
344 #undef AARCH64_REG_TYPES
346 /* Diagnostics used when we don't get a register of the expected type.
347 Note: this has to synchronized with aarch64_reg_type definitions
350 get_reg_expected_msg (aarch64_reg_type reg_type
)
357 msg
= N_("integer 32-bit register expected");
360 msg
= N_("integer 64-bit register expected");
363 msg
= N_("integer register expected");
365 case REG_TYPE_R64_SP
:
366 msg
= N_("64-bit integer or SP register expected");
368 case REG_TYPE_SVE_BASE
:
369 msg
= N_("base register expected");
372 msg
= N_("integer or zero register expected");
374 case REG_TYPE_SVE_OFFSET
:
375 msg
= N_("offset register expected");
378 msg
= N_("integer or SP register expected");
380 case REG_TYPE_R_Z_SP
:
381 msg
= N_("integer, zero or SP register expected");
384 msg
= N_("8-bit SIMD scalar register expected");
387 msg
= N_("16-bit SIMD scalar or floating-point half precision "
388 "register expected");
391 msg
= N_("32-bit SIMD scalar or floating-point single precision "
392 "register expected");
395 msg
= N_("64-bit SIMD scalar or floating-point double precision "
396 "register expected");
399 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
400 "register expected");
403 msg
= N_("C0 - C15 expected");
405 case REG_TYPE_R_Z_BHSDQ_V
:
406 msg
= N_("register expected");
408 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
409 msg
= N_("SIMD scalar or floating-point register expected");
411 case REG_TYPE_VN
: /* any V reg */
412 msg
= N_("vector register expected");
415 msg
= N_("SVE vector register expected");
418 msg
= N_("SVE predicate register expected");
421 as_fatal (_("invalid register type %d"), reg_type
);
426 /* Some well known registers that we refer to directly elsewhere. */
429 /* Instructions take 4 bytes in the object file. */
432 static struct hash_control
*aarch64_ops_hsh
;
433 static struct hash_control
*aarch64_cond_hsh
;
434 static struct hash_control
*aarch64_shift_hsh
;
435 static struct hash_control
*aarch64_sys_regs_hsh
;
436 static struct hash_control
*aarch64_pstatefield_hsh
;
437 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
438 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
439 static struct hash_control
*aarch64_sys_regs_at_hsh
;
440 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
441 static struct hash_control
*aarch64_reg_hsh
;
442 static struct hash_control
*aarch64_barrier_opt_hsh
;
443 static struct hash_control
*aarch64_nzcv_hsh
;
444 static struct hash_control
*aarch64_pldop_hsh
;
445 static struct hash_control
*aarch64_hint_opt_hsh
;
447 /* Stuff needed to resolve the label ambiguity
456 static symbolS
*last_label_seen
;
458 /* Literal pool structure. Held on a per-section
459 and per-sub-section basis. */
461 #define MAX_LITERAL_POOL_SIZE 1024
462 typedef struct literal_expression
465 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
466 LITTLENUM_TYPE
* bignum
;
467 } literal_expression
;
469 typedef struct literal_pool
471 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
472 unsigned int next_free_entry
;
478 struct literal_pool
*next
;
481 /* Pointer to a linked list of literal pools. */
482 static literal_pool
*list_of_pools
= NULL
;
486 /* This array holds the chars that always start a comment. If the
487 pre-processor is disabled, these aren't very useful. */
488 const char comment_chars
[] = "";
490 /* This array holds the chars that only start a comment at the beginning of
491 a line. If the line seems to have the form '# 123 filename'
492 .line and .file directives will appear in the pre-processed output. */
493 /* Note that input_file.c hand checks for '#' at the beginning of the
494 first line of the input file. This is because the compiler outputs
495 #NO_APP at the beginning of its output. */
496 /* Also note that comments like this one will always work. */
497 const char line_comment_chars
[] = "#";
499 const char line_separator_chars
[] = ";";
501 /* Chars that can be used to separate mant
502 from exp in floating point numbers. */
503 const char EXP_CHARS
[] = "eE";
505 /* Chars that mean this number is a floating point constant. */
509 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
511 /* Prefix character that indicates the start of an immediate value. */
512 #define is_immediate_prefix(C) ((C) == '#')
514 /* Separator character handling. */
516 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
518 static inline bfd_boolean
519 skip_past_char (char **str
, char c
)
530 #define skip_past_comma(str) skip_past_char (str, ',')
532 /* Arithmetic expressions (possibly involving symbols). */
534 static bfd_boolean in_my_get_expression_p
= FALSE
;
536 /* Third argument to my_get_expression. */
537 #define GE_NO_PREFIX 0
538 #define GE_OPT_PREFIX 1
540 /* Return TRUE if the string pointed by *STR is successfully parsed
541 as an valid expression; *EP will be filled with the information of
542 such an expression. Otherwise return FALSE. */
545 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
550 int prefix_present_p
= 0;
557 if (is_immediate_prefix (**str
))
560 prefix_present_p
= 1;
567 memset (ep
, 0, sizeof (expressionS
));
569 save_in
= input_line_pointer
;
570 input_line_pointer
= *str
;
571 in_my_get_expression_p
= TRUE
;
572 seg
= expression (ep
);
573 in_my_get_expression_p
= FALSE
;
575 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
577 /* We found a bad expression in md_operand(). */
578 *str
= input_line_pointer
;
579 input_line_pointer
= save_in
;
580 if (prefix_present_p
&& ! error_p ())
581 set_fatal_syntax_error (_("bad expression"));
583 set_first_syntax_error (_("bad expression"));
588 if (seg
!= absolute_section
589 && seg
!= text_section
590 && seg
!= data_section
591 && seg
!= bss_section
&& seg
!= undefined_section
)
593 set_syntax_error (_("bad segment"));
594 *str
= input_line_pointer
;
595 input_line_pointer
= save_in
;
602 *str
= input_line_pointer
;
603 input_line_pointer
= save_in
;
607 /* Turn a string in input_line_pointer into a floating point constant
608 of type TYPE, and store the appropriate bytes in *LITP. The number
609 of LITTLENUMS emitted is stored in *SIZEP. An error message is
610 returned, or NULL on OK. */
613 md_atof (int type
, char *litP
, int *sizeP
)
615 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
618 /* We handle all bad expressions here, so that we can report the faulty
619 instruction in the error message. */
621 md_operand (expressionS
* exp
)
623 if (in_my_get_expression_p
)
624 exp
->X_op
= O_illegal
;
627 /* Immediate values. */
629 /* Errors may be set multiple times during parsing or bit encoding
630 (particularly in the Neon bits), but usually the earliest error which is set
631 will be the most meaningful. Avoid overwriting it with later (cascading)
632 errors by calling this function. */
635 first_error (const char *error
)
638 set_syntax_error (error
);
641 /* Similiar to first_error, but this function accepts formatted error
644 first_error_fmt (const char *format
, ...)
649 /* N.B. this single buffer will not cause error messages for different
650 instructions to pollute each other; this is because at the end of
651 processing of each assembly line, error message if any will be
652 collected by as_bad. */
653 static char buffer
[size
];
657 int ret ATTRIBUTE_UNUSED
;
658 va_start (args
, format
);
659 ret
= vsnprintf (buffer
, size
, format
, args
);
660 know (ret
<= size
- 1 && ret
>= 0);
662 set_syntax_error (buffer
);
666 /* Register parsing. */
668 /* Generic register parser which is called by other specialized
670 CCP points to what should be the beginning of a register name.
671 If it is indeed a valid register name, advance CCP over it and
672 return the reg_entry structure; otherwise return NULL.
673 It does not issue diagnostics. */
676 parse_reg (char **ccp
)
682 #ifdef REGISTER_PREFIX
683 if (*start
!= REGISTER_PREFIX
)
689 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
694 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
696 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
705 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
708 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
710 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
713 /* Try to parse a base or offset register. Allow SVE base and offset
714 registers if REG_TYPE includes SVE registers. Return the register
715 entry on success, setting *QUALIFIER to the register qualifier.
716 Return null otherwise.
718 Note that this function does not issue any diagnostics. */
720 static const reg_entry
*
721 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
722 aarch64_opnd_qualifier_t
*qualifier
)
725 const reg_entry
*reg
= parse_reg (&str
);
735 *qualifier
= AARCH64_OPND_QLF_W
;
741 *qualifier
= AARCH64_OPND_QLF_X
;
745 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
748 switch (TOLOWER (str
[1]))
751 *qualifier
= AARCH64_OPND_QLF_S_S
;
754 *qualifier
= AARCH64_OPND_QLF_S_D
;
771 /* Try to parse a base or offset register. Return the register entry
772 on success, setting *QUALIFIER to the register qualifier. Return null
775 Note that this function does not issue any diagnostics. */
777 static const reg_entry
*
778 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
780 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
783 /* Parse the qualifier of a vector register or vector element of type
784 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
785 succeeds; otherwise return FALSE.
787 Accept only one occurrence of:
788 8b 16b 2h 4h 8h 2s 4s 1d 2d
791 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
792 struct vector_type_el
*parsed_type
, char **str
)
796 unsigned element_size
;
797 enum vector_el_type type
;
800 gas_assert (*ptr
== '.');
803 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
808 width
= strtoul (ptr
, &ptr
, 10);
809 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
811 first_error_fmt (_("bad size %d in vector width specifier"), width
);
816 switch (TOLOWER (*ptr
))
844 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
846 first_error (_("missing element size"));
849 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
850 && !(width
== 2 && element_size
== 16))
853 ("invalid element size %d and vector size combination %c"),
859 parsed_type
->type
= type
;
860 parsed_type
->width
= width
;
867 /* *STR contains an SVE zero/merge predication suffix. Parse it into
868 *PARSED_TYPE and point *STR at the end of the suffix. */
871 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
876 gas_assert (*ptr
== '/');
878 switch (TOLOWER (*ptr
))
881 parsed_type
->type
= NT_zero
;
884 parsed_type
->type
= NT_merge
;
887 if (*ptr
!= '\0' && *ptr
!= ',')
888 first_error_fmt (_("unexpected character `%c' in predication type"),
891 first_error (_("missing predication type"));
894 parsed_type
->width
= 0;
899 /* Parse a register of the type TYPE.
901 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
902 name or the parsed register is not of TYPE.
904 Otherwise return the register number, and optionally fill in the actual
905 type of the register in *RTYPE when multiple alternatives were given, and
906 return the register shape and element index information in *TYPEINFO.
908 IN_REG_LIST should be set with TRUE if the caller is parsing a register
912 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
913 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
916 const reg_entry
*reg
= parse_reg (&str
);
917 struct vector_type_el atype
;
918 struct vector_type_el parsetype
;
919 bfd_boolean is_typed_vecreg
= FALSE
;
922 atype
.type
= NT_invtype
;
930 set_default_error ();
934 if (! aarch64_check_reg_type (reg
, type
))
936 DEBUG_TRACE ("reg type check failed");
937 set_default_error ();
942 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
943 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
947 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
952 if (!parse_predication_for_operand (&parsetype
, &str
))
956 /* Register if of the form Vn.[bhsdq]. */
957 is_typed_vecreg
= TRUE
;
959 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
961 /* The width is always variable; we don't allow an integer width
963 gas_assert (parsetype
.width
== 0);
964 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
966 else if (parsetype
.width
== 0)
967 /* Expect index. In the new scheme we cannot have
968 Vn.[bhsdq] represent a scalar. Therefore any
969 Vn.[bhsdq] should have an index following it.
970 Except in reglists ofcourse. */
971 atype
.defined
|= NTA_HASINDEX
;
973 atype
.defined
|= NTA_HASTYPE
;
975 atype
.type
= parsetype
.type
;
976 atype
.width
= parsetype
.width
;
979 if (skip_past_char (&str
, '['))
983 /* Reject Sn[index] syntax. */
984 if (!is_typed_vecreg
)
986 first_error (_("this type of register can't be indexed"));
990 if (in_reg_list
== TRUE
)
992 first_error (_("index not allowed inside register list"));
996 atype
.defined
|= NTA_HASINDEX
;
998 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1000 if (exp
.X_op
!= O_constant
)
1002 first_error (_("constant expression required"));
1006 if (! skip_past_char (&str
, ']'))
1009 atype
.index
= exp
.X_add_number
;
1011 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1013 /* Indexed vector register expected. */
1014 first_error (_("indexed vector register expected"));
1018 /* A vector reg Vn should be typed or indexed. */
1019 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1021 first_error (_("invalid use of vector register"));
1037 Return the register number on success; return PARSE_FAIL otherwise.
1039 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1040 the register (e.g. NEON double or quad reg when either has been requested).
1042 If this is a NEON vector register with additional type information, fill
1043 in the struct pointed to by VECTYPE (if non-NULL).
1045 This parser does not handle register list. */
1048 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1049 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1051 struct vector_type_el atype
;
1053 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1054 /*in_reg_list= */ FALSE
);
1056 if (reg
== PARSE_FAIL
)
1067 static inline bfd_boolean
1068 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1072 && e1
.defined
== e2
.defined
1073 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1076 /* This function parses a list of vector registers of type TYPE.
1077 On success, it returns the parsed register list information in the
1078 following encoded format:
1080 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1081 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1083 The information of the register shape and/or index is returned in
1086 It returns PARSE_FAIL if the register list is invalid.
1088 The list contains one to four registers.
1089 Each register can be one of:
1092 All <T> should be identical.
1093 All <index> should be identical.
1094 There are restrictions on <Vt> numbers which are checked later
1095 (by reg_list_valid_p). */
1098 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1099 struct vector_type_el
*vectype
)
1103 struct vector_type_el typeinfo
, typeinfo_first
;
1108 bfd_boolean error
= FALSE
;
1109 bfd_boolean expect_index
= FALSE
;
1113 set_syntax_error (_("expecting {"));
1119 typeinfo_first
.defined
= 0;
1120 typeinfo_first
.type
= NT_invtype
;
1121 typeinfo_first
.width
= -1;
1122 typeinfo_first
.index
= 0;
1131 str
++; /* skip over '-' */
1134 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1135 /*in_reg_list= */ TRUE
);
1136 if (val
== PARSE_FAIL
)
1138 set_first_syntax_error (_("invalid vector register in list"));
1142 /* reject [bhsd]n */
1143 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1145 set_first_syntax_error (_("invalid scalar register in list"));
1150 if (typeinfo
.defined
& NTA_HASINDEX
)
1151 expect_index
= TRUE
;
1155 if (val
< val_range
)
1157 set_first_syntax_error
1158 (_("invalid range in vector register list"));
1167 typeinfo_first
= typeinfo
;
1168 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1170 set_first_syntax_error
1171 (_("type mismatch in vector register list"));
1176 for (i
= val_range
; i
<= val
; i
++)
1178 ret_val
|= i
<< (5 * nb_regs
);
1183 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1185 skip_whitespace (str
);
1188 set_first_syntax_error (_("end of vector register list not found"));
1193 skip_whitespace (str
);
1197 if (skip_past_char (&str
, '['))
1201 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1202 if (exp
.X_op
!= O_constant
)
1204 set_first_syntax_error (_("constant expression required."));
1207 if (! skip_past_char (&str
, ']'))
1210 typeinfo_first
.index
= exp
.X_add_number
;
1214 set_first_syntax_error (_("expected index"));
1221 set_first_syntax_error (_("too many registers in vector register list"));
1224 else if (nb_regs
== 0)
1226 set_first_syntax_error (_("empty vector register list"));
1232 *vectype
= typeinfo_first
;
1234 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1237 /* Directives: register aliases. */
1240 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1245 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1248 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1251 /* Only warn about a redefinition if it's not defined as the
1253 else if (new->number
!= number
|| new->type
!= type
)
1254 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1259 name
= xstrdup (str
);
1260 new = XNEW (reg_entry
);
1263 new->number
= number
;
1265 new->builtin
= FALSE
;
1267 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1273 /* Look for the .req directive. This is of the form:
1275 new_register_name .req existing_register_name
1277 If we find one, or if it looks sufficiently like one that we want to
1278 handle any error here, return TRUE. Otherwise return FALSE. */
1281 create_register_alias (char *newname
, char *p
)
1283 const reg_entry
*old
;
1284 char *oldname
, *nbuf
;
1287 /* The input scrubber ensures that whitespace after the mnemonic is
1288 collapsed to single spaces. */
1290 if (strncmp (oldname
, " .req ", 6) != 0)
1294 if (*oldname
== '\0')
1297 old
= hash_find (aarch64_reg_hsh
, oldname
);
1300 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1304 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1305 the desired alias name, and p points to its end. If not, then
1306 the desired alias name is in the global original_case_string. */
1307 #ifdef TC_CASE_SENSITIVE
1310 newname
= original_case_string
;
1311 nlen
= strlen (newname
);
1314 nbuf
= xmemdup0 (newname
, nlen
);
1316 /* Create aliases under the new name as stated; an all-lowercase
1317 version of the new name; and an all-uppercase version of the new
1319 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1321 for (p
= nbuf
; *p
; p
++)
1324 if (strncmp (nbuf
, newname
, nlen
))
1326 /* If this attempt to create an additional alias fails, do not bother
1327 trying to create the all-lower case alias. We will fail and issue
1328 a second, duplicate error message. This situation arises when the
1329 programmer does something like:
1332 The second .req creates the "Foo" alias but then fails to create
1333 the artificial FOO alias because it has already been created by the
1335 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1342 for (p
= nbuf
; *p
; p
++)
1345 if (strncmp (nbuf
, newname
, nlen
))
1346 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1353 /* Should never be called, as .req goes between the alias and the
1354 register name, not at the beginning of the line. */
1356 s_req (int a ATTRIBUTE_UNUSED
)
1358 as_bad (_("invalid syntax for .req directive"));
1361 /* The .unreq directive deletes an alias which was previously defined
1362 by .req. For example:
1368 s_unreq (int a ATTRIBUTE_UNUSED
)
1373 name
= input_line_pointer
;
1375 while (*input_line_pointer
!= 0
1376 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1377 ++input_line_pointer
;
1379 saved_char
= *input_line_pointer
;
1380 *input_line_pointer
= 0;
1383 as_bad (_("invalid syntax for .unreq directive"));
1386 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1389 as_bad (_("unknown register alias '%s'"), name
);
1390 else if (reg
->builtin
)
1391 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1398 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1399 free ((char *) reg
->name
);
1402 /* Also locate the all upper case and all lower case versions.
1403 Do not complain if we cannot find one or the other as it
1404 was probably deleted above. */
1406 nbuf
= strdup (name
);
1407 for (p
= nbuf
; *p
; p
++)
1409 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1412 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1413 free ((char *) reg
->name
);
1417 for (p
= nbuf
; *p
; p
++)
1419 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1422 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1423 free ((char *) reg
->name
);
1431 *input_line_pointer
= saved_char
;
1432 demand_empty_rest_of_line ();
1435 /* Directives: Instruction set selection. */
1438 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1439 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1440 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1441 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1443 /* Create a new mapping symbol for the transition to STATE. */
1446 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1449 const char *symname
;
1456 type
= BSF_NO_FLAGS
;
1460 type
= BSF_NO_FLAGS
;
1466 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1467 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1469 /* Save the mapping symbols for future reference. Also check that
1470 we do not place two mapping symbols at the same offset within a
1471 frag. We'll handle overlap between frags in
1472 check_mapping_symbols.
1474 If .fill or other data filling directive generates zero sized data,
1475 the mapping symbol for the following code will have the same value
1476 as the one generated for the data filling directive. In this case,
1477 we replace the old symbol with the new one at the same address. */
1480 if (frag
->tc_frag_data
.first_map
!= NULL
)
1482 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1483 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1486 frag
->tc_frag_data
.first_map
= symbolP
;
1488 if (frag
->tc_frag_data
.last_map
!= NULL
)
1490 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1491 S_GET_VALUE (symbolP
));
1492 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1493 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1496 frag
->tc_frag_data
.last_map
= symbolP
;
1499 /* We must sometimes convert a region marked as code to data during
1500 code alignment, if an odd number of bytes have to be padded. The
1501 code mapping symbol is pushed to an aligned address. */
1504 insert_data_mapping_symbol (enum mstate state
,
1505 valueT value
, fragS
* frag
, offsetT bytes
)
1507 /* If there was already a mapping symbol, remove it. */
1508 if (frag
->tc_frag_data
.last_map
!= NULL
1509 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1510 frag
->fr_address
+ value
)
1512 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1516 know (frag
->tc_frag_data
.first_map
== symp
);
1517 frag
->tc_frag_data
.first_map
= NULL
;
1519 frag
->tc_frag_data
.last_map
= NULL
;
1520 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1523 make_mapping_symbol (MAP_DATA
, value
, frag
);
1524 make_mapping_symbol (state
, value
+ bytes
, frag
);
1527 static void mapping_state_2 (enum mstate state
, int max_chars
);
1529 /* Set the mapping state to STATE. Only call this when about to
1530 emit some STATE bytes to the file. */
1533 mapping_state (enum mstate state
)
1535 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1537 if (state
== MAP_INSN
)
1538 /* AArch64 instructions require 4-byte alignment. When emitting
1539 instructions into any section, record the appropriate section
1541 record_alignment (now_seg
, 2);
1543 if (mapstate
== state
)
1544 /* The mapping symbol has already been emitted.
1545 There is nothing else to do. */
1548 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1549 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1550 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1551 evaluated later in the next else. */
1553 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1555 /* Only add the symbol if the offset is > 0:
1556 if we're at the first frag, check it's size > 0;
1557 if we're not at the first frag, then for sure
1558 the offset is > 0. */
1559 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1560 const int add_symbol
= (frag_now
!= frag_first
)
1561 || (frag_now_fix () > 0);
1564 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1568 mapping_state_2 (state
, 0);
1571 /* Same as mapping_state, but MAX_CHARS bytes have already been
1572 allocated. Put the mapping symbol that far back. */
1575 mapping_state_2 (enum mstate state
, int max_chars
)
1577 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1579 if (!SEG_NORMAL (now_seg
))
1582 if (mapstate
== state
)
1583 /* The mapping symbol has already been emitted.
1584 There is nothing else to do. */
1587 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1588 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1591 #define mapping_state(x) /* nothing */
1592 #define mapping_state_2(x, y) /* nothing */
1595 /* Directives: sectioning and alignment. */
1598 s_bss (int ignore ATTRIBUTE_UNUSED
)
1600 /* We don't support putting frags in the BSS segment, we fake it by
1601 marking in_bss, then looking at s_skip for clues. */
1602 subseg_set (bss_section
, 0);
1603 demand_empty_rest_of_line ();
1604 mapping_state (MAP_DATA
);
1608 s_even (int ignore ATTRIBUTE_UNUSED
)
1610 /* Never make frag if expect extra pass. */
1612 frag_align (1, 0, 0);
1614 record_alignment (now_seg
, 1);
1616 demand_empty_rest_of_line ();
1619 /* Directives: Literal pools. */
1621 static literal_pool
*
1622 find_literal_pool (int size
)
1626 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1628 if (pool
->section
== now_seg
1629 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1636 static literal_pool
*
1637 find_or_make_literal_pool (int size
)
1639 /* Next literal pool ID number. */
1640 static unsigned int latest_pool_num
= 1;
1643 pool
= find_literal_pool (size
);
1647 /* Create a new pool. */
1648 pool
= XNEW (literal_pool
);
1652 /* Currently we always put the literal pool in the current text
1653 section. If we were generating "small" model code where we
1654 knew that all code and initialised data was within 1MB then
1655 we could output literals to mergeable, read-only data
1658 pool
->next_free_entry
= 0;
1659 pool
->section
= now_seg
;
1660 pool
->sub_section
= now_subseg
;
1662 pool
->next
= list_of_pools
;
1663 pool
->symbol
= NULL
;
1665 /* Add it to the list. */
1666 list_of_pools
= pool
;
1669 /* New pools, and emptied pools, will have a NULL symbol. */
1670 if (pool
->symbol
== NULL
)
1672 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1673 (valueT
) 0, &zero_address_frag
);
1674 pool
->id
= latest_pool_num
++;
1681 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1682 Return TRUE on success, otherwise return FALSE. */
1684 add_to_lit_pool (expressionS
*exp
, int size
)
1689 pool
= find_or_make_literal_pool (size
);
1691 /* Check if this literal value is already in the pool. */
1692 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1694 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1696 if ((litexp
->X_op
== exp
->X_op
)
1697 && (exp
->X_op
== O_constant
)
1698 && (litexp
->X_add_number
== exp
->X_add_number
)
1699 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1702 if ((litexp
->X_op
== exp
->X_op
)
1703 && (exp
->X_op
== O_symbol
)
1704 && (litexp
->X_add_number
== exp
->X_add_number
)
1705 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1706 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1710 /* Do we need to create a new entry? */
1711 if (entry
== pool
->next_free_entry
)
1713 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1715 set_syntax_error (_("literal pool overflow"));
1719 pool
->literals
[entry
].exp
= *exp
;
1720 pool
->next_free_entry
+= 1;
1721 if (exp
->X_op
== O_big
)
1723 /* PR 16688: Bignums are held in a single global array. We must
1724 copy and preserve that value now, before it is overwritten. */
1725 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1727 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1728 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1731 pool
->literals
[entry
].bignum
= NULL
;
1734 exp
->X_op
= O_symbol
;
1735 exp
->X_add_number
= ((int) entry
) * size
;
1736 exp
->X_add_symbol
= pool
->symbol
;
1741 /* Can't use symbol_new here, so have to create a symbol and then at
1742 a later date assign it a value. Thats what these functions do. */
1745 symbol_locate (symbolS
* symbolP
,
1746 const char *name
,/* It is copied, the caller can modify. */
1747 segT segment
, /* Segment identifier (SEG_<something>). */
1748 valueT valu
, /* Symbol value. */
1749 fragS
* frag
) /* Associated fragment. */
1752 char *preserved_copy_of_name
;
1754 name_length
= strlen (name
) + 1; /* +1 for \0. */
1755 obstack_grow (¬es
, name
, name_length
);
1756 preserved_copy_of_name
= obstack_finish (¬es
);
1758 #ifdef tc_canonicalize_symbol_name
1759 preserved_copy_of_name
=
1760 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1763 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1765 S_SET_SEGMENT (symbolP
, segment
);
1766 S_SET_VALUE (symbolP
, valu
);
1767 symbol_clear_list_pointers (symbolP
);
1769 symbol_set_frag (symbolP
, frag
);
1771 /* Link to end of symbol chain. */
1773 extern int symbol_table_frozen
;
1775 if (symbol_table_frozen
)
1779 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1781 obj_symbol_new_hook (symbolP
);
1783 #ifdef tc_symbol_new_hook
1784 tc_symbol_new_hook (symbolP
);
1788 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1789 #endif /* DEBUG_SYMS */
1794 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1801 for (align
= 2; align
<= 4; align
++)
1803 int size
= 1 << align
;
1805 pool
= find_literal_pool (size
);
1806 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1809 /* Align pool as you have word accesses.
1810 Only make a frag if we have to. */
1812 frag_align (align
, 0, 0);
1814 mapping_state (MAP_DATA
);
1816 record_alignment (now_seg
, align
);
1818 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1820 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1821 (valueT
) frag_now_fix (), frag_now
);
1822 symbol_table_insert (pool
->symbol
);
1824 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1826 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1828 if (exp
->X_op
== O_big
)
1830 /* PR 16688: Restore the global bignum value. */
1831 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1832 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1833 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1836 /* First output the expression in the instruction to the pool. */
1837 emit_expr (exp
, size
); /* .word|.xword */
1839 if (exp
->X_op
== O_big
)
1841 free (pool
->literals
[entry
].bignum
);
1842 pool
->literals
[entry
].bignum
= NULL
;
1846 /* Mark the pool as empty. */
1847 pool
->next_free_entry
= 0;
1848 pool
->symbol
= NULL
;
1853 /* Forward declarations for functions below, in the MD interface
1855 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1856 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1858 /* Directives: Data. */
1859 /* N.B. the support for relocation suffix in this directive needs to be
1860 implemented properly. */
1863 s_aarch64_elf_cons (int nbytes
)
1867 #ifdef md_flush_pending_output
1868 md_flush_pending_output ();
1871 if (is_it_end_of_statement ())
1873 demand_empty_rest_of_line ();
1877 #ifdef md_cons_align
1878 md_cons_align (nbytes
);
1881 mapping_state (MAP_DATA
);
1884 struct reloc_table_entry
*reloc
;
1888 if (exp
.X_op
!= O_symbol
)
1889 emit_expr (&exp
, (unsigned int) nbytes
);
1892 skip_past_char (&input_line_pointer
, '#');
1893 if (skip_past_char (&input_line_pointer
, ':'))
1895 reloc
= find_reloc_table_entry (&input_line_pointer
);
1897 as_bad (_("unrecognized relocation suffix"));
1899 as_bad (_("unimplemented relocation suffix"));
1900 ignore_rest_of_line ();
1904 emit_expr (&exp
, (unsigned int) nbytes
);
1907 while (*input_line_pointer
++ == ',');
1909 /* Put terminator back into stream. */
1910 input_line_pointer
--;
1911 demand_empty_rest_of_line ();
1914 #endif /* OBJ_ELF */
1916 /* Output a 32-bit word, but mark as an instruction. */
1919 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1923 #ifdef md_flush_pending_output
1924 md_flush_pending_output ();
1927 if (is_it_end_of_statement ())
1929 demand_empty_rest_of_line ();
1933 /* Sections are assumed to start aligned. In executable section, there is no
1934 MAP_DATA symbol pending. So we only align the address during
1935 MAP_DATA --> MAP_INSN transition.
1936 For other sections, this is not guaranteed. */
1937 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1938 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1939 frag_align_code (2, 0);
1942 mapping_state (MAP_INSN
);
1948 if (exp
.X_op
!= O_constant
)
1950 as_bad (_("constant expression required"));
1951 ignore_rest_of_line ();
1955 if (target_big_endian
)
1957 unsigned int val
= exp
.X_add_number
;
1958 exp
.X_add_number
= SWAP_32 (val
);
1960 emit_expr (&exp
, 4);
1962 while (*input_line_pointer
++ == ',');
1964 /* Put terminator back into stream. */
1965 input_line_pointer
--;
1966 demand_empty_rest_of_line ();
1970 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1973 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1979 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1980 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1982 demand_empty_rest_of_line ();
1985 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1988 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1992 /* Since we're just labelling the code, there's no need to define a
1995 /* Make sure there is enough room in this frag for the following
1996 blr. This trick only works if the blr follows immediately after
1997 the .tlsdesc directive. */
1999 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2000 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2002 demand_empty_rest_of_line ();
2005 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2008 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2014 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2015 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2017 demand_empty_rest_of_line ();
2019 #endif /* OBJ_ELF */
2021 static void s_aarch64_arch (int);
2022 static void s_aarch64_cpu (int);
2023 static void s_aarch64_arch_extension (int);
2025 /* This table describes all the machine specific pseudo-ops the assembler
2026 has to support. The fields are:
2027 pseudo-op name without dot
2028 function to call to execute this pseudo-op
2029 Integer arg to pass to the function. */
2031 const pseudo_typeS md_pseudo_table
[] = {
2032 /* Never called because '.req' does not start a line. */
2034 {"unreq", s_unreq
, 0},
2036 {"even", s_even
, 0},
2037 {"ltorg", s_ltorg
, 0},
2038 {"pool", s_ltorg
, 0},
2039 {"cpu", s_aarch64_cpu
, 0},
2040 {"arch", s_aarch64_arch
, 0},
2041 {"arch_extension", s_aarch64_arch_extension
, 0},
2042 {"inst", s_aarch64_inst
, 0},
2044 {"tlsdescadd", s_tlsdescadd
, 0},
2045 {"tlsdesccall", s_tlsdesccall
, 0},
2046 {"tlsdescldr", s_tlsdescldr
, 0},
2047 {"word", s_aarch64_elf_cons
, 4},
2048 {"long", s_aarch64_elf_cons
, 4},
2049 {"xword", s_aarch64_elf_cons
, 8},
2050 {"dword", s_aarch64_elf_cons
, 8},
2056 /* Check whether STR points to a register name followed by a comma or the
2057 end of line; REG_TYPE indicates which register types are checked
2058 against. Return TRUE if STR is such a register name; otherwise return
2059 FALSE. The function does not intend to produce any diagnostics, but since
2060 the register parser aarch64_reg_parse, which is called by this function,
2061 does produce diagnostics, we call clear_error to clear any diagnostics
2062 that may be generated by aarch64_reg_parse.
2063 Also, the function returns FALSE directly if there is any user error
2064 present at the function entry. This prevents the existing diagnostics
2065 state from being spoiled.
2066 The function currently serves parse_constant_immediate and
2067 parse_big_immediate only. */
2069 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2073 /* Prevent the diagnostics state from being spoiled. */
2077 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2079 /* Clear the parsing error that may be set by the reg parser. */
2082 if (reg
== PARSE_FAIL
)
2085 skip_whitespace (str
);
2086 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2092 /* Parser functions used exclusively in instruction operands. */
2094 /* Parse an immediate expression which may not be constant.
2096 To prevent the expression parser from pushing a register name
2097 into the symbol table as an undefined symbol, firstly a check is
2098 done to find out whether STR is a register of type REG_TYPE followed
2099 by a comma or the end of line. Return FALSE if STR is such a string. */
2102 parse_immediate_expression (char **str
, expressionS
*exp
,
2103 aarch64_reg_type reg_type
)
2105 if (reg_name_p (*str
, reg_type
))
2107 set_recoverable_error (_("immediate operand required"));
2111 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2113 if (exp
->X_op
== O_absent
)
2115 set_fatal_syntax_error (_("missing immediate expression"));
2122 /* Constant immediate-value read function for use in insn parsing.
2123 STR points to the beginning of the immediate (with the optional
2124 leading #); *VAL receives the value. REG_TYPE says which register
2125 names should be treated as registers rather than as symbolic immediates.
2127 Return TRUE on success; otherwise return FALSE. */
2130 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2134 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2137 if (exp
.X_op
!= O_constant
)
2139 set_syntax_error (_("constant expression required"));
2143 *val
= exp
.X_add_number
;
2148 encode_imm_float_bits (uint32_t imm
)
2150 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2151 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2154 /* Return TRUE if the single-precision floating-point value encoded in IMM
2155 can be expressed in the AArch64 8-bit signed floating-point format with
2156 3-bit exponent and normalized 4 bits of precision; in other words, the
2157 floating-point value must be expressable as
2158 (+/-) n / 16 * power (2, r)
2159 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2162 aarch64_imm_float_p (uint32_t imm
)
2164 /* If a single-precision floating-point value has the following bit
2165 pattern, it can be expressed in the AArch64 8-bit floating-point
2168 3 32222222 2221111111111
2169 1 09876543 21098765432109876543210
2170 n Eeeeeexx xxxx0000000000000000000
2172 where n, e and each x are either 0 or 1 independently, with
2177 /* Prepare the pattern for 'Eeeeee'. */
2178 if (((imm
>> 30) & 0x1) == 0)
2179 pattern
= 0x3e000000;
2181 pattern
= 0x40000000;
2183 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2184 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2187 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2188 as an IEEE float without any loss of precision. Store the value in
2192 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2194 /* If a double-precision floating-point value has the following bit
2195 pattern, it can be expressed in a float:
2197 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2198 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2199 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2201 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2202 if Eeee_eeee != 1111_1111
2204 where n, e, s and S are either 0 or 1 independently and where ~ is the
2208 uint32_t high32
= imm
>> 32;
2209 uint32_t low32
= imm
;
2211 /* Lower 29 bits need to be 0s. */
2212 if ((imm
& 0x1fffffff) != 0)
2215 /* Prepare the pattern for 'Eeeeeeeee'. */
2216 if (((high32
>> 30) & 0x1) == 0)
2217 pattern
= 0x38000000;
2219 pattern
= 0x40000000;
2222 if ((high32
& 0x78000000) != pattern
)
2225 /* Check Eeee_eeee != 1111_1111. */
2226 if ((high32
& 0x7ff00000) == 0x47f00000)
2229 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2230 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2231 | (low32
>> 29)); /* 3 S bits. */
2235 /* Return true if we should treat OPERAND as a double-precision
2236 floating-point operand rather than a single-precision one. */
2238 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2240 /* Check for unsuffixed SVE registers, which are allowed
2241 for LDR and STR but not in instructions that require an
2242 immediate. We get better error messages if we arbitrarily
2243 pick one size, parse the immediate normally, and then
2244 report the match failure in the normal way. */
2245 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2246 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2249 /* Parse a floating-point immediate. Return TRUE on success and return the
2250 value in *IMMED in the format of IEEE754 single-precision encoding.
2251 *CCP points to the start of the string; DP_P is TRUE when the immediate
2252 is expected to be in double-precision (N.B. this only matters when
2253 hexadecimal representation is involved). REG_TYPE says which register
2254 names should be treated as registers rather than as symbolic immediates.
2256 This routine accepts any IEEE float; it is up to the callers to reject
2260 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2261 aarch64_reg_type reg_type
)
2265 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2266 int found_fpchar
= 0;
2268 unsigned fpword
= 0;
2269 bfd_boolean hex_p
= FALSE
;
2271 skip_past_char (&str
, '#');
2274 skip_whitespace (fpnum
);
2276 if (strncmp (fpnum
, "0x", 2) == 0)
2278 /* Support the hexadecimal representation of the IEEE754 encoding.
2279 Double-precision is expected when DP_P is TRUE, otherwise the
2280 representation should be in single-precision. */
2281 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2286 if (!can_convert_double_to_float (val
, &fpword
))
2289 else if ((uint64_t) val
> 0xffffffff)
2298 if (reg_name_p (str
, reg_type
))
2300 set_recoverable_error (_("immediate operand required"));
2304 /* We must not accidentally parse an integer as a floating-point number.
2305 Make sure that the value we parse is not an integer by checking for
2306 special characters '.' or 'e'. */
2307 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2308 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2322 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2325 /* Our FP word must be 32 bits (single-precision FP). */
2326 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2328 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2338 set_fatal_syntax_error (_("invalid floating-point constant"));
2342 /* Less-generic immediate-value read function with the possibility of loading
2343 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2346 To prevent the expression parser from pushing a register name into the
2347 symbol table as an undefined symbol, a check is firstly done to find
2348 out whether STR is a register of type REG_TYPE followed by a comma or
2349 the end of line. Return FALSE if STR is such a register. */
2352 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2356 if (reg_name_p (ptr
, reg_type
))
2358 set_syntax_error (_("immediate operand required"));
2362 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2364 if (inst
.reloc
.exp
.X_op
== O_constant
)
2365 *imm
= inst
.reloc
.exp
.X_add_number
;
2372 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2373 if NEED_LIBOPCODES is non-zero, the fixup will need
2374 assistance from the libopcodes. */
2377 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2378 const aarch64_opnd_info
*operand
,
2379 int need_libopcodes_p
)
2381 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2382 reloc
->opnd
= operand
->type
;
2383 if (need_libopcodes_p
)
2384 reloc
->need_libopcodes_p
= 1;
2387 /* Return TRUE if the instruction needs to be fixed up later internally by
2388 the GAS; otherwise return FALSE. */
2390 static inline bfd_boolean
2391 aarch64_gas_internal_fixup_p (void)
2393 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2396 /* Assign the immediate value to the relavant field in *OPERAND if
2397 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2398 needs an internal fixup in a later stage.
2399 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2400 IMM.VALUE that may get assigned with the constant. */
2402 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2403 aarch64_opnd_info
*operand
,
2405 int need_libopcodes_p
,
2408 if (reloc
->exp
.X_op
== O_constant
)
2411 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2413 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2414 reloc
->type
= BFD_RELOC_UNUSED
;
2418 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2419 /* Tell libopcodes to ignore this operand or not. This is helpful
2420 when one of the operands needs to be fixed up later but we need
2421 libopcodes to check the other operands. */
2422 operand
->skip
= skip_p
;
2426 /* Relocation modifiers. Each entry in the table contains the textual
2427 name for the relocation which may be placed before a symbol used as
2428 a load/store offset, or add immediate. It must be surrounded by a
2429 leading and trailing colon, for example:
2431 ldr x0, [x1, #:rello:varsym]
2432 add x0, x1, #:rello:varsym */
2434 struct reloc_table_entry
2438 bfd_reloc_code_real_type adr_type
;
2439 bfd_reloc_code_real_type adrp_type
;
2440 bfd_reloc_code_real_type movw_type
;
2441 bfd_reloc_code_real_type add_type
;
2442 bfd_reloc_code_real_type ldst_type
;
2443 bfd_reloc_code_real_type ld_literal_type
;
2446 static struct reloc_table_entry reloc_table
[] = {
2447 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2452 BFD_RELOC_AARCH64_ADD_LO12
,
2453 BFD_RELOC_AARCH64_LDST_LO12
,
2456 /* Higher 21 bits of pc-relative page offset: ADRP */
2459 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2465 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2468 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2474 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2478 BFD_RELOC_AARCH64_MOVW_G0
,
2483 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2487 BFD_RELOC_AARCH64_MOVW_G0_S
,
2492 /* Less significant bits 0-15 of address/value: MOVK, no check */
2496 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2501 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2505 BFD_RELOC_AARCH64_MOVW_G1
,
2510 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2514 BFD_RELOC_AARCH64_MOVW_G1_S
,
2519 /* Less significant bits 16-31 of address/value: MOVK, no check */
2523 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2528 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2532 BFD_RELOC_AARCH64_MOVW_G2
,
2537 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2541 BFD_RELOC_AARCH64_MOVW_G2_S
,
2546 /* Less significant bits 32-47 of address/value: MOVK, no check */
2550 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2555 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2559 BFD_RELOC_AARCH64_MOVW_G3
,
2564 /* Get to the page containing GOT entry for a symbol. */
2567 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2571 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2573 /* 12 bit offset into the page containing GOT entry for that symbol. */
2579 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2582 /* 0-15 bits of address/value: MOVk, no check. */
2586 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2591 /* Most significant bits 16-31 of address/value: MOVZ. */
2595 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2600 /* 15 bit offset into the page containing GOT entry for that symbol. */
2606 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2609 /* Get to the page containing GOT TLS entry for a symbol */
2610 {"gottprel_g0_nc", 0,
2613 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2618 /* Get to the page containing GOT TLS entry for a symbol */
2622 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2627 /* Get to the page containing GOT TLS entry for a symbol */
2629 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2630 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2636 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2641 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2645 /* Lower 16 bits address/value: MOVk. */
2649 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2654 /* Most significant bits 16-31 of address/value: MOVZ. */
2658 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2663 /* Get to the page containing GOT TLS entry for a symbol */
2665 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2666 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2670 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2672 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2677 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2678 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2681 /* Get to the page containing GOT TLS entry for a symbol.
2682 The same as GD, we allocate two consecutive GOT slots
2683 for module index and module offset, the only difference
2684 with GD is the module offset should be intialized to
2685 zero without any outstanding runtime relocation. */
2687 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2688 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2694 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2695 {"tlsldm_lo12_nc", 0,
2699 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2703 /* 12 bit offset into the module TLS base address. */
2708 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2709 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2712 /* Same as dtprel_lo12, no overflow check. */
2713 {"dtprel_lo12_nc", 0,
2717 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2718 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2721 /* bits[23:12] of offset to the module TLS base address. */
2726 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2730 /* bits[15:0] of offset to the module TLS base address. */
2734 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2739 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2743 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2748 /* bits[31:16] of offset to the module TLS base address. */
2752 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2757 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2761 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2766 /* bits[47:32] of offset to the module TLS base address. */
2770 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2775 /* Lower 16 bit offset into GOT entry for a symbol */
2776 {"tlsdesc_off_g0_nc", 0,
2779 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2784 /* Higher 16 bit offset into GOT entry for a symbol */
2785 {"tlsdesc_off_g1", 0,
2788 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2793 /* Get to the page containing GOT TLS entry for a symbol */
2796 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2800 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2802 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2803 {"gottprel_lo12", 0,
2808 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2811 /* Get tp offset for a symbol. */
2816 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2820 /* Get tp offset for a symbol. */
2825 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2829 /* Get tp offset for a symbol. */
2834 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2838 /* Get tp offset for a symbol. */
2839 {"tprel_lo12_nc", 0,
2843 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2847 /* Most significant bits 32-47 of address/value: MOVZ. */
2851 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2856 /* Most significant bits 16-31 of address/value: MOVZ. */
2860 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2865 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2869 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2874 /* Most significant bits 0-15 of address/value: MOVZ. */
2878 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2883 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2887 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2892 /* 15bit offset from got entry to base address of GOT table. */
2898 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2901 /* 14bit offset from got entry to base address of GOT table. */
2907 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2911 /* Given the address of a pointer pointing to the textual name of a
2912 relocation as may appear in assembler source, attempt to find its
2913 details in reloc_table. The pointer will be updated to the character
2914 after the trailing colon. On failure, NULL will be returned;
2915 otherwise return the reloc_table_entry. */
2917 static struct reloc_table_entry
*
2918 find_reloc_table_entry (char **str
)
2921 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2923 int length
= strlen (reloc_table
[i
].name
);
2925 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2926 && (*str
)[length
] == ':')
2928 *str
+= (length
+ 1);
2929 return &reloc_table
[i
];
2936 /* Mode argument to parse_shift and parser_shifter_operand. */
2937 enum parse_shift_mode
2939 SHIFTED_NONE
, /* no shifter allowed */
2940 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2942 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2944 SHIFTED_LSL
, /* bare "lsl #n" */
2945 SHIFTED_MUL
, /* bare "mul #n" */
2946 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2947 SHIFTED_MUL_VL
, /* "mul vl" */
2948 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2951 /* Parse a <shift> operator on an AArch64 data processing instruction.
2952 Return TRUE on success; otherwise return FALSE. */
2954 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2956 const struct aarch64_name_value_pair
*shift_op
;
2957 enum aarch64_modifier_kind kind
;
2963 for (p
= *str
; ISALPHA (*p
); p
++)
2968 set_syntax_error (_("shift expression expected"));
2972 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2974 if (shift_op
== NULL
)
2976 set_syntax_error (_("shift operator expected"));
2980 kind
= aarch64_get_operand_modifier (shift_op
);
2982 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2984 set_syntax_error (_("invalid use of 'MSL'"));
2988 if (kind
== AARCH64_MOD_MUL
2989 && mode
!= SHIFTED_MUL
2990 && mode
!= SHIFTED_MUL_VL
)
2992 set_syntax_error (_("invalid use of 'MUL'"));
2998 case SHIFTED_LOGIC_IMM
:
2999 if (aarch64_extend_operator_p (kind
) == TRUE
)
3001 set_syntax_error (_("extending shift is not permitted"));
3006 case SHIFTED_ARITH_IMM
:
3007 if (kind
== AARCH64_MOD_ROR
)
3009 set_syntax_error (_("'ROR' shift is not permitted"));
3015 if (kind
!= AARCH64_MOD_LSL
)
3017 set_syntax_error (_("only 'LSL' shift is permitted"));
3023 if (kind
!= AARCH64_MOD_MUL
)
3025 set_syntax_error (_("only 'MUL' is permitted"));
3030 case SHIFTED_MUL_VL
:
3031 /* "MUL VL" consists of two separate tokens. Require the first
3032 token to be "MUL" and look for a following "VL". */
3033 if (kind
== AARCH64_MOD_MUL
)
3035 skip_whitespace (p
);
3036 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3039 kind
= AARCH64_MOD_MUL_VL
;
3043 set_syntax_error (_("only 'MUL VL' is permitted"));
3046 case SHIFTED_REG_OFFSET
:
3047 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3048 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3050 set_fatal_syntax_error
3051 (_("invalid shift for the register offset addressing mode"));
3056 case SHIFTED_LSL_MSL
:
3057 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3059 set_syntax_error (_("invalid shift operator"));
3068 /* Whitespace can appear here if the next thing is a bare digit. */
3069 skip_whitespace (p
);
3071 /* Parse shift amount. */
3073 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3074 exp
.X_op
= O_absent
;
3077 if (is_immediate_prefix (*p
))
3082 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3084 if (kind
== AARCH64_MOD_MUL_VL
)
3085 /* For consistency, give MUL VL the same shift amount as an implicit
3087 operand
->shifter
.amount
= 1;
3088 else if (exp
.X_op
== O_absent
)
3090 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
3092 set_syntax_error (_("missing shift amount"));
3095 operand
->shifter
.amount
= 0;
3097 else if (exp
.X_op
!= O_constant
)
3099 set_syntax_error (_("constant shift amount required"));
3102 /* For parsing purposes, MUL #n has no inherent range. The range
3103 depends on the operand and will be checked by operand-specific
3105 else if (kind
!= AARCH64_MOD_MUL
3106 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3108 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3113 operand
->shifter
.amount
= exp
.X_add_number
;
3114 operand
->shifter
.amount_present
= 1;
3117 operand
->shifter
.operator_present
= 1;
3118 operand
->shifter
.kind
= kind
;
3124 /* Parse a <shifter_operand> for a data processing instruction:
3127 #<immediate>, LSL #imm
3129 Validation of immediate operands is deferred to md_apply_fix.
3131 Return TRUE on success; otherwise return FALSE. */
3134 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3135 enum parse_shift_mode mode
)
3139 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3144 /* Accept an immediate expression. */
3145 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3148 /* Accept optional LSL for arithmetic immediate values. */
3149 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3150 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3153 /* Not accept any shifter for logical immediate values. */
3154 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3155 && parse_shift (&p
, operand
, mode
))
3157 set_syntax_error (_("unexpected shift operator"));
3165 /* Parse a <shifter_operand> for a data processing instruction:
3170 #<immediate>, LSL #imm
3172 where <shift> is handled by parse_shift above, and the last two
3173 cases are handled by the function above.
3175 Validation of immediate operands is deferred to md_apply_fix.
3177 Return TRUE on success; otherwise return FALSE. */
3180 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3181 enum parse_shift_mode mode
)
3183 const reg_entry
*reg
;
3184 aarch64_opnd_qualifier_t qualifier
;
3185 enum aarch64_operand_class opd_class
3186 = aarch64_get_operand_class (operand
->type
);
3188 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3191 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3193 set_syntax_error (_("unexpected register in the immediate operand"));
3197 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3199 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3203 operand
->reg
.regno
= reg
->number
;
3204 operand
->qualifier
= qualifier
;
3206 /* Accept optional shift operation on register. */
3207 if (! skip_past_comma (str
))
3210 if (! parse_shift (str
, operand
, mode
))
3215 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3218 (_("integer register expected in the extended/shifted operand "
3223 /* We have a shifted immediate variable. */
3224 return parse_shifter_operand_imm (str
, operand
, mode
);
3227 /* Return TRUE on success; return FALSE otherwise. */
3230 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3231 enum parse_shift_mode mode
)
3235 /* Determine if we have the sequence of characters #: or just :
3236 coming next. If we do, then we check for a :rello: relocation
3237 modifier. If we don't, punt the whole lot to
3238 parse_shifter_operand. */
3240 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3242 struct reloc_table_entry
*entry
;
3250 /* Try to parse a relocation. Anything else is an error. */
3251 if (!(entry
= find_reloc_table_entry (str
)))
3253 set_syntax_error (_("unknown relocation modifier"));
3257 if (entry
->add_type
== 0)
3260 (_("this relocation modifier is not allowed on this instruction"));
3264 /* Save str before we decompose it. */
3267 /* Next, we parse the expression. */
3268 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3271 /* Record the relocation type (use the ADD variant here). */
3272 inst
.reloc
.type
= entry
->add_type
;
3273 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3275 /* If str is empty, we've reached the end, stop here. */
3279 /* Otherwise, we have a shifted reloc modifier, so rewind to
3280 recover the variable name and continue parsing for the shifter. */
3282 return parse_shifter_operand_imm (str
, operand
, mode
);
3285 return parse_shifter_operand (str
, operand
, mode
);
3288 /* Parse all forms of an address expression. Information is written
3289 to *OPERAND and/or inst.reloc.
3291 The A64 instruction set has the following addressing modes:
3294 [base] // in SIMD ld/st structure
3295 [base{,#0}] // in ld/st exclusive
3297 [base,Xm{,LSL #imm}]
3298 [base,Xm,SXTX {#imm}]
3299 [base,Wm,(S|U)XTW {#imm}]
3304 [base],Xm // in SIMD ld/st structure
3305 PC-relative (literal)
3309 [base,Zm.D{,LSL #imm}]
3310 [base,Zm.S,(S|U)XTW {#imm}]
3311 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3314 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3315 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3316 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3318 (As a convenience, the notation "=immediate" is permitted in conjunction
3319 with the pc-relative literal load instructions to automatically place an
3320 immediate value or symbolic address in a nearby literal pool and generate
3321 a hidden label which references it.)
3323 Upon a successful parsing, the address structure in *OPERAND will be
3324 filled in the following way:
3326 .base_regno = <base>
3327 .offset.is_reg // 1 if the offset is a register
3329 .offset.regno = <Rm>
3331 For different addressing modes defined in the A64 ISA:
3334 .pcrel=0; .preind=1; .postind=0; .writeback=0
3336 .pcrel=0; .preind=1; .postind=0; .writeback=1
3338 .pcrel=0; .preind=0; .postind=1; .writeback=1
3339 PC-relative (literal)
3340 .pcrel=1; .preind=1; .postind=0; .writeback=0
3342 The shift/extension information, if any, will be stored in .shifter.
3343 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3344 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3345 corresponding register.
3347 BASE_TYPE says which types of base register should be accepted and
3348 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3349 is the type of shifter that is allowed for immediate offsets,
3350 or SHIFTED_NONE if none.
3352 In all other respects, it is the caller's responsibility to check
3353 for addressing modes not supported by the instruction, and to set
3357 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3358 aarch64_opnd_qualifier_t
*base_qualifier
,
3359 aarch64_opnd_qualifier_t
*offset_qualifier
,
3360 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3361 enum parse_shift_mode imm_shift_mode
)
3364 const reg_entry
*reg
;
3365 expressionS
*exp
= &inst
.reloc
.exp
;
3367 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3368 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3369 if (! skip_past_char (&p
, '['))
3371 /* =immediate or label. */
3372 operand
->addr
.pcrel
= 1;
3373 operand
->addr
.preind
= 1;
3375 /* #:<reloc_op>:<symbol> */
3376 skip_past_char (&p
, '#');
3377 if (skip_past_char (&p
, ':'))
3379 bfd_reloc_code_real_type ty
;
3380 struct reloc_table_entry
*entry
;
3382 /* Try to parse a relocation modifier. Anything else is
3384 entry
= find_reloc_table_entry (&p
);
3387 set_syntax_error (_("unknown relocation modifier"));
3391 switch (operand
->type
)
3393 case AARCH64_OPND_ADDR_PCREL21
:
3395 ty
= entry
->adr_type
;
3399 ty
= entry
->ld_literal_type
;
3406 (_("this relocation modifier is not allowed on this "
3412 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3414 set_syntax_error (_("invalid relocation expression"));
3418 /* #:<reloc_op>:<expr> */
3419 /* Record the relocation type. */
3420 inst
.reloc
.type
= ty
;
3421 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3426 if (skip_past_char (&p
, '='))
3427 /* =immediate; need to generate the literal in the literal pool. */
3428 inst
.gen_lit_pool
= 1;
3430 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3432 set_syntax_error (_("invalid address"));
3443 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3444 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3446 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3449 operand
->addr
.base_regno
= reg
->number
;
3452 if (skip_past_comma (&p
))
3455 operand
->addr
.preind
= 1;
3457 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3460 if (!aarch64_check_reg_type (reg
, offset_type
))
3462 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3467 operand
->addr
.offset
.regno
= reg
->number
;
3468 operand
->addr
.offset
.is_reg
= 1;
3469 /* Shifted index. */
3470 if (skip_past_comma (&p
))
3473 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3474 /* Use the diagnostics set in parse_shift, so not set new
3475 error message here. */
3479 [base,Xm{,LSL #imm}]
3480 [base,Xm,SXTX {#imm}]
3481 [base,Wm,(S|U)XTW {#imm}] */
3482 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3483 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3484 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3486 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3488 set_syntax_error (_("invalid use of 32-bit register offset"));
3491 if (aarch64_get_qualifier_esize (*base_qualifier
)
3492 != aarch64_get_qualifier_esize (*offset_qualifier
))
3494 set_syntax_error (_("offset has different size from base"));
3498 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3500 set_syntax_error (_("invalid use of 64-bit register offset"));
3506 /* [Xn,#:<reloc_op>:<symbol> */
3507 skip_past_char (&p
, '#');
3508 if (skip_past_char (&p
, ':'))
3510 struct reloc_table_entry
*entry
;
3512 /* Try to parse a relocation modifier. Anything else is
3514 if (!(entry
= find_reloc_table_entry (&p
)))
3516 set_syntax_error (_("unknown relocation modifier"));
3520 if (entry
->ldst_type
== 0)
3523 (_("this relocation modifier is not allowed on this "
3528 /* [Xn,#:<reloc_op>: */
3529 /* We now have the group relocation table entry corresponding to
3530 the name in the assembler source. Next, we parse the
3532 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3534 set_syntax_error (_("invalid relocation expression"));
3538 /* [Xn,#:<reloc_op>:<expr> */
3539 /* Record the load/store relocation type. */
3540 inst
.reloc
.type
= entry
->ldst_type
;
3541 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3545 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3547 set_syntax_error (_("invalid expression in the address"));
3551 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3552 /* [Xn,<expr>,<shifter> */
3553 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3559 if (! skip_past_char (&p
, ']'))
3561 set_syntax_error (_("']' expected"));
3565 if (skip_past_char (&p
, '!'))
3567 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3569 set_syntax_error (_("register offset not allowed in pre-indexed "
3570 "addressing mode"));
3574 operand
->addr
.writeback
= 1;
3576 else if (skip_past_comma (&p
))
3579 operand
->addr
.postind
= 1;
3580 operand
->addr
.writeback
= 1;
3582 if (operand
->addr
.preind
)
3584 set_syntax_error (_("cannot combine pre- and post-indexing"));
3588 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3592 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3594 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3598 operand
->addr
.offset
.regno
= reg
->number
;
3599 operand
->addr
.offset
.is_reg
= 1;
3601 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3604 set_syntax_error (_("invalid expression in the address"));
3609 /* If at this point neither .preind nor .postind is set, we have a
3610 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3611 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3613 if (operand
->addr
.writeback
)
3616 set_syntax_error (_("missing offset in the pre-indexed address"));
3619 operand
->addr
.preind
= 1;
3620 inst
.reloc
.exp
.X_op
= O_constant
;
3621 inst
.reloc
.exp
.X_add_number
= 0;
3628 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3631 parse_address (char **str
, aarch64_opnd_info
*operand
)
3633 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3634 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3635 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3638 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3639 The arguments have the same meaning as for parse_address_main.
3640 Return TRUE on success. */
3642 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3643 aarch64_opnd_qualifier_t
*base_qualifier
,
3644 aarch64_opnd_qualifier_t
*offset_qualifier
)
3646 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3647 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3651 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3652 Return TRUE on success; otherwise return FALSE. */
3654 parse_half (char **str
, int *internal_fixup_p
)
3658 skip_past_char (&p
, '#');
3660 gas_assert (internal_fixup_p
);
3661 *internal_fixup_p
= 0;
3665 struct reloc_table_entry
*entry
;
3667 /* Try to parse a relocation. Anything else is an error. */
3669 if (!(entry
= find_reloc_table_entry (&p
)))
3671 set_syntax_error (_("unknown relocation modifier"));
3675 if (entry
->movw_type
== 0)
3678 (_("this relocation modifier is not allowed on this instruction"));
3682 inst
.reloc
.type
= entry
->movw_type
;
3685 *internal_fixup_p
= 1;
3687 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3694 /* Parse an operand for an ADRP instruction:
3696 Return TRUE on success; otherwise return FALSE. */
3699 parse_adrp (char **str
)
3706 struct reloc_table_entry
*entry
;
3708 /* Try to parse a relocation. Anything else is an error. */
3710 if (!(entry
= find_reloc_table_entry (&p
)))
3712 set_syntax_error (_("unknown relocation modifier"));
3716 if (entry
->adrp_type
== 0)
3719 (_("this relocation modifier is not allowed on this instruction"));
3723 inst
.reloc
.type
= entry
->adrp_type
;
3726 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3728 inst
.reloc
.pc_rel
= 1;
3730 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3737 /* Miscellaneous. */
3739 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3740 of SIZE tokens in which index I gives the token for field value I,
3741 or is null if field value I is invalid. REG_TYPE says which register
3742 names should be treated as registers rather than as symbolic immediates.
3744 Return true on success, moving *STR past the operand and storing the
3745 field value in *VAL. */
3748 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3749 size_t size
, aarch64_reg_type reg_type
)
3755 /* Match C-like tokens. */
3757 while (ISALNUM (*q
))
3760 for (i
= 0; i
< size
; ++i
)
3762 && strncasecmp (array
[i
], p
, q
- p
) == 0
3763 && array
[i
][q
- p
] == 0)
3770 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3773 if (exp
.X_op
== O_constant
3774 && (uint64_t) exp
.X_add_number
< size
)
3776 *val
= exp
.X_add_number
;
3781 /* Use the default error for this operand. */
3785 /* Parse an option for a preload instruction. Returns the encoding for the
3786 option, or PARSE_FAIL. */
3789 parse_pldop (char **str
)
3792 const struct aarch64_name_value_pair
*o
;
3795 while (ISALNUM (*q
))
3798 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3806 /* Parse an option for a barrier instruction. Returns the encoding for the
3807 option, or PARSE_FAIL. */
3810 parse_barrier (char **str
)
3813 const asm_barrier_opt
*o
;
3816 while (ISALPHA (*q
))
3819 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3827 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3828 return 0 if successful. Otherwise return PARSE_FAIL. */
3831 parse_barrier_psb (char **str
,
3832 const struct aarch64_name_value_pair
** hint_opt
)
3835 const struct aarch64_name_value_pair
*o
;
3838 while (ISALPHA (*q
))
3841 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3844 set_fatal_syntax_error
3845 ( _("unknown or missing option to PSB"));
3849 if (o
->value
!= 0x11)
3851 /* PSB only accepts option name 'CSYNC'. */
3853 (_("the specified option is not accepted for PSB"));
3862 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3863 Returns the encoding for the option, or PARSE_FAIL.
3865 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3866 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3868 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3869 field, otherwise as a system register.
3873 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3874 int imple_defined_p
, int pstatefield_p
)
3878 const aarch64_sys_reg
*o
;
3882 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3884 *p
++ = TOLOWER (*q
);
3886 /* Assert that BUF be large enough. */
3887 gas_assert (p
- buf
== q
- *str
);
3889 o
= hash_find (sys_regs
, buf
);
3892 if (!imple_defined_p
)
3896 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3897 unsigned int op0
, op1
, cn
, cm
, op2
;
3899 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3902 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3904 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3909 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3910 as_bad (_("selected processor does not support PSTATE field "
3912 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3913 as_bad (_("selected processor does not support system register "
3915 if (aarch64_sys_reg_deprecated_p (o
))
3916 as_warn (_("system register name '%s' is deprecated and may be "
3917 "removed in a future release"), buf
);
3925 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3926 for the option, or NULL. */
3928 static const aarch64_sys_ins_reg
*
3929 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3933 const aarch64_sys_ins_reg
*o
;
3936 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3938 *p
++ = TOLOWER (*q
);
3941 o
= hash_find (sys_ins_regs
, buf
);
3945 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3946 as_bad (_("selected processor does not support system register "
3953 #define po_char_or_fail(chr) do { \
3954 if (! skip_past_char (&str, chr)) \
3958 #define po_reg_or_fail(regtype) do { \
3959 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3960 if (val == PARSE_FAIL) \
3962 set_default_error (); \
3967 #define po_int_reg_or_fail(reg_type) do { \
3968 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
3969 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
3971 set_default_error (); \
3974 info->reg.regno = reg->number; \
3975 info->qualifier = qualifier; \
3978 #define po_imm_nc_or_fail() do { \
3979 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3983 #define po_imm_or_fail(min, max) do { \
3984 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3986 if (val < min || val > max) \
3988 set_fatal_syntax_error (_("immediate value out of range "\
3989 #min " to "#max)); \
3994 #define po_enum_or_fail(array) do { \
3995 if (!parse_enum_string (&str, &val, array, \
3996 ARRAY_SIZE (array), imm_reg_type)) \
4000 #define po_misc_or_fail(expr) do { \
4005 /* encode the 12-bit imm field of Add/sub immediate */
4006 static inline uint32_t
4007 encode_addsub_imm (uint32_t imm
)
4012 /* encode the shift amount field of Add/sub immediate */
4013 static inline uint32_t
4014 encode_addsub_imm_shift_amount (uint32_t cnt
)
4020 /* encode the imm field of Adr instruction */
4021 static inline uint32_t
4022 encode_adr_imm (uint32_t imm
)
4024 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4025 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4028 /* encode the immediate field of Move wide immediate */
4029 static inline uint32_t
4030 encode_movw_imm (uint32_t imm
)
4035 /* encode the 26-bit offset of unconditional branch */
4036 static inline uint32_t
4037 encode_branch_ofs_26 (uint32_t ofs
)
4039 return ofs
& ((1 << 26) - 1);
4042 /* encode the 19-bit offset of conditional branch and compare & branch */
4043 static inline uint32_t
4044 encode_cond_branch_ofs_19 (uint32_t ofs
)
4046 return (ofs
& ((1 << 19) - 1)) << 5;
4049 /* encode the 19-bit offset of ld literal */
4050 static inline uint32_t
4051 encode_ld_lit_ofs_19 (uint32_t ofs
)
4053 return (ofs
& ((1 << 19) - 1)) << 5;
4056 /* Encode the 14-bit offset of test & branch. */
4057 static inline uint32_t
4058 encode_tst_branch_ofs_14 (uint32_t ofs
)
4060 return (ofs
& ((1 << 14) - 1)) << 5;
4063 /* Encode the 16-bit imm field of svc/hvc/smc. */
4064 static inline uint32_t
4065 encode_svc_imm (uint32_t imm
)
4070 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4071 static inline uint32_t
4072 reencode_addsub_switch_add_sub (uint32_t opcode
)
4074 return opcode
^ (1 << 30);
4077 static inline uint32_t
4078 reencode_movzn_to_movz (uint32_t opcode
)
4080 return opcode
| (1 << 30);
4083 static inline uint32_t
4084 reencode_movzn_to_movn (uint32_t opcode
)
4086 return opcode
& ~(1 << 30);
4089 /* Overall per-instruction processing. */
4091 /* We need to be able to fix up arbitrary expressions in some statements.
4092 This is so that we can handle symbols that are an arbitrary distance from
4093 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4094 which returns part of an address in a form which will be valid for
4095 a data instruction. We do this by pushing the expression into a symbol
4096 in the expr_section, and creating a fix for that. */
4099 fix_new_aarch64 (fragS
* frag
,
4101 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4111 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4115 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4122 /* Diagnostics on operands errors. */
4124 /* By default, output verbose error message.
4125 Disable the verbose error message by -mno-verbose-error. */
4126 static int verbose_error_p
= 1;
4128 #ifdef DEBUG_AARCH64
4129 /* N.B. this is only for the purpose of debugging. */
4130 const char* operand_mismatch_kind_names
[] =
4133 "AARCH64_OPDE_RECOVERABLE",
4134 "AARCH64_OPDE_SYNTAX_ERROR",
4135 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4136 "AARCH64_OPDE_INVALID_VARIANT",
4137 "AARCH64_OPDE_OUT_OF_RANGE",
4138 "AARCH64_OPDE_UNALIGNED",
4139 "AARCH64_OPDE_REG_LIST",
4140 "AARCH64_OPDE_OTHER_ERROR",
4142 #endif /* DEBUG_AARCH64 */
4144 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4146 When multiple errors of different kinds are found in the same assembly
4147 line, only the error of the highest severity will be picked up for
4148 issuing the diagnostics. */
4150 static inline bfd_boolean
4151 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4152 enum aarch64_operand_error_kind rhs
)
4154 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4155 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4156 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4157 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4158 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4159 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4160 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4161 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4165 /* Helper routine to get the mnemonic name from the assembly instruction
4166 line; should only be called for the diagnosis purpose, as there is
4167 string copy operation involved, which may affect the runtime
4168 performance if used in elsewhere. */
4171 get_mnemonic_name (const char *str
)
4173 static char mnemonic
[32];
4176 /* Get the first 15 bytes and assume that the full name is included. */
4177 strncpy (mnemonic
, str
, 31);
4178 mnemonic
[31] = '\0';
4180 /* Scan up to the end of the mnemonic, which must end in white space,
4181 '.', or end of string. */
4182 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4187 /* Append '...' to the truncated long name. */
4188 if (ptr
- mnemonic
== 31)
4189 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4195 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4197 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4198 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4201 /* Data strutures storing one user error in the assembly code related to
4204 struct operand_error_record
4206 const aarch64_opcode
*opcode
;
4207 aarch64_operand_error detail
;
4208 struct operand_error_record
*next
;
4211 typedef struct operand_error_record operand_error_record
;
4213 struct operand_errors
4215 operand_error_record
*head
;
4216 operand_error_record
*tail
;
4219 typedef struct operand_errors operand_errors
;
4221 /* Top-level data structure reporting user errors for the current line of
4223 The way md_assemble works is that all opcodes sharing the same mnemonic
4224 name are iterated to find a match to the assembly line. In this data
4225 structure, each of the such opcodes will have one operand_error_record
4226 allocated and inserted. In other words, excessive errors related with
4227 a single opcode are disregarded. */
4228 operand_errors operand_error_report
;
4230 /* Free record nodes. */
4231 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4233 /* Initialize the data structure that stores the operand mismatch
4234 information on assembling one line of the assembly code. */
4236 init_operand_error_report (void)
4238 if (operand_error_report
.head
!= NULL
)
4240 gas_assert (operand_error_report
.tail
!= NULL
);
4241 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4242 free_opnd_error_record_nodes
= operand_error_report
.head
;
4243 operand_error_report
.head
= NULL
;
4244 operand_error_report
.tail
= NULL
;
4247 gas_assert (operand_error_report
.tail
== NULL
);
4250 /* Return TRUE if some operand error has been recorded during the
4251 parsing of the current assembly line using the opcode *OPCODE;
4252 otherwise return FALSE. */
4253 static inline bfd_boolean
4254 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4256 operand_error_record
*record
= operand_error_report
.head
;
4257 return record
&& record
->opcode
== opcode
;
4260 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4261 OPCODE field is initialized with OPCODE.
4262 N.B. only one record for each opcode, i.e. the maximum of one error is
4263 recorded for each instruction template. */
4266 add_operand_error_record (const operand_error_record
* new_record
)
4268 const aarch64_opcode
*opcode
= new_record
->opcode
;
4269 operand_error_record
* record
= operand_error_report
.head
;
4271 /* The record may have been created for this opcode. If not, we need
4273 if (! opcode_has_operand_error_p (opcode
))
4275 /* Get one empty record. */
4276 if (free_opnd_error_record_nodes
== NULL
)
4278 record
= XNEW (operand_error_record
);
4282 record
= free_opnd_error_record_nodes
;
4283 free_opnd_error_record_nodes
= record
->next
;
4285 record
->opcode
= opcode
;
4286 /* Insert at the head. */
4287 record
->next
= operand_error_report
.head
;
4288 operand_error_report
.head
= record
;
4289 if (operand_error_report
.tail
== NULL
)
4290 operand_error_report
.tail
= record
;
4292 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4293 && record
->detail
.index
<= new_record
->detail
.index
4294 && operand_error_higher_severity_p (record
->detail
.kind
,
4295 new_record
->detail
.kind
))
4297 /* In the case of multiple errors found on operands related with a
4298 single opcode, only record the error of the leftmost operand and
4299 only if the error is of higher severity. */
4300 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4301 " the existing error %s on operand %d",
4302 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4303 new_record
->detail
.index
,
4304 operand_mismatch_kind_names
[record
->detail
.kind
],
4305 record
->detail
.index
);
4309 record
->detail
= new_record
->detail
;
4313 record_operand_error_info (const aarch64_opcode
*opcode
,
4314 aarch64_operand_error
*error_info
)
4316 operand_error_record record
;
4317 record
.opcode
= opcode
;
4318 record
.detail
= *error_info
;
4319 add_operand_error_record (&record
);
4322 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4323 error message *ERROR, for operand IDX (count from 0). */
4326 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4327 enum aarch64_operand_error_kind kind
,
4330 aarch64_operand_error info
;
4331 memset(&info
, 0, sizeof (info
));
4335 record_operand_error_info (opcode
, &info
);
4339 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4340 enum aarch64_operand_error_kind kind
,
4341 const char* error
, const int *extra_data
)
4343 aarch64_operand_error info
;
4347 info
.data
[0] = extra_data
[0];
4348 info
.data
[1] = extra_data
[1];
4349 info
.data
[2] = extra_data
[2];
4350 record_operand_error_info (opcode
, &info
);
4354 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4355 const char* error
, int lower_bound
,
4358 int data
[3] = {lower_bound
, upper_bound
, 0};
4359 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4363 /* Remove the operand error record for *OPCODE. */
4364 static void ATTRIBUTE_UNUSED
4365 remove_operand_error_record (const aarch64_opcode
*opcode
)
4367 if (opcode_has_operand_error_p (opcode
))
4369 operand_error_record
* record
= operand_error_report
.head
;
4370 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4371 operand_error_report
.head
= record
->next
;
4372 record
->next
= free_opnd_error_record_nodes
;
4373 free_opnd_error_record_nodes
= record
;
4374 if (operand_error_report
.head
== NULL
)
4376 gas_assert (operand_error_report
.tail
== record
);
4377 operand_error_report
.tail
= NULL
;
4382 /* Given the instruction in *INSTR, return the index of the best matched
4383 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4385 Return -1 if there is no qualifier sequence; return the first match
4386 if there is multiple matches found. */
4389 find_best_match (const aarch64_inst
*instr
,
4390 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4392 int i
, num_opnds
, max_num_matched
, idx
;
4394 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4397 DEBUG_TRACE ("no operand");
4401 max_num_matched
= 0;
4404 /* For each pattern. */
4405 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4408 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4410 /* Most opcodes has much fewer patterns in the list. */
4411 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4413 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4417 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4418 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4421 if (num_matched
> max_num_matched
)
4423 max_num_matched
= num_matched
;
4428 DEBUG_TRACE ("return with %d", idx
);
4432 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4433 corresponding operands in *INSTR. */
4436 assign_qualifier_sequence (aarch64_inst
*instr
,
4437 const aarch64_opnd_qualifier_t
*qualifiers
)
4440 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4441 gas_assert (num_opnds
);
4442 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4443 instr
->operands
[i
].qualifier
= *qualifiers
;
4446 /* Print operands for the diagnosis purpose. */
4449 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4450 const aarch64_opnd_info
*opnds
)
4454 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4458 /* We regard the opcode operand info more, however we also look into
4459 the inst->operands to support the disassembling of the optional
4461 The two operand code should be the same in all cases, apart from
4462 when the operand can be optional. */
4463 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4464 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4467 /* Generate the operand string in STR. */
4468 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4472 strcat (buf
, i
== 0 ? " " : ",");
4474 /* Append the operand string. */
4479 /* Send to stderr a string as information. */
4482 output_info (const char *format
, ...)
4488 file
= as_where (&line
);
4492 fprintf (stderr
, "%s:%u: ", file
, line
);
4494 fprintf (stderr
, "%s: ", file
);
4496 fprintf (stderr
, _("Info: "));
4497 va_start (args
, format
);
4498 vfprintf (stderr
, format
, args
);
4500 (void) putc ('\n', stderr
);
4503 /* Output one operand error record. */
4506 output_operand_error_record (const operand_error_record
*record
, char *str
)
4508 const aarch64_operand_error
*detail
= &record
->detail
;
4509 int idx
= detail
->index
;
4510 const aarch64_opcode
*opcode
= record
->opcode
;
4511 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4512 : AARCH64_OPND_NIL
);
4514 switch (detail
->kind
)
4516 case AARCH64_OPDE_NIL
:
4520 case AARCH64_OPDE_SYNTAX_ERROR
:
4521 case AARCH64_OPDE_RECOVERABLE
:
4522 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4523 case AARCH64_OPDE_OTHER_ERROR
:
4524 /* Use the prepared error message if there is, otherwise use the
4525 operand description string to describe the error. */
4526 if (detail
->error
!= NULL
)
4529 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4531 as_bad (_("%s at operand %d -- `%s'"),
4532 detail
->error
, idx
+ 1, str
);
4536 gas_assert (idx
>= 0);
4537 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4538 aarch64_get_operand_desc (opd_code
), str
);
4542 case AARCH64_OPDE_INVALID_VARIANT
:
4543 as_bad (_("operand mismatch -- `%s'"), str
);
4544 if (verbose_error_p
)
4546 /* We will try to correct the erroneous instruction and also provide
4547 more information e.g. all other valid variants.
4549 The string representation of the corrected instruction and other
4550 valid variants are generated by
4552 1) obtaining the intermediate representation of the erroneous
4554 2) manipulating the IR, e.g. replacing the operand qualifier;
4555 3) printing out the instruction by calling the printer functions
4556 shared with the disassembler.
4558 The limitation of this method is that the exact input assembly
4559 line cannot be accurately reproduced in some cases, for example an
4560 optional operand present in the actual assembly line will be
4561 omitted in the output; likewise for the optional syntax rules,
4562 e.g. the # before the immediate. Another limitation is that the
4563 assembly symbols and relocation operations in the assembly line
4564 currently cannot be printed out in the error report. Last but not
4565 least, when there is other error(s) co-exist with this error, the
4566 'corrected' instruction may be still incorrect, e.g. given
4567 'ldnp h0,h1,[x0,#6]!'
4568 this diagnosis will provide the version:
4569 'ldnp s0,s1,[x0,#6]!'
4570 which is still not right. */
4571 size_t len
= strlen (get_mnemonic_name (str
));
4575 aarch64_inst
*inst_base
= &inst
.base
;
4576 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4579 reset_aarch64_instruction (&inst
);
4580 inst_base
->opcode
= opcode
;
4582 /* Reset the error report so that there is no side effect on the
4583 following operand parsing. */
4584 init_operand_error_report ();
4587 result
= parse_operands (str
+ len
, opcode
)
4588 && programmer_friendly_fixup (&inst
);
4589 gas_assert (result
);
4590 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4592 gas_assert (!result
);
4594 /* Find the most matched qualifier sequence. */
4595 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4596 gas_assert (qlf_idx
> -1);
4598 /* Assign the qualifiers. */
4599 assign_qualifier_sequence (inst_base
,
4600 opcode
->qualifiers_list
[qlf_idx
]);
4602 /* Print the hint. */
4603 output_info (_(" did you mean this?"));
4604 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4605 print_operands (buf
, opcode
, inst_base
->operands
);
4606 output_info (_(" %s"), buf
);
4608 /* Print out other variant(s) if there is any. */
4610 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4611 output_info (_(" other valid variant(s):"));
4613 /* For each pattern. */
4614 qualifiers_list
= opcode
->qualifiers_list
;
4615 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4617 /* Most opcodes has much fewer patterns in the list.
4618 First NIL qualifier indicates the end in the list. */
4619 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4624 /* Mnemonics name. */
4625 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4627 /* Assign the qualifiers. */
4628 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4630 /* Print instruction. */
4631 print_operands (buf
, opcode
, inst_base
->operands
);
4633 output_info (_(" %s"), buf
);
4639 case AARCH64_OPDE_UNTIED_OPERAND
:
4640 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4641 detail
->index
+ 1, str
);
4644 case AARCH64_OPDE_OUT_OF_RANGE
:
4645 if (detail
->data
[0] != detail
->data
[1])
4646 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4647 detail
->error
? detail
->error
: _("immediate value"),
4648 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4650 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4651 detail
->error
? detail
->error
: _("immediate value"),
4652 detail
->data
[0], idx
+ 1, str
);
4655 case AARCH64_OPDE_REG_LIST
:
4656 if (detail
->data
[0] == 1)
4657 as_bad (_("invalid number of registers in the list; "
4658 "only 1 register is expected at operand %d -- `%s'"),
4661 as_bad (_("invalid number of registers in the list; "
4662 "%d registers are expected at operand %d -- `%s'"),
4663 detail
->data
[0], idx
+ 1, str
);
4666 case AARCH64_OPDE_UNALIGNED
:
4667 as_bad (_("immediate value should be a multiple of "
4668 "%d at operand %d -- `%s'"),
4669 detail
->data
[0], idx
+ 1, str
);
4678 /* Process and output the error message about the operand mismatching.
4680 When this function is called, the operand error information had
4681 been collected for an assembly line and there will be multiple
4682 errors in the case of mulitple instruction templates; output the
4683 error message that most closely describes the problem. */
4686 output_operand_error_report (char *str
)
4688 int largest_error_pos
;
4689 const char *msg
= NULL
;
4690 enum aarch64_operand_error_kind kind
;
4691 operand_error_record
*curr
;
4692 operand_error_record
*head
= operand_error_report
.head
;
4693 operand_error_record
*record
= NULL
;
4695 /* No error to report. */
4699 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4701 /* Only one error. */
4702 if (head
== operand_error_report
.tail
)
4704 DEBUG_TRACE ("single opcode entry with error kind: %s",
4705 operand_mismatch_kind_names
[head
->detail
.kind
]);
4706 output_operand_error_record (head
, str
);
4710 /* Find the error kind of the highest severity. */
4711 DEBUG_TRACE ("multiple opcode entres with error kind");
4712 kind
= AARCH64_OPDE_NIL
;
4713 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4715 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4716 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4717 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4718 kind
= curr
->detail
.kind
;
4720 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4722 /* Pick up one of errors of KIND to report. */
4723 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4724 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4726 if (curr
->detail
.kind
!= kind
)
4728 /* If there are multiple errors, pick up the one with the highest
4729 mismatching operand index. In the case of multiple errors with
4730 the equally highest operand index, pick up the first one or the
4731 first one with non-NULL error message. */
4732 if (curr
->detail
.index
> largest_error_pos
4733 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4734 && curr
->detail
.error
!= NULL
))
4736 largest_error_pos
= curr
->detail
.index
;
4738 msg
= record
->detail
.error
;
4742 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4743 DEBUG_TRACE ("Pick up error kind %s to report",
4744 operand_mismatch_kind_names
[record
->detail
.kind
]);
4747 output_operand_error_record (record
, str
);
4750 /* Write an AARCH64 instruction to buf - always little-endian. */
4752 put_aarch64_insn (char *buf
, uint32_t insn
)
4754 unsigned char *where
= (unsigned char *) buf
;
4756 where
[1] = insn
>> 8;
4757 where
[2] = insn
>> 16;
4758 where
[3] = insn
>> 24;
4762 get_aarch64_insn (char *buf
)
4764 unsigned char *where
= (unsigned char *) buf
;
4766 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4771 output_inst (struct aarch64_inst
*new_inst
)
4775 to
= frag_more (INSN_SIZE
);
4777 frag_now
->tc_frag_data
.recorded
= 1;
4779 put_aarch64_insn (to
, inst
.base
.value
);
4781 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4783 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4784 INSN_SIZE
, &inst
.reloc
.exp
,
4787 DEBUG_TRACE ("Prepared relocation fix up");
4788 /* Don't check the addend value against the instruction size,
4789 that's the job of our code in md_apply_fix(). */
4790 fixp
->fx_no_overflow
= 1;
4791 if (new_inst
!= NULL
)
4792 fixp
->tc_fix_data
.inst
= new_inst
;
4793 if (aarch64_gas_internal_fixup_p ())
4795 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4796 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4797 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4801 dwarf2_emit_insn (INSN_SIZE
);
4804 /* Link together opcodes of the same name. */
4808 aarch64_opcode
*opcode
;
4809 struct templates
*next
;
4812 typedef struct templates templates
;
4815 lookup_mnemonic (const char *start
, int len
)
4817 templates
*templ
= NULL
;
4819 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4823 /* Subroutine of md_assemble, responsible for looking up the primary
4824 opcode from the mnemonic the user wrote. STR points to the
4825 beginning of the mnemonic. */
4828 opcode_lookup (char **str
)
4831 const aarch64_cond
*cond
;
4835 /* Scan up to the end of the mnemonic, which must end in white space,
4836 '.', or end of string. */
4837 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4844 inst
.cond
= COND_ALWAYS
;
4846 /* Handle a possible condition. */
4849 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4852 inst
.cond
= cond
->value
;
4866 if (inst
.cond
== COND_ALWAYS
)
4868 /* Look for unaffixed mnemonic. */
4869 return lookup_mnemonic (base
, len
);
4873 /* append ".c" to mnemonic if conditional */
4874 memcpy (condname
, base
, len
);
4875 memcpy (condname
+ len
, ".c", 2);
4878 return lookup_mnemonic (base
, len
);
4884 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4885 to a corresponding operand qualifier. */
4887 static inline aarch64_opnd_qualifier_t
4888 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4890 /* Element size in bytes indexed by vector_el_type. */
4891 const unsigned char ele_size
[5]
4893 const unsigned int ele_base
[5] =
4895 AARCH64_OPND_QLF_V_8B
,
4896 AARCH64_OPND_QLF_V_2H
,
4897 AARCH64_OPND_QLF_V_2S
,
4898 AARCH64_OPND_QLF_V_1D
,
4899 AARCH64_OPND_QLF_V_1Q
4902 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4903 goto vectype_conversion_fail
;
4905 if (vectype
->type
== NT_zero
)
4906 return AARCH64_OPND_QLF_P_Z
;
4907 if (vectype
->type
== NT_merge
)
4908 return AARCH64_OPND_QLF_P_M
;
4910 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4912 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
4913 /* Vector element register. */
4914 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4917 /* Vector register. */
4918 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4921 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4922 goto vectype_conversion_fail
;
4924 /* The conversion is by calculating the offset from the base operand
4925 qualifier for the vector type. The operand qualifiers are regular
4926 enough that the offset can established by shifting the vector width by
4927 a vector-type dependent amount. */
4929 if (vectype
->type
== NT_b
)
4931 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4933 else if (vectype
->type
>= NT_d
)
4938 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4939 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4940 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4944 vectype_conversion_fail
:
4945 first_error (_("bad vector arrangement type"));
4946 return AARCH64_OPND_QLF_NIL
;
4949 /* Process an optional operand that is found omitted from the assembly line.
4950 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4951 instruction's opcode entry while IDX is the index of this omitted operand.
4955 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4956 int idx
, aarch64_opnd_info
*operand
)
4958 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4959 gas_assert (optional_operand_p (opcode
, idx
));
4960 gas_assert (!operand
->present
);
4964 case AARCH64_OPND_Rd
:
4965 case AARCH64_OPND_Rn
:
4966 case AARCH64_OPND_Rm
:
4967 case AARCH64_OPND_Rt
:
4968 case AARCH64_OPND_Rt2
:
4969 case AARCH64_OPND_Rs
:
4970 case AARCH64_OPND_Ra
:
4971 case AARCH64_OPND_Rt_SYS
:
4972 case AARCH64_OPND_Rd_SP
:
4973 case AARCH64_OPND_Rn_SP
:
4974 case AARCH64_OPND_Fd
:
4975 case AARCH64_OPND_Fn
:
4976 case AARCH64_OPND_Fm
:
4977 case AARCH64_OPND_Fa
:
4978 case AARCH64_OPND_Ft
:
4979 case AARCH64_OPND_Ft2
:
4980 case AARCH64_OPND_Sd
:
4981 case AARCH64_OPND_Sn
:
4982 case AARCH64_OPND_Sm
:
4983 case AARCH64_OPND_Vd
:
4984 case AARCH64_OPND_Vn
:
4985 case AARCH64_OPND_Vm
:
4986 case AARCH64_OPND_VdD1
:
4987 case AARCH64_OPND_VnD1
:
4988 operand
->reg
.regno
= default_value
;
4991 case AARCH64_OPND_Ed
:
4992 case AARCH64_OPND_En
:
4993 case AARCH64_OPND_Em
:
4994 operand
->reglane
.regno
= default_value
;
4997 case AARCH64_OPND_IDX
:
4998 case AARCH64_OPND_BIT_NUM
:
4999 case AARCH64_OPND_IMMR
:
5000 case AARCH64_OPND_IMMS
:
5001 case AARCH64_OPND_SHLL_IMM
:
5002 case AARCH64_OPND_IMM_VLSL
:
5003 case AARCH64_OPND_IMM_VLSR
:
5004 case AARCH64_OPND_CCMP_IMM
:
5005 case AARCH64_OPND_FBITS
:
5006 case AARCH64_OPND_UIMM4
:
5007 case AARCH64_OPND_UIMM3_OP1
:
5008 case AARCH64_OPND_UIMM3_OP2
:
5009 case AARCH64_OPND_IMM
:
5010 case AARCH64_OPND_WIDTH
:
5011 case AARCH64_OPND_UIMM7
:
5012 case AARCH64_OPND_NZCV
:
5013 case AARCH64_OPND_SVE_PATTERN
:
5014 case AARCH64_OPND_SVE_PRFOP
:
5015 operand
->imm
.value
= default_value
;
5018 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5019 operand
->imm
.value
= default_value
;
5020 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5021 operand
->shifter
.amount
= 1;
5024 case AARCH64_OPND_EXCEPTION
:
5025 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5028 case AARCH64_OPND_BARRIER_ISB
:
5029 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5036 /* Process the relocation type for move wide instructions.
5037 Return TRUE on success; otherwise return FALSE. */
5040 process_movw_reloc_info (void)
5045 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5047 if (inst
.base
.opcode
->op
== OP_MOVK
)
5048 switch (inst
.reloc
.type
)
5050 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5051 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5052 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5053 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5054 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5055 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5056 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5058 (_("the specified relocation type is not allowed for MOVK"));
5064 switch (inst
.reloc
.type
)
5066 case BFD_RELOC_AARCH64_MOVW_G0
:
5067 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5068 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5069 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5070 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5071 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5072 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5073 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5074 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5075 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5076 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5079 case BFD_RELOC_AARCH64_MOVW_G1
:
5080 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5081 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5082 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5083 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5084 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5085 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5086 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5087 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5088 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5089 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5092 case BFD_RELOC_AARCH64_MOVW_G2
:
5093 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5094 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5095 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5096 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5099 set_fatal_syntax_error
5100 (_("the specified relocation type is not allowed for 32-bit "
5106 case BFD_RELOC_AARCH64_MOVW_G3
:
5109 set_fatal_syntax_error
5110 (_("the specified relocation type is not allowed for 32-bit "
5117 /* More cases should be added when more MOVW-related relocation types
5118 are supported in GAS. */
5119 gas_assert (aarch64_gas_internal_fixup_p ());
5120 /* The shift amount should have already been set by the parser. */
5123 inst
.base
.operands
[1].shifter
.amount
= shift
;
5127 /* A primitive log caculator. */
5129 static inline unsigned int
5130 get_logsz (unsigned int size
)
5132 const unsigned char ls
[16] =
5133 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5139 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5140 return ls
[size
- 1];
5143 /* Determine and return the real reloc type code for an instruction
5144 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5146 static inline bfd_reloc_code_real_type
5147 ldst_lo12_determine_real_reloc_type (void)
5150 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5151 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5153 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
5155 BFD_RELOC_AARCH64_LDST8_LO12
,
5156 BFD_RELOC_AARCH64_LDST16_LO12
,
5157 BFD_RELOC_AARCH64_LDST32_LO12
,
5158 BFD_RELOC_AARCH64_LDST64_LO12
,
5159 BFD_RELOC_AARCH64_LDST128_LO12
5162 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5163 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5164 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5165 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5166 BFD_RELOC_AARCH64_NONE
5169 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5170 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5171 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5172 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5173 BFD_RELOC_AARCH64_NONE
5177 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5178 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5180 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
5181 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5183 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5185 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5187 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5189 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5190 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5191 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5192 gas_assert (logsz
<= 3);
5194 gas_assert (logsz
<= 4);
5196 /* In reloc.c, these pseudo relocation types should be defined in similar
5197 order as above reloc_ldst_lo12 array. Because the array index calcuation
5198 below relies on this. */
5199 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5202 /* Check whether a register list REGINFO is valid. The registers must be
5203 numbered in increasing order (modulo 32), in increments of one or two.
5205 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5208 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5211 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5213 uint32_t i
, nb_regs
, prev_regno
, incr
;
5215 nb_regs
= 1 + (reginfo
& 0x3);
5217 prev_regno
= reginfo
& 0x1f;
5218 incr
= accept_alternate
? 2 : 1;
5220 for (i
= 1; i
< nb_regs
; ++i
)
5222 uint32_t curr_regno
;
5224 curr_regno
= reginfo
& 0x1f;
5225 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5227 prev_regno
= curr_regno
;
5233 /* Generic instruction operand parser. This does no encoding and no
5234 semantic validation; it merely squirrels values away in the inst
5235 structure. Returns TRUE or FALSE depending on whether the
5236 specified grammar matched. */
5239 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5242 char *backtrack_pos
= 0;
5243 const enum aarch64_opnd
*operands
= opcode
->operands
;
5244 aarch64_reg_type imm_reg_type
;
5247 skip_whitespace (str
);
5249 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5251 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5254 const reg_entry
*reg
;
5255 int comma_skipped_p
= 0;
5256 aarch64_reg_type rtype
;
5257 struct vector_type_el vectype
;
5258 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5259 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5260 aarch64_reg_type reg_type
;
5262 DEBUG_TRACE ("parse operand %d", i
);
5264 /* Assign the operand code. */
5265 info
->type
= operands
[i
];
5267 if (optional_operand_p (opcode
, i
))
5269 /* Remember where we are in case we need to backtrack. */
5270 gas_assert (!backtrack_pos
);
5271 backtrack_pos
= str
;
5274 /* Expect comma between operands; the backtrack mechanizm will take
5275 care of cases of omitted optional operand. */
5276 if (i
> 0 && ! skip_past_char (&str
, ','))
5278 set_syntax_error (_("comma expected between operands"));
5282 comma_skipped_p
= 1;
5284 switch (operands
[i
])
5286 case AARCH64_OPND_Rd
:
5287 case AARCH64_OPND_Rn
:
5288 case AARCH64_OPND_Rm
:
5289 case AARCH64_OPND_Rt
:
5290 case AARCH64_OPND_Rt2
:
5291 case AARCH64_OPND_Rs
:
5292 case AARCH64_OPND_Ra
:
5293 case AARCH64_OPND_Rt_SYS
:
5294 case AARCH64_OPND_PAIRREG
:
5295 po_int_reg_or_fail (REG_TYPE_R_Z
);
5298 case AARCH64_OPND_Rd_SP
:
5299 case AARCH64_OPND_Rn_SP
:
5300 po_int_reg_or_fail (REG_TYPE_R_SP
);
5303 case AARCH64_OPND_Rm_EXT
:
5304 case AARCH64_OPND_Rm_SFT
:
5305 po_misc_or_fail (parse_shifter_operand
5306 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5308 : SHIFTED_LOGIC_IMM
)));
5309 if (!info
->shifter
.operator_present
)
5311 /* Default to LSL if not present. Libopcodes prefers shifter
5312 kind to be explicit. */
5313 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5314 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5315 /* For Rm_EXT, libopcodes will carry out further check on whether
5316 or not stack pointer is used in the instruction (Recall that
5317 "the extend operator is not optional unless at least one of
5318 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5322 case AARCH64_OPND_Fd
:
5323 case AARCH64_OPND_Fn
:
5324 case AARCH64_OPND_Fm
:
5325 case AARCH64_OPND_Fa
:
5326 case AARCH64_OPND_Ft
:
5327 case AARCH64_OPND_Ft2
:
5328 case AARCH64_OPND_Sd
:
5329 case AARCH64_OPND_Sn
:
5330 case AARCH64_OPND_Sm
:
5331 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5332 if (val
== PARSE_FAIL
)
5334 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5337 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5339 info
->reg
.regno
= val
;
5340 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5343 case AARCH64_OPND_SVE_Pd
:
5344 case AARCH64_OPND_SVE_Pg3
:
5345 case AARCH64_OPND_SVE_Pg4_5
:
5346 case AARCH64_OPND_SVE_Pg4_10
:
5347 case AARCH64_OPND_SVE_Pg4_16
:
5348 case AARCH64_OPND_SVE_Pm
:
5349 case AARCH64_OPND_SVE_Pn
:
5350 case AARCH64_OPND_SVE_Pt
:
5351 reg_type
= REG_TYPE_PN
;
5354 case AARCH64_OPND_SVE_Za_5
:
5355 case AARCH64_OPND_SVE_Za_16
:
5356 case AARCH64_OPND_SVE_Zd
:
5357 case AARCH64_OPND_SVE_Zm_5
:
5358 case AARCH64_OPND_SVE_Zm_16
:
5359 case AARCH64_OPND_SVE_Zn
:
5360 case AARCH64_OPND_SVE_Zt
:
5361 reg_type
= REG_TYPE_ZN
;
5364 case AARCH64_OPND_Vd
:
5365 case AARCH64_OPND_Vn
:
5366 case AARCH64_OPND_Vm
:
5367 reg_type
= REG_TYPE_VN
;
5369 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5370 if (val
== PARSE_FAIL
)
5372 first_error (_(get_reg_expected_msg (reg_type
)));
5375 if (vectype
.defined
& NTA_HASINDEX
)
5378 info
->reg
.regno
= val
;
5379 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5380 && vectype
.type
== NT_invtype
)
5381 /* Unqualified Pn and Zn registers are allowed in certain
5382 contexts. Rely on F_STRICT qualifier checking to catch
5384 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5387 info
->qualifier
= vectype_to_qualifier (&vectype
);
5388 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5393 case AARCH64_OPND_VdD1
:
5394 case AARCH64_OPND_VnD1
:
5395 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5396 if (val
== PARSE_FAIL
)
5398 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5401 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5403 set_fatal_syntax_error
5404 (_("the top half of a 128-bit FP/SIMD register is expected"));
5407 info
->reg
.regno
= val
;
5408 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5409 here; it is correct for the purpose of encoding/decoding since
5410 only the register number is explicitly encoded in the related
5411 instructions, although this appears a bit hacky. */
5412 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5415 case AARCH64_OPND_SVE_Zn_INDEX
:
5416 reg_type
= REG_TYPE_ZN
;
5417 goto vector_reg_index
;
5419 case AARCH64_OPND_Ed
:
5420 case AARCH64_OPND_En
:
5421 case AARCH64_OPND_Em
:
5422 reg_type
= REG_TYPE_VN
;
5424 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5425 if (val
== PARSE_FAIL
)
5427 first_error (_(get_reg_expected_msg (reg_type
)));
5430 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5433 info
->reglane
.regno
= val
;
5434 info
->reglane
.index
= vectype
.index
;
5435 info
->qualifier
= vectype_to_qualifier (&vectype
);
5436 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5440 case AARCH64_OPND_SVE_ZnxN
:
5441 case AARCH64_OPND_SVE_ZtxN
:
5442 reg_type
= REG_TYPE_ZN
;
5443 goto vector_reg_list
;
5445 case AARCH64_OPND_LVn
:
5446 case AARCH64_OPND_LVt
:
5447 case AARCH64_OPND_LVt_AL
:
5448 case AARCH64_OPND_LEt
:
5449 reg_type
= REG_TYPE_VN
;
5451 if (reg_type
== REG_TYPE_ZN
5452 && get_opcode_dependent_value (opcode
) == 1
5455 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5456 if (val
== PARSE_FAIL
)
5458 first_error (_(get_reg_expected_msg (reg_type
)));
5461 info
->reglist
.first_regno
= val
;
5462 info
->reglist
.num_regs
= 1;
5466 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5467 if (val
== PARSE_FAIL
)
5469 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5471 set_fatal_syntax_error (_("invalid register list"));
5474 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5475 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5477 if (operands
[i
] == AARCH64_OPND_LEt
)
5479 if (!(vectype
.defined
& NTA_HASINDEX
))
5481 info
->reglist
.has_index
= 1;
5482 info
->reglist
.index
= vectype
.index
;
5486 if (vectype
.defined
& NTA_HASINDEX
)
5488 if (!(vectype
.defined
& NTA_HASTYPE
))
5490 if (reg_type
== REG_TYPE_ZN
)
5491 set_fatal_syntax_error (_("missing type suffix"));
5495 info
->qualifier
= vectype_to_qualifier (&vectype
);
5496 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5500 case AARCH64_OPND_Cn
:
5501 case AARCH64_OPND_Cm
:
5502 po_reg_or_fail (REG_TYPE_CN
);
5505 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5508 inst
.base
.operands
[i
].reg
.regno
= val
;
5511 case AARCH64_OPND_SHLL_IMM
:
5512 case AARCH64_OPND_IMM_VLSR
:
5513 po_imm_or_fail (1, 64);
5514 info
->imm
.value
= val
;
5517 case AARCH64_OPND_CCMP_IMM
:
5518 case AARCH64_OPND_SIMM5
:
5519 case AARCH64_OPND_FBITS
:
5520 case AARCH64_OPND_UIMM4
:
5521 case AARCH64_OPND_UIMM3_OP1
:
5522 case AARCH64_OPND_UIMM3_OP2
:
5523 case AARCH64_OPND_IMM_VLSL
:
5524 case AARCH64_OPND_IMM
:
5525 case AARCH64_OPND_WIDTH
:
5526 case AARCH64_OPND_SVE_INV_LIMM
:
5527 case AARCH64_OPND_SVE_LIMM
:
5528 case AARCH64_OPND_SVE_LIMM_MOV
:
5529 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5530 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5531 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5532 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5533 case AARCH64_OPND_SVE_SIMM5
:
5534 case AARCH64_OPND_SVE_SIMM5B
:
5535 case AARCH64_OPND_SVE_SIMM6
:
5536 case AARCH64_OPND_SVE_SIMM8
:
5537 case AARCH64_OPND_SVE_UIMM3
:
5538 case AARCH64_OPND_SVE_UIMM7
:
5539 case AARCH64_OPND_SVE_UIMM8
:
5540 case AARCH64_OPND_SVE_UIMM8_53
:
5541 po_imm_nc_or_fail ();
5542 info
->imm
.value
= val
;
5545 case AARCH64_OPND_SVE_AIMM
:
5546 case AARCH64_OPND_SVE_ASIMM
:
5547 po_imm_nc_or_fail ();
5548 info
->imm
.value
= val
;
5549 skip_whitespace (str
);
5550 if (skip_past_comma (&str
))
5551 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5553 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5556 case AARCH64_OPND_SVE_PATTERN
:
5557 po_enum_or_fail (aarch64_sve_pattern_array
);
5558 info
->imm
.value
= val
;
5561 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5562 po_enum_or_fail (aarch64_sve_pattern_array
);
5563 info
->imm
.value
= val
;
5564 if (skip_past_comma (&str
)
5565 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5567 if (!info
->shifter
.operator_present
)
5569 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5570 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5571 info
->shifter
.amount
= 1;
5575 case AARCH64_OPND_SVE_PRFOP
:
5576 po_enum_or_fail (aarch64_sve_prfop_array
);
5577 info
->imm
.value
= val
;
5580 case AARCH64_OPND_UIMM7
:
5581 po_imm_or_fail (0, 127);
5582 info
->imm
.value
= val
;
5585 case AARCH64_OPND_IDX
:
5586 case AARCH64_OPND_BIT_NUM
:
5587 case AARCH64_OPND_IMMR
:
5588 case AARCH64_OPND_IMMS
:
5589 po_imm_or_fail (0, 63);
5590 info
->imm
.value
= val
;
5593 case AARCH64_OPND_IMM0
:
5594 po_imm_nc_or_fail ();
5597 set_fatal_syntax_error (_("immediate zero expected"));
5600 info
->imm
.value
= 0;
5603 case AARCH64_OPND_FPIMM0
:
5606 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5607 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5608 it is probably not worth the effort to support it. */
5609 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5612 || !(res2
= parse_constant_immediate (&str
, &val
,
5615 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5617 info
->imm
.value
= 0;
5618 info
->imm
.is_fp
= 1;
5621 set_fatal_syntax_error (_("immediate zero expected"));
5625 case AARCH64_OPND_IMM_MOV
:
5628 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5629 reg_name_p (str
, REG_TYPE_VN
))
5632 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5634 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5635 later. fix_mov_imm_insn will try to determine a machine
5636 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5637 message if the immediate cannot be moved by a single
5639 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5640 inst
.base
.operands
[i
].skip
= 1;
5644 case AARCH64_OPND_SIMD_IMM
:
5645 case AARCH64_OPND_SIMD_IMM_SFT
:
5646 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5648 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5650 /* need_libopcodes_p */ 1,
5653 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5654 shift, we don't check it here; we leave the checking to
5655 the libopcodes (operand_general_constraint_met_p). By
5656 doing this, we achieve better diagnostics. */
5657 if (skip_past_comma (&str
)
5658 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5660 if (!info
->shifter
.operator_present
5661 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5663 /* Default to LSL if not present. Libopcodes prefers shifter
5664 kind to be explicit. */
5665 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5666 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5670 case AARCH64_OPND_FPIMM
:
5671 case AARCH64_OPND_SIMD_FPIMM
:
5672 case AARCH64_OPND_SVE_FPIMM8
:
5677 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5678 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5679 || !aarch64_imm_float_p (qfloat
))
5682 set_fatal_syntax_error (_("invalid floating-point"
5686 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5687 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5691 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5692 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5693 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5698 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5699 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5702 set_fatal_syntax_error (_("invalid floating-point"
5706 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5707 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5711 case AARCH64_OPND_LIMM
:
5712 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5713 SHIFTED_LOGIC_IMM
));
5714 if (info
->shifter
.operator_present
)
5716 set_fatal_syntax_error
5717 (_("shift not allowed for bitmask immediate"));
5720 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5722 /* need_libopcodes_p */ 1,
5726 case AARCH64_OPND_AIMM
:
5727 if (opcode
->op
== OP_ADD
)
5728 /* ADD may have relocation types. */
5729 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5730 SHIFTED_ARITH_IMM
));
5732 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5733 SHIFTED_ARITH_IMM
));
5734 switch (inst
.reloc
.type
)
5736 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5737 info
->shifter
.amount
= 12;
5739 case BFD_RELOC_UNUSED
:
5740 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5741 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5742 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5743 inst
.reloc
.pc_rel
= 0;
5748 info
->imm
.value
= 0;
5749 if (!info
->shifter
.operator_present
)
5751 /* Default to LSL if not present. Libopcodes prefers shifter
5752 kind to be explicit. */
5753 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5754 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5758 case AARCH64_OPND_HALF
:
5760 /* #<imm16> or relocation. */
5761 int internal_fixup_p
;
5762 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5763 if (internal_fixup_p
)
5764 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5765 skip_whitespace (str
);
5766 if (skip_past_comma (&str
))
5768 /* {, LSL #<shift>} */
5769 if (! aarch64_gas_internal_fixup_p ())
5771 set_fatal_syntax_error (_("can't mix relocation modifier "
5772 "with explicit shift"));
5775 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5778 inst
.base
.operands
[i
].shifter
.amount
= 0;
5779 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5780 inst
.base
.operands
[i
].imm
.value
= 0;
5781 if (! process_movw_reloc_info ())
5786 case AARCH64_OPND_EXCEPTION
:
5787 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5789 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5791 /* need_libopcodes_p */ 0,
5795 case AARCH64_OPND_NZCV
:
5797 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5801 info
->imm
.value
= nzcv
->value
;
5804 po_imm_or_fail (0, 15);
5805 info
->imm
.value
= val
;
5809 case AARCH64_OPND_COND
:
5810 case AARCH64_OPND_COND1
:
5811 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5813 if (info
->cond
== NULL
)
5815 set_syntax_error (_("invalid condition"));
5818 else if (operands
[i
] == AARCH64_OPND_COND1
5819 && (info
->cond
->value
& 0xe) == 0xe)
5821 /* Not allow AL or NV. */
5822 set_default_error ();
5827 case AARCH64_OPND_ADDR_ADRP
:
5828 po_misc_or_fail (parse_adrp (&str
));
5829 /* Clear the value as operand needs to be relocated. */
5830 info
->imm
.value
= 0;
5833 case AARCH64_OPND_ADDR_PCREL14
:
5834 case AARCH64_OPND_ADDR_PCREL19
:
5835 case AARCH64_OPND_ADDR_PCREL21
:
5836 case AARCH64_OPND_ADDR_PCREL26
:
5837 po_misc_or_fail (parse_address (&str
, info
));
5838 if (!info
->addr
.pcrel
)
5840 set_syntax_error (_("invalid pc-relative address"));
5843 if (inst
.gen_lit_pool
5844 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5846 /* Only permit "=value" in the literal load instructions.
5847 The literal will be generated by programmer_friendly_fixup. */
5848 set_syntax_error (_("invalid use of \"=immediate\""));
5851 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5853 set_syntax_error (_("unrecognized relocation suffix"));
5856 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5858 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5859 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5863 info
->imm
.value
= 0;
5864 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5865 switch (opcode
->iclass
)
5869 /* e.g. CBZ or B.COND */
5870 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5871 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5875 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5876 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5880 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5882 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5883 : BFD_RELOC_AARCH64_JUMP26
;
5886 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5887 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5890 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5891 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5897 inst
.reloc
.pc_rel
= 1;
5901 case AARCH64_OPND_ADDR_SIMPLE
:
5902 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5904 /* [<Xn|SP>{, #<simm>}] */
5906 /* First use the normal address-parsing routines, to get
5907 the usual syntax errors. */
5908 po_misc_or_fail (parse_address (&str
, info
));
5909 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5910 || !info
->addr
.preind
|| info
->addr
.postind
5911 || info
->addr
.writeback
)
5913 set_syntax_error (_("invalid addressing mode"));
5917 /* Then retry, matching the specific syntax of these addresses. */
5919 po_char_or_fail ('[');
5920 po_reg_or_fail (REG_TYPE_R64_SP
);
5921 /* Accept optional ", #0". */
5922 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5923 && skip_past_char (&str
, ','))
5925 skip_past_char (&str
, '#');
5926 if (! skip_past_char (&str
, '0'))
5928 set_fatal_syntax_error
5929 (_("the optional immediate offset can only be 0"));
5933 po_char_or_fail (']');
5937 case AARCH64_OPND_ADDR_REGOFF
:
5938 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5939 po_misc_or_fail (parse_address (&str
, info
));
5941 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5942 || !info
->addr
.preind
|| info
->addr
.postind
5943 || info
->addr
.writeback
)
5945 set_syntax_error (_("invalid addressing mode"));
5948 if (!info
->shifter
.operator_present
)
5950 /* Default to LSL if not present. Libopcodes prefers shifter
5951 kind to be explicit. */
5952 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5953 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5955 /* Qualifier to be deduced by libopcodes. */
5958 case AARCH64_OPND_ADDR_SIMM7
:
5959 po_misc_or_fail (parse_address (&str
, info
));
5960 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5961 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5963 set_syntax_error (_("invalid addressing mode"));
5966 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5968 set_syntax_error (_("relocation not allowed"));
5971 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5973 /* need_libopcodes_p */ 1,
5977 case AARCH64_OPND_ADDR_SIMM9
:
5978 case AARCH64_OPND_ADDR_SIMM9_2
:
5979 po_misc_or_fail (parse_address (&str
, info
));
5980 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5981 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5982 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5983 && info
->addr
.writeback
))
5985 set_syntax_error (_("invalid addressing mode"));
5988 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5990 set_syntax_error (_("relocation not allowed"));
5993 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5995 /* need_libopcodes_p */ 1,
5999 case AARCH64_OPND_ADDR_UIMM12
:
6000 po_misc_or_fail (parse_address (&str
, info
));
6001 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6002 || !info
->addr
.preind
|| info
->addr
.writeback
)
6004 set_syntax_error (_("invalid addressing mode"));
6007 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6008 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6009 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6011 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6013 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
6014 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6015 /* Leave qualifier to be determined by libopcodes. */
6018 case AARCH64_OPND_SIMD_ADDR_POST
:
6019 /* [<Xn|SP>], <Xm|#<amount>> */
6020 po_misc_or_fail (parse_address (&str
, info
));
6021 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6023 set_syntax_error (_("invalid addressing mode"));
6026 if (!info
->addr
.offset
.is_reg
)
6028 if (inst
.reloc
.exp
.X_op
== O_constant
)
6029 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6032 set_fatal_syntax_error
6033 (_("writeback value should be an immediate constant"));
6040 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6041 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6042 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6043 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6044 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6045 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6046 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6047 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6048 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6049 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6050 /* [X<n>{, #imm, MUL VL}]
6052 but recognizing SVE registers. */
6053 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6054 &offset_qualifier
));
6055 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6057 set_syntax_error (_("invalid addressing mode"));
6061 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6062 || !info
->addr
.preind
|| info
->addr
.writeback
)
6064 set_syntax_error (_("invalid addressing mode"));
6067 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6068 || inst
.reloc
.exp
.X_op
!= O_constant
)
6070 /* Make sure this has priority over
6071 "invalid addressing mode". */
6072 set_fatal_syntax_error (_("constant offset required"));
6075 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6078 case AARCH64_OPND_SVE_ADDR_RR
:
6079 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6080 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6081 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6082 case AARCH64_OPND_SVE_ADDR_RX
:
6083 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6084 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6085 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6086 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6087 but recognizing SVE registers. */
6088 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6089 &offset_qualifier
));
6090 if (base_qualifier
!= AARCH64_OPND_QLF_X
6091 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6093 set_syntax_error (_("invalid addressing mode"));
6098 case AARCH64_OPND_SVE_ADDR_RZ
:
6099 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6100 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6101 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6102 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6103 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6104 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6105 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6106 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6107 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6108 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6109 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6110 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6111 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6112 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6113 &offset_qualifier
));
6114 if (base_qualifier
!= AARCH64_OPND_QLF_X
6115 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6116 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6118 set_syntax_error (_("invalid addressing mode"));
6121 info
->qualifier
= offset_qualifier
;
6124 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6125 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6126 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6127 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6128 /* [Z<n>.<T>{, #imm}] */
6129 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6130 &offset_qualifier
));
6131 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6132 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6134 set_syntax_error (_("invalid addressing mode"));
6137 info
->qualifier
= base_qualifier
;
6140 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6141 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6142 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6143 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6144 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6148 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6150 here since we get better error messages by leaving it to
6151 the qualifier checking routines. */
6152 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6153 &offset_qualifier
));
6154 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6155 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6156 || offset_qualifier
!= base_qualifier
)
6158 set_syntax_error (_("invalid addressing mode"));
6161 info
->qualifier
= base_qualifier
;
6164 case AARCH64_OPND_SYSREG
:
6165 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
6168 set_syntax_error (_("unknown or missing system register name"));
6171 inst
.base
.operands
[i
].sysreg
= val
;
6174 case AARCH64_OPND_PSTATEFIELD
:
6175 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
6178 set_syntax_error (_("unknown or missing PSTATE field name"));
6181 inst
.base
.operands
[i
].pstatefield
= val
;
6184 case AARCH64_OPND_SYSREG_IC
:
6185 inst
.base
.operands
[i
].sysins_op
=
6186 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6188 case AARCH64_OPND_SYSREG_DC
:
6189 inst
.base
.operands
[i
].sysins_op
=
6190 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6192 case AARCH64_OPND_SYSREG_AT
:
6193 inst
.base
.operands
[i
].sysins_op
=
6194 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6196 case AARCH64_OPND_SYSREG_TLBI
:
6197 inst
.base
.operands
[i
].sysins_op
=
6198 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6200 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6202 set_fatal_syntax_error ( _("unknown or missing operation name"));
6207 case AARCH64_OPND_BARRIER
:
6208 case AARCH64_OPND_BARRIER_ISB
:
6209 val
= parse_barrier (&str
);
6210 if (val
!= PARSE_FAIL
6211 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6213 /* ISB only accepts options name 'sy'. */
6215 (_("the specified option is not accepted in ISB"));
6216 /* Turn off backtrack as this optional operand is present. */
6220 /* This is an extension to accept a 0..15 immediate. */
6221 if (val
== PARSE_FAIL
)
6222 po_imm_or_fail (0, 15);
6223 info
->barrier
= aarch64_barrier_options
+ val
;
6226 case AARCH64_OPND_PRFOP
:
6227 val
= parse_pldop (&str
);
6228 /* This is an extension to accept a 0..31 immediate. */
6229 if (val
== PARSE_FAIL
)
6230 po_imm_or_fail (0, 31);
6231 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6234 case AARCH64_OPND_BARRIER_PSB
:
6235 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6236 if (val
== PARSE_FAIL
)
6241 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6244 /* If we get here, this operand was successfully parsed. */
6245 inst
.base
.operands
[i
].present
= 1;
6249 /* The parse routine should already have set the error, but in case
6250 not, set a default one here. */
6252 set_default_error ();
6254 if (! backtrack_pos
)
6255 goto parse_operands_return
;
6258 /* We reach here because this operand is marked as optional, and
6259 either no operand was supplied or the operand was supplied but it
6260 was syntactically incorrect. In the latter case we report an
6261 error. In the former case we perform a few more checks before
6262 dropping through to the code to insert the default operand. */
6264 char *tmp
= backtrack_pos
;
6265 char endchar
= END_OF_INSN
;
6267 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6269 skip_past_char (&tmp
, ',');
6271 if (*tmp
!= endchar
)
6272 /* The user has supplied an operand in the wrong format. */
6273 goto parse_operands_return
;
6275 /* Make sure there is not a comma before the optional operand.
6276 For example the fifth operand of 'sys' is optional:
6278 sys #0,c0,c0,#0, <--- wrong
6279 sys #0,c0,c0,#0 <--- correct. */
6280 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6282 set_fatal_syntax_error
6283 (_("unexpected comma before the omitted optional operand"));
6284 goto parse_operands_return
;
6288 /* Reaching here means we are dealing with an optional operand that is
6289 omitted from the assembly line. */
6290 gas_assert (optional_operand_p (opcode
, i
));
6292 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6294 /* Try again, skipping the optional operand at backtrack_pos. */
6295 str
= backtrack_pos
;
6298 /* Clear any error record after the omitted optional operand has been
6299 successfully handled. */
6303 /* Check if we have parsed all the operands. */
6304 if (*str
!= '\0' && ! error_p ())
6306 /* Set I to the index of the last present operand; this is
6307 for the purpose of diagnostics. */
6308 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6310 set_fatal_syntax_error
6311 (_("unexpected characters following instruction"));
6314 parse_operands_return
:
6318 DEBUG_TRACE ("parsing FAIL: %s - %s",
6319 operand_mismatch_kind_names
[get_error_kind ()],
6320 get_error_message ());
6321 /* Record the operand error properly; this is useful when there
6322 are multiple instruction templates for a mnemonic name, so that
6323 later on, we can select the error that most closely describes
6325 record_operand_error (opcode
, i
, get_error_kind (),
6326 get_error_message ());
6331 DEBUG_TRACE ("parsing SUCCESS");
6336 /* It does some fix-up to provide some programmer friendly feature while
6337 keeping the libopcodes happy, i.e. libopcodes only accepts
6338 the preferred architectural syntax.
6339 Return FALSE if there is any failure; otherwise return TRUE. */
6342 programmer_friendly_fixup (aarch64_instruction
*instr
)
6344 aarch64_inst
*base
= &instr
->base
;
6345 const aarch64_opcode
*opcode
= base
->opcode
;
6346 enum aarch64_op op
= opcode
->op
;
6347 aarch64_opnd_info
*operands
= base
->operands
;
6349 DEBUG_TRACE ("enter");
6351 switch (opcode
->iclass
)
6354 /* TBNZ Xn|Wn, #uimm6, label
6355 Test and Branch Not Zero: conditionally jumps to label if bit number
6356 uimm6 in register Xn is not zero. The bit number implies the width of
6357 the register, which may be written and should be disassembled as Wn if
6358 uimm is less than 32. */
6359 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6361 if (operands
[1].imm
.value
>= 32)
6363 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6367 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6371 /* LDR Wt, label | =value
6372 As a convenience assemblers will typically permit the notation
6373 "=value" in conjunction with the pc-relative literal load instructions
6374 to automatically place an immediate value or symbolic address in a
6375 nearby literal pool and generate a hidden label which references it.
6376 ISREG has been set to 0 in the case of =value. */
6377 if (instr
->gen_lit_pool
6378 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6380 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6381 if (op
== OP_LDRSW_LIT
)
6383 if (instr
->reloc
.exp
.X_op
!= O_constant
6384 && instr
->reloc
.exp
.X_op
!= O_big
6385 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6387 record_operand_error (opcode
, 1,
6388 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6389 _("constant expression expected"));
6392 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6394 record_operand_error (opcode
, 1,
6395 AARCH64_OPDE_OTHER_ERROR
,
6396 _("literal pool insertion failed"));
6404 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6405 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6406 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6407 A programmer-friendly assembler should accept a destination Xd in
6408 place of Wd, however that is not the preferred form for disassembly.
6410 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6411 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6412 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6413 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6418 /* In the 64-bit form, the final register operand is written as Wm
6419 for all but the (possibly omitted) UXTX/LSL and SXTX
6421 As a programmer-friendly assembler, we accept e.g.
6422 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6423 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6424 int idx
= aarch64_operand_index (opcode
->operands
,
6425 AARCH64_OPND_Rm_EXT
);
6426 gas_assert (idx
== 1 || idx
== 2);
6427 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6428 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6429 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6430 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6431 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6432 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6440 DEBUG_TRACE ("exit with SUCCESS");
6444 /* Check for loads and stores that will cause unpredictable behavior. */
6447 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6449 aarch64_inst
*base
= &instr
->base
;
6450 const aarch64_opcode
*opcode
= base
->opcode
;
6451 const aarch64_opnd_info
*opnds
= base
->operands
;
6452 switch (opcode
->iclass
)
6458 /* Loading/storing the base register is unpredictable if writeback. */
6459 if ((aarch64_get_operand_class (opnds
[0].type
)
6460 == AARCH64_OPND_CLASS_INT_REG
)
6461 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6462 && opnds
[1].addr
.base_regno
!= REG_SP
6463 && opnds
[1].addr
.writeback
)
6464 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6467 case ldstnapair_offs
:
6468 case ldstpair_indexed
:
6469 /* Loading/storing the base register is unpredictable if writeback. */
6470 if ((aarch64_get_operand_class (opnds
[0].type
)
6471 == AARCH64_OPND_CLASS_INT_REG
)
6472 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6473 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6474 && opnds
[2].addr
.base_regno
!= REG_SP
6475 && opnds
[2].addr
.writeback
)
6476 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6477 /* Load operations must load different registers. */
6478 if ((opcode
->opcode
& (1 << 22))
6479 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6480 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6487 /* A wrapper function to interface with libopcodes on encoding and
6488 record the error message if there is any.
6490 Return TRUE on success; otherwise return FALSE. */
6493 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6496 aarch64_operand_error error_info
;
6497 error_info
.kind
= AARCH64_OPDE_NIL
;
6498 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
6502 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6503 record_operand_error_info (opcode
, &error_info
);
6508 #ifdef DEBUG_AARCH64
6510 dump_opcode_operands (const aarch64_opcode
*opcode
)
6513 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6515 aarch64_verbose ("\t\t opnd%d: %s", i
,
6516 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6517 ? aarch64_get_operand_name (opcode
->operands
[i
])
6518 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6522 #endif /* DEBUG_AARCH64 */
6524 /* This is the guts of the machine-dependent assembler. STR points to a
6525 machine dependent instruction. This function is supposed to emit
6526 the frags/bytes it assembles to. */
6529 md_assemble (char *str
)
6532 templates
*template;
6533 aarch64_opcode
*opcode
;
6534 aarch64_inst
*inst_base
;
6535 unsigned saved_cond
;
6537 /* Align the previous label if needed. */
6538 if (last_label_seen
!= NULL
)
6540 symbol_set_frag (last_label_seen
, frag_now
);
6541 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6542 S_SET_SEGMENT (last_label_seen
, now_seg
);
6545 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6547 DEBUG_TRACE ("\n\n");
6548 DEBUG_TRACE ("==============================");
6549 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6551 template = opcode_lookup (&p
);
6554 /* It wasn't an instruction, but it might be a register alias of
6555 the form alias .req reg directive. */
6556 if (!create_register_alias (str
, p
))
6557 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6562 skip_whitespace (p
);
6565 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6566 get_mnemonic_name (str
), str
);
6570 init_operand_error_report ();
6572 /* Sections are assumed to start aligned. In executable section, there is no
6573 MAP_DATA symbol pending. So we only align the address during
6574 MAP_DATA --> MAP_INSN transition.
6575 For other sections, this is not guaranteed. */
6576 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6577 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6578 frag_align_code (2, 0);
6580 saved_cond
= inst
.cond
;
6581 reset_aarch64_instruction (&inst
);
6582 inst
.cond
= saved_cond
;
6584 /* Iterate through all opcode entries with the same mnemonic name. */
6587 opcode
= template->opcode
;
6589 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6590 #ifdef DEBUG_AARCH64
6592 dump_opcode_operands (opcode
);
6593 #endif /* DEBUG_AARCH64 */
6595 mapping_state (MAP_INSN
);
6597 inst_base
= &inst
.base
;
6598 inst_base
->opcode
= opcode
;
6600 /* Truly conditionally executed instructions, e.g. b.cond. */
6601 if (opcode
->flags
& F_COND
)
6603 gas_assert (inst
.cond
!= COND_ALWAYS
);
6604 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6605 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6607 else if (inst
.cond
!= COND_ALWAYS
)
6609 /* It shouldn't arrive here, where the assembly looks like a
6610 conditional instruction but the found opcode is unconditional. */
6615 if (parse_operands (p
, opcode
)
6616 && programmer_friendly_fixup (&inst
)
6617 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6619 /* Check that this instruction is supported for this CPU. */
6620 if (!opcode
->avariant
6621 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6623 as_bad (_("selected processor does not support `%s'"), str
);
6627 warn_unpredictable_ldst (&inst
, str
);
6629 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6630 || !inst
.reloc
.need_libopcodes_p
)
6634 /* If there is relocation generated for the instruction,
6635 store the instruction information for the future fix-up. */
6636 struct aarch64_inst
*copy
;
6637 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6638 copy
= XNEW (struct aarch64_inst
);
6639 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6645 template = template->next
;
6646 if (template != NULL
)
6648 reset_aarch64_instruction (&inst
);
6649 inst
.cond
= saved_cond
;
6652 while (template != NULL
);
6654 /* Issue the error messages if any. */
6655 output_operand_error_report (str
);
6658 /* Various frobbings of labels and their addresses. */
6661 aarch64_start_line_hook (void)
6663 last_label_seen
= NULL
;
6667 aarch64_frob_label (symbolS
* sym
)
6669 last_label_seen
= sym
;
6671 dwarf2_emit_label (sym
);
6675 aarch64_data_in_code (void)
6677 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6679 *input_line_pointer
= '/';
6680 input_line_pointer
+= 5;
6681 *input_line_pointer
= 0;
6689 aarch64_canonicalize_symbol_name (char *name
)
6693 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6694 *(name
+ len
- 5) = 0;
6699 /* Table of all register names defined by default. The user can
6700 define additional names with .req. Note that all register names
6701 should appear in both upper and lowercase variants. Some registers
6702 also have mixed-case names. */
6704 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6705 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6706 #define REGSET16(p,t) \
6707 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6708 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6709 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6710 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6711 #define REGSET31(p,t) \
6713 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6714 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6715 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6716 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6717 #define REGSET(p,t) \
6718 REGSET31(p,t), REGNUM(p,31,t)
6720 /* These go into aarch64_reg_hsh hash-table. */
6721 static const reg_entry reg_names
[] = {
6722 /* Integer registers. */
6723 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6724 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6726 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6727 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6729 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6730 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6732 /* Coprocessor register numbers. */
6733 REGSET (c
, CN
), REGSET (C
, CN
),
6735 /* Floating-point single precision registers. */
6736 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6738 /* Floating-point double precision registers. */
6739 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6741 /* Floating-point half precision registers. */
6742 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6744 /* Floating-point byte precision registers. */
6745 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6747 /* Floating-point quad precision registers. */
6748 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6750 /* FP/SIMD registers. */
6751 REGSET (v
, VN
), REGSET (V
, VN
),
6753 /* SVE vector registers. */
6754 REGSET (z
, ZN
), REGSET (Z
, ZN
),
6756 /* SVE predicate registers. */
6757 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
6774 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6775 static const asm_nzcv nzcv_names
[] = {
6776 {"nzcv", B (n
, z
, c
, v
)},
6777 {"nzcV", B (n
, z
, c
, V
)},
6778 {"nzCv", B (n
, z
, C
, v
)},
6779 {"nzCV", B (n
, z
, C
, V
)},
6780 {"nZcv", B (n
, Z
, c
, v
)},
6781 {"nZcV", B (n
, Z
, c
, V
)},
6782 {"nZCv", B (n
, Z
, C
, v
)},
6783 {"nZCV", B (n
, Z
, C
, V
)},
6784 {"Nzcv", B (N
, z
, c
, v
)},
6785 {"NzcV", B (N
, z
, c
, V
)},
6786 {"NzCv", B (N
, z
, C
, v
)},
6787 {"NzCV", B (N
, z
, C
, V
)},
6788 {"NZcv", B (N
, Z
, c
, v
)},
6789 {"NZcV", B (N
, Z
, c
, V
)},
6790 {"NZCv", B (N
, Z
, C
, v
)},
6791 {"NZCV", B (N
, Z
, C
, V
)}
6804 /* MD interface: bits in the object file. */
6806 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6807 for use in the a.out file, and stores them in the array pointed to by buf.
6808 This knows about the endian-ness of the target machine and does
6809 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6810 2 (short) and 4 (long) Floating numbers are put out as a series of
6811 LITTLENUMS (shorts, here at least). */
6814 md_number_to_chars (char *buf
, valueT val
, int n
)
6816 if (target_big_endian
)
6817 number_to_chars_bigendian (buf
, val
, n
);
6819 number_to_chars_littleendian (buf
, val
, n
);
6822 /* MD interface: Sections. */
6824 /* Estimate the size of a frag before relaxing. Assume everything fits in
6828 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6834 /* Round up a section size to the appropriate boundary. */
6837 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6842 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6843 of an rs_align_code fragment.
6845 Here we fill the frag with the appropriate info for padding the
6846 output stream. The resulting frag will consist of a fixed (fr_fix)
6847 and of a repeating (fr_var) part.
6849 The fixed content is always emitted before the repeating content and
6850 these two parts are used as follows in constructing the output:
6851 - the fixed part will be used to align to a valid instruction word
6852 boundary, in case that we start at a misaligned address; as no
6853 executable instruction can live at the misaligned location, we
6854 simply fill with zeros;
6855 - the variable part will be used to cover the remaining padding and
6856 we fill using the AArch64 NOP instruction.
6858 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6859 enough storage space for up to 3 bytes for padding the back to a valid
6860 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6863 aarch64_handle_align (fragS
* fragP
)
6865 /* NOP = d503201f */
6866 /* AArch64 instructions are always little-endian. */
6867 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6869 int bytes
, fix
, noop_size
;
6872 if (fragP
->fr_type
!= rs_align_code
)
6875 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6876 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6879 gas_assert (fragP
->tc_frag_data
.recorded
);
6882 noop_size
= sizeof (aarch64_noop
);
6884 fix
= bytes
& (noop_size
- 1);
6888 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6892 fragP
->fr_fix
+= fix
;
6896 memcpy (p
, aarch64_noop
, noop_size
);
6897 fragP
->fr_var
= noop_size
;
6900 /* Perform target specific initialisation of a frag.
6901 Note - despite the name this initialisation is not done when the frag
6902 is created, but only when its type is assigned. A frag can be created
6903 and used a long time before its type is set, so beware of assuming that
6904 this initialisationis performed first. */
6908 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6909 int max_chars ATTRIBUTE_UNUSED
)
6913 #else /* OBJ_ELF is defined. */
6915 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6917 /* Record a mapping symbol for alignment frags. We will delete this
6918 later if the alignment ends up empty. */
6919 if (!fragP
->tc_frag_data
.recorded
)
6920 fragP
->tc_frag_data
.recorded
= 1;
6922 switch (fragP
->fr_type
)
6926 mapping_state_2 (MAP_DATA
, max_chars
);
6929 /* PR 20364: We can get alignment frags in code sections,
6930 so do not just assume that we should use the MAP_DATA state. */
6931 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
6934 mapping_state_2 (MAP_INSN
, max_chars
);
6941 /* Initialize the DWARF-2 unwind information for this procedure. */
6944 tc_aarch64_frame_initial_instructions (void)
6946 cfi_add_CFA_def_cfa (REG_SP
, 0);
6948 #endif /* OBJ_ELF */
6950 /* Convert REGNAME to a DWARF-2 register number. */
6953 tc_aarch64_regname_to_dw2regnum (char *regname
)
6955 const reg_entry
*reg
= parse_reg (®name
);
6961 case REG_TYPE_SP_32
:
6962 case REG_TYPE_SP_64
:
6972 return reg
->number
+ 64;
6980 /* Implement DWARF2_ADDR_SIZE. */
6983 aarch64_dwarf2_addr_size (void)
6985 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6989 return bfd_arch_bits_per_address (stdoutput
) / 8;
6992 /* MD interface: Symbol and relocation handling. */
6994 /* Return the address within the segment that a PC-relative fixup is
6995 relative to. For AArch64 PC-relative fixups applied to instructions
6996 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6999 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7001 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7003 /* If this is pc-relative and we are going to emit a relocation
7004 then we just want to put out any pipeline compensation that the linker
7005 will need. Otherwise we want to use the calculated base. */
7007 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7008 || aarch64_force_relocation (fixP
)))
7011 /* AArch64 should be consistent for all pc-relative relocations. */
7012 return base
+ AARCH64_PCREL_OFFSET
;
7015 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7016 Otherwise we have no need to default values of symbols. */
7019 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7022 if (name
[0] == '_' && name
[1] == 'G'
7023 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7027 if (symbol_find (name
))
7028 as_bad (_("GOT already in the symbol table"));
7030 GOT_symbol
= symbol_new (name
, undefined_section
,
7031 (valueT
) 0, &zero_address_frag
);
7041 /* Return non-zero if the indicated VALUE has overflowed the maximum
7042 range expressible by a unsigned number with the indicated number of
7046 unsigned_overflow (valueT value
, unsigned bits
)
7049 if (bits
>= sizeof (valueT
) * 8)
7051 lim
= (valueT
) 1 << bits
;
7052 return (value
>= lim
);
7056 /* Return non-zero if the indicated VALUE has overflowed the maximum
7057 range expressible by an signed number with the indicated number of
7061 signed_overflow (offsetT value
, unsigned bits
)
7064 if (bits
>= sizeof (offsetT
) * 8)
7066 lim
= (offsetT
) 1 << (bits
- 1);
7067 return (value
< -lim
|| value
>= lim
);
7070 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7071 unsigned immediate offset load/store instruction, try to encode it as
7072 an unscaled, 9-bit, signed immediate offset load/store instruction.
7073 Return TRUE if it is successful; otherwise return FALSE.
7075 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7076 in response to the standard LDR/STR mnemonics when the immediate offset is
7077 unambiguous, i.e. when it is negative or unaligned. */
7080 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7083 enum aarch64_op new_op
;
7084 const aarch64_opcode
*new_opcode
;
7086 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7088 switch (instr
->opcode
->op
)
7090 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7091 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7092 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7093 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7094 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7095 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7096 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7097 case OP_STR_POS
: new_op
= OP_STUR
; break;
7098 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7099 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7100 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7101 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7102 default: new_op
= OP_NIL
; break;
7105 if (new_op
== OP_NIL
)
7108 new_opcode
= aarch64_get_opcode (new_op
);
7109 gas_assert (new_opcode
!= NULL
);
7111 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7112 instr
->opcode
->op
, new_opcode
->op
);
7114 aarch64_replace_opcode (instr
, new_opcode
);
7116 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7117 qualifier matching may fail because the out-of-date qualifier will
7118 prevent the operand being updated with a new and correct qualifier. */
7119 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7120 AARCH64_OPND_ADDR_SIMM9
);
7121 gas_assert (idx
== 1);
7122 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7124 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7126 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
7132 /* Called by fix_insn to fix a MOV immediate alias instruction.
7134 Operand for a generic move immediate instruction, which is an alias
7135 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7136 a 32-bit/64-bit immediate value into general register. An assembler error
7137 shall result if the immediate cannot be created by a single one of these
7138 instructions. If there is a choice, then to ensure reversability an
7139 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7142 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7144 const aarch64_opcode
*opcode
;
7146 /* Need to check if the destination is SP/ZR. The check has to be done
7147 before any aarch64_replace_opcode. */
7148 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7149 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7151 instr
->operands
[1].imm
.value
= value
;
7152 instr
->operands
[1].skip
= 0;
7156 /* Try the MOVZ alias. */
7157 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7158 aarch64_replace_opcode (instr
, opcode
);
7159 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7160 &instr
->value
, NULL
, NULL
))
7162 put_aarch64_insn (buf
, instr
->value
);
7165 /* Try the MOVK alias. */
7166 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7167 aarch64_replace_opcode (instr
, opcode
);
7168 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7169 &instr
->value
, NULL
, NULL
))
7171 put_aarch64_insn (buf
, instr
->value
);
7176 if (try_mov_bitmask_p
)
7178 /* Try the ORR alias. */
7179 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7180 aarch64_replace_opcode (instr
, opcode
);
7181 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7182 &instr
->value
, NULL
, NULL
))
7184 put_aarch64_insn (buf
, instr
->value
);
7189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7190 _("immediate cannot be moved by a single instruction"));
7193 /* An instruction operand which is immediate related may have symbol used
7194 in the assembly, e.g.
7197 .set u32, 0x00ffff00
7199 At the time when the assembly instruction is parsed, a referenced symbol,
7200 like 'u32' in the above example may not have been seen; a fixS is created
7201 in such a case and is handled here after symbols have been resolved.
7202 Instruction is fixed up with VALUE using the information in *FIXP plus
7203 extra information in FLAGS.
7205 This function is called by md_apply_fix to fix up instructions that need
7206 a fix-up described above but does not involve any linker-time relocation. */
7209 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7213 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7214 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7215 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7219 /* Now the instruction is about to be fixed-up, so the operand that
7220 was previously marked as 'ignored' needs to be unmarked in order
7221 to get the encoding done properly. */
7222 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7223 new_inst
->operands
[idx
].skip
= 0;
7226 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7230 case AARCH64_OPND_EXCEPTION
:
7231 if (unsigned_overflow (value
, 16))
7232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7233 _("immediate out of range"));
7234 insn
= get_aarch64_insn (buf
);
7235 insn
|= encode_svc_imm (value
);
7236 put_aarch64_insn (buf
, insn
);
7239 case AARCH64_OPND_AIMM
:
7240 /* ADD or SUB with immediate.
7241 NOTE this assumes we come here with a add/sub shifted reg encoding
7242 3 322|2222|2 2 2 21111 111111
7243 1 098|7654|3 2 1 09876 543210 98765 43210
7244 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7245 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7246 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7247 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7249 3 322|2222|2 2 221111111111
7250 1 098|7654|3 2 109876543210 98765 43210
7251 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7252 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7253 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7254 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7255 Fields sf Rn Rd are already set. */
7256 insn
= get_aarch64_insn (buf
);
7260 insn
= reencode_addsub_switch_add_sub (insn
);
7264 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7265 && unsigned_overflow (value
, 12))
7267 /* Try to shift the value by 12 to make it fit. */
7268 if (((value
>> 12) << 12) == value
7269 && ! unsigned_overflow (value
, 12 + 12))
7272 insn
|= encode_addsub_imm_shift_amount (1);
7276 if (unsigned_overflow (value
, 12))
7277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7278 _("immediate out of range"));
7280 insn
|= encode_addsub_imm (value
);
7282 put_aarch64_insn (buf
, insn
);
7285 case AARCH64_OPND_SIMD_IMM
:
7286 case AARCH64_OPND_SIMD_IMM_SFT
:
7287 case AARCH64_OPND_LIMM
:
7288 /* Bit mask immediate. */
7289 gas_assert (new_inst
!= NULL
);
7290 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7291 new_inst
->operands
[idx
].imm
.value
= value
;
7292 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7293 &new_inst
->value
, NULL
, NULL
))
7294 put_aarch64_insn (buf
, new_inst
->value
);
7296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7297 _("invalid immediate"));
7300 case AARCH64_OPND_HALF
:
7301 /* 16-bit unsigned immediate. */
7302 if (unsigned_overflow (value
, 16))
7303 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7304 _("immediate out of range"));
7305 insn
= get_aarch64_insn (buf
);
7306 insn
|= encode_movw_imm (value
& 0xffff);
7307 put_aarch64_insn (buf
, insn
);
7310 case AARCH64_OPND_IMM_MOV
:
7311 /* Operand for a generic move immediate instruction, which is
7312 an alias instruction that generates a single MOVZ, MOVN or ORR
7313 instruction to loads a 32-bit/64-bit immediate value into general
7314 register. An assembler error shall result if the immediate cannot be
7315 created by a single one of these instructions. If there is a choice,
7316 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7317 and MOVZ or MOVN to ORR. */
7318 gas_assert (new_inst
!= NULL
);
7319 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7322 case AARCH64_OPND_ADDR_SIMM7
:
7323 case AARCH64_OPND_ADDR_SIMM9
:
7324 case AARCH64_OPND_ADDR_SIMM9_2
:
7325 case AARCH64_OPND_ADDR_UIMM12
:
7326 /* Immediate offset in an address. */
7327 insn
= get_aarch64_insn (buf
);
7329 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7330 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7331 || new_inst
->opcode
->operands
[2] == opnd
);
7333 /* Get the index of the address operand. */
7334 if (new_inst
->opcode
->operands
[1] == opnd
)
7335 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7338 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7341 /* Update the resolved offset value. */
7342 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7344 /* Encode/fix-up. */
7345 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7346 &new_inst
->value
, NULL
, NULL
))
7348 put_aarch64_insn (buf
, new_inst
->value
);
7351 else if (new_inst
->opcode
->iclass
== ldst_pos
7352 && try_to_encode_as_unscaled_ldst (new_inst
))
7354 put_aarch64_insn (buf
, new_inst
->value
);
7358 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7359 _("immediate offset out of range"));
7364 as_fatal (_("unhandled operand code %d"), opnd
);
7368 /* Apply a fixup (fixP) to segment data, once it has been determined
7369 by our caller that we have all the info we need to fix it up.
7371 Parameter valP is the pointer to the value of the bits. */
7374 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7376 offsetT value
= *valP
;
7378 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7380 unsigned flags
= fixP
->fx_addnumber
;
7382 DEBUG_TRACE ("\n\n");
7383 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7384 DEBUG_TRACE ("Enter md_apply_fix");
7386 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7388 /* Note whether this will delete the relocation. */
7390 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7393 /* Process the relocations. */
7394 switch (fixP
->fx_r_type
)
7396 case BFD_RELOC_NONE
:
7397 /* This will need to go in the object file. */
7402 case BFD_RELOC_8_PCREL
:
7403 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7404 md_number_to_chars (buf
, value
, 1);
7408 case BFD_RELOC_16_PCREL
:
7409 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7410 md_number_to_chars (buf
, value
, 2);
7414 case BFD_RELOC_32_PCREL
:
7415 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7416 md_number_to_chars (buf
, value
, 4);
7420 case BFD_RELOC_64_PCREL
:
7421 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7422 md_number_to_chars (buf
, value
, 8);
7425 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7426 /* We claim that these fixups have been processed here, even if
7427 in fact we generate an error because we do not have a reloc
7428 for them, so tc_gen_reloc() will reject them. */
7430 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7432 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7433 _("undefined symbol %s used as an immediate value"),
7434 S_GET_NAME (fixP
->fx_addsy
));
7435 goto apply_fix_return
;
7437 fix_insn (fixP
, flags
, value
);
7440 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7441 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7445 _("pc-relative load offset not word aligned"));
7446 if (signed_overflow (value
, 21))
7447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7448 _("pc-relative load offset out of range"));
7449 insn
= get_aarch64_insn (buf
);
7450 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7451 put_aarch64_insn (buf
, insn
);
7455 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7456 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7458 if (signed_overflow (value
, 21))
7459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7460 _("pc-relative address offset out of range"));
7461 insn
= get_aarch64_insn (buf
);
7462 insn
|= encode_adr_imm (value
);
7463 put_aarch64_insn (buf
, insn
);
7467 case BFD_RELOC_AARCH64_BRANCH19
:
7468 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7472 _("conditional branch target not word aligned"));
7473 if (signed_overflow (value
, 21))
7474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7475 _("conditional branch out of range"));
7476 insn
= get_aarch64_insn (buf
);
7477 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7478 put_aarch64_insn (buf
, insn
);
7482 case BFD_RELOC_AARCH64_TSTBR14
:
7483 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7487 _("conditional branch target not word aligned"));
7488 if (signed_overflow (value
, 16))
7489 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7490 _("conditional branch out of range"));
7491 insn
= get_aarch64_insn (buf
);
7492 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7493 put_aarch64_insn (buf
, insn
);
7497 case BFD_RELOC_AARCH64_CALL26
:
7498 case BFD_RELOC_AARCH64_JUMP26
:
7499 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7503 _("branch target not word aligned"));
7504 if (signed_overflow (value
, 28))
7505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7506 _("branch out of range"));
7507 insn
= get_aarch64_insn (buf
);
7508 insn
|= encode_branch_ofs_26 (value
>> 2);
7509 put_aarch64_insn (buf
, insn
);
7513 case BFD_RELOC_AARCH64_MOVW_G0
:
7514 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7515 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7516 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7519 case BFD_RELOC_AARCH64_MOVW_G1
:
7520 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7521 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7522 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7525 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7527 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7528 /* Should always be exported to object file, see
7529 aarch64_force_relocation(). */
7530 gas_assert (!fixP
->fx_done
);
7531 gas_assert (seg
->use_rela_p
);
7533 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7535 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7536 /* Should always be exported to object file, see
7537 aarch64_force_relocation(). */
7538 gas_assert (!fixP
->fx_done
);
7539 gas_assert (seg
->use_rela_p
);
7541 case BFD_RELOC_AARCH64_MOVW_G2
:
7542 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7543 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7546 case BFD_RELOC_AARCH64_MOVW_G3
:
7549 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7551 insn
= get_aarch64_insn (buf
);
7555 /* REL signed addend must fit in 16 bits */
7556 if (signed_overflow (value
, 16))
7557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7558 _("offset out of range"));
7562 /* Check for overflow and scale. */
7563 switch (fixP
->fx_r_type
)
7565 case BFD_RELOC_AARCH64_MOVW_G0
:
7566 case BFD_RELOC_AARCH64_MOVW_G1
:
7567 case BFD_RELOC_AARCH64_MOVW_G2
:
7568 case BFD_RELOC_AARCH64_MOVW_G3
:
7569 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7570 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7571 if (unsigned_overflow (value
, scale
+ 16))
7572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7573 _("unsigned value out of range"));
7575 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7576 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7577 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7578 /* NOTE: We can only come here with movz or movn. */
7579 if (signed_overflow (value
, scale
+ 16))
7580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7581 _("signed value out of range"));
7584 /* Force use of MOVN. */
7586 insn
= reencode_movzn_to_movn (insn
);
7590 /* Force use of MOVZ. */
7591 insn
= reencode_movzn_to_movz (insn
);
7595 /* Unchecked relocations. */
7601 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7602 insn
|= encode_movw_imm (value
& 0xffff);
7604 put_aarch64_insn (buf
, insn
);
7608 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7609 fixP
->fx_r_type
= (ilp32_p
7610 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7611 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7612 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7613 /* Should always be exported to object file, see
7614 aarch64_force_relocation(). */
7615 gas_assert (!fixP
->fx_done
);
7616 gas_assert (seg
->use_rela_p
);
7619 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7620 fixP
->fx_r_type
= (ilp32_p
7621 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7622 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7623 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7624 /* Should always be exported to object file, see
7625 aarch64_force_relocation(). */
7626 gas_assert (!fixP
->fx_done
);
7627 gas_assert (seg
->use_rela_p
);
7630 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7631 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7632 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7633 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7634 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7635 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7636 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7637 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7638 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7639 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7640 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7641 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7642 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7643 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7644 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7645 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7646 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7647 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7648 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7649 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7650 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7651 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7652 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7653 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7654 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7655 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7656 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7657 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7658 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7659 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7660 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7661 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7662 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7663 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7664 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7665 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7666 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7667 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7668 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7669 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7670 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7671 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7672 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7673 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7674 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7675 /* Should always be exported to object file, see
7676 aarch64_force_relocation(). */
7677 gas_assert (!fixP
->fx_done
);
7678 gas_assert (seg
->use_rela_p
);
7681 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7682 /* Should always be exported to object file, see
7683 aarch64_force_relocation(). */
7684 fixP
->fx_r_type
= (ilp32_p
7685 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7686 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7687 gas_assert (!fixP
->fx_done
);
7688 gas_assert (seg
->use_rela_p
);
7691 case BFD_RELOC_AARCH64_ADD_LO12
:
7692 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7693 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7694 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7695 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7696 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7697 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7698 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7699 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7700 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7701 case BFD_RELOC_AARCH64_LDST128_LO12
:
7702 case BFD_RELOC_AARCH64_LDST16_LO12
:
7703 case BFD_RELOC_AARCH64_LDST32_LO12
:
7704 case BFD_RELOC_AARCH64_LDST64_LO12
:
7705 case BFD_RELOC_AARCH64_LDST8_LO12
:
7706 /* Should always be exported to object file, see
7707 aarch64_force_relocation(). */
7708 gas_assert (!fixP
->fx_done
);
7709 gas_assert (seg
->use_rela_p
);
7712 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7713 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7714 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7717 case BFD_RELOC_UNUSED
:
7718 /* An error will already have been reported. */
7722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7723 _("unexpected %s fixup"),
7724 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7729 /* Free the allocated the struct aarch64_inst.
7730 N.B. currently there are very limited number of fix-up types actually use
7731 this field, so the impact on the performance should be minimal . */
7732 if (fixP
->tc_fix_data
.inst
!= NULL
)
7733 free (fixP
->tc_fix_data
.inst
);
7738 /* Translate internal representation of relocation info to BFD target
7742 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7745 bfd_reloc_code_real_type code
;
7747 reloc
= XNEW (arelent
);
7749 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7750 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7751 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7755 if (section
->use_rela_p
)
7756 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7758 fixp
->fx_offset
= reloc
->address
;
7760 reloc
->addend
= fixp
->fx_offset
;
7762 code
= fixp
->fx_r_type
;
7767 code
= BFD_RELOC_16_PCREL
;
7772 code
= BFD_RELOC_32_PCREL
;
7777 code
= BFD_RELOC_64_PCREL
;
7784 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7785 if (reloc
->howto
== NULL
)
7787 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7789 ("cannot represent %s relocation in this object file format"),
7790 bfd_get_reloc_code_name (code
));
7797 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7800 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7802 bfd_reloc_code_real_type type
;
7806 FIXME: @@ Should look at CPU word size. */
7813 type
= BFD_RELOC_16
;
7816 type
= BFD_RELOC_32
;
7819 type
= BFD_RELOC_64
;
7822 as_bad (_("cannot do %u-byte relocation"), size
);
7823 type
= BFD_RELOC_UNUSED
;
7827 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7831 aarch64_force_relocation (struct fix
*fixp
)
7833 switch (fixp
->fx_r_type
)
7835 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7836 /* Perform these "immediate" internal relocations
7837 even if the symbol is extern or weak. */
7840 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7841 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7842 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7843 /* Pseudo relocs that need to be fixed up according to
7847 case BFD_RELOC_AARCH64_ADD_LO12
:
7848 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7849 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7850 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7851 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7852 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7853 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7854 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7855 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7856 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7857 case BFD_RELOC_AARCH64_LDST128_LO12
:
7858 case BFD_RELOC_AARCH64_LDST16_LO12
:
7859 case BFD_RELOC_AARCH64_LDST32_LO12
:
7860 case BFD_RELOC_AARCH64_LDST64_LO12
:
7861 case BFD_RELOC_AARCH64_LDST8_LO12
:
7862 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7863 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7864 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7865 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7866 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7867 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7868 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7869 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7870 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7871 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7872 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7873 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7874 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7875 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7876 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7877 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7878 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7879 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7880 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7881 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7882 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7883 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7884 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7885 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7886 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7887 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7888 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7889 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7890 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7891 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7892 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7893 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7894 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7895 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7896 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7897 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7898 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7899 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7900 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7901 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7902 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7903 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7904 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7905 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7906 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7907 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7908 /* Always leave these relocations for the linker. */
7915 return generic_force_reloc (fixp
);
7921 elf64_aarch64_target_format (void)
7923 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7925 /* FIXME: What to do for ilp32_p ? */
7926 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7928 if (target_big_endian
)
7929 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7931 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7935 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7937 elf_frob_symbol (symp
, puntp
);
7941 /* MD interface: Finalization. */
7943 /* A good place to do this, although this was probably not intended
7944 for this kind of use. We need to dump the literal pool before
7945 references are made to a null symbol pointer. */
7948 aarch64_cleanup (void)
7952 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7954 /* Put it at the end of the relevant section. */
7955 subseg_set (pool
->section
, pool
->sub_section
);
7961 /* Remove any excess mapping symbols generated for alignment frags in
7962 SEC. We may have created a mapping symbol before a zero byte
7963 alignment; remove it if there's a mapping symbol after the
7966 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7967 void *dummy ATTRIBUTE_UNUSED
)
7969 segment_info_type
*seginfo
= seg_info (sec
);
7972 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7975 for (fragp
= seginfo
->frchainP
->frch_root
;
7976 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7978 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7979 fragS
*next
= fragp
->fr_next
;
7981 /* Variable-sized frags have been converted to fixed size by
7982 this point. But if this was variable-sized to start with,
7983 there will be a fixed-size frag after it. So don't handle
7985 if (sym
== NULL
|| next
== NULL
)
7988 if (S_GET_VALUE (sym
) < next
->fr_address
)
7989 /* Not at the end of this frag. */
7991 know (S_GET_VALUE (sym
) == next
->fr_address
);
7995 if (next
->tc_frag_data
.first_map
!= NULL
)
7997 /* Next frag starts with a mapping symbol. Discard this
7999 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8003 if (next
->fr_next
== NULL
)
8005 /* This mapping symbol is at the end of the section. Discard
8007 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8008 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8012 /* As long as we have empty frags without any mapping symbols,
8014 /* If the next frag is non-empty and does not start with a
8015 mapping symbol, then this mapping symbol is required. */
8016 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8019 next
= next
->fr_next
;
8021 while (next
!= NULL
);
8026 /* Adjust the symbol table. */
8029 aarch64_adjust_symtab (void)
8032 /* Remove any overlapping mapping symbols generated by alignment frags. */
8033 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8034 /* Now do generic ELF adjustments. */
8035 elf_adjust_symtab ();
8040 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8042 const char *hash_err
;
8044 hash_err
= hash_insert (table
, key
, value
);
8046 printf ("Internal Error: Can't hash %s\n", key
);
8050 fill_instruction_hash_table (void)
8052 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8054 while (opcode
->name
!= NULL
)
8056 templates
*templ
, *new_templ
;
8057 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8059 new_templ
= XNEW (templates
);
8060 new_templ
->opcode
= opcode
;
8061 new_templ
->next
= NULL
;
8064 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8067 new_templ
->next
= templ
->next
;
8068 templ
->next
= new_templ
;
8075 convert_to_upper (char *dst
, const char *src
, size_t num
)
8078 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8079 *dst
= TOUPPER (*src
);
8083 /* Assume STR point to a lower-case string, allocate, convert and return
8084 the corresponding upper-case string. */
8085 static inline const char*
8086 get_upper_str (const char *str
)
8089 size_t len
= strlen (str
);
8090 ret
= XNEWVEC (char, len
+ 1);
8091 convert_to_upper (ret
, str
, len
);
8095 /* MD interface: Initialization. */
8103 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8104 || (aarch64_cond_hsh
= hash_new ()) == NULL
8105 || (aarch64_shift_hsh
= hash_new ()) == NULL
8106 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8107 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8108 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8109 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8110 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8111 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8112 || (aarch64_reg_hsh
= hash_new ()) == NULL
8113 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8114 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8115 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8116 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8117 as_fatal (_("virtual memory exhausted"));
8119 fill_instruction_hash_table ();
8121 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8122 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8123 (void *) (aarch64_sys_regs
+ i
));
8125 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8126 checked_hash_insert (aarch64_pstatefield_hsh
,
8127 aarch64_pstatefields
[i
].name
,
8128 (void *) (aarch64_pstatefields
+ i
));
8130 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8131 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8132 aarch64_sys_regs_ic
[i
].name
,
8133 (void *) (aarch64_sys_regs_ic
+ i
));
8135 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8136 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8137 aarch64_sys_regs_dc
[i
].name
,
8138 (void *) (aarch64_sys_regs_dc
+ i
));
8140 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8141 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8142 aarch64_sys_regs_at
[i
].name
,
8143 (void *) (aarch64_sys_regs_at
+ i
));
8145 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8146 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8147 aarch64_sys_regs_tlbi
[i
].name
,
8148 (void *) (aarch64_sys_regs_tlbi
+ i
));
8150 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8151 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8152 (void *) (reg_names
+ i
));
8154 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8155 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8156 (void *) (nzcv_names
+ i
));
8158 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8160 const char *name
= aarch64_operand_modifiers
[i
].name
;
8161 checked_hash_insert (aarch64_shift_hsh
, name
,
8162 (void *) (aarch64_operand_modifiers
+ i
));
8163 /* Also hash the name in the upper case. */
8164 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8165 (void *) (aarch64_operand_modifiers
+ i
));
8168 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8171 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8172 the same condition code. */
8173 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8175 const char *name
= aarch64_conds
[i
].names
[j
];
8178 checked_hash_insert (aarch64_cond_hsh
, name
,
8179 (void *) (aarch64_conds
+ i
));
8180 /* Also hash the name in the upper case. */
8181 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8182 (void *) (aarch64_conds
+ i
));
8186 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8188 const char *name
= aarch64_barrier_options
[i
].name
;
8189 /* Skip xx00 - the unallocated values of option. */
8192 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8193 (void *) (aarch64_barrier_options
+ i
));
8194 /* Also hash the name in the upper case. */
8195 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8196 (void *) (aarch64_barrier_options
+ i
));
8199 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8201 const char* name
= aarch64_prfops
[i
].name
;
8202 /* Skip the unallocated hint encodings. */
8205 checked_hash_insert (aarch64_pldop_hsh
, name
,
8206 (void *) (aarch64_prfops
+ i
));
8207 /* Also hash the name in the upper case. */
8208 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8209 (void *) (aarch64_prfops
+ i
));
8212 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8214 const char* name
= aarch64_hint_options
[i
].name
;
8216 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8217 (void *) (aarch64_hint_options
+ i
));
8218 /* Also hash the name in the upper case. */
8219 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8220 (void *) (aarch64_hint_options
+ i
));
8223 /* Set the cpu variant based on the command-line options. */
8225 mcpu_cpu_opt
= march_cpu_opt
;
8228 mcpu_cpu_opt
= &cpu_default
;
8230 cpu_variant
= *mcpu_cpu_opt
;
8232 /* Record the CPU type. */
8233 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8235 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8238 /* Command line processing. */
8240 const char *md_shortopts
= "m:";
8242 #ifdef AARCH64_BI_ENDIAN
8243 #define OPTION_EB (OPTION_MD_BASE + 0)
8244 #define OPTION_EL (OPTION_MD_BASE + 1)
8246 #if TARGET_BYTES_BIG_ENDIAN
8247 #define OPTION_EB (OPTION_MD_BASE + 0)
8249 #define OPTION_EL (OPTION_MD_BASE + 1)
8253 struct option md_longopts
[] = {
8255 {"EB", no_argument
, NULL
, OPTION_EB
},
8258 {"EL", no_argument
, NULL
, OPTION_EL
},
8260 {NULL
, no_argument
, NULL
, 0}
8263 size_t md_longopts_size
= sizeof (md_longopts
);
8265 struct aarch64_option_table
8267 const char *option
; /* Option name to match. */
8268 const char *help
; /* Help information. */
8269 int *var
; /* Variable to change. */
8270 int value
; /* What to change it to. */
8271 char *deprecated
; /* If non-null, print this message. */
8274 static struct aarch64_option_table aarch64_opts
[] = {
8275 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8276 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8278 #ifdef DEBUG_AARCH64
8279 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8280 #endif /* DEBUG_AARCH64 */
8281 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8283 {"mno-verbose-error", N_("do not output verbose error messages"),
8284 &verbose_error_p
, 0, NULL
},
8285 {NULL
, NULL
, NULL
, 0, NULL
}
8288 struct aarch64_cpu_option_table
8291 const aarch64_feature_set value
;
8292 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8294 const char *canonical_name
;
8297 /* This list should, at a minimum, contain all the cpu names
8298 recognized by GCC. */
8299 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8300 {"all", AARCH64_ANY
, NULL
},
8301 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8302 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8303 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8304 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8305 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8306 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8307 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8308 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8309 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8310 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8311 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8312 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8313 "Samsung Exynos M1"},
8314 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8315 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8316 "Qualcomm QDF24XX"},
8317 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8318 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8320 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8321 AARCH64_FEATURE_CRYPTO
),
8323 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8324 in earlier releases and is superseded by 'xgene1' in all
8326 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8327 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8328 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8329 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8330 {"generic", AARCH64_ARCH_V8
, NULL
},
8332 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8335 struct aarch64_arch_option_table
8338 const aarch64_feature_set value
;
8341 /* This list should, at a minimum, contain all the architecture names
8342 recognized by GCC. */
8343 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8344 {"all", AARCH64_ANY
},
8345 {"armv8-a", AARCH64_ARCH_V8
},
8346 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8347 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8348 {NULL
, AARCH64_ARCH_NONE
}
8351 /* ISA extensions. */
8352 struct aarch64_option_cpu_value_table
8355 const aarch64_feature_set value
;
8356 const aarch64_feature_set require
; /* Feature dependencies. */
8359 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8360 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8362 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
8364 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8366 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8368 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8370 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8372 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8374 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8376 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8377 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8378 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8379 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8380 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8382 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8385 struct aarch64_long_option_table
8387 const char *option
; /* Substring to match. */
8388 const char *help
; /* Help information. */
8389 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8390 char *deprecated
; /* If non-null, print this message. */
8393 /* Transitive closure of features depending on set. */
8394 static aarch64_feature_set
8395 aarch64_feature_disable_set (aarch64_feature_set set
)
8397 const struct aarch64_option_cpu_value_table
*opt
;
8398 aarch64_feature_set prev
= 0;
8400 while (prev
!= set
) {
8402 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8403 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8404 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8409 /* Transitive closure of dependencies of set. */
8410 static aarch64_feature_set
8411 aarch64_feature_enable_set (aarch64_feature_set set
)
8413 const struct aarch64_option_cpu_value_table
*opt
;
8414 aarch64_feature_set prev
= 0;
8416 while (prev
!= set
) {
8418 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8419 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8420 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8426 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8427 bfd_boolean ext_only
)
8429 /* We insist on extensions being added before being removed. We achieve
8430 this by using the ADDING_VALUE variable to indicate whether we are
8431 adding an extension (1) or removing it (0) and only allowing it to
8432 change in the order -1 -> 1 -> 0. */
8433 int adding_value
= -1;
8434 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8436 /* Copy the feature set, so that we can modify it. */
8440 while (str
!= NULL
&& *str
!= 0)
8442 const struct aarch64_option_cpu_value_table
*opt
;
8443 const char *ext
= NULL
;
8450 as_bad (_("invalid architectural extension"));
8454 ext
= strchr (++str
, '+');
8460 optlen
= strlen (str
);
8462 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8464 if (adding_value
!= 0)
8469 else if (optlen
> 0)
8471 if (adding_value
== -1)
8473 else if (adding_value
!= 1)
8475 as_bad (_("must specify extensions to add before specifying "
8476 "those to remove"));
8483 as_bad (_("missing architectural extension"));
8487 gas_assert (adding_value
!= -1);
8489 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8490 if (strncmp (opt
->name
, str
, optlen
) == 0)
8492 aarch64_feature_set set
;
8494 /* Add or remove the extension. */
8497 set
= aarch64_feature_enable_set (opt
->value
);
8498 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8502 set
= aarch64_feature_disable_set (opt
->value
);
8503 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8508 if (opt
->name
== NULL
)
8510 as_bad (_("unknown architectural extension `%s'"), str
);
8521 aarch64_parse_cpu (const char *str
)
8523 const struct aarch64_cpu_option_table
*opt
;
8524 const char *ext
= strchr (str
, '+');
8530 optlen
= strlen (str
);
8534 as_bad (_("missing cpu name `%s'"), str
);
8538 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8539 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8541 mcpu_cpu_opt
= &opt
->value
;
8543 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
8548 as_bad (_("unknown cpu `%s'"), str
);
8553 aarch64_parse_arch (const char *str
)
8555 const struct aarch64_arch_option_table
*opt
;
8556 const char *ext
= strchr (str
, '+');
8562 optlen
= strlen (str
);
8566 as_bad (_("missing architecture name `%s'"), str
);
8570 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8571 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8573 march_cpu_opt
= &opt
->value
;
8575 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8580 as_bad (_("unknown architecture `%s'\n"), str
);
8585 struct aarch64_option_abi_value_table
8588 enum aarch64_abi_type value
;
8591 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8592 {"ilp32", AARCH64_ABI_ILP32
},
8593 {"lp64", AARCH64_ABI_LP64
},
8597 aarch64_parse_abi (const char *str
)
8603 as_bad (_("missing abi name `%s'"), str
);
8607 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8608 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8610 aarch64_abi
= aarch64_abis
[i
].value
;
8614 as_bad (_("unknown abi `%s'\n"), str
);
8618 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8620 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8621 aarch64_parse_abi
, NULL
},
8622 #endif /* OBJ_ELF */
8623 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8624 aarch64_parse_cpu
, NULL
},
8625 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8626 aarch64_parse_arch
, NULL
},
8627 {NULL
, NULL
, 0, NULL
}
8631 md_parse_option (int c
, const char *arg
)
8633 struct aarch64_option_table
*opt
;
8634 struct aarch64_long_option_table
*lopt
;
8640 target_big_endian
= 1;
8646 target_big_endian
= 0;
8651 /* Listing option. Just ignore these, we don't support additional
8656 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8658 if (c
== opt
->option
[0]
8659 && ((arg
== NULL
&& opt
->option
[1] == 0)
8660 || streq (arg
, opt
->option
+ 1)))
8662 /* If the option is deprecated, tell the user. */
8663 if (opt
->deprecated
!= NULL
)
8664 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8665 arg
? arg
: "", _(opt
->deprecated
));
8667 if (opt
->var
!= NULL
)
8668 *opt
->var
= opt
->value
;
8674 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8676 /* These options are expected to have an argument. */
8677 if (c
== lopt
->option
[0]
8679 && strncmp (arg
, lopt
->option
+ 1,
8680 strlen (lopt
->option
+ 1)) == 0)
8682 /* If the option is deprecated, tell the user. */
8683 if (lopt
->deprecated
!= NULL
)
8684 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8685 _(lopt
->deprecated
));
8687 /* Call the sup-option parser. */
8688 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8699 md_show_usage (FILE * fp
)
8701 struct aarch64_option_table
*opt
;
8702 struct aarch64_long_option_table
*lopt
;
8704 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8706 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8707 if (opt
->help
!= NULL
)
8708 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8710 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8711 if (lopt
->help
!= NULL
)
8712 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8716 -EB assemble code for a big-endian cpu\n"));
8721 -EL assemble code for a little-endian cpu\n"));
8725 /* Parse a .cpu directive. */
8728 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8730 const struct aarch64_cpu_option_table
*opt
;
8736 name
= input_line_pointer
;
8737 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8738 input_line_pointer
++;
8739 saved_char
= *input_line_pointer
;
8740 *input_line_pointer
= 0;
8742 ext
= strchr (name
, '+');
8745 optlen
= ext
- name
;
8747 optlen
= strlen (name
);
8749 /* Skip the first "all" entry. */
8750 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8751 if (strlen (opt
->name
) == optlen
8752 && strncmp (name
, opt
->name
, optlen
) == 0)
8754 mcpu_cpu_opt
= &opt
->value
;
8756 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8759 cpu_variant
= *mcpu_cpu_opt
;
8761 *input_line_pointer
= saved_char
;
8762 demand_empty_rest_of_line ();
8765 as_bad (_("unknown cpu `%s'"), name
);
8766 *input_line_pointer
= saved_char
;
8767 ignore_rest_of_line ();
8771 /* Parse a .arch directive. */
8774 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8776 const struct aarch64_arch_option_table
*opt
;
8782 name
= input_line_pointer
;
8783 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8784 input_line_pointer
++;
8785 saved_char
= *input_line_pointer
;
8786 *input_line_pointer
= 0;
8788 ext
= strchr (name
, '+');
8791 optlen
= ext
- name
;
8793 optlen
= strlen (name
);
8795 /* Skip the first "all" entry. */
8796 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8797 if (strlen (opt
->name
) == optlen
8798 && strncmp (name
, opt
->name
, optlen
) == 0)
8800 mcpu_cpu_opt
= &opt
->value
;
8802 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8805 cpu_variant
= *mcpu_cpu_opt
;
8807 *input_line_pointer
= saved_char
;
8808 demand_empty_rest_of_line ();
8812 as_bad (_("unknown architecture `%s'\n"), name
);
8813 *input_line_pointer
= saved_char
;
8814 ignore_rest_of_line ();
8817 /* Parse a .arch_extension directive. */
8820 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8823 char *ext
= input_line_pointer
;;
8825 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8826 input_line_pointer
++;
8827 saved_char
= *input_line_pointer
;
8828 *input_line_pointer
= 0;
8830 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8833 cpu_variant
= *mcpu_cpu_opt
;
8835 *input_line_pointer
= saved_char
;
8836 demand_empty_rest_of_line ();
8839 /* Copy symbol information. */
8842 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8844 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);