1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 static aarch64_feature_set cpu_variant
;
47 /* Variables that we set while parsing command-line options. Once all
48 options have been read we re-process these values to set the real
50 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
51 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
53 /* Constants for known architecture features. */
54 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
56 static const aarch64_feature_set aarch64_arch_any
= AARCH64_ANY
;
57 static const aarch64_feature_set aarch64_arch_none
= AARCH64_ARCH_NONE
;
60 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
61 static symbolS
*GOT_symbol
;
74 /* Bits for DEFINED field in neon_type_el. */
76 #define NTA_HASINDEX 2
80 enum neon_el_type type
;
81 unsigned char defined
;
86 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
90 bfd_reloc_code_real_type type
;
93 enum aarch64_opnd opnd
;
95 unsigned need_libopcodes_p
: 1;
98 struct aarch64_instruction
100 /* libopcodes structure for instruction intermediate representation. */
102 /* Record assembly errors found during the parsing. */
105 enum aarch64_operand_error_kind kind
;
108 /* The condition that appears in the assembly line. */
110 /* Relocation information (including the GAS internal fixup). */
112 /* Need to generate an immediate in the literal pool. */
113 unsigned gen_lit_pool
: 1;
116 typedef struct aarch64_instruction aarch64_instruction
;
118 static aarch64_instruction inst
;
120 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
121 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
123 /* Diagnostics inline function utilites.
125 These are lightweight utlities which should only be called by parse_operands
126 and other parsers. GAS processes each assembly line by parsing it against
127 instruction template(s), in the case of multiple templates (for the same
128 mnemonic name), those templates are tried one by one until one succeeds or
129 all fail. An assembly line may fail a few templates before being
130 successfully parsed; an error saved here in most cases is not a user error
131 but an error indicating the current template is not the right template.
132 Therefore it is very important that errors can be saved at a low cost during
133 the parsing; we don't want to slow down the whole parsing by recording
134 non-user errors in detail.
136 Remember that the objective is to help GAS pick up the most approapriate
137 error message in the case of multiple templates, e.g. FMOV which has 8
143 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
144 inst
.parsing_error
.error
= NULL
;
147 static inline bfd_boolean
150 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
153 static inline const char *
154 get_error_message (void)
156 return inst
.parsing_error
.error
;
160 set_error_message (const char *error
)
162 inst
.parsing_error
.error
= error
;
165 static inline enum aarch64_operand_error_kind
166 get_error_kind (void)
168 return inst
.parsing_error
.kind
;
172 set_error_kind (enum aarch64_operand_error_kind kind
)
174 inst
.parsing_error
.kind
= kind
;
178 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
180 inst
.parsing_error
.kind
= kind
;
181 inst
.parsing_error
.error
= error
;
185 set_recoverable_error (const char *error
)
187 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
190 /* Use the DESC field of the corresponding aarch64_operand entry to compose
191 the error message. */
193 set_default_error (void)
195 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
199 set_syntax_error (const char *error
)
201 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
205 set_first_syntax_error (const char *error
)
208 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
212 set_fatal_syntax_error (const char *error
)
214 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
217 /* Number of littlenums required to hold an extended precision number. */
218 #define MAX_LITTLENUMS 6
220 /* Return value for certain parsers when the parsing fails; those parsers
221 return the information of the parsed result, e.g. register number, on
223 #define PARSE_FAIL -1
225 /* This is an invalid condition code that means no conditional field is
227 #define COND_ALWAYS 0x10
231 const char *template;
237 const char *template;
244 bfd_reloc_code_real_type reloc
;
247 /* Structure for a hash table entry for a register. */
251 unsigned char number
;
253 unsigned char builtin
;
256 /* Macros to define the register types and masks for the purpose
259 #undef AARCH64_REG_TYPES
260 #define AARCH64_REG_TYPES \
261 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
262 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
263 BASIC_REG_TYPE(SP_32) /* wsp */ \
264 BASIC_REG_TYPE(SP_64) /* sp */ \
265 BASIC_REG_TYPE(Z_32) /* wzr */ \
266 BASIC_REG_TYPE(Z_64) /* xzr */ \
267 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
268 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
269 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
270 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
271 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
272 BASIC_REG_TYPE(CN) /* c[0-7] */ \
273 BASIC_REG_TYPE(VN) /* v[0-31] */ \
274 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
275 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
276 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
277 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
278 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
279 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
280 /* Typecheck: any [BHSDQ]P FP. */ \
281 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
282 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
283 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
284 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
285 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
286 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
287 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
288 /* Any integer register; used for error messages only. */ \
289 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
292 /* Pseudo type to mark the end of the enumerator sequence. */ \
295 #undef BASIC_REG_TYPE
296 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
297 #undef MULTI_REG_TYPE
298 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
300 /* Register type enumerators. */
303 /* A list of REG_TYPE_*. */
307 #undef BASIC_REG_TYPE
308 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
310 #define REG_TYPE(T) (1 << REG_TYPE_##T)
311 #undef MULTI_REG_TYPE
312 #define MULTI_REG_TYPE(T,V) V,
314 /* Values indexed by aarch64_reg_type to assist the type checking. */
315 static const unsigned reg_type_masks
[] =
320 #undef BASIC_REG_TYPE
322 #undef MULTI_REG_TYPE
323 #undef AARCH64_REG_TYPES
325 /* Diagnostics used when we don't get a register of the expected type.
326 Note: this has to synchronized with aarch64_reg_type definitions
329 get_reg_expected_msg (aarch64_reg_type reg_type
)
336 msg
= N_("integer 32-bit register expected");
339 msg
= N_("integer 64-bit register expected");
342 msg
= N_("integer register expected");
344 case REG_TYPE_R_Z_SP
:
345 msg
= N_("integer, zero or SP register expected");
348 msg
= N_("8-bit SIMD scalar register expected");
351 msg
= N_("16-bit SIMD scalar or floating-point half precision "
352 "register expected");
355 msg
= N_("32-bit SIMD scalar or floating-point single precision "
356 "register expected");
359 msg
= N_("64-bit SIMD scalar or floating-point double precision "
360 "register expected");
363 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
364 "register expected");
367 msg
= N_("C0 - C15 expected");
369 case REG_TYPE_R_Z_BHSDQ_V
:
370 msg
= N_("register expected");
372 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
373 msg
= N_("SIMD scalar or floating-point register expected");
375 case REG_TYPE_VN
: /* any V reg */
376 msg
= N_("vector register expected");
379 as_fatal (_("invalid register type %d"), reg_type
);
384 /* Some well known registers that we refer to directly elsewhere. */
387 /* Instructions take 4 bytes in the object file. */
390 /* Define some common error messages. */
391 #define BAD_SP _("SP not allowed here")
393 static struct hash_control
*aarch64_ops_hsh
;
394 static struct hash_control
*aarch64_cond_hsh
;
395 static struct hash_control
*aarch64_shift_hsh
;
396 static struct hash_control
*aarch64_sys_regs_hsh
;
397 static struct hash_control
*aarch64_pstatefield_hsh
;
398 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
399 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
400 static struct hash_control
*aarch64_sys_regs_at_hsh
;
401 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
402 static struct hash_control
*aarch64_reg_hsh
;
403 static struct hash_control
*aarch64_barrier_opt_hsh
;
404 static struct hash_control
*aarch64_nzcv_hsh
;
405 static struct hash_control
*aarch64_pldop_hsh
;
407 /* Stuff needed to resolve the label ambiguity
416 static symbolS
*last_label_seen
;
418 /* Literal pool structure. Held on a per-section
419 and per-sub-section basis. */
421 #define MAX_LITERAL_POOL_SIZE 1024
422 typedef struct literal_pool
424 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
425 unsigned int next_free_entry
;
431 struct literal_pool
*next
;
434 /* Pointer to a linked list of literal pools. */
435 static literal_pool
*list_of_pools
= NULL
;
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful. */
441 const char comment_chars
[] = "";
443 /* This array holds the chars that only start a comment at the beginning of
444 a line. If the line seems to have the form '# 123 filename'
445 .line and .file directives will appear in the pre-processed output. */
446 /* Note that input_file.c hand checks for '#' at the beginning of the
447 first line of the input file. This is because the compiler outputs
448 #NO_APP at the beginning of its output. */
449 /* Also note that comments like this one will always work. */
450 const char line_comment_chars
[] = "#";
452 const char line_separator_chars
[] = ";";
454 /* Chars that can be used to separate mant
455 from exp in floating point numbers. */
456 const char EXP_CHARS
[] = "eE";
458 /* Chars that mean this number is a floating point constant. */
462 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
464 /* Prefix character that indicates the start of an immediate value. */
465 #define is_immediate_prefix(C) ((C) == '#')
467 /* Separator character handling. */
469 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
471 static inline bfd_boolean
472 skip_past_char (char **str
, char c
)
483 #define skip_past_comma(str) skip_past_char (str, ',')
485 /* Arithmetic expressions (possibly involving symbols). */
487 /* Return TRUE if anything in the expression *SP is a bignum. */
490 exp_has_bignum_p (symbolS
* sp
)
492 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
495 if (symbol_get_value_expression (sp
)->X_add_symbol
)
497 return (exp_has_bignum_p (symbol_get_value_expression (sp
)->X_add_symbol
)
498 || (symbol_get_value_expression (sp
)->X_op_symbol
499 && exp_has_bignum_p (symbol_get_value_expression (sp
)->
506 static bfd_boolean in_my_get_expression_p
= FALSE
;
508 /* Third argument to my_get_expression. */
509 #define GE_NO_PREFIX 0
510 #define GE_OPT_PREFIX 1
512 /* Return TRUE if the string pointed by *STR is successfully parsed
513 as an valid expression; *EP will be filled with the information of
514 such an expression. Otherwise return FALSE. */
517 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
522 int prefix_present_p
= 0;
529 if (is_immediate_prefix (**str
))
532 prefix_present_p
= 1;
539 memset (ep
, 0, sizeof (expressionS
));
541 save_in
= input_line_pointer
;
542 input_line_pointer
= *str
;
543 in_my_get_expression_p
= TRUE
;
544 seg
= expression (ep
);
545 in_my_get_expression_p
= FALSE
;
547 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
549 /* We found a bad expression in md_operand(). */
550 *str
= input_line_pointer
;
551 input_line_pointer
= save_in
;
552 if (prefix_present_p
&& ! error_p ())
553 set_fatal_syntax_error (_("bad expression"));
555 set_first_syntax_error (_("bad expression"));
560 if (seg
!= absolute_section
561 && seg
!= text_section
562 && seg
!= data_section
563 && seg
!= bss_section
&& seg
!= undefined_section
)
565 set_syntax_error (_("bad segment"));
566 *str
= input_line_pointer
;
567 input_line_pointer
= save_in
;
574 /* Get rid of any bignums now, so that we don't generate an error for which
575 we can't establish a line number later on. Big numbers are never valid
576 in instructions, which is where this routine is always called. */
577 if (ep
->X_op
== O_big
579 && (exp_has_bignum_p (ep
->X_add_symbol
)
580 || (ep
->X_op_symbol
&& exp_has_bignum_p (ep
->X_op_symbol
)))))
582 if (prefix_present_p
&& error_p ())
583 set_fatal_syntax_error (_("invalid constant"));
585 set_first_syntax_error (_("invalid constant"));
586 *str
= input_line_pointer
;
587 input_line_pointer
= save_in
;
591 *str
= input_line_pointer
;
592 input_line_pointer
= save_in
;
596 /* Turn a string in input_line_pointer into a floating point constant
597 of type TYPE, and store the appropriate bytes in *LITP. The number
598 of LITTLENUMS emitted is stored in *SIZEP. An error message is
599 returned, or NULL on OK. */
602 md_atof (int type
, char *litP
, int *sizeP
)
604 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
607 /* We handle all bad expressions here, so that we can report the faulty
608 instruction in the error message. */
610 md_operand (expressionS
* exp
)
612 if (in_my_get_expression_p
)
613 exp
->X_op
= O_illegal
;
616 /* Immediate values. */
618 /* Errors may be set multiple times during parsing or bit encoding
619 (particularly in the Neon bits), but usually the earliest error which is set
620 will be the most meaningful. Avoid overwriting it with later (cascading)
621 errors by calling this function. */
624 first_error (const char *error
)
627 set_syntax_error (error
);
630 /* Similiar to first_error, but this function accepts formatted error
633 first_error_fmt (const char *format
, ...)
638 /* N.B. this single buffer will not cause error messages for different
639 instructions to pollute each other; this is because at the end of
640 processing of each assembly line, error message if any will be
641 collected by as_bad. */
642 static char buffer
[size
];
647 va_start (args
, format
);
648 ret
= vsnprintf (buffer
, size
, format
, args
);
649 know (ret
<= size
- 1 && ret
>= 0);
651 set_syntax_error (buffer
);
655 /* Register parsing. */
657 /* Generic register parser which is called by other specialized
659 CCP points to what should be the beginning of a register name.
660 If it is indeed a valid register name, advance CCP over it and
661 return the reg_entry structure; otherwise return NULL.
662 It does not issue diagnostics. */
665 parse_reg (char **ccp
)
671 #ifdef REGISTER_PREFIX
672 if (*start
!= REGISTER_PREFIX
)
678 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
683 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
685 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
694 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
697 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
699 if (reg
->type
== type
)
704 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
705 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
706 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
707 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
708 case REG_TYPE_VN
: /* Vector register. */
709 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
710 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
711 == reg_type_masks
[reg
->type
]);
713 as_fatal ("unhandled type %d", type
);
718 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
719 Return the register number otherwise. *ISREG32 is set to one if the
720 register is 32-bit wide; *ISREGZERO is set to one if the register is
721 of type Z_32 or Z_64.
722 Note that this function does not issue any diagnostics. */
725 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
726 int *isreg32
, int *isregzero
)
729 const reg_entry
*reg
= parse_reg (&str
);
734 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
743 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
748 *isreg32
= reg
->type
== REG_TYPE_R_32
;
755 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
767 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
768 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
769 otherwise return FALSE.
771 Accept only one occurrence of:
772 8b 16b 4h 8h 2s 4s 1d 2d
775 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
779 unsigned element_size
;
780 enum neon_el_type type
;
790 width
= strtoul (ptr
, &ptr
, 10);
791 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
793 first_error_fmt (_("bad size %d in vector width specifier"), width
);
798 switch (TOLOWER (*ptr
))
826 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
828 first_error (_("missing element size"));
831 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
834 ("invalid element size %d and vector size combination %c"),
840 parsed_type
->type
= type
;
841 parsed_type
->width
= width
;
848 /* Parse a single type, e.g. ".8b", leading period included.
849 Only applicable to Vn registers.
851 Return TRUE on success; otherwise return FALSE. */
853 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
859 if (! parse_neon_type_for_operand (vectype
, &str
))
861 first_error (_("vector type expected"));
873 /* Parse a register of the type TYPE.
875 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
876 name or the parsed register is not of TYPE.
878 Otherwise return the register number, and optionally fill in the actual
879 type of the register in *RTYPE when multiple alternatives were given, and
880 return the register shape and element index information in *TYPEINFO.
882 IN_REG_LIST should be set with TRUE if the caller is parsing a register
886 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
887 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
890 const reg_entry
*reg
= parse_reg (&str
);
891 struct neon_type_el atype
;
892 struct neon_type_el parsetype
;
893 bfd_boolean is_typed_vecreg
= FALSE
;
896 atype
.type
= NT_invtype
;
904 set_default_error ();
908 if (! aarch64_check_reg_type (reg
, type
))
910 DEBUG_TRACE ("reg type check failed");
911 set_default_error ();
916 if (type
== REG_TYPE_VN
917 && parse_neon_operand_type (&parsetype
, &str
))
919 /* Register if of the form Vn.[bhsdq]. */
920 is_typed_vecreg
= TRUE
;
922 if (parsetype
.width
== 0)
923 /* Expect index. In the new scheme we cannot have
924 Vn.[bhsdq] represent a scalar. Therefore any
925 Vn.[bhsdq] should have an index following it.
926 Except in reglists ofcourse. */
927 atype
.defined
|= NTA_HASINDEX
;
929 atype
.defined
|= NTA_HASTYPE
;
931 atype
.type
= parsetype
.type
;
932 atype
.width
= parsetype
.width
;
935 if (skip_past_char (&str
, '['))
939 /* Reject Sn[index] syntax. */
940 if (!is_typed_vecreg
)
942 first_error (_("this type of register can't be indexed"));
946 if (in_reg_list
== TRUE
)
948 first_error (_("index not allowed inside register list"));
952 atype
.defined
|= NTA_HASINDEX
;
954 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
956 if (exp
.X_op
!= O_constant
)
958 first_error (_("constant expression required"));
962 if (! skip_past_char (&str
, ']'))
965 atype
.index
= exp
.X_add_number
;
967 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
969 /* Indexed vector register expected. */
970 first_error (_("indexed vector register expected"));
974 /* A vector reg Vn should be typed or indexed. */
975 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
977 first_error (_("invalid use of vector register"));
993 Return the register number on success; return PARSE_FAIL otherwise.
995 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
996 the register (e.g. NEON double or quad reg when either has been requested).
998 If this is a NEON vector register with additional type information, fill
999 in the struct pointed to by VECTYPE (if non-NULL).
1001 This parser does not handle register list. */
1004 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1005 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
1007 struct neon_type_el atype
;
1009 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1010 /*in_reg_list= */ FALSE
);
1012 if (reg
== PARSE_FAIL
)
1023 static inline bfd_boolean
1024 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1028 && e1
.defined
== e2
.defined
1029 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1032 /* This function parses the NEON register list. On success, it returns
1033 the parsed register list information in the following encoded format:
1035 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1036 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1038 The information of the register shape and/or index is returned in
1041 It returns PARSE_FAIL if the register list is invalid.
1043 The list contains one to four registers.
1044 Each register can be one of:
1047 All <T> should be identical.
1048 All <index> should be identical.
1049 There are restrictions on <Vt> numbers which are checked later
1050 (by reg_list_valid_p). */
1053 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1057 struct neon_type_el typeinfo
, typeinfo_first
;
1062 bfd_boolean error
= FALSE
;
1063 bfd_boolean expect_index
= FALSE
;
1067 set_syntax_error (_("expecting {"));
1073 typeinfo_first
.defined
= 0;
1074 typeinfo_first
.type
= NT_invtype
;
1075 typeinfo_first
.width
= -1;
1076 typeinfo_first
.index
= 0;
1085 str
++; /* skip over '-' */
1088 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1089 /*in_reg_list= */ TRUE
);
1090 if (val
== PARSE_FAIL
)
1092 set_first_syntax_error (_("invalid vector register in list"));
1096 /* reject [bhsd]n */
1097 if (typeinfo
.defined
== 0)
1099 set_first_syntax_error (_("invalid scalar register in list"));
1104 if (typeinfo
.defined
& NTA_HASINDEX
)
1105 expect_index
= TRUE
;
1109 if (val
< val_range
)
1111 set_first_syntax_error
1112 (_("invalid range in vector register list"));
1121 typeinfo_first
= typeinfo
;
1122 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1124 set_first_syntax_error
1125 (_("type mismatch in vector register list"));
1130 for (i
= val_range
; i
<= val
; i
++)
1132 ret_val
|= i
<< (5 * nb_regs
);
1137 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1139 skip_whitespace (str
);
1142 set_first_syntax_error (_("end of vector register list not found"));
1147 skip_whitespace (str
);
1151 if (skip_past_char (&str
, '['))
1155 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1156 if (exp
.X_op
!= O_constant
)
1158 set_first_syntax_error (_("constant expression required."));
1161 if (! skip_past_char (&str
, ']'))
1164 typeinfo_first
.index
= exp
.X_add_number
;
1168 set_first_syntax_error (_("expected index"));
1175 set_first_syntax_error (_("too many registers in vector register list"));
1178 else if (nb_regs
== 0)
1180 set_first_syntax_error (_("empty vector register list"));
1186 *vectype
= typeinfo_first
;
1188 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1191 /* Directives: register aliases. */
1194 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1199 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1202 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1205 /* Only warn about a redefinition if it's not defined as the
1207 else if (new->number
!= number
|| new->type
!= type
)
1208 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1213 name
= xstrdup (str
);
1214 new = xmalloc (sizeof (reg_entry
));
1217 new->number
= number
;
1219 new->builtin
= FALSE
;
1221 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1227 /* Look for the .req directive. This is of the form:
1229 new_register_name .req existing_register_name
1231 If we find one, or if it looks sufficiently like one that we want to
1232 handle any error here, return TRUE. Otherwise return FALSE. */
1235 create_register_alias (char *newname
, char *p
)
1237 const reg_entry
*old
;
1238 char *oldname
, *nbuf
;
1241 /* The input scrubber ensures that whitespace after the mnemonic is
1242 collapsed to single spaces. */
1244 if (strncmp (oldname
, " .req ", 6) != 0)
1248 if (*oldname
== '\0')
1251 old
= hash_find (aarch64_reg_hsh
, oldname
);
1254 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1258 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1259 the desired alias name, and p points to its end. If not, then
1260 the desired alias name is in the global original_case_string. */
1261 #ifdef TC_CASE_SENSITIVE
1264 newname
= original_case_string
;
1265 nlen
= strlen (newname
);
1268 nbuf
= alloca (nlen
+ 1);
1269 memcpy (nbuf
, newname
, nlen
);
1272 /* Create aliases under the new name as stated; an all-lowercase
1273 version of the new name; and an all-uppercase version of the new
1275 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1277 for (p
= nbuf
; *p
; p
++)
1280 if (strncmp (nbuf
, newname
, nlen
))
1282 /* If this attempt to create an additional alias fails, do not bother
1283 trying to create the all-lower case alias. We will fail and issue
1284 a second, duplicate error message. This situation arises when the
1285 programmer does something like:
1288 The second .req creates the "Foo" alias but then fails to create
1289 the artificial FOO alias because it has already been created by the
1291 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1295 for (p
= nbuf
; *p
; p
++)
1298 if (strncmp (nbuf
, newname
, nlen
))
1299 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1305 /* Should never be called, as .req goes between the alias and the
1306 register name, not at the beginning of the line. */
1308 s_req (int a ATTRIBUTE_UNUSED
)
1310 as_bad (_("invalid syntax for .req directive"));
1313 /* The .unreq directive deletes an alias which was previously defined
1314 by .req. For example:
1320 s_unreq (int a ATTRIBUTE_UNUSED
)
1325 name
= input_line_pointer
;
1327 while (*input_line_pointer
!= 0
1328 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1329 ++input_line_pointer
;
1331 saved_char
= *input_line_pointer
;
1332 *input_line_pointer
= 0;
1335 as_bad (_("invalid syntax for .unreq directive"));
1338 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1341 as_bad (_("unknown register alias '%s'"), name
);
1342 else if (reg
->builtin
)
1343 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1350 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1351 free ((char *) reg
->name
);
1354 /* Also locate the all upper case and all lower case versions.
1355 Do not complain if we cannot find one or the other as it
1356 was probably deleted above. */
1358 nbuf
= strdup (name
);
1359 for (p
= nbuf
; *p
; p
++)
1361 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1364 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1365 free ((char *) reg
->name
);
1369 for (p
= nbuf
; *p
; p
++)
1371 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1374 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1375 free ((char *) reg
->name
);
1383 *input_line_pointer
= saved_char
;
1384 demand_empty_rest_of_line ();
1387 /* Directives: Instruction set selection. */
1390 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1391 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1392 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1393 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1395 /* Create a new mapping symbol for the transition to STATE. */
1398 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1401 const char *symname
;
1408 type
= BSF_NO_FLAGS
;
1412 type
= BSF_NO_FLAGS
;
1418 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1419 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1421 /* Save the mapping symbols for future reference. Also check that
1422 we do not place two mapping symbols at the same offset within a
1423 frag. We'll handle overlap between frags in
1424 check_mapping_symbols.
1426 If .fill or other data filling directive generates zero sized data,
1427 the mapping symbol for the following code will have the same value
1428 as the one generated for the data filling directive. In this case,
1429 we replace the old symbol with the new one at the same address. */
1432 if (frag
->tc_frag_data
.first_map
!= NULL
)
1434 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1435 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1438 frag
->tc_frag_data
.first_map
= symbolP
;
1440 if (frag
->tc_frag_data
.last_map
!= NULL
)
1442 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1443 S_GET_VALUE (symbolP
));
1444 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1445 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1448 frag
->tc_frag_data
.last_map
= symbolP
;
1451 /* We must sometimes convert a region marked as code to data during
1452 code alignment, if an odd number of bytes have to be padded. The
1453 code mapping symbol is pushed to an aligned address. */
1456 insert_data_mapping_symbol (enum mstate state
,
1457 valueT value
, fragS
* frag
, offsetT bytes
)
1459 /* If there was already a mapping symbol, remove it. */
1460 if (frag
->tc_frag_data
.last_map
!= NULL
1461 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1462 frag
->fr_address
+ value
)
1464 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1468 know (frag
->tc_frag_data
.first_map
== symp
);
1469 frag
->tc_frag_data
.first_map
= NULL
;
1471 frag
->tc_frag_data
.last_map
= NULL
;
1472 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1475 make_mapping_symbol (MAP_DATA
, value
, frag
);
1476 make_mapping_symbol (state
, value
+ bytes
, frag
);
1479 static void mapping_state_2 (enum mstate state
, int max_chars
);
1481 /* Set the mapping state to STATE. Only call this when about to
1482 emit some STATE bytes to the file. */
1485 mapping_state (enum mstate state
)
1487 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1489 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1491 if (mapstate
== state
)
1492 /* The mapping symbol has already been emitted.
1493 There is nothing else to do. */
1495 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
1496 /* This case will be evaluated later in the next else. */
1498 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1500 /* Only add the symbol if the offset is > 0:
1501 if we're at the first frag, check it's size > 0;
1502 if we're not at the first frag, then for sure
1503 the offset is > 0. */
1504 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1505 const int add_symbol
= (frag_now
!= frag_first
)
1506 || (frag_now_fix () > 0);
1509 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1512 mapping_state_2 (state
, 0);
1516 /* Same as mapping_state, but MAX_CHARS bytes have already been
1517 allocated. Put the mapping symbol that far back. */
1520 mapping_state_2 (enum mstate state
, int max_chars
)
1522 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1524 if (!SEG_NORMAL (now_seg
))
1527 if (mapstate
== state
)
1528 /* The mapping symbol has already been emitted.
1529 There is nothing else to do. */
1532 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1533 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1536 #define mapping_state(x) /* nothing */
1537 #define mapping_state_2(x, y) /* nothing */
1540 /* Directives: sectioning and alignment. */
1543 s_bss (int ignore ATTRIBUTE_UNUSED
)
1545 /* We don't support putting frags in the BSS segment, we fake it by
1546 marking in_bss, then looking at s_skip for clues. */
1547 subseg_set (bss_section
, 0);
1548 demand_empty_rest_of_line ();
1549 mapping_state (MAP_DATA
);
1553 s_even (int ignore ATTRIBUTE_UNUSED
)
1555 /* Never make frag if expect extra pass. */
1557 frag_align (1, 0, 0);
1559 record_alignment (now_seg
, 1);
1561 demand_empty_rest_of_line ();
1564 /* Directives: Literal pools. */
1566 static literal_pool
*
1567 find_literal_pool (int size
)
1571 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1573 if (pool
->section
== now_seg
1574 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1581 static literal_pool
*
1582 find_or_make_literal_pool (int size
)
1584 /* Next literal pool ID number. */
1585 static unsigned int latest_pool_num
= 1;
1588 pool
= find_literal_pool (size
);
1592 /* Create a new pool. */
1593 pool
= xmalloc (sizeof (*pool
));
1597 /* Currently we always put the literal pool in the current text
1598 section. If we were generating "small" model code where we
1599 knew that all code and initialised data was within 1MB then
1600 we could output literals to mergeable, read-only data
1603 pool
->next_free_entry
= 0;
1604 pool
->section
= now_seg
;
1605 pool
->sub_section
= now_subseg
;
1607 pool
->next
= list_of_pools
;
1608 pool
->symbol
= NULL
;
1610 /* Add it to the list. */
1611 list_of_pools
= pool
;
1614 /* New pools, and emptied pools, will have a NULL symbol. */
1615 if (pool
->symbol
== NULL
)
1617 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1618 (valueT
) 0, &zero_address_frag
);
1619 pool
->id
= latest_pool_num
++;
1626 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1627 Return TRUE on success, otherwise return FALSE. */
1629 add_to_lit_pool (expressionS
*exp
, int size
)
1634 pool
= find_or_make_literal_pool (size
);
1636 /* Check if this literal value is already in the pool. */
1637 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1639 if ((pool
->literals
[entry
].X_op
== exp
->X_op
)
1640 && (exp
->X_op
== O_constant
)
1641 && (pool
->literals
[entry
].X_add_number
== exp
->X_add_number
)
1642 && (pool
->literals
[entry
].X_unsigned
== exp
->X_unsigned
))
1645 if ((pool
->literals
[entry
].X_op
== exp
->X_op
)
1646 && (exp
->X_op
== O_symbol
)
1647 && (pool
->literals
[entry
].X_add_number
== exp
->X_add_number
)
1648 && (pool
->literals
[entry
].X_add_symbol
== exp
->X_add_symbol
)
1649 && (pool
->literals
[entry
].X_op_symbol
== exp
->X_op_symbol
))
1653 /* Do we need to create a new entry? */
1654 if (entry
== pool
->next_free_entry
)
1656 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1658 set_syntax_error (_("literal pool overflow"));
1662 pool
->literals
[entry
] = *exp
;
1663 pool
->next_free_entry
+= 1;
1666 exp
->X_op
= O_symbol
;
1667 exp
->X_add_number
= ((int) entry
) * size
;
1668 exp
->X_add_symbol
= pool
->symbol
;
1673 /* Can't use symbol_new here, so have to create a symbol and then at
1674 a later date assign it a value. Thats what these functions do. */
1677 symbol_locate (symbolS
* symbolP
,
1678 const char *name
,/* It is copied, the caller can modify. */
1679 segT segment
, /* Segment identifier (SEG_<something>). */
1680 valueT valu
, /* Symbol value. */
1681 fragS
* frag
) /* Associated fragment. */
1683 unsigned int name_length
;
1684 char *preserved_copy_of_name
;
1686 name_length
= strlen (name
) + 1; /* +1 for \0. */
1687 obstack_grow (¬es
, name
, name_length
);
1688 preserved_copy_of_name
= obstack_finish (¬es
);
1690 #ifdef tc_canonicalize_symbol_name
1691 preserved_copy_of_name
=
1692 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1695 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1697 S_SET_SEGMENT (symbolP
, segment
);
1698 S_SET_VALUE (symbolP
, valu
);
1699 symbol_clear_list_pointers (symbolP
);
1701 symbol_set_frag (symbolP
, frag
);
1703 /* Link to end of symbol chain. */
1705 extern int symbol_table_frozen
;
1707 if (symbol_table_frozen
)
1711 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1713 obj_symbol_new_hook (symbolP
);
1715 #ifdef tc_symbol_new_hook
1716 tc_symbol_new_hook (symbolP
);
1720 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1721 #endif /* DEBUG_SYMS */
1726 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1733 for (align
= 2; align
< 4; align
++)
1735 int size
= 1 << align
;
1737 pool
= find_literal_pool (size
);
1738 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1741 mapping_state (MAP_DATA
);
1743 /* Align pool as you have word accesses.
1744 Only make a frag if we have to. */
1746 frag_align (align
, 0, 0);
1748 record_alignment (now_seg
, align
);
1750 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1752 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1753 (valueT
) frag_now_fix (), frag_now
);
1754 symbol_table_insert (pool
->symbol
);
1756 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1757 /* First output the expression in the instruction to the pool. */
1758 emit_expr (&(pool
->literals
[entry
]), size
); /* .word|.xword */
1760 /* Mark the pool as empty. */
1761 pool
->next_free_entry
= 0;
1762 pool
->symbol
= NULL
;
1767 /* Forward declarations for functions below, in the MD interface
1769 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1770 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1772 /* Directives: Data. */
1773 /* N.B. the support for relocation suffix in this directive needs to be
1774 implemented properly. */
1777 s_aarch64_elf_cons (int nbytes
)
1781 #ifdef md_flush_pending_output
1782 md_flush_pending_output ();
1785 if (is_it_end_of_statement ())
1787 demand_empty_rest_of_line ();
1791 #ifdef md_cons_align
1792 md_cons_align (nbytes
);
1795 mapping_state (MAP_DATA
);
1798 struct reloc_table_entry
*reloc
;
1802 if (exp
.X_op
!= O_symbol
)
1803 emit_expr (&exp
, (unsigned int) nbytes
);
1806 skip_past_char (&input_line_pointer
, '#');
1807 if (skip_past_char (&input_line_pointer
, ':'))
1809 reloc
= find_reloc_table_entry (&input_line_pointer
);
1811 as_bad (_("unrecognized relocation suffix"));
1813 as_bad (_("unimplemented relocation suffix"));
1814 ignore_rest_of_line ();
1818 emit_expr (&exp
, (unsigned int) nbytes
);
1821 while (*input_line_pointer
++ == ',');
1823 /* Put terminator back into stream. */
1824 input_line_pointer
--;
1825 demand_empty_rest_of_line ();
1828 #endif /* OBJ_ELF */
1830 /* Output a 32-bit word, but mark as an instruction. */
1833 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1837 #ifdef md_flush_pending_output
1838 md_flush_pending_output ();
1841 if (is_it_end_of_statement ())
1843 demand_empty_rest_of_line ();
1848 frag_align_code (2, 0);
1850 mapping_state (MAP_INSN
);
1856 if (exp
.X_op
!= O_constant
)
1858 as_bad (_("constant expression required"));
1859 ignore_rest_of_line ();
1863 if (target_big_endian
)
1865 unsigned int val
= exp
.X_add_number
;
1866 exp
.X_add_number
= SWAP_32 (val
);
1868 emit_expr (&exp
, 4);
1870 while (*input_line_pointer
++ == ',');
1872 /* Put terminator back into stream. */
1873 input_line_pointer
--;
1874 demand_empty_rest_of_line ();
1878 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1881 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1885 /* Since we're just labelling the code, there's no need to define a
1888 /* Make sure there is enough room in this frag for the following
1889 blr. This trick only works if the blr follows immediately after
1890 the .tlsdesc directive. */
1892 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1893 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1895 demand_empty_rest_of_line ();
1897 #endif /* OBJ_ELF */
1899 static void s_aarch64_arch (int);
1900 static void s_aarch64_cpu (int);
1902 /* This table describes all the machine specific pseudo-ops the assembler
1903 has to support. The fields are:
1904 pseudo-op name without dot
1905 function to call to execute this pseudo-op
1906 Integer arg to pass to the function. */
1908 const pseudo_typeS md_pseudo_table
[] = {
1909 /* Never called because '.req' does not start a line. */
1911 {"unreq", s_unreq
, 0},
1913 {"even", s_even
, 0},
1914 {"ltorg", s_ltorg
, 0},
1915 {"pool", s_ltorg
, 0},
1916 {"cpu", s_aarch64_cpu
, 0},
1917 {"arch", s_aarch64_arch
, 0},
1918 {"inst", s_aarch64_inst
, 0},
1920 {"tlsdesccall", s_tlsdesccall
, 0},
1921 {"word", s_aarch64_elf_cons
, 4},
1922 {"long", s_aarch64_elf_cons
, 4},
1923 {"xword", s_aarch64_elf_cons
, 8},
1924 {"dword", s_aarch64_elf_cons
, 8},
1930 /* Check whether STR points to a register name followed by a comma or the
1931 end of line; REG_TYPE indicates which register types are checked
1932 against. Return TRUE if STR is such a register name; otherwise return
1933 FALSE. The function does not intend to produce any diagnostics, but since
1934 the register parser aarch64_reg_parse, which is called by this function,
1935 does produce diagnostics, we call clear_error to clear any diagnostics
1936 that may be generated by aarch64_reg_parse.
1937 Also, the function returns FALSE directly if there is any user error
1938 present at the function entry. This prevents the existing diagnostics
1939 state from being spoiled.
1940 The function currently serves parse_constant_immediate and
1941 parse_big_immediate only. */
1943 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1947 /* Prevent the diagnostics state from being spoiled. */
1951 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1953 /* Clear the parsing error that may be set by the reg parser. */
1956 if (reg
== PARSE_FAIL
)
1959 skip_whitespace (str
);
1960 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1966 /* Parser functions used exclusively in instruction operands. */
1968 /* Parse an immediate expression which may not be constant.
1970 To prevent the expression parser from pushing a register name
1971 into the symbol table as an undefined symbol, firstly a check is
1972 done to find out whether STR is a valid register name followed
1973 by a comma or the end of line. Return FALSE if STR is such a
1977 parse_immediate_expression (char **str
, expressionS
*exp
)
1979 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
1981 set_recoverable_error (_("immediate operand required"));
1985 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
1987 if (exp
->X_op
== O_absent
)
1989 set_fatal_syntax_error (_("missing immediate expression"));
1996 /* Constant immediate-value read function for use in insn parsing.
1997 STR points to the beginning of the immediate (with the optional
1998 leading #); *VAL receives the value.
2000 Return TRUE on success; otherwise return FALSE. */
2003 parse_constant_immediate (char **str
, int64_t * val
)
2007 if (! parse_immediate_expression (str
, &exp
))
2010 if (exp
.X_op
!= O_constant
)
2012 set_syntax_error (_("constant expression required"));
2016 *val
= exp
.X_add_number
;
2021 encode_imm_float_bits (uint32_t imm
)
2023 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2024 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2027 /* Return TRUE if IMM is a valid floating-point immediate; return FALSE
2030 aarch64_imm_float_p (uint32_t imm
)
2032 /* 3 32222222 2221111111111
2033 1 09876543 21098765432109876543210
2034 n Eeeeeexx xxxx0000000000000000000 */
2037 e
= (imm
>> 30) & 0x1;
2042 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0 */
2043 && ((imm
& 0x7e000000) == e
); /* bits 25-29 = ~ bit 30 */
2046 /* Note: this accepts the floating-point 0 constant. */
2048 parse_aarch64_imm_float (char **ccp
, int *immed
)
2052 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2053 int found_fpchar
= 0;
2055 skip_past_char (&str
, '#');
2057 /* We must not accidentally parse an integer as a floating-point number. Make
2058 sure that the value we parse is not an integer by checking for special
2059 characters '.' or 'e'.
2060 FIXME: This is a hack that is not very efficient, but doing better is
2061 tricky because type information isn't in a very usable state at parse
2064 skip_whitespace (fpnum
);
2066 if (strncmp (fpnum
, "0x", 2) == 0)
2070 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2071 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2081 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
2083 unsigned fpword
= 0;
2086 /* Our FP word must be 32 bits (single-precision FP). */
2087 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2089 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2093 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2104 set_fatal_syntax_error (_("invalid floating-point constant"));
2108 /* Less-generic immediate-value read function with the possibility of loading
2109 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2112 To prevent the expression parser from pushing a register name into the
2113 symbol table as an undefined symbol, a check is firstly done to find
2114 out whether STR is a valid register name followed by a comma or the end
2115 of line. Return FALSE if STR is such a register. */
2118 parse_big_immediate (char **str
, int64_t *imm
)
2122 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2124 set_syntax_error (_("immediate operand required"));
2128 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2130 if (inst
.reloc
.exp
.X_op
== O_constant
)
2131 *imm
= inst
.reloc
.exp
.X_add_number
;
2138 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2139 if NEED_LIBOPCODES is non-zero, the fixup will need
2140 assistance from the libopcodes. */
2143 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2144 const aarch64_opnd_info
*operand
,
2145 int need_libopcodes_p
)
2147 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2148 reloc
->opnd
= operand
->type
;
2149 if (need_libopcodes_p
)
2150 reloc
->need_libopcodes_p
= 1;
2153 /* Return TRUE if the instruction needs to be fixed up later internally by
2154 the GAS; otherwise return FALSE. */
2156 static inline bfd_boolean
2157 aarch64_gas_internal_fixup_p (void)
2159 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2162 /* Assign the immediate value to the relavant field in *OPERAND if
2163 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2164 needs an internal fixup in a later stage.
2165 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2166 IMM.VALUE that may get assigned with the constant. */
2168 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2169 aarch64_opnd_info
*operand
,
2171 int need_libopcodes_p
,
2174 if (reloc
->exp
.X_op
== O_constant
)
2177 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2179 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2180 reloc
->type
= BFD_RELOC_UNUSED
;
2184 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2185 /* Tell libopcodes to ignore this operand or not. This is helpful
2186 when one of the operands needs to be fixed up later but we need
2187 libopcodes to check the other operands. */
2188 operand
->skip
= skip_p
;
2192 /* Relocation modifiers. Each entry in the table contains the textual
2193 name for the relocation which may be placed before a symbol used as
2194 a load/store offset, or add immediate. It must be surrounded by a
2195 leading and trailing colon, for example:
2197 ldr x0, [x1, #:rello:varsym]
2198 add x0, x1, #:rello:varsym */
2200 struct reloc_table_entry
2204 bfd_reloc_code_real_type adrp_type
;
2205 bfd_reloc_code_real_type movw_type
;
2206 bfd_reloc_code_real_type add_type
;
2207 bfd_reloc_code_real_type ldst_type
;
2210 static struct reloc_table_entry reloc_table
[] = {
2211 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2215 BFD_RELOC_AARCH64_ADD_LO12
,
2216 BFD_RELOC_AARCH64_LDST_LO12
},
2218 /* Higher 21 bits of pc-relative page offset: ADRP */
2220 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2225 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2227 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2232 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2235 BFD_RELOC_AARCH64_MOVW_G0
,
2239 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2242 BFD_RELOC_AARCH64_MOVW_G0_S
,
2246 /* Less significant bits 0-15 of address/value: MOVK, no check */
2249 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2253 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2256 BFD_RELOC_AARCH64_MOVW_G1
,
2260 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2263 BFD_RELOC_AARCH64_MOVW_G1_S
,
2267 /* Less significant bits 16-31 of address/value: MOVK, no check */
2270 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2274 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2277 BFD_RELOC_AARCH64_MOVW_G2
,
2281 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2284 BFD_RELOC_AARCH64_MOVW_G2_S
,
2288 /* Less significant bits 32-47 of address/value: MOVK, no check */
2291 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2295 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2298 BFD_RELOC_AARCH64_MOVW_G3
,
2301 /* Get to the page containing GOT entry for a symbol. */
2303 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2307 /* 12 bit offset into the page containing GOT entry for that symbol. */
2312 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
},
2314 /* Get to the page containing GOT TLS entry for a symbol */
2316 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2321 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2325 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2328 /* Get to the page containing GOT TLS entry for a symbol */
2330 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
,
2335 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2339 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2340 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
},
2342 /* Get to the page containing GOT TLS entry for a symbol */
2344 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2349 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2350 {"gottprel_lo12", 0,
2354 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
},
2356 /* Get tp offset for a symbol. */
2360 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2363 /* Get tp offset for a symbol. */
2367 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2370 /* Get tp offset for a symbol. */
2374 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2377 /* Get tp offset for a symbol. */
2378 {"tprel_lo12_nc", 0,
2381 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2384 /* Most significant bits 32-47 of address/value: MOVZ. */
2387 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2391 /* Most significant bits 16-31 of address/value: MOVZ. */
2394 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2398 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2401 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2405 /* Most significant bits 0-15 of address/value: MOVZ. */
2408 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2412 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2415 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2420 /* Given the address of a pointer pointing to the textual name of a
2421 relocation as may appear in assembler source, attempt to find its
2422 details in reloc_table. The pointer will be updated to the character
2423 after the trailing colon. On failure, NULL will be returned;
2424 otherwise return the reloc_table_entry. */
2426 static struct reloc_table_entry
*
2427 find_reloc_table_entry (char **str
)
2430 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2432 int length
= strlen (reloc_table
[i
].name
);
2434 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2435 && (*str
)[length
] == ':')
2437 *str
+= (length
+ 1);
2438 return &reloc_table
[i
];
2445 /* Mode argument to parse_shift and parser_shifter_operand. */
2446 enum parse_shift_mode
2448 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2450 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2452 SHIFTED_LSL
, /* bare "lsl #n" */
2453 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2454 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2457 /* Parse a <shift> operator on an AArch64 data processing instruction.
2458 Return TRUE on success; otherwise return FALSE. */
2460 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2462 const struct aarch64_name_value_pair
*shift_op
;
2463 enum aarch64_modifier_kind kind
;
2469 for (p
= *str
; ISALPHA (*p
); p
++)
2474 set_syntax_error (_("shift expression expected"));
2478 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2480 if (shift_op
== NULL
)
2482 set_syntax_error (_("shift operator expected"));
2486 kind
= aarch64_get_operand_modifier (shift_op
);
2488 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2490 set_syntax_error (_("invalid use of 'MSL'"));
2496 case SHIFTED_LOGIC_IMM
:
2497 if (aarch64_extend_operator_p (kind
) == TRUE
)
2499 set_syntax_error (_("extending shift is not permitted"));
2504 case SHIFTED_ARITH_IMM
:
2505 if (kind
== AARCH64_MOD_ROR
)
2507 set_syntax_error (_("'ROR' shift is not permitted"));
2513 if (kind
!= AARCH64_MOD_LSL
)
2515 set_syntax_error (_("only 'LSL' shift is permitted"));
2520 case SHIFTED_REG_OFFSET
:
2521 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2522 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2524 set_fatal_syntax_error
2525 (_("invalid shift for the register offset addressing mode"));
2530 case SHIFTED_LSL_MSL
:
2531 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2533 set_syntax_error (_("invalid shift operator"));
2542 /* Whitespace can appear here if the next thing is a bare digit. */
2543 skip_whitespace (p
);
2545 /* Parse shift amount. */
2547 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2548 exp
.X_op
= O_absent
;
2551 if (is_immediate_prefix (*p
))
2556 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2558 if (exp
.X_op
== O_absent
)
2560 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2562 set_syntax_error (_("missing shift amount"));
2565 operand
->shifter
.amount
= 0;
2567 else if (exp
.X_op
!= O_constant
)
2569 set_syntax_error (_("constant shift amount required"));
2572 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2574 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2579 operand
->shifter
.amount
= exp
.X_add_number
;
2580 operand
->shifter
.amount_present
= 1;
2583 operand
->shifter
.operator_present
= 1;
2584 operand
->shifter
.kind
= kind
;
2590 /* Parse a <shifter_operand> for a data processing instruction:
2593 #<immediate>, LSL #imm
2595 Validation of immediate operands is deferred to md_apply_fix.
2597 Return TRUE on success; otherwise return FALSE. */
2600 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2601 enum parse_shift_mode mode
)
2605 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2610 /* Accept an immediate expression. */
2611 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2614 /* Accept optional LSL for arithmetic immediate values. */
2615 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2616 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2619 /* Not accept any shifter for logical immediate values. */
2620 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2621 && parse_shift (&p
, operand
, mode
))
2623 set_syntax_error (_("unexpected shift operator"));
2631 /* Parse a <shifter_operand> for a data processing instruction:
2636 #<immediate>, LSL #imm
2638 where <shift> is handled by parse_shift above, and the last two
2639 cases are handled by the function above.
2641 Validation of immediate operands is deferred to md_apply_fix.
2643 Return TRUE on success; otherwise return FALSE. */
2646 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2647 enum parse_shift_mode mode
)
2650 int isreg32
, isregzero
;
2651 enum aarch64_operand_class opd_class
2652 = aarch64_get_operand_class (operand
->type
);
2655 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2657 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2659 set_syntax_error (_("unexpected register in the immediate operand"));
2663 if (!isregzero
&& reg
== REG_SP
)
2665 set_syntax_error (BAD_SP
);
2669 operand
->reg
.regno
= reg
;
2670 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2672 /* Accept optional shift operation on register. */
2673 if (! skip_past_comma (str
))
2676 if (! parse_shift (str
, operand
, mode
))
2681 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2684 (_("integer register expected in the extended/shifted operand "
2689 /* We have a shifted immediate variable. */
2690 return parse_shifter_operand_imm (str
, operand
, mode
);
2693 /* Return TRUE on success; return FALSE otherwise. */
2696 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
2697 enum parse_shift_mode mode
)
2701 /* Determine if we have the sequence of characters #: or just :
2702 coming next. If we do, then we check for a :rello: relocation
2703 modifier. If we don't, punt the whole lot to
2704 parse_shifter_operand. */
2706 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
2708 struct reloc_table_entry
*entry
;
2716 /* Try to parse a relocation. Anything else is an error. */
2717 if (!(entry
= find_reloc_table_entry (str
)))
2719 set_syntax_error (_("unknown relocation modifier"));
2723 if (entry
->add_type
== 0)
2726 (_("this relocation modifier is not allowed on this instruction"));
2730 /* Save str before we decompose it. */
2733 /* Next, we parse the expression. */
2734 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
2737 /* Record the relocation type (use the ADD variant here). */
2738 inst
.reloc
.type
= entry
->add_type
;
2739 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2741 /* If str is empty, we've reached the end, stop here. */
2745 /* Otherwise, we have a shifted reloc modifier, so rewind to
2746 recover the variable name and continue parsing for the shifter. */
2748 return parse_shifter_operand_imm (str
, operand
, mode
);
2751 return parse_shifter_operand (str
, operand
, mode
);
2754 /* Parse all forms of an address expression. Information is written
2755 to *OPERAND and/or inst.reloc.
2757 The A64 instruction set has the following addressing modes:
2760 [base] // in SIMD ld/st structure
2761 [base{,#0}] // in ld/st exclusive
2763 [base,Xm{,LSL #imm}]
2764 [base,Xm,SXTX {#imm}]
2765 [base,Wm,(S|U)XTW {#imm}]
2770 [base],Xm // in SIMD ld/st structure
2771 PC-relative (literal)
2775 (As a convenience, the notation "=immediate" is permitted in conjunction
2776 with the pc-relative literal load instructions to automatically place an
2777 immediate value or symbolic address in a nearby literal pool and generate
2778 a hidden label which references it.)
2780 Upon a successful parsing, the address structure in *OPERAND will be
2781 filled in the following way:
2783 .base_regno = <base>
2784 .offset.is_reg // 1 if the offset is a register
2786 .offset.regno = <Rm>
2788 For different addressing modes defined in the A64 ISA:
2791 .pcrel=0; .preind=1; .postind=0; .writeback=0
2793 .pcrel=0; .preind=1; .postind=0; .writeback=1
2795 .pcrel=0; .preind=0; .postind=1; .writeback=1
2796 PC-relative (literal)
2797 .pcrel=1; .preind=1; .postind=0; .writeback=0
2799 The shift/extension information, if any, will be stored in .shifter.
2801 It is the caller's responsibility to check for addressing modes not
2802 supported by the instruction, and to set inst.reloc.type. */
2805 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
2806 int accept_reg_post_index
)
2810 int isreg32
, isregzero
;
2811 expressionS
*exp
= &inst
.reloc
.exp
;
2813 if (! skip_past_char (&p
, '['))
2815 /* =immediate or label. */
2816 operand
->addr
.pcrel
= 1;
2817 operand
->addr
.preind
= 1;
2819 if (skip_past_char (&p
, '='))
2820 /* =immediate; need to generate the literal in the liternal pool. */
2821 inst
.gen_lit_pool
= 1;
2823 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
2825 set_syntax_error (_("invalid address"));
2835 /* Accept SP and reject ZR */
2836 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
2837 if (reg
== PARSE_FAIL
|| isreg32
)
2839 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
2842 operand
->addr
.base_regno
= reg
;
2845 if (skip_past_comma (&p
))
2848 operand
->addr
.preind
= 1;
2850 /* Reject SP and accept ZR */
2851 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
2852 if (reg
!= PARSE_FAIL
)
2855 operand
->addr
.offset
.regno
= reg
;
2856 operand
->addr
.offset
.is_reg
= 1;
2857 /* Shifted index. */
2858 if (skip_past_comma (&p
))
2861 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
2862 /* Use the diagnostics set in parse_shift, so not set new
2863 error message here. */
2867 [base,Xm{,LSL #imm}]
2868 [base,Xm,SXTX {#imm}]
2869 [base,Wm,(S|U)XTW {#imm}] */
2870 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
2871 || operand
->shifter
.kind
== AARCH64_MOD_LSL
2872 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
2876 set_syntax_error (_("invalid use of 32-bit register offset"));
2882 set_syntax_error (_("invalid use of 64-bit register offset"));
2888 /* [Xn,#:<reloc_op>:<symbol> */
2889 skip_past_char (&p
, '#');
2890 if (reloc
&& skip_past_char (&p
, ':'))
2892 struct reloc_table_entry
*entry
;
2894 /* Try to parse a relocation modifier. Anything else is
2896 if (!(entry
= find_reloc_table_entry (&p
)))
2898 set_syntax_error (_("unknown relocation modifier"));
2902 if (entry
->ldst_type
== 0)
2905 (_("this relocation modifier is not allowed on this "
2910 /* [Xn,#:<reloc_op>: */
2911 /* We now have the group relocation table entry corresponding to
2912 the name in the assembler source. Next, we parse the
2914 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
2916 set_syntax_error (_("invalid relocation expression"));
2920 /* [Xn,#:<reloc_op>:<expr> */
2921 /* Record the load/store relocation type. */
2922 inst
.reloc
.type
= entry
->ldst_type
;
2923 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2925 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
2927 set_syntax_error (_("invalid expression in the address"));
2934 if (! skip_past_char (&p
, ']'))
2936 set_syntax_error (_("']' expected"));
2940 if (skip_past_char (&p
, '!'))
2942 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
2944 set_syntax_error (_("register offset not allowed in pre-indexed "
2945 "addressing mode"));
2949 operand
->addr
.writeback
= 1;
2951 else if (skip_past_comma (&p
))
2954 operand
->addr
.postind
= 1;
2955 operand
->addr
.writeback
= 1;
2957 if (operand
->addr
.preind
)
2959 set_syntax_error (_("cannot combine pre- and post-indexing"));
2963 if (accept_reg_post_index
2964 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
2965 &isregzero
)) != PARSE_FAIL
)
2970 set_syntax_error (_("invalid 32-bit register offset"));
2973 operand
->addr
.offset
.regno
= reg
;
2974 operand
->addr
.offset
.is_reg
= 1;
2976 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
2979 set_syntax_error (_("invalid expression in the address"));
2984 /* If at this point neither .preind nor .postind is set, we have a
2985 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
2986 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
2988 if (operand
->addr
.writeback
)
2991 set_syntax_error (_("missing offset in the pre-indexed address"));
2994 operand
->addr
.preind
= 1;
2995 inst
.reloc
.exp
.X_op
= O_constant
;
2996 inst
.reloc
.exp
.X_add_number
= 0;
3003 /* Return TRUE on success; otherwise return FALSE. */
3005 parse_address (char **str
, aarch64_opnd_info
*operand
,
3006 int accept_reg_post_index
)
3008 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3011 /* Return TRUE on success; otherwise return FALSE. */
3013 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3015 return parse_address_main (str
, operand
, 1, 0);
3018 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3019 Return TRUE on success; otherwise return FALSE. */
3021 parse_half (char **str
, int *internal_fixup_p
)
3027 skip_past_char (&p
, '#');
3029 gas_assert (internal_fixup_p
);
3030 *internal_fixup_p
= 0;
3034 struct reloc_table_entry
*entry
;
3036 /* Try to parse a relocation. Anything else is an error. */
3038 if (!(entry
= find_reloc_table_entry (&p
)))
3040 set_syntax_error (_("unknown relocation modifier"));
3044 if (entry
->movw_type
== 0)
3047 (_("this relocation modifier is not allowed on this instruction"));
3051 inst
.reloc
.type
= entry
->movw_type
;
3054 *internal_fixup_p
= 1;
3056 /* Avoid parsing a register as a general symbol. */
3058 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3062 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3069 /* Parse an operand for an ADRP instruction:
3071 Return TRUE on success; otherwise return FALSE. */
3074 parse_adrp (char **str
)
3081 struct reloc_table_entry
*entry
;
3083 /* Try to parse a relocation. Anything else is an error. */
3085 if (!(entry
= find_reloc_table_entry (&p
)))
3087 set_syntax_error (_("unknown relocation modifier"));
3091 if (entry
->adrp_type
== 0)
3094 (_("this relocation modifier is not allowed on this instruction"));
3098 inst
.reloc
.type
= entry
->adrp_type
;
3101 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3103 inst
.reloc
.pc_rel
= 1;
3105 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3112 /* Miscellaneous. */
3114 /* Parse an option for a preload instruction. Returns the encoding for the
3115 option, or PARSE_FAIL. */
3118 parse_pldop (char **str
)
3121 const struct aarch64_name_value_pair
*o
;
3124 while (ISALNUM (*q
))
3127 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3135 /* Parse an option for a barrier instruction. Returns the encoding for the
3136 option, or PARSE_FAIL. */
3139 parse_barrier (char **str
)
3142 const asm_barrier_opt
*o
;
3145 while (ISALPHA (*q
))
3148 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3156 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3157 Returns the encoding for the option, or PARSE_FAIL.
3159 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3160 implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
3163 parse_sys_reg (char **str
, struct hash_control
*sys_regs
, int imple_defined_p
)
3167 const struct aarch64_name_value_pair
*o
;
3171 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3173 *p
++ = TOLOWER (*q
);
3175 /* Assert that BUF be large enough. */
3176 gas_assert (p
- buf
== q
- *str
);
3178 o
= hash_find (sys_regs
, buf
);
3181 if (!imple_defined_p
)
3185 /* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
3187 unsigned int op0
, op1
, cn
, cm
, op2
;
3188 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
) != 5)
3190 /* Register access is encoded as follows:
3192 11 xxx 1x11 xxxx xxx. */
3193 if (op0
!= 3 || op1
> 7 || (cn
| 0x4) != 0xf || cm
> 15 || op2
> 7)
3195 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3205 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3206 for the option, or NULL. */
3208 static const aarch64_sys_ins_reg
*
3209 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3213 const aarch64_sys_ins_reg
*o
;
3216 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3218 *p
++ = TOLOWER (*q
);
3221 o
= hash_find (sys_ins_regs
, buf
);
3229 #define po_char_or_fail(chr) do { \
3230 if (! skip_past_char (&str, chr)) \
3234 #define po_reg_or_fail(regtype) do { \
3235 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3236 if (val == PARSE_FAIL) \
3238 set_default_error (); \
3243 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3244 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3245 &isreg32, &isregzero); \
3246 if (val == PARSE_FAIL) \
3248 set_default_error (); \
3251 info->reg.regno = val; \
3253 info->qualifier = AARCH64_OPND_QLF_W; \
3255 info->qualifier = AARCH64_OPND_QLF_X; \
3258 #define po_imm_nc_or_fail() do { \
3259 if (! parse_constant_immediate (&str, &val)) \
3263 #define po_imm_or_fail(min, max) do { \
3264 if (! parse_constant_immediate (&str, &val)) \
3266 if (val < min || val > max) \
3268 set_fatal_syntax_error (_("immediate value out of range "\
3269 #min " to "#max)); \
3274 #define po_misc_or_fail(expr) do { \
3279 /* encode the 12-bit imm field of Add/sub immediate */
3280 static inline uint32_t
3281 encode_addsub_imm (uint32_t imm
)
3286 /* encode the shift amount field of Add/sub immediate */
3287 static inline uint32_t
3288 encode_addsub_imm_shift_amount (uint32_t cnt
)
3294 /* encode the imm field of Adr instruction */
3295 static inline uint32_t
3296 encode_adr_imm (uint32_t imm
)
3298 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3299 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3302 /* encode the immediate field of Move wide immediate */
3303 static inline uint32_t
3304 encode_movw_imm (uint32_t imm
)
3309 /* encode the 26-bit offset of unconditional branch */
3310 static inline uint32_t
3311 encode_branch_ofs_26 (uint32_t ofs
)
3313 return ofs
& ((1 << 26) - 1);
3316 /* encode the 19-bit offset of conditional branch and compare & branch */
3317 static inline uint32_t
3318 encode_cond_branch_ofs_19 (uint32_t ofs
)
3320 return (ofs
& ((1 << 19) - 1)) << 5;
3323 /* encode the 19-bit offset of ld literal */
3324 static inline uint32_t
3325 encode_ld_lit_ofs_19 (uint32_t ofs
)
3327 return (ofs
& ((1 << 19) - 1)) << 5;
3330 /* Encode the 14-bit offset of test & branch. */
3331 static inline uint32_t
3332 encode_tst_branch_ofs_14 (uint32_t ofs
)
3334 return (ofs
& ((1 << 14) - 1)) << 5;
3337 /* Encode the 16-bit imm field of svc/hvc/smc. */
3338 static inline uint32_t
3339 encode_svc_imm (uint32_t imm
)
3344 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3345 static inline uint32_t
3346 reencode_addsub_switch_add_sub (uint32_t opcode
)
3348 return opcode
^ (1 << 30);
3351 static inline uint32_t
3352 reencode_movzn_to_movz (uint32_t opcode
)
3354 return opcode
| (1 << 30);
3357 static inline uint32_t
3358 reencode_movzn_to_movn (uint32_t opcode
)
3360 return opcode
& ~(1 << 30);
3363 /* Overall per-instruction processing. */
3365 /* We need to be able to fix up arbitrary expressions in some statements.
3366 This is so that we can handle symbols that are an arbitrary distance from
3367 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3368 which returns part of an address in a form which will be valid for
3369 a data instruction. We do this by pushing the expression into a symbol
3370 in the expr_section, and creating a fix for that. */
3373 fix_new_aarch64 (fragS
* frag
,
3375 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3385 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3389 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3396 /* Diagnostics on operands errors. */
3398 /* By default, output one-line error message only.
3399 Enable the verbose error message by -merror-verbose. */
3400 static int verbose_error_p
= 0;
3402 #ifdef DEBUG_AARCH64
3403 /* N.B. this is only for the purpose of debugging. */
3404 const char* operand_mismatch_kind_names
[] =
3407 "AARCH64_OPDE_RECOVERABLE",
3408 "AARCH64_OPDE_SYNTAX_ERROR",
3409 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3410 "AARCH64_OPDE_INVALID_VARIANT",
3411 "AARCH64_OPDE_OUT_OF_RANGE",
3412 "AARCH64_OPDE_UNALIGNED",
3413 "AARCH64_OPDE_REG_LIST",
3414 "AARCH64_OPDE_OTHER_ERROR",
3416 #endif /* DEBUG_AARCH64 */
3418 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3420 When multiple errors of different kinds are found in the same assembly
3421 line, only the error of the highest severity will be picked up for
3422 issuing the diagnostics. */
3424 static inline bfd_boolean
3425 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3426 enum aarch64_operand_error_kind rhs
)
3428 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3429 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3430 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3431 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3432 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3433 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3434 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3435 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3439 /* Helper routine to get the mnemonic name from the assembly instruction
3440 line; should only be called for the diagnosis purpose, as there is
3441 string copy operation involved, which may affect the runtime
3442 performance if used in elsewhere. */
3445 get_mnemonic_name (const char *str
)
3447 static char mnemonic
[32];
3450 /* Get the first 15 bytes and assume that the full name is included. */
3451 strncpy (mnemonic
, str
, 31);
3452 mnemonic
[31] = '\0';
3454 /* Scan up to the end of the mnemonic, which must end in white space,
3455 '.', or end of string. */
3456 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3461 /* Append '...' to the truncated long name. */
3462 if (ptr
- mnemonic
== 31)
3463 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3469 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3471 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3472 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3475 /* Data strutures storing one user error in the assembly code related to
3478 struct operand_error_record
3480 const aarch64_opcode
*opcode
;
3481 aarch64_operand_error detail
;
3482 struct operand_error_record
*next
;
3485 typedef struct operand_error_record operand_error_record
;
3487 struct operand_errors
3489 operand_error_record
*head
;
3490 operand_error_record
*tail
;
3493 typedef struct operand_errors operand_errors
;
3495 /* Top-level data structure reporting user errors for the current line of
3497 The way md_assemble works is that all opcodes sharing the same mnemonic
3498 name are iterated to find a match to the assembly line. In this data
3499 structure, each of the such opcodes will have one operand_error_record
3500 allocated and inserted. In other words, excessive errors related with
3501 a single opcode are disregarded. */
3502 operand_errors operand_error_report
;
3504 /* Free record nodes. */
3505 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3507 /* Initialize the data structure that stores the operand mismatch
3508 information on assembling one line of the assembly code. */
3510 init_operand_error_report (void)
3512 if (operand_error_report
.head
!= NULL
)
3514 gas_assert (operand_error_report
.tail
!= NULL
);
3515 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3516 free_opnd_error_record_nodes
= operand_error_report
.head
;
3517 operand_error_report
.head
= NULL
;
3518 operand_error_report
.tail
= NULL
;
3521 gas_assert (operand_error_report
.tail
== NULL
);
3524 /* Return TRUE if some operand error has been recorded during the
3525 parsing of the current assembly line using the opcode *OPCODE;
3526 otherwise return FALSE. */
3527 static inline bfd_boolean
3528 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3530 operand_error_record
*record
= operand_error_report
.head
;
3531 return record
&& record
->opcode
== opcode
;
3534 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3535 OPCODE field is initialized with OPCODE.
3536 N.B. only one record for each opcode, i.e. the maximum of one error is
3537 recorded for each instruction template. */
3540 add_operand_error_record (const operand_error_record
* new_record
)
3542 const aarch64_opcode
*opcode
= new_record
->opcode
;
3543 operand_error_record
* record
= operand_error_report
.head
;
3545 /* The record may have been created for this opcode. If not, we need
3547 if (! opcode_has_operand_error_p (opcode
))
3549 /* Get one empty record. */
3550 if (free_opnd_error_record_nodes
== NULL
)
3552 record
= xmalloc (sizeof (operand_error_record
));
3558 record
= free_opnd_error_record_nodes
;
3559 free_opnd_error_record_nodes
= record
->next
;
3561 record
->opcode
= opcode
;
3562 /* Insert at the head. */
3563 record
->next
= operand_error_report
.head
;
3564 operand_error_report
.head
= record
;
3565 if (operand_error_report
.tail
== NULL
)
3566 operand_error_report
.tail
= record
;
3568 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3569 && record
->detail
.index
<= new_record
->detail
.index
3570 && operand_error_higher_severity_p (record
->detail
.kind
,
3571 new_record
->detail
.kind
))
3573 /* In the case of multiple errors found on operands related with a
3574 single opcode, only record the error of the leftmost operand and
3575 only if the error is of higher severity. */
3576 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3577 " the existing error %s on operand %d",
3578 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3579 new_record
->detail
.index
,
3580 operand_mismatch_kind_names
[record
->detail
.kind
],
3581 record
->detail
.index
);
3585 record
->detail
= new_record
->detail
;
3589 record_operand_error_info (const aarch64_opcode
*opcode
,
3590 aarch64_operand_error
*error_info
)
3592 operand_error_record record
;
3593 record
.opcode
= opcode
;
3594 record
.detail
= *error_info
;
3595 add_operand_error_record (&record
);
3598 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3599 error message *ERROR, for operand IDX (count from 0). */
3602 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3603 enum aarch64_operand_error_kind kind
,
3606 aarch64_operand_error info
;
3607 memset(&info
, 0, sizeof (info
));
3611 record_operand_error_info (opcode
, &info
);
3615 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3616 enum aarch64_operand_error_kind kind
,
3617 const char* error
, const int *extra_data
)
3619 aarch64_operand_error info
;
3623 info
.data
[0] = extra_data
[0];
3624 info
.data
[1] = extra_data
[1];
3625 info
.data
[2] = extra_data
[2];
3626 record_operand_error_info (opcode
, &info
);
3630 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
3631 const char* error
, int lower_bound
,
3634 int data
[3] = {lower_bound
, upper_bound
, 0};
3635 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
3639 /* Remove the operand error record for *OPCODE. */
3640 static void ATTRIBUTE_UNUSED
3641 remove_operand_error_record (const aarch64_opcode
*opcode
)
3643 if (opcode_has_operand_error_p (opcode
))
3645 operand_error_record
* record
= operand_error_report
.head
;
3646 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
3647 operand_error_report
.head
= record
->next
;
3648 record
->next
= free_opnd_error_record_nodes
;
3649 free_opnd_error_record_nodes
= record
;
3650 if (operand_error_report
.head
== NULL
)
3652 gas_assert (operand_error_report
.tail
== record
);
3653 operand_error_report
.tail
= NULL
;
3658 /* Given the instruction in *INSTR, return the index of the best matched
3659 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3661 Return -1 if there is no qualifier sequence; return the first match
3662 if there is multiple matches found. */
3665 find_best_match (const aarch64_inst
*instr
,
3666 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
3668 int i
, num_opnds
, max_num_matched
, idx
;
3670 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3673 DEBUG_TRACE ("no operand");
3677 max_num_matched
= 0;
3680 /* For each pattern. */
3681 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
3684 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
3686 /* Most opcodes has much fewer patterns in the list. */
3687 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
3689 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
3690 if (i
!= 0 && idx
== -1)
3691 /* If nothing has been matched, return the 1st sequence. */
3696 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
3697 if (*qualifiers
== instr
->operands
[j
].qualifier
)
3700 if (num_matched
> max_num_matched
)
3702 max_num_matched
= num_matched
;
3707 DEBUG_TRACE ("return with %d", idx
);
3711 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3712 corresponding operands in *INSTR. */
3715 assign_qualifier_sequence (aarch64_inst
*instr
,
3716 const aarch64_opnd_qualifier_t
*qualifiers
)
3719 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3720 gas_assert (num_opnds
);
3721 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
3722 instr
->operands
[i
].qualifier
= *qualifiers
;
3725 /* Print operands for the diagnosis purpose. */
3728 print_operands (char *buf
, const aarch64_opcode
*opcode
,
3729 const aarch64_opnd_info
*opnds
)
3733 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
3735 const size_t size
= 128;
3738 /* We regard the opcode operand info more, however we also look into
3739 the inst->operands to support the disassembling of the optional
3741 The two operand code should be the same in all cases, apart from
3742 when the operand can be optional. */
3743 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
3744 || opnds
[i
].type
== AARCH64_OPND_NIL
)
3747 /* Generate the operand string in STR. */
3748 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
3752 strcat (buf
, i
== 0 ? " " : ",");
3754 /* Append the operand string. */
3759 /* Send to stderr a string as information. */
3762 output_info (const char *format
, ...)
3768 as_where (&file
, &line
);
3772 fprintf (stderr
, "%s:%u: ", file
, line
);
3774 fprintf (stderr
, "%s: ", file
);
3776 fprintf (stderr
, _("Info: "));
3777 va_start (args
, format
);
3778 vfprintf (stderr
, format
, args
);
3780 (void) putc ('\n', stderr
);
3783 /* Output one operand error record. */
3786 output_operand_error_record (const operand_error_record
*record
, char *str
)
3788 int idx
= record
->detail
.index
;
3789 const aarch64_opcode
*opcode
= record
->opcode
;
3790 enum aarch64_opnd opd_code
= (idx
!= -1 ? opcode
->operands
[idx
]
3791 : AARCH64_OPND_NIL
);
3792 const aarch64_operand_error
*detail
= &record
->detail
;
3794 switch (detail
->kind
)
3796 case AARCH64_OPDE_NIL
:
3800 case AARCH64_OPDE_SYNTAX_ERROR
:
3801 case AARCH64_OPDE_RECOVERABLE
:
3802 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
3803 case AARCH64_OPDE_OTHER_ERROR
:
3804 gas_assert (idx
>= 0);
3805 /* Use the prepared error message if there is, otherwise use the
3806 operand description string to describe the error. */
3807 if (detail
->error
!= NULL
)
3809 if (detail
->index
== -1)
3810 as_bad (_("%s -- `%s'"), detail
->error
, str
);
3812 as_bad (_("%s at operand %d -- `%s'"),
3813 detail
->error
, detail
->index
+ 1, str
);
3816 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
3817 aarch64_get_operand_desc (opd_code
), str
);
3820 case AARCH64_OPDE_INVALID_VARIANT
:
3821 as_bad (_("operand mismatch -- `%s'"), str
);
3822 if (verbose_error_p
)
3824 /* We will try to correct the erroneous instruction and also provide
3825 more information e.g. all other valid variants.
3827 The string representation of the corrected instruction and other
3828 valid variants are generated by
3830 1) obtaining the intermediate representation of the erroneous
3832 2) manipulating the IR, e.g. replacing the operand qualifier;
3833 3) printing out the instruction by calling the printer functions
3834 shared with the disassembler.
3836 The limitation of this method is that the exact input assembly
3837 line cannot be accurately reproduced in some cases, for example an
3838 optional operand present in the actual assembly line will be
3839 omitted in the output; likewise for the optional syntax rules,
3840 e.g. the # before the immediate. Another limitation is that the
3841 assembly symbols and relocation operations in the assembly line
3842 currently cannot be printed out in the error report. Last but not
3843 least, when there is other error(s) co-exist with this error, the
3844 'corrected' instruction may be still incorrect, e.g. given
3845 'ldnp h0,h1,[x0,#6]!'
3846 this diagnosis will provide the version:
3847 'ldnp s0,s1,[x0,#6]!'
3848 which is still not right. */
3849 size_t len
= strlen (get_mnemonic_name (str
));
3852 const size_t size
= 2048;
3854 aarch64_inst
*inst_base
= &inst
.base
;
3855 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
3858 reset_aarch64_instruction (&inst
);
3859 inst_base
->opcode
= opcode
;
3861 /* Reset the error report so that there is no side effect on the
3862 following operand parsing. */
3863 init_operand_error_report ();
3866 result
= parse_operands (str
+ len
, opcode
)
3867 && programmer_friendly_fixup (&inst
);
3868 gas_assert (result
);
3869 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
3871 gas_assert (!result
);
3873 /* Find the most matched qualifier sequence. */
3874 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
3875 gas_assert (qlf_idx
> -1);
3877 /* Assign the qualifiers. */
3878 assign_qualifier_sequence (inst_base
,
3879 opcode
->qualifiers_list
[qlf_idx
]);
3881 /* Print the hint. */
3882 output_info (_(" did you mean this?"));
3883 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
3884 print_operands (buf
, opcode
, inst_base
->operands
);
3885 output_info (_(" %s"), buf
);
3887 /* Print out other variant(s) if there is any. */
3889 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
3890 output_info (_(" other valid variant(s):"));
3892 /* For each pattern. */
3893 qualifiers_list
= opcode
->qualifiers_list
;
3894 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
3896 /* Most opcodes has much fewer patterns in the list.
3897 First NIL qualifier indicates the end in the list. */
3898 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
3903 /* Mnemonics name. */
3904 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
3906 /* Assign the qualifiers. */
3907 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
3909 /* Print instruction. */
3910 print_operands (buf
, opcode
, inst_base
->operands
);
3912 output_info (_(" %s"), buf
);
3918 case AARCH64_OPDE_OUT_OF_RANGE
:
3919 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
3920 detail
->error
? detail
->error
: _("immediate value"),
3921 detail
->data
[0], detail
->data
[1], detail
->index
+ 1, str
);
3924 case AARCH64_OPDE_REG_LIST
:
3925 if (detail
->data
[0] == 1)
3926 as_bad (_("invalid number of registers in the list; "
3927 "only 1 register is expected at operand %d -- `%s'"),
3928 detail
->index
+ 1, str
);
3930 as_bad (_("invalid number of registers in the list; "
3931 "%d registers are expected at operand %d -- `%s'"),
3932 detail
->data
[0], detail
->index
+ 1, str
);
3935 case AARCH64_OPDE_UNALIGNED
:
3936 as_bad (_("immediate value should be a multiple of "
3937 "%d at operand %d -- `%s'"),
3938 detail
->data
[0], detail
->index
+ 1, str
);
3947 /* Process and output the error message about the operand mismatching.
3949 When this function is called, the operand error information had
3950 been collected for an assembly line and there will be multiple
3951 errors in the case of mulitple instruction templates; output the
3952 error message that most closely describes the problem. */
3955 output_operand_error_report (char *str
)
3957 int largest_error_pos
;
3958 const char *msg
= NULL
;
3959 enum aarch64_operand_error_kind kind
;
3960 operand_error_record
*curr
;
3961 operand_error_record
*head
= operand_error_report
.head
;
3962 operand_error_record
*record
= NULL
;
3964 /* No error to report. */
3968 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
3970 /* Only one error. */
3971 if (head
== operand_error_report
.tail
)
3973 DEBUG_TRACE ("single opcode entry with error kind: %s",
3974 operand_mismatch_kind_names
[head
->detail
.kind
]);
3975 output_operand_error_record (head
, str
);
3979 /* Find the error kind of the highest severity. */
3980 DEBUG_TRACE ("multiple opcode entres with error kind");
3981 kind
= AARCH64_OPDE_NIL
;
3982 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
3984 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
3985 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
3986 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
3987 kind
= curr
->detail
.kind
;
3989 gas_assert (kind
!= AARCH64_OPDE_NIL
);
3991 /* Pick up one of errors of KIND to report. */
3992 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
3993 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
3995 if (curr
->detail
.kind
!= kind
)
3997 /* If there are multiple errors, pick up the one with the highest
3998 mismatching operand index. In the case of multiple errors with
3999 the equally highest operand index, pick up the first one or the
4000 first one with non-NULL error message. */
4001 if (curr
->detail
.index
> largest_error_pos
4002 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4003 && curr
->detail
.error
!= NULL
))
4005 largest_error_pos
= curr
->detail
.index
;
4007 msg
= record
->detail
.error
;
4011 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4012 DEBUG_TRACE ("Pick up error kind %s to report",
4013 operand_mismatch_kind_names
[record
->detail
.kind
]);
4016 output_operand_error_record (record
, str
);
4019 /* Write an AARCH64 instruction to buf - always little-endian. */
4021 put_aarch64_insn (char *buf
, uint32_t insn
)
4023 unsigned char *where
= (unsigned char *) buf
;
4025 where
[1] = insn
>> 8;
4026 where
[2] = insn
>> 16;
4027 where
[3] = insn
>> 24;
4031 get_aarch64_insn (char *buf
)
4033 unsigned char *where
= (unsigned char *) buf
;
4035 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4040 output_inst (struct aarch64_inst
*new_inst
)
4044 to
= frag_more (INSN_SIZE
);
4046 frag_now
->tc_frag_data
.recorded
= 1;
4048 put_aarch64_insn (to
, inst
.base
.value
);
4050 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4052 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4053 INSN_SIZE
, &inst
.reloc
.exp
,
4056 DEBUG_TRACE ("Prepared relocation fix up");
4057 /* Don't check the addend value against the instruction size,
4058 that's the job of our code in md_apply_fix(). */
4059 fixp
->fx_no_overflow
= 1;
4060 if (new_inst
!= NULL
)
4061 fixp
->tc_fix_data
.inst
= new_inst
;
4062 if (aarch64_gas_internal_fixup_p ())
4064 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4065 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4066 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4070 dwarf2_emit_insn (INSN_SIZE
);
4073 /* Link together opcodes of the same name. */
4077 aarch64_opcode
*opcode
;
4078 struct templates
*next
;
4081 typedef struct templates templates
;
4084 lookup_mnemonic (const char *start
, int len
)
4086 templates
*templ
= NULL
;
4088 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4092 /* Subroutine of md_assemble, responsible for looking up the primary
4093 opcode from the mnemonic the user wrote. STR points to the
4094 beginning of the mnemonic. */
4097 opcode_lookup (char **str
)
4100 const aarch64_cond
*cond
;
4104 /* Scan up to the end of the mnemonic, which must end in white space,
4105 '.', or end of string. */
4106 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4113 inst
.cond
= COND_ALWAYS
;
4115 /* Handle a possible condition. */
4118 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4121 inst
.cond
= cond
->value
;
4135 if (inst
.cond
== COND_ALWAYS
)
4137 /* Look for unaffixed mnemonic. */
4138 return lookup_mnemonic (base
, len
);
4142 /* append ".c" to mnemonic if conditional */
4143 memcpy (condname
, base
, len
);
4144 memcpy (condname
+ len
, ".c", 2);
4147 return lookup_mnemonic (base
, len
);
4153 /* Internal helper routine converting a vector neon_type_el structure
4154 *VECTYPE to a corresponding operand qualifier. */
4156 static inline aarch64_opnd_qualifier_t
4157 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4159 /* Element size in bytes indexed by neon_el_type. */
4160 const unsigned char ele_size
[5]
4163 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4164 goto vectype_conversion_fail
;
4166 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4168 if (vectype
->defined
& NTA_HASINDEX
)
4169 /* Vector element register. */
4170 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4173 /* Vector register. */
4174 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4176 if (reg_size
!= 16 && reg_size
!= 8)
4177 goto vectype_conversion_fail
;
4178 /* The conversion is calculated based on the relation of the order of
4179 qualifiers to the vector element size and vector register size. */
4180 offset
= (vectype
->type
== NT_q
)
4181 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4182 gas_assert (offset
<= 8);
4183 return AARCH64_OPND_QLF_V_8B
+ offset
;
4186 vectype_conversion_fail
:
4187 first_error (_("bad vector arrangement type"));
4188 return AARCH64_OPND_QLF_NIL
;
4191 /* Process an optional operand that is found omitted from the assembly line.
4192 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4193 instruction's opcode entry while IDX is the index of this omitted operand.
4197 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4198 int idx
, aarch64_opnd_info
*operand
)
4200 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4201 gas_assert (optional_operand_p (opcode
, idx
));
4202 gas_assert (!operand
->present
);
4206 case AARCH64_OPND_Rd
:
4207 case AARCH64_OPND_Rn
:
4208 case AARCH64_OPND_Rm
:
4209 case AARCH64_OPND_Rt
:
4210 case AARCH64_OPND_Rt2
:
4211 case AARCH64_OPND_Rs
:
4212 case AARCH64_OPND_Ra
:
4213 case AARCH64_OPND_Rt_SYS
:
4214 case AARCH64_OPND_Rd_SP
:
4215 case AARCH64_OPND_Rn_SP
:
4216 case AARCH64_OPND_Fd
:
4217 case AARCH64_OPND_Fn
:
4218 case AARCH64_OPND_Fm
:
4219 case AARCH64_OPND_Fa
:
4220 case AARCH64_OPND_Ft
:
4221 case AARCH64_OPND_Ft2
:
4222 case AARCH64_OPND_Sd
:
4223 case AARCH64_OPND_Sn
:
4224 case AARCH64_OPND_Sm
:
4225 case AARCH64_OPND_Vd
:
4226 case AARCH64_OPND_Vn
:
4227 case AARCH64_OPND_Vm
:
4228 case AARCH64_OPND_VdD1
:
4229 case AARCH64_OPND_VnD1
:
4230 operand
->reg
.regno
= default_value
;
4233 case AARCH64_OPND_Ed
:
4234 case AARCH64_OPND_En
:
4235 case AARCH64_OPND_Em
:
4236 operand
->reglane
.regno
= default_value
;
4239 case AARCH64_OPND_IDX
:
4240 case AARCH64_OPND_BIT_NUM
:
4241 case AARCH64_OPND_IMMR
:
4242 case AARCH64_OPND_IMMS
:
4243 case AARCH64_OPND_SHLL_IMM
:
4244 case AARCH64_OPND_IMM_VLSL
:
4245 case AARCH64_OPND_IMM_VLSR
:
4246 case AARCH64_OPND_CCMP_IMM
:
4247 case AARCH64_OPND_FBITS
:
4248 case AARCH64_OPND_UIMM4
:
4249 case AARCH64_OPND_UIMM3_OP1
:
4250 case AARCH64_OPND_UIMM3_OP2
:
4251 case AARCH64_OPND_IMM
:
4252 case AARCH64_OPND_WIDTH
:
4253 case AARCH64_OPND_UIMM7
:
4254 case AARCH64_OPND_NZCV
:
4255 operand
->imm
.value
= default_value
;
4258 case AARCH64_OPND_EXCEPTION
:
4259 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4262 case AARCH64_OPND_BARRIER_ISB
:
4263 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4270 /* Process the relocation type for move wide instructions.
4271 Return TRUE on success; otherwise return FALSE. */
4274 process_movw_reloc_info (void)
4279 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4281 if (inst
.base
.opcode
->op
== OP_MOVK
)
4282 switch (inst
.reloc
.type
)
4284 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4285 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4286 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4287 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4288 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4289 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4290 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4291 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4293 (_("the specified relocation type is not allowed for MOVK"));
4299 switch (inst
.reloc
.type
)
4301 case BFD_RELOC_AARCH64_MOVW_G0
:
4302 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4303 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4304 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4305 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4308 case BFD_RELOC_AARCH64_MOVW_G1
:
4309 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4310 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4311 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4312 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4315 case BFD_RELOC_AARCH64_MOVW_G2
:
4316 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4317 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4318 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4321 set_fatal_syntax_error
4322 (_("the specified relocation type is not allowed for 32-bit "
4328 case BFD_RELOC_AARCH64_MOVW_G3
:
4331 set_fatal_syntax_error
4332 (_("the specified relocation type is not allowed for 32-bit "
4339 /* More cases should be added when more MOVW-related relocation types
4340 are supported in GAS. */
4341 gas_assert (aarch64_gas_internal_fixup_p ());
4342 /* The shift amount should have already been set by the parser. */
4345 inst
.base
.operands
[1].shifter
.amount
= shift
;
4349 /* A primitive log caculator. */
4351 static inline unsigned int
4352 get_logsz (unsigned int size
)
4354 const unsigned char ls
[16] =
4355 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4361 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4362 return ls
[size
- 1];
4365 /* Determine and return the real reloc type code for an instruction
4366 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4368 static inline bfd_reloc_code_real_type
4369 ldst_lo12_determine_real_reloc_type (void)
4372 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4373 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4375 const bfd_reloc_code_real_type reloc_ldst_lo12
[5] = {
4376 BFD_RELOC_AARCH64_LDST8_LO12
, BFD_RELOC_AARCH64_LDST16_LO12
,
4377 BFD_RELOC_AARCH64_LDST32_LO12
, BFD_RELOC_AARCH64_LDST64_LO12
,
4378 BFD_RELOC_AARCH64_LDST128_LO12
4381 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
);
4382 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4384 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4386 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4388 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4390 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4391 gas_assert (logsz
>= 0 && logsz
<= 4);
4393 return reloc_ldst_lo12
[logsz
];
4396 /* Check whether a register list REGINFO is valid. The registers must be
4397 numbered in increasing order (modulo 32), in increments of one or two.
4399 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4402 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4405 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4407 uint32_t i
, nb_regs
, prev_regno
, incr
;
4409 nb_regs
= 1 + (reginfo
& 0x3);
4411 prev_regno
= reginfo
& 0x1f;
4412 incr
= accept_alternate
? 2 : 1;
4414 for (i
= 1; i
< nb_regs
; ++i
)
4416 uint32_t curr_regno
;
4418 curr_regno
= reginfo
& 0x1f;
4419 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4421 prev_regno
= curr_regno
;
4427 /* Generic instruction operand parser. This does no encoding and no
4428 semantic validation; it merely squirrels values away in the inst
4429 structure. Returns TRUE or FALSE depending on whether the
4430 specified grammar matched. */
4433 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4436 char *backtrack_pos
= 0;
4437 const enum aarch64_opnd
*operands
= opcode
->operands
;
4440 skip_whitespace (str
);
4442 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4445 int isreg32
, isregzero
;
4446 int comma_skipped_p
= 0;
4447 aarch64_reg_type rtype
;
4448 struct neon_type_el vectype
;
4449 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4451 DEBUG_TRACE ("parse operand %d", i
);
4453 /* Assign the operand code. */
4454 info
->type
= operands
[i
];
4456 if (optional_operand_p (opcode
, i
))
4458 /* Remember where we are in case we need to backtrack. */
4459 gas_assert (!backtrack_pos
);
4460 backtrack_pos
= str
;
4463 /* Expect comma between operands; the backtrack mechanizm will take
4464 care of cases of omitted optional operand. */
4465 if (i
> 0 && ! skip_past_char (&str
, ','))
4467 set_syntax_error (_("comma expected between operands"));
4471 comma_skipped_p
= 1;
4473 switch (operands
[i
])
4475 case AARCH64_OPND_Rd
:
4476 case AARCH64_OPND_Rn
:
4477 case AARCH64_OPND_Rm
:
4478 case AARCH64_OPND_Rt
:
4479 case AARCH64_OPND_Rt2
:
4480 case AARCH64_OPND_Rs
:
4481 case AARCH64_OPND_Ra
:
4482 case AARCH64_OPND_Rt_SYS
:
4483 po_int_reg_or_fail (1, 0);
4486 case AARCH64_OPND_Rd_SP
:
4487 case AARCH64_OPND_Rn_SP
:
4488 po_int_reg_or_fail (0, 1);
4491 case AARCH64_OPND_Rm_EXT
:
4492 case AARCH64_OPND_Rm_SFT
:
4493 po_misc_or_fail (parse_shifter_operand
4494 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4496 : SHIFTED_LOGIC_IMM
)));
4497 if (!info
->shifter
.operator_present
)
4499 /* Default to LSL if not present. Libopcodes prefers shifter
4500 kind to be explicit. */
4501 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4502 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4503 /* For Rm_EXT, libopcodes will carry out further check on whether
4504 or not stack pointer is used in the instruction (Recall that
4505 "the extend operator is not optional unless at least one of
4506 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4510 case AARCH64_OPND_Fd
:
4511 case AARCH64_OPND_Fn
:
4512 case AARCH64_OPND_Fm
:
4513 case AARCH64_OPND_Fa
:
4514 case AARCH64_OPND_Ft
:
4515 case AARCH64_OPND_Ft2
:
4516 case AARCH64_OPND_Sd
:
4517 case AARCH64_OPND_Sn
:
4518 case AARCH64_OPND_Sm
:
4519 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4520 if (val
== PARSE_FAIL
)
4522 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4525 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4527 info
->reg
.regno
= val
;
4528 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4531 case AARCH64_OPND_Vd
:
4532 case AARCH64_OPND_Vn
:
4533 case AARCH64_OPND_Vm
:
4534 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4535 if (val
== PARSE_FAIL
)
4537 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4540 if (vectype
.defined
& NTA_HASINDEX
)
4543 info
->reg
.regno
= val
;
4544 info
->qualifier
= vectype_to_qualifier (&vectype
);
4545 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4549 case AARCH64_OPND_VdD1
:
4550 case AARCH64_OPND_VnD1
:
4551 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4552 if (val
== PARSE_FAIL
)
4554 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4557 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4559 set_fatal_syntax_error
4560 (_("the top half of a 128-bit FP/SIMD register is expected"));
4563 info
->reg
.regno
= val
;
4564 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4565 here; it is correct for the purpose of encoding/decoding since
4566 only the register number is explicitly encoded in the related
4567 instructions, although this appears a bit hacky. */
4568 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4571 case AARCH64_OPND_Ed
:
4572 case AARCH64_OPND_En
:
4573 case AARCH64_OPND_Em
:
4574 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4575 if (val
== PARSE_FAIL
)
4577 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4580 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
4583 info
->reglane
.regno
= val
;
4584 info
->reglane
.index
= vectype
.index
;
4585 info
->qualifier
= vectype_to_qualifier (&vectype
);
4586 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4590 case AARCH64_OPND_LVn
:
4591 case AARCH64_OPND_LVt
:
4592 case AARCH64_OPND_LVt_AL
:
4593 case AARCH64_OPND_LEt
:
4594 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
4596 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
4598 set_fatal_syntax_error (_("invalid register list"));
4601 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
4602 info
->reglist
.num_regs
= (val
& 0x3) + 1;
4603 if (operands
[i
] == AARCH64_OPND_LEt
)
4605 if (!(vectype
.defined
& NTA_HASINDEX
))
4607 info
->reglist
.has_index
= 1;
4608 info
->reglist
.index
= vectype
.index
;
4610 else if (!(vectype
.defined
& NTA_HASTYPE
))
4612 info
->qualifier
= vectype_to_qualifier (&vectype
);
4613 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4617 case AARCH64_OPND_Cn
:
4618 case AARCH64_OPND_Cm
:
4619 po_reg_or_fail (REG_TYPE_CN
);
4622 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
4625 inst
.base
.operands
[i
].reg
.regno
= val
;
4628 case AARCH64_OPND_SHLL_IMM
:
4629 case AARCH64_OPND_IMM_VLSR
:
4630 po_imm_or_fail (1, 64);
4631 info
->imm
.value
= val
;
4634 case AARCH64_OPND_CCMP_IMM
:
4635 case AARCH64_OPND_FBITS
:
4636 case AARCH64_OPND_UIMM4
:
4637 case AARCH64_OPND_UIMM3_OP1
:
4638 case AARCH64_OPND_UIMM3_OP2
:
4639 case AARCH64_OPND_IMM_VLSL
:
4640 case AARCH64_OPND_IMM
:
4641 case AARCH64_OPND_WIDTH
:
4642 po_imm_nc_or_fail ();
4643 info
->imm
.value
= val
;
4646 case AARCH64_OPND_UIMM7
:
4647 po_imm_or_fail (0, 127);
4648 info
->imm
.value
= val
;
4651 case AARCH64_OPND_IDX
:
4652 case AARCH64_OPND_BIT_NUM
:
4653 case AARCH64_OPND_IMMR
:
4654 case AARCH64_OPND_IMMS
:
4655 po_imm_or_fail (0, 63);
4656 info
->imm
.value
= val
;
4659 case AARCH64_OPND_IMM0
:
4660 po_imm_nc_or_fail ();
4663 set_fatal_syntax_error (_("immediate zero expected"));
4666 info
->imm
.value
= 0;
4669 case AARCH64_OPND_FPIMM0
:
4672 bfd_boolean res1
= FALSE
, res2
= FALSE
;
4673 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4674 it is probably not worth the effort to support it. */
4675 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
))
4676 && !(res2
= parse_constant_immediate (&str
, &val
)))
4678 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
4680 info
->imm
.value
= 0;
4681 info
->imm
.is_fp
= 1;
4684 set_fatal_syntax_error (_("immediate zero expected"));
4688 case AARCH64_OPND_IMM_MOV
:
4691 if (reg_name_p (str
, REG_TYPE_R_Z_SP
))
4694 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
4696 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4697 later. fix_mov_imm_insn will try to determine a machine
4698 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4699 message if the immediate cannot be moved by a single
4701 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
4702 inst
.base
.operands
[i
].skip
= 1;
4706 case AARCH64_OPND_SIMD_IMM
:
4707 case AARCH64_OPND_SIMD_IMM_SFT
:
4708 if (! parse_big_immediate (&str
, &val
))
4710 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4712 /* need_libopcodes_p */ 1,
4715 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4716 shift, we don't check it here; we leave the checking to
4717 the libopcodes (operand_general_constraint_met_p). By
4718 doing this, we achieve better diagnostics. */
4719 if (skip_past_comma (&str
)
4720 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
4722 if (!info
->shifter
.operator_present
4723 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
4725 /* Default to LSL if not present. Libopcodes prefers shifter
4726 kind to be explicit. */
4727 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4728 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4732 case AARCH64_OPND_FPIMM
:
4733 case AARCH64_OPND_SIMD_FPIMM
:
4736 if (! parse_aarch64_imm_float (&str
, &qfloat
))
4740 set_fatal_syntax_error (_("invalid floating-point constant"));
4743 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
4744 inst
.base
.operands
[i
].imm
.is_fp
= 1;
4748 case AARCH64_OPND_LIMM
:
4749 po_misc_or_fail (parse_shifter_operand (&str
, info
,
4750 SHIFTED_LOGIC_IMM
));
4751 if (info
->shifter
.operator_present
)
4753 set_fatal_syntax_error
4754 (_("shift not allowed for bitmask immediate"));
4757 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4759 /* need_libopcodes_p */ 1,
4763 case AARCH64_OPND_AIMM
:
4764 if (opcode
->op
== OP_ADD
)
4765 /* ADD may have relocation types. */
4766 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
4767 SHIFTED_ARITH_IMM
));
4769 po_misc_or_fail (parse_shifter_operand (&str
, info
,
4770 SHIFTED_ARITH_IMM
));
4771 switch (inst
.reloc
.type
)
4773 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
4774 info
->shifter
.amount
= 12;
4776 case BFD_RELOC_UNUSED
:
4777 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
4778 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
4779 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
4780 inst
.reloc
.pc_rel
= 0;
4785 info
->imm
.value
= 0;
4786 if (!info
->shifter
.operator_present
)
4788 /* Default to LSL if not present. Libopcodes prefers shifter
4789 kind to be explicit. */
4790 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4791 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4795 case AARCH64_OPND_HALF
:
4797 /* #<imm16> or relocation. */
4798 int internal_fixup_p
;
4799 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
4800 if (internal_fixup_p
)
4801 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
4802 skip_whitespace (str
);
4803 if (skip_past_comma (&str
))
4805 /* {, LSL #<shift>} */
4806 if (! aarch64_gas_internal_fixup_p ())
4808 set_fatal_syntax_error (_("can't mix relocation modifier "
4809 "with explicit shift"));
4812 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
4815 inst
.base
.operands
[i
].shifter
.amount
= 0;
4816 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
4817 inst
.base
.operands
[i
].imm
.value
= 0;
4818 if (! process_movw_reloc_info ())
4823 case AARCH64_OPND_EXCEPTION
:
4824 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
4825 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4827 /* need_libopcodes_p */ 0,
4831 case AARCH64_OPND_NZCV
:
4833 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
4837 info
->imm
.value
= nzcv
->value
;
4840 po_imm_or_fail (0, 15);
4841 info
->imm
.value
= val
;
4845 case AARCH64_OPND_COND
:
4846 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
4848 if (info
->cond
== NULL
)
4850 set_syntax_error (_("invalid condition"));
4855 case AARCH64_OPND_ADDR_ADRP
:
4856 po_misc_or_fail (parse_adrp (&str
));
4857 /* Clear the value as operand needs to be relocated. */
4858 info
->imm
.value
= 0;
4861 case AARCH64_OPND_ADDR_PCREL14
:
4862 case AARCH64_OPND_ADDR_PCREL19
:
4863 case AARCH64_OPND_ADDR_PCREL21
:
4864 case AARCH64_OPND_ADDR_PCREL26
:
4865 po_misc_or_fail (parse_address_reloc (&str
, info
));
4866 if (!info
->addr
.pcrel
)
4868 set_syntax_error (_("invalid pc-relative address"));
4871 if (inst
.gen_lit_pool
4872 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
4874 /* Only permit "=value" in the literal load instructions.
4875 The literal will be generated by programmer_friendly_fixup. */
4876 set_syntax_error (_("invalid use of \"=immediate\""));
4879 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
4881 set_syntax_error (_("unrecognized relocation suffix"));
4884 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
4886 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
4887 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4891 info
->imm
.value
= 0;
4892 switch (opcode
->iclass
)
4896 /* e.g. CBZ or B.COND */
4897 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
4898 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
4902 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
4903 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
4907 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
4908 inst
.reloc
.type
= (opcode
->op
== OP_BL
)
4909 ? BFD_RELOC_AARCH64_CALL26
: BFD_RELOC_AARCH64_JUMP26
;
4912 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
4913 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
4916 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
4917 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
4923 inst
.reloc
.pc_rel
= 1;
4927 case AARCH64_OPND_ADDR_SIMPLE
:
4928 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
4929 /* [<Xn|SP>{, #<simm>}] */
4930 po_char_or_fail ('[');
4931 po_reg_or_fail (REG_TYPE_R64_SP
);
4932 /* Accept optional ", #0". */
4933 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
4934 && skip_past_char (&str
, ','))
4936 skip_past_char (&str
, '#');
4937 if (! skip_past_char (&str
, '0'))
4939 set_fatal_syntax_error
4940 (_("the optional immediate offset can only be 0"));
4944 po_char_or_fail (']');
4945 info
->addr
.base_regno
= val
;
4948 case AARCH64_OPND_ADDR_REGOFF
:
4949 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
4950 po_misc_or_fail (parse_address (&str
, info
, 0));
4951 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
4952 || !info
->addr
.preind
|| info
->addr
.postind
4953 || info
->addr
.writeback
)
4955 set_syntax_error (_("invalid addressing mode"));
4958 if (!info
->shifter
.operator_present
)
4960 /* Default to LSL if not present. Libopcodes prefers shifter
4961 kind to be explicit. */
4962 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4963 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4965 /* Qualifier to be deduced by libopcodes. */
4968 case AARCH64_OPND_ADDR_SIMM7
:
4969 po_misc_or_fail (parse_address (&str
, info
, 0));
4970 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
4971 || (!info
->addr
.preind
&& !info
->addr
.postind
))
4973 set_syntax_error (_("invalid addressing mode"));
4976 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4978 /* need_libopcodes_p */ 1,
4982 case AARCH64_OPND_ADDR_SIMM9
:
4983 case AARCH64_OPND_ADDR_SIMM9_2
:
4984 po_misc_or_fail (parse_address_reloc (&str
, info
));
4985 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
4986 || (!info
->addr
.preind
&& !info
->addr
.postind
)
4987 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
4988 && info
->addr
.writeback
))
4990 set_syntax_error (_("invalid addressing mode"));
4993 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4995 set_syntax_error (_("relocation not allowed"));
4998 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5000 /* need_libopcodes_p */ 1,
5004 case AARCH64_OPND_ADDR_UIMM12
:
5005 po_misc_or_fail (parse_address_reloc (&str
, info
));
5006 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5007 || !info
->addr
.preind
|| info
->addr
.writeback
)
5009 set_syntax_error (_("invalid addressing mode"));
5012 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5013 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5014 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
)
5015 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5016 /* Leave qualifier to be determined by libopcodes. */
5019 case AARCH64_OPND_SIMD_ADDR_POST
:
5020 /* [<Xn|SP>], <Xm|#<amount>> */
5021 po_misc_or_fail (parse_address (&str
, info
, 1));
5022 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5024 set_syntax_error (_("invalid addressing mode"));
5027 if (!info
->addr
.offset
.is_reg
)
5029 if (inst
.reloc
.exp
.X_op
== O_constant
)
5030 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5033 set_fatal_syntax_error
5034 (_("writeback value should be an immediate constant"));
5041 case AARCH64_OPND_SYSREG
:
5042 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1)) == FALSE
)
5044 set_syntax_error (_("unknown or missing system register name"));
5047 inst
.base
.operands
[i
].sysreg
= val
;
5050 case AARCH64_OPND_PSTATEFIELD
:
5051 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0)) == FALSE
)
5053 set_syntax_error (_("unknown or missing PSTATE field name"));
5056 inst
.base
.operands
[i
].pstatefield
= val
;
5059 case AARCH64_OPND_SYSREG_IC
:
5060 inst
.base
.operands
[i
].sysins_op
=
5061 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5063 case AARCH64_OPND_SYSREG_DC
:
5064 inst
.base
.operands
[i
].sysins_op
=
5065 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5067 case AARCH64_OPND_SYSREG_AT
:
5068 inst
.base
.operands
[i
].sysins_op
=
5069 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5071 case AARCH64_OPND_SYSREG_TLBI
:
5072 inst
.base
.operands
[i
].sysins_op
=
5073 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5075 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5077 set_fatal_syntax_error ( _("unknown or missing operation name"));
5082 case AARCH64_OPND_BARRIER
:
5083 case AARCH64_OPND_BARRIER_ISB
:
5084 val
= parse_barrier (&str
);
5085 if (val
!= PARSE_FAIL
5086 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5088 /* ISB only accepts options name 'sy'. */
5090 (_("the specified option is not accepted in ISB"));
5091 /* Turn off backtrack as this optional operand is present. */
5095 /* This is an extension to accept a 0..15 immediate. */
5096 if (val
== PARSE_FAIL
)
5097 po_imm_or_fail (0, 15);
5098 info
->barrier
= aarch64_barrier_options
+ val
;
5101 case AARCH64_OPND_PRFOP
:
5102 val
= parse_pldop (&str
);
5103 /* This is an extension to accept a 0..31 immediate. */
5104 if (val
== PARSE_FAIL
)
5105 po_imm_or_fail (0, 31);
5106 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5110 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5113 /* If we get here, this operand was successfully parsed. */
5114 inst
.base
.operands
[i
].present
= 1;
5118 /* The parse routine should already have set the error, but in case
5119 not, set a default one here. */
5121 set_default_error ();
5123 if (! backtrack_pos
)
5124 goto parse_operands_return
;
5126 /* Reaching here means we are dealing with an optional operand that is
5127 omitted from the assembly line. */
5128 gas_assert (optional_operand_p (opcode
, i
));
5130 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5132 /* Try again, skipping the optional operand at backtrack_pos. */
5133 str
= backtrack_pos
;
5136 /* If this is the last operand that is optional and omitted, but without
5137 the presence of a comma. */
5138 if (i
&& comma_skipped_p
&& i
== aarch64_num_of_operands (opcode
) - 1)
5140 set_fatal_syntax_error
5141 (_("unexpected comma before the omitted optional operand"));
5142 goto parse_operands_return
;
5145 /* Clear any error record after the omitted optional operand has been
5146 successfully handled. */
5150 /* Check if we have parsed all the operands. */
5151 if (*str
!= '\0' && ! error_p ())
5153 /* Set I to the index of the last present operand; this is
5154 for the purpose of diagnostics. */
5155 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5157 set_fatal_syntax_error
5158 (_("unexpected characters following instruction"));
5161 parse_operands_return
:
5165 DEBUG_TRACE ("parsing FAIL: %s - %s",
5166 operand_mismatch_kind_names
[get_error_kind ()],
5167 get_error_message ());
5168 /* Record the operand error properly; this is useful when there
5169 are multiple instruction templates for a mnemonic name, so that
5170 later on, we can select the error that most closely describes
5172 record_operand_error (opcode
, i
, get_error_kind (),
5173 get_error_message ());
5178 DEBUG_TRACE ("parsing SUCCESS");
5183 /* It does some fix-up to provide some programmer friendly feature while
5184 keeping the libopcodes happy, i.e. libopcodes only accepts
5185 the preferred architectural syntax.
5186 Return FALSE if there is any failure; otherwise return TRUE. */
5189 programmer_friendly_fixup (aarch64_instruction
*instr
)
5191 aarch64_inst
*base
= &instr
->base
;
5192 const aarch64_opcode
*opcode
= base
->opcode
;
5193 enum aarch64_op op
= opcode
->op
;
5194 aarch64_opnd_info
*operands
= base
->operands
;
5196 DEBUG_TRACE ("enter");
5198 switch (opcode
->iclass
)
5201 /* TBNZ Xn|Wn, #uimm6, label
5202 Test and Branch Not Zero: conditionally jumps to label if bit number
5203 uimm6 in register Xn is not zero. The bit number implies the width of
5204 the register, which may be written and should be disassembled as Wn if
5205 uimm is less than 32. */
5206 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5208 if (operands
[1].imm
.value
>= 32)
5210 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5214 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5218 /* LDR Wt, label | =value
5219 As a convenience assemblers will typically permit the notation
5220 "=value" in conjunction with the pc-relative literal load instructions
5221 to automatically place an immediate value or symbolic address in a
5222 nearby literal pool and generate a hidden label which references it.
5223 ISREG has been set to 0 in the case of =value. */
5224 if (instr
->gen_lit_pool
5225 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5227 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5228 if (op
== OP_LDRSW_LIT
)
5230 if (instr
->reloc
.exp
.X_op
!= O_constant
5231 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5233 record_operand_error (opcode
, 1,
5234 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5235 _("constant expression expected"));
5238 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5240 record_operand_error (opcode
, 1,
5241 AARCH64_OPDE_OTHER_ERROR
,
5242 _("literal pool insertion failed"));
5248 /* Allow MOVI V0.16B, 97, LSL 0, although the preferred architectural
5249 syntax requires that the LSL shifter can only be used when the
5250 destination register has the shape of 4H, 8H, 2S or 4S. */
5251 if (op
== OP_V_MOVI_B
&& operands
[1].shifter
.kind
== AARCH64_MOD_LSL
5252 && (operands
[0].qualifier
== AARCH64_OPND_QLF_V_8B
5253 || operands
[0].qualifier
== AARCH64_OPND_QLF_V_16B
))
5255 if (operands
[1].shifter
.amount
!= 0)
5257 record_operand_error (opcode
, 1,
5258 AARCH64_OPDE_OTHER_ERROR
,
5259 _("shift amount non-zero"));
5262 operands
[1].shifter
.kind
= AARCH64_MOD_NONE
;
5263 operands
[1].qualifier
= AARCH64_OPND_QLF_NIL
;
5269 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5270 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5271 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5272 A programmer-friendly assembler should accept a destination Xd in
5273 place of Wd, however that is not the preferred form for disassembly.
5275 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5276 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5277 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5278 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5283 /* In the 64-bit form, the final register operand is written as Wm
5284 for all but the (possibly omitted) UXTX/LSL and SXTX
5286 As a programmer-friendly assembler, we accept e.g.
5287 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5288 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5289 int idx
= aarch64_operand_index (opcode
->operands
,
5290 AARCH64_OPND_Rm_EXT
);
5291 gas_assert (idx
== 1 || idx
== 2);
5292 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5293 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5294 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5295 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5296 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5297 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5305 DEBUG_TRACE ("exit with SUCCESS");
5309 /* A wrapper function to interface with libopcodes on encoding and
5310 record the error message if there is any.
5312 Return TRUE on success; otherwise return FALSE. */
5315 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5318 aarch64_operand_error error_info
;
5319 error_info
.kind
= AARCH64_OPDE_NIL
;
5320 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5324 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5325 record_operand_error_info (opcode
, &error_info
);
5330 #ifdef DEBUG_AARCH64
5332 dump_opcode_operands (const aarch64_opcode
*opcode
)
5335 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5337 aarch64_verbose ("\t\t opnd%d: %s", i
,
5338 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5339 ? aarch64_get_operand_name (opcode
->operands
[i
])
5340 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5344 #endif /* DEBUG_AARCH64 */
5346 /* This is the guts of the machine-dependent assembler. STR points to a
5347 machine dependent instruction. This function is supposed to emit
5348 the frags/bytes it assembles to. */
5351 md_assemble (char *str
)
5354 templates
*template;
5355 aarch64_opcode
*opcode
;
5356 aarch64_inst
*inst_base
;
5357 unsigned saved_cond
;
5359 /* Align the previous label if needed. */
5360 if (last_label_seen
!= NULL
)
5362 symbol_set_frag (last_label_seen
, frag_now
);
5363 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5364 S_SET_SEGMENT (last_label_seen
, now_seg
);
5367 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5369 DEBUG_TRACE ("\n\n");
5370 DEBUG_TRACE ("==============================");
5371 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5373 template = opcode_lookup (&p
);
5376 /* It wasn't an instruction, but it might be a register alias of
5377 the form alias .req reg directive. */
5378 if (!create_register_alias (str
, p
))
5379 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5384 skip_whitespace (p
);
5387 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5388 get_mnemonic_name (str
), str
);
5392 init_operand_error_report ();
5394 saved_cond
= inst
.cond
;
5395 reset_aarch64_instruction (&inst
);
5396 inst
.cond
= saved_cond
;
5398 /* Iterate through all opcode entries with the same mnemonic name. */
5401 opcode
= template->opcode
;
5403 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5404 #ifdef DEBUG_AARCH64
5406 dump_opcode_operands (opcode
);
5407 #endif /* DEBUG_AARCH64 */
5409 /* Check that this instruction is supported for this CPU. */
5410 if (!opcode
->avariant
5411 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5413 as_bad (_("selected processor does not support `%s'"), str
);
5417 mapping_state (MAP_INSN
);
5419 inst_base
= &inst
.base
;
5420 inst_base
->opcode
= opcode
;
5422 /* Truly conditionally executed instructions, e.g. b.cond. */
5423 if (opcode
->flags
& F_COND
)
5425 gas_assert (inst
.cond
!= COND_ALWAYS
);
5426 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5427 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5429 else if (inst
.cond
!= COND_ALWAYS
)
5431 /* It shouldn't arrive here, where the assembly looks like a
5432 conditional instruction but the found opcode is unconditional. */
5437 if (parse_operands (p
, opcode
)
5438 && programmer_friendly_fixup (&inst
)
5439 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5441 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5442 || !inst
.reloc
.need_libopcodes_p
)
5446 /* If there is relocation generated for the instruction,
5447 store the instruction information for the future fix-up. */
5448 struct aarch64_inst
*copy
;
5449 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5450 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5452 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5458 template = template->next
;
5459 if (template != NULL
)
5461 reset_aarch64_instruction (&inst
);
5462 inst
.cond
= saved_cond
;
5465 while (template != NULL
);
5467 /* Issue the error messages if any. */
5468 output_operand_error_report (str
);
5471 /* Various frobbings of labels and their addresses. */
5474 aarch64_start_line_hook (void)
5476 last_label_seen
= NULL
;
5480 aarch64_frob_label (symbolS
* sym
)
5482 last_label_seen
= sym
;
5484 dwarf2_emit_label (sym
);
5488 aarch64_data_in_code (void)
5490 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5492 *input_line_pointer
= '/';
5493 input_line_pointer
+= 5;
5494 *input_line_pointer
= 0;
5502 aarch64_canonicalize_symbol_name (char *name
)
5506 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
5507 *(name
+ len
- 5) = 0;
5512 /* Table of all register names defined by default. The user can
5513 define additional names with .req. Note that all register names
5514 should appear in both upper and lowercase variants. Some registers
5515 also have mixed-case names. */
5517 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5518 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5519 #define REGSET31(p,t) \
5520 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5521 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5522 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5523 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5524 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5525 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5526 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5527 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5528 #define REGSET(p,t) \
5529 REGSET31(p,t), REGNUM(p,31,t)
5531 /* These go into aarch64_reg_hsh hash-table. */
5532 static const reg_entry reg_names
[] = {
5533 /* Integer registers. */
5534 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
5535 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
5537 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
5538 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
5540 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
5541 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
5543 /* Coprocessor register numbers. */
5544 REGSET (c
, CN
), REGSET (C
, CN
),
5546 /* Floating-point single precision registers. */
5547 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
5549 /* Floating-point double precision registers. */
5550 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
5552 /* Floating-point half precision registers. */
5553 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
5555 /* Floating-point byte precision registers. */
5556 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
5558 /* Floating-point quad precision registers. */
5559 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
5561 /* FP/SIMD registers. */
5562 REGSET (v
, VN
), REGSET (V
, VN
),
5577 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5578 static const asm_nzcv nzcv_names
[] = {
5579 {"nzcv", B (n
, z
, c
, v
)},
5580 {"nzcV", B (n
, z
, c
, V
)},
5581 {"nzCv", B (n
, z
, C
, v
)},
5582 {"nzCV", B (n
, z
, C
, V
)},
5583 {"nZcv", B (n
, Z
, c
, v
)},
5584 {"nZcV", B (n
, Z
, c
, V
)},
5585 {"nZCv", B (n
, Z
, C
, v
)},
5586 {"nZCV", B (n
, Z
, C
, V
)},
5587 {"Nzcv", B (N
, z
, c
, v
)},
5588 {"NzcV", B (N
, z
, c
, V
)},
5589 {"NzCv", B (N
, z
, C
, v
)},
5590 {"NzCV", B (N
, z
, C
, V
)},
5591 {"NZcv", B (N
, Z
, c
, v
)},
5592 {"NZcV", B (N
, Z
, c
, V
)},
5593 {"NZCv", B (N
, Z
, C
, v
)},
5594 {"NZCV", B (N
, Z
, C
, V
)}
5607 /* MD interface: bits in the object file. */
5609 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5610 for use in the a.out file, and stores them in the array pointed to by buf.
5611 This knows about the endian-ness of the target machine and does
5612 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5613 2 (short) and 4 (long) Floating numbers are put out as a series of
5614 LITTLENUMS (shorts, here at least). */
5617 md_number_to_chars (char *buf
, valueT val
, int n
)
5619 if (target_big_endian
)
5620 number_to_chars_bigendian (buf
, val
, n
);
5622 number_to_chars_littleendian (buf
, val
, n
);
5625 /* MD interface: Sections. */
5627 /* Estimate the size of a frag before relaxing. Assume everything fits in
5631 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
5637 /* Round up a section size to the appropriate boundary. */
5640 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5645 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5646 of an rs_align_code fragment. */
5649 aarch64_handle_align (fragS
* fragP
)
5651 /* NOP = d503201f */
5652 /* AArch64 instructions are always little-endian. */
5653 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5655 int bytes
, fix
, noop_size
;
5659 if (fragP
->fr_type
!= rs_align_code
)
5662 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5663 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
5666 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
5667 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
5670 gas_assert (fragP
->tc_frag_data
.recorded
);
5673 noop
= aarch64_noop
;
5674 noop_size
= sizeof (aarch64_noop
);
5675 fragP
->fr_var
= noop_size
;
5677 if (bytes
& (noop_size
- 1))
5679 fix
= bytes
& (noop_size
- 1);
5681 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
5688 while (bytes
>= noop_size
)
5690 memcpy (p
, noop
, noop_size
);
5696 fragP
->fr_fix
+= fix
;
5699 /* Called from md_do_align. Used to create an alignment
5700 frag in a code section. */
5703 aarch64_frag_align_code (int n
, int max
)
5707 /* We assume that there will never be a requirement
5708 to support alignments greater than x bytes. */
5709 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
5711 ("alignments greater than %d bytes not supported in .text sections"),
5712 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
5714 p
= frag_var (rs_align_code
,
5715 MAX_MEM_FOR_RS_ALIGN_CODE
,
5717 (relax_substateT
) max
,
5718 (symbolS
*) NULL
, (offsetT
) n
, (char *) NULL
);
5722 /* Perform target specific initialisation of a frag.
5723 Note - despite the name this initialisation is not done when the frag
5724 is created, but only when its type is assigned. A frag can be created
5725 and used a long time before its type is set, so beware of assuming that
5726 this initialisationis performed first. */
5730 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
5731 int max_chars ATTRIBUTE_UNUSED
)
5735 #else /* OBJ_ELF is defined. */
5737 aarch64_init_frag (fragS
* fragP
, int max_chars
)
5739 /* Record a mapping symbol for alignment frags. We will delete this
5740 later if the alignment ends up empty. */
5741 if (!fragP
->tc_frag_data
.recorded
)
5743 fragP
->tc_frag_data
.recorded
= 1;
5744 switch (fragP
->fr_type
)
5749 mapping_state_2 (MAP_DATA
, max_chars
);
5752 mapping_state_2 (MAP_INSN
, max_chars
);
5760 /* Initialize the DWARF-2 unwind information for this procedure. */
5763 tc_aarch64_frame_initial_instructions (void)
5765 cfi_add_CFA_def_cfa (REG_SP
, 0);
5767 #endif /* OBJ_ELF */
5769 /* Convert REGNAME to a DWARF-2 register number. */
5772 tc_aarch64_regname_to_dw2regnum (char *regname
)
5774 const reg_entry
*reg
= parse_reg (®name
);
5780 case REG_TYPE_SP_32
:
5781 case REG_TYPE_SP_64
:
5796 /* MD interface: Symbol and relocation handling. */
5798 /* Return the address within the segment that a PC-relative fixup is
5799 relative to. For AArch64 PC-relative fixups applied to instructions
5800 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
5803 md_pcrel_from_section (fixS
* fixP
, segT seg
)
5805 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5807 /* If this is pc-relative and we are going to emit a relocation
5808 then we just want to put out any pipeline compensation that the linker
5809 will need. Otherwise we want to use the calculated base. */
5811 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
5812 || aarch64_force_relocation (fixP
)))
5815 /* AArch64 should be consistent for all pc-relative relocations. */
5816 return base
+ AARCH64_PCREL_OFFSET
;
5819 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5820 Otherwise we have no need to default values of symbols. */
5823 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5826 if (name
[0] == '_' && name
[1] == 'G'
5827 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
5831 if (symbol_find (name
))
5832 as_bad (_("GOT already in the symbol table"));
5834 GOT_symbol
= symbol_new (name
, undefined_section
,
5835 (valueT
) 0, &zero_address_frag
);
5845 /* Return non-zero if the indicated VALUE has overflowed the maximum
5846 range expressible by a unsigned number with the indicated number of
5850 unsigned_overflow (valueT value
, unsigned bits
)
5853 if (bits
>= sizeof (valueT
) * 8)
5855 lim
= (valueT
) 1 << bits
;
5856 return (value
>= lim
);
5860 /* Return non-zero if the indicated VALUE has overflowed the maximum
5861 range expressible by an signed number with the indicated number of
5865 signed_overflow (offsetT value
, unsigned bits
)
5868 if (bits
>= sizeof (offsetT
) * 8)
5870 lim
= (offsetT
) 1 << (bits
- 1);
5871 return (value
< -lim
|| value
>= lim
);
5874 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
5875 unsigned immediate offset load/store instruction, try to encode it as
5876 an unscaled, 9-bit, signed immediate offset load/store instruction.
5877 Return TRUE if it is successful; otherwise return FALSE.
5879 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
5880 in response to the standard LDR/STR mnemonics when the immediate offset is
5881 unambiguous, i.e. when it is negative or unaligned. */
5884 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
5887 enum aarch64_op new_op
;
5888 const aarch64_opcode
*new_opcode
;
5890 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
5892 switch (instr
->opcode
->op
)
5894 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
5895 case OP_STRB_POS
: new_op
= OP_STURB
; break;
5896 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
5897 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
5898 case OP_STRH_POS
: new_op
= OP_STURH
; break;
5899 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
5900 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
5901 case OP_STR_POS
: new_op
= OP_STUR
; break;
5902 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
5903 case OP_STRF_POS
: new_op
= OP_STURV
; break;
5904 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
5905 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
5906 default: new_op
= OP_NIL
; break;
5909 if (new_op
== OP_NIL
)
5912 new_opcode
= aarch64_get_opcode (new_op
);
5913 gas_assert (new_opcode
!= NULL
);
5915 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
5916 instr
->opcode
->op
, new_opcode
->op
);
5918 aarch64_replace_opcode (instr
, new_opcode
);
5920 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
5921 qualifier matching may fail because the out-of-date qualifier will
5922 prevent the operand being updated with a new and correct qualifier. */
5923 idx
= aarch64_operand_index (instr
->opcode
->operands
,
5924 AARCH64_OPND_ADDR_SIMM9
);
5925 gas_assert (idx
== 1);
5926 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
5928 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
5930 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
5936 /* Called by fix_insn to fix a MOV immediate alias instruction.
5938 Operand for a generic move immediate instruction, which is an alias
5939 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
5940 a 32-bit/64-bit immediate value into general register. An assembler error
5941 shall result if the immediate cannot be created by a single one of these
5942 instructions. If there is a choice, then to ensure reversability an
5943 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
5946 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
5948 const aarch64_opcode
*opcode
;
5950 /* Need to check if the destination is SP/ZR. The check has to be done
5951 before any aarch64_replace_opcode. */
5952 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
5953 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
5955 instr
->operands
[1].imm
.value
= value
;
5956 instr
->operands
[1].skip
= 0;
5960 /* Try the MOVZ alias. */
5961 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
5962 aarch64_replace_opcode (instr
, opcode
);
5963 if (aarch64_opcode_encode (instr
->opcode
, instr
,
5964 &instr
->value
, NULL
, NULL
))
5966 put_aarch64_insn (buf
, instr
->value
);
5969 /* Try the MOVK alias. */
5970 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
5971 aarch64_replace_opcode (instr
, opcode
);
5972 if (aarch64_opcode_encode (instr
->opcode
, instr
,
5973 &instr
->value
, NULL
, NULL
))
5975 put_aarch64_insn (buf
, instr
->value
);
5980 if (try_mov_bitmask_p
)
5982 /* Try the ORR alias. */
5983 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
5984 aarch64_replace_opcode (instr
, opcode
);
5985 if (aarch64_opcode_encode (instr
->opcode
, instr
,
5986 &instr
->value
, NULL
, NULL
))
5988 put_aarch64_insn (buf
, instr
->value
);
5993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5994 _("immediate cannot be moved by a single instruction"));
5997 /* An instruction operand which is immediate related may have symbol used
5998 in the assembly, e.g.
6001 .set u32, 0x00ffff00
6003 At the time when the assembly instruction is parsed, a referenced symbol,
6004 like 'u32' in the above example may not have been seen; a fixS is created
6005 in such a case and is handled here after symbols have been resolved.
6006 Instruction is fixed up with VALUE using the information in *FIXP plus
6007 extra information in FLAGS.
6009 This function is called by md_apply_fix to fix up instructions that need
6010 a fix-up described above but does not involve any linker-time relocation. */
6013 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6017 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6018 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6019 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6023 /* Now the instruction is about to be fixed-up, so the operand that
6024 was previously marked as 'ignored' needs to be unmarked in order
6025 to get the encoding done properly. */
6026 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6027 new_inst
->operands
[idx
].skip
= 0;
6030 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6034 case AARCH64_OPND_EXCEPTION
:
6035 if (unsigned_overflow (value
, 16))
6036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6037 _("immediate out of range"));
6038 insn
= get_aarch64_insn (buf
);
6039 insn
|= encode_svc_imm (value
);
6040 put_aarch64_insn (buf
, insn
);
6043 case AARCH64_OPND_AIMM
:
6044 /* ADD or SUB with immediate.
6045 NOTE this assumes we come here with a add/sub shifted reg encoding
6046 3 322|2222|2 2 2 21111 111111
6047 1 098|7654|3 2 1 09876 543210 98765 43210
6048 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6049 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6050 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6051 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6053 3 322|2222|2 2 221111111111
6054 1 098|7654|3 2 109876543210 98765 43210
6055 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6056 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6057 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6058 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6059 Fields sf Rn Rd are already set. */
6060 insn
= get_aarch64_insn (buf
);
6064 insn
= reencode_addsub_switch_add_sub (insn
);
6068 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6069 && unsigned_overflow (value
, 12))
6071 /* Try to shift the value by 12 to make it fit. */
6072 if (((value
>> 12) << 12) == value
6073 && ! unsigned_overflow (value
, 12 + 12))
6076 insn
|= encode_addsub_imm_shift_amount (1);
6080 if (unsigned_overflow (value
, 12))
6081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6082 _("immediate out of range"));
6084 insn
|= encode_addsub_imm (value
);
6086 put_aarch64_insn (buf
, insn
);
6089 case AARCH64_OPND_SIMD_IMM
:
6090 case AARCH64_OPND_SIMD_IMM_SFT
:
6091 case AARCH64_OPND_LIMM
:
6092 /* Bit mask immediate. */
6093 gas_assert (new_inst
!= NULL
);
6094 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6095 new_inst
->operands
[idx
].imm
.value
= value
;
6096 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6097 &new_inst
->value
, NULL
, NULL
))
6098 put_aarch64_insn (buf
, new_inst
->value
);
6100 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6101 _("invalid immediate"));
6104 case AARCH64_OPND_HALF
:
6105 /* 16-bit unsigned immediate. */
6106 if (unsigned_overflow (value
, 16))
6107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6108 _("immediate out of range"));
6109 insn
= get_aarch64_insn (buf
);
6110 insn
|= encode_movw_imm (value
& 0xffff);
6111 put_aarch64_insn (buf
, insn
);
6114 case AARCH64_OPND_IMM_MOV
:
6115 /* Operand for a generic move immediate instruction, which is
6116 an alias instruction that generates a single MOVZ, MOVN or ORR
6117 instruction to loads a 32-bit/64-bit immediate value into general
6118 register. An assembler error shall result if the immediate cannot be
6119 created by a single one of these instructions. If there is a choice,
6120 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6121 and MOVZ or MOVN to ORR. */
6122 gas_assert (new_inst
!= NULL
);
6123 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6126 case AARCH64_OPND_ADDR_SIMM7
:
6127 case AARCH64_OPND_ADDR_SIMM9
:
6128 case AARCH64_OPND_ADDR_SIMM9_2
:
6129 case AARCH64_OPND_ADDR_UIMM12
:
6130 /* Immediate offset in an address. */
6131 insn
= get_aarch64_insn (buf
);
6133 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6134 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6135 || new_inst
->opcode
->operands
[2] == opnd
);
6137 /* Get the index of the address operand. */
6138 if (new_inst
->opcode
->operands
[1] == opnd
)
6139 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6142 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6145 /* Update the resolved offset value. */
6146 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6148 /* Encode/fix-up. */
6149 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6150 &new_inst
->value
, NULL
, NULL
))
6152 put_aarch64_insn (buf
, new_inst
->value
);
6155 else if (new_inst
->opcode
->iclass
== ldst_pos
6156 && try_to_encode_as_unscaled_ldst (new_inst
))
6158 put_aarch64_insn (buf
, new_inst
->value
);
6162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6163 _("immediate offset out of range"));
6168 as_fatal (_("unhandled operand code %d"), opnd
);
6172 /* Apply a fixup (fixP) to segment data, once it has been determined
6173 by our caller that we have all the info we need to fix it up.
6175 Parameter valP is the pointer to the value of the bits. */
6178 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6180 offsetT value
= *valP
;
6182 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6184 unsigned flags
= fixP
->fx_addnumber
;
6186 DEBUG_TRACE ("\n\n");
6187 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6188 DEBUG_TRACE ("Enter md_apply_fix");
6190 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6192 /* Note whether this will delete the relocation. */
6194 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6197 /* Process the relocations. */
6198 switch (fixP
->fx_r_type
)
6200 case BFD_RELOC_NONE
:
6201 /* This will need to go in the object file. */
6206 case BFD_RELOC_8_PCREL
:
6207 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6208 md_number_to_chars (buf
, value
, 1);
6212 case BFD_RELOC_16_PCREL
:
6213 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6214 md_number_to_chars (buf
, value
, 2);
6218 case BFD_RELOC_32_PCREL
:
6219 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6220 md_number_to_chars (buf
, value
, 4);
6224 case BFD_RELOC_64_PCREL
:
6225 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6226 md_number_to_chars (buf
, value
, 8);
6229 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6230 /* We claim that these fixups have been processed here, even if
6231 in fact we generate an error because we do not have a reloc
6232 for them, so tc_gen_reloc() will reject them. */
6234 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6236 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6237 _("undefined symbol %s used as an immediate value"),
6238 S_GET_NAME (fixP
->fx_addsy
));
6239 goto apply_fix_return
;
6241 fix_insn (fixP
, flags
, value
);
6244 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6247 _("pc-relative load offset not word aligned"));
6248 if (signed_overflow (value
, 21))
6249 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6250 _("pc-relative load offset out of range"));
6251 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6253 insn
= get_aarch64_insn (buf
);
6254 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6255 put_aarch64_insn (buf
, insn
);
6259 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6260 if (signed_overflow (value
, 21))
6261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6262 _("pc-relative address offset out of range"));
6263 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6265 insn
= get_aarch64_insn (buf
);
6266 insn
|= encode_adr_imm (value
);
6267 put_aarch64_insn (buf
, insn
);
6271 case BFD_RELOC_AARCH64_BRANCH19
:
6273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6274 _("conditional branch target not word aligned"));
6275 if (signed_overflow (value
, 21))
6276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6277 _("conditional branch out of range"));
6278 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6280 insn
= get_aarch64_insn (buf
);
6281 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6282 put_aarch64_insn (buf
, insn
);
6286 case BFD_RELOC_AARCH64_TSTBR14
:
6288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6289 _("conditional branch target not word aligned"));
6290 if (signed_overflow (value
, 16))
6291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6292 _("conditional branch out of range"));
6293 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6295 insn
= get_aarch64_insn (buf
);
6296 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6297 put_aarch64_insn (buf
, insn
);
6301 case BFD_RELOC_AARCH64_JUMP26
:
6302 case BFD_RELOC_AARCH64_CALL26
:
6304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6305 _("branch target not word aligned"));
6306 if (signed_overflow (value
, 28))
6307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("branch out of range"));
6308 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6310 insn
= get_aarch64_insn (buf
);
6311 insn
|= encode_branch_ofs_26 (value
>> 2);
6312 put_aarch64_insn (buf
, insn
);
6316 case BFD_RELOC_AARCH64_MOVW_G0
:
6317 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6318 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6321 case BFD_RELOC_AARCH64_MOVW_G1
:
6322 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6323 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6326 case BFD_RELOC_AARCH64_MOVW_G2
:
6327 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6328 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6331 case BFD_RELOC_AARCH64_MOVW_G3
:
6334 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6336 insn
= get_aarch64_insn (buf
);
6340 /* REL signed addend must fit in 16 bits */
6341 if (signed_overflow (value
, 16))
6342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6343 _("offset out of range"));
6347 /* Check for overflow and scale. */
6348 switch (fixP
->fx_r_type
)
6350 case BFD_RELOC_AARCH64_MOVW_G0
:
6351 case BFD_RELOC_AARCH64_MOVW_G1
:
6352 case BFD_RELOC_AARCH64_MOVW_G2
:
6353 case BFD_RELOC_AARCH64_MOVW_G3
:
6354 if (unsigned_overflow (value
, scale
+ 16))
6355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6356 _("unsigned value out of range"));
6358 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6359 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6360 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6361 /* NOTE: We can only come here with movz or movn. */
6362 if (signed_overflow (value
, scale
+ 16))
6363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6364 _("signed value out of range"));
6367 /* Force use of MOVN. */
6369 insn
= reencode_movzn_to_movn (insn
);
6373 /* Force use of MOVZ. */
6374 insn
= reencode_movzn_to_movz (insn
);
6378 /* Unchecked relocations. */
6384 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6385 insn
|= encode_movw_imm (value
& 0xffff);
6387 put_aarch64_insn (buf
, insn
);
6391 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6392 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6393 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6394 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6395 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6396 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6397 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6398 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6399 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6400 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6401 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6402 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6403 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
:
6404 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6405 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6406 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6407 /* Should always be exported to object file, see
6408 aarch64_force_relocation(). */
6409 gas_assert (!fixP
->fx_done
);
6410 gas_assert (seg
->use_rela_p
);
6413 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6414 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6415 case BFD_RELOC_AARCH64_ADD_LO12
:
6416 case BFD_RELOC_AARCH64_LDST8_LO12
:
6417 case BFD_RELOC_AARCH64_LDST16_LO12
:
6418 case BFD_RELOC_AARCH64_LDST32_LO12
:
6419 case BFD_RELOC_AARCH64_LDST64_LO12
:
6420 case BFD_RELOC_AARCH64_LDST128_LO12
:
6421 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6422 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6423 /* Should always be exported to object file, see
6424 aarch64_force_relocation(). */
6425 gas_assert (!fixP
->fx_done
);
6426 gas_assert (seg
->use_rela_p
);
6429 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6430 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6431 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6435 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6436 _("unexpected %s fixup"),
6437 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6442 /* Free the allocated the struct aarch64_inst.
6443 N.B. currently there are very limited number of fix-up types actually use
6444 this field, so the impact on the performance should be minimal . */
6445 if (fixP
->tc_fix_data
.inst
!= NULL
)
6446 free (fixP
->tc_fix_data
.inst
);
6451 /* Translate internal representation of relocation info to BFD target
6455 tc_gen_reloc (asection
* section
, fixS
* fixp
)
6458 bfd_reloc_code_real_type code
;
6460 reloc
= xmalloc (sizeof (arelent
));
6462 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
6463 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6464 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6468 if (section
->use_rela_p
)
6469 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
6471 fixp
->fx_offset
= reloc
->address
;
6473 reloc
->addend
= fixp
->fx_offset
;
6475 code
= fixp
->fx_r_type
;
6480 code
= BFD_RELOC_16_PCREL
;
6485 code
= BFD_RELOC_32_PCREL
;
6490 code
= BFD_RELOC_64_PCREL
;
6497 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6498 if (reloc
->howto
== NULL
)
6500 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6502 ("cannot represent %s relocation in this object file format"),
6503 bfd_get_reloc_code_name (code
));
6510 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6513 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
6515 bfd_reloc_code_real_type type
;
6519 FIXME: @@ Should look at CPU word size. */
6526 type
= BFD_RELOC_16
;
6529 type
= BFD_RELOC_32
;
6532 type
= BFD_RELOC_64
;
6535 as_bad (_("cannot do %u-byte relocation"), size
);
6536 type
= BFD_RELOC_UNUSED
;
6540 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6544 aarch64_force_relocation (struct fix
*fixp
)
6546 switch (fixp
->fx_r_type
)
6548 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6549 /* Perform these "immediate" internal relocations
6550 even if the symbol is extern or weak. */
6553 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6554 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6555 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6556 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6557 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6558 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6559 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6560 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6561 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6562 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6563 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6564 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6565 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
:
6566 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6567 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6568 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6569 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6570 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6571 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6572 case BFD_RELOC_AARCH64_ADD_LO12
:
6573 case BFD_RELOC_AARCH64_LDST8_LO12
:
6574 case BFD_RELOC_AARCH64_LDST16_LO12
:
6575 case BFD_RELOC_AARCH64_LDST32_LO12
:
6576 case BFD_RELOC_AARCH64_LDST64_LO12
:
6577 case BFD_RELOC_AARCH64_LDST128_LO12
:
6578 /* Always leave these relocations for the linker. */
6585 return generic_force_reloc (fixp
);
6591 elf64_aarch64_target_format (void)
6593 if (target_big_endian
)
6594 return "elf64-bigaarch64";
6596 return "elf64-littleaarch64";
6600 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
6602 elf_frob_symbol (symp
, puntp
);
6606 /* MD interface: Finalization. */
6608 /* A good place to do this, although this was probably not intended
6609 for this kind of use. We need to dump the literal pool before
6610 references are made to a null symbol pointer. */
6613 aarch64_cleanup (void)
6617 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
6619 /* Put it at the end of the relevant section. */
6620 subseg_set (pool
->section
, pool
->sub_section
);
6626 /* Remove any excess mapping symbols generated for alignment frags in
6627 SEC. We may have created a mapping symbol before a zero byte
6628 alignment; remove it if there's a mapping symbol after the
6631 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
6632 void *dummy ATTRIBUTE_UNUSED
)
6634 segment_info_type
*seginfo
= seg_info (sec
);
6637 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
6640 for (fragp
= seginfo
->frchainP
->frch_root
;
6641 fragp
!= NULL
; fragp
= fragp
->fr_next
)
6643 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
6644 fragS
*next
= fragp
->fr_next
;
6646 /* Variable-sized frags have been converted to fixed size by
6647 this point. But if this was variable-sized to start with,
6648 there will be a fixed-size frag after it. So don't handle
6650 if (sym
== NULL
|| next
== NULL
)
6653 if (S_GET_VALUE (sym
) < next
->fr_address
)
6654 /* Not at the end of this frag. */
6656 know (S_GET_VALUE (sym
) == next
->fr_address
);
6660 if (next
->tc_frag_data
.first_map
!= NULL
)
6662 /* Next frag starts with a mapping symbol. Discard this
6664 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
6668 if (next
->fr_next
== NULL
)
6670 /* This mapping symbol is at the end of the section. Discard
6672 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
6673 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
6677 /* As long as we have empty frags without any mapping symbols,
6679 /* If the next frag is non-empty and does not start with a
6680 mapping symbol, then this mapping symbol is required. */
6681 if (next
->fr_address
!= next
->fr_next
->fr_address
)
6684 next
= next
->fr_next
;
6686 while (next
!= NULL
);
6691 /* Adjust the symbol table. */
6694 aarch64_adjust_symtab (void)
6697 /* Remove any overlapping mapping symbols generated by alignment frags. */
6698 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
6699 /* Now do generic ELF adjustments. */
6700 elf_adjust_symtab ();
6705 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
6707 const char *hash_err
;
6709 hash_err
= hash_insert (table
, key
, value
);
6711 printf ("Internal Error: Can't hash %s\n", key
);
6715 fill_instruction_hash_table (void)
6717 aarch64_opcode
*opcode
= aarch64_opcode_table
;
6719 while (opcode
->name
!= NULL
)
6721 templates
*templ
, *new_templ
;
6722 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
6724 new_templ
= (templates
*) xmalloc (sizeof (templates
));
6725 new_templ
->opcode
= opcode
;
6726 new_templ
->next
= NULL
;
6729 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
6732 new_templ
->next
= templ
->next
;
6733 templ
->next
= new_templ
;
6740 convert_to_upper (char *dst
, const char *src
, size_t num
)
6743 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
6744 *dst
= TOUPPER (*src
);
6748 /* Assume STR point to a lower-case string, allocate, convert and return
6749 the corresponding upper-case string. */
6750 static inline const char*
6751 get_upper_str (const char *str
)
6754 size_t len
= strlen (str
);
6755 if ((ret
= xmalloc (len
+ 1)) == NULL
)
6757 convert_to_upper (ret
, str
, len
);
6761 /* MD interface: Initialization. */
6769 if ((aarch64_ops_hsh
= hash_new ()) == NULL
6770 || (aarch64_cond_hsh
= hash_new ()) == NULL
6771 || (aarch64_shift_hsh
= hash_new ()) == NULL
6772 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
6773 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
6774 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
6775 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
6776 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
6777 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
6778 || (aarch64_reg_hsh
= hash_new ()) == NULL
6779 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
6780 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
6781 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
6782 as_fatal (_("virtual memory exhausted"));
6784 fill_instruction_hash_table ();
6786 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
6787 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
6788 (void *) (aarch64_sys_regs
+ i
));
6790 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
6791 checked_hash_insert (aarch64_pstatefield_hsh
,
6792 aarch64_pstatefields
[i
].name
,
6793 (void *) (aarch64_pstatefields
+ i
));
6795 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
6796 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
6797 aarch64_sys_regs_ic
[i
].template,
6798 (void *) (aarch64_sys_regs_ic
+ i
));
6800 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
6801 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
6802 aarch64_sys_regs_dc
[i
].template,
6803 (void *) (aarch64_sys_regs_dc
+ i
));
6805 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
6806 checked_hash_insert (aarch64_sys_regs_at_hsh
,
6807 aarch64_sys_regs_at
[i
].template,
6808 (void *) (aarch64_sys_regs_at
+ i
));
6810 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
6811 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
6812 aarch64_sys_regs_tlbi
[i
].template,
6813 (void *) (aarch64_sys_regs_tlbi
+ i
));
6815 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
6816 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
6817 (void *) (reg_names
+ i
));
6819 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
6820 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
6821 (void *) (nzcv_names
+ i
));
6823 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
6825 const char *name
= aarch64_operand_modifiers
[i
].name
;
6826 checked_hash_insert (aarch64_shift_hsh
, name
,
6827 (void *) (aarch64_operand_modifiers
+ i
));
6828 /* Also hash the name in the upper case. */
6829 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
6830 (void *) (aarch64_operand_modifiers
+ i
));
6833 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
6836 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
6837 the same condition code. */
6838 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
6840 const char *name
= aarch64_conds
[i
].names
[j
];
6843 checked_hash_insert (aarch64_cond_hsh
, name
,
6844 (void *) (aarch64_conds
+ i
));
6845 /* Also hash the name in the upper case. */
6846 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
6847 (void *) (aarch64_conds
+ i
));
6851 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
6853 const char *name
= aarch64_barrier_options
[i
].name
;
6854 /* Skip xx00 - the unallocated values of option. */
6857 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
6858 (void *) (aarch64_barrier_options
+ i
));
6859 /* Also hash the name in the upper case. */
6860 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
6861 (void *) (aarch64_barrier_options
+ i
));
6864 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
6866 const char* name
= aarch64_prfops
[i
].name
;
6867 /* Skip 0011x, 01xxx, 1011x and 11xxx - the unallocated hint encodings
6868 as a 5-bit immediate #uimm5. */
6871 checked_hash_insert (aarch64_pldop_hsh
, name
,
6872 (void *) (aarch64_prfops
+ i
));
6873 /* Also hash the name in the upper case. */
6874 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
6875 (void *) (aarch64_prfops
+ i
));
6878 /* Set the cpu variant based on the command-line options. */
6880 mcpu_cpu_opt
= march_cpu_opt
;
6883 mcpu_cpu_opt
= &cpu_default
;
6885 cpu_variant
= *mcpu_cpu_opt
;
6887 /* Record the CPU type. */
6888 mach
= bfd_mach_aarch64
;
6890 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
6893 /* Command line processing. */
6895 const char *md_shortopts
= "m:";
6897 #ifdef AARCH64_BI_ENDIAN
6898 #define OPTION_EB (OPTION_MD_BASE + 0)
6899 #define OPTION_EL (OPTION_MD_BASE + 1)
6901 #if TARGET_BYTES_BIG_ENDIAN
6902 #define OPTION_EB (OPTION_MD_BASE + 0)
6904 #define OPTION_EL (OPTION_MD_BASE + 1)
6908 struct option md_longopts
[] = {
6910 {"EB", no_argument
, NULL
, OPTION_EB
},
6913 {"EL", no_argument
, NULL
, OPTION_EL
},
6915 {NULL
, no_argument
, NULL
, 0}
6918 size_t md_longopts_size
= sizeof (md_longopts
);
6920 struct aarch64_option_table
6922 char *option
; /* Option name to match. */
6923 char *help
; /* Help information. */
6924 int *var
; /* Variable to change. */
6925 int value
; /* What to change it to. */
6926 char *deprecated
; /* If non-null, print this message. */
6929 static struct aarch64_option_table aarch64_opts
[] = {
6930 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
6931 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
6933 #ifdef DEBUG_AARCH64
6934 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
6935 #endif /* DEBUG_AARCH64 */
6936 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
6938 {NULL
, NULL
, NULL
, 0, NULL
}
6941 struct aarch64_cpu_option_table
6944 const aarch64_feature_set value
;
6945 /* The canonical name of the CPU, or NULL to use NAME converted to upper
6947 const char *canonical_name
;
6950 /* This list should, at a minimum, contain all the cpu names
6951 recognized by GCC. */
6952 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
6953 {"all", AARCH64_ANY
, NULL
},
6954 {"generic", AARCH64_ARCH_V8
, NULL
},
6956 /* These two are example CPUs supported in GCC, once we have real
6957 CPUs they will be removed. */
6958 {"example-1", AARCH64_ARCH_V8
, NULL
},
6959 {"example-2", AARCH64_ARCH_V8
, NULL
},
6961 {NULL
, AARCH64_ARCH_NONE
, NULL
}
6964 struct aarch64_arch_option_table
6967 const aarch64_feature_set value
;
6970 /* This list should, at a minimum, contain all the architecture names
6971 recognized by GCC. */
6972 static const struct aarch64_arch_option_table aarch64_archs
[] = {
6973 {"all", AARCH64_ANY
},
6974 {"armv8", AARCH64_ARCH_V8
},
6975 {NULL
, AARCH64_ARCH_NONE
}
6978 /* ISA extensions. */
6979 struct aarch64_option_cpu_value_table
6982 const aarch64_feature_set value
;
6985 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
6986 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
6987 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
6988 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
6989 {NULL
, AARCH64_ARCH_NONE
}
6992 struct aarch64_long_option_table
6994 char *option
; /* Substring to match. */
6995 char *help
; /* Help information. */
6996 int (*func
) (char *subopt
); /* Function to decode sub-option. */
6997 char *deprecated
; /* If non-null, print this message. */
7001 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
)
7003 /* We insist on extensions being added before being removed. We achieve
7004 this by using the ADDING_VALUE variable to indicate whether we are
7005 adding an extension (1) or removing it (0) and only allowing it to
7006 change in the order -1 -> 1 -> 0. */
7007 int adding_value
= -1;
7008 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7010 /* Copy the feature set, so that we can modify it. */
7014 while (str
!= NULL
&& *str
!= 0)
7016 const struct aarch64_option_cpu_value_table
*opt
;
7022 as_bad (_("invalid architectural extension"));
7027 ext
= strchr (str
, '+');
7032 optlen
= strlen (str
);
7034 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7036 if (adding_value
!= 0)
7041 else if (optlen
> 0)
7043 if (adding_value
== -1)
7045 else if (adding_value
!= 1)
7047 as_bad (_("must specify extensions to add before specifying "
7048 "those to remove"));
7055 as_bad (_("missing architectural extension"));
7059 gas_assert (adding_value
!= -1);
7061 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7062 if (strncmp (opt
->name
, str
, optlen
) == 0)
7064 /* Add or remove the extension. */
7066 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7068 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7072 if (opt
->name
== NULL
)
7074 as_bad (_("unknown architectural extension `%s'"), str
);
7085 aarch64_parse_cpu (char *str
)
7087 const struct aarch64_cpu_option_table
*opt
;
7088 char *ext
= strchr (str
, '+');
7094 optlen
= strlen (str
);
7098 as_bad (_("missing cpu name `%s'"), str
);
7102 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7103 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7105 mcpu_cpu_opt
= &opt
->value
;
7107 return aarch64_parse_features (ext
, &mcpu_cpu_opt
);
7112 as_bad (_("unknown cpu `%s'"), str
);
7117 aarch64_parse_arch (char *str
)
7119 const struct aarch64_arch_option_table
*opt
;
7120 char *ext
= strchr (str
, '+');
7126 optlen
= strlen (str
);
7130 as_bad (_("missing architecture name `%s'"), str
);
7134 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7135 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7137 march_cpu_opt
= &opt
->value
;
7139 return aarch64_parse_features (ext
, &march_cpu_opt
);
7144 as_bad (_("unknown architecture `%s'\n"), str
);
7148 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7149 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7150 aarch64_parse_cpu
, NULL
},
7151 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7152 aarch64_parse_arch
, NULL
},
7153 {NULL
, NULL
, 0, NULL
}
7157 md_parse_option (int c
, char *arg
)
7159 struct aarch64_option_table
*opt
;
7160 struct aarch64_long_option_table
*lopt
;
7166 target_big_endian
= 1;
7172 target_big_endian
= 0;
7177 /* Listing option. Just ignore these, we don't support additional
7182 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7184 if (c
== opt
->option
[0]
7185 && ((arg
== NULL
&& opt
->option
[1] == 0)
7186 || streq (arg
, opt
->option
+ 1)))
7188 /* If the option is deprecated, tell the user. */
7189 if (opt
->deprecated
!= NULL
)
7190 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7191 arg
? arg
: "", _(opt
->deprecated
));
7193 if (opt
->var
!= NULL
)
7194 *opt
->var
= opt
->value
;
7200 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7202 /* These options are expected to have an argument. */
7203 if (c
== lopt
->option
[0]
7205 && strncmp (arg
, lopt
->option
+ 1,
7206 strlen (lopt
->option
+ 1)) == 0)
7208 /* If the option is deprecated, tell the user. */
7209 if (lopt
->deprecated
!= NULL
)
7210 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7211 _(lopt
->deprecated
));
7213 /* Call the sup-option parser. */
7214 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7225 md_show_usage (FILE * fp
)
7227 struct aarch64_option_table
*opt
;
7228 struct aarch64_long_option_table
*lopt
;
7230 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7232 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7233 if (opt
->help
!= NULL
)
7234 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7236 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7237 if (lopt
->help
!= NULL
)
7238 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7242 -EB assemble code for a big-endian cpu\n"));
7247 -EL assemble code for a little-endian cpu\n"));
7251 /* Parse a .cpu directive. */
7254 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7256 const struct aarch64_cpu_option_table
*opt
;
7262 name
= input_line_pointer
;
7263 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7264 input_line_pointer
++;
7265 saved_char
= *input_line_pointer
;
7266 *input_line_pointer
= 0;
7268 ext
= strchr (name
, '+');
7271 optlen
= ext
- name
;
7273 optlen
= strlen (name
);
7275 /* Skip the first "all" entry. */
7276 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7277 if (strlen (opt
->name
) == optlen
7278 && strncmp (name
, opt
->name
, optlen
) == 0)
7280 mcpu_cpu_opt
= &opt
->value
;
7282 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
))
7285 cpu_variant
= *mcpu_cpu_opt
;
7287 *input_line_pointer
= saved_char
;
7288 demand_empty_rest_of_line ();
7291 as_bad (_("unknown cpu `%s'"), name
);
7292 *input_line_pointer
= saved_char
;
7293 ignore_rest_of_line ();
7297 /* Parse a .arch directive. */
7300 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7302 const struct aarch64_arch_option_table
*opt
;
7308 name
= input_line_pointer
;
7309 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7310 input_line_pointer
++;
7311 saved_char
= *input_line_pointer
;
7312 *input_line_pointer
= 0;
7314 ext
= strchr (name
, '+');
7317 optlen
= ext
- name
;
7319 optlen
= strlen (name
);
7321 /* Skip the first "all" entry. */
7322 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7323 if (strlen (opt
->name
) == optlen
7324 && strncmp (name
, opt
->name
, optlen
) == 0)
7326 mcpu_cpu_opt
= &opt
->value
;
7328 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
))
7331 cpu_variant
= *mcpu_cpu_opt
;
7333 *input_line_pointer
= saved_char
;
7334 demand_empty_rest_of_line ();
7338 as_bad (_("unknown architecture `%s'\n"), name
);
7339 *input_line_pointer
= saved_char
;
7340 ignore_rest_of_line ();
7343 /* Copy symbol information. */
7346 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
7348 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);