1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2021 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
259 bfd_reloc_code_real_type reloc
;
262 /* Macros to define the register types and masks for the purpose
265 #undef AARCH64_REG_TYPES
266 #define AARCH64_REG_TYPES \
267 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
268 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
269 BASIC_REG_TYPE(SP_32) /* wsp */ \
270 BASIC_REG_TYPE(SP_64) /* sp */ \
271 BASIC_REG_TYPE(Z_32) /* wzr */ \
272 BASIC_REG_TYPE(Z_64) /* xzr */ \
273 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
274 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
275 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
276 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
277 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
278 BASIC_REG_TYPE(VN) /* v[0-31] */ \
279 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
280 BASIC_REG_TYPE(PN) /* p[0-15] */ \
281 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
282 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
283 /* Typecheck: same, plus SVE registers. */ \
284 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
286 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
287 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
293 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
294 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
296 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
297 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
298 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
299 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
300 /* Typecheck: any [BHSDQ]P FP. */ \
301 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
302 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
303 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
304 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
306 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
307 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
308 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
309 be used for SVE instructions, since Zn and Pn are valid symbols \
310 in other contexts. */ \
311 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
314 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
315 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
316 | REG_TYPE(ZN) | REG_TYPE(PN)) \
317 /* Any integer register; used for error messages only. */ \
318 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
320 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
321 /* Pseudo type to mark the end of the enumerator sequence. */ \
324 #undef BASIC_REG_TYPE
325 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
326 #undef MULTI_REG_TYPE
327 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
329 /* Register type enumerators. */
330 typedef enum aarch64_reg_type_
332 /* A list of REG_TYPE_*. */
336 #undef BASIC_REG_TYPE
337 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
339 #define REG_TYPE(T) (1 << REG_TYPE_##T)
340 #undef MULTI_REG_TYPE
341 #define MULTI_REG_TYPE(T,V) V,
343 /* Structure for a hash table entry for a register. */
347 unsigned char number
;
348 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
349 unsigned char builtin
;
352 /* Values indexed by aarch64_reg_type to assist the type checking. */
353 static const unsigned reg_type_masks
[] =
358 #undef BASIC_REG_TYPE
360 #undef MULTI_REG_TYPE
361 #undef AARCH64_REG_TYPES
363 /* Diagnostics used when we don't get a register of the expected type.
364 Note: this has to synchronized with aarch64_reg_type definitions
367 get_reg_expected_msg (aarch64_reg_type reg_type
)
374 msg
= N_("integer 32-bit register expected");
377 msg
= N_("integer 64-bit register expected");
380 msg
= N_("integer register expected");
382 case REG_TYPE_R64_SP
:
383 msg
= N_("64-bit integer or SP register expected");
385 case REG_TYPE_SVE_BASE
:
386 msg
= N_("base register expected");
389 msg
= N_("integer or zero register expected");
391 case REG_TYPE_SVE_OFFSET
:
392 msg
= N_("offset register expected");
395 msg
= N_("integer or SP register expected");
397 case REG_TYPE_R_Z_SP
:
398 msg
= N_("integer, zero or SP register expected");
401 msg
= N_("8-bit SIMD scalar register expected");
404 msg
= N_("16-bit SIMD scalar or floating-point half precision "
405 "register expected");
408 msg
= N_("32-bit SIMD scalar or floating-point single precision "
409 "register expected");
412 msg
= N_("64-bit SIMD scalar or floating-point double precision "
413 "register expected");
416 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
417 "register expected");
419 case REG_TYPE_R_Z_BHSDQ_V
:
420 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
421 msg
= N_("register expected");
423 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
424 msg
= N_("SIMD scalar or floating-point register expected");
426 case REG_TYPE_VN
: /* any V reg */
427 msg
= N_("vector register expected");
430 msg
= N_("SVE vector register expected");
433 msg
= N_("SVE predicate register expected");
436 as_fatal (_("invalid register type %d"), reg_type
);
441 /* Some well known registers that we refer to directly elsewhere. */
445 /* Instructions take 4 bytes in the object file. */
448 static htab_t aarch64_ops_hsh
;
449 static htab_t aarch64_cond_hsh
;
450 static htab_t aarch64_shift_hsh
;
451 static htab_t aarch64_sys_regs_hsh
;
452 static htab_t aarch64_pstatefield_hsh
;
453 static htab_t aarch64_sys_regs_ic_hsh
;
454 static htab_t aarch64_sys_regs_dc_hsh
;
455 static htab_t aarch64_sys_regs_at_hsh
;
456 static htab_t aarch64_sys_regs_tlbi_hsh
;
457 static htab_t aarch64_sys_regs_sr_hsh
;
458 static htab_t aarch64_reg_hsh
;
459 static htab_t aarch64_barrier_opt_hsh
;
460 static htab_t aarch64_nzcv_hsh
;
461 static htab_t aarch64_pldop_hsh
;
462 static htab_t aarch64_hint_opt_hsh
;
464 /* Stuff needed to resolve the label ambiguity
473 static symbolS
*last_label_seen
;
475 /* Literal pool structure. Held on a per-section
476 and per-sub-section basis. */
478 #define MAX_LITERAL_POOL_SIZE 1024
479 typedef struct literal_expression
482 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
483 LITTLENUM_TYPE
* bignum
;
484 } literal_expression
;
486 typedef struct literal_pool
488 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
489 unsigned int next_free_entry
;
495 struct literal_pool
*next
;
498 /* Pointer to a linked list of literal pools. */
499 static literal_pool
*list_of_pools
= NULL
;
503 /* This array holds the chars that always start a comment. If the
504 pre-processor is disabled, these aren't very useful. */
505 const char comment_chars
[] = "";
507 /* This array holds the chars that only start a comment at the beginning of
508 a line. If the line seems to have the form '# 123 filename'
509 .line and .file directives will appear in the pre-processed output. */
510 /* Note that input_file.c hand checks for '#' at the beginning of the
511 first line of the input file. This is because the compiler outputs
512 #NO_APP at the beginning of its output. */
513 /* Also note that comments like this one will always work. */
514 const char line_comment_chars
[] = "#";
516 const char line_separator_chars
[] = ";";
518 /* Chars that can be used to separate mant
519 from exp in floating point numbers. */
520 const char EXP_CHARS
[] = "eE";
522 /* Chars that mean this number is a floating point constant. */
526 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
528 /* Prefix character that indicates the start of an immediate value. */
529 #define is_immediate_prefix(C) ((C) == '#')
531 /* Separator character handling. */
533 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
535 static inline bfd_boolean
536 skip_past_char (char **str
, char c
)
547 #define skip_past_comma(str) skip_past_char (str, ',')
549 /* Arithmetic expressions (possibly involving symbols). */
551 static bfd_boolean in_my_get_expression_p
= FALSE
;
553 /* Third argument to my_get_expression. */
554 #define GE_NO_PREFIX 0
555 #define GE_OPT_PREFIX 1
557 /* Return TRUE if the string pointed by *STR is successfully parsed
558 as an valid expression; *EP will be filled with the information of
559 such an expression. Otherwise return FALSE. */
562 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
567 int prefix_present_p
= 0;
574 if (is_immediate_prefix (**str
))
577 prefix_present_p
= 1;
584 memset (ep
, 0, sizeof (expressionS
));
586 save_in
= input_line_pointer
;
587 input_line_pointer
= *str
;
588 in_my_get_expression_p
= TRUE
;
589 seg
= expression (ep
);
590 in_my_get_expression_p
= FALSE
;
592 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
594 /* We found a bad expression in md_operand(). */
595 *str
= input_line_pointer
;
596 input_line_pointer
= save_in
;
597 if (prefix_present_p
&& ! error_p ())
598 set_fatal_syntax_error (_("bad expression"));
600 set_first_syntax_error (_("bad expression"));
605 if (seg
!= absolute_section
606 && seg
!= text_section
607 && seg
!= data_section
608 && seg
!= bss_section
&& seg
!= undefined_section
)
610 set_syntax_error (_("bad segment"));
611 *str
= input_line_pointer
;
612 input_line_pointer
= save_in
;
619 *str
= input_line_pointer
;
620 input_line_pointer
= save_in
;
624 /* Turn a string in input_line_pointer into a floating point constant
625 of type TYPE, and store the appropriate bytes in *LITP. The number
626 of LITTLENUMS emitted is stored in *SIZEP. An error message is
627 returned, or NULL on OK. */
630 md_atof (int type
, char *litP
, int *sizeP
)
632 /* If this is a bfloat16 type, then parse it slightly differently -
633 as it does not follow the IEEE standard exactly. */
637 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
638 FLONUM_TYPE generic_float
;
640 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
643 input_line_pointer
= t
;
645 return _("invalid floating point number");
647 switch (generic_float
.sign
)
660 /* bfloat16 has two types of NaN - quiet and signalling.
661 Quiet NaN has bit[6] == 1 && faction != 0, whereas
662 signalling Nan's have bit[0] == 0 && fraction != 0.
663 Chose this specific encoding as it is the same form
664 as used by other IEEE 754 encodings in GAS. */
675 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
680 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
683 /* We handle all bad expressions here, so that we can report the faulty
684 instruction in the error message. */
686 md_operand (expressionS
* exp
)
688 if (in_my_get_expression_p
)
689 exp
->X_op
= O_illegal
;
692 /* Immediate values. */
694 /* Errors may be set multiple times during parsing or bit encoding
695 (particularly in the Neon bits), but usually the earliest error which is set
696 will be the most meaningful. Avoid overwriting it with later (cascading)
697 errors by calling this function. */
700 first_error (const char *error
)
703 set_syntax_error (error
);
706 /* Similar to first_error, but this function accepts formatted error
709 first_error_fmt (const char *format
, ...)
714 /* N.B. this single buffer will not cause error messages for different
715 instructions to pollute each other; this is because at the end of
716 processing of each assembly line, error message if any will be
717 collected by as_bad. */
718 static char buffer
[size
];
722 int ret ATTRIBUTE_UNUSED
;
723 va_start (args
, format
);
724 ret
= vsnprintf (buffer
, size
, format
, args
);
725 know (ret
<= size
- 1 && ret
>= 0);
727 set_syntax_error (buffer
);
731 /* Register parsing. */
733 /* Generic register parser which is called by other specialized
735 CCP points to what should be the beginning of a register name.
736 If it is indeed a valid register name, advance CCP over it and
737 return the reg_entry structure; otherwise return NULL.
738 It does not issue diagnostics. */
741 parse_reg (char **ccp
)
747 #ifdef REGISTER_PREFIX
748 if (*start
!= REGISTER_PREFIX
)
754 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
759 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
761 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
770 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
773 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
775 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
778 /* Try to parse a base or offset register. Allow SVE base and offset
779 registers if REG_TYPE includes SVE registers. Return the register
780 entry on success, setting *QUALIFIER to the register qualifier.
781 Return null otherwise.
783 Note that this function does not issue any diagnostics. */
785 static const reg_entry
*
786 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
787 aarch64_opnd_qualifier_t
*qualifier
)
790 const reg_entry
*reg
= parse_reg (&str
);
800 *qualifier
= AARCH64_OPND_QLF_W
;
806 *qualifier
= AARCH64_OPND_QLF_X
;
810 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
813 switch (TOLOWER (str
[1]))
816 *qualifier
= AARCH64_OPND_QLF_S_S
;
819 *qualifier
= AARCH64_OPND_QLF_S_D
;
836 /* Try to parse a base or offset register. Return the register entry
837 on success, setting *QUALIFIER to the register qualifier. Return null
840 Note that this function does not issue any diagnostics. */
842 static const reg_entry
*
843 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
845 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
848 /* Parse the qualifier of a vector register or vector element of type
849 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
850 succeeds; otherwise return FALSE.
852 Accept only one occurrence of:
853 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
856 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
857 struct vector_type_el
*parsed_type
, char **str
)
861 unsigned element_size
;
862 enum vector_el_type type
;
865 gas_assert (*ptr
== '.');
868 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
873 width
= strtoul (ptr
, &ptr
, 10);
874 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
876 first_error_fmt (_("bad size %d in vector width specifier"), width
);
881 switch (TOLOWER (*ptr
))
900 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
909 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
911 first_error (_("missing element size"));
914 if (width
!= 0 && width
* element_size
!= 64
915 && width
* element_size
!= 128
916 && !(width
== 2 && element_size
== 16)
917 && !(width
== 4 && element_size
== 8))
920 ("invalid element size %d and vector size combination %c"),
926 parsed_type
->type
= type
;
927 parsed_type
->width
= width
;
934 /* *STR contains an SVE zero/merge predication suffix. Parse it into
935 *PARSED_TYPE and point *STR at the end of the suffix. */
938 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
943 gas_assert (*ptr
== '/');
945 switch (TOLOWER (*ptr
))
948 parsed_type
->type
= NT_zero
;
951 parsed_type
->type
= NT_merge
;
954 if (*ptr
!= '\0' && *ptr
!= ',')
955 first_error_fmt (_("unexpected character `%c' in predication type"),
958 first_error (_("missing predication type"));
961 parsed_type
->width
= 0;
966 /* Parse a register of the type TYPE.
968 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
969 name or the parsed register is not of TYPE.
971 Otherwise return the register number, and optionally fill in the actual
972 type of the register in *RTYPE when multiple alternatives were given, and
973 return the register shape and element index information in *TYPEINFO.
975 IN_REG_LIST should be set with TRUE if the caller is parsing a register
979 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
980 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
983 const reg_entry
*reg
= parse_reg (&str
);
984 struct vector_type_el atype
;
985 struct vector_type_el parsetype
;
986 bfd_boolean is_typed_vecreg
= FALSE
;
989 atype
.type
= NT_invtype
;
997 set_default_error ();
1001 if (! aarch64_check_reg_type (reg
, type
))
1003 DEBUG_TRACE ("reg type check failed");
1004 set_default_error ();
1009 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1010 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
1014 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1019 if (!parse_predication_for_operand (&parsetype
, &str
))
1023 /* Register if of the form Vn.[bhsdq]. */
1024 is_typed_vecreg
= TRUE
;
1026 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1028 /* The width is always variable; we don't allow an integer width
1030 gas_assert (parsetype
.width
== 0);
1031 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1033 else if (parsetype
.width
== 0)
1034 /* Expect index. In the new scheme we cannot have
1035 Vn.[bhsdq] represent a scalar. Therefore any
1036 Vn.[bhsdq] should have an index following it.
1037 Except in reglists of course. */
1038 atype
.defined
|= NTA_HASINDEX
;
1040 atype
.defined
|= NTA_HASTYPE
;
1042 atype
.type
= parsetype
.type
;
1043 atype
.width
= parsetype
.width
;
1046 if (skip_past_char (&str
, '['))
1050 /* Reject Sn[index] syntax. */
1051 if (!is_typed_vecreg
)
1053 first_error (_("this type of register can't be indexed"));
1059 first_error (_("index not allowed inside register list"));
1063 atype
.defined
|= NTA_HASINDEX
;
1065 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1067 if (exp
.X_op
!= O_constant
)
1069 first_error (_("constant expression required"));
1073 if (! skip_past_char (&str
, ']'))
1076 atype
.index
= exp
.X_add_number
;
1078 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1080 /* Indexed vector register expected. */
1081 first_error (_("indexed vector register expected"));
1085 /* A vector reg Vn should be typed or indexed. */
1086 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1088 first_error (_("invalid use of vector register"));
1104 Return the register number on success; return PARSE_FAIL otherwise.
1106 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1107 the register (e.g. NEON double or quad reg when either has been requested).
1109 If this is a NEON vector register with additional type information, fill
1110 in the struct pointed to by VECTYPE (if non-NULL).
1112 This parser does not handle register list. */
1115 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1116 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1118 struct vector_type_el atype
;
1120 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1121 /*in_reg_list= */ FALSE
);
1123 if (reg
== PARSE_FAIL
)
1134 static inline bfd_boolean
1135 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1139 && e1
.defined
== e2
.defined
1140 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1143 /* This function parses a list of vector registers of type TYPE.
1144 On success, it returns the parsed register list information in the
1145 following encoded format:
1147 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1148 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1150 The information of the register shape and/or index is returned in
1153 It returns PARSE_FAIL if the register list is invalid.
1155 The list contains one to four registers.
1156 Each register can be one of:
1159 All <T> should be identical.
1160 All <index> should be identical.
1161 There are restrictions on <Vt> numbers which are checked later
1162 (by reg_list_valid_p). */
1165 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1166 struct vector_type_el
*vectype
)
1170 struct vector_type_el typeinfo
, typeinfo_first
;
1175 bfd_boolean error
= FALSE
;
1176 bfd_boolean expect_index
= FALSE
;
1180 set_syntax_error (_("expecting {"));
1186 typeinfo_first
.defined
= 0;
1187 typeinfo_first
.type
= NT_invtype
;
1188 typeinfo_first
.width
= -1;
1189 typeinfo_first
.index
= 0;
1198 str
++; /* skip over '-' */
1201 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1202 /*in_reg_list= */ TRUE
);
1203 if (val
== PARSE_FAIL
)
1205 set_first_syntax_error (_("invalid vector register in list"));
1209 /* reject [bhsd]n */
1210 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1212 set_first_syntax_error (_("invalid scalar register in list"));
1217 if (typeinfo
.defined
& NTA_HASINDEX
)
1218 expect_index
= TRUE
;
1222 if (val
< val_range
)
1224 set_first_syntax_error
1225 (_("invalid range in vector register list"));
1234 typeinfo_first
= typeinfo
;
1235 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1237 set_first_syntax_error
1238 (_("type mismatch in vector register list"));
1243 for (i
= val_range
; i
<= val
; i
++)
1245 ret_val
|= i
<< (5 * nb_regs
);
1250 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1252 skip_whitespace (str
);
1255 set_first_syntax_error (_("end of vector register list not found"));
1260 skip_whitespace (str
);
1264 if (skip_past_char (&str
, '['))
1268 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1269 if (exp
.X_op
!= O_constant
)
1271 set_first_syntax_error (_("constant expression required."));
1274 if (! skip_past_char (&str
, ']'))
1277 typeinfo_first
.index
= exp
.X_add_number
;
1281 set_first_syntax_error (_("expected index"));
1288 set_first_syntax_error (_("too many registers in vector register list"));
1291 else if (nb_regs
== 0)
1293 set_first_syntax_error (_("empty vector register list"));
1299 *vectype
= typeinfo_first
;
1301 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1304 /* Directives: register aliases. */
1307 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1312 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1315 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1318 /* Only warn about a redefinition if it's not defined as the
1320 else if (new->number
!= number
|| new->type
!= type
)
1321 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1326 name
= xstrdup (str
);
1327 new = XNEW (reg_entry
);
1330 new->number
= number
;
1332 new->builtin
= FALSE
;
1334 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1339 /* Look for the .req directive. This is of the form:
1341 new_register_name .req existing_register_name
1343 If we find one, or if it looks sufficiently like one that we want to
1344 handle any error here, return TRUE. Otherwise return FALSE. */
1347 create_register_alias (char *newname
, char *p
)
1349 const reg_entry
*old
;
1350 char *oldname
, *nbuf
;
1353 /* The input scrubber ensures that whitespace after the mnemonic is
1354 collapsed to single spaces. */
1356 if (strncmp (oldname
, " .req ", 6) != 0)
1360 if (*oldname
== '\0')
1363 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1366 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1370 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1371 the desired alias name, and p points to its end. If not, then
1372 the desired alias name is in the global original_case_string. */
1373 #ifdef TC_CASE_SENSITIVE
1376 newname
= original_case_string
;
1377 nlen
= strlen (newname
);
1380 nbuf
= xmemdup0 (newname
, nlen
);
1382 /* Create aliases under the new name as stated; an all-lowercase
1383 version of the new name; and an all-uppercase version of the new
1385 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1387 for (p
= nbuf
; *p
; p
++)
1390 if (strncmp (nbuf
, newname
, nlen
))
1392 /* If this attempt to create an additional alias fails, do not bother
1393 trying to create the all-lower case alias. We will fail and issue
1394 a second, duplicate error message. This situation arises when the
1395 programmer does something like:
1398 The second .req creates the "Foo" alias but then fails to create
1399 the artificial FOO alias because it has already been created by the
1401 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1408 for (p
= nbuf
; *p
; p
++)
1411 if (strncmp (nbuf
, newname
, nlen
))
1412 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1419 /* Should never be called, as .req goes between the alias and the
1420 register name, not at the beginning of the line. */
1422 s_req (int a ATTRIBUTE_UNUSED
)
1424 as_bad (_("invalid syntax for .req directive"));
1427 /* The .unreq directive deletes an alias which was previously defined
1428 by .req. For example:
1434 s_unreq (int a ATTRIBUTE_UNUSED
)
1439 name
= input_line_pointer
;
1441 while (*input_line_pointer
!= 0
1442 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1443 ++input_line_pointer
;
1445 saved_char
= *input_line_pointer
;
1446 *input_line_pointer
= 0;
1449 as_bad (_("invalid syntax for .unreq directive"));
1452 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1455 as_bad (_("unknown register alias '%s'"), name
);
1456 else if (reg
->builtin
)
1457 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1464 str_hash_delete (aarch64_reg_hsh
, name
);
1465 free ((char *) reg
->name
);
1468 /* Also locate the all upper case and all lower case versions.
1469 Do not complain if we cannot find one or the other as it
1470 was probably deleted above. */
1472 nbuf
= strdup (name
);
1473 for (p
= nbuf
; *p
; p
++)
1475 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1478 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1479 free ((char *) reg
->name
);
1483 for (p
= nbuf
; *p
; p
++)
1485 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1488 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1489 free ((char *) reg
->name
);
1497 *input_line_pointer
= saved_char
;
1498 demand_empty_rest_of_line ();
1501 /* Directives: Instruction set selection. */
1504 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1505 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1506 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1507 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1509 /* Create a new mapping symbol for the transition to STATE. */
1512 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1515 const char *symname
;
1522 type
= BSF_NO_FLAGS
;
1526 type
= BSF_NO_FLAGS
;
1532 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1533 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1535 /* Save the mapping symbols for future reference. Also check that
1536 we do not place two mapping symbols at the same offset within a
1537 frag. We'll handle overlap between frags in
1538 check_mapping_symbols.
1540 If .fill or other data filling directive generates zero sized data,
1541 the mapping symbol for the following code will have the same value
1542 as the one generated for the data filling directive. In this case,
1543 we replace the old symbol with the new one at the same address. */
1546 if (frag
->tc_frag_data
.first_map
!= NULL
)
1548 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1549 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1552 frag
->tc_frag_data
.first_map
= symbolP
;
1554 if (frag
->tc_frag_data
.last_map
!= NULL
)
1556 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1557 S_GET_VALUE (symbolP
));
1558 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1559 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1562 frag
->tc_frag_data
.last_map
= symbolP
;
1565 /* We must sometimes convert a region marked as code to data during
1566 code alignment, if an odd number of bytes have to be padded. The
1567 code mapping symbol is pushed to an aligned address. */
1570 insert_data_mapping_symbol (enum mstate state
,
1571 valueT value
, fragS
* frag
, offsetT bytes
)
1573 /* If there was already a mapping symbol, remove it. */
1574 if (frag
->tc_frag_data
.last_map
!= NULL
1575 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1576 frag
->fr_address
+ value
)
1578 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1582 know (frag
->tc_frag_data
.first_map
== symp
);
1583 frag
->tc_frag_data
.first_map
= NULL
;
1585 frag
->tc_frag_data
.last_map
= NULL
;
1586 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1589 make_mapping_symbol (MAP_DATA
, value
, frag
);
1590 make_mapping_symbol (state
, value
+ bytes
, frag
);
1593 static void mapping_state_2 (enum mstate state
, int max_chars
);
1595 /* Set the mapping state to STATE. Only call this when about to
1596 emit some STATE bytes to the file. */
1599 mapping_state (enum mstate state
)
1601 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1603 if (state
== MAP_INSN
)
1604 /* AArch64 instructions require 4-byte alignment. When emitting
1605 instructions into any section, record the appropriate section
1607 record_alignment (now_seg
, 2);
1609 if (mapstate
== state
)
1610 /* The mapping symbol has already been emitted.
1611 There is nothing else to do. */
1614 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1615 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1616 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1617 evaluated later in the next else. */
1619 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1621 /* Only add the symbol if the offset is > 0:
1622 if we're at the first frag, check it's size > 0;
1623 if we're not at the first frag, then for sure
1624 the offset is > 0. */
1625 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1626 const int add_symbol
= (frag_now
!= frag_first
)
1627 || (frag_now_fix () > 0);
1630 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1634 mapping_state_2 (state
, 0);
1637 /* Same as mapping_state, but MAX_CHARS bytes have already been
1638 allocated. Put the mapping symbol that far back. */
1641 mapping_state_2 (enum mstate state
, int max_chars
)
1643 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1645 if (!SEG_NORMAL (now_seg
))
1648 if (mapstate
== state
)
1649 /* The mapping symbol has already been emitted.
1650 There is nothing else to do. */
1653 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1654 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1657 #define mapping_state(x) /* nothing */
1658 #define mapping_state_2(x, y) /* nothing */
1661 /* Directives: sectioning and alignment. */
1664 s_bss (int ignore ATTRIBUTE_UNUSED
)
1666 /* We don't support putting frags in the BSS segment, we fake it by
1667 marking in_bss, then looking at s_skip for clues. */
1668 subseg_set (bss_section
, 0);
1669 demand_empty_rest_of_line ();
1670 mapping_state (MAP_DATA
);
1674 s_even (int ignore ATTRIBUTE_UNUSED
)
1676 /* Never make frag if expect extra pass. */
1678 frag_align (1, 0, 0);
1680 record_alignment (now_seg
, 1);
1682 demand_empty_rest_of_line ();
1685 /* Directives: Literal pools. */
1687 static literal_pool
*
1688 find_literal_pool (int size
)
1692 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1694 if (pool
->section
== now_seg
1695 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1702 static literal_pool
*
1703 find_or_make_literal_pool (int size
)
1705 /* Next literal pool ID number. */
1706 static unsigned int latest_pool_num
= 1;
1709 pool
= find_literal_pool (size
);
1713 /* Create a new pool. */
1714 pool
= XNEW (literal_pool
);
1718 /* Currently we always put the literal pool in the current text
1719 section. If we were generating "small" model code where we
1720 knew that all code and initialised data was within 1MB then
1721 we could output literals to mergeable, read-only data
1724 pool
->next_free_entry
= 0;
1725 pool
->section
= now_seg
;
1726 pool
->sub_section
= now_subseg
;
1728 pool
->next
= list_of_pools
;
1729 pool
->symbol
= NULL
;
1731 /* Add it to the list. */
1732 list_of_pools
= pool
;
1735 /* New pools, and emptied pools, will have a NULL symbol. */
1736 if (pool
->symbol
== NULL
)
1738 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1739 &zero_address_frag
, 0);
1740 pool
->id
= latest_pool_num
++;
1747 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1748 Return TRUE on success, otherwise return FALSE. */
1750 add_to_lit_pool (expressionS
*exp
, int size
)
1755 pool
= find_or_make_literal_pool (size
);
1757 /* Check if this literal value is already in the pool. */
1758 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1760 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1762 if ((litexp
->X_op
== exp
->X_op
)
1763 && (exp
->X_op
== O_constant
)
1764 && (litexp
->X_add_number
== exp
->X_add_number
)
1765 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1768 if ((litexp
->X_op
== exp
->X_op
)
1769 && (exp
->X_op
== O_symbol
)
1770 && (litexp
->X_add_number
== exp
->X_add_number
)
1771 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1772 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1776 /* Do we need to create a new entry? */
1777 if (entry
== pool
->next_free_entry
)
1779 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1781 set_syntax_error (_("literal pool overflow"));
1785 pool
->literals
[entry
].exp
= *exp
;
1786 pool
->next_free_entry
+= 1;
1787 if (exp
->X_op
== O_big
)
1789 /* PR 16688: Bignums are held in a single global array. We must
1790 copy and preserve that value now, before it is overwritten. */
1791 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1793 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1794 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1797 pool
->literals
[entry
].bignum
= NULL
;
1800 exp
->X_op
= O_symbol
;
1801 exp
->X_add_number
= ((int) entry
) * size
;
1802 exp
->X_add_symbol
= pool
->symbol
;
1807 /* Can't use symbol_new here, so have to create a symbol and then at
1808 a later date assign it a value. That's what these functions do. */
1811 symbol_locate (symbolS
* symbolP
,
1812 const char *name
,/* It is copied, the caller can modify. */
1813 segT segment
, /* Segment identifier (SEG_<something>). */
1814 valueT valu
, /* Symbol value. */
1815 fragS
* frag
) /* Associated fragment. */
1818 char *preserved_copy_of_name
;
1820 name_length
= strlen (name
) + 1; /* +1 for \0. */
1821 obstack_grow (¬es
, name
, name_length
);
1822 preserved_copy_of_name
= obstack_finish (¬es
);
1824 #ifdef tc_canonicalize_symbol_name
1825 preserved_copy_of_name
=
1826 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1829 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1831 S_SET_SEGMENT (symbolP
, segment
);
1832 S_SET_VALUE (symbolP
, valu
);
1833 symbol_clear_list_pointers (symbolP
);
1835 symbol_set_frag (symbolP
, frag
);
1837 /* Link to end of symbol chain. */
1839 extern int symbol_table_frozen
;
1841 if (symbol_table_frozen
)
1845 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1847 obj_symbol_new_hook (symbolP
);
1849 #ifdef tc_symbol_new_hook
1850 tc_symbol_new_hook (symbolP
);
1854 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1855 #endif /* DEBUG_SYMS */
1860 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1867 for (align
= 2; align
<= 4; align
++)
1869 int size
= 1 << align
;
1871 pool
= find_literal_pool (size
);
1872 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1875 /* Align pool as you have word accesses.
1876 Only make a frag if we have to. */
1878 frag_align (align
, 0, 0);
1880 mapping_state (MAP_DATA
);
1882 record_alignment (now_seg
, align
);
1884 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1886 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1887 (valueT
) frag_now_fix (), frag_now
);
1888 symbol_table_insert (pool
->symbol
);
1890 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1892 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1894 if (exp
->X_op
== O_big
)
1896 /* PR 16688: Restore the global bignum value. */
1897 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1898 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1899 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1902 /* First output the expression in the instruction to the pool. */
1903 emit_expr (exp
, size
); /* .word|.xword */
1905 if (exp
->X_op
== O_big
)
1907 free (pool
->literals
[entry
].bignum
);
1908 pool
->literals
[entry
].bignum
= NULL
;
1912 /* Mark the pool as empty. */
1913 pool
->next_free_entry
= 0;
1914 pool
->symbol
= NULL
;
1919 /* Forward declarations for functions below, in the MD interface
1921 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1922 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1924 /* Directives: Data. */
1925 /* N.B. the support for relocation suffix in this directive needs to be
1926 implemented properly. */
1929 s_aarch64_elf_cons (int nbytes
)
1933 #ifdef md_flush_pending_output
1934 md_flush_pending_output ();
1937 if (is_it_end_of_statement ())
1939 demand_empty_rest_of_line ();
1943 #ifdef md_cons_align
1944 md_cons_align (nbytes
);
1947 mapping_state (MAP_DATA
);
1950 struct reloc_table_entry
*reloc
;
1954 if (exp
.X_op
!= O_symbol
)
1955 emit_expr (&exp
, (unsigned int) nbytes
);
1958 skip_past_char (&input_line_pointer
, '#');
1959 if (skip_past_char (&input_line_pointer
, ':'))
1961 reloc
= find_reloc_table_entry (&input_line_pointer
);
1963 as_bad (_("unrecognized relocation suffix"));
1965 as_bad (_("unimplemented relocation suffix"));
1966 ignore_rest_of_line ();
1970 emit_expr (&exp
, (unsigned int) nbytes
);
1973 while (*input_line_pointer
++ == ',');
1975 /* Put terminator back into stream. */
1976 input_line_pointer
--;
1977 demand_empty_rest_of_line ();
1980 /* Mark symbol that it follows a variant PCS convention. */
1983 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1989 elf_symbol_type
*elfsym
;
1991 c
= get_symbol_name (&name
);
1993 as_bad (_("Missing symbol name in directive"));
1994 sym
= symbol_find_or_make (name
);
1995 restore_line_pointer (c
);
1996 demand_empty_rest_of_line ();
1997 bfdsym
= symbol_get_bfdsym (sym
);
1998 elfsym
= elf_symbol_from (bfdsym
);
1999 gas_assert (elfsym
);
2000 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2002 #endif /* OBJ_ELF */
2004 /* Output a 32-bit word, but mark as an instruction. */
2007 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2011 #ifdef md_flush_pending_output
2012 md_flush_pending_output ();
2015 if (is_it_end_of_statement ())
2017 demand_empty_rest_of_line ();
2021 /* Sections are assumed to start aligned. In executable section, there is no
2022 MAP_DATA symbol pending. So we only align the address during
2023 MAP_DATA --> MAP_INSN transition.
2024 For other sections, this is not guaranteed. */
2025 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2026 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2027 frag_align_code (2, 0);
2030 mapping_state (MAP_INSN
);
2036 if (exp
.X_op
!= O_constant
)
2038 as_bad (_("constant expression required"));
2039 ignore_rest_of_line ();
2043 if (target_big_endian
)
2045 unsigned int val
= exp
.X_add_number
;
2046 exp
.X_add_number
= SWAP_32 (val
);
2048 emit_expr (&exp
, 4);
2050 while (*input_line_pointer
++ == ',');
2052 /* Put terminator back into stream. */
2053 input_line_pointer
--;
2054 demand_empty_rest_of_line ();
2058 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2060 demand_empty_rest_of_line ();
2061 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2062 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2066 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2069 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2075 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2076 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2078 demand_empty_rest_of_line ();
2081 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2084 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2088 /* Since we're just labelling the code, there's no need to define a
2091 /* Make sure there is enough room in this frag for the following
2092 blr. This trick only works if the blr follows immediately after
2093 the .tlsdesc directive. */
2095 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2096 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2098 demand_empty_rest_of_line ();
2101 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2104 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2110 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2111 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2113 demand_empty_rest_of_line ();
2115 #endif /* OBJ_ELF */
2117 static void s_aarch64_arch (int);
2118 static void s_aarch64_cpu (int);
2119 static void s_aarch64_arch_extension (int);
2121 /* This table describes all the machine specific pseudo-ops the assembler
2122 has to support. The fields are:
2123 pseudo-op name without dot
2124 function to call to execute this pseudo-op
2125 Integer arg to pass to the function. */
2127 const pseudo_typeS md_pseudo_table
[] = {
2128 /* Never called because '.req' does not start a line. */
2130 {"unreq", s_unreq
, 0},
2132 {"even", s_even
, 0},
2133 {"ltorg", s_ltorg
, 0},
2134 {"pool", s_ltorg
, 0},
2135 {"cpu", s_aarch64_cpu
, 0},
2136 {"arch", s_aarch64_arch
, 0},
2137 {"arch_extension", s_aarch64_arch_extension
, 0},
2138 {"inst", s_aarch64_inst
, 0},
2139 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2141 {"tlsdescadd", s_tlsdescadd
, 0},
2142 {"tlsdesccall", s_tlsdesccall
, 0},
2143 {"tlsdescldr", s_tlsdescldr
, 0},
2144 {"word", s_aarch64_elf_cons
, 4},
2145 {"long", s_aarch64_elf_cons
, 4},
2146 {"xword", s_aarch64_elf_cons
, 8},
2147 {"dword", s_aarch64_elf_cons
, 8},
2148 {"variant_pcs", s_variant_pcs
, 0},
2150 {"float16", float_cons
, 'h'},
2151 {"bfloat16", float_cons
, 'b'},
2156 /* Check whether STR points to a register name followed by a comma or the
2157 end of line; REG_TYPE indicates which register types are checked
2158 against. Return TRUE if STR is such a register name; otherwise return
2159 FALSE. The function does not intend to produce any diagnostics, but since
2160 the register parser aarch64_reg_parse, which is called by this function,
2161 does produce diagnostics, we call clear_error to clear any diagnostics
2162 that may be generated by aarch64_reg_parse.
2163 Also, the function returns FALSE directly if there is any user error
2164 present at the function entry. This prevents the existing diagnostics
2165 state from being spoiled.
2166 The function currently serves parse_constant_immediate and
2167 parse_big_immediate only. */
2169 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2173 /* Prevent the diagnostics state from being spoiled. */
2177 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2179 /* Clear the parsing error that may be set by the reg parser. */
2182 if (reg
== PARSE_FAIL
)
2185 skip_whitespace (str
);
2186 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2192 /* Parser functions used exclusively in instruction operands. */
2194 /* Parse an immediate expression which may not be constant.
2196 To prevent the expression parser from pushing a register name
2197 into the symbol table as an undefined symbol, firstly a check is
2198 done to find out whether STR is a register of type REG_TYPE followed
2199 by a comma or the end of line. Return FALSE if STR is such a string. */
2202 parse_immediate_expression (char **str
, expressionS
*exp
,
2203 aarch64_reg_type reg_type
)
2205 if (reg_name_p (*str
, reg_type
))
2207 set_recoverable_error (_("immediate operand required"));
2211 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2213 if (exp
->X_op
== O_absent
)
2215 set_fatal_syntax_error (_("missing immediate expression"));
2222 /* Constant immediate-value read function for use in insn parsing.
2223 STR points to the beginning of the immediate (with the optional
2224 leading #); *VAL receives the value. REG_TYPE says which register
2225 names should be treated as registers rather than as symbolic immediates.
2227 Return TRUE on success; otherwise return FALSE. */
2230 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2234 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2237 if (exp
.X_op
!= O_constant
)
2239 set_syntax_error (_("constant expression required"));
2243 *val
= exp
.X_add_number
;
2248 encode_imm_float_bits (uint32_t imm
)
2250 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2251 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2254 /* Return TRUE if the single-precision floating-point value encoded in IMM
2255 can be expressed in the AArch64 8-bit signed floating-point format with
2256 3-bit exponent and normalized 4 bits of precision; in other words, the
2257 floating-point value must be expressable as
2258 (+/-) n / 16 * power (2, r)
2259 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2262 aarch64_imm_float_p (uint32_t imm
)
2264 /* If a single-precision floating-point value has the following bit
2265 pattern, it can be expressed in the AArch64 8-bit floating-point
2268 3 32222222 2221111111111
2269 1 09876543 21098765432109876543210
2270 n Eeeeeexx xxxx0000000000000000000
2272 where n, e and each x are either 0 or 1 independently, with
2277 /* Prepare the pattern for 'Eeeeee'. */
2278 if (((imm
>> 30) & 0x1) == 0)
2279 pattern
= 0x3e000000;
2281 pattern
= 0x40000000;
2283 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2284 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2287 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2288 as an IEEE float without any loss of precision. Store the value in
2292 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2294 /* If a double-precision floating-point value has the following bit
2295 pattern, it can be expressed in a float:
2297 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2298 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2299 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2301 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2302 if Eeee_eeee != 1111_1111
2304 where n, e, s and S are either 0 or 1 independently and where ~ is the
2308 uint32_t high32
= imm
>> 32;
2309 uint32_t low32
= imm
;
2311 /* Lower 29 bits need to be 0s. */
2312 if ((imm
& 0x1fffffff) != 0)
2315 /* Prepare the pattern for 'Eeeeeeeee'. */
2316 if (((high32
>> 30) & 0x1) == 0)
2317 pattern
= 0x38000000;
2319 pattern
= 0x40000000;
2322 if ((high32
& 0x78000000) != pattern
)
2325 /* Check Eeee_eeee != 1111_1111. */
2326 if ((high32
& 0x7ff00000) == 0x47f00000)
2329 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2330 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2331 | (low32
>> 29)); /* 3 S bits. */
2335 /* Return true if we should treat OPERAND as a double-precision
2336 floating-point operand rather than a single-precision one. */
2338 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2340 /* Check for unsuffixed SVE registers, which are allowed
2341 for LDR and STR but not in instructions that require an
2342 immediate. We get better error messages if we arbitrarily
2343 pick one size, parse the immediate normally, and then
2344 report the match failure in the normal way. */
2345 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2346 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2349 /* Parse a floating-point immediate. Return TRUE on success and return the
2350 value in *IMMED in the format of IEEE754 single-precision encoding.
2351 *CCP points to the start of the string; DP_P is TRUE when the immediate
2352 is expected to be in double-precision (N.B. this only matters when
2353 hexadecimal representation is involved). REG_TYPE says which register
2354 names should be treated as registers rather than as symbolic immediates.
2356 This routine accepts any IEEE float; it is up to the callers to reject
2360 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2361 aarch64_reg_type reg_type
)
2365 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2367 unsigned fpword
= 0;
2368 bfd_boolean hex_p
= FALSE
;
2370 skip_past_char (&str
, '#');
2373 skip_whitespace (fpnum
);
2375 if (strncmp (fpnum
, "0x", 2) == 0)
2377 /* Support the hexadecimal representation of the IEEE754 encoding.
2378 Double-precision is expected when DP_P is TRUE, otherwise the
2379 representation should be in single-precision. */
2380 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2385 if (!can_convert_double_to_float (val
, &fpword
))
2388 else if ((uint64_t) val
> 0xffffffff)
2395 else if (reg_name_p (str
, reg_type
))
2397 set_recoverable_error (_("immediate operand required"));
2405 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2408 /* Our FP word must be 32 bits (single-precision FP). */
2409 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2411 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2421 set_fatal_syntax_error (_("invalid floating-point constant"));
2425 /* Less-generic immediate-value read function with the possibility of loading
2426 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2429 To prevent the expression parser from pushing a register name into the
2430 symbol table as an undefined symbol, a check is firstly done to find
2431 out whether STR is a register of type REG_TYPE followed by a comma or
2432 the end of line. Return FALSE if STR is such a register. */
2435 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2439 if (reg_name_p (ptr
, reg_type
))
2441 set_syntax_error (_("immediate operand required"));
2445 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2447 if (inst
.reloc
.exp
.X_op
== O_constant
)
2448 *imm
= inst
.reloc
.exp
.X_add_number
;
2455 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2456 if NEED_LIBOPCODES is non-zero, the fixup will need
2457 assistance from the libopcodes. */
2460 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2461 const aarch64_opnd_info
*operand
,
2462 int need_libopcodes_p
)
2464 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2465 reloc
->opnd
= operand
->type
;
2466 if (need_libopcodes_p
)
2467 reloc
->need_libopcodes_p
= 1;
2470 /* Return TRUE if the instruction needs to be fixed up later internally by
2471 the GAS; otherwise return FALSE. */
2473 static inline bfd_boolean
2474 aarch64_gas_internal_fixup_p (void)
2476 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2479 /* Assign the immediate value to the relevant field in *OPERAND if
2480 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2481 needs an internal fixup in a later stage.
2482 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2483 IMM.VALUE that may get assigned with the constant. */
2485 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2486 aarch64_opnd_info
*operand
,
2488 int need_libopcodes_p
,
2491 if (reloc
->exp
.X_op
== O_constant
)
2494 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2496 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2497 reloc
->type
= BFD_RELOC_UNUSED
;
2501 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2502 /* Tell libopcodes to ignore this operand or not. This is helpful
2503 when one of the operands needs to be fixed up later but we need
2504 libopcodes to check the other operands. */
2505 operand
->skip
= skip_p
;
2509 /* Relocation modifiers. Each entry in the table contains the textual
2510 name for the relocation which may be placed before a symbol used as
2511 a load/store offset, or add immediate. It must be surrounded by a
2512 leading and trailing colon, for example:
2514 ldr x0, [x1, #:rello:varsym]
2515 add x0, x1, #:rello:varsym */
2517 struct reloc_table_entry
2521 bfd_reloc_code_real_type adr_type
;
2522 bfd_reloc_code_real_type adrp_type
;
2523 bfd_reloc_code_real_type movw_type
;
2524 bfd_reloc_code_real_type add_type
;
2525 bfd_reloc_code_real_type ldst_type
;
2526 bfd_reloc_code_real_type ld_literal_type
;
2529 static struct reloc_table_entry reloc_table
[] = {
2530 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2535 BFD_RELOC_AARCH64_ADD_LO12
,
2536 BFD_RELOC_AARCH64_LDST_LO12
,
2539 /* Higher 21 bits of pc-relative page offset: ADRP */
2542 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2548 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2551 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2557 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2561 BFD_RELOC_AARCH64_MOVW_G0
,
2566 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2570 BFD_RELOC_AARCH64_MOVW_G0_S
,
2575 /* Less significant bits 0-15 of address/value: MOVK, no check */
2579 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2584 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2588 BFD_RELOC_AARCH64_MOVW_G1
,
2593 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2597 BFD_RELOC_AARCH64_MOVW_G1_S
,
2602 /* Less significant bits 16-31 of address/value: MOVK, no check */
2606 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2611 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2615 BFD_RELOC_AARCH64_MOVW_G2
,
2620 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2624 BFD_RELOC_AARCH64_MOVW_G2_S
,
2629 /* Less significant bits 32-47 of address/value: MOVK, no check */
2633 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2638 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2642 BFD_RELOC_AARCH64_MOVW_G3
,
2647 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2651 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2656 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2660 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2665 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2669 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2674 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2678 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2683 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2687 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2692 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2696 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2701 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2705 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2710 /* Get to the page containing GOT entry for a symbol. */
2713 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2717 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2719 /* 12 bit offset into the page containing GOT entry for that symbol. */
2725 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2728 /* 0-15 bits of address/value: MOVk, no check. */
2732 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2737 /* Most significant bits 16-31 of address/value: MOVZ. */
2741 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2746 /* 15 bit offset into the page containing GOT entry for that symbol. */
2752 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2755 /* Get to the page containing GOT TLS entry for a symbol */
2756 {"gottprel_g0_nc", 0,
2759 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2764 /* Get to the page containing GOT TLS entry for a symbol */
2768 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2773 /* Get to the page containing GOT TLS entry for a symbol */
2775 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2776 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2782 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2787 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2791 /* Lower 16 bits address/value: MOVk. */
2795 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2800 /* Most significant bits 16-31 of address/value: MOVZ. */
2804 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2809 /* Get to the page containing GOT TLS entry for a symbol */
2811 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2812 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2816 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2818 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2823 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2824 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2827 /* Get to the page containing GOT TLS entry for a symbol.
2828 The same as GD, we allocate two consecutive GOT slots
2829 for module index and module offset, the only difference
2830 with GD is the module offset should be initialized to
2831 zero without any outstanding runtime relocation. */
2833 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2834 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2840 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2841 {"tlsldm_lo12_nc", 0,
2845 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2849 /* 12 bit offset into the module TLS base address. */
2854 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2855 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2858 /* Same as dtprel_lo12, no overflow check. */
2859 {"dtprel_lo12_nc", 0,
2863 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2864 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2867 /* bits[23:12] of offset to the module TLS base address. */
2872 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2876 /* bits[15:0] of offset to the module TLS base address. */
2880 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2885 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2889 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2894 /* bits[31:16] of offset to the module TLS base address. */
2898 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2903 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2907 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2912 /* bits[47:32] of offset to the module TLS base address. */
2916 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2921 /* Lower 16 bit offset into GOT entry for a symbol */
2922 {"tlsdesc_off_g0_nc", 0,
2925 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2930 /* Higher 16 bit offset into GOT entry for a symbol */
2931 {"tlsdesc_off_g1", 0,
2934 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2939 /* Get to the page containing GOT TLS entry for a symbol */
2942 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2946 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2948 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2949 {"gottprel_lo12", 0,
2954 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2957 /* Get tp offset for a symbol. */
2962 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2966 /* Get tp offset for a symbol. */
2971 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2972 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2975 /* Get tp offset for a symbol. */
2980 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2984 /* Get tp offset for a symbol. */
2985 {"tprel_lo12_nc", 0,
2989 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2990 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2993 /* Most significant bits 32-47 of address/value: MOVZ. */
2997 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3002 /* Most significant bits 16-31 of address/value: MOVZ. */
3006 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3011 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3015 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3020 /* Most significant bits 0-15 of address/value: MOVZ. */
3024 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3029 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3033 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3038 /* 15bit offset from got entry to base address of GOT table. */
3044 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3047 /* 14bit offset from got entry to base address of GOT table. */
3053 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3057 /* Given the address of a pointer pointing to the textual name of a
3058 relocation as may appear in assembler source, attempt to find its
3059 details in reloc_table. The pointer will be updated to the character
3060 after the trailing colon. On failure, NULL will be returned;
3061 otherwise return the reloc_table_entry. */
3063 static struct reloc_table_entry
*
3064 find_reloc_table_entry (char **str
)
3067 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3069 int length
= strlen (reloc_table
[i
].name
);
3071 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3072 && (*str
)[length
] == ':')
3074 *str
+= (length
+ 1);
3075 return &reloc_table
[i
];
3082 /* Mode argument to parse_shift and parser_shifter_operand. */
3083 enum parse_shift_mode
3085 SHIFTED_NONE
, /* no shifter allowed */
3086 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3088 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3090 SHIFTED_LSL
, /* bare "lsl #n" */
3091 SHIFTED_MUL
, /* bare "mul #n" */
3092 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3093 SHIFTED_MUL_VL
, /* "mul vl" */
3094 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3097 /* Parse a <shift> operator on an AArch64 data processing instruction.
3098 Return TRUE on success; otherwise return FALSE. */
3100 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3102 const struct aarch64_name_value_pair
*shift_op
;
3103 enum aarch64_modifier_kind kind
;
3109 for (p
= *str
; ISALPHA (*p
); p
++)
3114 set_syntax_error (_("shift expression expected"));
3118 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3120 if (shift_op
== NULL
)
3122 set_syntax_error (_("shift operator expected"));
3126 kind
= aarch64_get_operand_modifier (shift_op
);
3128 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3130 set_syntax_error (_("invalid use of 'MSL'"));
3134 if (kind
== AARCH64_MOD_MUL
3135 && mode
!= SHIFTED_MUL
3136 && mode
!= SHIFTED_MUL_VL
)
3138 set_syntax_error (_("invalid use of 'MUL'"));
3144 case SHIFTED_LOGIC_IMM
:
3145 if (aarch64_extend_operator_p (kind
))
3147 set_syntax_error (_("extending shift is not permitted"));
3152 case SHIFTED_ARITH_IMM
:
3153 if (kind
== AARCH64_MOD_ROR
)
3155 set_syntax_error (_("'ROR' shift is not permitted"));
3161 if (kind
!= AARCH64_MOD_LSL
)
3163 set_syntax_error (_("only 'LSL' shift is permitted"));
3169 if (kind
!= AARCH64_MOD_MUL
)
3171 set_syntax_error (_("only 'MUL' is permitted"));
3176 case SHIFTED_MUL_VL
:
3177 /* "MUL VL" consists of two separate tokens. Require the first
3178 token to be "MUL" and look for a following "VL". */
3179 if (kind
== AARCH64_MOD_MUL
)
3181 skip_whitespace (p
);
3182 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3185 kind
= AARCH64_MOD_MUL_VL
;
3189 set_syntax_error (_("only 'MUL VL' is permitted"));
3192 case SHIFTED_REG_OFFSET
:
3193 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3194 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3196 set_fatal_syntax_error
3197 (_("invalid shift for the register offset addressing mode"));
3202 case SHIFTED_LSL_MSL
:
3203 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3205 set_syntax_error (_("invalid shift operator"));
3214 /* Whitespace can appear here if the next thing is a bare digit. */
3215 skip_whitespace (p
);
3217 /* Parse shift amount. */
3219 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3220 exp
.X_op
= O_absent
;
3223 if (is_immediate_prefix (*p
))
3228 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3230 if (kind
== AARCH64_MOD_MUL_VL
)
3231 /* For consistency, give MUL VL the same shift amount as an implicit
3233 operand
->shifter
.amount
= 1;
3234 else if (exp
.X_op
== O_absent
)
3236 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3238 set_syntax_error (_("missing shift amount"));
3241 operand
->shifter
.amount
= 0;
3243 else if (exp
.X_op
!= O_constant
)
3245 set_syntax_error (_("constant shift amount required"));
3248 /* For parsing purposes, MUL #n has no inherent range. The range
3249 depends on the operand and will be checked by operand-specific
3251 else if (kind
!= AARCH64_MOD_MUL
3252 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3254 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3259 operand
->shifter
.amount
= exp
.X_add_number
;
3260 operand
->shifter
.amount_present
= 1;
3263 operand
->shifter
.operator_present
= 1;
3264 operand
->shifter
.kind
= kind
;
3270 /* Parse a <shifter_operand> for a data processing instruction:
3273 #<immediate>, LSL #imm
3275 Validation of immediate operands is deferred to md_apply_fix.
3277 Return TRUE on success; otherwise return FALSE. */
3280 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3281 enum parse_shift_mode mode
)
3285 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3290 /* Accept an immediate expression. */
3291 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3294 /* Accept optional LSL for arithmetic immediate values. */
3295 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3296 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3299 /* Not accept any shifter for logical immediate values. */
3300 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3301 && parse_shift (&p
, operand
, mode
))
3303 set_syntax_error (_("unexpected shift operator"));
3311 /* Parse a <shifter_operand> for a data processing instruction:
3316 #<immediate>, LSL #imm
3318 where <shift> is handled by parse_shift above, and the last two
3319 cases are handled by the function above.
3321 Validation of immediate operands is deferred to md_apply_fix.
3323 Return TRUE on success; otherwise return FALSE. */
3326 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3327 enum parse_shift_mode mode
)
3329 const reg_entry
*reg
;
3330 aarch64_opnd_qualifier_t qualifier
;
3331 enum aarch64_operand_class opd_class
3332 = aarch64_get_operand_class (operand
->type
);
3334 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3337 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3339 set_syntax_error (_("unexpected register in the immediate operand"));
3343 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3345 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3349 operand
->reg
.regno
= reg
->number
;
3350 operand
->qualifier
= qualifier
;
3352 /* Accept optional shift operation on register. */
3353 if (! skip_past_comma (str
))
3356 if (! parse_shift (str
, operand
, mode
))
3361 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3364 (_("integer register expected in the extended/shifted operand "
3369 /* We have a shifted immediate variable. */
3370 return parse_shifter_operand_imm (str
, operand
, mode
);
3373 /* Return TRUE on success; return FALSE otherwise. */
3376 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3377 enum parse_shift_mode mode
)
3381 /* Determine if we have the sequence of characters #: or just :
3382 coming next. If we do, then we check for a :rello: relocation
3383 modifier. If we don't, punt the whole lot to
3384 parse_shifter_operand. */
3386 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3388 struct reloc_table_entry
*entry
;
3396 /* Try to parse a relocation. Anything else is an error. */
3397 if (!(entry
= find_reloc_table_entry (str
)))
3399 set_syntax_error (_("unknown relocation modifier"));
3403 if (entry
->add_type
== 0)
3406 (_("this relocation modifier is not allowed on this instruction"));
3410 /* Save str before we decompose it. */
3413 /* Next, we parse the expression. */
3414 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3417 /* Record the relocation type (use the ADD variant here). */
3418 inst
.reloc
.type
= entry
->add_type
;
3419 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3421 /* If str is empty, we've reached the end, stop here. */
3425 /* Otherwise, we have a shifted reloc modifier, so rewind to
3426 recover the variable name and continue parsing for the shifter. */
3428 return parse_shifter_operand_imm (str
, operand
, mode
);
3431 return parse_shifter_operand (str
, operand
, mode
);
3434 /* Parse all forms of an address expression. Information is written
3435 to *OPERAND and/or inst.reloc.
3437 The A64 instruction set has the following addressing modes:
3440 [base] // in SIMD ld/st structure
3441 [base{,#0}] // in ld/st exclusive
3443 [base,Xm{,LSL #imm}]
3444 [base,Xm,SXTX {#imm}]
3445 [base,Wm,(S|U)XTW {#imm}]
3447 [base]! // in ldraa/ldrab exclusive
3451 [base],Xm // in SIMD ld/st structure
3452 PC-relative (literal)
3456 [base,Zm.D{,LSL #imm}]
3457 [base,Zm.S,(S|U)XTW {#imm}]
3458 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3462 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3463 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3464 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3466 (As a convenience, the notation "=immediate" is permitted in conjunction
3467 with the pc-relative literal load instructions to automatically place an
3468 immediate value or symbolic address in a nearby literal pool and generate
3469 a hidden label which references it.)
3471 Upon a successful parsing, the address structure in *OPERAND will be
3472 filled in the following way:
3474 .base_regno = <base>
3475 .offset.is_reg // 1 if the offset is a register
3477 .offset.regno = <Rm>
3479 For different addressing modes defined in the A64 ISA:
3482 .pcrel=0; .preind=1; .postind=0; .writeback=0
3484 .pcrel=0; .preind=1; .postind=0; .writeback=1
3486 .pcrel=0; .preind=0; .postind=1; .writeback=1
3487 PC-relative (literal)
3488 .pcrel=1; .preind=1; .postind=0; .writeback=0
3490 The shift/extension information, if any, will be stored in .shifter.
3491 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3492 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3493 corresponding register.
3495 BASE_TYPE says which types of base register should be accepted and
3496 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3497 is the type of shifter that is allowed for immediate offsets,
3498 or SHIFTED_NONE if none.
3500 In all other respects, it is the caller's responsibility to check
3501 for addressing modes not supported by the instruction, and to set
3505 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3506 aarch64_opnd_qualifier_t
*base_qualifier
,
3507 aarch64_opnd_qualifier_t
*offset_qualifier
,
3508 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3509 enum parse_shift_mode imm_shift_mode
)
3512 const reg_entry
*reg
;
3513 expressionS
*exp
= &inst
.reloc
.exp
;
3515 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3516 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3517 if (! skip_past_char (&p
, '['))
3519 /* =immediate or label. */
3520 operand
->addr
.pcrel
= 1;
3521 operand
->addr
.preind
= 1;
3523 /* #:<reloc_op>:<symbol> */
3524 skip_past_char (&p
, '#');
3525 if (skip_past_char (&p
, ':'))
3527 bfd_reloc_code_real_type ty
;
3528 struct reloc_table_entry
*entry
;
3530 /* Try to parse a relocation modifier. Anything else is
3532 entry
= find_reloc_table_entry (&p
);
3535 set_syntax_error (_("unknown relocation modifier"));
3539 switch (operand
->type
)
3541 case AARCH64_OPND_ADDR_PCREL21
:
3543 ty
= entry
->adr_type
;
3547 ty
= entry
->ld_literal_type
;
3554 (_("this relocation modifier is not allowed on this "
3560 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3562 set_syntax_error (_("invalid relocation expression"));
3566 /* #:<reloc_op>:<expr> */
3567 /* Record the relocation type. */
3568 inst
.reloc
.type
= ty
;
3569 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3574 if (skip_past_char (&p
, '='))
3575 /* =immediate; need to generate the literal in the literal pool. */
3576 inst
.gen_lit_pool
= 1;
3578 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3580 set_syntax_error (_("invalid address"));
3591 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3592 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3594 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3597 operand
->addr
.base_regno
= reg
->number
;
3600 if (skip_past_comma (&p
))
3603 operand
->addr
.preind
= 1;
3605 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3608 if (!aarch64_check_reg_type (reg
, offset_type
))
3610 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3615 operand
->addr
.offset
.regno
= reg
->number
;
3616 operand
->addr
.offset
.is_reg
= 1;
3617 /* Shifted index. */
3618 if (skip_past_comma (&p
))
3621 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3622 /* Use the diagnostics set in parse_shift, so not set new
3623 error message here. */
3627 [base,Xm] # For vector plus scalar SVE2 indexing.
3628 [base,Xm{,LSL #imm}]
3629 [base,Xm,SXTX {#imm}]
3630 [base,Wm,(S|U)XTW {#imm}] */
3631 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3632 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3633 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3635 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3637 set_syntax_error (_("invalid use of 32-bit register offset"));
3640 if (aarch64_get_qualifier_esize (*base_qualifier
)
3641 != aarch64_get_qualifier_esize (*offset_qualifier
)
3642 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3643 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3644 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3646 set_syntax_error (_("offset has different size from base"));
3650 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3652 set_syntax_error (_("invalid use of 64-bit register offset"));
3658 /* [Xn,#:<reloc_op>:<symbol> */
3659 skip_past_char (&p
, '#');
3660 if (skip_past_char (&p
, ':'))
3662 struct reloc_table_entry
*entry
;
3664 /* Try to parse a relocation modifier. Anything else is
3666 if (!(entry
= find_reloc_table_entry (&p
)))
3668 set_syntax_error (_("unknown relocation modifier"));
3672 if (entry
->ldst_type
== 0)
3675 (_("this relocation modifier is not allowed on this "
3680 /* [Xn,#:<reloc_op>: */
3681 /* We now have the group relocation table entry corresponding to
3682 the name in the assembler source. Next, we parse the
3684 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3686 set_syntax_error (_("invalid relocation expression"));
3690 /* [Xn,#:<reloc_op>:<expr> */
3691 /* Record the load/store relocation type. */
3692 inst
.reloc
.type
= entry
->ldst_type
;
3693 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3697 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3699 set_syntax_error (_("invalid expression in the address"));
3703 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3704 /* [Xn,<expr>,<shifter> */
3705 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3711 if (! skip_past_char (&p
, ']'))
3713 set_syntax_error (_("']' expected"));
3717 if (skip_past_char (&p
, '!'))
3719 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3721 set_syntax_error (_("register offset not allowed in pre-indexed "
3722 "addressing mode"));
3726 operand
->addr
.writeback
= 1;
3728 else if (skip_past_comma (&p
))
3731 operand
->addr
.postind
= 1;
3732 operand
->addr
.writeback
= 1;
3734 if (operand
->addr
.preind
)
3736 set_syntax_error (_("cannot combine pre- and post-indexing"));
3740 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3744 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3746 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3750 operand
->addr
.offset
.regno
= reg
->number
;
3751 operand
->addr
.offset
.is_reg
= 1;
3753 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3756 set_syntax_error (_("invalid expression in the address"));
3761 /* If at this point neither .preind nor .postind is set, we have a
3762 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3763 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3764 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3766 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3768 if (operand
->addr
.writeback
)
3770 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3772 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3773 operand
->addr
.offset
.is_reg
= 0;
3774 operand
->addr
.offset
.imm
= 0;
3775 operand
->addr
.preind
= 1;
3780 set_syntax_error (_("missing offset in the pre-indexed address"));
3786 operand
->addr
.preind
= 1;
3787 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3789 operand
->addr
.offset
.is_reg
= 1;
3790 operand
->addr
.offset
.regno
= REG_ZR
;
3791 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3795 inst
.reloc
.exp
.X_op
= O_constant
;
3796 inst
.reloc
.exp
.X_add_number
= 0;
3805 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3808 parse_address (char **str
, aarch64_opnd_info
*operand
)
3810 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3811 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3812 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3815 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3816 The arguments have the same meaning as for parse_address_main.
3817 Return TRUE on success. */
3819 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3820 aarch64_opnd_qualifier_t
*base_qualifier
,
3821 aarch64_opnd_qualifier_t
*offset_qualifier
)
3823 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3824 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3828 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3829 Return TRUE on success; otherwise return FALSE. */
3831 parse_half (char **str
, int *internal_fixup_p
)
3835 skip_past_char (&p
, '#');
3837 gas_assert (internal_fixup_p
);
3838 *internal_fixup_p
= 0;
3842 struct reloc_table_entry
*entry
;
3844 /* Try to parse a relocation. Anything else is an error. */
3846 if (!(entry
= find_reloc_table_entry (&p
)))
3848 set_syntax_error (_("unknown relocation modifier"));
3852 if (entry
->movw_type
== 0)
3855 (_("this relocation modifier is not allowed on this instruction"));
3859 inst
.reloc
.type
= entry
->movw_type
;
3862 *internal_fixup_p
= 1;
3864 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3871 /* Parse an operand for an ADRP instruction:
3873 Return TRUE on success; otherwise return FALSE. */
3876 parse_adrp (char **str
)
3883 struct reloc_table_entry
*entry
;
3885 /* Try to parse a relocation. Anything else is an error. */
3887 if (!(entry
= find_reloc_table_entry (&p
)))
3889 set_syntax_error (_("unknown relocation modifier"));
3893 if (entry
->adrp_type
== 0)
3896 (_("this relocation modifier is not allowed on this instruction"));
3900 inst
.reloc
.type
= entry
->adrp_type
;
3903 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3905 inst
.reloc
.pc_rel
= 1;
3907 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3914 /* Miscellaneous. */
3916 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3917 of SIZE tokens in which index I gives the token for field value I,
3918 or is null if field value I is invalid. REG_TYPE says which register
3919 names should be treated as registers rather than as symbolic immediates.
3921 Return true on success, moving *STR past the operand and storing the
3922 field value in *VAL. */
3925 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3926 size_t size
, aarch64_reg_type reg_type
)
3932 /* Match C-like tokens. */
3934 while (ISALNUM (*q
))
3937 for (i
= 0; i
< size
; ++i
)
3939 && strncasecmp (array
[i
], p
, q
- p
) == 0
3940 && array
[i
][q
- p
] == 0)
3947 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3950 if (exp
.X_op
== O_constant
3951 && (uint64_t) exp
.X_add_number
< size
)
3953 *val
= exp
.X_add_number
;
3958 /* Use the default error for this operand. */
3962 /* Parse an option for a preload instruction. Returns the encoding for the
3963 option, or PARSE_FAIL. */
3966 parse_pldop (char **str
)
3969 const struct aarch64_name_value_pair
*o
;
3972 while (ISALNUM (*q
))
3975 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3983 /* Parse an option for a barrier instruction. Returns the encoding for the
3984 option, or PARSE_FAIL. */
3987 parse_barrier (char **str
)
3990 const struct aarch64_name_value_pair
*o
;
3993 while (ISALPHA (*q
))
3996 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4004 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4005 return 0 if successful. Otherwise return PARSE_FAIL. */
4008 parse_barrier_psb (char **str
,
4009 const struct aarch64_name_value_pair
** hint_opt
)
4012 const struct aarch64_name_value_pair
*o
;
4015 while (ISALPHA (*q
))
4018 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4021 set_fatal_syntax_error
4022 ( _("unknown or missing option to PSB/TSB"));
4026 if (o
->value
!= 0x11)
4028 /* PSB only accepts option name 'CSYNC'. */
4030 (_("the specified option is not accepted for PSB/TSB"));
4039 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4040 return 0 if successful. Otherwise return PARSE_FAIL. */
4043 parse_bti_operand (char **str
,
4044 const struct aarch64_name_value_pair
** hint_opt
)
4047 const struct aarch64_name_value_pair
*o
;
4050 while (ISALPHA (*q
))
4053 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4056 set_fatal_syntax_error
4057 ( _("unknown option to BTI"));
4063 /* Valid BTI operands. */
4071 (_("unknown option to BTI"));
4080 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4081 Returns the encoding for the option, or PARSE_FAIL.
4083 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4084 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4086 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4087 field, otherwise as a system register.
4091 parse_sys_reg (char **str
, htab_t sys_regs
,
4092 int imple_defined_p
, int pstatefield_p
,
4096 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4097 const aarch64_sys_reg
*o
;
4101 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4102 if (p
< buf
+ (sizeof (buf
) - 1))
4103 *p
++ = TOLOWER (*q
);
4106 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4107 valid system register. This is enforced by construction of the hash
4109 if (p
- buf
!= q
- *str
)
4112 o
= str_hash_find (sys_regs
, buf
);
4115 if (!imple_defined_p
)
4119 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4120 unsigned int op0
, op1
, cn
, cm
, op2
;
4122 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4125 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4127 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4134 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4135 as_bad (_("selected processor does not support PSTATE field "
4138 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4139 o
->value
, o
->flags
, o
->features
))
4140 as_bad (_("selected processor does not support system register "
4142 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4143 as_warn (_("system register name '%s' is deprecated and may be "
4144 "removed in a future release"), buf
);
4154 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4155 for the option, or NULL. */
4157 static const aarch64_sys_ins_reg
*
4158 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4161 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4162 const aarch64_sys_ins_reg
*o
;
4165 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4166 if (p
< buf
+ (sizeof (buf
) - 1))
4167 *p
++ = TOLOWER (*q
);
4170 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4171 valid system register. This is enforced by construction of the hash
4173 if (p
- buf
!= q
- *str
)
4176 o
= str_hash_find (sys_ins_regs
, buf
);
4180 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4181 o
->name
, o
->value
, o
->flags
, 0))
4182 as_bad (_("selected processor does not support system register "
4184 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4185 as_warn (_("system register name '%s' is deprecated and may be "
4186 "removed in a future release"), buf
);
4192 #define po_char_or_fail(chr) do { \
4193 if (! skip_past_char (&str, chr)) \
4197 #define po_reg_or_fail(regtype) do { \
4198 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4199 if (val == PARSE_FAIL) \
4201 set_default_error (); \
4206 #define po_int_reg_or_fail(reg_type) do { \
4207 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4208 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4210 set_default_error (); \
4213 info->reg.regno = reg->number; \
4214 info->qualifier = qualifier; \
4217 #define po_imm_nc_or_fail() do { \
4218 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4222 #define po_imm_or_fail(min, max) do { \
4223 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4225 if (val < min || val > max) \
4227 set_fatal_syntax_error (_("immediate value out of range "\
4228 #min " to "#max)); \
4233 #define po_enum_or_fail(array) do { \
4234 if (!parse_enum_string (&str, &val, array, \
4235 ARRAY_SIZE (array), imm_reg_type)) \
4239 #define po_misc_or_fail(expr) do { \
4244 /* encode the 12-bit imm field of Add/sub immediate */
4245 static inline uint32_t
4246 encode_addsub_imm (uint32_t imm
)
4251 /* encode the shift amount field of Add/sub immediate */
4252 static inline uint32_t
4253 encode_addsub_imm_shift_amount (uint32_t cnt
)
4259 /* encode the imm field of Adr instruction */
4260 static inline uint32_t
4261 encode_adr_imm (uint32_t imm
)
4263 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4264 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4267 /* encode the immediate field of Move wide immediate */
4268 static inline uint32_t
4269 encode_movw_imm (uint32_t imm
)
4274 /* encode the 26-bit offset of unconditional branch */
4275 static inline uint32_t
4276 encode_branch_ofs_26 (uint32_t ofs
)
4278 return ofs
& ((1 << 26) - 1);
4281 /* encode the 19-bit offset of conditional branch and compare & branch */
4282 static inline uint32_t
4283 encode_cond_branch_ofs_19 (uint32_t ofs
)
4285 return (ofs
& ((1 << 19) - 1)) << 5;
4288 /* encode the 19-bit offset of ld literal */
4289 static inline uint32_t
4290 encode_ld_lit_ofs_19 (uint32_t ofs
)
4292 return (ofs
& ((1 << 19) - 1)) << 5;
4295 /* Encode the 14-bit offset of test & branch. */
4296 static inline uint32_t
4297 encode_tst_branch_ofs_14 (uint32_t ofs
)
4299 return (ofs
& ((1 << 14) - 1)) << 5;
4302 /* Encode the 16-bit imm field of svc/hvc/smc. */
4303 static inline uint32_t
4304 encode_svc_imm (uint32_t imm
)
4309 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4310 static inline uint32_t
4311 reencode_addsub_switch_add_sub (uint32_t opcode
)
4313 return opcode
^ (1 << 30);
4316 static inline uint32_t
4317 reencode_movzn_to_movz (uint32_t opcode
)
4319 return opcode
| (1 << 30);
4322 static inline uint32_t
4323 reencode_movzn_to_movn (uint32_t opcode
)
4325 return opcode
& ~(1 << 30);
4328 /* Overall per-instruction processing. */
4330 /* We need to be able to fix up arbitrary expressions in some statements.
4331 This is so that we can handle symbols that are an arbitrary distance from
4332 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4333 which returns part of an address in a form which will be valid for
4334 a data instruction. We do this by pushing the expression into a symbol
4335 in the expr_section, and creating a fix for that. */
4338 fix_new_aarch64 (fragS
* frag
,
4353 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4357 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4364 /* Diagnostics on operands errors. */
4366 /* By default, output verbose error message.
4367 Disable the verbose error message by -mno-verbose-error. */
4368 static int verbose_error_p
= 1;
4370 #ifdef DEBUG_AARCH64
4371 /* N.B. this is only for the purpose of debugging. */
4372 const char* operand_mismatch_kind_names
[] =
4375 "AARCH64_OPDE_RECOVERABLE",
4376 "AARCH64_OPDE_SYNTAX_ERROR",
4377 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4378 "AARCH64_OPDE_INVALID_VARIANT",
4379 "AARCH64_OPDE_OUT_OF_RANGE",
4380 "AARCH64_OPDE_UNALIGNED",
4381 "AARCH64_OPDE_REG_LIST",
4382 "AARCH64_OPDE_OTHER_ERROR",
4384 #endif /* DEBUG_AARCH64 */
4386 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4388 When multiple errors of different kinds are found in the same assembly
4389 line, only the error of the highest severity will be picked up for
4390 issuing the diagnostics. */
4392 static inline bfd_boolean
4393 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4394 enum aarch64_operand_error_kind rhs
)
4396 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4397 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4398 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4399 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4400 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4401 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4402 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4403 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4407 /* Helper routine to get the mnemonic name from the assembly instruction
4408 line; should only be called for the diagnosis purpose, as there is
4409 string copy operation involved, which may affect the runtime
4410 performance if used in elsewhere. */
4413 get_mnemonic_name (const char *str
)
4415 static char mnemonic
[32];
4418 /* Get the first 15 bytes and assume that the full name is included. */
4419 strncpy (mnemonic
, str
, 31);
4420 mnemonic
[31] = '\0';
4422 /* Scan up to the end of the mnemonic, which must end in white space,
4423 '.', or end of string. */
4424 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4429 /* Append '...' to the truncated long name. */
4430 if (ptr
- mnemonic
== 31)
4431 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4437 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4439 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4440 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4443 /* Data structures storing one user error in the assembly code related to
4446 struct operand_error_record
4448 const aarch64_opcode
*opcode
;
4449 aarch64_operand_error detail
;
4450 struct operand_error_record
*next
;
4453 typedef struct operand_error_record operand_error_record
;
4455 struct operand_errors
4457 operand_error_record
*head
;
4458 operand_error_record
*tail
;
4461 typedef struct operand_errors operand_errors
;
4463 /* Top-level data structure reporting user errors for the current line of
4465 The way md_assemble works is that all opcodes sharing the same mnemonic
4466 name are iterated to find a match to the assembly line. In this data
4467 structure, each of the such opcodes will have one operand_error_record
4468 allocated and inserted. In other words, excessive errors related with
4469 a single opcode are disregarded. */
4470 operand_errors operand_error_report
;
4472 /* Free record nodes. */
4473 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4475 /* Initialize the data structure that stores the operand mismatch
4476 information on assembling one line of the assembly code. */
4478 init_operand_error_report (void)
4480 if (operand_error_report
.head
!= NULL
)
4482 gas_assert (operand_error_report
.tail
!= NULL
);
4483 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4484 free_opnd_error_record_nodes
= operand_error_report
.head
;
4485 operand_error_report
.head
= NULL
;
4486 operand_error_report
.tail
= NULL
;
4489 gas_assert (operand_error_report
.tail
== NULL
);
4492 /* Return TRUE if some operand error has been recorded during the
4493 parsing of the current assembly line using the opcode *OPCODE;
4494 otherwise return FALSE. */
4495 static inline bfd_boolean
4496 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4498 operand_error_record
*record
= operand_error_report
.head
;
4499 return record
&& record
->opcode
== opcode
;
4502 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4503 OPCODE field is initialized with OPCODE.
4504 N.B. only one record for each opcode, i.e. the maximum of one error is
4505 recorded for each instruction template. */
4508 add_operand_error_record (const operand_error_record
* new_record
)
4510 const aarch64_opcode
*opcode
= new_record
->opcode
;
4511 operand_error_record
* record
= operand_error_report
.head
;
4513 /* The record may have been created for this opcode. If not, we need
4515 if (! opcode_has_operand_error_p (opcode
))
4517 /* Get one empty record. */
4518 if (free_opnd_error_record_nodes
== NULL
)
4520 record
= XNEW (operand_error_record
);
4524 record
= free_opnd_error_record_nodes
;
4525 free_opnd_error_record_nodes
= record
->next
;
4527 record
->opcode
= opcode
;
4528 /* Insert at the head. */
4529 record
->next
= operand_error_report
.head
;
4530 operand_error_report
.head
= record
;
4531 if (operand_error_report
.tail
== NULL
)
4532 operand_error_report
.tail
= record
;
4534 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4535 && record
->detail
.index
<= new_record
->detail
.index
4536 && operand_error_higher_severity_p (record
->detail
.kind
,
4537 new_record
->detail
.kind
))
4539 /* In the case of multiple errors found on operands related with a
4540 single opcode, only record the error of the leftmost operand and
4541 only if the error is of higher severity. */
4542 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4543 " the existing error %s on operand %d",
4544 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4545 new_record
->detail
.index
,
4546 operand_mismatch_kind_names
[record
->detail
.kind
],
4547 record
->detail
.index
);
4551 record
->detail
= new_record
->detail
;
4555 record_operand_error_info (const aarch64_opcode
*opcode
,
4556 aarch64_operand_error
*error_info
)
4558 operand_error_record record
;
4559 record
.opcode
= opcode
;
4560 record
.detail
= *error_info
;
4561 add_operand_error_record (&record
);
4564 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4565 error message *ERROR, for operand IDX (count from 0). */
4568 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4569 enum aarch64_operand_error_kind kind
,
4572 aarch64_operand_error info
;
4573 memset(&info
, 0, sizeof (info
));
4577 info
.non_fatal
= FALSE
;
4578 record_operand_error_info (opcode
, &info
);
4582 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4583 enum aarch64_operand_error_kind kind
,
4584 const char* error
, const int *extra_data
)
4586 aarch64_operand_error info
;
4590 info
.data
[0] = extra_data
[0];
4591 info
.data
[1] = extra_data
[1];
4592 info
.data
[2] = extra_data
[2];
4593 info
.non_fatal
= FALSE
;
4594 record_operand_error_info (opcode
, &info
);
4598 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4599 const char* error
, int lower_bound
,
4602 int data
[3] = {lower_bound
, upper_bound
, 0};
4603 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4607 /* Remove the operand error record for *OPCODE. */
4608 static void ATTRIBUTE_UNUSED
4609 remove_operand_error_record (const aarch64_opcode
*opcode
)
4611 if (opcode_has_operand_error_p (opcode
))
4613 operand_error_record
* record
= operand_error_report
.head
;
4614 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4615 operand_error_report
.head
= record
->next
;
4616 record
->next
= free_opnd_error_record_nodes
;
4617 free_opnd_error_record_nodes
= record
;
4618 if (operand_error_report
.head
== NULL
)
4620 gas_assert (operand_error_report
.tail
== record
);
4621 operand_error_report
.tail
= NULL
;
4626 /* Given the instruction in *INSTR, return the index of the best matched
4627 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4629 Return -1 if there is no qualifier sequence; return the first match
4630 if there is multiple matches found. */
4633 find_best_match (const aarch64_inst
*instr
,
4634 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4636 int i
, num_opnds
, max_num_matched
, idx
;
4638 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4641 DEBUG_TRACE ("no operand");
4645 max_num_matched
= 0;
4648 /* For each pattern. */
4649 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4652 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4654 /* Most opcodes has much fewer patterns in the list. */
4655 if (empty_qualifier_sequence_p (qualifiers
))
4657 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4661 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4662 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4665 if (num_matched
> max_num_matched
)
4667 max_num_matched
= num_matched
;
4672 DEBUG_TRACE ("return with %d", idx
);
4676 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4677 corresponding operands in *INSTR. */
4680 assign_qualifier_sequence (aarch64_inst
*instr
,
4681 const aarch64_opnd_qualifier_t
*qualifiers
)
4684 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4685 gas_assert (num_opnds
);
4686 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4687 instr
->operands
[i
].qualifier
= *qualifiers
;
4690 /* Print operands for the diagnosis purpose. */
4693 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4694 const aarch64_opnd_info
*opnds
)
4698 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4702 /* We regard the opcode operand info more, however we also look into
4703 the inst->operands to support the disassembling of the optional
4705 The two operand code should be the same in all cases, apart from
4706 when the operand can be optional. */
4707 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4708 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4711 /* Generate the operand string in STR. */
4712 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4717 strcat (buf
, i
== 0 ? " " : ", ");
4719 /* Append the operand string. */
4724 /* Send to stderr a string as information. */
4727 output_info (const char *format
, ...)
4733 file
= as_where (&line
);
4737 fprintf (stderr
, "%s:%u: ", file
, line
);
4739 fprintf (stderr
, "%s: ", file
);
4741 fprintf (stderr
, _("Info: "));
4742 va_start (args
, format
);
4743 vfprintf (stderr
, format
, args
);
4745 (void) putc ('\n', stderr
);
4748 /* Output one operand error record. */
4751 output_operand_error_record (const operand_error_record
*record
, char *str
)
4753 const aarch64_operand_error
*detail
= &record
->detail
;
4754 int idx
= detail
->index
;
4755 const aarch64_opcode
*opcode
= record
->opcode
;
4756 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4757 : AARCH64_OPND_NIL
);
4759 typedef void (*handler_t
)(const char *format
, ...);
4760 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4762 switch (detail
->kind
)
4764 case AARCH64_OPDE_NIL
:
4767 case AARCH64_OPDE_SYNTAX_ERROR
:
4768 case AARCH64_OPDE_RECOVERABLE
:
4769 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4770 case AARCH64_OPDE_OTHER_ERROR
:
4771 /* Use the prepared error message if there is, otherwise use the
4772 operand description string to describe the error. */
4773 if (detail
->error
!= NULL
)
4776 handler (_("%s -- `%s'"), detail
->error
, str
);
4778 handler (_("%s at operand %d -- `%s'"),
4779 detail
->error
, idx
+ 1, str
);
4783 gas_assert (idx
>= 0);
4784 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4785 aarch64_get_operand_desc (opd_code
), str
);
4789 case AARCH64_OPDE_INVALID_VARIANT
:
4790 handler (_("operand mismatch -- `%s'"), str
);
4791 if (verbose_error_p
)
4793 /* We will try to correct the erroneous instruction and also provide
4794 more information e.g. all other valid variants.
4796 The string representation of the corrected instruction and other
4797 valid variants are generated by
4799 1) obtaining the intermediate representation of the erroneous
4801 2) manipulating the IR, e.g. replacing the operand qualifier;
4802 3) printing out the instruction by calling the printer functions
4803 shared with the disassembler.
4805 The limitation of this method is that the exact input assembly
4806 line cannot be accurately reproduced in some cases, for example an
4807 optional operand present in the actual assembly line will be
4808 omitted in the output; likewise for the optional syntax rules,
4809 e.g. the # before the immediate. Another limitation is that the
4810 assembly symbols and relocation operations in the assembly line
4811 currently cannot be printed out in the error report. Last but not
4812 least, when there is other error(s) co-exist with this error, the
4813 'corrected' instruction may be still incorrect, e.g. given
4814 'ldnp h0,h1,[x0,#6]!'
4815 this diagnosis will provide the version:
4816 'ldnp s0,s1,[x0,#6]!'
4817 which is still not right. */
4818 size_t len
= strlen (get_mnemonic_name (str
));
4822 aarch64_inst
*inst_base
= &inst
.base
;
4823 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4826 reset_aarch64_instruction (&inst
);
4827 inst_base
->opcode
= opcode
;
4829 /* Reset the error report so that there is no side effect on the
4830 following operand parsing. */
4831 init_operand_error_report ();
4834 result
= parse_operands (str
+ len
, opcode
)
4835 && programmer_friendly_fixup (&inst
);
4836 gas_assert (result
);
4837 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4838 NULL
, NULL
, insn_sequence
);
4839 gas_assert (!result
);
4841 /* Find the most matched qualifier sequence. */
4842 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4843 gas_assert (qlf_idx
> -1);
4845 /* Assign the qualifiers. */
4846 assign_qualifier_sequence (inst_base
,
4847 opcode
->qualifiers_list
[qlf_idx
]);
4849 /* Print the hint. */
4850 output_info (_(" did you mean this?"));
4851 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4852 print_operands (buf
, opcode
, inst_base
->operands
);
4853 output_info (_(" %s"), buf
);
4855 /* Print out other variant(s) if there is any. */
4857 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4858 output_info (_(" other valid variant(s):"));
4860 /* For each pattern. */
4861 qualifiers_list
= opcode
->qualifiers_list
;
4862 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4864 /* Most opcodes has much fewer patterns in the list.
4865 First NIL qualifier indicates the end in the list. */
4866 if (empty_qualifier_sequence_p (*qualifiers_list
))
4871 /* Mnemonics name. */
4872 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4874 /* Assign the qualifiers. */
4875 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4877 /* Print instruction. */
4878 print_operands (buf
, opcode
, inst_base
->operands
);
4880 output_info (_(" %s"), buf
);
4886 case AARCH64_OPDE_UNTIED_OPERAND
:
4887 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4888 detail
->index
+ 1, str
);
4891 case AARCH64_OPDE_OUT_OF_RANGE
:
4892 if (detail
->data
[0] != detail
->data
[1])
4893 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4894 detail
->error
? detail
->error
: _("immediate value"),
4895 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4897 handler (_("%s must be %d at operand %d -- `%s'"),
4898 detail
->error
? detail
->error
: _("immediate value"),
4899 detail
->data
[0], idx
+ 1, str
);
4902 case AARCH64_OPDE_REG_LIST
:
4903 if (detail
->data
[0] == 1)
4904 handler (_("invalid number of registers in the list; "
4905 "only 1 register is expected at operand %d -- `%s'"),
4908 handler (_("invalid number of registers in the list; "
4909 "%d registers are expected at operand %d -- `%s'"),
4910 detail
->data
[0], idx
+ 1, str
);
4913 case AARCH64_OPDE_UNALIGNED
:
4914 handler (_("immediate value must be a multiple of "
4915 "%d at operand %d -- `%s'"),
4916 detail
->data
[0], idx
+ 1, str
);
4925 /* Process and output the error message about the operand mismatching.
4927 When this function is called, the operand error information had
4928 been collected for an assembly line and there will be multiple
4929 errors in the case of multiple instruction templates; output the
4930 error message that most closely describes the problem.
4932 The errors to be printed can be filtered on printing all errors
4933 or only non-fatal errors. This distinction has to be made because
4934 the error buffer may already be filled with fatal errors we don't want to
4935 print due to the different instruction templates. */
4938 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4940 int largest_error_pos
;
4941 const char *msg
= NULL
;
4942 enum aarch64_operand_error_kind kind
;
4943 operand_error_record
*curr
;
4944 operand_error_record
*head
= operand_error_report
.head
;
4945 operand_error_record
*record
= NULL
;
4947 /* No error to report. */
4951 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4953 /* Only one error. */
4954 if (head
== operand_error_report
.tail
)
4956 /* If the only error is a non-fatal one and we don't want to print it,
4958 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4960 DEBUG_TRACE ("single opcode entry with error kind: %s",
4961 operand_mismatch_kind_names
[head
->detail
.kind
]);
4962 output_operand_error_record (head
, str
);
4967 /* Find the error kind of the highest severity. */
4968 DEBUG_TRACE ("multiple opcode entries with error kind");
4969 kind
= AARCH64_OPDE_NIL
;
4970 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4972 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4973 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4974 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4975 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4976 kind
= curr
->detail
.kind
;
4979 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4981 /* Pick up one of errors of KIND to report. */
4982 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4983 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4985 /* If we don't want to print non-fatal errors then don't consider them
4987 if (curr
->detail
.kind
!= kind
4988 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4990 /* If there are multiple errors, pick up the one with the highest
4991 mismatching operand index. In the case of multiple errors with
4992 the equally highest operand index, pick up the first one or the
4993 first one with non-NULL error message. */
4994 if (curr
->detail
.index
> largest_error_pos
4995 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4996 && curr
->detail
.error
!= NULL
))
4998 largest_error_pos
= curr
->detail
.index
;
5000 msg
= record
->detail
.error
;
5004 /* The way errors are collected in the back-end is a bit non-intuitive. But
5005 essentially, because each operand template is tried recursively you may
5006 always have errors collected from the previous tried OPND. These are
5007 usually skipped if there is one successful match. However now with the
5008 non-fatal errors we have to ignore those previously collected hard errors
5009 when we're only interested in printing the non-fatal ones. This condition
5010 prevents us from printing errors that are not appropriate, since we did
5011 match a condition, but it also has warnings that it wants to print. */
5012 if (non_fatal_only
&& !record
)
5015 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5016 DEBUG_TRACE ("Pick up error kind %s to report",
5017 operand_mismatch_kind_names
[record
->detail
.kind
]);
5020 output_operand_error_record (record
, str
);
5023 /* Write an AARCH64 instruction to buf - always little-endian. */
5025 put_aarch64_insn (char *buf
, uint32_t insn
)
5027 unsigned char *where
= (unsigned char *) buf
;
5029 where
[1] = insn
>> 8;
5030 where
[2] = insn
>> 16;
5031 where
[3] = insn
>> 24;
5035 get_aarch64_insn (char *buf
)
5037 unsigned char *where
= (unsigned char *) buf
;
5039 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5040 | ((uint32_t) where
[3] << 24)));
5045 output_inst (struct aarch64_inst
*new_inst
)
5049 to
= frag_more (INSN_SIZE
);
5051 frag_now
->tc_frag_data
.recorded
= 1;
5053 put_aarch64_insn (to
, inst
.base
.value
);
5055 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5057 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5058 INSN_SIZE
, &inst
.reloc
.exp
,
5061 DEBUG_TRACE ("Prepared relocation fix up");
5062 /* Don't check the addend value against the instruction size,
5063 that's the job of our code in md_apply_fix(). */
5064 fixp
->fx_no_overflow
= 1;
5065 if (new_inst
!= NULL
)
5066 fixp
->tc_fix_data
.inst
= new_inst
;
5067 if (aarch64_gas_internal_fixup_p ())
5069 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5070 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5071 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5075 dwarf2_emit_insn (INSN_SIZE
);
5078 /* Link together opcodes of the same name. */
5082 aarch64_opcode
*opcode
;
5083 struct templates
*next
;
5086 typedef struct templates templates
;
5089 lookup_mnemonic (const char *start
, int len
)
5091 templates
*templ
= NULL
;
5093 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5097 /* Subroutine of md_assemble, responsible for looking up the primary
5098 opcode from the mnemonic the user wrote. STR points to the
5099 beginning of the mnemonic. */
5102 opcode_lookup (char **str
)
5104 char *end
, *base
, *dot
;
5105 const aarch64_cond
*cond
;
5109 /* Scan up to the end of the mnemonic, which must end in white space,
5110 '.', or end of string. */
5112 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5113 if (*end
== '.' && !dot
)
5116 if (end
== base
|| dot
== base
)
5119 inst
.cond
= COND_ALWAYS
;
5121 /* Handle a possible condition. */
5124 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5127 inst
.cond
= cond
->value
;
5143 if (inst
.cond
== COND_ALWAYS
)
5145 /* Look for unaffixed mnemonic. */
5146 return lookup_mnemonic (base
, len
);
5150 /* append ".c" to mnemonic if conditional */
5151 memcpy (condname
, base
, len
);
5152 memcpy (condname
+ len
, ".c", 2);
5155 return lookup_mnemonic (base
, len
);
5161 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5162 to a corresponding operand qualifier. */
5164 static inline aarch64_opnd_qualifier_t
5165 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5167 /* Element size in bytes indexed by vector_el_type. */
5168 const unsigned char ele_size
[5]
5170 const unsigned int ele_base
[5] =
5172 AARCH64_OPND_QLF_V_4B
,
5173 AARCH64_OPND_QLF_V_2H
,
5174 AARCH64_OPND_QLF_V_2S
,
5175 AARCH64_OPND_QLF_V_1D
,
5176 AARCH64_OPND_QLF_V_1Q
5179 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5180 goto vectype_conversion_fail
;
5182 if (vectype
->type
== NT_zero
)
5183 return AARCH64_OPND_QLF_P_Z
;
5184 if (vectype
->type
== NT_merge
)
5185 return AARCH64_OPND_QLF_P_M
;
5187 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5189 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5191 /* Special case S_4B. */
5192 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5193 return AARCH64_OPND_QLF_S_4B
;
5195 /* Special case S_2H. */
5196 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5197 return AARCH64_OPND_QLF_S_2H
;
5199 /* Vector element register. */
5200 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5204 /* Vector register. */
5205 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5208 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5209 goto vectype_conversion_fail
;
5211 /* The conversion is by calculating the offset from the base operand
5212 qualifier for the vector type. The operand qualifiers are regular
5213 enough that the offset can established by shifting the vector width by
5214 a vector-type dependent amount. */
5216 if (vectype
->type
== NT_b
)
5218 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5220 else if (vectype
->type
>= NT_d
)
5225 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5226 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5227 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5231 vectype_conversion_fail
:
5232 first_error (_("bad vector arrangement type"));
5233 return AARCH64_OPND_QLF_NIL
;
5236 /* Process an optional operand that is found omitted from the assembly line.
5237 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5238 instruction's opcode entry while IDX is the index of this omitted operand.
5242 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5243 int idx
, aarch64_opnd_info
*operand
)
5245 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5246 gas_assert (optional_operand_p (opcode
, idx
));
5247 gas_assert (!operand
->present
);
5251 case AARCH64_OPND_Rd
:
5252 case AARCH64_OPND_Rn
:
5253 case AARCH64_OPND_Rm
:
5254 case AARCH64_OPND_Rt
:
5255 case AARCH64_OPND_Rt2
:
5256 case AARCH64_OPND_Rt_LS64
:
5257 case AARCH64_OPND_Rt_SP
:
5258 case AARCH64_OPND_Rs
:
5259 case AARCH64_OPND_Ra
:
5260 case AARCH64_OPND_Rt_SYS
:
5261 case AARCH64_OPND_Rd_SP
:
5262 case AARCH64_OPND_Rn_SP
:
5263 case AARCH64_OPND_Rm_SP
:
5264 case AARCH64_OPND_Fd
:
5265 case AARCH64_OPND_Fn
:
5266 case AARCH64_OPND_Fm
:
5267 case AARCH64_OPND_Fa
:
5268 case AARCH64_OPND_Ft
:
5269 case AARCH64_OPND_Ft2
:
5270 case AARCH64_OPND_Sd
:
5271 case AARCH64_OPND_Sn
:
5272 case AARCH64_OPND_Sm
:
5273 case AARCH64_OPND_Va
:
5274 case AARCH64_OPND_Vd
:
5275 case AARCH64_OPND_Vn
:
5276 case AARCH64_OPND_Vm
:
5277 case AARCH64_OPND_VdD1
:
5278 case AARCH64_OPND_VnD1
:
5279 operand
->reg
.regno
= default_value
;
5282 case AARCH64_OPND_Ed
:
5283 case AARCH64_OPND_En
:
5284 case AARCH64_OPND_Em
:
5285 case AARCH64_OPND_Em16
:
5286 case AARCH64_OPND_SM3_IMM2
:
5287 operand
->reglane
.regno
= default_value
;
5290 case AARCH64_OPND_IDX
:
5291 case AARCH64_OPND_BIT_NUM
:
5292 case AARCH64_OPND_IMMR
:
5293 case AARCH64_OPND_IMMS
:
5294 case AARCH64_OPND_SHLL_IMM
:
5295 case AARCH64_OPND_IMM_VLSL
:
5296 case AARCH64_OPND_IMM_VLSR
:
5297 case AARCH64_OPND_CCMP_IMM
:
5298 case AARCH64_OPND_FBITS
:
5299 case AARCH64_OPND_UIMM4
:
5300 case AARCH64_OPND_UIMM3_OP1
:
5301 case AARCH64_OPND_UIMM3_OP2
:
5302 case AARCH64_OPND_IMM
:
5303 case AARCH64_OPND_IMM_2
:
5304 case AARCH64_OPND_WIDTH
:
5305 case AARCH64_OPND_UIMM7
:
5306 case AARCH64_OPND_NZCV
:
5307 case AARCH64_OPND_SVE_PATTERN
:
5308 case AARCH64_OPND_SVE_PRFOP
:
5309 operand
->imm
.value
= default_value
;
5312 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5313 operand
->imm
.value
= default_value
;
5314 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5315 operand
->shifter
.amount
= 1;
5318 case AARCH64_OPND_EXCEPTION
:
5319 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5322 case AARCH64_OPND_BARRIER_ISB
:
5323 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5326 case AARCH64_OPND_BTI_TARGET
:
5327 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5335 /* Process the relocation type for move wide instructions.
5336 Return TRUE on success; otherwise return FALSE. */
5339 process_movw_reloc_info (void)
5344 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5346 if (inst
.base
.opcode
->op
== OP_MOVK
)
5347 switch (inst
.reloc
.type
)
5349 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5350 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5351 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5352 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5353 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5354 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5355 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5356 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5357 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5358 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5359 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5361 (_("the specified relocation type is not allowed for MOVK"));
5367 switch (inst
.reloc
.type
)
5369 case BFD_RELOC_AARCH64_MOVW_G0
:
5370 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5371 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5372 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5373 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5374 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5375 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5376 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5377 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5378 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5379 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5380 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5381 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5384 case BFD_RELOC_AARCH64_MOVW_G1
:
5385 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5386 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5387 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5388 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5389 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5390 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5391 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5392 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5393 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5394 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5395 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5396 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5399 case BFD_RELOC_AARCH64_MOVW_G2
:
5400 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5401 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5402 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5403 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5404 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5405 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5408 set_fatal_syntax_error
5409 (_("the specified relocation type is not allowed for 32-bit "
5415 case BFD_RELOC_AARCH64_MOVW_G3
:
5416 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5419 set_fatal_syntax_error
5420 (_("the specified relocation type is not allowed for 32-bit "
5427 /* More cases should be added when more MOVW-related relocation types
5428 are supported in GAS. */
5429 gas_assert (aarch64_gas_internal_fixup_p ());
5430 /* The shift amount should have already been set by the parser. */
5433 inst
.base
.operands
[1].shifter
.amount
= shift
;
5437 /* A primitive log calculator. */
5439 static inline unsigned int
5440 get_logsz (unsigned int size
)
5442 const unsigned char ls
[16] =
5443 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5449 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5450 return ls
[size
- 1];
5453 /* Determine and return the real reloc type code for an instruction
5454 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5456 static inline bfd_reloc_code_real_type
5457 ldst_lo12_determine_real_reloc_type (void)
5460 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5461 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5463 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5465 BFD_RELOC_AARCH64_LDST8_LO12
,
5466 BFD_RELOC_AARCH64_LDST16_LO12
,
5467 BFD_RELOC_AARCH64_LDST32_LO12
,
5468 BFD_RELOC_AARCH64_LDST64_LO12
,
5469 BFD_RELOC_AARCH64_LDST128_LO12
5472 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5473 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5474 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5475 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5476 BFD_RELOC_AARCH64_NONE
5479 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5480 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5481 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5482 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5483 BFD_RELOC_AARCH64_NONE
5486 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5487 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5488 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5489 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5490 BFD_RELOC_AARCH64_NONE
5493 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5494 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5495 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5496 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5497 BFD_RELOC_AARCH64_NONE
5501 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5502 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5504 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5506 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5508 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5509 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5511 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5513 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5515 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5517 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5518 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5519 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5520 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5521 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5522 gas_assert (logsz
<= 3);
5524 gas_assert (logsz
<= 4);
5526 /* In reloc.c, these pseudo relocation types should be defined in similar
5527 order as above reloc_ldst_lo12 array. Because the array index calculation
5528 below relies on this. */
5529 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5532 /* Check whether a register list REGINFO is valid. The registers must be
5533 numbered in increasing order (modulo 32), in increments of one or two.
5535 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5538 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5541 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5543 uint32_t i
, nb_regs
, prev_regno
, incr
;
5545 nb_regs
= 1 + (reginfo
& 0x3);
5547 prev_regno
= reginfo
& 0x1f;
5548 incr
= accept_alternate
? 2 : 1;
5550 for (i
= 1; i
< nb_regs
; ++i
)
5552 uint32_t curr_regno
;
5554 curr_regno
= reginfo
& 0x1f;
5555 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5557 prev_regno
= curr_regno
;
5563 /* Generic instruction operand parser. This does no encoding and no
5564 semantic validation; it merely squirrels values away in the inst
5565 structure. Returns TRUE or FALSE depending on whether the
5566 specified grammar matched. */
5569 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5572 char *backtrack_pos
= 0;
5573 const enum aarch64_opnd
*operands
= opcode
->operands
;
5574 aarch64_reg_type imm_reg_type
;
5577 skip_whitespace (str
);
5579 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5580 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5582 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5584 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5587 const reg_entry
*reg
;
5588 int comma_skipped_p
= 0;
5589 aarch64_reg_type rtype
;
5590 struct vector_type_el vectype
;
5591 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5592 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5593 aarch64_reg_type reg_type
;
5595 DEBUG_TRACE ("parse operand %d", i
);
5597 /* Assign the operand code. */
5598 info
->type
= operands
[i
];
5600 if (optional_operand_p (opcode
, i
))
5602 /* Remember where we are in case we need to backtrack. */
5603 gas_assert (!backtrack_pos
);
5604 backtrack_pos
= str
;
5607 /* Expect comma between operands; the backtrack mechanism will take
5608 care of cases of omitted optional operand. */
5609 if (i
> 0 && ! skip_past_char (&str
, ','))
5611 set_syntax_error (_("comma expected between operands"));
5615 comma_skipped_p
= 1;
5617 switch (operands
[i
])
5619 case AARCH64_OPND_Rd
:
5620 case AARCH64_OPND_Rn
:
5621 case AARCH64_OPND_Rm
:
5622 case AARCH64_OPND_Rt
:
5623 case AARCH64_OPND_Rt2
:
5624 case AARCH64_OPND_Rs
:
5625 case AARCH64_OPND_Ra
:
5626 case AARCH64_OPND_Rt_LS64
:
5627 case AARCH64_OPND_Rt_SYS
:
5628 case AARCH64_OPND_PAIRREG
:
5629 case AARCH64_OPND_SVE_Rm
:
5630 po_int_reg_or_fail (REG_TYPE_R_Z
);
5632 /* In LS64 load/store instructions Rt register number must be even
5634 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
5636 /* We've already checked if this is valid register.
5637 This will check if register number (Rt) is not undefined for LS64
5639 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
5640 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
5642 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
5648 case AARCH64_OPND_Rd_SP
:
5649 case AARCH64_OPND_Rn_SP
:
5650 case AARCH64_OPND_Rt_SP
:
5651 case AARCH64_OPND_SVE_Rn_SP
:
5652 case AARCH64_OPND_Rm_SP
:
5653 po_int_reg_or_fail (REG_TYPE_R_SP
);
5656 case AARCH64_OPND_Rm_EXT
:
5657 case AARCH64_OPND_Rm_SFT
:
5658 po_misc_or_fail (parse_shifter_operand
5659 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5661 : SHIFTED_LOGIC_IMM
)));
5662 if (!info
->shifter
.operator_present
)
5664 /* Default to LSL if not present. Libopcodes prefers shifter
5665 kind to be explicit. */
5666 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5667 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5668 /* For Rm_EXT, libopcodes will carry out further check on whether
5669 or not stack pointer is used in the instruction (Recall that
5670 "the extend operator is not optional unless at least one of
5671 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5675 case AARCH64_OPND_Fd
:
5676 case AARCH64_OPND_Fn
:
5677 case AARCH64_OPND_Fm
:
5678 case AARCH64_OPND_Fa
:
5679 case AARCH64_OPND_Ft
:
5680 case AARCH64_OPND_Ft2
:
5681 case AARCH64_OPND_Sd
:
5682 case AARCH64_OPND_Sn
:
5683 case AARCH64_OPND_Sm
:
5684 case AARCH64_OPND_SVE_VZn
:
5685 case AARCH64_OPND_SVE_Vd
:
5686 case AARCH64_OPND_SVE_Vm
:
5687 case AARCH64_OPND_SVE_Vn
:
5688 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5689 if (val
== PARSE_FAIL
)
5691 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5694 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5696 info
->reg
.regno
= val
;
5697 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5700 case AARCH64_OPND_SVE_Pd
:
5701 case AARCH64_OPND_SVE_Pg3
:
5702 case AARCH64_OPND_SVE_Pg4_5
:
5703 case AARCH64_OPND_SVE_Pg4_10
:
5704 case AARCH64_OPND_SVE_Pg4_16
:
5705 case AARCH64_OPND_SVE_Pm
:
5706 case AARCH64_OPND_SVE_Pn
:
5707 case AARCH64_OPND_SVE_Pt
:
5708 reg_type
= REG_TYPE_PN
;
5711 case AARCH64_OPND_SVE_Za_5
:
5712 case AARCH64_OPND_SVE_Za_16
:
5713 case AARCH64_OPND_SVE_Zd
:
5714 case AARCH64_OPND_SVE_Zm_5
:
5715 case AARCH64_OPND_SVE_Zm_16
:
5716 case AARCH64_OPND_SVE_Zn
:
5717 case AARCH64_OPND_SVE_Zt
:
5718 reg_type
= REG_TYPE_ZN
;
5721 case AARCH64_OPND_Va
:
5722 case AARCH64_OPND_Vd
:
5723 case AARCH64_OPND_Vn
:
5724 case AARCH64_OPND_Vm
:
5725 reg_type
= REG_TYPE_VN
;
5727 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5728 if (val
== PARSE_FAIL
)
5730 first_error (_(get_reg_expected_msg (reg_type
)));
5733 if (vectype
.defined
& NTA_HASINDEX
)
5736 info
->reg
.regno
= val
;
5737 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5738 && vectype
.type
== NT_invtype
)
5739 /* Unqualified Pn and Zn registers are allowed in certain
5740 contexts. Rely on F_STRICT qualifier checking to catch
5742 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5745 info
->qualifier
= vectype_to_qualifier (&vectype
);
5746 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5751 case AARCH64_OPND_VdD1
:
5752 case AARCH64_OPND_VnD1
:
5753 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5754 if (val
== PARSE_FAIL
)
5756 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5759 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5761 set_fatal_syntax_error
5762 (_("the top half of a 128-bit FP/SIMD register is expected"));
5765 info
->reg
.regno
= val
;
5766 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5767 here; it is correct for the purpose of encoding/decoding since
5768 only the register number is explicitly encoded in the related
5769 instructions, although this appears a bit hacky. */
5770 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5773 case AARCH64_OPND_SVE_Zm3_INDEX
:
5774 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5775 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5776 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5777 case AARCH64_OPND_SVE_Zm4_INDEX
:
5778 case AARCH64_OPND_SVE_Zn_INDEX
:
5779 reg_type
= REG_TYPE_ZN
;
5780 goto vector_reg_index
;
5782 case AARCH64_OPND_Ed
:
5783 case AARCH64_OPND_En
:
5784 case AARCH64_OPND_Em
:
5785 case AARCH64_OPND_Em16
:
5786 case AARCH64_OPND_SM3_IMM2
:
5787 reg_type
= REG_TYPE_VN
;
5789 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5790 if (val
== PARSE_FAIL
)
5792 first_error (_(get_reg_expected_msg (reg_type
)));
5795 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5798 info
->reglane
.regno
= val
;
5799 info
->reglane
.index
= vectype
.index
;
5800 info
->qualifier
= vectype_to_qualifier (&vectype
);
5801 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5805 case AARCH64_OPND_SVE_ZnxN
:
5806 case AARCH64_OPND_SVE_ZtxN
:
5807 reg_type
= REG_TYPE_ZN
;
5808 goto vector_reg_list
;
5810 case AARCH64_OPND_LVn
:
5811 case AARCH64_OPND_LVt
:
5812 case AARCH64_OPND_LVt_AL
:
5813 case AARCH64_OPND_LEt
:
5814 reg_type
= REG_TYPE_VN
;
5816 if (reg_type
== REG_TYPE_ZN
5817 && get_opcode_dependent_value (opcode
) == 1
5820 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5821 if (val
== PARSE_FAIL
)
5823 first_error (_(get_reg_expected_msg (reg_type
)));
5826 info
->reglist
.first_regno
= val
;
5827 info
->reglist
.num_regs
= 1;
5831 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5832 if (val
== PARSE_FAIL
)
5835 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5837 set_fatal_syntax_error (_("invalid register list"));
5841 if (vectype
.width
!= 0 && *str
!= ',')
5843 set_fatal_syntax_error
5844 (_("expected element type rather than vector type"));
5848 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5849 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5851 if (operands
[i
] == AARCH64_OPND_LEt
)
5853 if (!(vectype
.defined
& NTA_HASINDEX
))
5855 info
->reglist
.has_index
= 1;
5856 info
->reglist
.index
= vectype
.index
;
5860 if (vectype
.defined
& NTA_HASINDEX
)
5862 if (!(vectype
.defined
& NTA_HASTYPE
))
5864 if (reg_type
== REG_TYPE_ZN
)
5865 set_fatal_syntax_error (_("missing type suffix"));
5869 info
->qualifier
= vectype_to_qualifier (&vectype
);
5870 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5874 case AARCH64_OPND_CRn
:
5875 case AARCH64_OPND_CRm
:
5877 char prefix
= *(str
++);
5878 if (prefix
!= 'c' && prefix
!= 'C')
5881 po_imm_nc_or_fail ();
5884 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5887 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5888 info
->imm
.value
= val
;
5892 case AARCH64_OPND_SHLL_IMM
:
5893 case AARCH64_OPND_IMM_VLSR
:
5894 po_imm_or_fail (1, 64);
5895 info
->imm
.value
= val
;
5898 case AARCH64_OPND_CCMP_IMM
:
5899 case AARCH64_OPND_SIMM5
:
5900 case AARCH64_OPND_FBITS
:
5901 case AARCH64_OPND_TME_UIMM16
:
5902 case AARCH64_OPND_UIMM4
:
5903 case AARCH64_OPND_UIMM4_ADDG
:
5904 case AARCH64_OPND_UIMM10
:
5905 case AARCH64_OPND_UIMM3_OP1
:
5906 case AARCH64_OPND_UIMM3_OP2
:
5907 case AARCH64_OPND_IMM_VLSL
:
5908 case AARCH64_OPND_IMM
:
5909 case AARCH64_OPND_IMM_2
:
5910 case AARCH64_OPND_WIDTH
:
5911 case AARCH64_OPND_SVE_INV_LIMM
:
5912 case AARCH64_OPND_SVE_LIMM
:
5913 case AARCH64_OPND_SVE_LIMM_MOV
:
5914 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5915 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5916 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
5917 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5918 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5919 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
5920 case AARCH64_OPND_SVE_SIMM5
:
5921 case AARCH64_OPND_SVE_SIMM5B
:
5922 case AARCH64_OPND_SVE_SIMM6
:
5923 case AARCH64_OPND_SVE_SIMM8
:
5924 case AARCH64_OPND_SVE_UIMM3
:
5925 case AARCH64_OPND_SVE_UIMM7
:
5926 case AARCH64_OPND_SVE_UIMM8
:
5927 case AARCH64_OPND_SVE_UIMM8_53
:
5928 case AARCH64_OPND_IMM_ROT1
:
5929 case AARCH64_OPND_IMM_ROT2
:
5930 case AARCH64_OPND_IMM_ROT3
:
5931 case AARCH64_OPND_SVE_IMM_ROT1
:
5932 case AARCH64_OPND_SVE_IMM_ROT2
:
5933 case AARCH64_OPND_SVE_IMM_ROT3
:
5934 po_imm_nc_or_fail ();
5935 info
->imm
.value
= val
;
5938 case AARCH64_OPND_SVE_AIMM
:
5939 case AARCH64_OPND_SVE_ASIMM
:
5940 po_imm_nc_or_fail ();
5941 info
->imm
.value
= val
;
5942 skip_whitespace (str
);
5943 if (skip_past_comma (&str
))
5944 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5946 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5949 case AARCH64_OPND_SVE_PATTERN
:
5950 po_enum_or_fail (aarch64_sve_pattern_array
);
5951 info
->imm
.value
= val
;
5954 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5955 po_enum_or_fail (aarch64_sve_pattern_array
);
5956 info
->imm
.value
= val
;
5957 if (skip_past_comma (&str
)
5958 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5960 if (!info
->shifter
.operator_present
)
5962 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5963 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5964 info
->shifter
.amount
= 1;
5968 case AARCH64_OPND_SVE_PRFOP
:
5969 po_enum_or_fail (aarch64_sve_prfop_array
);
5970 info
->imm
.value
= val
;
5973 case AARCH64_OPND_UIMM7
:
5974 po_imm_or_fail (0, 127);
5975 info
->imm
.value
= val
;
5978 case AARCH64_OPND_IDX
:
5979 case AARCH64_OPND_MASK
:
5980 case AARCH64_OPND_BIT_NUM
:
5981 case AARCH64_OPND_IMMR
:
5982 case AARCH64_OPND_IMMS
:
5983 po_imm_or_fail (0, 63);
5984 info
->imm
.value
= val
;
5987 case AARCH64_OPND_IMM0
:
5988 po_imm_nc_or_fail ();
5991 set_fatal_syntax_error (_("immediate zero expected"));
5994 info
->imm
.value
= 0;
5997 case AARCH64_OPND_FPIMM0
:
6000 bfd_boolean res1
= FALSE
, res2
= FALSE
;
6001 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6002 it is probably not worth the effort to support it. */
6003 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
6006 || !(res2
= parse_constant_immediate (&str
, &val
,
6009 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6011 info
->imm
.value
= 0;
6012 info
->imm
.is_fp
= 1;
6015 set_fatal_syntax_error (_("immediate zero expected"));
6019 case AARCH64_OPND_IMM_MOV
:
6022 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6023 reg_name_p (str
, REG_TYPE_VN
))
6026 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6028 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6029 later. fix_mov_imm_insn will try to determine a machine
6030 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6031 message if the immediate cannot be moved by a single
6033 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6034 inst
.base
.operands
[i
].skip
= 1;
6038 case AARCH64_OPND_SIMD_IMM
:
6039 case AARCH64_OPND_SIMD_IMM_SFT
:
6040 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6042 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6044 /* need_libopcodes_p */ 1,
6047 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6048 shift, we don't check it here; we leave the checking to
6049 the libopcodes (operand_general_constraint_met_p). By
6050 doing this, we achieve better diagnostics. */
6051 if (skip_past_comma (&str
)
6052 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6054 if (!info
->shifter
.operator_present
6055 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6057 /* Default to LSL if not present. Libopcodes prefers shifter
6058 kind to be explicit. */
6059 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6060 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6064 case AARCH64_OPND_FPIMM
:
6065 case AARCH64_OPND_SIMD_FPIMM
:
6066 case AARCH64_OPND_SVE_FPIMM8
:
6071 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6072 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6073 || !aarch64_imm_float_p (qfloat
))
6076 set_fatal_syntax_error (_("invalid floating-point"
6080 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6081 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6085 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6086 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6087 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6092 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6093 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6096 set_fatal_syntax_error (_("invalid floating-point"
6100 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6101 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6105 case AARCH64_OPND_LIMM
:
6106 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6107 SHIFTED_LOGIC_IMM
));
6108 if (info
->shifter
.operator_present
)
6110 set_fatal_syntax_error
6111 (_("shift not allowed for bitmask immediate"));
6114 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6116 /* need_libopcodes_p */ 1,
6120 case AARCH64_OPND_AIMM
:
6121 if (opcode
->op
== OP_ADD
)
6122 /* ADD may have relocation types. */
6123 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6124 SHIFTED_ARITH_IMM
));
6126 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6127 SHIFTED_ARITH_IMM
));
6128 switch (inst
.reloc
.type
)
6130 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6131 info
->shifter
.amount
= 12;
6133 case BFD_RELOC_UNUSED
:
6134 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6135 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6136 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6137 inst
.reloc
.pc_rel
= 0;
6142 info
->imm
.value
= 0;
6143 if (!info
->shifter
.operator_present
)
6145 /* Default to LSL if not present. Libopcodes prefers shifter
6146 kind to be explicit. */
6147 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6148 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6152 case AARCH64_OPND_HALF
:
6154 /* #<imm16> or relocation. */
6155 int internal_fixup_p
;
6156 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6157 if (internal_fixup_p
)
6158 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6159 skip_whitespace (str
);
6160 if (skip_past_comma (&str
))
6162 /* {, LSL #<shift>} */
6163 if (! aarch64_gas_internal_fixup_p ())
6165 set_fatal_syntax_error (_("can't mix relocation modifier "
6166 "with explicit shift"));
6169 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6172 inst
.base
.operands
[i
].shifter
.amount
= 0;
6173 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6174 inst
.base
.operands
[i
].imm
.value
= 0;
6175 if (! process_movw_reloc_info ())
6180 case AARCH64_OPND_EXCEPTION
:
6181 case AARCH64_OPND_UNDEFINED
:
6182 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6184 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6186 /* need_libopcodes_p */ 0,
6190 case AARCH64_OPND_NZCV
:
6192 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6196 info
->imm
.value
= nzcv
->value
;
6199 po_imm_or_fail (0, 15);
6200 info
->imm
.value
= val
;
6204 case AARCH64_OPND_COND
:
6205 case AARCH64_OPND_COND1
:
6210 while (ISALPHA (*str
));
6211 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6212 if (info
->cond
== NULL
)
6214 set_syntax_error (_("invalid condition"));
6217 else if (operands
[i
] == AARCH64_OPND_COND1
6218 && (info
->cond
->value
& 0xe) == 0xe)
6220 /* Do not allow AL or NV. */
6221 set_default_error ();
6227 case AARCH64_OPND_ADDR_ADRP
:
6228 po_misc_or_fail (parse_adrp (&str
));
6229 /* Clear the value as operand needs to be relocated. */
6230 info
->imm
.value
= 0;
6233 case AARCH64_OPND_ADDR_PCREL14
:
6234 case AARCH64_OPND_ADDR_PCREL19
:
6235 case AARCH64_OPND_ADDR_PCREL21
:
6236 case AARCH64_OPND_ADDR_PCREL26
:
6237 po_misc_or_fail (parse_address (&str
, info
));
6238 if (!info
->addr
.pcrel
)
6240 set_syntax_error (_("invalid pc-relative address"));
6243 if (inst
.gen_lit_pool
6244 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6246 /* Only permit "=value" in the literal load instructions.
6247 The literal will be generated by programmer_friendly_fixup. */
6248 set_syntax_error (_("invalid use of \"=immediate\""));
6251 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6253 set_syntax_error (_("unrecognized relocation suffix"));
6256 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6258 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6259 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6263 info
->imm
.value
= 0;
6264 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6265 switch (opcode
->iclass
)
6269 /* e.g. CBZ or B.COND */
6270 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6271 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6275 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6276 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6280 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6282 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6283 : BFD_RELOC_AARCH64_JUMP26
;
6286 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6287 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6290 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6291 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6297 inst
.reloc
.pc_rel
= 1;
6301 case AARCH64_OPND_ADDR_SIMPLE
:
6302 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6304 /* [<Xn|SP>{, #<simm>}] */
6306 /* First use the normal address-parsing routines, to get
6307 the usual syntax errors. */
6308 po_misc_or_fail (parse_address (&str
, info
));
6309 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6310 || !info
->addr
.preind
|| info
->addr
.postind
6311 || info
->addr
.writeback
)
6313 set_syntax_error (_("invalid addressing mode"));
6317 /* Then retry, matching the specific syntax of these addresses. */
6319 po_char_or_fail ('[');
6320 po_reg_or_fail (REG_TYPE_R64_SP
);
6321 /* Accept optional ", #0". */
6322 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6323 && skip_past_char (&str
, ','))
6325 skip_past_char (&str
, '#');
6326 if (! skip_past_char (&str
, '0'))
6328 set_fatal_syntax_error
6329 (_("the optional immediate offset can only be 0"));
6333 po_char_or_fail (']');
6337 case AARCH64_OPND_ADDR_REGOFF
:
6338 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6339 po_misc_or_fail (parse_address (&str
, info
));
6341 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6342 || !info
->addr
.preind
|| info
->addr
.postind
6343 || info
->addr
.writeback
)
6345 set_syntax_error (_("invalid addressing mode"));
6348 if (!info
->shifter
.operator_present
)
6350 /* Default to LSL if not present. Libopcodes prefers shifter
6351 kind to be explicit. */
6352 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6353 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6355 /* Qualifier to be deduced by libopcodes. */
6358 case AARCH64_OPND_ADDR_SIMM7
:
6359 po_misc_or_fail (parse_address (&str
, info
));
6360 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6361 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6363 set_syntax_error (_("invalid addressing mode"));
6366 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6368 set_syntax_error (_("relocation not allowed"));
6371 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6373 /* need_libopcodes_p */ 1,
6377 case AARCH64_OPND_ADDR_SIMM9
:
6378 case AARCH64_OPND_ADDR_SIMM9_2
:
6379 case AARCH64_OPND_ADDR_SIMM11
:
6380 case AARCH64_OPND_ADDR_SIMM13
:
6381 po_misc_or_fail (parse_address (&str
, info
));
6382 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6383 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6384 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6385 && info
->addr
.writeback
))
6387 set_syntax_error (_("invalid addressing mode"));
6390 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6392 set_syntax_error (_("relocation not allowed"));
6395 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6397 /* need_libopcodes_p */ 1,
6401 case AARCH64_OPND_ADDR_SIMM10
:
6402 case AARCH64_OPND_ADDR_OFFSET
:
6403 po_misc_or_fail (parse_address (&str
, info
));
6404 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6405 || !info
->addr
.preind
|| info
->addr
.postind
)
6407 set_syntax_error (_("invalid addressing mode"));
6410 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6412 set_syntax_error (_("relocation not allowed"));
6415 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6417 /* need_libopcodes_p */ 1,
6421 case AARCH64_OPND_ADDR_UIMM12
:
6422 po_misc_or_fail (parse_address (&str
, info
));
6423 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6424 || !info
->addr
.preind
|| info
->addr
.writeback
)
6426 set_syntax_error (_("invalid addressing mode"));
6429 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6430 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6431 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6433 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6435 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6437 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6439 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6440 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6441 /* Leave qualifier to be determined by libopcodes. */
6444 case AARCH64_OPND_SIMD_ADDR_POST
:
6445 /* [<Xn|SP>], <Xm|#<amount>> */
6446 po_misc_or_fail (parse_address (&str
, info
));
6447 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6449 set_syntax_error (_("invalid addressing mode"));
6452 if (!info
->addr
.offset
.is_reg
)
6454 if (inst
.reloc
.exp
.X_op
== O_constant
)
6455 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6458 set_fatal_syntax_error
6459 (_("writeback value must be an immediate constant"));
6466 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6467 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
6468 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6469 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6470 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6471 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6472 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6473 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6474 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6475 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6476 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6477 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6478 /* [X<n>{, #imm, MUL VL}]
6480 but recognizing SVE registers. */
6481 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6482 &offset_qualifier
));
6483 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6485 set_syntax_error (_("invalid addressing mode"));
6489 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6490 || !info
->addr
.preind
|| info
->addr
.writeback
)
6492 set_syntax_error (_("invalid addressing mode"));
6495 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6496 || inst
.reloc
.exp
.X_op
!= O_constant
)
6498 /* Make sure this has priority over
6499 "invalid addressing mode". */
6500 set_fatal_syntax_error (_("constant offset required"));
6503 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6506 case AARCH64_OPND_SVE_ADDR_R
:
6507 /* [<Xn|SP>{, <R><m>}]
6508 but recognizing SVE registers. */
6509 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6510 &offset_qualifier
));
6511 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6513 offset_qualifier
= AARCH64_OPND_QLF_X
;
6514 info
->addr
.offset
.is_reg
= 1;
6515 info
->addr
.offset
.regno
= 31;
6517 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6518 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6520 set_syntax_error (_("invalid addressing mode"));
6525 case AARCH64_OPND_SVE_ADDR_RR
:
6526 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6527 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6528 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6529 case AARCH64_OPND_SVE_ADDR_RX
:
6530 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6531 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6532 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6533 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6534 but recognizing SVE registers. */
6535 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6536 &offset_qualifier
));
6537 if (base_qualifier
!= AARCH64_OPND_QLF_X
6538 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6540 set_syntax_error (_("invalid addressing mode"));
6545 case AARCH64_OPND_SVE_ADDR_RZ
:
6546 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6547 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6548 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6549 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6550 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6551 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6552 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6553 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6554 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6555 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6556 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6557 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6558 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6559 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6560 &offset_qualifier
));
6561 if (base_qualifier
!= AARCH64_OPND_QLF_X
6562 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6563 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6565 set_syntax_error (_("invalid addressing mode"));
6568 info
->qualifier
= offset_qualifier
;
6571 case AARCH64_OPND_SVE_ADDR_ZX
:
6572 /* [Zn.<T>{, <Xm>}]. */
6573 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6574 &offset_qualifier
));
6576 base_qualifier either S_S or S_D
6577 offset_qualifier must be X
6579 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6580 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6581 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6583 set_syntax_error (_("invalid addressing mode"));
6586 info
->qualifier
= base_qualifier
;
6587 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6588 || !info
->addr
.preind
|| info
->addr
.writeback
6589 || info
->shifter
.operator_present
!= 0)
6591 set_syntax_error (_("invalid addressing mode"));
6594 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6598 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6599 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6600 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6601 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6602 /* [Z<n>.<T>{, #imm}] */
6603 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6604 &offset_qualifier
));
6605 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6606 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6608 set_syntax_error (_("invalid addressing mode"));
6611 info
->qualifier
= base_qualifier
;
6614 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6615 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6616 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6617 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6618 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6622 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6624 here since we get better error messages by leaving it to
6625 the qualifier checking routines. */
6626 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6627 &offset_qualifier
));
6628 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6629 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6630 || offset_qualifier
!= base_qualifier
)
6632 set_syntax_error (_("invalid addressing mode"));
6635 info
->qualifier
= base_qualifier
;
6638 case AARCH64_OPND_SYSREG
:
6640 uint32_t sysreg_flags
;
6641 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6642 &sysreg_flags
)) == PARSE_FAIL
)
6644 set_syntax_error (_("unknown or missing system register name"));
6647 inst
.base
.operands
[i
].sysreg
.value
= val
;
6648 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6652 case AARCH64_OPND_PSTATEFIELD
:
6653 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6656 set_syntax_error (_("unknown or missing PSTATE field name"));
6659 inst
.base
.operands
[i
].pstatefield
= val
;
6662 case AARCH64_OPND_SYSREG_IC
:
6663 inst
.base
.operands
[i
].sysins_op
=
6664 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6667 case AARCH64_OPND_SYSREG_DC
:
6668 inst
.base
.operands
[i
].sysins_op
=
6669 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6672 case AARCH64_OPND_SYSREG_AT
:
6673 inst
.base
.operands
[i
].sysins_op
=
6674 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6677 case AARCH64_OPND_SYSREG_SR
:
6678 inst
.base
.operands
[i
].sysins_op
=
6679 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6682 case AARCH64_OPND_SYSREG_TLBI
:
6683 inst
.base
.operands
[i
].sysins_op
=
6684 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6686 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6688 set_fatal_syntax_error ( _("unknown or missing operation name"));
6693 case AARCH64_OPND_BARRIER
:
6694 case AARCH64_OPND_BARRIER_ISB
:
6695 val
= parse_barrier (&str
);
6696 if (val
!= PARSE_FAIL
6697 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6699 /* ISB only accepts options name 'sy'. */
6701 (_("the specified option is not accepted in ISB"));
6702 /* Turn off backtrack as this optional operand is present. */
6706 if (val
!= PARSE_FAIL
6707 && operands
[i
] == AARCH64_OPND_BARRIER
)
6709 /* Regular barriers accept options CRm (C0-C15).
6710 DSB nXS barrier variant accepts values > 15. */
6711 if (val
< 0 || val
> 15)
6713 set_syntax_error (_("the specified option is not accepted in DSB"));
6717 /* This is an extension to accept a 0..15 immediate. */
6718 if (val
== PARSE_FAIL
)
6719 po_imm_or_fail (0, 15);
6720 info
->barrier
= aarch64_barrier_options
+ val
;
6723 case AARCH64_OPND_BARRIER_DSB_NXS
:
6724 val
= parse_barrier (&str
);
6725 if (val
!= PARSE_FAIL
)
6727 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
6728 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
6730 set_syntax_error (_("the specified option is not accepted in DSB"));
6731 /* Turn off backtrack as this optional operand is present. */
6738 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
6739 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
6740 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
6742 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
6744 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
6748 /* Option index is encoded as 2-bit value in val<3:2>. */
6749 val
= (val
>> 2) - 4;
6750 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
6753 case AARCH64_OPND_PRFOP
:
6754 val
= parse_pldop (&str
);
6755 /* This is an extension to accept a 0..31 immediate. */
6756 if (val
== PARSE_FAIL
)
6757 po_imm_or_fail (0, 31);
6758 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6761 case AARCH64_OPND_BARRIER_PSB
:
6762 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6763 if (val
== PARSE_FAIL
)
6767 case AARCH64_OPND_BTI_TARGET
:
6768 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6769 if (val
== PARSE_FAIL
)
6774 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6777 /* If we get here, this operand was successfully parsed. */
6778 inst
.base
.operands
[i
].present
= 1;
6782 /* The parse routine should already have set the error, but in case
6783 not, set a default one here. */
6785 set_default_error ();
6787 if (! backtrack_pos
)
6788 goto parse_operands_return
;
6791 /* We reach here because this operand is marked as optional, and
6792 either no operand was supplied or the operand was supplied but it
6793 was syntactically incorrect. In the latter case we report an
6794 error. In the former case we perform a few more checks before
6795 dropping through to the code to insert the default operand. */
6797 char *tmp
= backtrack_pos
;
6798 char endchar
= END_OF_INSN
;
6800 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6802 skip_past_char (&tmp
, ',');
6804 if (*tmp
!= endchar
)
6805 /* The user has supplied an operand in the wrong format. */
6806 goto parse_operands_return
;
6808 /* Make sure there is not a comma before the optional operand.
6809 For example the fifth operand of 'sys' is optional:
6811 sys #0,c0,c0,#0, <--- wrong
6812 sys #0,c0,c0,#0 <--- correct. */
6813 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6815 set_fatal_syntax_error
6816 (_("unexpected comma before the omitted optional operand"));
6817 goto parse_operands_return
;
6821 /* Reaching here means we are dealing with an optional operand that is
6822 omitted from the assembly line. */
6823 gas_assert (optional_operand_p (opcode
, i
));
6825 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6827 /* Try again, skipping the optional operand at backtrack_pos. */
6828 str
= backtrack_pos
;
6831 /* Clear any error record after the omitted optional operand has been
6832 successfully handled. */
6836 /* Check if we have parsed all the operands. */
6837 if (*str
!= '\0' && ! error_p ())
6839 /* Set I to the index of the last present operand; this is
6840 for the purpose of diagnostics. */
6841 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6843 set_fatal_syntax_error
6844 (_("unexpected characters following instruction"));
6847 parse_operands_return
:
6851 DEBUG_TRACE ("parsing FAIL: %s - %s",
6852 operand_mismatch_kind_names
[get_error_kind ()],
6853 get_error_message ());
6854 /* Record the operand error properly; this is useful when there
6855 are multiple instruction templates for a mnemonic name, so that
6856 later on, we can select the error that most closely describes
6858 record_operand_error (opcode
, i
, get_error_kind (),
6859 get_error_message ());
6864 DEBUG_TRACE ("parsing SUCCESS");
6869 /* It does some fix-up to provide some programmer friendly feature while
6870 keeping the libopcodes happy, i.e. libopcodes only accepts
6871 the preferred architectural syntax.
6872 Return FALSE if there is any failure; otherwise return TRUE. */
6875 programmer_friendly_fixup (aarch64_instruction
*instr
)
6877 aarch64_inst
*base
= &instr
->base
;
6878 const aarch64_opcode
*opcode
= base
->opcode
;
6879 enum aarch64_op op
= opcode
->op
;
6880 aarch64_opnd_info
*operands
= base
->operands
;
6882 DEBUG_TRACE ("enter");
6884 switch (opcode
->iclass
)
6887 /* TBNZ Xn|Wn, #uimm6, label
6888 Test and Branch Not Zero: conditionally jumps to label if bit number
6889 uimm6 in register Xn is not zero. The bit number implies the width of
6890 the register, which may be written and should be disassembled as Wn if
6891 uimm is less than 32. */
6892 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6894 if (operands
[1].imm
.value
>= 32)
6896 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6900 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6904 /* LDR Wt, label | =value
6905 As a convenience assemblers will typically permit the notation
6906 "=value" in conjunction with the pc-relative literal load instructions
6907 to automatically place an immediate value or symbolic address in a
6908 nearby literal pool and generate a hidden label which references it.
6909 ISREG has been set to 0 in the case of =value. */
6910 if (instr
->gen_lit_pool
6911 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6913 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6914 if (op
== OP_LDRSW_LIT
)
6916 if (instr
->reloc
.exp
.X_op
!= O_constant
6917 && instr
->reloc
.exp
.X_op
!= O_big
6918 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6920 record_operand_error (opcode
, 1,
6921 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6922 _("constant expression expected"));
6925 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6927 record_operand_error (opcode
, 1,
6928 AARCH64_OPDE_OTHER_ERROR
,
6929 _("literal pool insertion failed"));
6937 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6938 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6939 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6940 A programmer-friendly assembler should accept a destination Xd in
6941 place of Wd, however that is not the preferred form for disassembly.
6943 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6944 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6945 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6946 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6951 /* In the 64-bit form, the final register operand is written as Wm
6952 for all but the (possibly omitted) UXTX/LSL and SXTX
6954 As a programmer-friendly assembler, we accept e.g.
6955 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6956 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6957 int idx
= aarch64_operand_index (opcode
->operands
,
6958 AARCH64_OPND_Rm_EXT
);
6959 gas_assert (idx
== 1 || idx
== 2);
6960 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6961 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6962 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6963 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6964 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6965 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6973 DEBUG_TRACE ("exit with SUCCESS");
6977 /* Check for loads and stores that will cause unpredictable behavior. */
6980 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6982 aarch64_inst
*base
= &instr
->base
;
6983 const aarch64_opcode
*opcode
= base
->opcode
;
6984 const aarch64_opnd_info
*opnds
= base
->operands
;
6985 switch (opcode
->iclass
)
6992 /* Loading/storing the base register is unpredictable if writeback. */
6993 if ((aarch64_get_operand_class (opnds
[0].type
)
6994 == AARCH64_OPND_CLASS_INT_REG
)
6995 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6996 && opnds
[1].addr
.base_regno
!= REG_SP
6997 /* Exempt STG/STZG/ST2G/STZ2G. */
6998 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
6999 && opnds
[1].addr
.writeback
)
7000 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7004 case ldstnapair_offs
:
7005 case ldstpair_indexed
:
7006 /* Loading/storing the base register is unpredictable if writeback. */
7007 if ((aarch64_get_operand_class (opnds
[0].type
)
7008 == AARCH64_OPND_CLASS_INT_REG
)
7009 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7010 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7011 && opnds
[2].addr
.base_regno
!= REG_SP
7013 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7014 && opnds
[2].addr
.writeback
)
7015 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7016 /* Load operations must load different registers. */
7017 if ((opcode
->opcode
& (1 << 22))
7018 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7019 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7023 /* It is unpredictable if the destination and status registers are the
7025 if ((aarch64_get_operand_class (opnds
[0].type
)
7026 == AARCH64_OPND_CLASS_INT_REG
)
7027 && (aarch64_get_operand_class (opnds
[1].type
)
7028 == AARCH64_OPND_CLASS_INT_REG
)
7029 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
7030 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
7031 as_warn (_("unpredictable: identical transfer and status registers"
7043 force_automatic_sequence_close (void)
7045 if (now_instr_sequence
.instr
)
7047 as_warn (_("previous `%s' sequence has not been closed"),
7048 now_instr_sequence
.instr
->opcode
->name
);
7049 init_insn_sequence (NULL
, &now_instr_sequence
);
7053 /* A wrapper function to interface with libopcodes on encoding and
7054 record the error message if there is any.
7056 Return TRUE on success; otherwise return FALSE. */
7059 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7062 aarch64_operand_error error_info
;
7063 memset (&error_info
, '\0', sizeof (error_info
));
7064 error_info
.kind
= AARCH64_OPDE_NIL
;
7065 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7066 && !error_info
.non_fatal
)
7069 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7070 record_operand_error_info (opcode
, &error_info
);
7071 return error_info
.non_fatal
;
7074 #ifdef DEBUG_AARCH64
7076 dump_opcode_operands (const aarch64_opcode
*opcode
)
7079 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7081 aarch64_verbose ("\t\t opnd%d: %s", i
,
7082 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7083 ? aarch64_get_operand_name (opcode
->operands
[i
])
7084 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7088 #endif /* DEBUG_AARCH64 */
7090 /* This is the guts of the machine-dependent assembler. STR points to a
7091 machine dependent instruction. This function is supposed to emit
7092 the frags/bytes it assembles to. */
7095 md_assemble (char *str
)
7098 templates
*template;
7099 aarch64_opcode
*opcode
;
7100 aarch64_inst
*inst_base
;
7101 unsigned saved_cond
;
7103 /* Align the previous label if needed. */
7104 if (last_label_seen
!= NULL
)
7106 symbol_set_frag (last_label_seen
, frag_now
);
7107 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7108 S_SET_SEGMENT (last_label_seen
, now_seg
);
7111 /* Update the current insn_sequence from the segment. */
7112 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7114 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7116 DEBUG_TRACE ("\n\n");
7117 DEBUG_TRACE ("==============================");
7118 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7120 template = opcode_lookup (&p
);
7123 /* It wasn't an instruction, but it might be a register alias of
7124 the form alias .req reg directive. */
7125 if (!create_register_alias (str
, p
))
7126 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7131 skip_whitespace (p
);
7134 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7135 get_mnemonic_name (str
), str
);
7139 init_operand_error_report ();
7141 /* Sections are assumed to start aligned. In executable section, there is no
7142 MAP_DATA symbol pending. So we only align the address during
7143 MAP_DATA --> MAP_INSN transition.
7144 For other sections, this is not guaranteed. */
7145 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7146 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7147 frag_align_code (2, 0);
7149 saved_cond
= inst
.cond
;
7150 reset_aarch64_instruction (&inst
);
7151 inst
.cond
= saved_cond
;
7153 /* Iterate through all opcode entries with the same mnemonic name. */
7156 opcode
= template->opcode
;
7158 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7159 #ifdef DEBUG_AARCH64
7161 dump_opcode_operands (opcode
);
7162 #endif /* DEBUG_AARCH64 */
7164 mapping_state (MAP_INSN
);
7166 inst_base
= &inst
.base
;
7167 inst_base
->opcode
= opcode
;
7169 /* Truly conditionally executed instructions, e.g. b.cond. */
7170 if (opcode
->flags
& F_COND
)
7172 gas_assert (inst
.cond
!= COND_ALWAYS
);
7173 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7174 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7176 else if (inst
.cond
!= COND_ALWAYS
)
7178 /* It shouldn't arrive here, where the assembly looks like a
7179 conditional instruction but the found opcode is unconditional. */
7184 if (parse_operands (p
, opcode
)
7185 && programmer_friendly_fixup (&inst
)
7186 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7188 /* Check that this instruction is supported for this CPU. */
7189 if (!opcode
->avariant
7190 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7192 as_bad (_("selected processor does not support `%s'"), str
);
7196 warn_unpredictable_ldst (&inst
, str
);
7198 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7199 || !inst
.reloc
.need_libopcodes_p
)
7203 /* If there is relocation generated for the instruction,
7204 store the instruction information for the future fix-up. */
7205 struct aarch64_inst
*copy
;
7206 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7207 copy
= XNEW (struct aarch64_inst
);
7208 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7212 /* Issue non-fatal messages if any. */
7213 output_operand_error_report (str
, TRUE
);
7217 template = template->next
;
7218 if (template != NULL
)
7220 reset_aarch64_instruction (&inst
);
7221 inst
.cond
= saved_cond
;
7224 while (template != NULL
);
7226 /* Issue the error messages if any. */
7227 output_operand_error_report (str
, FALSE
);
7230 /* Various frobbings of labels and their addresses. */
7233 aarch64_start_line_hook (void)
7235 last_label_seen
= NULL
;
7239 aarch64_frob_label (symbolS
* sym
)
7241 last_label_seen
= sym
;
7243 dwarf2_emit_label (sym
);
7247 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7249 /* Check to see if we have a block to close. */
7250 force_automatic_sequence_close ();
7254 aarch64_data_in_code (void)
7256 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7258 *input_line_pointer
= '/';
7259 input_line_pointer
+= 5;
7260 *input_line_pointer
= 0;
7268 aarch64_canonicalize_symbol_name (char *name
)
7272 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7273 *(name
+ len
- 5) = 0;
7278 /* Table of all register names defined by default. The user can
7279 define additional names with .req. Note that all register names
7280 should appear in both upper and lowercase variants. Some registers
7281 also have mixed-case names. */
7283 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7284 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7285 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7286 #define REGSET16(p,t) \
7287 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7288 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7289 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7290 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7291 #define REGSET31(p,t) \
7293 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7294 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7295 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7296 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7297 #define REGSET(p,t) \
7298 REGSET31(p,t), REGNUM(p,31,t)
7300 /* These go into aarch64_reg_hsh hash-table. */
7301 static const reg_entry reg_names
[] = {
7302 /* Integer registers. */
7303 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7304 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7306 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7307 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7308 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7309 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7310 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7311 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7313 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7314 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7316 /* Floating-point single precision registers. */
7317 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7319 /* Floating-point double precision registers. */
7320 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7322 /* Floating-point half precision registers. */
7323 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7325 /* Floating-point byte precision registers. */
7326 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7328 /* Floating-point quad precision registers. */
7329 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7331 /* FP/SIMD registers. */
7332 REGSET (v
, VN
), REGSET (V
, VN
),
7334 /* SVE vector registers. */
7335 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7337 /* SVE predicate registers. */
7338 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7356 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7357 static const asm_nzcv nzcv_names
[] = {
7358 {"nzcv", B (n
, z
, c
, v
)},
7359 {"nzcV", B (n
, z
, c
, V
)},
7360 {"nzCv", B (n
, z
, C
, v
)},
7361 {"nzCV", B (n
, z
, C
, V
)},
7362 {"nZcv", B (n
, Z
, c
, v
)},
7363 {"nZcV", B (n
, Z
, c
, V
)},
7364 {"nZCv", B (n
, Z
, C
, v
)},
7365 {"nZCV", B (n
, Z
, C
, V
)},
7366 {"Nzcv", B (N
, z
, c
, v
)},
7367 {"NzcV", B (N
, z
, c
, V
)},
7368 {"NzCv", B (N
, z
, C
, v
)},
7369 {"NzCV", B (N
, z
, C
, V
)},
7370 {"NZcv", B (N
, Z
, c
, v
)},
7371 {"NZcV", B (N
, Z
, c
, V
)},
7372 {"NZCv", B (N
, Z
, C
, v
)},
7373 {"NZCV", B (N
, Z
, C
, V
)}
7386 /* MD interface: bits in the object file. */
7388 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7389 for use in the a.out file, and stores them in the array pointed to by buf.
7390 This knows about the endian-ness of the target machine and does
7391 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7392 2 (short) and 4 (long) Floating numbers are put out as a series of
7393 LITTLENUMS (shorts, here at least). */
7396 md_number_to_chars (char *buf
, valueT val
, int n
)
7398 if (target_big_endian
)
7399 number_to_chars_bigendian (buf
, val
, n
);
7401 number_to_chars_littleendian (buf
, val
, n
);
7404 /* MD interface: Sections. */
7406 /* Estimate the size of a frag before relaxing. Assume everything fits in
7410 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7416 /* Round up a section size to the appropriate boundary. */
7419 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7424 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7425 of an rs_align_code fragment.
7427 Here we fill the frag with the appropriate info for padding the
7428 output stream. The resulting frag will consist of a fixed (fr_fix)
7429 and of a repeating (fr_var) part.
7431 The fixed content is always emitted before the repeating content and
7432 these two parts are used as follows in constructing the output:
7433 - the fixed part will be used to align to a valid instruction word
7434 boundary, in case that we start at a misaligned address; as no
7435 executable instruction can live at the misaligned location, we
7436 simply fill with zeros;
7437 - the variable part will be used to cover the remaining padding and
7438 we fill using the AArch64 NOP instruction.
7440 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7441 enough storage space for up to 3 bytes for padding the back to a valid
7442 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7445 aarch64_handle_align (fragS
* fragP
)
7447 /* NOP = d503201f */
7448 /* AArch64 instructions are always little-endian. */
7449 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7451 int bytes
, fix
, noop_size
;
7454 if (fragP
->fr_type
!= rs_align_code
)
7457 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7458 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7461 gas_assert (fragP
->tc_frag_data
.recorded
);
7464 noop_size
= sizeof (aarch64_noop
);
7466 fix
= bytes
& (noop_size
- 1);
7470 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7474 fragP
->fr_fix
+= fix
;
7478 memcpy (p
, aarch64_noop
, noop_size
);
7479 fragP
->fr_var
= noop_size
;
7482 /* Perform target specific initialisation of a frag.
7483 Note - despite the name this initialisation is not done when the frag
7484 is created, but only when its type is assigned. A frag can be created
7485 and used a long time before its type is set, so beware of assuming that
7486 this initialisation is performed first. */
7490 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7491 int max_chars ATTRIBUTE_UNUSED
)
7495 #else /* OBJ_ELF is defined. */
7497 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7499 /* Record a mapping symbol for alignment frags. We will delete this
7500 later if the alignment ends up empty. */
7501 if (!fragP
->tc_frag_data
.recorded
)
7502 fragP
->tc_frag_data
.recorded
= 1;
7504 /* PR 21809: Do not set a mapping state for debug sections
7505 - it just confuses other tools. */
7506 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7509 switch (fragP
->fr_type
)
7513 mapping_state_2 (MAP_DATA
, max_chars
);
7516 /* PR 20364: We can get alignment frags in code sections,
7517 so do not just assume that we should use the MAP_DATA state. */
7518 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7521 mapping_state_2 (MAP_INSN
, max_chars
);
7528 /* Initialize the DWARF-2 unwind information for this procedure. */
7531 tc_aarch64_frame_initial_instructions (void)
7533 cfi_add_CFA_def_cfa (REG_SP
, 0);
7535 #endif /* OBJ_ELF */
7537 /* Convert REGNAME to a DWARF-2 register number. */
7540 tc_aarch64_regname_to_dw2regnum (char *regname
)
7542 const reg_entry
*reg
= parse_reg (®name
);
7548 case REG_TYPE_SP_32
:
7549 case REG_TYPE_SP_64
:
7559 return reg
->number
+ 64;
7567 /* Implement DWARF2_ADDR_SIZE. */
7570 aarch64_dwarf2_addr_size (void)
7572 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7576 return bfd_arch_bits_per_address (stdoutput
) / 8;
7579 /* MD interface: Symbol and relocation handling. */
7581 /* Return the address within the segment that a PC-relative fixup is
7582 relative to. For AArch64 PC-relative fixups applied to instructions
7583 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7586 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7588 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7590 /* If this is pc-relative and we are going to emit a relocation
7591 then we just want to put out any pipeline compensation that the linker
7592 will need. Otherwise we want to use the calculated base. */
7594 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7595 || aarch64_force_relocation (fixP
)))
7598 /* AArch64 should be consistent for all pc-relative relocations. */
7599 return base
+ AARCH64_PCREL_OFFSET
;
7602 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7603 Otherwise we have no need to default values of symbols. */
7606 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7609 if (name
[0] == '_' && name
[1] == 'G'
7610 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7614 if (symbol_find (name
))
7615 as_bad (_("GOT already in the symbol table"));
7617 GOT_symbol
= symbol_new (name
, undefined_section
,
7618 &zero_address_frag
, 0);
7628 /* Return non-zero if the indicated VALUE has overflowed the maximum
7629 range expressible by a unsigned number with the indicated number of
7633 unsigned_overflow (valueT value
, unsigned bits
)
7636 if (bits
>= sizeof (valueT
) * 8)
7638 lim
= (valueT
) 1 << bits
;
7639 return (value
>= lim
);
7643 /* Return non-zero if the indicated VALUE has overflowed the maximum
7644 range expressible by an signed number with the indicated number of
7648 signed_overflow (offsetT value
, unsigned bits
)
7651 if (bits
>= sizeof (offsetT
) * 8)
7653 lim
= (offsetT
) 1 << (bits
- 1);
7654 return (value
< -lim
|| value
>= lim
);
7657 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7658 unsigned immediate offset load/store instruction, try to encode it as
7659 an unscaled, 9-bit, signed immediate offset load/store instruction.
7660 Return TRUE if it is successful; otherwise return FALSE.
7662 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7663 in response to the standard LDR/STR mnemonics when the immediate offset is
7664 unambiguous, i.e. when it is negative or unaligned. */
7667 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7670 enum aarch64_op new_op
;
7671 const aarch64_opcode
*new_opcode
;
7673 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7675 switch (instr
->opcode
->op
)
7677 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7678 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7679 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7680 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7681 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7682 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7683 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7684 case OP_STR_POS
: new_op
= OP_STUR
; break;
7685 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7686 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7687 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7688 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7689 default: new_op
= OP_NIL
; break;
7692 if (new_op
== OP_NIL
)
7695 new_opcode
= aarch64_get_opcode (new_op
);
7696 gas_assert (new_opcode
!= NULL
);
7698 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7699 instr
->opcode
->op
, new_opcode
->op
);
7701 aarch64_replace_opcode (instr
, new_opcode
);
7703 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7704 qualifier matching may fail because the out-of-date qualifier will
7705 prevent the operand being updated with a new and correct qualifier. */
7706 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7707 AARCH64_OPND_ADDR_SIMM9
);
7708 gas_assert (idx
== 1);
7709 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7711 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7713 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7720 /* Called by fix_insn to fix a MOV immediate alias instruction.
7722 Operand for a generic move immediate instruction, which is an alias
7723 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7724 a 32-bit/64-bit immediate value into general register. An assembler error
7725 shall result if the immediate cannot be created by a single one of these
7726 instructions. If there is a choice, then to ensure reversability an
7727 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7730 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7732 const aarch64_opcode
*opcode
;
7734 /* Need to check if the destination is SP/ZR. The check has to be done
7735 before any aarch64_replace_opcode. */
7736 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7737 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7739 instr
->operands
[1].imm
.value
= value
;
7740 instr
->operands
[1].skip
= 0;
7744 /* Try the MOVZ alias. */
7745 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7746 aarch64_replace_opcode (instr
, opcode
);
7747 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7748 &instr
->value
, NULL
, NULL
, insn_sequence
))
7750 put_aarch64_insn (buf
, instr
->value
);
7753 /* Try the MOVK alias. */
7754 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7755 aarch64_replace_opcode (instr
, opcode
);
7756 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7757 &instr
->value
, NULL
, NULL
, insn_sequence
))
7759 put_aarch64_insn (buf
, instr
->value
);
7764 if (try_mov_bitmask_p
)
7766 /* Try the ORR alias. */
7767 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7768 aarch64_replace_opcode (instr
, opcode
);
7769 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7770 &instr
->value
, NULL
, NULL
, insn_sequence
))
7772 put_aarch64_insn (buf
, instr
->value
);
7777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7778 _("immediate cannot be moved by a single instruction"));
7781 /* An instruction operand which is immediate related may have symbol used
7782 in the assembly, e.g.
7785 .set u32, 0x00ffff00
7787 At the time when the assembly instruction is parsed, a referenced symbol,
7788 like 'u32' in the above example may not have been seen; a fixS is created
7789 in such a case and is handled here after symbols have been resolved.
7790 Instruction is fixed up with VALUE using the information in *FIXP plus
7791 extra information in FLAGS.
7793 This function is called by md_apply_fix to fix up instructions that need
7794 a fix-up described above but does not involve any linker-time relocation. */
7797 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7801 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7802 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7803 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7807 /* Now the instruction is about to be fixed-up, so the operand that
7808 was previously marked as 'ignored' needs to be unmarked in order
7809 to get the encoding done properly. */
7810 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7811 new_inst
->operands
[idx
].skip
= 0;
7814 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7818 case AARCH64_OPND_EXCEPTION
:
7819 case AARCH64_OPND_UNDEFINED
:
7820 if (unsigned_overflow (value
, 16))
7821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7822 _("immediate out of range"));
7823 insn
= get_aarch64_insn (buf
);
7824 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
7825 put_aarch64_insn (buf
, insn
);
7828 case AARCH64_OPND_AIMM
:
7829 /* ADD or SUB with immediate.
7830 NOTE this assumes we come here with a add/sub shifted reg encoding
7831 3 322|2222|2 2 2 21111 111111
7832 1 098|7654|3 2 1 09876 543210 98765 43210
7833 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7834 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7835 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7836 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7838 3 322|2222|2 2 221111111111
7839 1 098|7654|3 2 109876543210 98765 43210
7840 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7841 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7842 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7843 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7844 Fields sf Rn Rd are already set. */
7845 insn
= get_aarch64_insn (buf
);
7849 insn
= reencode_addsub_switch_add_sub (insn
);
7853 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7854 && unsigned_overflow (value
, 12))
7856 /* Try to shift the value by 12 to make it fit. */
7857 if (((value
>> 12) << 12) == value
7858 && ! unsigned_overflow (value
, 12 + 12))
7861 insn
|= encode_addsub_imm_shift_amount (1);
7865 if (unsigned_overflow (value
, 12))
7866 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7867 _("immediate out of range"));
7869 insn
|= encode_addsub_imm (value
);
7871 put_aarch64_insn (buf
, insn
);
7874 case AARCH64_OPND_SIMD_IMM
:
7875 case AARCH64_OPND_SIMD_IMM_SFT
:
7876 case AARCH64_OPND_LIMM
:
7877 /* Bit mask immediate. */
7878 gas_assert (new_inst
!= NULL
);
7879 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7880 new_inst
->operands
[idx
].imm
.value
= value
;
7881 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7882 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7883 put_aarch64_insn (buf
, new_inst
->value
);
7885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7886 _("invalid immediate"));
7889 case AARCH64_OPND_HALF
:
7890 /* 16-bit unsigned immediate. */
7891 if (unsigned_overflow (value
, 16))
7892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7893 _("immediate out of range"));
7894 insn
= get_aarch64_insn (buf
);
7895 insn
|= encode_movw_imm (value
& 0xffff);
7896 put_aarch64_insn (buf
, insn
);
7899 case AARCH64_OPND_IMM_MOV
:
7900 /* Operand for a generic move immediate instruction, which is
7901 an alias instruction that generates a single MOVZ, MOVN or ORR
7902 instruction to loads a 32-bit/64-bit immediate value into general
7903 register. An assembler error shall result if the immediate cannot be
7904 created by a single one of these instructions. If there is a choice,
7905 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7906 and MOVZ or MOVN to ORR. */
7907 gas_assert (new_inst
!= NULL
);
7908 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7911 case AARCH64_OPND_ADDR_SIMM7
:
7912 case AARCH64_OPND_ADDR_SIMM9
:
7913 case AARCH64_OPND_ADDR_SIMM9_2
:
7914 case AARCH64_OPND_ADDR_SIMM10
:
7915 case AARCH64_OPND_ADDR_UIMM12
:
7916 case AARCH64_OPND_ADDR_SIMM11
:
7917 case AARCH64_OPND_ADDR_SIMM13
:
7918 /* Immediate offset in an address. */
7919 insn
= get_aarch64_insn (buf
);
7921 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7922 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7923 || new_inst
->opcode
->operands
[2] == opnd
);
7925 /* Get the index of the address operand. */
7926 if (new_inst
->opcode
->operands
[1] == opnd
)
7927 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7930 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7933 /* Update the resolved offset value. */
7934 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7936 /* Encode/fix-up. */
7937 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7938 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7940 put_aarch64_insn (buf
, new_inst
->value
);
7943 else if (new_inst
->opcode
->iclass
== ldst_pos
7944 && try_to_encode_as_unscaled_ldst (new_inst
))
7946 put_aarch64_insn (buf
, new_inst
->value
);
7950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7951 _("immediate offset out of range"));
7956 as_fatal (_("unhandled operand code %d"), opnd
);
7960 /* Apply a fixup (fixP) to segment data, once it has been determined
7961 by our caller that we have all the info we need to fix it up.
7963 Parameter valP is the pointer to the value of the bits. */
7966 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7968 offsetT value
= *valP
;
7970 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7972 unsigned flags
= fixP
->fx_addnumber
;
7974 DEBUG_TRACE ("\n\n");
7975 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7976 DEBUG_TRACE ("Enter md_apply_fix");
7978 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7980 /* Note whether this will delete the relocation. */
7982 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7985 /* Process the relocations. */
7986 switch (fixP
->fx_r_type
)
7988 case BFD_RELOC_NONE
:
7989 /* This will need to go in the object file. */
7994 case BFD_RELOC_8_PCREL
:
7995 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7996 md_number_to_chars (buf
, value
, 1);
8000 case BFD_RELOC_16_PCREL
:
8001 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8002 md_number_to_chars (buf
, value
, 2);
8006 case BFD_RELOC_32_PCREL
:
8007 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8008 md_number_to_chars (buf
, value
, 4);
8012 case BFD_RELOC_64_PCREL
:
8013 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8014 md_number_to_chars (buf
, value
, 8);
8017 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8018 /* We claim that these fixups have been processed here, even if
8019 in fact we generate an error because we do not have a reloc
8020 for them, so tc_gen_reloc() will reject them. */
8022 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8025 _("undefined symbol %s used as an immediate value"),
8026 S_GET_NAME (fixP
->fx_addsy
));
8027 goto apply_fix_return
;
8029 fix_insn (fixP
, flags
, value
);
8032 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8033 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8037 _("pc-relative load offset not word aligned"));
8038 if (signed_overflow (value
, 21))
8039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8040 _("pc-relative load offset out of range"));
8041 insn
= get_aarch64_insn (buf
);
8042 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8043 put_aarch64_insn (buf
, insn
);
8047 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8048 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8050 if (signed_overflow (value
, 21))
8051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8052 _("pc-relative address offset out of range"));
8053 insn
= get_aarch64_insn (buf
);
8054 insn
|= encode_adr_imm (value
);
8055 put_aarch64_insn (buf
, insn
);
8059 case BFD_RELOC_AARCH64_BRANCH19
:
8060 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8064 _("conditional branch target not word aligned"));
8065 if (signed_overflow (value
, 21))
8066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8067 _("conditional branch out of range"));
8068 insn
= get_aarch64_insn (buf
);
8069 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8070 put_aarch64_insn (buf
, insn
);
8074 case BFD_RELOC_AARCH64_TSTBR14
:
8075 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8079 _("conditional branch target not word aligned"));
8080 if (signed_overflow (value
, 16))
8081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8082 _("conditional branch out of range"));
8083 insn
= get_aarch64_insn (buf
);
8084 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8085 put_aarch64_insn (buf
, insn
);
8089 case BFD_RELOC_AARCH64_CALL26
:
8090 case BFD_RELOC_AARCH64_JUMP26
:
8091 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8095 _("branch target not word aligned"));
8096 if (signed_overflow (value
, 28))
8097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8098 _("branch out of range"));
8099 insn
= get_aarch64_insn (buf
);
8100 insn
|= encode_branch_ofs_26 (value
>> 2);
8101 put_aarch64_insn (buf
, insn
);
8105 case BFD_RELOC_AARCH64_MOVW_G0
:
8106 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8107 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8108 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8109 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8110 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8113 case BFD_RELOC_AARCH64_MOVW_G1
:
8114 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8115 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8116 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8117 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8118 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8121 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8123 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8124 /* Should always be exported to object file, see
8125 aarch64_force_relocation(). */
8126 gas_assert (!fixP
->fx_done
);
8127 gas_assert (seg
->use_rela_p
);
8129 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8131 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8132 /* Should always be exported to object file, see
8133 aarch64_force_relocation(). */
8134 gas_assert (!fixP
->fx_done
);
8135 gas_assert (seg
->use_rela_p
);
8137 case BFD_RELOC_AARCH64_MOVW_G2
:
8138 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8139 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8140 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8141 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8144 case BFD_RELOC_AARCH64_MOVW_G3
:
8145 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8148 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8150 insn
= get_aarch64_insn (buf
);
8154 /* REL signed addend must fit in 16 bits */
8155 if (signed_overflow (value
, 16))
8156 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8157 _("offset out of range"));
8161 /* Check for overflow and scale. */
8162 switch (fixP
->fx_r_type
)
8164 case BFD_RELOC_AARCH64_MOVW_G0
:
8165 case BFD_RELOC_AARCH64_MOVW_G1
:
8166 case BFD_RELOC_AARCH64_MOVW_G2
:
8167 case BFD_RELOC_AARCH64_MOVW_G3
:
8168 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8169 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8170 if (unsigned_overflow (value
, scale
+ 16))
8171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8172 _("unsigned value out of range"));
8174 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8175 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8176 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8177 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8178 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8179 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8180 /* NOTE: We can only come here with movz or movn. */
8181 if (signed_overflow (value
, scale
+ 16))
8182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8183 _("signed value out of range"));
8186 /* Force use of MOVN. */
8188 insn
= reencode_movzn_to_movn (insn
);
8192 /* Force use of MOVZ. */
8193 insn
= reencode_movzn_to_movz (insn
);
8197 /* Unchecked relocations. */
8203 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8204 insn
|= encode_movw_imm (value
& 0xffff);
8206 put_aarch64_insn (buf
, insn
);
8210 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8211 fixP
->fx_r_type
= (ilp32_p
8212 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8213 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8214 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8215 /* Should always be exported to object file, see
8216 aarch64_force_relocation(). */
8217 gas_assert (!fixP
->fx_done
);
8218 gas_assert (seg
->use_rela_p
);
8221 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8222 fixP
->fx_r_type
= (ilp32_p
8223 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8224 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8225 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8226 /* Should always be exported to object file, see
8227 aarch64_force_relocation(). */
8228 gas_assert (!fixP
->fx_done
);
8229 gas_assert (seg
->use_rela_p
);
8232 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8233 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8234 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8235 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8236 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8237 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8238 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8239 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8240 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8241 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8242 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8243 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8244 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8245 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8246 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8247 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8248 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8249 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8250 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8251 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8252 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8253 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8254 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8255 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8256 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8257 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8258 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8259 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8260 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8261 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8262 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8263 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8264 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8265 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8266 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8267 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8268 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8269 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8270 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8271 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8272 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8273 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8274 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8275 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8276 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8277 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8278 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8279 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8280 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8281 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8282 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8283 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8284 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8285 /* Should always be exported to object file, see
8286 aarch64_force_relocation(). */
8287 gas_assert (!fixP
->fx_done
);
8288 gas_assert (seg
->use_rela_p
);
8291 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8292 /* Should always be exported to object file, see
8293 aarch64_force_relocation(). */
8294 fixP
->fx_r_type
= (ilp32_p
8295 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8296 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8297 gas_assert (!fixP
->fx_done
);
8298 gas_assert (seg
->use_rela_p
);
8301 case BFD_RELOC_AARCH64_ADD_LO12
:
8302 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8303 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8304 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8305 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8306 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8307 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8308 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8309 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8310 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8311 case BFD_RELOC_AARCH64_LDST128_LO12
:
8312 case BFD_RELOC_AARCH64_LDST16_LO12
:
8313 case BFD_RELOC_AARCH64_LDST32_LO12
:
8314 case BFD_RELOC_AARCH64_LDST64_LO12
:
8315 case BFD_RELOC_AARCH64_LDST8_LO12
:
8316 /* Should always be exported to object file, see
8317 aarch64_force_relocation(). */
8318 gas_assert (!fixP
->fx_done
);
8319 gas_assert (seg
->use_rela_p
);
8322 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8323 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8324 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8327 case BFD_RELOC_UNUSED
:
8328 /* An error will already have been reported. */
8332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8333 _("unexpected %s fixup"),
8334 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8339 /* Free the allocated the struct aarch64_inst.
8340 N.B. currently there are very limited number of fix-up types actually use
8341 this field, so the impact on the performance should be minimal . */
8342 free (fixP
->tc_fix_data
.inst
);
8347 /* Translate internal representation of relocation info to BFD target
8351 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8354 bfd_reloc_code_real_type code
;
8356 reloc
= XNEW (arelent
);
8358 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8359 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8360 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8364 if (section
->use_rela_p
)
8365 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8367 fixp
->fx_offset
= reloc
->address
;
8369 reloc
->addend
= fixp
->fx_offset
;
8371 code
= fixp
->fx_r_type
;
8376 code
= BFD_RELOC_16_PCREL
;
8381 code
= BFD_RELOC_32_PCREL
;
8386 code
= BFD_RELOC_64_PCREL
;
8393 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8394 if (reloc
->howto
== NULL
)
8396 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8398 ("cannot represent %s relocation in this object file format"),
8399 bfd_get_reloc_code_name (code
));
8406 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8409 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8411 bfd_reloc_code_real_type type
;
8415 FIXME: @@ Should look at CPU word size. */
8422 type
= BFD_RELOC_16
;
8425 type
= BFD_RELOC_32
;
8428 type
= BFD_RELOC_64
;
8431 as_bad (_("cannot do %u-byte relocation"), size
);
8432 type
= BFD_RELOC_UNUSED
;
8436 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8440 aarch64_force_relocation (struct fix
*fixp
)
8442 switch (fixp
->fx_r_type
)
8444 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8445 /* Perform these "immediate" internal relocations
8446 even if the symbol is extern or weak. */
8449 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8450 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8451 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8452 /* Pseudo relocs that need to be fixed up according to
8456 case BFD_RELOC_AARCH64_ADD_LO12
:
8457 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8458 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8459 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8460 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8461 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8462 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8463 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8464 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8465 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8466 case BFD_RELOC_AARCH64_LDST128_LO12
:
8467 case BFD_RELOC_AARCH64_LDST16_LO12
:
8468 case BFD_RELOC_AARCH64_LDST32_LO12
:
8469 case BFD_RELOC_AARCH64_LDST64_LO12
:
8470 case BFD_RELOC_AARCH64_LDST8_LO12
:
8471 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8472 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8473 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8474 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8475 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8476 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8477 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8478 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8479 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8480 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8481 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8482 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8483 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8484 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8485 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8486 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8487 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8488 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8489 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8490 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8491 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8492 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8493 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8494 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8495 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8496 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8497 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8498 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8499 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8500 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8501 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8502 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8503 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8504 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8505 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8506 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8507 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8508 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8509 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8510 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8511 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8512 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8513 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8514 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8515 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8516 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8517 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8518 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8519 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8520 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8521 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8522 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8523 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8524 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8525 /* Always leave these relocations for the linker. */
8532 return generic_force_reloc (fixp
);
8537 /* Implement md_after_parse_args. This is the earliest time we need to decide
8538 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8541 aarch64_after_parse_args (void)
8543 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8546 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8547 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8548 aarch64_abi
= AARCH64_ABI_ILP32
;
8550 aarch64_abi
= AARCH64_ABI_LP64
;
8554 elf64_aarch64_target_format (void)
8557 /* FIXME: What to do for ilp32_p ? */
8558 if (target_big_endian
)
8559 return "elf64-bigaarch64-cloudabi";
8561 return "elf64-littleaarch64-cloudabi";
8563 if (target_big_endian
)
8564 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8566 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8571 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8573 elf_frob_symbol (symp
, puntp
);
8577 /* MD interface: Finalization. */
8579 /* A good place to do this, although this was probably not intended
8580 for this kind of use. We need to dump the literal pool before
8581 references are made to a null symbol pointer. */
8584 aarch64_cleanup (void)
8588 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8590 /* Put it at the end of the relevant section. */
8591 subseg_set (pool
->section
, pool
->sub_section
);
8597 /* Remove any excess mapping symbols generated for alignment frags in
8598 SEC. We may have created a mapping symbol before a zero byte
8599 alignment; remove it if there's a mapping symbol after the
8602 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8603 void *dummy ATTRIBUTE_UNUSED
)
8605 segment_info_type
*seginfo
= seg_info (sec
);
8608 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8611 for (fragp
= seginfo
->frchainP
->frch_root
;
8612 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8614 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8615 fragS
*next
= fragp
->fr_next
;
8617 /* Variable-sized frags have been converted to fixed size by
8618 this point. But if this was variable-sized to start with,
8619 there will be a fixed-size frag after it. So don't handle
8621 if (sym
== NULL
|| next
== NULL
)
8624 if (S_GET_VALUE (sym
) < next
->fr_address
)
8625 /* Not at the end of this frag. */
8627 know (S_GET_VALUE (sym
) == next
->fr_address
);
8631 if (next
->tc_frag_data
.first_map
!= NULL
)
8633 /* Next frag starts with a mapping symbol. Discard this
8635 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8639 if (next
->fr_next
== NULL
)
8641 /* This mapping symbol is at the end of the section. Discard
8643 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8644 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8648 /* As long as we have empty frags without any mapping symbols,
8650 /* If the next frag is non-empty and does not start with a
8651 mapping symbol, then this mapping symbol is required. */
8652 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8655 next
= next
->fr_next
;
8657 while (next
!= NULL
);
8662 /* Adjust the symbol table. */
8665 aarch64_adjust_symtab (void)
8668 /* Remove any overlapping mapping symbols generated by alignment frags. */
8669 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8670 /* Now do generic ELF adjustments. */
8671 elf_adjust_symtab ();
8676 checked_hash_insert (htab_t table
, const char *key
, void *value
)
8678 str_hash_insert (table
, key
, value
, 0);
8682 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
8684 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
8685 checked_hash_insert (table
, key
, value
);
8689 fill_instruction_hash_table (void)
8691 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8693 while (opcode
->name
!= NULL
)
8695 templates
*templ
, *new_templ
;
8696 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
8698 new_templ
= XNEW (templates
);
8699 new_templ
->opcode
= opcode
;
8700 new_templ
->next
= NULL
;
8703 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8706 new_templ
->next
= templ
->next
;
8707 templ
->next
= new_templ
;
8714 convert_to_upper (char *dst
, const char *src
, size_t num
)
8717 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8718 *dst
= TOUPPER (*src
);
8722 /* Assume STR point to a lower-case string, allocate, convert and return
8723 the corresponding upper-case string. */
8724 static inline const char*
8725 get_upper_str (const char *str
)
8728 size_t len
= strlen (str
);
8729 ret
= XNEWVEC (char, len
+ 1);
8730 convert_to_upper (ret
, str
, len
);
8734 /* MD interface: Initialization. */
8742 aarch64_ops_hsh
= str_htab_create ();
8743 aarch64_cond_hsh
= str_htab_create ();
8744 aarch64_shift_hsh
= str_htab_create ();
8745 aarch64_sys_regs_hsh
= str_htab_create ();
8746 aarch64_pstatefield_hsh
= str_htab_create ();
8747 aarch64_sys_regs_ic_hsh
= str_htab_create ();
8748 aarch64_sys_regs_dc_hsh
= str_htab_create ();
8749 aarch64_sys_regs_at_hsh
= str_htab_create ();
8750 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
8751 aarch64_sys_regs_sr_hsh
= str_htab_create ();
8752 aarch64_reg_hsh
= str_htab_create ();
8753 aarch64_barrier_opt_hsh
= str_htab_create ();
8754 aarch64_nzcv_hsh
= str_htab_create ();
8755 aarch64_pldop_hsh
= str_htab_create ();
8756 aarch64_hint_opt_hsh
= str_htab_create ();
8758 fill_instruction_hash_table ();
8760 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8761 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8762 (void *) (aarch64_sys_regs
+ i
));
8764 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8765 sysreg_hash_insert (aarch64_pstatefield_hsh
,
8766 aarch64_pstatefields
[i
].name
,
8767 (void *) (aarch64_pstatefields
+ i
));
8769 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8770 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
8771 aarch64_sys_regs_ic
[i
].name
,
8772 (void *) (aarch64_sys_regs_ic
+ i
));
8774 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8775 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
8776 aarch64_sys_regs_dc
[i
].name
,
8777 (void *) (aarch64_sys_regs_dc
+ i
));
8779 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8780 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
8781 aarch64_sys_regs_at
[i
].name
,
8782 (void *) (aarch64_sys_regs_at
+ i
));
8784 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8785 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8786 aarch64_sys_regs_tlbi
[i
].name
,
8787 (void *) (aarch64_sys_regs_tlbi
+ i
));
8789 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8790 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
8791 aarch64_sys_regs_sr
[i
].name
,
8792 (void *) (aarch64_sys_regs_sr
+ i
));
8794 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8795 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8796 (void *) (reg_names
+ i
));
8798 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8799 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8800 (void *) (nzcv_names
+ i
));
8802 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8804 const char *name
= aarch64_operand_modifiers
[i
].name
;
8805 checked_hash_insert (aarch64_shift_hsh
, name
,
8806 (void *) (aarch64_operand_modifiers
+ i
));
8807 /* Also hash the name in the upper case. */
8808 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8809 (void *) (aarch64_operand_modifiers
+ i
));
8812 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8815 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8816 the same condition code. */
8817 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8819 const char *name
= aarch64_conds
[i
].names
[j
];
8822 checked_hash_insert (aarch64_cond_hsh
, name
,
8823 (void *) (aarch64_conds
+ i
));
8824 /* Also hash the name in the upper case. */
8825 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8826 (void *) (aarch64_conds
+ i
));
8830 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8832 const char *name
= aarch64_barrier_options
[i
].name
;
8833 /* Skip xx00 - the unallocated values of option. */
8836 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8837 (void *) (aarch64_barrier_options
+ i
));
8838 /* Also hash the name in the upper case. */
8839 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8840 (void *) (aarch64_barrier_options
+ i
));
8843 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
8845 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
8846 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8847 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
8848 /* Also hash the name in the upper case. */
8849 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8850 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
8853 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8855 const char* name
= aarch64_prfops
[i
].name
;
8856 /* Skip the unallocated hint encodings. */
8859 checked_hash_insert (aarch64_pldop_hsh
, name
,
8860 (void *) (aarch64_prfops
+ i
));
8861 /* Also hash the name in the upper case. */
8862 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8863 (void *) (aarch64_prfops
+ i
));
8866 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8868 const char* name
= aarch64_hint_options
[i
].name
;
8869 const char* upper_name
= get_upper_str(name
);
8871 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8872 (void *) (aarch64_hint_options
+ i
));
8874 /* Also hash the name in the upper case if not the same. */
8875 if (strcmp (name
, upper_name
) != 0)
8876 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
8877 (void *) (aarch64_hint_options
+ i
));
8880 /* Set the cpu variant based on the command-line options. */
8882 mcpu_cpu_opt
= march_cpu_opt
;
8885 mcpu_cpu_opt
= &cpu_default
;
8887 cpu_variant
= *mcpu_cpu_opt
;
8889 /* Record the CPU type. */
8890 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8892 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8895 /* Command line processing. */
8897 const char *md_shortopts
= "m:";
8899 #ifdef AARCH64_BI_ENDIAN
8900 #define OPTION_EB (OPTION_MD_BASE + 0)
8901 #define OPTION_EL (OPTION_MD_BASE + 1)
8903 #if TARGET_BYTES_BIG_ENDIAN
8904 #define OPTION_EB (OPTION_MD_BASE + 0)
8906 #define OPTION_EL (OPTION_MD_BASE + 1)
8910 struct option md_longopts
[] = {
8912 {"EB", no_argument
, NULL
, OPTION_EB
},
8915 {"EL", no_argument
, NULL
, OPTION_EL
},
8917 {NULL
, no_argument
, NULL
, 0}
8920 size_t md_longopts_size
= sizeof (md_longopts
);
8922 struct aarch64_option_table
8924 const char *option
; /* Option name to match. */
8925 const char *help
; /* Help information. */
8926 int *var
; /* Variable to change. */
8927 int value
; /* What to change it to. */
8928 char *deprecated
; /* If non-null, print this message. */
8931 static struct aarch64_option_table aarch64_opts
[] = {
8932 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8933 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8935 #ifdef DEBUG_AARCH64
8936 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8937 #endif /* DEBUG_AARCH64 */
8938 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8940 {"mno-verbose-error", N_("do not output verbose error messages"),
8941 &verbose_error_p
, 0, NULL
},
8942 {NULL
, NULL
, NULL
, 0, NULL
}
8945 struct aarch64_cpu_option_table
8948 const aarch64_feature_set value
;
8949 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8951 const char *canonical_name
;
8954 /* This list should, at a minimum, contain all the cpu names
8955 recognized by GCC. */
8956 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8957 {"all", AARCH64_ANY
, NULL
},
8958 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8959 AARCH64_FEATURE_CRC
), "Cortex-A34"},
8960 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8961 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8962 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8963 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8964 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8965 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8966 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8967 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8968 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8969 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8970 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8971 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8973 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8974 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8976 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8977 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8979 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8980 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8981 | AARCH64_FEATURE_DOTPROD
8982 | AARCH64_FEATURE_SSBS
),
8984 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8985 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8986 | AARCH64_FEATURE_DOTPROD
8987 | AARCH64_FEATURE_SSBS
),
8989 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8990 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8991 | AARCH64_FEATURE_DOTPROD
8992 | AARCH64_FEATURE_SSBS
),
8994 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8995 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8996 | AARCH64_FEATURE_DOTPROD
8997 | AARCH64_FEATURE_SSBS
),
8999 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9001 | AARCH64_FEATURE_RCPC
9002 | AARCH64_FEATURE_DOTPROD
9003 | AARCH64_FEATURE_SSBS
9004 | AARCH64_FEATURE_PROFILE
),
9006 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9008 | AARCH64_FEATURE_RCPC
9009 | AARCH64_FEATURE_DOTPROD
9010 | AARCH64_FEATURE_SSBS
9011 | AARCH64_FEATURE_PROFILE
),
9013 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9014 AARCH64_FEATURE_DOTPROD
9015 | AARCH64_FEATURE_F16
9016 | AARCH64_FEATURE_FLAGM
9017 | AARCH64_FEATURE_PAC
9018 | AARCH64_FEATURE_PROFILE
9019 | AARCH64_FEATURE_RCPC
9020 | AARCH64_FEATURE_SSBS
),
9022 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9023 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9024 | AARCH64_FEATURE_DOTPROD
9025 | AARCH64_FEATURE_PROFILE
),
9027 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9028 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9029 "Samsung Exynos M1"},
9030 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9031 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9032 | AARCH64_FEATURE_RDMA
),
9034 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9035 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9036 | AARCH64_FEATURE_DOTPROD
9037 | AARCH64_FEATURE_SSBS
),
9039 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9040 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9041 | AARCH64_FEATURE_DOTPROD
9042 | AARCH64_FEATURE_PROFILE
),
9044 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9045 AARCH64_FEATURE_BFLOAT16
9046 | AARCH64_FEATURE_I8MM
9047 | AARCH64_FEATURE_F16
9048 | AARCH64_FEATURE_SVE
9049 | AARCH64_FEATURE_SVE2
9050 | AARCH64_FEATURE_SVE2_BITPERM
9051 | AARCH64_FEATURE_MEMTAG
9052 | AARCH64_FEATURE_RNG
),
9054 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9055 AARCH64_FEATURE_PROFILE
9056 | AARCH64_FEATURE_CVADP
9057 | AARCH64_FEATURE_SVE
9058 | AARCH64_FEATURE_SSBS
9059 | AARCH64_FEATURE_RNG
9060 | AARCH64_FEATURE_F16
9061 | AARCH64_FEATURE_BFLOAT16
9062 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9063 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9064 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9065 | AARCH64_FEATURE_RDMA
),
9066 "Qualcomm QDF24XX"},
9067 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9068 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9069 "Qualcomm Saphira"},
9070 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9071 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9073 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9074 AARCH64_FEATURE_CRYPTO
),
9076 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9077 in earlier releases and is superseded by 'xgene1' in all
9079 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9080 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9081 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9082 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9083 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9084 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9086 | AARCH64_FEATURE_RCPC
9087 | AARCH64_FEATURE_DOTPROD
9088 | AARCH64_FEATURE_SSBS
9089 | AARCH64_FEATURE_PROFILE
),
9091 {"generic", AARCH64_ARCH_V8
, NULL
},
9093 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9096 struct aarch64_arch_option_table
9099 const aarch64_feature_set value
;
9102 /* This list should, at a minimum, contain all the architecture names
9103 recognized by GCC. */
9104 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9105 {"all", AARCH64_ANY
},
9106 {"armv8-a", AARCH64_ARCH_V8
},
9107 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9108 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9109 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9110 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9111 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9112 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9113 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9114 {"armv8-r", AARCH64_ARCH_V8_R
},
9115 {NULL
, AARCH64_ARCH_NONE
}
9118 /* ISA extensions. */
9119 struct aarch64_option_cpu_value_table
9122 const aarch64_feature_set value
;
9123 const aarch64_feature_set require
; /* Feature dependencies. */
9126 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9127 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9129 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9130 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9131 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9133 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9135 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9136 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9137 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9139 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9141 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9143 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9144 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9145 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9146 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9147 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9148 AARCH64_FEATURE (AARCH64_FEATURE_FP
9149 | AARCH64_FEATURE_F16
, 0)},
9150 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9152 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9153 AARCH64_FEATURE (AARCH64_FEATURE_F16
9154 | AARCH64_FEATURE_SIMD
9155 | AARCH64_FEATURE_COMPNUM
, 0)},
9156 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9158 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9159 AARCH64_FEATURE (AARCH64_FEATURE_F16
9160 | AARCH64_FEATURE_SIMD
, 0)},
9161 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9163 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9165 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9167 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9169 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9171 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9173 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9175 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9176 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9177 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9179 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9181 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9183 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9184 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9185 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9186 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9187 | AARCH64_FEATURE_SM4
, 0)},
9188 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9189 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9190 | AARCH64_FEATURE_AES
, 0)},
9191 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9192 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9193 | AARCH64_FEATURE_SHA3
, 0)},
9194 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9195 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9196 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9198 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9200 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9201 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9202 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9203 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9204 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
9206 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
9208 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
9210 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9213 struct aarch64_long_option_table
9215 const char *option
; /* Substring to match. */
9216 const char *help
; /* Help information. */
9217 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9218 char *deprecated
; /* If non-null, print this message. */
9221 /* Transitive closure of features depending on set. */
9222 static aarch64_feature_set
9223 aarch64_feature_disable_set (aarch64_feature_set set
)
9225 const struct aarch64_option_cpu_value_table
*opt
;
9226 aarch64_feature_set prev
= 0;
9228 while (prev
!= set
) {
9230 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9231 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9232 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9237 /* Transitive closure of dependencies of set. */
9238 static aarch64_feature_set
9239 aarch64_feature_enable_set (aarch64_feature_set set
)
9241 const struct aarch64_option_cpu_value_table
*opt
;
9242 aarch64_feature_set prev
= 0;
9244 while (prev
!= set
) {
9246 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9247 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9248 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9254 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9255 bfd_boolean ext_only
)
9257 /* We insist on extensions being added before being removed. We achieve
9258 this by using the ADDING_VALUE variable to indicate whether we are
9259 adding an extension (1) or removing it (0) and only allowing it to
9260 change in the order -1 -> 1 -> 0. */
9261 int adding_value
= -1;
9262 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9264 /* Copy the feature set, so that we can modify it. */
9268 while (str
!= NULL
&& *str
!= 0)
9270 const struct aarch64_option_cpu_value_table
*opt
;
9271 const char *ext
= NULL
;
9278 as_bad (_("invalid architectural extension"));
9282 ext
= strchr (++str
, '+');
9288 optlen
= strlen (str
);
9290 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9292 if (adding_value
!= 0)
9297 else if (optlen
> 0)
9299 if (adding_value
== -1)
9301 else if (adding_value
!= 1)
9303 as_bad (_("must specify extensions to add before specifying "
9304 "those to remove"));
9311 as_bad (_("missing architectural extension"));
9315 gas_assert (adding_value
!= -1);
9317 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9318 if (strncmp (opt
->name
, str
, optlen
) == 0)
9320 aarch64_feature_set set
;
9322 /* Add or remove the extension. */
9325 set
= aarch64_feature_enable_set (opt
->value
);
9326 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9330 set
= aarch64_feature_disable_set (opt
->value
);
9331 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9336 if (opt
->name
== NULL
)
9338 as_bad (_("unknown architectural extension `%s'"), str
);
9349 aarch64_parse_cpu (const char *str
)
9351 const struct aarch64_cpu_option_table
*opt
;
9352 const char *ext
= strchr (str
, '+');
9358 optlen
= strlen (str
);
9362 as_bad (_("missing cpu name `%s'"), str
);
9366 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9367 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9369 mcpu_cpu_opt
= &opt
->value
;
9371 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9376 as_bad (_("unknown cpu `%s'"), str
);
9381 aarch64_parse_arch (const char *str
)
9383 const struct aarch64_arch_option_table
*opt
;
9384 const char *ext
= strchr (str
, '+');
9390 optlen
= strlen (str
);
9394 as_bad (_("missing architecture name `%s'"), str
);
9398 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9399 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9401 march_cpu_opt
= &opt
->value
;
9403 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9408 as_bad (_("unknown architecture `%s'\n"), str
);
9413 struct aarch64_option_abi_value_table
9416 enum aarch64_abi_type value
;
9419 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9420 {"ilp32", AARCH64_ABI_ILP32
},
9421 {"lp64", AARCH64_ABI_LP64
},
9425 aarch64_parse_abi (const char *str
)
9431 as_bad (_("missing abi name `%s'"), str
);
9435 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9436 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9438 aarch64_abi
= aarch64_abis
[i
].value
;
9442 as_bad (_("unknown abi `%s'\n"), str
);
9446 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9448 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9449 aarch64_parse_abi
, NULL
},
9450 #endif /* OBJ_ELF */
9451 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9452 aarch64_parse_cpu
, NULL
},
9453 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9454 aarch64_parse_arch
, NULL
},
9455 {NULL
, NULL
, 0, NULL
}
9459 md_parse_option (int c
, const char *arg
)
9461 struct aarch64_option_table
*opt
;
9462 struct aarch64_long_option_table
*lopt
;
9468 target_big_endian
= 1;
9474 target_big_endian
= 0;
9479 /* Listing option. Just ignore these, we don't support additional
9484 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9486 if (c
== opt
->option
[0]
9487 && ((arg
== NULL
&& opt
->option
[1] == 0)
9488 || streq (arg
, opt
->option
+ 1)))
9490 /* If the option is deprecated, tell the user. */
9491 if (opt
->deprecated
!= NULL
)
9492 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9493 arg
? arg
: "", _(opt
->deprecated
));
9495 if (opt
->var
!= NULL
)
9496 *opt
->var
= opt
->value
;
9502 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9504 /* These options are expected to have an argument. */
9505 if (c
== lopt
->option
[0]
9507 && strncmp (arg
, lopt
->option
+ 1,
9508 strlen (lopt
->option
+ 1)) == 0)
9510 /* If the option is deprecated, tell the user. */
9511 if (lopt
->deprecated
!= NULL
)
9512 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9513 _(lopt
->deprecated
));
9515 /* Call the sup-option parser. */
9516 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9527 md_show_usage (FILE * fp
)
9529 struct aarch64_option_table
*opt
;
9530 struct aarch64_long_option_table
*lopt
;
9532 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9534 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9535 if (opt
->help
!= NULL
)
9536 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9538 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9539 if (lopt
->help
!= NULL
)
9540 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9544 -EB assemble code for a big-endian cpu\n"));
9549 -EL assemble code for a little-endian cpu\n"));
9553 /* Parse a .cpu directive. */
9556 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9558 const struct aarch64_cpu_option_table
*opt
;
9564 name
= input_line_pointer
;
9565 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9566 input_line_pointer
++;
9567 saved_char
= *input_line_pointer
;
9568 *input_line_pointer
= 0;
9570 ext
= strchr (name
, '+');
9573 optlen
= ext
- name
;
9575 optlen
= strlen (name
);
9577 /* Skip the first "all" entry. */
9578 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9579 if (strlen (opt
->name
) == optlen
9580 && strncmp (name
, opt
->name
, optlen
) == 0)
9582 mcpu_cpu_opt
= &opt
->value
;
9584 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9587 cpu_variant
= *mcpu_cpu_opt
;
9589 *input_line_pointer
= saved_char
;
9590 demand_empty_rest_of_line ();
9593 as_bad (_("unknown cpu `%s'"), name
);
9594 *input_line_pointer
= saved_char
;
9595 ignore_rest_of_line ();
9599 /* Parse a .arch directive. */
9602 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9604 const struct aarch64_arch_option_table
*opt
;
9610 name
= input_line_pointer
;
9611 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9612 input_line_pointer
++;
9613 saved_char
= *input_line_pointer
;
9614 *input_line_pointer
= 0;
9616 ext
= strchr (name
, '+');
9619 optlen
= ext
- name
;
9621 optlen
= strlen (name
);
9623 /* Skip the first "all" entry. */
9624 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9625 if (strlen (opt
->name
) == optlen
9626 && strncmp (name
, opt
->name
, optlen
) == 0)
9628 mcpu_cpu_opt
= &opt
->value
;
9630 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9633 cpu_variant
= *mcpu_cpu_opt
;
9635 *input_line_pointer
= saved_char
;
9636 demand_empty_rest_of_line ();
9640 as_bad (_("unknown architecture `%s'\n"), name
);
9641 *input_line_pointer
= saved_char
;
9642 ignore_rest_of_line ();
9645 /* Parse a .arch_extension directive. */
9648 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9651 char *ext
= input_line_pointer
;;
9653 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9654 input_line_pointer
++;
9655 saved_char
= *input_line_pointer
;
9656 *input_line_pointer
= 0;
9658 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9661 cpu_variant
= *mcpu_cpu_opt
;
9663 *input_line_pointer
= saved_char
;
9664 demand_empty_rest_of_line ();
9667 /* Copy symbol information. */
9670 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9672 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
9676 /* Same as elf_copy_symbol_attributes, but without copying st_other.
9677 This is needed so AArch64 specific st_other values can be independently
9678 specified for an IFUNC resolver (that is called by the dynamic linker)
9679 and the symbol it resolves (aliased to the resolver). In particular,
9680 if a function symbol has special st_other value set via directives,
9681 then attaching an IFUNC resolver to that symbol should not override
9682 the st_other setting. Requiring the directive on the IFUNC resolver
9683 symbol would be unexpected and problematic in C code, where the two
9684 symbols appear as two independent function declarations. */
9687 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
9689 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
9690 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
9693 if (destelf
->size
== NULL
)
9694 destelf
->size
= XNEW (expressionS
);
9695 *destelf
->size
= *srcelf
->size
;
9699 free (destelf
->size
);
9700 destelf
->size
= NULL
;
9702 S_SET_SIZE (dest
, S_GET_SIZE (src
));