1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
259 bfd_reloc_code_real_type reloc
;
262 /* Macros to define the register types and masks for the purpose
265 #undef AARCH64_REG_TYPES
266 #define AARCH64_REG_TYPES \
267 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
268 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
269 BASIC_REG_TYPE(SP_32) /* wsp */ \
270 BASIC_REG_TYPE(SP_64) /* sp */ \
271 BASIC_REG_TYPE(Z_32) /* wzr */ \
272 BASIC_REG_TYPE(Z_64) /* xzr */ \
273 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
274 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
275 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
276 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
277 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
278 BASIC_REG_TYPE(VN) /* v[0-31] */ \
279 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
280 BASIC_REG_TYPE(PN) /* p[0-15] */ \
281 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
282 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
283 /* Typecheck: same, plus SVE registers. */ \
284 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
286 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
287 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
293 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
294 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
296 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
297 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
298 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
299 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
300 /* Typecheck: any [BHSDQ]P FP. */ \
301 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
302 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
303 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
304 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
306 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
307 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
308 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
309 be used for SVE instructions, since Zn and Pn are valid symbols \
310 in other contexts. */ \
311 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
314 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
315 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
316 | REG_TYPE(ZN) | REG_TYPE(PN)) \
317 /* Any integer register; used for error messages only. */ \
318 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
320 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
321 /* Pseudo type to mark the end of the enumerator sequence. */ \
324 #undef BASIC_REG_TYPE
325 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
326 #undef MULTI_REG_TYPE
327 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
329 /* Register type enumerators. */
330 typedef enum aarch64_reg_type_
332 /* A list of REG_TYPE_*. */
336 #undef BASIC_REG_TYPE
337 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
339 #define REG_TYPE(T) (1 << REG_TYPE_##T)
340 #undef MULTI_REG_TYPE
341 #define MULTI_REG_TYPE(T,V) V,
343 /* Structure for a hash table entry for a register. */
347 unsigned char number
;
348 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
349 unsigned char builtin
;
352 /* Values indexed by aarch64_reg_type to assist the type checking. */
353 static const unsigned reg_type_masks
[] =
358 #undef BASIC_REG_TYPE
360 #undef MULTI_REG_TYPE
361 #undef AARCH64_REG_TYPES
363 /* Diagnostics used when we don't get a register of the expected type.
364 Note: this has to synchronized with aarch64_reg_type definitions
367 get_reg_expected_msg (aarch64_reg_type reg_type
)
374 msg
= N_("integer 32-bit register expected");
377 msg
= N_("integer 64-bit register expected");
380 msg
= N_("integer register expected");
382 case REG_TYPE_R64_SP
:
383 msg
= N_("64-bit integer or SP register expected");
385 case REG_TYPE_SVE_BASE
:
386 msg
= N_("base register expected");
389 msg
= N_("integer or zero register expected");
391 case REG_TYPE_SVE_OFFSET
:
392 msg
= N_("offset register expected");
395 msg
= N_("integer or SP register expected");
397 case REG_TYPE_R_Z_SP
:
398 msg
= N_("integer, zero or SP register expected");
401 msg
= N_("8-bit SIMD scalar register expected");
404 msg
= N_("16-bit SIMD scalar or floating-point half precision "
405 "register expected");
408 msg
= N_("32-bit SIMD scalar or floating-point single precision "
409 "register expected");
412 msg
= N_("64-bit SIMD scalar or floating-point double precision "
413 "register expected");
416 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
417 "register expected");
419 case REG_TYPE_R_Z_BHSDQ_V
:
420 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
421 msg
= N_("register expected");
423 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
424 msg
= N_("SIMD scalar or floating-point register expected");
426 case REG_TYPE_VN
: /* any V reg */
427 msg
= N_("vector register expected");
430 msg
= N_("SVE vector register expected");
433 msg
= N_("SVE predicate register expected");
436 as_fatal (_("invalid register type %d"), reg_type
);
441 /* Some well known registers that we refer to directly elsewhere. */
445 /* Instructions take 4 bytes in the object file. */
448 static htab_t aarch64_ops_hsh
;
449 static htab_t aarch64_cond_hsh
;
450 static htab_t aarch64_shift_hsh
;
451 static htab_t aarch64_sys_regs_hsh
;
452 static htab_t aarch64_pstatefield_hsh
;
453 static htab_t aarch64_sys_regs_ic_hsh
;
454 static htab_t aarch64_sys_regs_dc_hsh
;
455 static htab_t aarch64_sys_regs_at_hsh
;
456 static htab_t aarch64_sys_regs_tlbi_hsh
;
457 static htab_t aarch64_sys_regs_sr_hsh
;
458 static htab_t aarch64_reg_hsh
;
459 static htab_t aarch64_barrier_opt_hsh
;
460 static htab_t aarch64_nzcv_hsh
;
461 static htab_t aarch64_pldop_hsh
;
462 static htab_t aarch64_hint_opt_hsh
;
464 /* Stuff needed to resolve the label ambiguity
473 static symbolS
*last_label_seen
;
475 /* Literal pool structure. Held on a per-section
476 and per-sub-section basis. */
478 #define MAX_LITERAL_POOL_SIZE 1024
479 typedef struct literal_expression
482 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
483 LITTLENUM_TYPE
* bignum
;
484 } literal_expression
;
486 typedef struct literal_pool
488 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
489 unsigned int next_free_entry
;
495 struct literal_pool
*next
;
498 /* Pointer to a linked list of literal pools. */
499 static literal_pool
*list_of_pools
= NULL
;
503 /* This array holds the chars that always start a comment. If the
504 pre-processor is disabled, these aren't very useful. */
505 const char comment_chars
[] = "";
507 /* This array holds the chars that only start a comment at the beginning of
508 a line. If the line seems to have the form '# 123 filename'
509 .line and .file directives will appear in the pre-processed output. */
510 /* Note that input_file.c hand checks for '#' at the beginning of the
511 first line of the input file. This is because the compiler outputs
512 #NO_APP at the beginning of its output. */
513 /* Also note that comments like this one will always work. */
514 const char line_comment_chars
[] = "#";
516 const char line_separator_chars
[] = ";";
518 /* Chars that can be used to separate mant
519 from exp in floating point numbers. */
520 const char EXP_CHARS
[] = "eE";
522 /* Chars that mean this number is a floating point constant. */
526 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
528 /* Prefix character that indicates the start of an immediate value. */
529 #define is_immediate_prefix(C) ((C) == '#')
531 /* Separator character handling. */
533 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
535 static inline bfd_boolean
536 skip_past_char (char **str
, char c
)
547 #define skip_past_comma(str) skip_past_char (str, ',')
549 /* Arithmetic expressions (possibly involving symbols). */
551 static bfd_boolean in_my_get_expression_p
= FALSE
;
553 /* Third argument to my_get_expression. */
554 #define GE_NO_PREFIX 0
555 #define GE_OPT_PREFIX 1
557 /* Return TRUE if the string pointed by *STR is successfully parsed
558 as an valid expression; *EP will be filled with the information of
559 such an expression. Otherwise return FALSE. */
562 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
567 int prefix_present_p
= 0;
574 if (is_immediate_prefix (**str
))
577 prefix_present_p
= 1;
584 memset (ep
, 0, sizeof (expressionS
));
586 save_in
= input_line_pointer
;
587 input_line_pointer
= *str
;
588 in_my_get_expression_p
= TRUE
;
589 seg
= expression (ep
);
590 in_my_get_expression_p
= FALSE
;
592 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
594 /* We found a bad expression in md_operand(). */
595 *str
= input_line_pointer
;
596 input_line_pointer
= save_in
;
597 if (prefix_present_p
&& ! error_p ())
598 set_fatal_syntax_error (_("bad expression"));
600 set_first_syntax_error (_("bad expression"));
605 if (seg
!= absolute_section
606 && seg
!= text_section
607 && seg
!= data_section
608 && seg
!= bss_section
&& seg
!= undefined_section
)
610 set_syntax_error (_("bad segment"));
611 *str
= input_line_pointer
;
612 input_line_pointer
= save_in
;
619 *str
= input_line_pointer
;
620 input_line_pointer
= save_in
;
624 /* Turn a string in input_line_pointer into a floating point constant
625 of type TYPE, and store the appropriate bytes in *LITP. The number
626 of LITTLENUMS emitted is stored in *SIZEP. An error message is
627 returned, or NULL on OK. */
630 md_atof (int type
, char *litP
, int *sizeP
)
632 /* If this is a bfloat16 type, then parse it slightly differently -
633 as it does not follow the IEEE standard exactly. */
637 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
638 FLONUM_TYPE generic_float
;
640 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
643 input_line_pointer
= t
;
645 return _("invalid floating point number");
647 switch (generic_float
.sign
)
660 /* bfloat16 has two types of NaN - quiet and signalling.
661 Quiet NaN has bit[6] == 1 && faction != 0, whereas
662 signalling Nan's have bit[0] == 0 && fraction != 0.
663 Chose this specific encoding as it is the same form
664 as used by other IEEE 754 encodings in GAS. */
675 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
680 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
683 /* We handle all bad expressions here, so that we can report the faulty
684 instruction in the error message. */
686 md_operand (expressionS
* exp
)
688 if (in_my_get_expression_p
)
689 exp
->X_op
= O_illegal
;
692 /* Immediate values. */
694 /* Errors may be set multiple times during parsing or bit encoding
695 (particularly in the Neon bits), but usually the earliest error which is set
696 will be the most meaningful. Avoid overwriting it with later (cascading)
697 errors by calling this function. */
700 first_error (const char *error
)
703 set_syntax_error (error
);
706 /* Similar to first_error, but this function accepts formatted error
709 first_error_fmt (const char *format
, ...)
714 /* N.B. this single buffer will not cause error messages for different
715 instructions to pollute each other; this is because at the end of
716 processing of each assembly line, error message if any will be
717 collected by as_bad. */
718 static char buffer
[size
];
722 int ret ATTRIBUTE_UNUSED
;
723 va_start (args
, format
);
724 ret
= vsnprintf (buffer
, size
, format
, args
);
725 know (ret
<= size
- 1 && ret
>= 0);
727 set_syntax_error (buffer
);
731 /* Register parsing. */
733 /* Generic register parser which is called by other specialized
735 CCP points to what should be the beginning of a register name.
736 If it is indeed a valid register name, advance CCP over it and
737 return the reg_entry structure; otherwise return NULL.
738 It does not issue diagnostics. */
741 parse_reg (char **ccp
)
747 #ifdef REGISTER_PREFIX
748 if (*start
!= REGISTER_PREFIX
)
754 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
759 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
761 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
770 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
773 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
775 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
778 /* Try to parse a base or offset register. Allow SVE base and offset
779 registers if REG_TYPE includes SVE registers. Return the register
780 entry on success, setting *QUALIFIER to the register qualifier.
781 Return null otherwise.
783 Note that this function does not issue any diagnostics. */
785 static const reg_entry
*
786 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
787 aarch64_opnd_qualifier_t
*qualifier
)
790 const reg_entry
*reg
= parse_reg (&str
);
800 *qualifier
= AARCH64_OPND_QLF_W
;
806 *qualifier
= AARCH64_OPND_QLF_X
;
810 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
813 switch (TOLOWER (str
[1]))
816 *qualifier
= AARCH64_OPND_QLF_S_S
;
819 *qualifier
= AARCH64_OPND_QLF_S_D
;
836 /* Try to parse a base or offset register. Return the register entry
837 on success, setting *QUALIFIER to the register qualifier. Return null
840 Note that this function does not issue any diagnostics. */
842 static const reg_entry
*
843 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
845 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
848 /* Parse the qualifier of a vector register or vector element of type
849 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
850 succeeds; otherwise return FALSE.
852 Accept only one occurrence of:
853 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
856 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
857 struct vector_type_el
*parsed_type
, char **str
)
861 unsigned element_size
;
862 enum vector_el_type type
;
865 gas_assert (*ptr
== '.');
868 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
873 width
= strtoul (ptr
, &ptr
, 10);
874 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
876 first_error_fmt (_("bad size %d in vector width specifier"), width
);
881 switch (TOLOWER (*ptr
))
900 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
909 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
911 first_error (_("missing element size"));
914 if (width
!= 0 && width
* element_size
!= 64
915 && width
* element_size
!= 128
916 && !(width
== 2 && element_size
== 16)
917 && !(width
== 4 && element_size
== 8))
920 ("invalid element size %d and vector size combination %c"),
926 parsed_type
->type
= type
;
927 parsed_type
->width
= width
;
934 /* *STR contains an SVE zero/merge predication suffix. Parse it into
935 *PARSED_TYPE and point *STR at the end of the suffix. */
938 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
943 gas_assert (*ptr
== '/');
945 switch (TOLOWER (*ptr
))
948 parsed_type
->type
= NT_zero
;
951 parsed_type
->type
= NT_merge
;
954 if (*ptr
!= '\0' && *ptr
!= ',')
955 first_error_fmt (_("unexpected character `%c' in predication type"),
958 first_error (_("missing predication type"));
961 parsed_type
->width
= 0;
966 /* Parse a register of the type TYPE.
968 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
969 name or the parsed register is not of TYPE.
971 Otherwise return the register number, and optionally fill in the actual
972 type of the register in *RTYPE when multiple alternatives were given, and
973 return the register shape and element index information in *TYPEINFO.
975 IN_REG_LIST should be set with TRUE if the caller is parsing a register
979 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
980 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
983 const reg_entry
*reg
= parse_reg (&str
);
984 struct vector_type_el atype
;
985 struct vector_type_el parsetype
;
986 bfd_boolean is_typed_vecreg
= FALSE
;
989 atype
.type
= NT_invtype
;
997 set_default_error ();
1001 if (! aarch64_check_reg_type (reg
, type
))
1003 DEBUG_TRACE ("reg type check failed");
1004 set_default_error ();
1009 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1010 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
1014 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1019 if (!parse_predication_for_operand (&parsetype
, &str
))
1023 /* Register if of the form Vn.[bhsdq]. */
1024 is_typed_vecreg
= TRUE
;
1026 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1028 /* The width is always variable; we don't allow an integer width
1030 gas_assert (parsetype
.width
== 0);
1031 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1033 else if (parsetype
.width
== 0)
1034 /* Expect index. In the new scheme we cannot have
1035 Vn.[bhsdq] represent a scalar. Therefore any
1036 Vn.[bhsdq] should have an index following it.
1037 Except in reglists of course. */
1038 atype
.defined
|= NTA_HASINDEX
;
1040 atype
.defined
|= NTA_HASTYPE
;
1042 atype
.type
= parsetype
.type
;
1043 atype
.width
= parsetype
.width
;
1046 if (skip_past_char (&str
, '['))
1050 /* Reject Sn[index] syntax. */
1051 if (!is_typed_vecreg
)
1053 first_error (_("this type of register can't be indexed"));
1059 first_error (_("index not allowed inside register list"));
1063 atype
.defined
|= NTA_HASINDEX
;
1065 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1067 if (exp
.X_op
!= O_constant
)
1069 first_error (_("constant expression required"));
1073 if (! skip_past_char (&str
, ']'))
1076 atype
.index
= exp
.X_add_number
;
1078 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1080 /* Indexed vector register expected. */
1081 first_error (_("indexed vector register expected"));
1085 /* A vector reg Vn should be typed or indexed. */
1086 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1088 first_error (_("invalid use of vector register"));
1104 Return the register number on success; return PARSE_FAIL otherwise.
1106 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1107 the register (e.g. NEON double or quad reg when either has been requested).
1109 If this is a NEON vector register with additional type information, fill
1110 in the struct pointed to by VECTYPE (if non-NULL).
1112 This parser does not handle register list. */
1115 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1116 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1118 struct vector_type_el atype
;
1120 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1121 /*in_reg_list= */ FALSE
);
1123 if (reg
== PARSE_FAIL
)
1134 static inline bfd_boolean
1135 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1139 && e1
.defined
== e2
.defined
1140 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1143 /* This function parses a list of vector registers of type TYPE.
1144 On success, it returns the parsed register list information in the
1145 following encoded format:
1147 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1148 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1150 The information of the register shape and/or index is returned in
1153 It returns PARSE_FAIL if the register list is invalid.
1155 The list contains one to four registers.
1156 Each register can be one of:
1159 All <T> should be identical.
1160 All <index> should be identical.
1161 There are restrictions on <Vt> numbers which are checked later
1162 (by reg_list_valid_p). */
1165 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1166 struct vector_type_el
*vectype
)
1170 struct vector_type_el typeinfo
, typeinfo_first
;
1175 bfd_boolean error
= FALSE
;
1176 bfd_boolean expect_index
= FALSE
;
1180 set_syntax_error (_("expecting {"));
1186 typeinfo_first
.defined
= 0;
1187 typeinfo_first
.type
= NT_invtype
;
1188 typeinfo_first
.width
= -1;
1189 typeinfo_first
.index
= 0;
1198 str
++; /* skip over '-' */
1201 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1202 /*in_reg_list= */ TRUE
);
1203 if (val
== PARSE_FAIL
)
1205 set_first_syntax_error (_("invalid vector register in list"));
1209 /* reject [bhsd]n */
1210 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1212 set_first_syntax_error (_("invalid scalar register in list"));
1217 if (typeinfo
.defined
& NTA_HASINDEX
)
1218 expect_index
= TRUE
;
1222 if (val
< val_range
)
1224 set_first_syntax_error
1225 (_("invalid range in vector register list"));
1234 typeinfo_first
= typeinfo
;
1235 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1237 set_first_syntax_error
1238 (_("type mismatch in vector register list"));
1243 for (i
= val_range
; i
<= val
; i
++)
1245 ret_val
|= i
<< (5 * nb_regs
);
1250 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1252 skip_whitespace (str
);
1255 set_first_syntax_error (_("end of vector register list not found"));
1260 skip_whitespace (str
);
1264 if (skip_past_char (&str
, '['))
1268 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1269 if (exp
.X_op
!= O_constant
)
1271 set_first_syntax_error (_("constant expression required."));
1274 if (! skip_past_char (&str
, ']'))
1277 typeinfo_first
.index
= exp
.X_add_number
;
1281 set_first_syntax_error (_("expected index"));
1288 set_first_syntax_error (_("too many registers in vector register list"));
1291 else if (nb_regs
== 0)
1293 set_first_syntax_error (_("empty vector register list"));
1299 *vectype
= typeinfo_first
;
1301 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1304 /* Directives: register aliases. */
1307 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1312 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1315 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1318 /* Only warn about a redefinition if it's not defined as the
1320 else if (new->number
!= number
|| new->type
!= type
)
1321 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1326 name
= xstrdup (str
);
1327 new = XNEW (reg_entry
);
1330 new->number
= number
;
1332 new->builtin
= FALSE
;
1334 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1339 /* Look for the .req directive. This is of the form:
1341 new_register_name .req existing_register_name
1343 If we find one, or if it looks sufficiently like one that we want to
1344 handle any error here, return TRUE. Otherwise return FALSE. */
1347 create_register_alias (char *newname
, char *p
)
1349 const reg_entry
*old
;
1350 char *oldname
, *nbuf
;
1353 /* The input scrubber ensures that whitespace after the mnemonic is
1354 collapsed to single spaces. */
1356 if (strncmp (oldname
, " .req ", 6) != 0)
1360 if (*oldname
== '\0')
1363 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1366 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1370 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1371 the desired alias name, and p points to its end. If not, then
1372 the desired alias name is in the global original_case_string. */
1373 #ifdef TC_CASE_SENSITIVE
1376 newname
= original_case_string
;
1377 nlen
= strlen (newname
);
1380 nbuf
= xmemdup0 (newname
, nlen
);
1382 /* Create aliases under the new name as stated; an all-lowercase
1383 version of the new name; and an all-uppercase version of the new
1385 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1387 for (p
= nbuf
; *p
; p
++)
1390 if (strncmp (nbuf
, newname
, nlen
))
1392 /* If this attempt to create an additional alias fails, do not bother
1393 trying to create the all-lower case alias. We will fail and issue
1394 a second, duplicate error message. This situation arises when the
1395 programmer does something like:
1398 The second .req creates the "Foo" alias but then fails to create
1399 the artificial FOO alias because it has already been created by the
1401 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1408 for (p
= nbuf
; *p
; p
++)
1411 if (strncmp (nbuf
, newname
, nlen
))
1412 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1419 /* Should never be called, as .req goes between the alias and the
1420 register name, not at the beginning of the line. */
1422 s_req (int a ATTRIBUTE_UNUSED
)
1424 as_bad (_("invalid syntax for .req directive"));
1427 /* The .unreq directive deletes an alias which was previously defined
1428 by .req. For example:
1434 s_unreq (int a ATTRIBUTE_UNUSED
)
1439 name
= input_line_pointer
;
1441 while (*input_line_pointer
!= 0
1442 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1443 ++input_line_pointer
;
1445 saved_char
= *input_line_pointer
;
1446 *input_line_pointer
= 0;
1449 as_bad (_("invalid syntax for .unreq directive"));
1452 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1455 as_bad (_("unknown register alias '%s'"), name
);
1456 else if (reg
->builtin
)
1457 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1464 str_hash_delete (aarch64_reg_hsh
, name
);
1465 free ((char *) reg
->name
);
1468 /* Also locate the all upper case and all lower case versions.
1469 Do not complain if we cannot find one or the other as it
1470 was probably deleted above. */
1472 nbuf
= strdup (name
);
1473 for (p
= nbuf
; *p
; p
++)
1475 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1478 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1479 free ((char *) reg
->name
);
1483 for (p
= nbuf
; *p
; p
++)
1485 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1488 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1489 free ((char *) reg
->name
);
1497 *input_line_pointer
= saved_char
;
1498 demand_empty_rest_of_line ();
1501 /* Directives: Instruction set selection. */
1504 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1505 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1506 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1507 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1509 /* Create a new mapping symbol for the transition to STATE. */
1512 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1515 const char *symname
;
1522 type
= BSF_NO_FLAGS
;
1526 type
= BSF_NO_FLAGS
;
1532 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1533 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1535 /* Save the mapping symbols for future reference. Also check that
1536 we do not place two mapping symbols at the same offset within a
1537 frag. We'll handle overlap between frags in
1538 check_mapping_symbols.
1540 If .fill or other data filling directive generates zero sized data,
1541 the mapping symbol for the following code will have the same value
1542 as the one generated for the data filling directive. In this case,
1543 we replace the old symbol with the new one at the same address. */
1546 if (frag
->tc_frag_data
.first_map
!= NULL
)
1548 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1549 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1552 frag
->tc_frag_data
.first_map
= symbolP
;
1554 if (frag
->tc_frag_data
.last_map
!= NULL
)
1556 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1557 S_GET_VALUE (symbolP
));
1558 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1559 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1562 frag
->tc_frag_data
.last_map
= symbolP
;
1565 /* We must sometimes convert a region marked as code to data during
1566 code alignment, if an odd number of bytes have to be padded. The
1567 code mapping symbol is pushed to an aligned address. */
1570 insert_data_mapping_symbol (enum mstate state
,
1571 valueT value
, fragS
* frag
, offsetT bytes
)
1573 /* If there was already a mapping symbol, remove it. */
1574 if (frag
->tc_frag_data
.last_map
!= NULL
1575 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1576 frag
->fr_address
+ value
)
1578 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1582 know (frag
->tc_frag_data
.first_map
== symp
);
1583 frag
->tc_frag_data
.first_map
= NULL
;
1585 frag
->tc_frag_data
.last_map
= NULL
;
1586 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1589 make_mapping_symbol (MAP_DATA
, value
, frag
);
1590 make_mapping_symbol (state
, value
+ bytes
, frag
);
1593 static void mapping_state_2 (enum mstate state
, int max_chars
);
1595 /* Set the mapping state to STATE. Only call this when about to
1596 emit some STATE bytes to the file. */
1599 mapping_state (enum mstate state
)
1601 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1603 if (state
== MAP_INSN
)
1604 /* AArch64 instructions require 4-byte alignment. When emitting
1605 instructions into any section, record the appropriate section
1607 record_alignment (now_seg
, 2);
1609 if (mapstate
== state
)
1610 /* The mapping symbol has already been emitted.
1611 There is nothing else to do. */
1614 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1615 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1616 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1617 evaluated later in the next else. */
1619 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1621 /* Only add the symbol if the offset is > 0:
1622 if we're at the first frag, check it's size > 0;
1623 if we're not at the first frag, then for sure
1624 the offset is > 0. */
1625 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1626 const int add_symbol
= (frag_now
!= frag_first
)
1627 || (frag_now_fix () > 0);
1630 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1634 mapping_state_2 (state
, 0);
1637 /* Same as mapping_state, but MAX_CHARS bytes have already been
1638 allocated. Put the mapping symbol that far back. */
1641 mapping_state_2 (enum mstate state
, int max_chars
)
1643 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1645 if (!SEG_NORMAL (now_seg
))
1648 if (mapstate
== state
)
1649 /* The mapping symbol has already been emitted.
1650 There is nothing else to do. */
1653 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1654 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1657 #define mapping_state(x) /* nothing */
1658 #define mapping_state_2(x, y) /* nothing */
1661 /* Directives: sectioning and alignment. */
1664 s_bss (int ignore ATTRIBUTE_UNUSED
)
1666 /* We don't support putting frags in the BSS segment, we fake it by
1667 marking in_bss, then looking at s_skip for clues. */
1668 subseg_set (bss_section
, 0);
1669 demand_empty_rest_of_line ();
1670 mapping_state (MAP_DATA
);
1674 s_even (int ignore ATTRIBUTE_UNUSED
)
1676 /* Never make frag if expect extra pass. */
1678 frag_align (1, 0, 0);
1680 record_alignment (now_seg
, 1);
1682 demand_empty_rest_of_line ();
1685 /* Directives: Literal pools. */
1687 static literal_pool
*
1688 find_literal_pool (int size
)
1692 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1694 if (pool
->section
== now_seg
1695 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1702 static literal_pool
*
1703 find_or_make_literal_pool (int size
)
1705 /* Next literal pool ID number. */
1706 static unsigned int latest_pool_num
= 1;
1709 pool
= find_literal_pool (size
);
1713 /* Create a new pool. */
1714 pool
= XNEW (literal_pool
);
1718 /* Currently we always put the literal pool in the current text
1719 section. If we were generating "small" model code where we
1720 knew that all code and initialised data was within 1MB then
1721 we could output literals to mergeable, read-only data
1724 pool
->next_free_entry
= 0;
1725 pool
->section
= now_seg
;
1726 pool
->sub_section
= now_subseg
;
1728 pool
->next
= list_of_pools
;
1729 pool
->symbol
= NULL
;
1731 /* Add it to the list. */
1732 list_of_pools
= pool
;
1735 /* New pools, and emptied pools, will have a NULL symbol. */
1736 if (pool
->symbol
== NULL
)
1738 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1739 &zero_address_frag
, 0);
1740 pool
->id
= latest_pool_num
++;
1747 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1748 Return TRUE on success, otherwise return FALSE. */
1750 add_to_lit_pool (expressionS
*exp
, int size
)
1755 pool
= find_or_make_literal_pool (size
);
1757 /* Check if this literal value is already in the pool. */
1758 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1760 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1762 if ((litexp
->X_op
== exp
->X_op
)
1763 && (exp
->X_op
== O_constant
)
1764 && (litexp
->X_add_number
== exp
->X_add_number
)
1765 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1768 if ((litexp
->X_op
== exp
->X_op
)
1769 && (exp
->X_op
== O_symbol
)
1770 && (litexp
->X_add_number
== exp
->X_add_number
)
1771 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1772 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1776 /* Do we need to create a new entry? */
1777 if (entry
== pool
->next_free_entry
)
1779 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1781 set_syntax_error (_("literal pool overflow"));
1785 pool
->literals
[entry
].exp
= *exp
;
1786 pool
->next_free_entry
+= 1;
1787 if (exp
->X_op
== O_big
)
1789 /* PR 16688: Bignums are held in a single global array. We must
1790 copy and preserve that value now, before it is overwritten. */
1791 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1793 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1794 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1797 pool
->literals
[entry
].bignum
= NULL
;
1800 exp
->X_op
= O_symbol
;
1801 exp
->X_add_number
= ((int) entry
) * size
;
1802 exp
->X_add_symbol
= pool
->symbol
;
1807 /* Can't use symbol_new here, so have to create a symbol and then at
1808 a later date assign it a value. That's what these functions do. */
1811 symbol_locate (symbolS
* symbolP
,
1812 const char *name
,/* It is copied, the caller can modify. */
1813 segT segment
, /* Segment identifier (SEG_<something>). */
1814 valueT valu
, /* Symbol value. */
1815 fragS
* frag
) /* Associated fragment. */
1818 char *preserved_copy_of_name
;
1820 name_length
= strlen (name
) + 1; /* +1 for \0. */
1821 obstack_grow (¬es
, name
, name_length
);
1822 preserved_copy_of_name
= obstack_finish (¬es
);
1824 #ifdef tc_canonicalize_symbol_name
1825 preserved_copy_of_name
=
1826 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1829 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1831 S_SET_SEGMENT (symbolP
, segment
);
1832 S_SET_VALUE (symbolP
, valu
);
1833 symbol_clear_list_pointers (symbolP
);
1835 symbol_set_frag (symbolP
, frag
);
1837 /* Link to end of symbol chain. */
1839 extern int symbol_table_frozen
;
1841 if (symbol_table_frozen
)
1845 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1847 obj_symbol_new_hook (symbolP
);
1849 #ifdef tc_symbol_new_hook
1850 tc_symbol_new_hook (symbolP
);
1854 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1855 #endif /* DEBUG_SYMS */
1860 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1867 for (align
= 2; align
<= 4; align
++)
1869 int size
= 1 << align
;
1871 pool
= find_literal_pool (size
);
1872 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1875 /* Align pool as you have word accesses.
1876 Only make a frag if we have to. */
1878 frag_align (align
, 0, 0);
1880 mapping_state (MAP_DATA
);
1882 record_alignment (now_seg
, align
);
1884 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1886 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1887 (valueT
) frag_now_fix (), frag_now
);
1888 symbol_table_insert (pool
->symbol
);
1890 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1892 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1894 if (exp
->X_op
== O_big
)
1896 /* PR 16688: Restore the global bignum value. */
1897 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1898 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1899 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1902 /* First output the expression in the instruction to the pool. */
1903 emit_expr (exp
, size
); /* .word|.xword */
1905 if (exp
->X_op
== O_big
)
1907 free (pool
->literals
[entry
].bignum
);
1908 pool
->literals
[entry
].bignum
= NULL
;
1912 /* Mark the pool as empty. */
1913 pool
->next_free_entry
= 0;
1914 pool
->symbol
= NULL
;
1919 /* Forward declarations for functions below, in the MD interface
1921 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1922 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1924 /* Directives: Data. */
1925 /* N.B. the support for relocation suffix in this directive needs to be
1926 implemented properly. */
1929 s_aarch64_elf_cons (int nbytes
)
1933 #ifdef md_flush_pending_output
1934 md_flush_pending_output ();
1937 if (is_it_end_of_statement ())
1939 demand_empty_rest_of_line ();
1943 #ifdef md_cons_align
1944 md_cons_align (nbytes
);
1947 mapping_state (MAP_DATA
);
1950 struct reloc_table_entry
*reloc
;
1954 if (exp
.X_op
!= O_symbol
)
1955 emit_expr (&exp
, (unsigned int) nbytes
);
1958 skip_past_char (&input_line_pointer
, '#');
1959 if (skip_past_char (&input_line_pointer
, ':'))
1961 reloc
= find_reloc_table_entry (&input_line_pointer
);
1963 as_bad (_("unrecognized relocation suffix"));
1965 as_bad (_("unimplemented relocation suffix"));
1966 ignore_rest_of_line ();
1970 emit_expr (&exp
, (unsigned int) nbytes
);
1973 while (*input_line_pointer
++ == ',');
1975 /* Put terminator back into stream. */
1976 input_line_pointer
--;
1977 demand_empty_rest_of_line ();
1980 /* Mark symbol that it follows a variant PCS convention. */
1983 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1989 elf_symbol_type
*elfsym
;
1991 c
= get_symbol_name (&name
);
1993 as_bad (_("Missing symbol name in directive"));
1994 sym
= symbol_find_or_make (name
);
1995 restore_line_pointer (c
);
1996 demand_empty_rest_of_line ();
1997 bfdsym
= symbol_get_bfdsym (sym
);
1998 elfsym
= elf_symbol_from (bfdsym
);
1999 gas_assert (elfsym
);
2000 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2002 #endif /* OBJ_ELF */
2004 /* Output a 32-bit word, but mark as an instruction. */
2007 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2011 #ifdef md_flush_pending_output
2012 md_flush_pending_output ();
2015 if (is_it_end_of_statement ())
2017 demand_empty_rest_of_line ();
2021 /* Sections are assumed to start aligned. In executable section, there is no
2022 MAP_DATA symbol pending. So we only align the address during
2023 MAP_DATA --> MAP_INSN transition.
2024 For other sections, this is not guaranteed. */
2025 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2026 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2027 frag_align_code (2, 0);
2030 mapping_state (MAP_INSN
);
2036 if (exp
.X_op
!= O_constant
)
2038 as_bad (_("constant expression required"));
2039 ignore_rest_of_line ();
2043 if (target_big_endian
)
2045 unsigned int val
= exp
.X_add_number
;
2046 exp
.X_add_number
= SWAP_32 (val
);
2048 emit_expr (&exp
, 4);
2050 while (*input_line_pointer
++ == ',');
2052 /* Put terminator back into stream. */
2053 input_line_pointer
--;
2054 demand_empty_rest_of_line ();
2058 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2060 demand_empty_rest_of_line ();
2061 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2062 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2066 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2069 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2075 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2076 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2078 demand_empty_rest_of_line ();
2081 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2084 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2088 /* Since we're just labelling the code, there's no need to define a
2091 /* Make sure there is enough room in this frag for the following
2092 blr. This trick only works if the blr follows immediately after
2093 the .tlsdesc directive. */
2095 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2096 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2098 demand_empty_rest_of_line ();
2101 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2104 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2110 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2111 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2113 demand_empty_rest_of_line ();
2115 #endif /* OBJ_ELF */
2117 static void s_aarch64_arch (int);
2118 static void s_aarch64_cpu (int);
2119 static void s_aarch64_arch_extension (int);
2121 /* This table describes all the machine specific pseudo-ops the assembler
2122 has to support. The fields are:
2123 pseudo-op name without dot
2124 function to call to execute this pseudo-op
2125 Integer arg to pass to the function. */
2127 const pseudo_typeS md_pseudo_table
[] = {
2128 /* Never called because '.req' does not start a line. */
2130 {"unreq", s_unreq
, 0},
2132 {"even", s_even
, 0},
2133 {"ltorg", s_ltorg
, 0},
2134 {"pool", s_ltorg
, 0},
2135 {"cpu", s_aarch64_cpu
, 0},
2136 {"arch", s_aarch64_arch
, 0},
2137 {"arch_extension", s_aarch64_arch_extension
, 0},
2138 {"inst", s_aarch64_inst
, 0},
2139 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2141 {"tlsdescadd", s_tlsdescadd
, 0},
2142 {"tlsdesccall", s_tlsdesccall
, 0},
2143 {"tlsdescldr", s_tlsdescldr
, 0},
2144 {"word", s_aarch64_elf_cons
, 4},
2145 {"long", s_aarch64_elf_cons
, 4},
2146 {"xword", s_aarch64_elf_cons
, 8},
2147 {"dword", s_aarch64_elf_cons
, 8},
2148 {"variant_pcs", s_variant_pcs
, 0},
2150 {"float16", float_cons
, 'h'},
2151 {"bfloat16", float_cons
, 'b'},
2156 /* Check whether STR points to a register name followed by a comma or the
2157 end of line; REG_TYPE indicates which register types are checked
2158 against. Return TRUE if STR is such a register name; otherwise return
2159 FALSE. The function does not intend to produce any diagnostics, but since
2160 the register parser aarch64_reg_parse, which is called by this function,
2161 does produce diagnostics, we call clear_error to clear any diagnostics
2162 that may be generated by aarch64_reg_parse.
2163 Also, the function returns FALSE directly if there is any user error
2164 present at the function entry. This prevents the existing diagnostics
2165 state from being spoiled.
2166 The function currently serves parse_constant_immediate and
2167 parse_big_immediate only. */
2169 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2173 /* Prevent the diagnostics state from being spoiled. */
2177 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2179 /* Clear the parsing error that may be set by the reg parser. */
2182 if (reg
== PARSE_FAIL
)
2185 skip_whitespace (str
);
2186 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2192 /* Parser functions used exclusively in instruction operands. */
2194 /* Parse an immediate expression which may not be constant.
2196 To prevent the expression parser from pushing a register name
2197 into the symbol table as an undefined symbol, firstly a check is
2198 done to find out whether STR is a register of type REG_TYPE followed
2199 by a comma or the end of line. Return FALSE if STR is such a string. */
2202 parse_immediate_expression (char **str
, expressionS
*exp
,
2203 aarch64_reg_type reg_type
)
2205 if (reg_name_p (*str
, reg_type
))
2207 set_recoverable_error (_("immediate operand required"));
2211 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2213 if (exp
->X_op
== O_absent
)
2215 set_fatal_syntax_error (_("missing immediate expression"));
2222 /* Constant immediate-value read function for use in insn parsing.
2223 STR points to the beginning of the immediate (with the optional
2224 leading #); *VAL receives the value. REG_TYPE says which register
2225 names should be treated as registers rather than as symbolic immediates.
2227 Return TRUE on success; otherwise return FALSE. */
2230 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2234 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2237 if (exp
.X_op
!= O_constant
)
2239 set_syntax_error (_("constant expression required"));
2243 *val
= exp
.X_add_number
;
2248 encode_imm_float_bits (uint32_t imm
)
2250 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2251 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2254 /* Return TRUE if the single-precision floating-point value encoded in IMM
2255 can be expressed in the AArch64 8-bit signed floating-point format with
2256 3-bit exponent and normalized 4 bits of precision; in other words, the
2257 floating-point value must be expressable as
2258 (+/-) n / 16 * power (2, r)
2259 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2262 aarch64_imm_float_p (uint32_t imm
)
2264 /* If a single-precision floating-point value has the following bit
2265 pattern, it can be expressed in the AArch64 8-bit floating-point
2268 3 32222222 2221111111111
2269 1 09876543 21098765432109876543210
2270 n Eeeeeexx xxxx0000000000000000000
2272 where n, e and each x are either 0 or 1 independently, with
2277 /* Prepare the pattern for 'Eeeeee'. */
2278 if (((imm
>> 30) & 0x1) == 0)
2279 pattern
= 0x3e000000;
2281 pattern
= 0x40000000;
2283 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2284 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2287 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2288 as an IEEE float without any loss of precision. Store the value in
2292 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2294 /* If a double-precision floating-point value has the following bit
2295 pattern, it can be expressed in a float:
2297 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2298 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2299 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2301 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2302 if Eeee_eeee != 1111_1111
2304 where n, e, s and S are either 0 or 1 independently and where ~ is the
2308 uint32_t high32
= imm
>> 32;
2309 uint32_t low32
= imm
;
2311 /* Lower 29 bits need to be 0s. */
2312 if ((imm
& 0x1fffffff) != 0)
2315 /* Prepare the pattern for 'Eeeeeeeee'. */
2316 if (((high32
>> 30) & 0x1) == 0)
2317 pattern
= 0x38000000;
2319 pattern
= 0x40000000;
2322 if ((high32
& 0x78000000) != pattern
)
2325 /* Check Eeee_eeee != 1111_1111. */
2326 if ((high32
& 0x7ff00000) == 0x47f00000)
2329 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2330 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2331 | (low32
>> 29)); /* 3 S bits. */
2335 /* Return true if we should treat OPERAND as a double-precision
2336 floating-point operand rather than a single-precision one. */
2338 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2340 /* Check for unsuffixed SVE registers, which are allowed
2341 for LDR and STR but not in instructions that require an
2342 immediate. We get better error messages if we arbitrarily
2343 pick one size, parse the immediate normally, and then
2344 report the match failure in the normal way. */
2345 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2346 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2349 /* Parse a floating-point immediate. Return TRUE on success and return the
2350 value in *IMMED in the format of IEEE754 single-precision encoding.
2351 *CCP points to the start of the string; DP_P is TRUE when the immediate
2352 is expected to be in double-precision (N.B. this only matters when
2353 hexadecimal representation is involved). REG_TYPE says which register
2354 names should be treated as registers rather than as symbolic immediates.
2356 This routine accepts any IEEE float; it is up to the callers to reject
2360 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2361 aarch64_reg_type reg_type
)
2365 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2367 unsigned fpword
= 0;
2368 bfd_boolean hex_p
= FALSE
;
2370 skip_past_char (&str
, '#');
2373 skip_whitespace (fpnum
);
2375 if (strncmp (fpnum
, "0x", 2) == 0)
2377 /* Support the hexadecimal representation of the IEEE754 encoding.
2378 Double-precision is expected when DP_P is TRUE, otherwise the
2379 representation should be in single-precision. */
2380 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2385 if (!can_convert_double_to_float (val
, &fpword
))
2388 else if ((uint64_t) val
> 0xffffffff)
2395 else if (reg_name_p (str
, reg_type
))
2397 set_recoverable_error (_("immediate operand required"));
2405 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2408 /* Our FP word must be 32 bits (single-precision FP). */
2409 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2411 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2421 set_fatal_syntax_error (_("invalid floating-point constant"));
2425 /* Less-generic immediate-value read function with the possibility of loading
2426 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2429 To prevent the expression parser from pushing a register name into the
2430 symbol table as an undefined symbol, a check is firstly done to find
2431 out whether STR is a register of type REG_TYPE followed by a comma or
2432 the end of line. Return FALSE if STR is such a register. */
2435 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2439 if (reg_name_p (ptr
, reg_type
))
2441 set_syntax_error (_("immediate operand required"));
2445 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2447 if (inst
.reloc
.exp
.X_op
== O_constant
)
2448 *imm
= inst
.reloc
.exp
.X_add_number
;
2455 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2456 if NEED_LIBOPCODES is non-zero, the fixup will need
2457 assistance from the libopcodes. */
2460 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2461 const aarch64_opnd_info
*operand
,
2462 int need_libopcodes_p
)
2464 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2465 reloc
->opnd
= operand
->type
;
2466 if (need_libopcodes_p
)
2467 reloc
->need_libopcodes_p
= 1;
2470 /* Return TRUE if the instruction needs to be fixed up later internally by
2471 the GAS; otherwise return FALSE. */
2473 static inline bfd_boolean
2474 aarch64_gas_internal_fixup_p (void)
2476 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2479 /* Assign the immediate value to the relevant field in *OPERAND if
2480 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2481 needs an internal fixup in a later stage.
2482 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2483 IMM.VALUE that may get assigned with the constant. */
2485 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2486 aarch64_opnd_info
*operand
,
2488 int need_libopcodes_p
,
2491 if (reloc
->exp
.X_op
== O_constant
)
2494 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2496 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2497 reloc
->type
= BFD_RELOC_UNUSED
;
2501 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2502 /* Tell libopcodes to ignore this operand or not. This is helpful
2503 when one of the operands needs to be fixed up later but we need
2504 libopcodes to check the other operands. */
2505 operand
->skip
= skip_p
;
2509 /* Relocation modifiers. Each entry in the table contains the textual
2510 name for the relocation which may be placed before a symbol used as
2511 a load/store offset, or add immediate. It must be surrounded by a
2512 leading and trailing colon, for example:
2514 ldr x0, [x1, #:rello:varsym]
2515 add x0, x1, #:rello:varsym */
2517 struct reloc_table_entry
2521 bfd_reloc_code_real_type adr_type
;
2522 bfd_reloc_code_real_type adrp_type
;
2523 bfd_reloc_code_real_type movw_type
;
2524 bfd_reloc_code_real_type add_type
;
2525 bfd_reloc_code_real_type ldst_type
;
2526 bfd_reloc_code_real_type ld_literal_type
;
2529 static struct reloc_table_entry reloc_table
[] = {
2530 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2535 BFD_RELOC_AARCH64_ADD_LO12
,
2536 BFD_RELOC_AARCH64_LDST_LO12
,
2539 /* Higher 21 bits of pc-relative page offset: ADRP */
2542 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2548 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2551 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2557 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2561 BFD_RELOC_AARCH64_MOVW_G0
,
2566 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2570 BFD_RELOC_AARCH64_MOVW_G0_S
,
2575 /* Less significant bits 0-15 of address/value: MOVK, no check */
2579 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2584 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2588 BFD_RELOC_AARCH64_MOVW_G1
,
2593 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2597 BFD_RELOC_AARCH64_MOVW_G1_S
,
2602 /* Less significant bits 16-31 of address/value: MOVK, no check */
2606 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2611 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2615 BFD_RELOC_AARCH64_MOVW_G2
,
2620 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2624 BFD_RELOC_AARCH64_MOVW_G2_S
,
2629 /* Less significant bits 32-47 of address/value: MOVK, no check */
2633 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2638 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2642 BFD_RELOC_AARCH64_MOVW_G3
,
2647 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2651 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2656 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2660 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2665 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2669 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2674 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2678 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2683 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2687 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2692 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2696 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2701 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2705 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2710 /* Get to the page containing GOT entry for a symbol. */
2713 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2717 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2719 /* 12 bit offset into the page containing GOT entry for that symbol. */
2725 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2728 /* 0-15 bits of address/value: MOVk, no check. */
2732 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2737 /* Most significant bits 16-31 of address/value: MOVZ. */
2741 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2746 /* 15 bit offset into the page containing GOT entry for that symbol. */
2752 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2755 /* Get to the page containing GOT TLS entry for a symbol */
2756 {"gottprel_g0_nc", 0,
2759 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2764 /* Get to the page containing GOT TLS entry for a symbol */
2768 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2773 /* Get to the page containing GOT TLS entry for a symbol */
2775 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2776 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2782 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2787 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2791 /* Lower 16 bits address/value: MOVk. */
2795 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2800 /* Most significant bits 16-31 of address/value: MOVZ. */
2804 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2809 /* Get to the page containing GOT TLS entry for a symbol */
2811 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2812 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2816 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2818 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2823 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2824 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2827 /* Get to the page containing GOT TLS entry for a symbol.
2828 The same as GD, we allocate two consecutive GOT slots
2829 for module index and module offset, the only difference
2830 with GD is the module offset should be initialized to
2831 zero without any outstanding runtime relocation. */
2833 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2834 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2840 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2841 {"tlsldm_lo12_nc", 0,
2845 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2849 /* 12 bit offset into the module TLS base address. */
2854 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2855 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2858 /* Same as dtprel_lo12, no overflow check. */
2859 {"dtprel_lo12_nc", 0,
2863 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2864 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2867 /* bits[23:12] of offset to the module TLS base address. */
2872 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2876 /* bits[15:0] of offset to the module TLS base address. */
2880 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2885 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2889 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2894 /* bits[31:16] of offset to the module TLS base address. */
2898 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2903 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2907 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2912 /* bits[47:32] of offset to the module TLS base address. */
2916 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2921 /* Lower 16 bit offset into GOT entry for a symbol */
2922 {"tlsdesc_off_g0_nc", 0,
2925 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2930 /* Higher 16 bit offset into GOT entry for a symbol */
2931 {"tlsdesc_off_g1", 0,
2934 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2939 /* Get to the page containing GOT TLS entry for a symbol */
2942 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2946 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2948 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2949 {"gottprel_lo12", 0,
2954 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2957 /* Get tp offset for a symbol. */
2962 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2966 /* Get tp offset for a symbol. */
2971 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2972 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2975 /* Get tp offset for a symbol. */
2980 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2984 /* Get tp offset for a symbol. */
2985 {"tprel_lo12_nc", 0,
2989 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2990 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2993 /* Most significant bits 32-47 of address/value: MOVZ. */
2997 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3002 /* Most significant bits 16-31 of address/value: MOVZ. */
3006 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3011 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3015 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3020 /* Most significant bits 0-15 of address/value: MOVZ. */
3024 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3029 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3033 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3038 /* 15bit offset from got entry to base address of GOT table. */
3044 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3047 /* 14bit offset from got entry to base address of GOT table. */
3053 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3057 /* Given the address of a pointer pointing to the textual name of a
3058 relocation as may appear in assembler source, attempt to find its
3059 details in reloc_table. The pointer will be updated to the character
3060 after the trailing colon. On failure, NULL will be returned;
3061 otherwise return the reloc_table_entry. */
3063 static struct reloc_table_entry
*
3064 find_reloc_table_entry (char **str
)
3067 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3069 int length
= strlen (reloc_table
[i
].name
);
3071 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3072 && (*str
)[length
] == ':')
3074 *str
+= (length
+ 1);
3075 return &reloc_table
[i
];
3082 /* Mode argument to parse_shift and parser_shifter_operand. */
3083 enum parse_shift_mode
3085 SHIFTED_NONE
, /* no shifter allowed */
3086 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3088 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3090 SHIFTED_LSL
, /* bare "lsl #n" */
3091 SHIFTED_MUL
, /* bare "mul #n" */
3092 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3093 SHIFTED_MUL_VL
, /* "mul vl" */
3094 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3097 /* Parse a <shift> operator on an AArch64 data processing instruction.
3098 Return TRUE on success; otherwise return FALSE. */
3100 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3102 const struct aarch64_name_value_pair
*shift_op
;
3103 enum aarch64_modifier_kind kind
;
3109 for (p
= *str
; ISALPHA (*p
); p
++)
3114 set_syntax_error (_("shift expression expected"));
3118 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3120 if (shift_op
== NULL
)
3122 set_syntax_error (_("shift operator expected"));
3126 kind
= aarch64_get_operand_modifier (shift_op
);
3128 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3130 set_syntax_error (_("invalid use of 'MSL'"));
3134 if (kind
== AARCH64_MOD_MUL
3135 && mode
!= SHIFTED_MUL
3136 && mode
!= SHIFTED_MUL_VL
)
3138 set_syntax_error (_("invalid use of 'MUL'"));
3144 case SHIFTED_LOGIC_IMM
:
3145 if (aarch64_extend_operator_p (kind
))
3147 set_syntax_error (_("extending shift is not permitted"));
3152 case SHIFTED_ARITH_IMM
:
3153 if (kind
== AARCH64_MOD_ROR
)
3155 set_syntax_error (_("'ROR' shift is not permitted"));
3161 if (kind
!= AARCH64_MOD_LSL
)
3163 set_syntax_error (_("only 'LSL' shift is permitted"));
3169 if (kind
!= AARCH64_MOD_MUL
)
3171 set_syntax_error (_("only 'MUL' is permitted"));
3176 case SHIFTED_MUL_VL
:
3177 /* "MUL VL" consists of two separate tokens. Require the first
3178 token to be "MUL" and look for a following "VL". */
3179 if (kind
== AARCH64_MOD_MUL
)
3181 skip_whitespace (p
);
3182 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3185 kind
= AARCH64_MOD_MUL_VL
;
3189 set_syntax_error (_("only 'MUL VL' is permitted"));
3192 case SHIFTED_REG_OFFSET
:
3193 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3194 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3196 set_fatal_syntax_error
3197 (_("invalid shift for the register offset addressing mode"));
3202 case SHIFTED_LSL_MSL
:
3203 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3205 set_syntax_error (_("invalid shift operator"));
3214 /* Whitespace can appear here if the next thing is a bare digit. */
3215 skip_whitespace (p
);
3217 /* Parse shift amount. */
3219 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3220 exp
.X_op
= O_absent
;
3223 if (is_immediate_prefix (*p
))
3228 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3230 if (kind
== AARCH64_MOD_MUL_VL
)
3231 /* For consistency, give MUL VL the same shift amount as an implicit
3233 operand
->shifter
.amount
= 1;
3234 else if (exp
.X_op
== O_absent
)
3236 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3238 set_syntax_error (_("missing shift amount"));
3241 operand
->shifter
.amount
= 0;
3243 else if (exp
.X_op
!= O_constant
)
3245 set_syntax_error (_("constant shift amount required"));
3248 /* For parsing purposes, MUL #n has no inherent range. The range
3249 depends on the operand and will be checked by operand-specific
3251 else if (kind
!= AARCH64_MOD_MUL
3252 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3254 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3259 operand
->shifter
.amount
= exp
.X_add_number
;
3260 operand
->shifter
.amount_present
= 1;
3263 operand
->shifter
.operator_present
= 1;
3264 operand
->shifter
.kind
= kind
;
3270 /* Parse a <shifter_operand> for a data processing instruction:
3273 #<immediate>, LSL #imm
3275 Validation of immediate operands is deferred to md_apply_fix.
3277 Return TRUE on success; otherwise return FALSE. */
3280 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3281 enum parse_shift_mode mode
)
3285 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3290 /* Accept an immediate expression. */
3291 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3294 /* Accept optional LSL for arithmetic immediate values. */
3295 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3296 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3299 /* Not accept any shifter for logical immediate values. */
3300 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3301 && parse_shift (&p
, operand
, mode
))
3303 set_syntax_error (_("unexpected shift operator"));
3311 /* Parse a <shifter_operand> for a data processing instruction:
3316 #<immediate>, LSL #imm
3318 where <shift> is handled by parse_shift above, and the last two
3319 cases are handled by the function above.
3321 Validation of immediate operands is deferred to md_apply_fix.
3323 Return TRUE on success; otherwise return FALSE. */
3326 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3327 enum parse_shift_mode mode
)
3329 const reg_entry
*reg
;
3330 aarch64_opnd_qualifier_t qualifier
;
3331 enum aarch64_operand_class opd_class
3332 = aarch64_get_operand_class (operand
->type
);
3334 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3337 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3339 set_syntax_error (_("unexpected register in the immediate operand"));
3343 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3345 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3349 operand
->reg
.regno
= reg
->number
;
3350 operand
->qualifier
= qualifier
;
3352 /* Accept optional shift operation on register. */
3353 if (! skip_past_comma (str
))
3356 if (! parse_shift (str
, operand
, mode
))
3361 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3364 (_("integer register expected in the extended/shifted operand "
3369 /* We have a shifted immediate variable. */
3370 return parse_shifter_operand_imm (str
, operand
, mode
);
3373 /* Return TRUE on success; return FALSE otherwise. */
3376 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3377 enum parse_shift_mode mode
)
3381 /* Determine if we have the sequence of characters #: or just :
3382 coming next. If we do, then we check for a :rello: relocation
3383 modifier. If we don't, punt the whole lot to
3384 parse_shifter_operand. */
3386 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3388 struct reloc_table_entry
*entry
;
3396 /* Try to parse a relocation. Anything else is an error. */
3397 if (!(entry
= find_reloc_table_entry (str
)))
3399 set_syntax_error (_("unknown relocation modifier"));
3403 if (entry
->add_type
== 0)
3406 (_("this relocation modifier is not allowed on this instruction"));
3410 /* Save str before we decompose it. */
3413 /* Next, we parse the expression. */
3414 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3417 /* Record the relocation type (use the ADD variant here). */
3418 inst
.reloc
.type
= entry
->add_type
;
3419 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3421 /* If str is empty, we've reached the end, stop here. */
3425 /* Otherwise, we have a shifted reloc modifier, so rewind to
3426 recover the variable name and continue parsing for the shifter. */
3428 return parse_shifter_operand_imm (str
, operand
, mode
);
3431 return parse_shifter_operand (str
, operand
, mode
);
3434 /* Parse all forms of an address expression. Information is written
3435 to *OPERAND and/or inst.reloc.
3437 The A64 instruction set has the following addressing modes:
3440 [base] // in SIMD ld/st structure
3441 [base{,#0}] // in ld/st exclusive
3443 [base,Xm{,LSL #imm}]
3444 [base,Xm,SXTX {#imm}]
3445 [base,Wm,(S|U)XTW {#imm}]
3447 [base]! // in ldraa/ldrab exclusive
3451 [base],Xm // in SIMD ld/st structure
3452 PC-relative (literal)
3456 [base,Zm.D{,LSL #imm}]
3457 [base,Zm.S,(S|U)XTW {#imm}]
3458 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3462 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3463 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3464 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3466 (As a convenience, the notation "=immediate" is permitted in conjunction
3467 with the pc-relative literal load instructions to automatically place an
3468 immediate value or symbolic address in a nearby literal pool and generate
3469 a hidden label which references it.)
3471 Upon a successful parsing, the address structure in *OPERAND will be
3472 filled in the following way:
3474 .base_regno = <base>
3475 .offset.is_reg // 1 if the offset is a register
3477 .offset.regno = <Rm>
3479 For different addressing modes defined in the A64 ISA:
3482 .pcrel=0; .preind=1; .postind=0; .writeback=0
3484 .pcrel=0; .preind=1; .postind=0; .writeback=1
3486 .pcrel=0; .preind=0; .postind=1; .writeback=1
3487 PC-relative (literal)
3488 .pcrel=1; .preind=1; .postind=0; .writeback=0
3490 The shift/extension information, if any, will be stored in .shifter.
3491 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3492 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3493 corresponding register.
3495 BASE_TYPE says which types of base register should be accepted and
3496 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3497 is the type of shifter that is allowed for immediate offsets,
3498 or SHIFTED_NONE if none.
3500 In all other respects, it is the caller's responsibility to check
3501 for addressing modes not supported by the instruction, and to set
3505 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3506 aarch64_opnd_qualifier_t
*base_qualifier
,
3507 aarch64_opnd_qualifier_t
*offset_qualifier
,
3508 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3509 enum parse_shift_mode imm_shift_mode
)
3512 const reg_entry
*reg
;
3513 expressionS
*exp
= &inst
.reloc
.exp
;
3515 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3516 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3517 if (! skip_past_char (&p
, '['))
3519 /* =immediate or label. */
3520 operand
->addr
.pcrel
= 1;
3521 operand
->addr
.preind
= 1;
3523 /* #:<reloc_op>:<symbol> */
3524 skip_past_char (&p
, '#');
3525 if (skip_past_char (&p
, ':'))
3527 bfd_reloc_code_real_type ty
;
3528 struct reloc_table_entry
*entry
;
3530 /* Try to parse a relocation modifier. Anything else is
3532 entry
= find_reloc_table_entry (&p
);
3535 set_syntax_error (_("unknown relocation modifier"));
3539 switch (operand
->type
)
3541 case AARCH64_OPND_ADDR_PCREL21
:
3543 ty
= entry
->adr_type
;
3547 ty
= entry
->ld_literal_type
;
3554 (_("this relocation modifier is not allowed on this "
3560 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3562 set_syntax_error (_("invalid relocation expression"));
3566 /* #:<reloc_op>:<expr> */
3567 /* Record the relocation type. */
3568 inst
.reloc
.type
= ty
;
3569 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3574 if (skip_past_char (&p
, '='))
3575 /* =immediate; need to generate the literal in the literal pool. */
3576 inst
.gen_lit_pool
= 1;
3578 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3580 set_syntax_error (_("invalid address"));
3591 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3592 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3594 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3597 operand
->addr
.base_regno
= reg
->number
;
3600 if (skip_past_comma (&p
))
3603 operand
->addr
.preind
= 1;
3605 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3608 if (!aarch64_check_reg_type (reg
, offset_type
))
3610 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3615 operand
->addr
.offset
.regno
= reg
->number
;
3616 operand
->addr
.offset
.is_reg
= 1;
3617 /* Shifted index. */
3618 if (skip_past_comma (&p
))
3621 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3622 /* Use the diagnostics set in parse_shift, so not set new
3623 error message here. */
3627 [base,Xm] # For vector plus scalar SVE2 indexing.
3628 [base,Xm{,LSL #imm}]
3629 [base,Xm,SXTX {#imm}]
3630 [base,Wm,(S|U)XTW {#imm}] */
3631 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3632 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3633 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3635 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3637 set_syntax_error (_("invalid use of 32-bit register offset"));
3640 if (aarch64_get_qualifier_esize (*base_qualifier
)
3641 != aarch64_get_qualifier_esize (*offset_qualifier
)
3642 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3643 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3644 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3646 set_syntax_error (_("offset has different size from base"));
3650 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3652 set_syntax_error (_("invalid use of 64-bit register offset"));
3658 /* [Xn,#:<reloc_op>:<symbol> */
3659 skip_past_char (&p
, '#');
3660 if (skip_past_char (&p
, ':'))
3662 struct reloc_table_entry
*entry
;
3664 /* Try to parse a relocation modifier. Anything else is
3666 if (!(entry
= find_reloc_table_entry (&p
)))
3668 set_syntax_error (_("unknown relocation modifier"));
3672 if (entry
->ldst_type
== 0)
3675 (_("this relocation modifier is not allowed on this "
3680 /* [Xn,#:<reloc_op>: */
3681 /* We now have the group relocation table entry corresponding to
3682 the name in the assembler source. Next, we parse the
3684 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3686 set_syntax_error (_("invalid relocation expression"));
3690 /* [Xn,#:<reloc_op>:<expr> */
3691 /* Record the load/store relocation type. */
3692 inst
.reloc
.type
= entry
->ldst_type
;
3693 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3697 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3699 set_syntax_error (_("invalid expression in the address"));
3703 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3704 /* [Xn,<expr>,<shifter> */
3705 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3711 if (! skip_past_char (&p
, ']'))
3713 set_syntax_error (_("']' expected"));
3717 if (skip_past_char (&p
, '!'))
3719 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3721 set_syntax_error (_("register offset not allowed in pre-indexed "
3722 "addressing mode"));
3726 operand
->addr
.writeback
= 1;
3728 else if (skip_past_comma (&p
))
3731 operand
->addr
.postind
= 1;
3732 operand
->addr
.writeback
= 1;
3734 if (operand
->addr
.preind
)
3736 set_syntax_error (_("cannot combine pre- and post-indexing"));
3740 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3744 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3746 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3750 operand
->addr
.offset
.regno
= reg
->number
;
3751 operand
->addr
.offset
.is_reg
= 1;
3753 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3756 set_syntax_error (_("invalid expression in the address"));
3761 /* If at this point neither .preind nor .postind is set, we have a
3762 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3763 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3764 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3766 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3768 if (operand
->addr
.writeback
)
3770 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3772 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3773 operand
->addr
.offset
.is_reg
= 0;
3774 operand
->addr
.offset
.imm
= 0;
3775 operand
->addr
.preind
= 1;
3780 set_syntax_error (_("missing offset in the pre-indexed address"));
3786 operand
->addr
.preind
= 1;
3787 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3789 operand
->addr
.offset
.is_reg
= 1;
3790 operand
->addr
.offset
.regno
= REG_ZR
;
3791 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3795 inst
.reloc
.exp
.X_op
= O_constant
;
3796 inst
.reloc
.exp
.X_add_number
= 0;
3805 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3808 parse_address (char **str
, aarch64_opnd_info
*operand
)
3810 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3811 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3812 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3815 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3816 The arguments have the same meaning as for parse_address_main.
3817 Return TRUE on success. */
3819 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3820 aarch64_opnd_qualifier_t
*base_qualifier
,
3821 aarch64_opnd_qualifier_t
*offset_qualifier
)
3823 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3824 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3828 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3829 Return TRUE on success; otherwise return FALSE. */
3831 parse_half (char **str
, int *internal_fixup_p
)
3835 skip_past_char (&p
, '#');
3837 gas_assert (internal_fixup_p
);
3838 *internal_fixup_p
= 0;
3842 struct reloc_table_entry
*entry
;
3844 /* Try to parse a relocation. Anything else is an error. */
3846 if (!(entry
= find_reloc_table_entry (&p
)))
3848 set_syntax_error (_("unknown relocation modifier"));
3852 if (entry
->movw_type
== 0)
3855 (_("this relocation modifier is not allowed on this instruction"));
3859 inst
.reloc
.type
= entry
->movw_type
;
3862 *internal_fixup_p
= 1;
3864 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3871 /* Parse an operand for an ADRP instruction:
3873 Return TRUE on success; otherwise return FALSE. */
3876 parse_adrp (char **str
)
3883 struct reloc_table_entry
*entry
;
3885 /* Try to parse a relocation. Anything else is an error. */
3887 if (!(entry
= find_reloc_table_entry (&p
)))
3889 set_syntax_error (_("unknown relocation modifier"));
3893 if (entry
->adrp_type
== 0)
3896 (_("this relocation modifier is not allowed on this instruction"));
3900 inst
.reloc
.type
= entry
->adrp_type
;
3903 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3905 inst
.reloc
.pc_rel
= 1;
3907 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3914 /* Miscellaneous. */
3916 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3917 of SIZE tokens in which index I gives the token for field value I,
3918 or is null if field value I is invalid. REG_TYPE says which register
3919 names should be treated as registers rather than as symbolic immediates.
3921 Return true on success, moving *STR past the operand and storing the
3922 field value in *VAL. */
3925 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3926 size_t size
, aarch64_reg_type reg_type
)
3932 /* Match C-like tokens. */
3934 while (ISALNUM (*q
))
3937 for (i
= 0; i
< size
; ++i
)
3939 && strncasecmp (array
[i
], p
, q
- p
) == 0
3940 && array
[i
][q
- p
] == 0)
3947 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3950 if (exp
.X_op
== O_constant
3951 && (uint64_t) exp
.X_add_number
< size
)
3953 *val
= exp
.X_add_number
;
3958 /* Use the default error for this operand. */
3962 /* Parse an option for a preload instruction. Returns the encoding for the
3963 option, or PARSE_FAIL. */
3966 parse_pldop (char **str
)
3969 const struct aarch64_name_value_pair
*o
;
3972 while (ISALNUM (*q
))
3975 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3983 /* Parse an option for a barrier instruction. Returns the encoding for the
3984 option, or PARSE_FAIL. */
3987 parse_barrier (char **str
)
3990 const struct aarch64_name_value_pair
*o
;
3993 while (ISALPHA (*q
))
3996 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4004 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4005 return 0 if successful. Otherwise return PARSE_FAIL. */
4008 parse_barrier_psb (char **str
,
4009 const struct aarch64_name_value_pair
** hint_opt
)
4012 const struct aarch64_name_value_pair
*o
;
4015 while (ISALPHA (*q
))
4018 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4021 set_fatal_syntax_error
4022 ( _("unknown or missing option to PSB/TSB"));
4026 if (o
->value
!= 0x11)
4028 /* PSB only accepts option name 'CSYNC'. */
4030 (_("the specified option is not accepted for PSB/TSB"));
4039 /* Parse an operand for CSR (CSRE instruction). */
4042 parse_csr_operand (char **str
)
4047 while (ISALPHA (*q
))
4050 /* Instruction has only one operand PDEC which encodes Rt field of the
4051 operation to 0b11111. */
4052 if (strcasecmp(p
, "pdec"))
4054 set_syntax_error (_("CSR instruction accepts only PDEC"));
4062 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4063 return 0 if successful. Otherwise return PARSE_FAIL. */
4066 parse_bti_operand (char **str
,
4067 const struct aarch64_name_value_pair
** hint_opt
)
4070 const struct aarch64_name_value_pair
*o
;
4073 while (ISALPHA (*q
))
4076 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4079 set_fatal_syntax_error
4080 ( _("unknown option to BTI"));
4086 /* Valid BTI operands. */
4094 (_("unknown option to BTI"));
4103 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4104 Returns the encoding for the option, or PARSE_FAIL.
4106 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4107 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4109 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4110 field, otherwise as a system register.
4114 parse_sys_reg (char **str
, htab_t sys_regs
,
4115 int imple_defined_p
, int pstatefield_p
,
4119 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4120 const aarch64_sys_reg
*o
;
4124 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4125 if (p
< buf
+ (sizeof (buf
) - 1))
4126 *p
++ = TOLOWER (*q
);
4129 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4130 valid system register. This is enforced by construction of the hash
4132 if (p
- buf
!= q
- *str
)
4135 o
= str_hash_find (sys_regs
, buf
);
4138 if (!imple_defined_p
)
4142 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4143 unsigned int op0
, op1
, cn
, cm
, op2
;
4145 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4148 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4150 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4157 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4158 as_bad (_("selected processor does not support PSTATE field "
4161 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4162 o
->value
, o
->flags
, o
->features
))
4163 as_bad (_("selected processor does not support system register "
4165 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4166 as_warn (_("system register name '%s' is deprecated and may be "
4167 "removed in a future release"), buf
);
4177 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4178 for the option, or NULL. */
4180 static const aarch64_sys_ins_reg
*
4181 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4184 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4185 const aarch64_sys_ins_reg
*o
;
4188 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4189 if (p
< buf
+ (sizeof (buf
) - 1))
4190 *p
++ = TOLOWER (*q
);
4193 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4194 valid system register. This is enforced by construction of the hash
4196 if (p
- buf
!= q
- *str
)
4199 o
= str_hash_find (sys_ins_regs
, buf
);
4203 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4204 o
->name
, o
->value
, o
->flags
, 0))
4205 as_bad (_("selected processor does not support system register "
4207 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4208 as_warn (_("system register name '%s' is deprecated and may be "
4209 "removed in a future release"), buf
);
4215 #define po_char_or_fail(chr) do { \
4216 if (! skip_past_char (&str, chr)) \
4220 #define po_reg_or_fail(regtype) do { \
4221 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4222 if (val == PARSE_FAIL) \
4224 set_default_error (); \
4229 #define po_int_reg_or_fail(reg_type) do { \
4230 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4231 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4233 set_default_error (); \
4236 info->reg.regno = reg->number; \
4237 info->qualifier = qualifier; \
4240 #define po_imm_nc_or_fail() do { \
4241 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4245 #define po_imm_or_fail(min, max) do { \
4246 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4248 if (val < min || val > max) \
4250 set_fatal_syntax_error (_("immediate value out of range "\
4251 #min " to "#max)); \
4256 #define po_enum_or_fail(array) do { \
4257 if (!parse_enum_string (&str, &val, array, \
4258 ARRAY_SIZE (array), imm_reg_type)) \
4262 #define po_misc_or_fail(expr) do { \
4267 /* encode the 12-bit imm field of Add/sub immediate */
4268 static inline uint32_t
4269 encode_addsub_imm (uint32_t imm
)
4274 /* encode the shift amount field of Add/sub immediate */
4275 static inline uint32_t
4276 encode_addsub_imm_shift_amount (uint32_t cnt
)
4282 /* encode the imm field of Adr instruction */
4283 static inline uint32_t
4284 encode_adr_imm (uint32_t imm
)
4286 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4287 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4290 /* encode the immediate field of Move wide immediate */
4291 static inline uint32_t
4292 encode_movw_imm (uint32_t imm
)
4297 /* encode the 26-bit offset of unconditional branch */
4298 static inline uint32_t
4299 encode_branch_ofs_26 (uint32_t ofs
)
4301 return ofs
& ((1 << 26) - 1);
4304 /* encode the 19-bit offset of conditional branch and compare & branch */
4305 static inline uint32_t
4306 encode_cond_branch_ofs_19 (uint32_t ofs
)
4308 return (ofs
& ((1 << 19) - 1)) << 5;
4311 /* encode the 19-bit offset of ld literal */
4312 static inline uint32_t
4313 encode_ld_lit_ofs_19 (uint32_t ofs
)
4315 return (ofs
& ((1 << 19) - 1)) << 5;
4318 /* Encode the 14-bit offset of test & branch. */
4319 static inline uint32_t
4320 encode_tst_branch_ofs_14 (uint32_t ofs
)
4322 return (ofs
& ((1 << 14) - 1)) << 5;
4325 /* Encode the 16-bit imm field of svc/hvc/smc. */
4326 static inline uint32_t
4327 encode_svc_imm (uint32_t imm
)
4332 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4333 static inline uint32_t
4334 reencode_addsub_switch_add_sub (uint32_t opcode
)
4336 return opcode
^ (1 << 30);
4339 static inline uint32_t
4340 reencode_movzn_to_movz (uint32_t opcode
)
4342 return opcode
| (1 << 30);
4345 static inline uint32_t
4346 reencode_movzn_to_movn (uint32_t opcode
)
4348 return opcode
& ~(1 << 30);
4351 /* Overall per-instruction processing. */
4353 /* We need to be able to fix up arbitrary expressions in some statements.
4354 This is so that we can handle symbols that are an arbitrary distance from
4355 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4356 which returns part of an address in a form which will be valid for
4357 a data instruction. We do this by pushing the expression into a symbol
4358 in the expr_section, and creating a fix for that. */
4361 fix_new_aarch64 (fragS
* frag
,
4376 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4380 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4387 /* Diagnostics on operands errors. */
4389 /* By default, output verbose error message.
4390 Disable the verbose error message by -mno-verbose-error. */
4391 static int verbose_error_p
= 1;
4393 #ifdef DEBUG_AARCH64
4394 /* N.B. this is only for the purpose of debugging. */
4395 const char* operand_mismatch_kind_names
[] =
4398 "AARCH64_OPDE_RECOVERABLE",
4399 "AARCH64_OPDE_SYNTAX_ERROR",
4400 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4401 "AARCH64_OPDE_INVALID_VARIANT",
4402 "AARCH64_OPDE_OUT_OF_RANGE",
4403 "AARCH64_OPDE_UNALIGNED",
4404 "AARCH64_OPDE_REG_LIST",
4405 "AARCH64_OPDE_OTHER_ERROR",
4407 #endif /* DEBUG_AARCH64 */
4409 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4411 When multiple errors of different kinds are found in the same assembly
4412 line, only the error of the highest severity will be picked up for
4413 issuing the diagnostics. */
4415 static inline bfd_boolean
4416 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4417 enum aarch64_operand_error_kind rhs
)
4419 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4420 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4421 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4422 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4423 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4424 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4425 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4426 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4430 /* Helper routine to get the mnemonic name from the assembly instruction
4431 line; should only be called for the diagnosis purpose, as there is
4432 string copy operation involved, which may affect the runtime
4433 performance if used in elsewhere. */
4436 get_mnemonic_name (const char *str
)
4438 static char mnemonic
[32];
4441 /* Get the first 15 bytes and assume that the full name is included. */
4442 strncpy (mnemonic
, str
, 31);
4443 mnemonic
[31] = '\0';
4445 /* Scan up to the end of the mnemonic, which must end in white space,
4446 '.', or end of string. */
4447 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4452 /* Append '...' to the truncated long name. */
4453 if (ptr
- mnemonic
== 31)
4454 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4460 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4462 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4463 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4466 /* Data structures storing one user error in the assembly code related to
4469 struct operand_error_record
4471 const aarch64_opcode
*opcode
;
4472 aarch64_operand_error detail
;
4473 struct operand_error_record
*next
;
4476 typedef struct operand_error_record operand_error_record
;
4478 struct operand_errors
4480 operand_error_record
*head
;
4481 operand_error_record
*tail
;
4484 typedef struct operand_errors operand_errors
;
4486 /* Top-level data structure reporting user errors for the current line of
4488 The way md_assemble works is that all opcodes sharing the same mnemonic
4489 name are iterated to find a match to the assembly line. In this data
4490 structure, each of the such opcodes will have one operand_error_record
4491 allocated and inserted. In other words, excessive errors related with
4492 a single opcode are disregarded. */
4493 operand_errors operand_error_report
;
4495 /* Free record nodes. */
4496 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4498 /* Initialize the data structure that stores the operand mismatch
4499 information on assembling one line of the assembly code. */
4501 init_operand_error_report (void)
4503 if (operand_error_report
.head
!= NULL
)
4505 gas_assert (operand_error_report
.tail
!= NULL
);
4506 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4507 free_opnd_error_record_nodes
= operand_error_report
.head
;
4508 operand_error_report
.head
= NULL
;
4509 operand_error_report
.tail
= NULL
;
4512 gas_assert (operand_error_report
.tail
== NULL
);
4515 /* Return TRUE if some operand error has been recorded during the
4516 parsing of the current assembly line using the opcode *OPCODE;
4517 otherwise return FALSE. */
4518 static inline bfd_boolean
4519 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4521 operand_error_record
*record
= operand_error_report
.head
;
4522 return record
&& record
->opcode
== opcode
;
4525 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4526 OPCODE field is initialized with OPCODE.
4527 N.B. only one record for each opcode, i.e. the maximum of one error is
4528 recorded for each instruction template. */
4531 add_operand_error_record (const operand_error_record
* new_record
)
4533 const aarch64_opcode
*opcode
= new_record
->opcode
;
4534 operand_error_record
* record
= operand_error_report
.head
;
4536 /* The record may have been created for this opcode. If not, we need
4538 if (! opcode_has_operand_error_p (opcode
))
4540 /* Get one empty record. */
4541 if (free_opnd_error_record_nodes
== NULL
)
4543 record
= XNEW (operand_error_record
);
4547 record
= free_opnd_error_record_nodes
;
4548 free_opnd_error_record_nodes
= record
->next
;
4550 record
->opcode
= opcode
;
4551 /* Insert at the head. */
4552 record
->next
= operand_error_report
.head
;
4553 operand_error_report
.head
= record
;
4554 if (operand_error_report
.tail
== NULL
)
4555 operand_error_report
.tail
= record
;
4557 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4558 && record
->detail
.index
<= new_record
->detail
.index
4559 && operand_error_higher_severity_p (record
->detail
.kind
,
4560 new_record
->detail
.kind
))
4562 /* In the case of multiple errors found on operands related with a
4563 single opcode, only record the error of the leftmost operand and
4564 only if the error is of higher severity. */
4565 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4566 " the existing error %s on operand %d",
4567 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4568 new_record
->detail
.index
,
4569 operand_mismatch_kind_names
[record
->detail
.kind
],
4570 record
->detail
.index
);
4574 record
->detail
= new_record
->detail
;
4578 record_operand_error_info (const aarch64_opcode
*opcode
,
4579 aarch64_operand_error
*error_info
)
4581 operand_error_record record
;
4582 record
.opcode
= opcode
;
4583 record
.detail
= *error_info
;
4584 add_operand_error_record (&record
);
4587 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4588 error message *ERROR, for operand IDX (count from 0). */
4591 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4592 enum aarch64_operand_error_kind kind
,
4595 aarch64_operand_error info
;
4596 memset(&info
, 0, sizeof (info
));
4600 info
.non_fatal
= FALSE
;
4601 record_operand_error_info (opcode
, &info
);
4605 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4606 enum aarch64_operand_error_kind kind
,
4607 const char* error
, const int *extra_data
)
4609 aarch64_operand_error info
;
4613 info
.data
[0] = extra_data
[0];
4614 info
.data
[1] = extra_data
[1];
4615 info
.data
[2] = extra_data
[2];
4616 info
.non_fatal
= FALSE
;
4617 record_operand_error_info (opcode
, &info
);
4621 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4622 const char* error
, int lower_bound
,
4625 int data
[3] = {lower_bound
, upper_bound
, 0};
4626 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4630 /* Remove the operand error record for *OPCODE. */
4631 static void ATTRIBUTE_UNUSED
4632 remove_operand_error_record (const aarch64_opcode
*opcode
)
4634 if (opcode_has_operand_error_p (opcode
))
4636 operand_error_record
* record
= operand_error_report
.head
;
4637 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4638 operand_error_report
.head
= record
->next
;
4639 record
->next
= free_opnd_error_record_nodes
;
4640 free_opnd_error_record_nodes
= record
;
4641 if (operand_error_report
.head
== NULL
)
4643 gas_assert (operand_error_report
.tail
== record
);
4644 operand_error_report
.tail
= NULL
;
4649 /* Given the instruction in *INSTR, return the index of the best matched
4650 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4652 Return -1 if there is no qualifier sequence; return the first match
4653 if there is multiple matches found. */
4656 find_best_match (const aarch64_inst
*instr
,
4657 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4659 int i
, num_opnds
, max_num_matched
, idx
;
4661 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4664 DEBUG_TRACE ("no operand");
4668 max_num_matched
= 0;
4671 /* For each pattern. */
4672 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4675 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4677 /* Most opcodes has much fewer patterns in the list. */
4678 if (empty_qualifier_sequence_p (qualifiers
))
4680 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4684 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4685 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4688 if (num_matched
> max_num_matched
)
4690 max_num_matched
= num_matched
;
4695 DEBUG_TRACE ("return with %d", idx
);
4699 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4700 corresponding operands in *INSTR. */
4703 assign_qualifier_sequence (aarch64_inst
*instr
,
4704 const aarch64_opnd_qualifier_t
*qualifiers
)
4707 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4708 gas_assert (num_opnds
);
4709 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4710 instr
->operands
[i
].qualifier
= *qualifiers
;
4713 /* Print operands for the diagnosis purpose. */
4716 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4717 const aarch64_opnd_info
*opnds
)
4721 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4725 /* We regard the opcode operand info more, however we also look into
4726 the inst->operands to support the disassembling of the optional
4728 The two operand code should be the same in all cases, apart from
4729 when the operand can be optional. */
4730 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4731 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4734 /* Generate the operand string in STR. */
4735 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4740 strcat (buf
, i
== 0 ? " " : ", ");
4742 /* Append the operand string. */
4747 /* Send to stderr a string as information. */
4750 output_info (const char *format
, ...)
4756 file
= as_where (&line
);
4760 fprintf (stderr
, "%s:%u: ", file
, line
);
4762 fprintf (stderr
, "%s: ", file
);
4764 fprintf (stderr
, _("Info: "));
4765 va_start (args
, format
);
4766 vfprintf (stderr
, format
, args
);
4768 (void) putc ('\n', stderr
);
4771 /* Output one operand error record. */
4774 output_operand_error_record (const operand_error_record
*record
, char *str
)
4776 const aarch64_operand_error
*detail
= &record
->detail
;
4777 int idx
= detail
->index
;
4778 const aarch64_opcode
*opcode
= record
->opcode
;
4779 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4780 : AARCH64_OPND_NIL
);
4782 typedef void (*handler_t
)(const char *format
, ...);
4783 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4785 switch (detail
->kind
)
4787 case AARCH64_OPDE_NIL
:
4790 case AARCH64_OPDE_SYNTAX_ERROR
:
4791 case AARCH64_OPDE_RECOVERABLE
:
4792 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4793 case AARCH64_OPDE_OTHER_ERROR
:
4794 /* Use the prepared error message if there is, otherwise use the
4795 operand description string to describe the error. */
4796 if (detail
->error
!= NULL
)
4799 handler (_("%s -- `%s'"), detail
->error
, str
);
4801 handler (_("%s at operand %d -- `%s'"),
4802 detail
->error
, idx
+ 1, str
);
4806 gas_assert (idx
>= 0);
4807 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4808 aarch64_get_operand_desc (opd_code
), str
);
4812 case AARCH64_OPDE_INVALID_VARIANT
:
4813 handler (_("operand mismatch -- `%s'"), str
);
4814 if (verbose_error_p
)
4816 /* We will try to correct the erroneous instruction and also provide
4817 more information e.g. all other valid variants.
4819 The string representation of the corrected instruction and other
4820 valid variants are generated by
4822 1) obtaining the intermediate representation of the erroneous
4824 2) manipulating the IR, e.g. replacing the operand qualifier;
4825 3) printing out the instruction by calling the printer functions
4826 shared with the disassembler.
4828 The limitation of this method is that the exact input assembly
4829 line cannot be accurately reproduced in some cases, for example an
4830 optional operand present in the actual assembly line will be
4831 omitted in the output; likewise for the optional syntax rules,
4832 e.g. the # before the immediate. Another limitation is that the
4833 assembly symbols and relocation operations in the assembly line
4834 currently cannot be printed out in the error report. Last but not
4835 least, when there is other error(s) co-exist with this error, the
4836 'corrected' instruction may be still incorrect, e.g. given
4837 'ldnp h0,h1,[x0,#6]!'
4838 this diagnosis will provide the version:
4839 'ldnp s0,s1,[x0,#6]!'
4840 which is still not right. */
4841 size_t len
= strlen (get_mnemonic_name (str
));
4845 aarch64_inst
*inst_base
= &inst
.base
;
4846 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4849 reset_aarch64_instruction (&inst
);
4850 inst_base
->opcode
= opcode
;
4852 /* Reset the error report so that there is no side effect on the
4853 following operand parsing. */
4854 init_operand_error_report ();
4857 result
= parse_operands (str
+ len
, opcode
)
4858 && programmer_friendly_fixup (&inst
);
4859 gas_assert (result
);
4860 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4861 NULL
, NULL
, insn_sequence
);
4862 gas_assert (!result
);
4864 /* Find the most matched qualifier sequence. */
4865 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4866 gas_assert (qlf_idx
> -1);
4868 /* Assign the qualifiers. */
4869 assign_qualifier_sequence (inst_base
,
4870 opcode
->qualifiers_list
[qlf_idx
]);
4872 /* Print the hint. */
4873 output_info (_(" did you mean this?"));
4874 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4875 print_operands (buf
, opcode
, inst_base
->operands
);
4876 output_info (_(" %s"), buf
);
4878 /* Print out other variant(s) if there is any. */
4880 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4881 output_info (_(" other valid variant(s):"));
4883 /* For each pattern. */
4884 qualifiers_list
= opcode
->qualifiers_list
;
4885 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4887 /* Most opcodes has much fewer patterns in the list.
4888 First NIL qualifier indicates the end in the list. */
4889 if (empty_qualifier_sequence_p (*qualifiers_list
))
4894 /* Mnemonics name. */
4895 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4897 /* Assign the qualifiers. */
4898 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4900 /* Print instruction. */
4901 print_operands (buf
, opcode
, inst_base
->operands
);
4903 output_info (_(" %s"), buf
);
4909 case AARCH64_OPDE_UNTIED_OPERAND
:
4910 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4911 detail
->index
+ 1, str
);
4914 case AARCH64_OPDE_OUT_OF_RANGE
:
4915 if (detail
->data
[0] != detail
->data
[1])
4916 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4917 detail
->error
? detail
->error
: _("immediate value"),
4918 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4920 handler (_("%s must be %d at operand %d -- `%s'"),
4921 detail
->error
? detail
->error
: _("immediate value"),
4922 detail
->data
[0], idx
+ 1, str
);
4925 case AARCH64_OPDE_REG_LIST
:
4926 if (detail
->data
[0] == 1)
4927 handler (_("invalid number of registers in the list; "
4928 "only 1 register is expected at operand %d -- `%s'"),
4931 handler (_("invalid number of registers in the list; "
4932 "%d registers are expected at operand %d -- `%s'"),
4933 detail
->data
[0], idx
+ 1, str
);
4936 case AARCH64_OPDE_UNALIGNED
:
4937 handler (_("immediate value must be a multiple of "
4938 "%d at operand %d -- `%s'"),
4939 detail
->data
[0], idx
+ 1, str
);
4948 /* Process and output the error message about the operand mismatching.
4950 When this function is called, the operand error information had
4951 been collected for an assembly line and there will be multiple
4952 errors in the case of multiple instruction templates; output the
4953 error message that most closely describes the problem.
4955 The errors to be printed can be filtered on printing all errors
4956 or only non-fatal errors. This distinction has to be made because
4957 the error buffer may already be filled with fatal errors we don't want to
4958 print due to the different instruction templates. */
4961 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4963 int largest_error_pos
;
4964 const char *msg
= NULL
;
4965 enum aarch64_operand_error_kind kind
;
4966 operand_error_record
*curr
;
4967 operand_error_record
*head
= operand_error_report
.head
;
4968 operand_error_record
*record
= NULL
;
4970 /* No error to report. */
4974 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4976 /* Only one error. */
4977 if (head
== operand_error_report
.tail
)
4979 /* If the only error is a non-fatal one and we don't want to print it,
4981 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4983 DEBUG_TRACE ("single opcode entry with error kind: %s",
4984 operand_mismatch_kind_names
[head
->detail
.kind
]);
4985 output_operand_error_record (head
, str
);
4990 /* Find the error kind of the highest severity. */
4991 DEBUG_TRACE ("multiple opcode entries with error kind");
4992 kind
= AARCH64_OPDE_NIL
;
4993 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4995 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4996 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4997 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4998 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4999 kind
= curr
->detail
.kind
;
5002 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5004 /* Pick up one of errors of KIND to report. */
5005 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5006 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5008 /* If we don't want to print non-fatal errors then don't consider them
5010 if (curr
->detail
.kind
!= kind
5011 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5013 /* If there are multiple errors, pick up the one with the highest
5014 mismatching operand index. In the case of multiple errors with
5015 the equally highest operand index, pick up the first one or the
5016 first one with non-NULL error message. */
5017 if (curr
->detail
.index
> largest_error_pos
5018 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5019 && curr
->detail
.error
!= NULL
))
5021 largest_error_pos
= curr
->detail
.index
;
5023 msg
= record
->detail
.error
;
5027 /* The way errors are collected in the back-end is a bit non-intuitive. But
5028 essentially, because each operand template is tried recursively you may
5029 always have errors collected from the previous tried OPND. These are
5030 usually skipped if there is one successful match. However now with the
5031 non-fatal errors we have to ignore those previously collected hard errors
5032 when we're only interested in printing the non-fatal ones. This condition
5033 prevents us from printing errors that are not appropriate, since we did
5034 match a condition, but it also has warnings that it wants to print. */
5035 if (non_fatal_only
&& !record
)
5038 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5039 DEBUG_TRACE ("Pick up error kind %s to report",
5040 operand_mismatch_kind_names
[record
->detail
.kind
]);
5043 output_operand_error_record (record
, str
);
5046 /* Write an AARCH64 instruction to buf - always little-endian. */
5048 put_aarch64_insn (char *buf
, uint32_t insn
)
5050 unsigned char *where
= (unsigned char *) buf
;
5052 where
[1] = insn
>> 8;
5053 where
[2] = insn
>> 16;
5054 where
[3] = insn
>> 24;
5058 get_aarch64_insn (char *buf
)
5060 unsigned char *where
= (unsigned char *) buf
;
5062 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5063 | ((uint32_t) where
[3] << 24)));
5068 output_inst (struct aarch64_inst
*new_inst
)
5072 to
= frag_more (INSN_SIZE
);
5074 frag_now
->tc_frag_data
.recorded
= 1;
5076 put_aarch64_insn (to
, inst
.base
.value
);
5078 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5080 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5081 INSN_SIZE
, &inst
.reloc
.exp
,
5084 DEBUG_TRACE ("Prepared relocation fix up");
5085 /* Don't check the addend value against the instruction size,
5086 that's the job of our code in md_apply_fix(). */
5087 fixp
->fx_no_overflow
= 1;
5088 if (new_inst
!= NULL
)
5089 fixp
->tc_fix_data
.inst
= new_inst
;
5090 if (aarch64_gas_internal_fixup_p ())
5092 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5093 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5094 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5098 dwarf2_emit_insn (INSN_SIZE
);
5101 /* Link together opcodes of the same name. */
5105 aarch64_opcode
*opcode
;
5106 struct templates
*next
;
5109 typedef struct templates templates
;
5112 lookup_mnemonic (const char *start
, int len
)
5114 templates
*templ
= NULL
;
5116 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5120 /* Subroutine of md_assemble, responsible for looking up the primary
5121 opcode from the mnemonic the user wrote. STR points to the
5122 beginning of the mnemonic. */
5125 opcode_lookup (char **str
)
5127 char *end
, *base
, *dot
;
5128 const aarch64_cond
*cond
;
5132 /* Scan up to the end of the mnemonic, which must end in white space,
5133 '.', or end of string. */
5135 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5136 if (*end
== '.' && !dot
)
5139 if (end
== base
|| dot
== base
)
5142 inst
.cond
= COND_ALWAYS
;
5144 /* Handle a possible condition. */
5147 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5150 inst
.cond
= cond
->value
;
5166 if (inst
.cond
== COND_ALWAYS
)
5168 /* Look for unaffixed mnemonic. */
5169 return lookup_mnemonic (base
, len
);
5173 /* append ".c" to mnemonic if conditional */
5174 memcpy (condname
, base
, len
);
5175 memcpy (condname
+ len
, ".c", 2);
5178 return lookup_mnemonic (base
, len
);
5184 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5185 to a corresponding operand qualifier. */
5187 static inline aarch64_opnd_qualifier_t
5188 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5190 /* Element size in bytes indexed by vector_el_type. */
5191 const unsigned char ele_size
[5]
5193 const unsigned int ele_base
[5] =
5195 AARCH64_OPND_QLF_V_4B
,
5196 AARCH64_OPND_QLF_V_2H
,
5197 AARCH64_OPND_QLF_V_2S
,
5198 AARCH64_OPND_QLF_V_1D
,
5199 AARCH64_OPND_QLF_V_1Q
5202 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5203 goto vectype_conversion_fail
;
5205 if (vectype
->type
== NT_zero
)
5206 return AARCH64_OPND_QLF_P_Z
;
5207 if (vectype
->type
== NT_merge
)
5208 return AARCH64_OPND_QLF_P_M
;
5210 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5212 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5214 /* Special case S_4B. */
5215 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5216 return AARCH64_OPND_QLF_S_4B
;
5218 /* Special case S_2H. */
5219 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5220 return AARCH64_OPND_QLF_S_2H
;
5222 /* Vector element register. */
5223 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5227 /* Vector register. */
5228 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5231 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5232 goto vectype_conversion_fail
;
5234 /* The conversion is by calculating the offset from the base operand
5235 qualifier for the vector type. The operand qualifiers are regular
5236 enough that the offset can established by shifting the vector width by
5237 a vector-type dependent amount. */
5239 if (vectype
->type
== NT_b
)
5241 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5243 else if (vectype
->type
>= NT_d
)
5248 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5249 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5250 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5254 vectype_conversion_fail
:
5255 first_error (_("bad vector arrangement type"));
5256 return AARCH64_OPND_QLF_NIL
;
5259 /* Process an optional operand that is found omitted from the assembly line.
5260 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5261 instruction's opcode entry while IDX is the index of this omitted operand.
5265 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5266 int idx
, aarch64_opnd_info
*operand
)
5268 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5269 gas_assert (optional_operand_p (opcode
, idx
));
5270 gas_assert (!operand
->present
);
5274 case AARCH64_OPND_Rd
:
5275 case AARCH64_OPND_Rn
:
5276 case AARCH64_OPND_Rm
:
5277 case AARCH64_OPND_Rt
:
5278 case AARCH64_OPND_Rt2
:
5279 case AARCH64_OPND_Rt_LS64
:
5280 case AARCH64_OPND_Rt_SP
:
5281 case AARCH64_OPND_Rs
:
5282 case AARCH64_OPND_Ra
:
5283 case AARCH64_OPND_Rt_SYS
:
5284 case AARCH64_OPND_Rd_SP
:
5285 case AARCH64_OPND_Rn_SP
:
5286 case AARCH64_OPND_Rm_SP
:
5287 case AARCH64_OPND_Fd
:
5288 case AARCH64_OPND_Fn
:
5289 case AARCH64_OPND_Fm
:
5290 case AARCH64_OPND_Fa
:
5291 case AARCH64_OPND_Ft
:
5292 case AARCH64_OPND_Ft2
:
5293 case AARCH64_OPND_Sd
:
5294 case AARCH64_OPND_Sn
:
5295 case AARCH64_OPND_Sm
:
5296 case AARCH64_OPND_Va
:
5297 case AARCH64_OPND_Vd
:
5298 case AARCH64_OPND_Vn
:
5299 case AARCH64_OPND_Vm
:
5300 case AARCH64_OPND_VdD1
:
5301 case AARCH64_OPND_VnD1
:
5302 operand
->reg
.regno
= default_value
;
5305 case AARCH64_OPND_Ed
:
5306 case AARCH64_OPND_En
:
5307 case AARCH64_OPND_Em
:
5308 case AARCH64_OPND_Em16
:
5309 case AARCH64_OPND_SM3_IMM2
:
5310 operand
->reglane
.regno
= default_value
;
5313 case AARCH64_OPND_IDX
:
5314 case AARCH64_OPND_BIT_NUM
:
5315 case AARCH64_OPND_IMMR
:
5316 case AARCH64_OPND_IMMS
:
5317 case AARCH64_OPND_SHLL_IMM
:
5318 case AARCH64_OPND_IMM_VLSL
:
5319 case AARCH64_OPND_IMM_VLSR
:
5320 case AARCH64_OPND_CCMP_IMM
:
5321 case AARCH64_OPND_FBITS
:
5322 case AARCH64_OPND_UIMM4
:
5323 case AARCH64_OPND_UIMM3_OP1
:
5324 case AARCH64_OPND_UIMM3_OP2
:
5325 case AARCH64_OPND_IMM
:
5326 case AARCH64_OPND_IMM_2
:
5327 case AARCH64_OPND_WIDTH
:
5328 case AARCH64_OPND_UIMM7
:
5329 case AARCH64_OPND_NZCV
:
5330 case AARCH64_OPND_SVE_PATTERN
:
5331 case AARCH64_OPND_SVE_PRFOP
:
5332 operand
->imm
.value
= default_value
;
5335 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5336 operand
->imm
.value
= default_value
;
5337 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5338 operand
->shifter
.amount
= 1;
5341 case AARCH64_OPND_EXCEPTION
:
5342 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5345 case AARCH64_OPND_BARRIER_ISB
:
5346 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5349 case AARCH64_OPND_BTI_TARGET
:
5350 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5358 /* Process the relocation type for move wide instructions.
5359 Return TRUE on success; otherwise return FALSE. */
5362 process_movw_reloc_info (void)
5367 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5369 if (inst
.base
.opcode
->op
== OP_MOVK
)
5370 switch (inst
.reloc
.type
)
5372 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5373 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5374 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5375 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5376 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5377 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5378 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5379 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5380 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5381 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5382 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5384 (_("the specified relocation type is not allowed for MOVK"));
5390 switch (inst
.reloc
.type
)
5392 case BFD_RELOC_AARCH64_MOVW_G0
:
5393 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5394 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5395 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5396 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5397 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5398 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5399 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5400 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5401 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5402 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5403 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5404 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5407 case BFD_RELOC_AARCH64_MOVW_G1
:
5408 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5409 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5410 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5411 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5412 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5413 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5414 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5415 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5416 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5417 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5418 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5419 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5422 case BFD_RELOC_AARCH64_MOVW_G2
:
5423 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5424 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5425 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5426 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5427 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5428 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5431 set_fatal_syntax_error
5432 (_("the specified relocation type is not allowed for 32-bit "
5438 case BFD_RELOC_AARCH64_MOVW_G3
:
5439 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5442 set_fatal_syntax_error
5443 (_("the specified relocation type is not allowed for 32-bit "
5450 /* More cases should be added when more MOVW-related relocation types
5451 are supported in GAS. */
5452 gas_assert (aarch64_gas_internal_fixup_p ());
5453 /* The shift amount should have already been set by the parser. */
5456 inst
.base
.operands
[1].shifter
.amount
= shift
;
5460 /* A primitive log calculator. */
5462 static inline unsigned int
5463 get_logsz (unsigned int size
)
5465 const unsigned char ls
[16] =
5466 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5472 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5473 return ls
[size
- 1];
5476 /* Determine and return the real reloc type code for an instruction
5477 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5479 static inline bfd_reloc_code_real_type
5480 ldst_lo12_determine_real_reloc_type (void)
5483 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5484 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5486 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5488 BFD_RELOC_AARCH64_LDST8_LO12
,
5489 BFD_RELOC_AARCH64_LDST16_LO12
,
5490 BFD_RELOC_AARCH64_LDST32_LO12
,
5491 BFD_RELOC_AARCH64_LDST64_LO12
,
5492 BFD_RELOC_AARCH64_LDST128_LO12
5495 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5496 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5497 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5498 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5499 BFD_RELOC_AARCH64_NONE
5502 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5503 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5504 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5505 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5506 BFD_RELOC_AARCH64_NONE
5509 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5510 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5511 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5512 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5513 BFD_RELOC_AARCH64_NONE
5516 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5517 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5518 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5519 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5520 BFD_RELOC_AARCH64_NONE
5524 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5525 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5527 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5529 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5531 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5532 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5534 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5536 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5538 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5540 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5541 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5542 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5543 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5544 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5545 gas_assert (logsz
<= 3);
5547 gas_assert (logsz
<= 4);
5549 /* In reloc.c, these pseudo relocation types should be defined in similar
5550 order as above reloc_ldst_lo12 array. Because the array index calculation
5551 below relies on this. */
5552 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5555 /* Check whether a register list REGINFO is valid. The registers must be
5556 numbered in increasing order (modulo 32), in increments of one or two.
5558 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5561 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5564 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5566 uint32_t i
, nb_regs
, prev_regno
, incr
;
5568 nb_regs
= 1 + (reginfo
& 0x3);
5570 prev_regno
= reginfo
& 0x1f;
5571 incr
= accept_alternate
? 2 : 1;
5573 for (i
= 1; i
< nb_regs
; ++i
)
5575 uint32_t curr_regno
;
5577 curr_regno
= reginfo
& 0x1f;
5578 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5580 prev_regno
= curr_regno
;
5586 /* Generic instruction operand parser. This does no encoding and no
5587 semantic validation; it merely squirrels values away in the inst
5588 structure. Returns TRUE or FALSE depending on whether the
5589 specified grammar matched. */
5592 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5595 char *backtrack_pos
= 0;
5596 const enum aarch64_opnd
*operands
= opcode
->operands
;
5597 aarch64_reg_type imm_reg_type
;
5600 skip_whitespace (str
);
5602 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5603 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5605 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5607 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5610 const reg_entry
*reg
;
5611 int comma_skipped_p
= 0;
5612 aarch64_reg_type rtype
;
5613 struct vector_type_el vectype
;
5614 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5615 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5616 aarch64_reg_type reg_type
;
5618 DEBUG_TRACE ("parse operand %d", i
);
5620 /* Assign the operand code. */
5621 info
->type
= operands
[i
];
5623 if (optional_operand_p (opcode
, i
))
5625 /* Remember where we are in case we need to backtrack. */
5626 gas_assert (!backtrack_pos
);
5627 backtrack_pos
= str
;
5630 /* Expect comma between operands; the backtrack mechanism will take
5631 care of cases of omitted optional operand. */
5632 if (i
> 0 && ! skip_past_char (&str
, ','))
5634 set_syntax_error (_("comma expected between operands"));
5638 comma_skipped_p
= 1;
5640 switch (operands
[i
])
5642 case AARCH64_OPND_Rd
:
5643 case AARCH64_OPND_Rn
:
5644 case AARCH64_OPND_Rm
:
5645 case AARCH64_OPND_Rt
:
5646 case AARCH64_OPND_Rt2
:
5647 case AARCH64_OPND_Rs
:
5648 case AARCH64_OPND_Ra
:
5649 case AARCH64_OPND_Rt_LS64
:
5650 case AARCH64_OPND_Rt_SYS
:
5651 case AARCH64_OPND_PAIRREG
:
5652 case AARCH64_OPND_SVE_Rm
:
5653 po_int_reg_or_fail (REG_TYPE_R_Z
);
5655 /* In LS64 load/store instructions Rt register number must be even
5657 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
5659 /* We've already checked if this is valid register.
5660 This will check if register number (Rt) is not undefined for LS64
5662 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
5663 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
5665 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
5671 case AARCH64_OPND_Rd_SP
:
5672 case AARCH64_OPND_Rn_SP
:
5673 case AARCH64_OPND_Rt_SP
:
5674 case AARCH64_OPND_SVE_Rn_SP
:
5675 case AARCH64_OPND_Rm_SP
:
5676 po_int_reg_or_fail (REG_TYPE_R_SP
);
5679 case AARCH64_OPND_Rm_EXT
:
5680 case AARCH64_OPND_Rm_SFT
:
5681 po_misc_or_fail (parse_shifter_operand
5682 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5684 : SHIFTED_LOGIC_IMM
)));
5685 if (!info
->shifter
.operator_present
)
5687 /* Default to LSL if not present. Libopcodes prefers shifter
5688 kind to be explicit. */
5689 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5690 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5691 /* For Rm_EXT, libopcodes will carry out further check on whether
5692 or not stack pointer is used in the instruction (Recall that
5693 "the extend operator is not optional unless at least one of
5694 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5698 case AARCH64_OPND_Fd
:
5699 case AARCH64_OPND_Fn
:
5700 case AARCH64_OPND_Fm
:
5701 case AARCH64_OPND_Fa
:
5702 case AARCH64_OPND_Ft
:
5703 case AARCH64_OPND_Ft2
:
5704 case AARCH64_OPND_Sd
:
5705 case AARCH64_OPND_Sn
:
5706 case AARCH64_OPND_Sm
:
5707 case AARCH64_OPND_SVE_VZn
:
5708 case AARCH64_OPND_SVE_Vd
:
5709 case AARCH64_OPND_SVE_Vm
:
5710 case AARCH64_OPND_SVE_Vn
:
5711 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5712 if (val
== PARSE_FAIL
)
5714 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5717 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5719 info
->reg
.regno
= val
;
5720 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5723 case AARCH64_OPND_SVE_Pd
:
5724 case AARCH64_OPND_SVE_Pg3
:
5725 case AARCH64_OPND_SVE_Pg4_5
:
5726 case AARCH64_OPND_SVE_Pg4_10
:
5727 case AARCH64_OPND_SVE_Pg4_16
:
5728 case AARCH64_OPND_SVE_Pm
:
5729 case AARCH64_OPND_SVE_Pn
:
5730 case AARCH64_OPND_SVE_Pt
:
5731 reg_type
= REG_TYPE_PN
;
5734 case AARCH64_OPND_SVE_Za_5
:
5735 case AARCH64_OPND_SVE_Za_16
:
5736 case AARCH64_OPND_SVE_Zd
:
5737 case AARCH64_OPND_SVE_Zm_5
:
5738 case AARCH64_OPND_SVE_Zm_16
:
5739 case AARCH64_OPND_SVE_Zn
:
5740 case AARCH64_OPND_SVE_Zt
:
5741 reg_type
= REG_TYPE_ZN
;
5744 case AARCH64_OPND_Va
:
5745 case AARCH64_OPND_Vd
:
5746 case AARCH64_OPND_Vn
:
5747 case AARCH64_OPND_Vm
:
5748 reg_type
= REG_TYPE_VN
;
5750 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5751 if (val
== PARSE_FAIL
)
5753 first_error (_(get_reg_expected_msg (reg_type
)));
5756 if (vectype
.defined
& NTA_HASINDEX
)
5759 info
->reg
.regno
= val
;
5760 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5761 && vectype
.type
== NT_invtype
)
5762 /* Unqualified Pn and Zn registers are allowed in certain
5763 contexts. Rely on F_STRICT qualifier checking to catch
5765 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5768 info
->qualifier
= vectype_to_qualifier (&vectype
);
5769 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5774 case AARCH64_OPND_VdD1
:
5775 case AARCH64_OPND_VnD1
:
5776 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5777 if (val
== PARSE_FAIL
)
5779 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5782 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5784 set_fatal_syntax_error
5785 (_("the top half of a 128-bit FP/SIMD register is expected"));
5788 info
->reg
.regno
= val
;
5789 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5790 here; it is correct for the purpose of encoding/decoding since
5791 only the register number is explicitly encoded in the related
5792 instructions, although this appears a bit hacky. */
5793 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5796 case AARCH64_OPND_SVE_Zm3_INDEX
:
5797 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5798 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5799 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5800 case AARCH64_OPND_SVE_Zm4_INDEX
:
5801 case AARCH64_OPND_SVE_Zn_INDEX
:
5802 reg_type
= REG_TYPE_ZN
;
5803 goto vector_reg_index
;
5805 case AARCH64_OPND_Ed
:
5806 case AARCH64_OPND_En
:
5807 case AARCH64_OPND_Em
:
5808 case AARCH64_OPND_Em16
:
5809 case AARCH64_OPND_SM3_IMM2
:
5810 reg_type
= REG_TYPE_VN
;
5812 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5813 if (val
== PARSE_FAIL
)
5815 first_error (_(get_reg_expected_msg (reg_type
)));
5818 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5821 info
->reglane
.regno
= val
;
5822 info
->reglane
.index
= vectype
.index
;
5823 info
->qualifier
= vectype_to_qualifier (&vectype
);
5824 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5828 case AARCH64_OPND_SVE_ZnxN
:
5829 case AARCH64_OPND_SVE_ZtxN
:
5830 reg_type
= REG_TYPE_ZN
;
5831 goto vector_reg_list
;
5833 case AARCH64_OPND_LVn
:
5834 case AARCH64_OPND_LVt
:
5835 case AARCH64_OPND_LVt_AL
:
5836 case AARCH64_OPND_LEt
:
5837 reg_type
= REG_TYPE_VN
;
5839 if (reg_type
== REG_TYPE_ZN
5840 && get_opcode_dependent_value (opcode
) == 1
5843 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5844 if (val
== PARSE_FAIL
)
5846 first_error (_(get_reg_expected_msg (reg_type
)));
5849 info
->reglist
.first_regno
= val
;
5850 info
->reglist
.num_regs
= 1;
5854 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5855 if (val
== PARSE_FAIL
)
5858 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5860 set_fatal_syntax_error (_("invalid register list"));
5864 if (vectype
.width
!= 0 && *str
!= ',')
5866 set_fatal_syntax_error
5867 (_("expected element type rather than vector type"));
5871 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5872 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5874 if (operands
[i
] == AARCH64_OPND_LEt
)
5876 if (!(vectype
.defined
& NTA_HASINDEX
))
5878 info
->reglist
.has_index
= 1;
5879 info
->reglist
.index
= vectype
.index
;
5883 if (vectype
.defined
& NTA_HASINDEX
)
5885 if (!(vectype
.defined
& NTA_HASTYPE
))
5887 if (reg_type
== REG_TYPE_ZN
)
5888 set_fatal_syntax_error (_("missing type suffix"));
5892 info
->qualifier
= vectype_to_qualifier (&vectype
);
5893 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5897 case AARCH64_OPND_CRn
:
5898 case AARCH64_OPND_CRm
:
5900 char prefix
= *(str
++);
5901 if (prefix
!= 'c' && prefix
!= 'C')
5904 po_imm_nc_or_fail ();
5907 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5910 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5911 info
->imm
.value
= val
;
5915 case AARCH64_OPND_SHLL_IMM
:
5916 case AARCH64_OPND_IMM_VLSR
:
5917 po_imm_or_fail (1, 64);
5918 info
->imm
.value
= val
;
5921 case AARCH64_OPND_CCMP_IMM
:
5922 case AARCH64_OPND_SIMM5
:
5923 case AARCH64_OPND_FBITS
:
5924 case AARCH64_OPND_TME_UIMM16
:
5925 case AARCH64_OPND_UIMM4
:
5926 case AARCH64_OPND_UIMM4_ADDG
:
5927 case AARCH64_OPND_UIMM10
:
5928 case AARCH64_OPND_UIMM3_OP1
:
5929 case AARCH64_OPND_UIMM3_OP2
:
5930 case AARCH64_OPND_IMM_VLSL
:
5931 case AARCH64_OPND_IMM
:
5932 case AARCH64_OPND_IMM_2
:
5933 case AARCH64_OPND_WIDTH
:
5934 case AARCH64_OPND_SVE_INV_LIMM
:
5935 case AARCH64_OPND_SVE_LIMM
:
5936 case AARCH64_OPND_SVE_LIMM_MOV
:
5937 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5938 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5939 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
5940 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5941 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5942 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
5943 case AARCH64_OPND_SVE_SIMM5
:
5944 case AARCH64_OPND_SVE_SIMM5B
:
5945 case AARCH64_OPND_SVE_SIMM6
:
5946 case AARCH64_OPND_SVE_SIMM8
:
5947 case AARCH64_OPND_SVE_UIMM3
:
5948 case AARCH64_OPND_SVE_UIMM7
:
5949 case AARCH64_OPND_SVE_UIMM8
:
5950 case AARCH64_OPND_SVE_UIMM8_53
:
5951 case AARCH64_OPND_IMM_ROT1
:
5952 case AARCH64_OPND_IMM_ROT2
:
5953 case AARCH64_OPND_IMM_ROT3
:
5954 case AARCH64_OPND_SVE_IMM_ROT1
:
5955 case AARCH64_OPND_SVE_IMM_ROT2
:
5956 case AARCH64_OPND_SVE_IMM_ROT3
:
5957 po_imm_nc_or_fail ();
5958 info
->imm
.value
= val
;
5961 case AARCH64_OPND_SVE_AIMM
:
5962 case AARCH64_OPND_SVE_ASIMM
:
5963 po_imm_nc_or_fail ();
5964 info
->imm
.value
= val
;
5965 skip_whitespace (str
);
5966 if (skip_past_comma (&str
))
5967 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5969 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5972 case AARCH64_OPND_SVE_PATTERN
:
5973 po_enum_or_fail (aarch64_sve_pattern_array
);
5974 info
->imm
.value
= val
;
5977 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5978 po_enum_or_fail (aarch64_sve_pattern_array
);
5979 info
->imm
.value
= val
;
5980 if (skip_past_comma (&str
)
5981 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5983 if (!info
->shifter
.operator_present
)
5985 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5986 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5987 info
->shifter
.amount
= 1;
5991 case AARCH64_OPND_SVE_PRFOP
:
5992 po_enum_or_fail (aarch64_sve_prfop_array
);
5993 info
->imm
.value
= val
;
5996 case AARCH64_OPND_UIMM7
:
5997 po_imm_or_fail (0, 127);
5998 info
->imm
.value
= val
;
6001 case AARCH64_OPND_IDX
:
6002 case AARCH64_OPND_MASK
:
6003 case AARCH64_OPND_BIT_NUM
:
6004 case AARCH64_OPND_IMMR
:
6005 case AARCH64_OPND_IMMS
:
6006 po_imm_or_fail (0, 63);
6007 info
->imm
.value
= val
;
6010 case AARCH64_OPND_IMM0
:
6011 po_imm_nc_or_fail ();
6014 set_fatal_syntax_error (_("immediate zero expected"));
6017 info
->imm
.value
= 0;
6020 case AARCH64_OPND_FPIMM0
:
6023 bfd_boolean res1
= FALSE
, res2
= FALSE
;
6024 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6025 it is probably not worth the effort to support it. */
6026 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
6029 || !(res2
= parse_constant_immediate (&str
, &val
,
6032 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6034 info
->imm
.value
= 0;
6035 info
->imm
.is_fp
= 1;
6038 set_fatal_syntax_error (_("immediate zero expected"));
6042 case AARCH64_OPND_IMM_MOV
:
6045 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6046 reg_name_p (str
, REG_TYPE_VN
))
6049 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6051 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6052 later. fix_mov_imm_insn will try to determine a machine
6053 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6054 message if the immediate cannot be moved by a single
6056 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6057 inst
.base
.operands
[i
].skip
= 1;
6061 case AARCH64_OPND_SIMD_IMM
:
6062 case AARCH64_OPND_SIMD_IMM_SFT
:
6063 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6065 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6067 /* need_libopcodes_p */ 1,
6070 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6071 shift, we don't check it here; we leave the checking to
6072 the libopcodes (operand_general_constraint_met_p). By
6073 doing this, we achieve better diagnostics. */
6074 if (skip_past_comma (&str
)
6075 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6077 if (!info
->shifter
.operator_present
6078 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6080 /* Default to LSL if not present. Libopcodes prefers shifter
6081 kind to be explicit. */
6082 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6083 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6087 case AARCH64_OPND_FPIMM
:
6088 case AARCH64_OPND_SIMD_FPIMM
:
6089 case AARCH64_OPND_SVE_FPIMM8
:
6094 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6095 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6096 || !aarch64_imm_float_p (qfloat
))
6099 set_fatal_syntax_error (_("invalid floating-point"
6103 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6104 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6108 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6109 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6110 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6115 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6116 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6119 set_fatal_syntax_error (_("invalid floating-point"
6123 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6124 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6128 case AARCH64_OPND_LIMM
:
6129 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6130 SHIFTED_LOGIC_IMM
));
6131 if (info
->shifter
.operator_present
)
6133 set_fatal_syntax_error
6134 (_("shift not allowed for bitmask immediate"));
6137 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6139 /* need_libopcodes_p */ 1,
6143 case AARCH64_OPND_AIMM
:
6144 if (opcode
->op
== OP_ADD
)
6145 /* ADD may have relocation types. */
6146 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6147 SHIFTED_ARITH_IMM
));
6149 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6150 SHIFTED_ARITH_IMM
));
6151 switch (inst
.reloc
.type
)
6153 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6154 info
->shifter
.amount
= 12;
6156 case BFD_RELOC_UNUSED
:
6157 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6158 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6159 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6160 inst
.reloc
.pc_rel
= 0;
6165 info
->imm
.value
= 0;
6166 if (!info
->shifter
.operator_present
)
6168 /* Default to LSL if not present. Libopcodes prefers shifter
6169 kind to be explicit. */
6170 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6171 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6175 case AARCH64_OPND_HALF
:
6177 /* #<imm16> or relocation. */
6178 int internal_fixup_p
;
6179 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6180 if (internal_fixup_p
)
6181 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6182 skip_whitespace (str
);
6183 if (skip_past_comma (&str
))
6185 /* {, LSL #<shift>} */
6186 if (! aarch64_gas_internal_fixup_p ())
6188 set_fatal_syntax_error (_("can't mix relocation modifier "
6189 "with explicit shift"));
6192 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6195 inst
.base
.operands
[i
].shifter
.amount
= 0;
6196 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6197 inst
.base
.operands
[i
].imm
.value
= 0;
6198 if (! process_movw_reloc_info ())
6203 case AARCH64_OPND_EXCEPTION
:
6204 case AARCH64_OPND_UNDEFINED
:
6205 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6207 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6209 /* need_libopcodes_p */ 0,
6213 case AARCH64_OPND_NZCV
:
6215 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6219 info
->imm
.value
= nzcv
->value
;
6222 po_imm_or_fail (0, 15);
6223 info
->imm
.value
= val
;
6227 case AARCH64_OPND_COND
:
6228 case AARCH64_OPND_COND1
:
6233 while (ISALPHA (*str
));
6234 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6235 if (info
->cond
== NULL
)
6237 set_syntax_error (_("invalid condition"));
6240 else if (operands
[i
] == AARCH64_OPND_COND1
6241 && (info
->cond
->value
& 0xe) == 0xe)
6243 /* Do not allow AL or NV. */
6244 set_default_error ();
6250 case AARCH64_OPND_ADDR_ADRP
:
6251 po_misc_or_fail (parse_adrp (&str
));
6252 /* Clear the value as operand needs to be relocated. */
6253 info
->imm
.value
= 0;
6256 case AARCH64_OPND_ADDR_PCREL14
:
6257 case AARCH64_OPND_ADDR_PCREL19
:
6258 case AARCH64_OPND_ADDR_PCREL21
:
6259 case AARCH64_OPND_ADDR_PCREL26
:
6260 po_misc_or_fail (parse_address (&str
, info
));
6261 if (!info
->addr
.pcrel
)
6263 set_syntax_error (_("invalid pc-relative address"));
6266 if (inst
.gen_lit_pool
6267 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6269 /* Only permit "=value" in the literal load instructions.
6270 The literal will be generated by programmer_friendly_fixup. */
6271 set_syntax_error (_("invalid use of \"=immediate\""));
6274 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6276 set_syntax_error (_("unrecognized relocation suffix"));
6279 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6281 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6282 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6286 info
->imm
.value
= 0;
6287 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6288 switch (opcode
->iclass
)
6292 /* e.g. CBZ or B.COND */
6293 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6294 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6298 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6299 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6303 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6305 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6306 : BFD_RELOC_AARCH64_JUMP26
;
6309 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6310 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6313 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6314 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6320 inst
.reloc
.pc_rel
= 1;
6324 case AARCH64_OPND_ADDR_SIMPLE
:
6325 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6327 /* [<Xn|SP>{, #<simm>}] */
6329 /* First use the normal address-parsing routines, to get
6330 the usual syntax errors. */
6331 po_misc_or_fail (parse_address (&str
, info
));
6332 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6333 || !info
->addr
.preind
|| info
->addr
.postind
6334 || info
->addr
.writeback
)
6336 set_syntax_error (_("invalid addressing mode"));
6340 /* Then retry, matching the specific syntax of these addresses. */
6342 po_char_or_fail ('[');
6343 po_reg_or_fail (REG_TYPE_R64_SP
);
6344 /* Accept optional ", #0". */
6345 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6346 && skip_past_char (&str
, ','))
6348 skip_past_char (&str
, '#');
6349 if (! skip_past_char (&str
, '0'))
6351 set_fatal_syntax_error
6352 (_("the optional immediate offset can only be 0"));
6356 po_char_or_fail (']');
6360 case AARCH64_OPND_ADDR_REGOFF
:
6361 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6362 po_misc_or_fail (parse_address (&str
, info
));
6364 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6365 || !info
->addr
.preind
|| info
->addr
.postind
6366 || info
->addr
.writeback
)
6368 set_syntax_error (_("invalid addressing mode"));
6371 if (!info
->shifter
.operator_present
)
6373 /* Default to LSL if not present. Libopcodes prefers shifter
6374 kind to be explicit. */
6375 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6376 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6378 /* Qualifier to be deduced by libopcodes. */
6381 case AARCH64_OPND_ADDR_SIMM7
:
6382 po_misc_or_fail (parse_address (&str
, info
));
6383 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6384 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6386 set_syntax_error (_("invalid addressing mode"));
6389 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6391 set_syntax_error (_("relocation not allowed"));
6394 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6396 /* need_libopcodes_p */ 1,
6400 case AARCH64_OPND_ADDR_SIMM9
:
6401 case AARCH64_OPND_ADDR_SIMM9_2
:
6402 case AARCH64_OPND_ADDR_SIMM11
:
6403 case AARCH64_OPND_ADDR_SIMM13
:
6404 po_misc_or_fail (parse_address (&str
, info
));
6405 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6406 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6407 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6408 && info
->addr
.writeback
))
6410 set_syntax_error (_("invalid addressing mode"));
6413 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6415 set_syntax_error (_("relocation not allowed"));
6418 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6420 /* need_libopcodes_p */ 1,
6424 case AARCH64_OPND_ADDR_SIMM10
:
6425 case AARCH64_OPND_ADDR_OFFSET
:
6426 po_misc_or_fail (parse_address (&str
, info
));
6427 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6428 || !info
->addr
.preind
|| info
->addr
.postind
)
6430 set_syntax_error (_("invalid addressing mode"));
6433 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6435 set_syntax_error (_("relocation not allowed"));
6438 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6440 /* need_libopcodes_p */ 1,
6444 case AARCH64_OPND_ADDR_UIMM12
:
6445 po_misc_or_fail (parse_address (&str
, info
));
6446 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6447 || !info
->addr
.preind
|| info
->addr
.writeback
)
6449 set_syntax_error (_("invalid addressing mode"));
6452 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6453 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6454 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6456 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6458 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6460 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6462 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6463 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6464 /* Leave qualifier to be determined by libopcodes. */
6467 case AARCH64_OPND_SIMD_ADDR_POST
:
6468 /* [<Xn|SP>], <Xm|#<amount>> */
6469 po_misc_or_fail (parse_address (&str
, info
));
6470 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6472 set_syntax_error (_("invalid addressing mode"));
6475 if (!info
->addr
.offset
.is_reg
)
6477 if (inst
.reloc
.exp
.X_op
== O_constant
)
6478 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6481 set_fatal_syntax_error
6482 (_("writeback value must be an immediate constant"));
6489 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6490 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
6491 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6492 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6493 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6494 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6495 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6496 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6497 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6498 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6499 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6500 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6501 /* [X<n>{, #imm, MUL VL}]
6503 but recognizing SVE registers. */
6504 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6505 &offset_qualifier
));
6506 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6508 set_syntax_error (_("invalid addressing mode"));
6512 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6513 || !info
->addr
.preind
|| info
->addr
.writeback
)
6515 set_syntax_error (_("invalid addressing mode"));
6518 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6519 || inst
.reloc
.exp
.X_op
!= O_constant
)
6521 /* Make sure this has priority over
6522 "invalid addressing mode". */
6523 set_fatal_syntax_error (_("constant offset required"));
6526 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6529 case AARCH64_OPND_SVE_ADDR_R
:
6530 /* [<Xn|SP>{, <R><m>}]
6531 but recognizing SVE registers. */
6532 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6533 &offset_qualifier
));
6534 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6536 offset_qualifier
= AARCH64_OPND_QLF_X
;
6537 info
->addr
.offset
.is_reg
= 1;
6538 info
->addr
.offset
.regno
= 31;
6540 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6541 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6543 set_syntax_error (_("invalid addressing mode"));
6548 case AARCH64_OPND_SVE_ADDR_RR
:
6549 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6550 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6551 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6552 case AARCH64_OPND_SVE_ADDR_RX
:
6553 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6554 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6555 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6556 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6557 but recognizing SVE registers. */
6558 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6559 &offset_qualifier
));
6560 if (base_qualifier
!= AARCH64_OPND_QLF_X
6561 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6563 set_syntax_error (_("invalid addressing mode"));
6568 case AARCH64_OPND_SVE_ADDR_RZ
:
6569 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6570 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6571 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6572 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6573 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6574 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6575 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6576 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6577 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6578 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6579 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6580 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6581 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6582 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6583 &offset_qualifier
));
6584 if (base_qualifier
!= AARCH64_OPND_QLF_X
6585 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6586 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6588 set_syntax_error (_("invalid addressing mode"));
6591 info
->qualifier
= offset_qualifier
;
6594 case AARCH64_OPND_SVE_ADDR_ZX
:
6595 /* [Zn.<T>{, <Xm>}]. */
6596 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6597 &offset_qualifier
));
6599 base_qualifier either S_S or S_D
6600 offset_qualifier must be X
6602 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6603 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6604 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6606 set_syntax_error (_("invalid addressing mode"));
6609 info
->qualifier
= base_qualifier
;
6610 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6611 || !info
->addr
.preind
|| info
->addr
.writeback
6612 || info
->shifter
.operator_present
!= 0)
6614 set_syntax_error (_("invalid addressing mode"));
6617 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6621 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6622 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6623 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6624 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6625 /* [Z<n>.<T>{, #imm}] */
6626 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6627 &offset_qualifier
));
6628 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6629 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6631 set_syntax_error (_("invalid addressing mode"));
6634 info
->qualifier
= base_qualifier
;
6637 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6638 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6639 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6640 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6641 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6645 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6647 here since we get better error messages by leaving it to
6648 the qualifier checking routines. */
6649 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6650 &offset_qualifier
));
6651 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6652 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6653 || offset_qualifier
!= base_qualifier
)
6655 set_syntax_error (_("invalid addressing mode"));
6658 info
->qualifier
= base_qualifier
;
6661 case AARCH64_OPND_SYSREG
:
6663 uint32_t sysreg_flags
;
6664 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6665 &sysreg_flags
)) == PARSE_FAIL
)
6667 set_syntax_error (_("unknown or missing system register name"));
6670 inst
.base
.operands
[i
].sysreg
.value
= val
;
6671 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6675 case AARCH64_OPND_PSTATEFIELD
:
6676 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6679 set_syntax_error (_("unknown or missing PSTATE field name"));
6682 inst
.base
.operands
[i
].pstatefield
= val
;
6685 case AARCH64_OPND_SYSREG_IC
:
6686 inst
.base
.operands
[i
].sysins_op
=
6687 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6690 case AARCH64_OPND_SYSREG_DC
:
6691 inst
.base
.operands
[i
].sysins_op
=
6692 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6695 case AARCH64_OPND_SYSREG_AT
:
6696 inst
.base
.operands
[i
].sysins_op
=
6697 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6700 case AARCH64_OPND_SYSREG_SR
:
6701 inst
.base
.operands
[i
].sysins_op
=
6702 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6705 case AARCH64_OPND_SYSREG_TLBI
:
6706 inst
.base
.operands
[i
].sysins_op
=
6707 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6709 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6711 set_fatal_syntax_error ( _("unknown or missing operation name"));
6716 case AARCH64_OPND_BARRIER
:
6717 case AARCH64_OPND_BARRIER_ISB
:
6718 val
= parse_barrier (&str
);
6719 if (val
!= PARSE_FAIL
6720 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6722 /* ISB only accepts options name 'sy'. */
6724 (_("the specified option is not accepted in ISB"));
6725 /* Turn off backtrack as this optional operand is present. */
6729 if (val
!= PARSE_FAIL
6730 && operands
[i
] == AARCH64_OPND_BARRIER
)
6732 /* Regular barriers accept options CRm (C0-C15).
6733 DSB nXS barrier variant accepts values > 15. */
6734 if (val
< 0 || val
> 15)
6736 set_syntax_error (_("the specified option is not accepted in DSB"));
6740 /* This is an extension to accept a 0..15 immediate. */
6741 if (val
== PARSE_FAIL
)
6742 po_imm_or_fail (0, 15);
6743 info
->barrier
= aarch64_barrier_options
+ val
;
6746 case AARCH64_OPND_BARRIER_DSB_NXS
:
6747 val
= parse_barrier (&str
);
6748 if (val
!= PARSE_FAIL
)
6750 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
6751 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
6753 set_syntax_error (_("the specified option is not accepted in DSB"));
6754 /* Turn off backtrack as this optional operand is present. */
6761 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
6762 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
6763 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
6765 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
6767 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
6771 /* Option index is encoded as 2-bit value in val<3:2>. */
6772 val
= (val
>> 2) - 4;
6773 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
6776 case AARCH64_OPND_PRFOP
:
6777 val
= parse_pldop (&str
);
6778 /* This is an extension to accept a 0..31 immediate. */
6779 if (val
== PARSE_FAIL
)
6780 po_imm_or_fail (0, 31);
6781 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6784 case AARCH64_OPND_BARRIER_PSB
:
6785 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6786 if (val
== PARSE_FAIL
)
6790 case AARCH64_OPND_BTI_TARGET
:
6791 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6792 if (val
== PARSE_FAIL
)
6796 case AARCH64_OPND_CSRE_CSR
:
6797 val
= parse_csr_operand (&str
);
6798 if (val
== PARSE_FAIL
)
6803 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6806 /* If we get here, this operand was successfully parsed. */
6807 inst
.base
.operands
[i
].present
= 1;
6811 /* The parse routine should already have set the error, but in case
6812 not, set a default one here. */
6814 set_default_error ();
6816 if (! backtrack_pos
)
6817 goto parse_operands_return
;
6820 /* We reach here because this operand is marked as optional, and
6821 either no operand was supplied or the operand was supplied but it
6822 was syntactically incorrect. In the latter case we report an
6823 error. In the former case we perform a few more checks before
6824 dropping through to the code to insert the default operand. */
6826 char *tmp
= backtrack_pos
;
6827 char endchar
= END_OF_INSN
;
6829 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6831 skip_past_char (&tmp
, ',');
6833 if (*tmp
!= endchar
)
6834 /* The user has supplied an operand in the wrong format. */
6835 goto parse_operands_return
;
6837 /* Make sure there is not a comma before the optional operand.
6838 For example the fifth operand of 'sys' is optional:
6840 sys #0,c0,c0,#0, <--- wrong
6841 sys #0,c0,c0,#0 <--- correct. */
6842 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6844 set_fatal_syntax_error
6845 (_("unexpected comma before the omitted optional operand"));
6846 goto parse_operands_return
;
6850 /* Reaching here means we are dealing with an optional operand that is
6851 omitted from the assembly line. */
6852 gas_assert (optional_operand_p (opcode
, i
));
6854 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6856 /* Try again, skipping the optional operand at backtrack_pos. */
6857 str
= backtrack_pos
;
6860 /* Clear any error record after the omitted optional operand has been
6861 successfully handled. */
6865 /* Check if we have parsed all the operands. */
6866 if (*str
!= '\0' && ! error_p ())
6868 /* Set I to the index of the last present operand; this is
6869 for the purpose of diagnostics. */
6870 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6872 set_fatal_syntax_error
6873 (_("unexpected characters following instruction"));
6876 parse_operands_return
:
6880 DEBUG_TRACE ("parsing FAIL: %s - %s",
6881 operand_mismatch_kind_names
[get_error_kind ()],
6882 get_error_message ());
6883 /* Record the operand error properly; this is useful when there
6884 are multiple instruction templates for a mnemonic name, so that
6885 later on, we can select the error that most closely describes
6887 record_operand_error (opcode
, i
, get_error_kind (),
6888 get_error_message ());
6893 DEBUG_TRACE ("parsing SUCCESS");
6898 /* It does some fix-up to provide some programmer friendly feature while
6899 keeping the libopcodes happy, i.e. libopcodes only accepts
6900 the preferred architectural syntax.
6901 Return FALSE if there is any failure; otherwise return TRUE. */
6904 programmer_friendly_fixup (aarch64_instruction
*instr
)
6906 aarch64_inst
*base
= &instr
->base
;
6907 const aarch64_opcode
*opcode
= base
->opcode
;
6908 enum aarch64_op op
= opcode
->op
;
6909 aarch64_opnd_info
*operands
= base
->operands
;
6911 DEBUG_TRACE ("enter");
6913 switch (opcode
->iclass
)
6916 /* TBNZ Xn|Wn, #uimm6, label
6917 Test and Branch Not Zero: conditionally jumps to label if bit number
6918 uimm6 in register Xn is not zero. The bit number implies the width of
6919 the register, which may be written and should be disassembled as Wn if
6920 uimm is less than 32. */
6921 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6923 if (operands
[1].imm
.value
>= 32)
6925 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6929 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6933 /* LDR Wt, label | =value
6934 As a convenience assemblers will typically permit the notation
6935 "=value" in conjunction with the pc-relative literal load instructions
6936 to automatically place an immediate value or symbolic address in a
6937 nearby literal pool and generate a hidden label which references it.
6938 ISREG has been set to 0 in the case of =value. */
6939 if (instr
->gen_lit_pool
6940 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6942 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6943 if (op
== OP_LDRSW_LIT
)
6945 if (instr
->reloc
.exp
.X_op
!= O_constant
6946 && instr
->reloc
.exp
.X_op
!= O_big
6947 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6949 record_operand_error (opcode
, 1,
6950 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6951 _("constant expression expected"));
6954 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6956 record_operand_error (opcode
, 1,
6957 AARCH64_OPDE_OTHER_ERROR
,
6958 _("literal pool insertion failed"));
6966 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6967 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6968 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6969 A programmer-friendly assembler should accept a destination Xd in
6970 place of Wd, however that is not the preferred form for disassembly.
6972 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6973 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6974 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6975 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6980 /* In the 64-bit form, the final register operand is written as Wm
6981 for all but the (possibly omitted) UXTX/LSL and SXTX
6983 As a programmer-friendly assembler, we accept e.g.
6984 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6985 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6986 int idx
= aarch64_operand_index (opcode
->operands
,
6987 AARCH64_OPND_Rm_EXT
);
6988 gas_assert (idx
== 1 || idx
== 2);
6989 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6990 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6991 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6992 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6993 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6994 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7002 DEBUG_TRACE ("exit with SUCCESS");
7006 /* Check for loads and stores that will cause unpredictable behavior. */
7009 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7011 aarch64_inst
*base
= &instr
->base
;
7012 const aarch64_opcode
*opcode
= base
->opcode
;
7013 const aarch64_opnd_info
*opnds
= base
->operands
;
7014 switch (opcode
->iclass
)
7021 /* Loading/storing the base register is unpredictable if writeback. */
7022 if ((aarch64_get_operand_class (opnds
[0].type
)
7023 == AARCH64_OPND_CLASS_INT_REG
)
7024 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7025 && opnds
[1].addr
.base_regno
!= REG_SP
7026 /* Exempt STG/STZG/ST2G/STZ2G. */
7027 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7028 && opnds
[1].addr
.writeback
)
7029 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7033 case ldstnapair_offs
:
7034 case ldstpair_indexed
:
7035 /* Loading/storing the base register is unpredictable if writeback. */
7036 if ((aarch64_get_operand_class (opnds
[0].type
)
7037 == AARCH64_OPND_CLASS_INT_REG
)
7038 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7039 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7040 && opnds
[2].addr
.base_regno
!= REG_SP
7042 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7043 && opnds
[2].addr
.writeback
)
7044 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7045 /* Load operations must load different registers. */
7046 if ((opcode
->opcode
& (1 << 22))
7047 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7048 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7052 /* It is unpredictable if the destination and status registers are the
7054 if ((aarch64_get_operand_class (opnds
[0].type
)
7055 == AARCH64_OPND_CLASS_INT_REG
)
7056 && (aarch64_get_operand_class (opnds
[1].type
)
7057 == AARCH64_OPND_CLASS_INT_REG
)
7058 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
7059 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
7060 as_warn (_("unpredictable: identical transfer and status registers"
7072 force_automatic_sequence_close (void)
7074 if (now_instr_sequence
.instr
)
7076 as_warn (_("previous `%s' sequence has not been closed"),
7077 now_instr_sequence
.instr
->opcode
->name
);
7078 init_insn_sequence (NULL
, &now_instr_sequence
);
7082 /* A wrapper function to interface with libopcodes on encoding and
7083 record the error message if there is any.
7085 Return TRUE on success; otherwise return FALSE. */
7088 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7091 aarch64_operand_error error_info
;
7092 memset (&error_info
, '\0', sizeof (error_info
));
7093 error_info
.kind
= AARCH64_OPDE_NIL
;
7094 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7095 && !error_info
.non_fatal
)
7098 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7099 record_operand_error_info (opcode
, &error_info
);
7100 return error_info
.non_fatal
;
7103 #ifdef DEBUG_AARCH64
7105 dump_opcode_operands (const aarch64_opcode
*opcode
)
7108 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7110 aarch64_verbose ("\t\t opnd%d: %s", i
,
7111 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7112 ? aarch64_get_operand_name (opcode
->operands
[i
])
7113 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7117 #endif /* DEBUG_AARCH64 */
7119 /* This is the guts of the machine-dependent assembler. STR points to a
7120 machine dependent instruction. This function is supposed to emit
7121 the frags/bytes it assembles to. */
7124 md_assemble (char *str
)
7127 templates
*template;
7128 aarch64_opcode
*opcode
;
7129 aarch64_inst
*inst_base
;
7130 unsigned saved_cond
;
7132 /* Align the previous label if needed. */
7133 if (last_label_seen
!= NULL
)
7135 symbol_set_frag (last_label_seen
, frag_now
);
7136 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7137 S_SET_SEGMENT (last_label_seen
, now_seg
);
7140 /* Update the current insn_sequence from the segment. */
7141 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7143 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7145 DEBUG_TRACE ("\n\n");
7146 DEBUG_TRACE ("==============================");
7147 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7149 template = opcode_lookup (&p
);
7152 /* It wasn't an instruction, but it might be a register alias of
7153 the form alias .req reg directive. */
7154 if (!create_register_alias (str
, p
))
7155 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7160 skip_whitespace (p
);
7163 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7164 get_mnemonic_name (str
), str
);
7168 init_operand_error_report ();
7170 /* Sections are assumed to start aligned. In executable section, there is no
7171 MAP_DATA symbol pending. So we only align the address during
7172 MAP_DATA --> MAP_INSN transition.
7173 For other sections, this is not guaranteed. */
7174 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7175 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7176 frag_align_code (2, 0);
7178 saved_cond
= inst
.cond
;
7179 reset_aarch64_instruction (&inst
);
7180 inst
.cond
= saved_cond
;
7182 /* Iterate through all opcode entries with the same mnemonic name. */
7185 opcode
= template->opcode
;
7187 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7188 #ifdef DEBUG_AARCH64
7190 dump_opcode_operands (opcode
);
7191 #endif /* DEBUG_AARCH64 */
7193 mapping_state (MAP_INSN
);
7195 inst_base
= &inst
.base
;
7196 inst_base
->opcode
= opcode
;
7198 /* Truly conditionally executed instructions, e.g. b.cond. */
7199 if (opcode
->flags
& F_COND
)
7201 gas_assert (inst
.cond
!= COND_ALWAYS
);
7202 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7203 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7205 else if (inst
.cond
!= COND_ALWAYS
)
7207 /* It shouldn't arrive here, where the assembly looks like a
7208 conditional instruction but the found opcode is unconditional. */
7213 if (parse_operands (p
, opcode
)
7214 && programmer_friendly_fixup (&inst
)
7215 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7217 /* Check that this instruction is supported for this CPU. */
7218 if (!opcode
->avariant
7219 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7221 as_bad (_("selected processor does not support `%s'"), str
);
7225 warn_unpredictable_ldst (&inst
, str
);
7227 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7228 || !inst
.reloc
.need_libopcodes_p
)
7232 /* If there is relocation generated for the instruction,
7233 store the instruction information for the future fix-up. */
7234 struct aarch64_inst
*copy
;
7235 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7236 copy
= XNEW (struct aarch64_inst
);
7237 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7241 /* Issue non-fatal messages if any. */
7242 output_operand_error_report (str
, TRUE
);
7246 template = template->next
;
7247 if (template != NULL
)
7249 reset_aarch64_instruction (&inst
);
7250 inst
.cond
= saved_cond
;
7253 while (template != NULL
);
7255 /* Issue the error messages if any. */
7256 output_operand_error_report (str
, FALSE
);
7259 /* Various frobbings of labels and their addresses. */
7262 aarch64_start_line_hook (void)
7264 last_label_seen
= NULL
;
7268 aarch64_frob_label (symbolS
* sym
)
7270 last_label_seen
= sym
;
7272 dwarf2_emit_label (sym
);
7276 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7278 /* Check to see if we have a block to close. */
7279 force_automatic_sequence_close ();
7283 aarch64_data_in_code (void)
7285 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7287 *input_line_pointer
= '/';
7288 input_line_pointer
+= 5;
7289 *input_line_pointer
= 0;
7297 aarch64_canonicalize_symbol_name (char *name
)
7301 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7302 *(name
+ len
- 5) = 0;
7307 /* Table of all register names defined by default. The user can
7308 define additional names with .req. Note that all register names
7309 should appear in both upper and lowercase variants. Some registers
7310 also have mixed-case names. */
7312 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7313 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7314 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7315 #define REGSET16(p,t) \
7316 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7317 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7318 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7319 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7320 #define REGSET31(p,t) \
7322 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7323 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7324 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7325 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7326 #define REGSET(p,t) \
7327 REGSET31(p,t), REGNUM(p,31,t)
7329 /* These go into aarch64_reg_hsh hash-table. */
7330 static const reg_entry reg_names
[] = {
7331 /* Integer registers. */
7332 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7333 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7335 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7336 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7337 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7338 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7339 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7340 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7342 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7343 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7345 /* Floating-point single precision registers. */
7346 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7348 /* Floating-point double precision registers. */
7349 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7351 /* Floating-point half precision registers. */
7352 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7354 /* Floating-point byte precision registers. */
7355 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7357 /* Floating-point quad precision registers. */
7358 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7360 /* FP/SIMD registers. */
7361 REGSET (v
, VN
), REGSET (V
, VN
),
7363 /* SVE vector registers. */
7364 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7366 /* SVE predicate registers. */
7367 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7385 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7386 static const asm_nzcv nzcv_names
[] = {
7387 {"nzcv", B (n
, z
, c
, v
)},
7388 {"nzcV", B (n
, z
, c
, V
)},
7389 {"nzCv", B (n
, z
, C
, v
)},
7390 {"nzCV", B (n
, z
, C
, V
)},
7391 {"nZcv", B (n
, Z
, c
, v
)},
7392 {"nZcV", B (n
, Z
, c
, V
)},
7393 {"nZCv", B (n
, Z
, C
, v
)},
7394 {"nZCV", B (n
, Z
, C
, V
)},
7395 {"Nzcv", B (N
, z
, c
, v
)},
7396 {"NzcV", B (N
, z
, c
, V
)},
7397 {"NzCv", B (N
, z
, C
, v
)},
7398 {"NzCV", B (N
, z
, C
, V
)},
7399 {"NZcv", B (N
, Z
, c
, v
)},
7400 {"NZcV", B (N
, Z
, c
, V
)},
7401 {"NZCv", B (N
, Z
, C
, v
)},
7402 {"NZCV", B (N
, Z
, C
, V
)}
7415 /* MD interface: bits in the object file. */
7417 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7418 for use in the a.out file, and stores them in the array pointed to by buf.
7419 This knows about the endian-ness of the target machine and does
7420 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7421 2 (short) and 4 (long) Floating numbers are put out as a series of
7422 LITTLENUMS (shorts, here at least). */
7425 md_number_to_chars (char *buf
, valueT val
, int n
)
7427 if (target_big_endian
)
7428 number_to_chars_bigendian (buf
, val
, n
);
7430 number_to_chars_littleendian (buf
, val
, n
);
7433 /* MD interface: Sections. */
7435 /* Estimate the size of a frag before relaxing. Assume everything fits in
7439 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7445 /* Round up a section size to the appropriate boundary. */
7448 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7453 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7454 of an rs_align_code fragment.
7456 Here we fill the frag with the appropriate info for padding the
7457 output stream. The resulting frag will consist of a fixed (fr_fix)
7458 and of a repeating (fr_var) part.
7460 The fixed content is always emitted before the repeating content and
7461 these two parts are used as follows in constructing the output:
7462 - the fixed part will be used to align to a valid instruction word
7463 boundary, in case that we start at a misaligned address; as no
7464 executable instruction can live at the misaligned location, we
7465 simply fill with zeros;
7466 - the variable part will be used to cover the remaining padding and
7467 we fill using the AArch64 NOP instruction.
7469 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7470 enough storage space for up to 3 bytes for padding the back to a valid
7471 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7474 aarch64_handle_align (fragS
* fragP
)
7476 /* NOP = d503201f */
7477 /* AArch64 instructions are always little-endian. */
7478 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7480 int bytes
, fix
, noop_size
;
7483 if (fragP
->fr_type
!= rs_align_code
)
7486 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7487 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7490 gas_assert (fragP
->tc_frag_data
.recorded
);
7493 noop_size
= sizeof (aarch64_noop
);
7495 fix
= bytes
& (noop_size
- 1);
7499 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7503 fragP
->fr_fix
+= fix
;
7507 memcpy (p
, aarch64_noop
, noop_size
);
7508 fragP
->fr_var
= noop_size
;
7511 /* Perform target specific initialisation of a frag.
7512 Note - despite the name this initialisation is not done when the frag
7513 is created, but only when its type is assigned. A frag can be created
7514 and used a long time before its type is set, so beware of assuming that
7515 this initialisation is performed first. */
7519 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7520 int max_chars ATTRIBUTE_UNUSED
)
7524 #else /* OBJ_ELF is defined. */
7526 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7528 /* Record a mapping symbol for alignment frags. We will delete this
7529 later if the alignment ends up empty. */
7530 if (!fragP
->tc_frag_data
.recorded
)
7531 fragP
->tc_frag_data
.recorded
= 1;
7533 /* PR 21809: Do not set a mapping state for debug sections
7534 - it just confuses other tools. */
7535 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7538 switch (fragP
->fr_type
)
7542 mapping_state_2 (MAP_DATA
, max_chars
);
7545 /* PR 20364: We can get alignment frags in code sections,
7546 so do not just assume that we should use the MAP_DATA state. */
7547 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7550 mapping_state_2 (MAP_INSN
, max_chars
);
7557 /* Initialize the DWARF-2 unwind information for this procedure. */
7560 tc_aarch64_frame_initial_instructions (void)
7562 cfi_add_CFA_def_cfa (REG_SP
, 0);
7564 #endif /* OBJ_ELF */
7566 /* Convert REGNAME to a DWARF-2 register number. */
7569 tc_aarch64_regname_to_dw2regnum (char *regname
)
7571 const reg_entry
*reg
= parse_reg (®name
);
7577 case REG_TYPE_SP_32
:
7578 case REG_TYPE_SP_64
:
7588 return reg
->number
+ 64;
7596 /* Implement DWARF2_ADDR_SIZE. */
7599 aarch64_dwarf2_addr_size (void)
7601 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7605 return bfd_arch_bits_per_address (stdoutput
) / 8;
7608 /* MD interface: Symbol and relocation handling. */
7610 /* Return the address within the segment that a PC-relative fixup is
7611 relative to. For AArch64 PC-relative fixups applied to instructions
7612 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7615 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7617 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7619 /* If this is pc-relative and we are going to emit a relocation
7620 then we just want to put out any pipeline compensation that the linker
7621 will need. Otherwise we want to use the calculated base. */
7623 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7624 || aarch64_force_relocation (fixP
)))
7627 /* AArch64 should be consistent for all pc-relative relocations. */
7628 return base
+ AARCH64_PCREL_OFFSET
;
7631 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7632 Otherwise we have no need to default values of symbols. */
7635 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7638 if (name
[0] == '_' && name
[1] == 'G'
7639 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7643 if (symbol_find (name
))
7644 as_bad (_("GOT already in the symbol table"));
7646 GOT_symbol
= symbol_new (name
, undefined_section
,
7647 &zero_address_frag
, 0);
7657 /* Return non-zero if the indicated VALUE has overflowed the maximum
7658 range expressible by a unsigned number with the indicated number of
7662 unsigned_overflow (valueT value
, unsigned bits
)
7665 if (bits
>= sizeof (valueT
) * 8)
7667 lim
= (valueT
) 1 << bits
;
7668 return (value
>= lim
);
7672 /* Return non-zero if the indicated VALUE has overflowed the maximum
7673 range expressible by an signed number with the indicated number of
7677 signed_overflow (offsetT value
, unsigned bits
)
7680 if (bits
>= sizeof (offsetT
) * 8)
7682 lim
= (offsetT
) 1 << (bits
- 1);
7683 return (value
< -lim
|| value
>= lim
);
7686 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7687 unsigned immediate offset load/store instruction, try to encode it as
7688 an unscaled, 9-bit, signed immediate offset load/store instruction.
7689 Return TRUE if it is successful; otherwise return FALSE.
7691 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7692 in response to the standard LDR/STR mnemonics when the immediate offset is
7693 unambiguous, i.e. when it is negative or unaligned. */
7696 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7699 enum aarch64_op new_op
;
7700 const aarch64_opcode
*new_opcode
;
7702 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7704 switch (instr
->opcode
->op
)
7706 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7707 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7708 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7709 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7710 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7711 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7712 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7713 case OP_STR_POS
: new_op
= OP_STUR
; break;
7714 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7715 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7716 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7717 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7718 default: new_op
= OP_NIL
; break;
7721 if (new_op
== OP_NIL
)
7724 new_opcode
= aarch64_get_opcode (new_op
);
7725 gas_assert (new_opcode
!= NULL
);
7727 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7728 instr
->opcode
->op
, new_opcode
->op
);
7730 aarch64_replace_opcode (instr
, new_opcode
);
7732 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7733 qualifier matching may fail because the out-of-date qualifier will
7734 prevent the operand being updated with a new and correct qualifier. */
7735 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7736 AARCH64_OPND_ADDR_SIMM9
);
7737 gas_assert (idx
== 1);
7738 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7740 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7742 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7749 /* Called by fix_insn to fix a MOV immediate alias instruction.
7751 Operand for a generic move immediate instruction, which is an alias
7752 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7753 a 32-bit/64-bit immediate value into general register. An assembler error
7754 shall result if the immediate cannot be created by a single one of these
7755 instructions. If there is a choice, then to ensure reversability an
7756 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7759 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7761 const aarch64_opcode
*opcode
;
7763 /* Need to check if the destination is SP/ZR. The check has to be done
7764 before any aarch64_replace_opcode. */
7765 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7766 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7768 instr
->operands
[1].imm
.value
= value
;
7769 instr
->operands
[1].skip
= 0;
7773 /* Try the MOVZ alias. */
7774 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7775 aarch64_replace_opcode (instr
, opcode
);
7776 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7777 &instr
->value
, NULL
, NULL
, insn_sequence
))
7779 put_aarch64_insn (buf
, instr
->value
);
7782 /* Try the MOVK alias. */
7783 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7784 aarch64_replace_opcode (instr
, opcode
);
7785 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7786 &instr
->value
, NULL
, NULL
, insn_sequence
))
7788 put_aarch64_insn (buf
, instr
->value
);
7793 if (try_mov_bitmask_p
)
7795 /* Try the ORR alias. */
7796 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7797 aarch64_replace_opcode (instr
, opcode
);
7798 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7799 &instr
->value
, NULL
, NULL
, insn_sequence
))
7801 put_aarch64_insn (buf
, instr
->value
);
7806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7807 _("immediate cannot be moved by a single instruction"));
7810 /* An instruction operand which is immediate related may have symbol used
7811 in the assembly, e.g.
7814 .set u32, 0x00ffff00
7816 At the time when the assembly instruction is parsed, a referenced symbol,
7817 like 'u32' in the above example may not have been seen; a fixS is created
7818 in such a case and is handled here after symbols have been resolved.
7819 Instruction is fixed up with VALUE using the information in *FIXP plus
7820 extra information in FLAGS.
7822 This function is called by md_apply_fix to fix up instructions that need
7823 a fix-up described above but does not involve any linker-time relocation. */
7826 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7830 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7831 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7832 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7836 /* Now the instruction is about to be fixed-up, so the operand that
7837 was previously marked as 'ignored' needs to be unmarked in order
7838 to get the encoding done properly. */
7839 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7840 new_inst
->operands
[idx
].skip
= 0;
7843 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7847 case AARCH64_OPND_EXCEPTION
:
7848 case AARCH64_OPND_UNDEFINED
:
7849 if (unsigned_overflow (value
, 16))
7850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7851 _("immediate out of range"));
7852 insn
= get_aarch64_insn (buf
);
7853 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
7854 put_aarch64_insn (buf
, insn
);
7857 case AARCH64_OPND_AIMM
:
7858 /* ADD or SUB with immediate.
7859 NOTE this assumes we come here with a add/sub shifted reg encoding
7860 3 322|2222|2 2 2 21111 111111
7861 1 098|7654|3 2 1 09876 543210 98765 43210
7862 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7863 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7864 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7865 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7867 3 322|2222|2 2 221111111111
7868 1 098|7654|3 2 109876543210 98765 43210
7869 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7870 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7871 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7872 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7873 Fields sf Rn Rd are already set. */
7874 insn
= get_aarch64_insn (buf
);
7878 insn
= reencode_addsub_switch_add_sub (insn
);
7882 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7883 && unsigned_overflow (value
, 12))
7885 /* Try to shift the value by 12 to make it fit. */
7886 if (((value
>> 12) << 12) == value
7887 && ! unsigned_overflow (value
, 12 + 12))
7890 insn
|= encode_addsub_imm_shift_amount (1);
7894 if (unsigned_overflow (value
, 12))
7895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7896 _("immediate out of range"));
7898 insn
|= encode_addsub_imm (value
);
7900 put_aarch64_insn (buf
, insn
);
7903 case AARCH64_OPND_SIMD_IMM
:
7904 case AARCH64_OPND_SIMD_IMM_SFT
:
7905 case AARCH64_OPND_LIMM
:
7906 /* Bit mask immediate. */
7907 gas_assert (new_inst
!= NULL
);
7908 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7909 new_inst
->operands
[idx
].imm
.value
= value
;
7910 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7911 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7912 put_aarch64_insn (buf
, new_inst
->value
);
7914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7915 _("invalid immediate"));
7918 case AARCH64_OPND_HALF
:
7919 /* 16-bit unsigned immediate. */
7920 if (unsigned_overflow (value
, 16))
7921 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7922 _("immediate out of range"));
7923 insn
= get_aarch64_insn (buf
);
7924 insn
|= encode_movw_imm (value
& 0xffff);
7925 put_aarch64_insn (buf
, insn
);
7928 case AARCH64_OPND_IMM_MOV
:
7929 /* Operand for a generic move immediate instruction, which is
7930 an alias instruction that generates a single MOVZ, MOVN or ORR
7931 instruction to loads a 32-bit/64-bit immediate value into general
7932 register. An assembler error shall result if the immediate cannot be
7933 created by a single one of these instructions. If there is a choice,
7934 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7935 and MOVZ or MOVN to ORR. */
7936 gas_assert (new_inst
!= NULL
);
7937 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7940 case AARCH64_OPND_ADDR_SIMM7
:
7941 case AARCH64_OPND_ADDR_SIMM9
:
7942 case AARCH64_OPND_ADDR_SIMM9_2
:
7943 case AARCH64_OPND_ADDR_SIMM10
:
7944 case AARCH64_OPND_ADDR_UIMM12
:
7945 case AARCH64_OPND_ADDR_SIMM11
:
7946 case AARCH64_OPND_ADDR_SIMM13
:
7947 /* Immediate offset in an address. */
7948 insn
= get_aarch64_insn (buf
);
7950 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7951 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7952 || new_inst
->opcode
->operands
[2] == opnd
);
7954 /* Get the index of the address operand. */
7955 if (new_inst
->opcode
->operands
[1] == opnd
)
7956 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7959 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7962 /* Update the resolved offset value. */
7963 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7965 /* Encode/fix-up. */
7966 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7967 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7969 put_aarch64_insn (buf
, new_inst
->value
);
7972 else if (new_inst
->opcode
->iclass
== ldst_pos
7973 && try_to_encode_as_unscaled_ldst (new_inst
))
7975 put_aarch64_insn (buf
, new_inst
->value
);
7979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7980 _("immediate offset out of range"));
7985 as_fatal (_("unhandled operand code %d"), opnd
);
7989 /* Apply a fixup (fixP) to segment data, once it has been determined
7990 by our caller that we have all the info we need to fix it up.
7992 Parameter valP is the pointer to the value of the bits. */
7995 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7997 offsetT value
= *valP
;
7999 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8001 unsigned flags
= fixP
->fx_addnumber
;
8003 DEBUG_TRACE ("\n\n");
8004 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8005 DEBUG_TRACE ("Enter md_apply_fix");
8007 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8009 /* Note whether this will delete the relocation. */
8011 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
8014 /* Process the relocations. */
8015 switch (fixP
->fx_r_type
)
8017 case BFD_RELOC_NONE
:
8018 /* This will need to go in the object file. */
8023 case BFD_RELOC_8_PCREL
:
8024 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8025 md_number_to_chars (buf
, value
, 1);
8029 case BFD_RELOC_16_PCREL
:
8030 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8031 md_number_to_chars (buf
, value
, 2);
8035 case BFD_RELOC_32_PCREL
:
8036 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8037 md_number_to_chars (buf
, value
, 4);
8041 case BFD_RELOC_64_PCREL
:
8042 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8043 md_number_to_chars (buf
, value
, 8);
8046 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8047 /* We claim that these fixups have been processed here, even if
8048 in fact we generate an error because we do not have a reloc
8049 for them, so tc_gen_reloc() will reject them. */
8051 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8054 _("undefined symbol %s used as an immediate value"),
8055 S_GET_NAME (fixP
->fx_addsy
));
8056 goto apply_fix_return
;
8058 fix_insn (fixP
, flags
, value
);
8061 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8062 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8066 _("pc-relative load offset not word aligned"));
8067 if (signed_overflow (value
, 21))
8068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8069 _("pc-relative load offset out of range"));
8070 insn
= get_aarch64_insn (buf
);
8071 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8072 put_aarch64_insn (buf
, insn
);
8076 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8077 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8079 if (signed_overflow (value
, 21))
8080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8081 _("pc-relative address offset out of range"));
8082 insn
= get_aarch64_insn (buf
);
8083 insn
|= encode_adr_imm (value
);
8084 put_aarch64_insn (buf
, insn
);
8088 case BFD_RELOC_AARCH64_BRANCH19
:
8089 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8093 _("conditional branch target not word aligned"));
8094 if (signed_overflow (value
, 21))
8095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8096 _("conditional branch out of range"));
8097 insn
= get_aarch64_insn (buf
);
8098 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8099 put_aarch64_insn (buf
, insn
);
8103 case BFD_RELOC_AARCH64_TSTBR14
:
8104 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8108 _("conditional branch target not word aligned"));
8109 if (signed_overflow (value
, 16))
8110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8111 _("conditional branch out of range"));
8112 insn
= get_aarch64_insn (buf
);
8113 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8114 put_aarch64_insn (buf
, insn
);
8118 case BFD_RELOC_AARCH64_CALL26
:
8119 case BFD_RELOC_AARCH64_JUMP26
:
8120 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8124 _("branch target not word aligned"));
8125 if (signed_overflow (value
, 28))
8126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8127 _("branch out of range"));
8128 insn
= get_aarch64_insn (buf
);
8129 insn
|= encode_branch_ofs_26 (value
>> 2);
8130 put_aarch64_insn (buf
, insn
);
8134 case BFD_RELOC_AARCH64_MOVW_G0
:
8135 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8136 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8137 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8138 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8139 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8142 case BFD_RELOC_AARCH64_MOVW_G1
:
8143 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8144 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8145 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8146 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8147 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8150 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8152 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8153 /* Should always be exported to object file, see
8154 aarch64_force_relocation(). */
8155 gas_assert (!fixP
->fx_done
);
8156 gas_assert (seg
->use_rela_p
);
8158 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8160 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8161 /* Should always be exported to object file, see
8162 aarch64_force_relocation(). */
8163 gas_assert (!fixP
->fx_done
);
8164 gas_assert (seg
->use_rela_p
);
8166 case BFD_RELOC_AARCH64_MOVW_G2
:
8167 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8168 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8169 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8170 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8173 case BFD_RELOC_AARCH64_MOVW_G3
:
8174 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8177 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8179 insn
= get_aarch64_insn (buf
);
8183 /* REL signed addend must fit in 16 bits */
8184 if (signed_overflow (value
, 16))
8185 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8186 _("offset out of range"));
8190 /* Check for overflow and scale. */
8191 switch (fixP
->fx_r_type
)
8193 case BFD_RELOC_AARCH64_MOVW_G0
:
8194 case BFD_RELOC_AARCH64_MOVW_G1
:
8195 case BFD_RELOC_AARCH64_MOVW_G2
:
8196 case BFD_RELOC_AARCH64_MOVW_G3
:
8197 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8198 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8199 if (unsigned_overflow (value
, scale
+ 16))
8200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8201 _("unsigned value out of range"));
8203 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8204 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8205 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8206 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8207 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8208 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8209 /* NOTE: We can only come here with movz or movn. */
8210 if (signed_overflow (value
, scale
+ 16))
8211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8212 _("signed value out of range"));
8215 /* Force use of MOVN. */
8217 insn
= reencode_movzn_to_movn (insn
);
8221 /* Force use of MOVZ. */
8222 insn
= reencode_movzn_to_movz (insn
);
8226 /* Unchecked relocations. */
8232 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8233 insn
|= encode_movw_imm (value
& 0xffff);
8235 put_aarch64_insn (buf
, insn
);
8239 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8240 fixP
->fx_r_type
= (ilp32_p
8241 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8242 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8243 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8244 /* Should always be exported to object file, see
8245 aarch64_force_relocation(). */
8246 gas_assert (!fixP
->fx_done
);
8247 gas_assert (seg
->use_rela_p
);
8250 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8251 fixP
->fx_r_type
= (ilp32_p
8252 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8253 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8254 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8255 /* Should always be exported to object file, see
8256 aarch64_force_relocation(). */
8257 gas_assert (!fixP
->fx_done
);
8258 gas_assert (seg
->use_rela_p
);
8261 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8262 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8263 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8264 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8265 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8266 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8267 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8268 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8269 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8270 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8271 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8272 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8273 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8274 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8275 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8276 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8277 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8278 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8279 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8280 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8281 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8282 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8283 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8284 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8285 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8286 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8287 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8288 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8289 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8290 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8291 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8292 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8293 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8294 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8295 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8296 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8297 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8298 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8299 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8300 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8301 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8302 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8303 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8304 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8305 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8306 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8307 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8308 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8309 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8310 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8311 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8312 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8313 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8314 /* Should always be exported to object file, see
8315 aarch64_force_relocation(). */
8316 gas_assert (!fixP
->fx_done
);
8317 gas_assert (seg
->use_rela_p
);
8320 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8321 /* Should always be exported to object file, see
8322 aarch64_force_relocation(). */
8323 fixP
->fx_r_type
= (ilp32_p
8324 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8325 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8326 gas_assert (!fixP
->fx_done
);
8327 gas_assert (seg
->use_rela_p
);
8330 case BFD_RELOC_AARCH64_ADD_LO12
:
8331 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8332 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8333 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8334 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8335 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8336 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8337 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8338 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8339 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8340 case BFD_RELOC_AARCH64_LDST128_LO12
:
8341 case BFD_RELOC_AARCH64_LDST16_LO12
:
8342 case BFD_RELOC_AARCH64_LDST32_LO12
:
8343 case BFD_RELOC_AARCH64_LDST64_LO12
:
8344 case BFD_RELOC_AARCH64_LDST8_LO12
:
8345 /* Should always be exported to object file, see
8346 aarch64_force_relocation(). */
8347 gas_assert (!fixP
->fx_done
);
8348 gas_assert (seg
->use_rela_p
);
8351 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8352 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8353 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8356 case BFD_RELOC_UNUSED
:
8357 /* An error will already have been reported. */
8361 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8362 _("unexpected %s fixup"),
8363 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8368 /* Free the allocated the struct aarch64_inst.
8369 N.B. currently there are very limited number of fix-up types actually use
8370 this field, so the impact on the performance should be minimal . */
8371 free (fixP
->tc_fix_data
.inst
);
8376 /* Translate internal representation of relocation info to BFD target
8380 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8383 bfd_reloc_code_real_type code
;
8385 reloc
= XNEW (arelent
);
8387 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8388 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8389 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8393 if (section
->use_rela_p
)
8394 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8396 fixp
->fx_offset
= reloc
->address
;
8398 reloc
->addend
= fixp
->fx_offset
;
8400 code
= fixp
->fx_r_type
;
8405 code
= BFD_RELOC_16_PCREL
;
8410 code
= BFD_RELOC_32_PCREL
;
8415 code
= BFD_RELOC_64_PCREL
;
8422 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8423 if (reloc
->howto
== NULL
)
8425 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8427 ("cannot represent %s relocation in this object file format"),
8428 bfd_get_reloc_code_name (code
));
8435 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8438 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8440 bfd_reloc_code_real_type type
;
8444 FIXME: @@ Should look at CPU word size. */
8451 type
= BFD_RELOC_16
;
8454 type
= BFD_RELOC_32
;
8457 type
= BFD_RELOC_64
;
8460 as_bad (_("cannot do %u-byte relocation"), size
);
8461 type
= BFD_RELOC_UNUSED
;
8465 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8469 aarch64_force_relocation (struct fix
*fixp
)
8471 switch (fixp
->fx_r_type
)
8473 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8474 /* Perform these "immediate" internal relocations
8475 even if the symbol is extern or weak. */
8478 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8479 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8480 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8481 /* Pseudo relocs that need to be fixed up according to
8485 case BFD_RELOC_AARCH64_ADD_LO12
:
8486 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8487 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8488 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8489 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8490 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8491 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8492 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8493 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8494 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8495 case BFD_RELOC_AARCH64_LDST128_LO12
:
8496 case BFD_RELOC_AARCH64_LDST16_LO12
:
8497 case BFD_RELOC_AARCH64_LDST32_LO12
:
8498 case BFD_RELOC_AARCH64_LDST64_LO12
:
8499 case BFD_RELOC_AARCH64_LDST8_LO12
:
8500 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8501 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8502 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8503 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8504 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8505 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8506 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8507 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8508 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8509 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8510 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8511 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8512 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8513 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8514 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8515 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8516 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8517 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8518 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8519 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8520 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8521 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8522 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8523 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8524 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8525 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8526 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8527 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8528 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8529 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8530 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8531 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8532 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8533 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8534 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8535 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8536 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8537 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8538 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8539 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8540 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8541 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8542 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8543 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8544 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8545 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8546 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8547 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8548 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8549 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8550 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8551 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8552 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8553 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8554 /* Always leave these relocations for the linker. */
8561 return generic_force_reloc (fixp
);
8566 /* Implement md_after_parse_args. This is the earliest time we need to decide
8567 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8570 aarch64_after_parse_args (void)
8572 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8575 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8576 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8577 aarch64_abi
= AARCH64_ABI_ILP32
;
8579 aarch64_abi
= AARCH64_ABI_LP64
;
8583 elf64_aarch64_target_format (void)
8586 /* FIXME: What to do for ilp32_p ? */
8587 if (target_big_endian
)
8588 return "elf64-bigaarch64-cloudabi";
8590 return "elf64-littleaarch64-cloudabi";
8592 if (target_big_endian
)
8593 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8595 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8600 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8602 elf_frob_symbol (symp
, puntp
);
8606 /* MD interface: Finalization. */
8608 /* A good place to do this, although this was probably not intended
8609 for this kind of use. We need to dump the literal pool before
8610 references are made to a null symbol pointer. */
8613 aarch64_cleanup (void)
8617 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8619 /* Put it at the end of the relevant section. */
8620 subseg_set (pool
->section
, pool
->sub_section
);
8626 /* Remove any excess mapping symbols generated for alignment frags in
8627 SEC. We may have created a mapping symbol before a zero byte
8628 alignment; remove it if there's a mapping symbol after the
8631 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8632 void *dummy ATTRIBUTE_UNUSED
)
8634 segment_info_type
*seginfo
= seg_info (sec
);
8637 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8640 for (fragp
= seginfo
->frchainP
->frch_root
;
8641 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8643 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8644 fragS
*next
= fragp
->fr_next
;
8646 /* Variable-sized frags have been converted to fixed size by
8647 this point. But if this was variable-sized to start with,
8648 there will be a fixed-size frag after it. So don't handle
8650 if (sym
== NULL
|| next
== NULL
)
8653 if (S_GET_VALUE (sym
) < next
->fr_address
)
8654 /* Not at the end of this frag. */
8656 know (S_GET_VALUE (sym
) == next
->fr_address
);
8660 if (next
->tc_frag_data
.first_map
!= NULL
)
8662 /* Next frag starts with a mapping symbol. Discard this
8664 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8668 if (next
->fr_next
== NULL
)
8670 /* This mapping symbol is at the end of the section. Discard
8672 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8673 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8677 /* As long as we have empty frags without any mapping symbols,
8679 /* If the next frag is non-empty and does not start with a
8680 mapping symbol, then this mapping symbol is required. */
8681 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8684 next
= next
->fr_next
;
8686 while (next
!= NULL
);
8691 /* Adjust the symbol table. */
8694 aarch64_adjust_symtab (void)
8697 /* Remove any overlapping mapping symbols generated by alignment frags. */
8698 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8699 /* Now do generic ELF adjustments. */
8700 elf_adjust_symtab ();
8705 checked_hash_insert (htab_t table
, const char *key
, void *value
)
8707 str_hash_insert (table
, key
, value
, 0);
8711 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
8713 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
8714 checked_hash_insert (table
, key
, value
);
8718 fill_instruction_hash_table (void)
8720 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8722 while (opcode
->name
!= NULL
)
8724 templates
*templ
, *new_templ
;
8725 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
8727 new_templ
= XNEW (templates
);
8728 new_templ
->opcode
= opcode
;
8729 new_templ
->next
= NULL
;
8732 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8735 new_templ
->next
= templ
->next
;
8736 templ
->next
= new_templ
;
8743 convert_to_upper (char *dst
, const char *src
, size_t num
)
8746 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8747 *dst
= TOUPPER (*src
);
8751 /* Assume STR point to a lower-case string, allocate, convert and return
8752 the corresponding upper-case string. */
8753 static inline const char*
8754 get_upper_str (const char *str
)
8757 size_t len
= strlen (str
);
8758 ret
= XNEWVEC (char, len
+ 1);
8759 convert_to_upper (ret
, str
, len
);
8763 /* MD interface: Initialization. */
8771 aarch64_ops_hsh
= str_htab_create ();
8772 aarch64_cond_hsh
= str_htab_create ();
8773 aarch64_shift_hsh
= str_htab_create ();
8774 aarch64_sys_regs_hsh
= str_htab_create ();
8775 aarch64_pstatefield_hsh
= str_htab_create ();
8776 aarch64_sys_regs_ic_hsh
= str_htab_create ();
8777 aarch64_sys_regs_dc_hsh
= str_htab_create ();
8778 aarch64_sys_regs_at_hsh
= str_htab_create ();
8779 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
8780 aarch64_sys_regs_sr_hsh
= str_htab_create ();
8781 aarch64_reg_hsh
= str_htab_create ();
8782 aarch64_barrier_opt_hsh
= str_htab_create ();
8783 aarch64_nzcv_hsh
= str_htab_create ();
8784 aarch64_pldop_hsh
= str_htab_create ();
8785 aarch64_hint_opt_hsh
= str_htab_create ();
8787 fill_instruction_hash_table ();
8789 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8790 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8791 (void *) (aarch64_sys_regs
+ i
));
8793 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8794 sysreg_hash_insert (aarch64_pstatefield_hsh
,
8795 aarch64_pstatefields
[i
].name
,
8796 (void *) (aarch64_pstatefields
+ i
));
8798 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8799 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
8800 aarch64_sys_regs_ic
[i
].name
,
8801 (void *) (aarch64_sys_regs_ic
+ i
));
8803 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8804 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
8805 aarch64_sys_regs_dc
[i
].name
,
8806 (void *) (aarch64_sys_regs_dc
+ i
));
8808 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8809 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
8810 aarch64_sys_regs_at
[i
].name
,
8811 (void *) (aarch64_sys_regs_at
+ i
));
8813 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8814 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8815 aarch64_sys_regs_tlbi
[i
].name
,
8816 (void *) (aarch64_sys_regs_tlbi
+ i
));
8818 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8819 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
8820 aarch64_sys_regs_sr
[i
].name
,
8821 (void *) (aarch64_sys_regs_sr
+ i
));
8823 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8824 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8825 (void *) (reg_names
+ i
));
8827 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8828 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8829 (void *) (nzcv_names
+ i
));
8831 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8833 const char *name
= aarch64_operand_modifiers
[i
].name
;
8834 checked_hash_insert (aarch64_shift_hsh
, name
,
8835 (void *) (aarch64_operand_modifiers
+ i
));
8836 /* Also hash the name in the upper case. */
8837 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8838 (void *) (aarch64_operand_modifiers
+ i
));
8841 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8844 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8845 the same condition code. */
8846 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8848 const char *name
= aarch64_conds
[i
].names
[j
];
8851 checked_hash_insert (aarch64_cond_hsh
, name
,
8852 (void *) (aarch64_conds
+ i
));
8853 /* Also hash the name in the upper case. */
8854 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8855 (void *) (aarch64_conds
+ i
));
8859 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8861 const char *name
= aarch64_barrier_options
[i
].name
;
8862 /* Skip xx00 - the unallocated values of option. */
8865 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8866 (void *) (aarch64_barrier_options
+ i
));
8867 /* Also hash the name in the upper case. */
8868 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8869 (void *) (aarch64_barrier_options
+ i
));
8872 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
8874 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
8875 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8876 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
8877 /* Also hash the name in the upper case. */
8878 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8879 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
8882 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8884 const char* name
= aarch64_prfops
[i
].name
;
8885 /* Skip the unallocated hint encodings. */
8888 checked_hash_insert (aarch64_pldop_hsh
, name
,
8889 (void *) (aarch64_prfops
+ i
));
8890 /* Also hash the name in the upper case. */
8891 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8892 (void *) (aarch64_prfops
+ i
));
8895 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8897 const char* name
= aarch64_hint_options
[i
].name
;
8898 const char* upper_name
= get_upper_str(name
);
8900 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8901 (void *) (aarch64_hint_options
+ i
));
8903 /* Also hash the name in the upper case if not the same. */
8904 if (strcmp (name
, upper_name
) != 0)
8905 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
8906 (void *) (aarch64_hint_options
+ i
));
8909 /* Set the cpu variant based on the command-line options. */
8911 mcpu_cpu_opt
= march_cpu_opt
;
8914 mcpu_cpu_opt
= &cpu_default
;
8916 cpu_variant
= *mcpu_cpu_opt
;
8918 /* Record the CPU type. */
8919 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8921 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8924 /* Command line processing. */
8926 const char *md_shortopts
= "m:";
8928 #ifdef AARCH64_BI_ENDIAN
8929 #define OPTION_EB (OPTION_MD_BASE + 0)
8930 #define OPTION_EL (OPTION_MD_BASE + 1)
8932 #if TARGET_BYTES_BIG_ENDIAN
8933 #define OPTION_EB (OPTION_MD_BASE + 0)
8935 #define OPTION_EL (OPTION_MD_BASE + 1)
8939 struct option md_longopts
[] = {
8941 {"EB", no_argument
, NULL
, OPTION_EB
},
8944 {"EL", no_argument
, NULL
, OPTION_EL
},
8946 {NULL
, no_argument
, NULL
, 0}
8949 size_t md_longopts_size
= sizeof (md_longopts
);
8951 struct aarch64_option_table
8953 const char *option
; /* Option name to match. */
8954 const char *help
; /* Help information. */
8955 int *var
; /* Variable to change. */
8956 int value
; /* What to change it to. */
8957 char *deprecated
; /* If non-null, print this message. */
8960 static struct aarch64_option_table aarch64_opts
[] = {
8961 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8962 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8964 #ifdef DEBUG_AARCH64
8965 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8966 #endif /* DEBUG_AARCH64 */
8967 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8969 {"mno-verbose-error", N_("do not output verbose error messages"),
8970 &verbose_error_p
, 0, NULL
},
8971 {NULL
, NULL
, NULL
, 0, NULL
}
8974 struct aarch64_cpu_option_table
8977 const aarch64_feature_set value
;
8978 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8980 const char *canonical_name
;
8983 /* This list should, at a minimum, contain all the cpu names
8984 recognized by GCC. */
8985 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8986 {"all", AARCH64_ANY
, NULL
},
8987 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8988 AARCH64_FEATURE_CRC
), "Cortex-A34"},
8989 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8990 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8991 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8992 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8993 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8994 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8995 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8996 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8997 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8998 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8999 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9000 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9002 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9003 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9005 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9006 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9008 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9009 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9010 | AARCH64_FEATURE_DOTPROD
9011 | AARCH64_FEATURE_SSBS
),
9013 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9014 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9015 | AARCH64_FEATURE_DOTPROD
9016 | AARCH64_FEATURE_SSBS
),
9018 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9019 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9020 | AARCH64_FEATURE_DOTPROD
9021 | AARCH64_FEATURE_SSBS
),
9023 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9024 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9025 | AARCH64_FEATURE_DOTPROD
9026 | AARCH64_FEATURE_SSBS
),
9028 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9030 | AARCH64_FEATURE_RCPC
9031 | AARCH64_FEATURE_DOTPROD
9032 | AARCH64_FEATURE_SSBS
9033 | AARCH64_FEATURE_PROFILE
),
9035 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9037 | AARCH64_FEATURE_RCPC
9038 | AARCH64_FEATURE_DOTPROD
9039 | AARCH64_FEATURE_SSBS
9040 | AARCH64_FEATURE_PROFILE
),
9042 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9043 AARCH64_FEATURE_DOTPROD
9044 | AARCH64_FEATURE_F16
9045 | AARCH64_FEATURE_FLAGM
9046 | AARCH64_FEATURE_PAC
9047 | AARCH64_FEATURE_PROFILE
9048 | AARCH64_FEATURE_RCPC
9049 | AARCH64_FEATURE_SSBS
),
9051 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9052 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9053 | AARCH64_FEATURE_DOTPROD
9054 | AARCH64_FEATURE_PROFILE
),
9056 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9057 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9058 "Samsung Exynos M1"},
9059 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9060 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9061 | AARCH64_FEATURE_RDMA
),
9063 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9064 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9065 | AARCH64_FEATURE_DOTPROD
9066 | AARCH64_FEATURE_SSBS
),
9068 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9069 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9070 | AARCH64_FEATURE_DOTPROD
9071 | AARCH64_FEATURE_PROFILE
),
9073 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9074 AARCH64_FEATURE_BFLOAT16
9075 | AARCH64_FEATURE_I8MM
9076 | AARCH64_FEATURE_F16
9077 | AARCH64_FEATURE_SVE
9078 | AARCH64_FEATURE_SVE2
9079 | AARCH64_FEATURE_SVE2_BITPERM
9080 | AARCH64_FEATURE_MEMTAG
9081 | AARCH64_FEATURE_RNG
),
9083 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9084 AARCH64_FEATURE_PROFILE
9085 | AARCH64_FEATURE_CVADP
9086 | AARCH64_FEATURE_SVE
9087 | AARCH64_FEATURE_SSBS
9088 | AARCH64_FEATURE_RNG
9089 | AARCH64_FEATURE_F16
9090 | AARCH64_FEATURE_BFLOAT16
9091 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9092 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9093 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9094 | AARCH64_FEATURE_RDMA
),
9095 "Qualcomm QDF24XX"},
9096 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9097 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9098 "Qualcomm Saphira"},
9099 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9100 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9102 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9103 AARCH64_FEATURE_CRYPTO
),
9105 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9106 in earlier releases and is superseded by 'xgene1' in all
9108 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9109 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9110 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9111 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9112 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9113 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9115 | AARCH64_FEATURE_RCPC
9116 | AARCH64_FEATURE_DOTPROD
9117 | AARCH64_FEATURE_SSBS
9118 | AARCH64_FEATURE_PROFILE
),
9120 {"generic", AARCH64_ARCH_V8
, NULL
},
9122 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9125 struct aarch64_arch_option_table
9128 const aarch64_feature_set value
;
9131 /* This list should, at a minimum, contain all the architecture names
9132 recognized by GCC. */
9133 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9134 {"all", AARCH64_ANY
},
9135 {"armv8-a", AARCH64_ARCH_V8
},
9136 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9137 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9138 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9139 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9140 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9141 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9142 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9143 {"armv8-r", AARCH64_ARCH_V8_R
},
9144 {NULL
, AARCH64_ARCH_NONE
}
9147 /* ISA extensions. */
9148 struct aarch64_option_cpu_value_table
9151 const aarch64_feature_set value
;
9152 const aarch64_feature_set require
; /* Feature dependencies. */
9155 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9156 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9158 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9159 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9160 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9162 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9164 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9165 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9166 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9168 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9170 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9172 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9173 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9174 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9175 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9176 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9177 AARCH64_FEATURE (AARCH64_FEATURE_FP
9178 | AARCH64_FEATURE_F16
, 0)},
9179 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9181 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9182 AARCH64_FEATURE (AARCH64_FEATURE_F16
9183 | AARCH64_FEATURE_SIMD
9184 | AARCH64_FEATURE_COMPNUM
, 0)},
9185 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9187 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9188 AARCH64_FEATURE (AARCH64_FEATURE_F16
9189 | AARCH64_FEATURE_SIMD
, 0)},
9190 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9192 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9194 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9196 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9198 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9200 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9202 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9204 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9205 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9206 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9208 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9210 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9212 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9213 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9214 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9215 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9216 | AARCH64_FEATURE_SM4
, 0)},
9217 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9218 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9219 | AARCH64_FEATURE_AES
, 0)},
9220 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9221 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9222 | AARCH64_FEATURE_SHA3
, 0)},
9223 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9224 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9225 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9227 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9229 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9230 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9231 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9232 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9233 {"csre", AARCH64_FEATURE (AARCH64_FEATURE_CSRE
, 0),
9235 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
9237 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
9239 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
9241 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9244 struct aarch64_long_option_table
9246 const char *option
; /* Substring to match. */
9247 const char *help
; /* Help information. */
9248 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9249 char *deprecated
; /* If non-null, print this message. */
9252 /* Transitive closure of features depending on set. */
9253 static aarch64_feature_set
9254 aarch64_feature_disable_set (aarch64_feature_set set
)
9256 const struct aarch64_option_cpu_value_table
*opt
;
9257 aarch64_feature_set prev
= 0;
9259 while (prev
!= set
) {
9261 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9262 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9263 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9268 /* Transitive closure of dependencies of set. */
9269 static aarch64_feature_set
9270 aarch64_feature_enable_set (aarch64_feature_set set
)
9272 const struct aarch64_option_cpu_value_table
*opt
;
9273 aarch64_feature_set prev
= 0;
9275 while (prev
!= set
) {
9277 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9278 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9279 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9285 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9286 bfd_boolean ext_only
)
9288 /* We insist on extensions being added before being removed. We achieve
9289 this by using the ADDING_VALUE variable to indicate whether we are
9290 adding an extension (1) or removing it (0) and only allowing it to
9291 change in the order -1 -> 1 -> 0. */
9292 int adding_value
= -1;
9293 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9295 /* Copy the feature set, so that we can modify it. */
9299 while (str
!= NULL
&& *str
!= 0)
9301 const struct aarch64_option_cpu_value_table
*opt
;
9302 const char *ext
= NULL
;
9309 as_bad (_("invalid architectural extension"));
9313 ext
= strchr (++str
, '+');
9319 optlen
= strlen (str
);
9321 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9323 if (adding_value
!= 0)
9328 else if (optlen
> 0)
9330 if (adding_value
== -1)
9332 else if (adding_value
!= 1)
9334 as_bad (_("must specify extensions to add before specifying "
9335 "those to remove"));
9342 as_bad (_("missing architectural extension"));
9346 gas_assert (adding_value
!= -1);
9348 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9349 if (strncmp (opt
->name
, str
, optlen
) == 0)
9351 aarch64_feature_set set
;
9353 /* Add or remove the extension. */
9356 set
= aarch64_feature_enable_set (opt
->value
);
9357 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9361 set
= aarch64_feature_disable_set (opt
->value
);
9362 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9367 if (opt
->name
== NULL
)
9369 as_bad (_("unknown architectural extension `%s'"), str
);
9380 aarch64_parse_cpu (const char *str
)
9382 const struct aarch64_cpu_option_table
*opt
;
9383 const char *ext
= strchr (str
, '+');
9389 optlen
= strlen (str
);
9393 as_bad (_("missing cpu name `%s'"), str
);
9397 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9398 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9400 mcpu_cpu_opt
= &opt
->value
;
9402 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9407 as_bad (_("unknown cpu `%s'"), str
);
9412 aarch64_parse_arch (const char *str
)
9414 const struct aarch64_arch_option_table
*opt
;
9415 const char *ext
= strchr (str
, '+');
9421 optlen
= strlen (str
);
9425 as_bad (_("missing architecture name `%s'"), str
);
9429 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9430 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9432 march_cpu_opt
= &opt
->value
;
9434 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9439 as_bad (_("unknown architecture `%s'\n"), str
);
9444 struct aarch64_option_abi_value_table
9447 enum aarch64_abi_type value
;
9450 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9451 {"ilp32", AARCH64_ABI_ILP32
},
9452 {"lp64", AARCH64_ABI_LP64
},
9456 aarch64_parse_abi (const char *str
)
9462 as_bad (_("missing abi name `%s'"), str
);
9466 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9467 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9469 aarch64_abi
= aarch64_abis
[i
].value
;
9473 as_bad (_("unknown abi `%s'\n"), str
);
9477 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9479 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9480 aarch64_parse_abi
, NULL
},
9481 #endif /* OBJ_ELF */
9482 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9483 aarch64_parse_cpu
, NULL
},
9484 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9485 aarch64_parse_arch
, NULL
},
9486 {NULL
, NULL
, 0, NULL
}
9490 md_parse_option (int c
, const char *arg
)
9492 struct aarch64_option_table
*opt
;
9493 struct aarch64_long_option_table
*lopt
;
9499 target_big_endian
= 1;
9505 target_big_endian
= 0;
9510 /* Listing option. Just ignore these, we don't support additional
9515 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9517 if (c
== opt
->option
[0]
9518 && ((arg
== NULL
&& opt
->option
[1] == 0)
9519 || streq (arg
, opt
->option
+ 1)))
9521 /* If the option is deprecated, tell the user. */
9522 if (opt
->deprecated
!= NULL
)
9523 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9524 arg
? arg
: "", _(opt
->deprecated
));
9526 if (opt
->var
!= NULL
)
9527 *opt
->var
= opt
->value
;
9533 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9535 /* These options are expected to have an argument. */
9536 if (c
== lopt
->option
[0]
9538 && strncmp (arg
, lopt
->option
+ 1,
9539 strlen (lopt
->option
+ 1)) == 0)
9541 /* If the option is deprecated, tell the user. */
9542 if (lopt
->deprecated
!= NULL
)
9543 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9544 _(lopt
->deprecated
));
9546 /* Call the sup-option parser. */
9547 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9558 md_show_usage (FILE * fp
)
9560 struct aarch64_option_table
*opt
;
9561 struct aarch64_long_option_table
*lopt
;
9563 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9565 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9566 if (opt
->help
!= NULL
)
9567 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9569 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9570 if (lopt
->help
!= NULL
)
9571 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9575 -EB assemble code for a big-endian cpu\n"));
9580 -EL assemble code for a little-endian cpu\n"));
9584 /* Parse a .cpu directive. */
9587 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9589 const struct aarch64_cpu_option_table
*opt
;
9595 name
= input_line_pointer
;
9596 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9597 input_line_pointer
++;
9598 saved_char
= *input_line_pointer
;
9599 *input_line_pointer
= 0;
9601 ext
= strchr (name
, '+');
9604 optlen
= ext
- name
;
9606 optlen
= strlen (name
);
9608 /* Skip the first "all" entry. */
9609 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9610 if (strlen (opt
->name
) == optlen
9611 && strncmp (name
, opt
->name
, optlen
) == 0)
9613 mcpu_cpu_opt
= &opt
->value
;
9615 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9618 cpu_variant
= *mcpu_cpu_opt
;
9620 *input_line_pointer
= saved_char
;
9621 demand_empty_rest_of_line ();
9624 as_bad (_("unknown cpu `%s'"), name
);
9625 *input_line_pointer
= saved_char
;
9626 ignore_rest_of_line ();
9630 /* Parse a .arch directive. */
9633 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9635 const struct aarch64_arch_option_table
*opt
;
9641 name
= input_line_pointer
;
9642 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9643 input_line_pointer
++;
9644 saved_char
= *input_line_pointer
;
9645 *input_line_pointer
= 0;
9647 ext
= strchr (name
, '+');
9650 optlen
= ext
- name
;
9652 optlen
= strlen (name
);
9654 /* Skip the first "all" entry. */
9655 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9656 if (strlen (opt
->name
) == optlen
9657 && strncmp (name
, opt
->name
, optlen
) == 0)
9659 mcpu_cpu_opt
= &opt
->value
;
9661 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9664 cpu_variant
= *mcpu_cpu_opt
;
9666 *input_line_pointer
= saved_char
;
9667 demand_empty_rest_of_line ();
9671 as_bad (_("unknown architecture `%s'\n"), name
);
9672 *input_line_pointer
= saved_char
;
9673 ignore_rest_of_line ();
9676 /* Parse a .arch_extension directive. */
9679 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9682 char *ext
= input_line_pointer
;;
9684 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9685 input_line_pointer
++;
9686 saved_char
= *input_line_pointer
;
9687 *input_line_pointer
= 0;
9689 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9692 cpu_variant
= *mcpu_cpu_opt
;
9694 *input_line_pointer
= saved_char
;
9695 demand_empty_rest_of_line ();
9698 /* Copy symbol information. */
9701 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9703 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
9707 /* Same as elf_copy_symbol_attributes, but without copying st_other.
9708 This is needed so AArch64 specific st_other values can be independently
9709 specified for an IFUNC resolver (that is called by the dynamic linker)
9710 and the symbol it resolves (aliased to the resolver). In particular,
9711 if a function symbol has special st_other value set via directives,
9712 then attaching an IFUNC resolver to that symbol should not override
9713 the st_other setting. Requiring the directive on the IFUNC resolver
9714 symbol would be unexpected and problematic in C code, where the two
9715 symbols appear as two independent function declarations. */
9718 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
9720 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
9721 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
9724 if (destelf
->size
== NULL
)
9725 destelf
->size
= XNEW (expressionS
);
9726 *destelf
->size
= *srcelf
->size
;
9730 free (destelf
->size
);
9731 destelf
->size
= NULL
;
9733 S_SET_SIZE (dest
, S_GET_SIZE (src
));