1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
71 #define DEFAULT_ARCH "aarch64"
74 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
75 static const char *default_arch
= DEFAULT_ARCH
;
77 /* AArch64 ABI for the output file. */
78 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
80 /* When non-zero, program to a 32-bit model, in which the C data types
81 int, long and all pointer types are 32-bit objects (ILP32); or to a
82 64-bit model, in which the C int type is 32-bits but the C long type
83 and all pointer types are 64-bit objects (LP64). */
84 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
99 /* Bits for DEFINED field in vector_type_el. */
100 #define NTA_HASTYPE 1
101 #define NTA_HASINDEX 2
102 #define NTA_HASVARWIDTH 4
104 struct vector_type_el
106 enum vector_el_type type
;
107 unsigned char defined
;
112 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
116 bfd_reloc_code_real_type type
;
119 enum aarch64_opnd opnd
;
121 unsigned need_libopcodes_p
: 1;
124 struct aarch64_instruction
126 /* libopcodes structure for instruction intermediate representation. */
128 /* Record assembly errors found during the parsing. */
131 enum aarch64_operand_error_kind kind
;
134 /* The condition that appears in the assembly line. */
136 /* Relocation information (including the GAS internal fixup). */
138 /* Need to generate an immediate in the literal pool. */
139 unsigned gen_lit_pool
: 1;
142 typedef struct aarch64_instruction aarch64_instruction
;
144 static aarch64_instruction inst
;
146 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
147 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
149 /* Diagnostics inline function utilities.
151 These are lightweight utilities which should only be called by parse_operands
152 and other parsers. GAS processes each assembly line by parsing it against
153 instruction template(s), in the case of multiple templates (for the same
154 mnemonic name), those templates are tried one by one until one succeeds or
155 all fail. An assembly line may fail a few templates before being
156 successfully parsed; an error saved here in most cases is not a user error
157 but an error indicating the current template is not the right template.
158 Therefore it is very important that errors can be saved at a low cost during
159 the parsing; we don't want to slow down the whole parsing by recording
160 non-user errors in detail.
162 Remember that the objective is to help GAS pick up the most appropriate
163 error message in the case of multiple templates, e.g. FMOV which has 8
169 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
170 inst
.parsing_error
.error
= NULL
;
173 static inline bfd_boolean
176 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
179 static inline const char *
180 get_error_message (void)
182 return inst
.parsing_error
.error
;
185 static inline enum aarch64_operand_error_kind
186 get_error_kind (void)
188 return inst
.parsing_error
.kind
;
192 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
194 inst
.parsing_error
.kind
= kind
;
195 inst
.parsing_error
.error
= error
;
199 set_recoverable_error (const char *error
)
201 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
204 /* Use the DESC field of the corresponding aarch64_operand entry to compose
205 the error message. */
207 set_default_error (void)
209 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
213 set_syntax_error (const char *error
)
215 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
219 set_first_syntax_error (const char *error
)
222 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
226 set_fatal_syntax_error (const char *error
)
228 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
231 /* Number of littlenums required to hold an extended precision number. */
232 #define MAX_LITTLENUMS 6
234 /* Return value for certain parsers when the parsing fails; those parsers
235 return the information of the parsed result, e.g. register number, on
237 #define PARSE_FAIL -1
239 /* This is an invalid condition code that means no conditional field is
241 #define COND_ALWAYS 0x10
245 const char *template;
251 const char *template;
258 bfd_reloc_code_real_type reloc
;
261 /* Macros to define the register types and masks for the purpose
264 #undef AARCH64_REG_TYPES
265 #define AARCH64_REG_TYPES \
266 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
267 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
268 BASIC_REG_TYPE(SP_32) /* wsp */ \
269 BASIC_REG_TYPE(SP_64) /* sp */ \
270 BASIC_REG_TYPE(Z_32) /* wzr */ \
271 BASIC_REG_TYPE(Z_64) /* xzr */ \
272 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
273 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
274 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
275 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
276 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
277 BASIC_REG_TYPE(VN) /* v[0-31] */ \
278 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
279 BASIC_REG_TYPE(PN) /* p[0-15] */ \
280 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
281 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
282 /* Typecheck: same, plus SVE registers. */ \
283 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
285 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
286 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
287 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
288 /* Typecheck: same, plus SVE registers. */ \
289 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
292 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
293 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
295 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
296 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
298 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
299 /* Typecheck: any [BHSDQ]P FP. */ \
300 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
301 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
302 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
305 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
306 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
307 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
308 be used for SVE instructions, since Zn and Pn are valid symbols \
309 in other contexts. */ \
310 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
312 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
313 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
314 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
315 | REG_TYPE(ZN) | REG_TYPE(PN)) \
316 /* Any integer register; used for error messages only. */ \
317 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
320 /* Pseudo type to mark the end of the enumerator sequence. */ \
323 #undef BASIC_REG_TYPE
324 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
325 #undef MULTI_REG_TYPE
326 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
328 /* Register type enumerators. */
329 typedef enum aarch64_reg_type_
331 /* A list of REG_TYPE_*. */
335 #undef BASIC_REG_TYPE
336 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
338 #define REG_TYPE(T) (1 << REG_TYPE_##T)
339 #undef MULTI_REG_TYPE
340 #define MULTI_REG_TYPE(T,V) V,
342 /* Structure for a hash table entry for a register. */
346 unsigned char number
;
347 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
348 unsigned char builtin
;
351 /* Values indexed by aarch64_reg_type to assist the type checking. */
352 static const unsigned reg_type_masks
[] =
357 #undef BASIC_REG_TYPE
359 #undef MULTI_REG_TYPE
360 #undef AARCH64_REG_TYPES
362 /* Diagnostics used when we don't get a register of the expected type.
363 Note: this has to synchronized with aarch64_reg_type definitions
366 get_reg_expected_msg (aarch64_reg_type reg_type
)
373 msg
= N_("integer 32-bit register expected");
376 msg
= N_("integer 64-bit register expected");
379 msg
= N_("integer register expected");
381 case REG_TYPE_R64_SP
:
382 msg
= N_("64-bit integer or SP register expected");
384 case REG_TYPE_SVE_BASE
:
385 msg
= N_("base register expected");
388 msg
= N_("integer or zero register expected");
390 case REG_TYPE_SVE_OFFSET
:
391 msg
= N_("offset register expected");
394 msg
= N_("integer or SP register expected");
396 case REG_TYPE_R_Z_SP
:
397 msg
= N_("integer, zero or SP register expected");
400 msg
= N_("8-bit SIMD scalar register expected");
403 msg
= N_("16-bit SIMD scalar or floating-point half precision "
404 "register expected");
407 msg
= N_("32-bit SIMD scalar or floating-point single precision "
408 "register expected");
411 msg
= N_("64-bit SIMD scalar or floating-point double precision "
412 "register expected");
415 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
416 "register expected");
418 case REG_TYPE_R_Z_BHSDQ_V
:
419 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
420 msg
= N_("register expected");
422 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
423 msg
= N_("SIMD scalar or floating-point register expected");
425 case REG_TYPE_VN
: /* any V reg */
426 msg
= N_("vector register expected");
429 msg
= N_("SVE vector register expected");
432 msg
= N_("SVE predicate register expected");
435 as_fatal (_("invalid register type %d"), reg_type
);
440 /* Some well known registers that we refer to directly elsewhere. */
443 /* Instructions take 4 bytes in the object file. */
446 static struct hash_control
*aarch64_ops_hsh
;
447 static struct hash_control
*aarch64_cond_hsh
;
448 static struct hash_control
*aarch64_shift_hsh
;
449 static struct hash_control
*aarch64_sys_regs_hsh
;
450 static struct hash_control
*aarch64_pstatefield_hsh
;
451 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
452 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
453 static struct hash_control
*aarch64_sys_regs_at_hsh
;
454 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
455 static struct hash_control
*aarch64_reg_hsh
;
456 static struct hash_control
*aarch64_barrier_opt_hsh
;
457 static struct hash_control
*aarch64_nzcv_hsh
;
458 static struct hash_control
*aarch64_pldop_hsh
;
459 static struct hash_control
*aarch64_hint_opt_hsh
;
461 /* Stuff needed to resolve the label ambiguity
470 static symbolS
*last_label_seen
;
472 /* Literal pool structure. Held on a per-section
473 and per-sub-section basis. */
475 #define MAX_LITERAL_POOL_SIZE 1024
476 typedef struct literal_expression
479 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
480 LITTLENUM_TYPE
* bignum
;
481 } literal_expression
;
483 typedef struct literal_pool
485 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
486 unsigned int next_free_entry
;
492 struct literal_pool
*next
;
495 /* Pointer to a linked list of literal pools. */
496 static literal_pool
*list_of_pools
= NULL
;
500 /* This array holds the chars that always start a comment. If the
501 pre-processor is disabled, these aren't very useful. */
502 const char comment_chars
[] = "";
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output. */
507 /* Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output. */
510 /* Also note that comments like this one will always work. */
511 const char line_comment_chars
[] = "#";
513 const char line_separator_chars
[] = ";";
515 /* Chars that can be used to separate mant
516 from exp in floating point numbers. */
517 const char EXP_CHARS
[] = "eE";
519 /* Chars that mean this number is a floating point constant. */
523 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
525 /* Prefix character that indicates the start of an immediate value. */
526 #define is_immediate_prefix(C) ((C) == '#')
528 /* Separator character handling. */
530 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
532 static inline bfd_boolean
533 skip_past_char (char **str
, char c
)
544 #define skip_past_comma(str) skip_past_char (str, ',')
546 /* Arithmetic expressions (possibly involving symbols). */
548 static bfd_boolean in_my_get_expression_p
= FALSE
;
550 /* Third argument to my_get_expression. */
551 #define GE_NO_PREFIX 0
552 #define GE_OPT_PREFIX 1
554 /* Return TRUE if the string pointed by *STR is successfully parsed
555 as an valid expression; *EP will be filled with the information of
556 such an expression. Otherwise return FALSE. */
559 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
564 int prefix_present_p
= 0;
571 if (is_immediate_prefix (**str
))
574 prefix_present_p
= 1;
581 memset (ep
, 0, sizeof (expressionS
));
583 save_in
= input_line_pointer
;
584 input_line_pointer
= *str
;
585 in_my_get_expression_p
= TRUE
;
586 seg
= expression (ep
);
587 in_my_get_expression_p
= FALSE
;
589 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
591 /* We found a bad expression in md_operand(). */
592 *str
= input_line_pointer
;
593 input_line_pointer
= save_in
;
594 if (prefix_present_p
&& ! error_p ())
595 set_fatal_syntax_error (_("bad expression"));
597 set_first_syntax_error (_("bad expression"));
602 if (seg
!= absolute_section
603 && seg
!= text_section
604 && seg
!= data_section
605 && seg
!= bss_section
&& seg
!= undefined_section
)
607 set_syntax_error (_("bad segment"));
608 *str
= input_line_pointer
;
609 input_line_pointer
= save_in
;
616 *str
= input_line_pointer
;
617 input_line_pointer
= save_in
;
621 /* Turn a string in input_line_pointer into a floating point constant
622 of type TYPE, and store the appropriate bytes in *LITP. The number
623 of LITTLENUMS emitted is stored in *SIZEP. An error message is
624 returned, or NULL on OK. */
627 md_atof (int type
, char *litP
, int *sizeP
)
629 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
632 /* We handle all bad expressions here, so that we can report the faulty
633 instruction in the error message. */
635 md_operand (expressionS
* exp
)
637 if (in_my_get_expression_p
)
638 exp
->X_op
= O_illegal
;
641 /* Immediate values. */
643 /* Errors may be set multiple times during parsing or bit encoding
644 (particularly in the Neon bits), but usually the earliest error which is set
645 will be the most meaningful. Avoid overwriting it with later (cascading)
646 errors by calling this function. */
649 first_error (const char *error
)
652 set_syntax_error (error
);
655 /* Similar to first_error, but this function accepts formatted error
658 first_error_fmt (const char *format
, ...)
663 /* N.B. this single buffer will not cause error messages for different
664 instructions to pollute each other; this is because at the end of
665 processing of each assembly line, error message if any will be
666 collected by as_bad. */
667 static char buffer
[size
];
671 int ret ATTRIBUTE_UNUSED
;
672 va_start (args
, format
);
673 ret
= vsnprintf (buffer
, size
, format
, args
);
674 know (ret
<= size
- 1 && ret
>= 0);
676 set_syntax_error (buffer
);
680 /* Register parsing. */
682 /* Generic register parser which is called by other specialized
684 CCP points to what should be the beginning of a register name.
685 If it is indeed a valid register name, advance CCP over it and
686 return the reg_entry structure; otherwise return NULL.
687 It does not issue diagnostics. */
690 parse_reg (char **ccp
)
696 #ifdef REGISTER_PREFIX
697 if (*start
!= REGISTER_PREFIX
)
703 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
708 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
710 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
719 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
722 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
724 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
727 /* Try to parse a base or offset register. Allow SVE base and offset
728 registers if REG_TYPE includes SVE registers. Return the register
729 entry on success, setting *QUALIFIER to the register qualifier.
730 Return null otherwise.
732 Note that this function does not issue any diagnostics. */
734 static const reg_entry
*
735 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
736 aarch64_opnd_qualifier_t
*qualifier
)
739 const reg_entry
*reg
= parse_reg (&str
);
749 *qualifier
= AARCH64_OPND_QLF_W
;
755 *qualifier
= AARCH64_OPND_QLF_X
;
759 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
762 switch (TOLOWER (str
[1]))
765 *qualifier
= AARCH64_OPND_QLF_S_S
;
768 *qualifier
= AARCH64_OPND_QLF_S_D
;
785 /* Try to parse a base or offset register. Return the register entry
786 on success, setting *QUALIFIER to the register qualifier. Return null
789 Note that this function does not issue any diagnostics. */
791 static const reg_entry
*
792 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
794 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
797 /* Parse the qualifier of a vector register or vector element of type
798 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
799 succeeds; otherwise return FALSE.
801 Accept only one occurrence of:
802 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
805 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
806 struct vector_type_el
*parsed_type
, char **str
)
810 unsigned element_size
;
811 enum vector_el_type type
;
814 gas_assert (*ptr
== '.');
817 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
822 width
= strtoul (ptr
, &ptr
, 10);
823 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
825 first_error_fmt (_("bad size %d in vector width specifier"), width
);
830 switch (TOLOWER (*ptr
))
849 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
858 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
860 first_error (_("missing element size"));
863 if (width
!= 0 && width
* element_size
!= 64
864 && width
* element_size
!= 128
865 && !(width
== 2 && element_size
== 16)
866 && !(width
== 4 && element_size
== 8))
869 ("invalid element size %d and vector size combination %c"),
875 parsed_type
->type
= type
;
876 parsed_type
->width
= width
;
883 /* *STR contains an SVE zero/merge predication suffix. Parse it into
884 *PARSED_TYPE and point *STR at the end of the suffix. */
887 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
892 gas_assert (*ptr
== '/');
894 switch (TOLOWER (*ptr
))
897 parsed_type
->type
= NT_zero
;
900 parsed_type
->type
= NT_merge
;
903 if (*ptr
!= '\0' && *ptr
!= ',')
904 first_error_fmt (_("unexpected character `%c' in predication type"),
907 first_error (_("missing predication type"));
910 parsed_type
->width
= 0;
915 /* Parse a register of the type TYPE.
917 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
918 name or the parsed register is not of TYPE.
920 Otherwise return the register number, and optionally fill in the actual
921 type of the register in *RTYPE when multiple alternatives were given, and
922 return the register shape and element index information in *TYPEINFO.
924 IN_REG_LIST should be set with TRUE if the caller is parsing a register
928 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
929 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
932 const reg_entry
*reg
= parse_reg (&str
);
933 struct vector_type_el atype
;
934 struct vector_type_el parsetype
;
935 bfd_boolean is_typed_vecreg
= FALSE
;
938 atype
.type
= NT_invtype
;
946 set_default_error ();
950 if (! aarch64_check_reg_type (reg
, type
))
952 DEBUG_TRACE ("reg type check failed");
953 set_default_error ();
958 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
959 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
963 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
968 if (!parse_predication_for_operand (&parsetype
, &str
))
972 /* Register if of the form Vn.[bhsdq]. */
973 is_typed_vecreg
= TRUE
;
975 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
977 /* The width is always variable; we don't allow an integer width
979 gas_assert (parsetype
.width
== 0);
980 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
982 else if (parsetype
.width
== 0)
983 /* Expect index. In the new scheme we cannot have
984 Vn.[bhsdq] represent a scalar. Therefore any
985 Vn.[bhsdq] should have an index following it.
986 Except in reglists of course. */
987 atype
.defined
|= NTA_HASINDEX
;
989 atype
.defined
|= NTA_HASTYPE
;
991 atype
.type
= parsetype
.type
;
992 atype
.width
= parsetype
.width
;
995 if (skip_past_char (&str
, '['))
999 /* Reject Sn[index] syntax. */
1000 if (!is_typed_vecreg
)
1002 first_error (_("this type of register can't be indexed"));
1008 first_error (_("index not allowed inside register list"));
1012 atype
.defined
|= NTA_HASINDEX
;
1014 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1016 if (exp
.X_op
!= O_constant
)
1018 first_error (_("constant expression required"));
1022 if (! skip_past_char (&str
, ']'))
1025 atype
.index
= exp
.X_add_number
;
1027 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1029 /* Indexed vector register expected. */
1030 first_error (_("indexed vector register expected"));
1034 /* A vector reg Vn should be typed or indexed. */
1035 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1037 first_error (_("invalid use of vector register"));
1053 Return the register number on success; return PARSE_FAIL otherwise.
1055 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1056 the register (e.g. NEON double or quad reg when either has been requested).
1058 If this is a NEON vector register with additional type information, fill
1059 in the struct pointed to by VECTYPE (if non-NULL).
1061 This parser does not handle register list. */
1064 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1065 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1067 struct vector_type_el atype
;
1069 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1070 /*in_reg_list= */ FALSE
);
1072 if (reg
== PARSE_FAIL
)
1083 static inline bfd_boolean
1084 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1088 && e1
.defined
== e2
.defined
1089 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1092 /* This function parses a list of vector registers of type TYPE.
1093 On success, it returns the parsed register list information in the
1094 following encoded format:
1096 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1097 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1099 The information of the register shape and/or index is returned in
1102 It returns PARSE_FAIL if the register list is invalid.
1104 The list contains one to four registers.
1105 Each register can be one of:
1108 All <T> should be identical.
1109 All <index> should be identical.
1110 There are restrictions on <Vt> numbers which are checked later
1111 (by reg_list_valid_p). */
1114 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1115 struct vector_type_el
*vectype
)
1119 struct vector_type_el typeinfo
, typeinfo_first
;
1124 bfd_boolean error
= FALSE
;
1125 bfd_boolean expect_index
= FALSE
;
1129 set_syntax_error (_("expecting {"));
1135 typeinfo_first
.defined
= 0;
1136 typeinfo_first
.type
= NT_invtype
;
1137 typeinfo_first
.width
= -1;
1138 typeinfo_first
.index
= 0;
1147 str
++; /* skip over '-' */
1150 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1151 /*in_reg_list= */ TRUE
);
1152 if (val
== PARSE_FAIL
)
1154 set_first_syntax_error (_("invalid vector register in list"));
1158 /* reject [bhsd]n */
1159 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1161 set_first_syntax_error (_("invalid scalar register in list"));
1166 if (typeinfo
.defined
& NTA_HASINDEX
)
1167 expect_index
= TRUE
;
1171 if (val
< val_range
)
1173 set_first_syntax_error
1174 (_("invalid range in vector register list"));
1183 typeinfo_first
= typeinfo
;
1184 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1186 set_first_syntax_error
1187 (_("type mismatch in vector register list"));
1192 for (i
= val_range
; i
<= val
; i
++)
1194 ret_val
|= i
<< (5 * nb_regs
);
1199 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1201 skip_whitespace (str
);
1204 set_first_syntax_error (_("end of vector register list not found"));
1209 skip_whitespace (str
);
1213 if (skip_past_char (&str
, '['))
1217 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1218 if (exp
.X_op
!= O_constant
)
1220 set_first_syntax_error (_("constant expression required."));
1223 if (! skip_past_char (&str
, ']'))
1226 typeinfo_first
.index
= exp
.X_add_number
;
1230 set_first_syntax_error (_("expected index"));
1237 set_first_syntax_error (_("too many registers in vector register list"));
1240 else if (nb_regs
== 0)
1242 set_first_syntax_error (_("empty vector register list"));
1248 *vectype
= typeinfo_first
;
1250 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1253 /* Directives: register aliases. */
1256 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1261 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1264 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1267 /* Only warn about a redefinition if it's not defined as the
1269 else if (new->number
!= number
|| new->type
!= type
)
1270 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1275 name
= xstrdup (str
);
1276 new = XNEW (reg_entry
);
1279 new->number
= number
;
1281 new->builtin
= FALSE
;
1283 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1289 /* Look for the .req directive. This is of the form:
1291 new_register_name .req existing_register_name
1293 If we find one, or if it looks sufficiently like one that we want to
1294 handle any error here, return TRUE. Otherwise return FALSE. */
1297 create_register_alias (char *newname
, char *p
)
1299 const reg_entry
*old
;
1300 char *oldname
, *nbuf
;
1303 /* The input scrubber ensures that whitespace after the mnemonic is
1304 collapsed to single spaces. */
1306 if (strncmp (oldname
, " .req ", 6) != 0)
1310 if (*oldname
== '\0')
1313 old
= hash_find (aarch64_reg_hsh
, oldname
);
1316 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1320 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1321 the desired alias name, and p points to its end. If not, then
1322 the desired alias name is in the global original_case_string. */
1323 #ifdef TC_CASE_SENSITIVE
1326 newname
= original_case_string
;
1327 nlen
= strlen (newname
);
1330 nbuf
= xmemdup0 (newname
, nlen
);
1332 /* Create aliases under the new name as stated; an all-lowercase
1333 version of the new name; and an all-uppercase version of the new
1335 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1337 for (p
= nbuf
; *p
; p
++)
1340 if (strncmp (nbuf
, newname
, nlen
))
1342 /* If this attempt to create an additional alias fails, do not bother
1343 trying to create the all-lower case alias. We will fail and issue
1344 a second, duplicate error message. This situation arises when the
1345 programmer does something like:
1348 The second .req creates the "Foo" alias but then fails to create
1349 the artificial FOO alias because it has already been created by the
1351 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1358 for (p
= nbuf
; *p
; p
++)
1361 if (strncmp (nbuf
, newname
, nlen
))
1362 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1369 /* Should never be called, as .req goes between the alias and the
1370 register name, not at the beginning of the line. */
1372 s_req (int a ATTRIBUTE_UNUSED
)
1374 as_bad (_("invalid syntax for .req directive"));
1377 /* The .unreq directive deletes an alias which was previously defined
1378 by .req. For example:
1384 s_unreq (int a ATTRIBUTE_UNUSED
)
1389 name
= input_line_pointer
;
1391 while (*input_line_pointer
!= 0
1392 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1393 ++input_line_pointer
;
1395 saved_char
= *input_line_pointer
;
1396 *input_line_pointer
= 0;
1399 as_bad (_("invalid syntax for .unreq directive"));
1402 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1405 as_bad (_("unknown register alias '%s'"), name
);
1406 else if (reg
->builtin
)
1407 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1414 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1415 free ((char *) reg
->name
);
1418 /* Also locate the all upper case and all lower case versions.
1419 Do not complain if we cannot find one or the other as it
1420 was probably deleted above. */
1422 nbuf
= strdup (name
);
1423 for (p
= nbuf
; *p
; p
++)
1425 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1428 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1429 free ((char *) reg
->name
);
1433 for (p
= nbuf
; *p
; p
++)
1435 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1438 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1439 free ((char *) reg
->name
);
1447 *input_line_pointer
= saved_char
;
1448 demand_empty_rest_of_line ();
1451 /* Directives: Instruction set selection. */
1454 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1455 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1456 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1457 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1459 /* Create a new mapping symbol for the transition to STATE. */
1462 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1465 const char *symname
;
1472 type
= BSF_NO_FLAGS
;
1476 type
= BSF_NO_FLAGS
;
1482 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1483 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1485 /* Save the mapping symbols for future reference. Also check that
1486 we do not place two mapping symbols at the same offset within a
1487 frag. We'll handle overlap between frags in
1488 check_mapping_symbols.
1490 If .fill or other data filling directive generates zero sized data,
1491 the mapping symbol for the following code will have the same value
1492 as the one generated for the data filling directive. In this case,
1493 we replace the old symbol with the new one at the same address. */
1496 if (frag
->tc_frag_data
.first_map
!= NULL
)
1498 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1499 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1502 frag
->tc_frag_data
.first_map
= symbolP
;
1504 if (frag
->tc_frag_data
.last_map
!= NULL
)
1506 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1507 S_GET_VALUE (symbolP
));
1508 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1509 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1512 frag
->tc_frag_data
.last_map
= symbolP
;
1515 /* We must sometimes convert a region marked as code to data during
1516 code alignment, if an odd number of bytes have to be padded. The
1517 code mapping symbol is pushed to an aligned address. */
1520 insert_data_mapping_symbol (enum mstate state
,
1521 valueT value
, fragS
* frag
, offsetT bytes
)
1523 /* If there was already a mapping symbol, remove it. */
1524 if (frag
->tc_frag_data
.last_map
!= NULL
1525 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1526 frag
->fr_address
+ value
)
1528 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1532 know (frag
->tc_frag_data
.first_map
== symp
);
1533 frag
->tc_frag_data
.first_map
= NULL
;
1535 frag
->tc_frag_data
.last_map
= NULL
;
1536 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1539 make_mapping_symbol (MAP_DATA
, value
, frag
);
1540 make_mapping_symbol (state
, value
+ bytes
, frag
);
1543 static void mapping_state_2 (enum mstate state
, int max_chars
);
1545 /* Set the mapping state to STATE. Only call this when about to
1546 emit some STATE bytes to the file. */
1549 mapping_state (enum mstate state
)
1551 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1553 if (state
== MAP_INSN
)
1554 /* AArch64 instructions require 4-byte alignment. When emitting
1555 instructions into any section, record the appropriate section
1557 record_alignment (now_seg
, 2);
1559 if (mapstate
== state
)
1560 /* The mapping symbol has already been emitted.
1561 There is nothing else to do. */
1564 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1565 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1566 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1567 evaluated later in the next else. */
1569 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1571 /* Only add the symbol if the offset is > 0:
1572 if we're at the first frag, check it's size > 0;
1573 if we're not at the first frag, then for sure
1574 the offset is > 0. */
1575 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1576 const int add_symbol
= (frag_now
!= frag_first
)
1577 || (frag_now_fix () > 0);
1580 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1584 mapping_state_2 (state
, 0);
1587 /* Same as mapping_state, but MAX_CHARS bytes have already been
1588 allocated. Put the mapping symbol that far back. */
1591 mapping_state_2 (enum mstate state
, int max_chars
)
1593 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1595 if (!SEG_NORMAL (now_seg
))
1598 if (mapstate
== state
)
1599 /* The mapping symbol has already been emitted.
1600 There is nothing else to do. */
1603 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1604 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1607 #define mapping_state(x) /* nothing */
1608 #define mapping_state_2(x, y) /* nothing */
1611 /* Directives: sectioning and alignment. */
1614 s_bss (int ignore ATTRIBUTE_UNUSED
)
1616 /* We don't support putting frags in the BSS segment, we fake it by
1617 marking in_bss, then looking at s_skip for clues. */
1618 subseg_set (bss_section
, 0);
1619 demand_empty_rest_of_line ();
1620 mapping_state (MAP_DATA
);
1624 s_even (int ignore ATTRIBUTE_UNUSED
)
1626 /* Never make frag if expect extra pass. */
1628 frag_align (1, 0, 0);
1630 record_alignment (now_seg
, 1);
1632 demand_empty_rest_of_line ();
1635 /* Directives: Literal pools. */
1637 static literal_pool
*
1638 find_literal_pool (int size
)
1642 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1644 if (pool
->section
== now_seg
1645 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1652 static literal_pool
*
1653 find_or_make_literal_pool (int size
)
1655 /* Next literal pool ID number. */
1656 static unsigned int latest_pool_num
= 1;
1659 pool
= find_literal_pool (size
);
1663 /* Create a new pool. */
1664 pool
= XNEW (literal_pool
);
1668 /* Currently we always put the literal pool in the current text
1669 section. If we were generating "small" model code where we
1670 knew that all code and initialised data was within 1MB then
1671 we could output literals to mergeable, read-only data
1674 pool
->next_free_entry
= 0;
1675 pool
->section
= now_seg
;
1676 pool
->sub_section
= now_subseg
;
1678 pool
->next
= list_of_pools
;
1679 pool
->symbol
= NULL
;
1681 /* Add it to the list. */
1682 list_of_pools
= pool
;
1685 /* New pools, and emptied pools, will have a NULL symbol. */
1686 if (pool
->symbol
== NULL
)
1688 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1689 (valueT
) 0, &zero_address_frag
);
1690 pool
->id
= latest_pool_num
++;
1697 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1698 Return TRUE on success, otherwise return FALSE. */
1700 add_to_lit_pool (expressionS
*exp
, int size
)
1705 pool
= find_or_make_literal_pool (size
);
1707 /* Check if this literal value is already in the pool. */
1708 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1710 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1712 if ((litexp
->X_op
== exp
->X_op
)
1713 && (exp
->X_op
== O_constant
)
1714 && (litexp
->X_add_number
== exp
->X_add_number
)
1715 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1718 if ((litexp
->X_op
== exp
->X_op
)
1719 && (exp
->X_op
== O_symbol
)
1720 && (litexp
->X_add_number
== exp
->X_add_number
)
1721 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1722 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1726 /* Do we need to create a new entry? */
1727 if (entry
== pool
->next_free_entry
)
1729 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1731 set_syntax_error (_("literal pool overflow"));
1735 pool
->literals
[entry
].exp
= *exp
;
1736 pool
->next_free_entry
+= 1;
1737 if (exp
->X_op
== O_big
)
1739 /* PR 16688: Bignums are held in a single global array. We must
1740 copy and preserve that value now, before it is overwritten. */
1741 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1743 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1744 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1747 pool
->literals
[entry
].bignum
= NULL
;
1750 exp
->X_op
= O_symbol
;
1751 exp
->X_add_number
= ((int) entry
) * size
;
1752 exp
->X_add_symbol
= pool
->symbol
;
1757 /* Can't use symbol_new here, so have to create a symbol and then at
1758 a later date assign it a value. That's what these functions do. */
1761 symbol_locate (symbolS
* symbolP
,
1762 const char *name
,/* It is copied, the caller can modify. */
1763 segT segment
, /* Segment identifier (SEG_<something>). */
1764 valueT valu
, /* Symbol value. */
1765 fragS
* frag
) /* Associated fragment. */
1768 char *preserved_copy_of_name
;
1770 name_length
= strlen (name
) + 1; /* +1 for \0. */
1771 obstack_grow (¬es
, name
, name_length
);
1772 preserved_copy_of_name
= obstack_finish (¬es
);
1774 #ifdef tc_canonicalize_symbol_name
1775 preserved_copy_of_name
=
1776 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1779 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1781 S_SET_SEGMENT (symbolP
, segment
);
1782 S_SET_VALUE (symbolP
, valu
);
1783 symbol_clear_list_pointers (symbolP
);
1785 symbol_set_frag (symbolP
, frag
);
1787 /* Link to end of symbol chain. */
1789 extern int symbol_table_frozen
;
1791 if (symbol_table_frozen
)
1795 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1797 obj_symbol_new_hook (symbolP
);
1799 #ifdef tc_symbol_new_hook
1800 tc_symbol_new_hook (symbolP
);
1804 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1805 #endif /* DEBUG_SYMS */
1810 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1817 for (align
= 2; align
<= 4; align
++)
1819 int size
= 1 << align
;
1821 pool
= find_literal_pool (size
);
1822 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1825 /* Align pool as you have word accesses.
1826 Only make a frag if we have to. */
1828 frag_align (align
, 0, 0);
1830 mapping_state (MAP_DATA
);
1832 record_alignment (now_seg
, align
);
1834 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1836 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1837 (valueT
) frag_now_fix (), frag_now
);
1838 symbol_table_insert (pool
->symbol
);
1840 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1842 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1844 if (exp
->X_op
== O_big
)
1846 /* PR 16688: Restore the global bignum value. */
1847 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1848 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1849 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1852 /* First output the expression in the instruction to the pool. */
1853 emit_expr (exp
, size
); /* .word|.xword */
1855 if (exp
->X_op
== O_big
)
1857 free (pool
->literals
[entry
].bignum
);
1858 pool
->literals
[entry
].bignum
= NULL
;
1862 /* Mark the pool as empty. */
1863 pool
->next_free_entry
= 0;
1864 pool
->symbol
= NULL
;
1869 /* Forward declarations for functions below, in the MD interface
1871 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1872 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1874 /* Directives: Data. */
1875 /* N.B. the support for relocation suffix in this directive needs to be
1876 implemented properly. */
1879 s_aarch64_elf_cons (int nbytes
)
1883 #ifdef md_flush_pending_output
1884 md_flush_pending_output ();
1887 if (is_it_end_of_statement ())
1889 demand_empty_rest_of_line ();
1893 #ifdef md_cons_align
1894 md_cons_align (nbytes
);
1897 mapping_state (MAP_DATA
);
1900 struct reloc_table_entry
*reloc
;
1904 if (exp
.X_op
!= O_symbol
)
1905 emit_expr (&exp
, (unsigned int) nbytes
);
1908 skip_past_char (&input_line_pointer
, '#');
1909 if (skip_past_char (&input_line_pointer
, ':'))
1911 reloc
= find_reloc_table_entry (&input_line_pointer
);
1913 as_bad (_("unrecognized relocation suffix"));
1915 as_bad (_("unimplemented relocation suffix"));
1916 ignore_rest_of_line ();
1920 emit_expr (&exp
, (unsigned int) nbytes
);
1923 while (*input_line_pointer
++ == ',');
1925 /* Put terminator back into stream. */
1926 input_line_pointer
--;
1927 demand_empty_rest_of_line ();
1930 #endif /* OBJ_ELF */
1932 /* Output a 32-bit word, but mark as an instruction. */
1935 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1939 #ifdef md_flush_pending_output
1940 md_flush_pending_output ();
1943 if (is_it_end_of_statement ())
1945 demand_empty_rest_of_line ();
1949 /* Sections are assumed to start aligned. In executable section, there is no
1950 MAP_DATA symbol pending. So we only align the address during
1951 MAP_DATA --> MAP_INSN transition.
1952 For other sections, this is not guaranteed. */
1953 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1954 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1955 frag_align_code (2, 0);
1958 mapping_state (MAP_INSN
);
1964 if (exp
.X_op
!= O_constant
)
1966 as_bad (_("constant expression required"));
1967 ignore_rest_of_line ();
1971 if (target_big_endian
)
1973 unsigned int val
= exp
.X_add_number
;
1974 exp
.X_add_number
= SWAP_32 (val
);
1976 emit_expr (&exp
, 4);
1978 while (*input_line_pointer
++ == ',');
1980 /* Put terminator back into stream. */
1981 input_line_pointer
--;
1982 demand_empty_rest_of_line ();
1986 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1989 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1995 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1996 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1998 demand_empty_rest_of_line ();
2001 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2004 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2008 /* Since we're just labelling the code, there's no need to define a
2011 /* Make sure there is enough room in this frag for the following
2012 blr. This trick only works if the blr follows immediately after
2013 the .tlsdesc directive. */
2015 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2016 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2018 demand_empty_rest_of_line ();
2021 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2024 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2030 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2031 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2033 demand_empty_rest_of_line ();
2035 #endif /* OBJ_ELF */
2037 static void s_aarch64_arch (int);
2038 static void s_aarch64_cpu (int);
2039 static void s_aarch64_arch_extension (int);
2041 /* This table describes all the machine specific pseudo-ops the assembler
2042 has to support. The fields are:
2043 pseudo-op name without dot
2044 function to call to execute this pseudo-op
2045 Integer arg to pass to the function. */
2047 const pseudo_typeS md_pseudo_table
[] = {
2048 /* Never called because '.req' does not start a line. */
2050 {"unreq", s_unreq
, 0},
2052 {"even", s_even
, 0},
2053 {"ltorg", s_ltorg
, 0},
2054 {"pool", s_ltorg
, 0},
2055 {"cpu", s_aarch64_cpu
, 0},
2056 {"arch", s_aarch64_arch
, 0},
2057 {"arch_extension", s_aarch64_arch_extension
, 0},
2058 {"inst", s_aarch64_inst
, 0},
2060 {"tlsdescadd", s_tlsdescadd
, 0},
2061 {"tlsdesccall", s_tlsdesccall
, 0},
2062 {"tlsdescldr", s_tlsdescldr
, 0},
2063 {"word", s_aarch64_elf_cons
, 4},
2064 {"long", s_aarch64_elf_cons
, 4},
2065 {"xword", s_aarch64_elf_cons
, 8},
2066 {"dword", s_aarch64_elf_cons
, 8},
2072 /* Check whether STR points to a register name followed by a comma or the
2073 end of line; REG_TYPE indicates which register types are checked
2074 against. Return TRUE if STR is such a register name; otherwise return
2075 FALSE. The function does not intend to produce any diagnostics, but since
2076 the register parser aarch64_reg_parse, which is called by this function,
2077 does produce diagnostics, we call clear_error to clear any diagnostics
2078 that may be generated by aarch64_reg_parse.
2079 Also, the function returns FALSE directly if there is any user error
2080 present at the function entry. This prevents the existing diagnostics
2081 state from being spoiled.
2082 The function currently serves parse_constant_immediate and
2083 parse_big_immediate only. */
2085 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2089 /* Prevent the diagnostics state from being spoiled. */
2093 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2095 /* Clear the parsing error that may be set by the reg parser. */
2098 if (reg
== PARSE_FAIL
)
2101 skip_whitespace (str
);
2102 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2108 /* Parser functions used exclusively in instruction operands. */
2110 /* Parse an immediate expression which may not be constant.
2112 To prevent the expression parser from pushing a register name
2113 into the symbol table as an undefined symbol, firstly a check is
2114 done to find out whether STR is a register of type REG_TYPE followed
2115 by a comma or the end of line. Return FALSE if STR is such a string. */
2118 parse_immediate_expression (char **str
, expressionS
*exp
,
2119 aarch64_reg_type reg_type
)
2121 if (reg_name_p (*str
, reg_type
))
2123 set_recoverable_error (_("immediate operand required"));
2127 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2129 if (exp
->X_op
== O_absent
)
2131 set_fatal_syntax_error (_("missing immediate expression"));
2138 /* Constant immediate-value read function for use in insn parsing.
2139 STR points to the beginning of the immediate (with the optional
2140 leading #); *VAL receives the value. REG_TYPE says which register
2141 names should be treated as registers rather than as symbolic immediates.
2143 Return TRUE on success; otherwise return FALSE. */
2146 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2150 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2153 if (exp
.X_op
!= O_constant
)
2155 set_syntax_error (_("constant expression required"));
2159 *val
= exp
.X_add_number
;
2164 encode_imm_float_bits (uint32_t imm
)
2166 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2167 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2170 /* Return TRUE if the single-precision floating-point value encoded in IMM
2171 can be expressed in the AArch64 8-bit signed floating-point format with
2172 3-bit exponent and normalized 4 bits of precision; in other words, the
2173 floating-point value must be expressable as
2174 (+/-) n / 16 * power (2, r)
2175 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2178 aarch64_imm_float_p (uint32_t imm
)
2180 /* If a single-precision floating-point value has the following bit
2181 pattern, it can be expressed in the AArch64 8-bit floating-point
2184 3 32222222 2221111111111
2185 1 09876543 21098765432109876543210
2186 n Eeeeeexx xxxx0000000000000000000
2188 where n, e and each x are either 0 or 1 independently, with
2193 /* Prepare the pattern for 'Eeeeee'. */
2194 if (((imm
>> 30) & 0x1) == 0)
2195 pattern
= 0x3e000000;
2197 pattern
= 0x40000000;
2199 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2200 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2203 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2204 as an IEEE float without any loss of precision. Store the value in
2208 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2210 /* If a double-precision floating-point value has the following bit
2211 pattern, it can be expressed in a float:
2213 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2214 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2215 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2217 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2218 if Eeee_eeee != 1111_1111
2220 where n, e, s and S are either 0 or 1 independently and where ~ is the
2224 uint32_t high32
= imm
>> 32;
2225 uint32_t low32
= imm
;
2227 /* Lower 29 bits need to be 0s. */
2228 if ((imm
& 0x1fffffff) != 0)
2231 /* Prepare the pattern for 'Eeeeeeeee'. */
2232 if (((high32
>> 30) & 0x1) == 0)
2233 pattern
= 0x38000000;
2235 pattern
= 0x40000000;
2238 if ((high32
& 0x78000000) != pattern
)
2241 /* Check Eeee_eeee != 1111_1111. */
2242 if ((high32
& 0x7ff00000) == 0x47f00000)
2245 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2246 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2247 | (low32
>> 29)); /* 3 S bits. */
2251 /* Return true if we should treat OPERAND as a double-precision
2252 floating-point operand rather than a single-precision one. */
2254 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2256 /* Check for unsuffixed SVE registers, which are allowed
2257 for LDR and STR but not in instructions that require an
2258 immediate. We get better error messages if we arbitrarily
2259 pick one size, parse the immediate normally, and then
2260 report the match failure in the normal way. */
2261 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2262 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2265 /* Parse a floating-point immediate. Return TRUE on success and return the
2266 value in *IMMED in the format of IEEE754 single-precision encoding.
2267 *CCP points to the start of the string; DP_P is TRUE when the immediate
2268 is expected to be in double-precision (N.B. this only matters when
2269 hexadecimal representation is involved). REG_TYPE says which register
2270 names should be treated as registers rather than as symbolic immediates.
2272 This routine accepts any IEEE float; it is up to the callers to reject
2276 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2277 aarch64_reg_type reg_type
)
2281 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2282 int found_fpchar
= 0;
2284 unsigned fpword
= 0;
2285 bfd_boolean hex_p
= FALSE
;
2287 skip_past_char (&str
, '#');
2290 skip_whitespace (fpnum
);
2292 if (strncmp (fpnum
, "0x", 2) == 0)
2294 /* Support the hexadecimal representation of the IEEE754 encoding.
2295 Double-precision is expected when DP_P is TRUE, otherwise the
2296 representation should be in single-precision. */
2297 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2302 if (!can_convert_double_to_float (val
, &fpword
))
2305 else if ((uint64_t) val
> 0xffffffff)
2314 if (reg_name_p (str
, reg_type
))
2316 set_recoverable_error (_("immediate operand required"));
2320 /* We must not accidentally parse an integer as a floating-point number.
2321 Make sure that the value we parse is not an integer by checking for
2322 special characters '.' or 'e'. */
2323 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2324 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2338 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2341 /* Our FP word must be 32 bits (single-precision FP). */
2342 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2344 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2354 set_fatal_syntax_error (_("invalid floating-point constant"));
2358 /* Less-generic immediate-value read function with the possibility of loading
2359 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2362 To prevent the expression parser from pushing a register name into the
2363 symbol table as an undefined symbol, a check is firstly done to find
2364 out whether STR is a register of type REG_TYPE followed by a comma or
2365 the end of line. Return FALSE if STR is such a register. */
2368 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2372 if (reg_name_p (ptr
, reg_type
))
2374 set_syntax_error (_("immediate operand required"));
2378 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2380 if (inst
.reloc
.exp
.X_op
== O_constant
)
2381 *imm
= inst
.reloc
.exp
.X_add_number
;
2388 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2389 if NEED_LIBOPCODES is non-zero, the fixup will need
2390 assistance from the libopcodes. */
2393 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2394 const aarch64_opnd_info
*operand
,
2395 int need_libopcodes_p
)
2397 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2398 reloc
->opnd
= operand
->type
;
2399 if (need_libopcodes_p
)
2400 reloc
->need_libopcodes_p
= 1;
2403 /* Return TRUE if the instruction needs to be fixed up later internally by
2404 the GAS; otherwise return FALSE. */
2406 static inline bfd_boolean
2407 aarch64_gas_internal_fixup_p (void)
2409 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2412 /* Assign the immediate value to the relevant field in *OPERAND if
2413 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2414 needs an internal fixup in a later stage.
2415 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2416 IMM.VALUE that may get assigned with the constant. */
2418 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2419 aarch64_opnd_info
*operand
,
2421 int need_libopcodes_p
,
2424 if (reloc
->exp
.X_op
== O_constant
)
2427 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2429 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2430 reloc
->type
= BFD_RELOC_UNUSED
;
2434 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2435 /* Tell libopcodes to ignore this operand or not. This is helpful
2436 when one of the operands needs to be fixed up later but we need
2437 libopcodes to check the other operands. */
2438 operand
->skip
= skip_p
;
2442 /* Relocation modifiers. Each entry in the table contains the textual
2443 name for the relocation which may be placed before a symbol used as
2444 a load/store offset, or add immediate. It must be surrounded by a
2445 leading and trailing colon, for example:
2447 ldr x0, [x1, #:rello:varsym]
2448 add x0, x1, #:rello:varsym */
2450 struct reloc_table_entry
2454 bfd_reloc_code_real_type adr_type
;
2455 bfd_reloc_code_real_type adrp_type
;
2456 bfd_reloc_code_real_type movw_type
;
2457 bfd_reloc_code_real_type add_type
;
2458 bfd_reloc_code_real_type ldst_type
;
2459 bfd_reloc_code_real_type ld_literal_type
;
2462 static struct reloc_table_entry reloc_table
[] = {
2463 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2468 BFD_RELOC_AARCH64_ADD_LO12
,
2469 BFD_RELOC_AARCH64_LDST_LO12
,
2472 /* Higher 21 bits of pc-relative page offset: ADRP */
2475 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2481 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2484 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2490 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2494 BFD_RELOC_AARCH64_MOVW_G0
,
2499 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2503 BFD_RELOC_AARCH64_MOVW_G0_S
,
2508 /* Less significant bits 0-15 of address/value: MOVK, no check */
2512 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2517 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2521 BFD_RELOC_AARCH64_MOVW_G1
,
2526 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2530 BFD_RELOC_AARCH64_MOVW_G1_S
,
2535 /* Less significant bits 16-31 of address/value: MOVK, no check */
2539 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2544 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2548 BFD_RELOC_AARCH64_MOVW_G2
,
2553 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2557 BFD_RELOC_AARCH64_MOVW_G2_S
,
2562 /* Less significant bits 32-47 of address/value: MOVK, no check */
2566 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2571 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2575 BFD_RELOC_AARCH64_MOVW_G3
,
2580 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2584 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2589 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2593 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2598 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2602 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2607 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2611 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2616 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2620 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2625 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2629 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2634 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2638 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2643 /* Get to the page containing GOT entry for a symbol. */
2646 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2650 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2652 /* 12 bit offset into the page containing GOT entry for that symbol. */
2658 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2661 /* 0-15 bits of address/value: MOVk, no check. */
2665 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2670 /* Most significant bits 16-31 of address/value: MOVZ. */
2674 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2679 /* 15 bit offset into the page containing GOT entry for that symbol. */
2685 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2688 /* Get to the page containing GOT TLS entry for a symbol */
2689 {"gottprel_g0_nc", 0,
2692 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2697 /* Get to the page containing GOT TLS entry for a symbol */
2701 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2706 /* Get to the page containing GOT TLS entry for a symbol */
2708 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2709 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2715 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2720 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2724 /* Lower 16 bits address/value: MOVk. */
2728 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2733 /* Most significant bits 16-31 of address/value: MOVZ. */
2737 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2742 /* Get to the page containing GOT TLS entry for a symbol */
2744 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2745 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2749 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2751 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2756 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2757 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2760 /* Get to the page containing GOT TLS entry for a symbol.
2761 The same as GD, we allocate two consecutive GOT slots
2762 for module index and module offset, the only difference
2763 with GD is the module offset should be initialized to
2764 zero without any outstanding runtime relocation. */
2766 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2767 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2773 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2774 {"tlsldm_lo12_nc", 0,
2778 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2782 /* 12 bit offset into the module TLS base address. */
2787 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2788 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2791 /* Same as dtprel_lo12, no overflow check. */
2792 {"dtprel_lo12_nc", 0,
2796 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2797 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2800 /* bits[23:12] of offset to the module TLS base address. */
2805 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2809 /* bits[15:0] of offset to the module TLS base address. */
2813 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2818 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2822 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2827 /* bits[31:16] of offset to the module TLS base address. */
2831 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2836 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2840 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2845 /* bits[47:32] of offset to the module TLS base address. */
2849 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2854 /* Lower 16 bit offset into GOT entry for a symbol */
2855 {"tlsdesc_off_g0_nc", 0,
2858 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2863 /* Higher 16 bit offset into GOT entry for a symbol */
2864 {"tlsdesc_off_g1", 0,
2867 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2872 /* Get to the page containing GOT TLS entry for a symbol */
2875 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2879 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2881 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2882 {"gottprel_lo12", 0,
2887 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2890 /* Get tp offset for a symbol. */
2895 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2899 /* Get tp offset for a symbol. */
2904 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2908 /* Get tp offset for a symbol. */
2913 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2917 /* Get tp offset for a symbol. */
2918 {"tprel_lo12_nc", 0,
2922 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2926 /* Most significant bits 32-47 of address/value: MOVZ. */
2930 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2935 /* Most significant bits 16-31 of address/value: MOVZ. */
2939 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2944 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2948 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2953 /* Most significant bits 0-15 of address/value: MOVZ. */
2957 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2962 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2966 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2971 /* 15bit offset from got entry to base address of GOT table. */
2977 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2980 /* 14bit offset from got entry to base address of GOT table. */
2986 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2990 /* Given the address of a pointer pointing to the textual name of a
2991 relocation as may appear in assembler source, attempt to find its
2992 details in reloc_table. The pointer will be updated to the character
2993 after the trailing colon. On failure, NULL will be returned;
2994 otherwise return the reloc_table_entry. */
2996 static struct reloc_table_entry
*
2997 find_reloc_table_entry (char **str
)
3000 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3002 int length
= strlen (reloc_table
[i
].name
);
3004 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3005 && (*str
)[length
] == ':')
3007 *str
+= (length
+ 1);
3008 return &reloc_table
[i
];
3015 /* Mode argument to parse_shift and parser_shifter_operand. */
3016 enum parse_shift_mode
3018 SHIFTED_NONE
, /* no shifter allowed */
3019 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3021 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3023 SHIFTED_LSL
, /* bare "lsl #n" */
3024 SHIFTED_MUL
, /* bare "mul #n" */
3025 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3026 SHIFTED_MUL_VL
, /* "mul vl" */
3027 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3030 /* Parse a <shift> operator on an AArch64 data processing instruction.
3031 Return TRUE on success; otherwise return FALSE. */
3033 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3035 const struct aarch64_name_value_pair
*shift_op
;
3036 enum aarch64_modifier_kind kind
;
3042 for (p
= *str
; ISALPHA (*p
); p
++)
3047 set_syntax_error (_("shift expression expected"));
3051 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3053 if (shift_op
== NULL
)
3055 set_syntax_error (_("shift operator expected"));
3059 kind
= aarch64_get_operand_modifier (shift_op
);
3061 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3063 set_syntax_error (_("invalid use of 'MSL'"));
3067 if (kind
== AARCH64_MOD_MUL
3068 && mode
!= SHIFTED_MUL
3069 && mode
!= SHIFTED_MUL_VL
)
3071 set_syntax_error (_("invalid use of 'MUL'"));
3077 case SHIFTED_LOGIC_IMM
:
3078 if (aarch64_extend_operator_p (kind
))
3080 set_syntax_error (_("extending shift is not permitted"));
3085 case SHIFTED_ARITH_IMM
:
3086 if (kind
== AARCH64_MOD_ROR
)
3088 set_syntax_error (_("'ROR' shift is not permitted"));
3094 if (kind
!= AARCH64_MOD_LSL
)
3096 set_syntax_error (_("only 'LSL' shift is permitted"));
3102 if (kind
!= AARCH64_MOD_MUL
)
3104 set_syntax_error (_("only 'MUL' is permitted"));
3109 case SHIFTED_MUL_VL
:
3110 /* "MUL VL" consists of two separate tokens. Require the first
3111 token to be "MUL" and look for a following "VL". */
3112 if (kind
== AARCH64_MOD_MUL
)
3114 skip_whitespace (p
);
3115 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3118 kind
= AARCH64_MOD_MUL_VL
;
3122 set_syntax_error (_("only 'MUL VL' is permitted"));
3125 case SHIFTED_REG_OFFSET
:
3126 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3127 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3129 set_fatal_syntax_error
3130 (_("invalid shift for the register offset addressing mode"));
3135 case SHIFTED_LSL_MSL
:
3136 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3138 set_syntax_error (_("invalid shift operator"));
3147 /* Whitespace can appear here if the next thing is a bare digit. */
3148 skip_whitespace (p
);
3150 /* Parse shift amount. */
3152 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3153 exp
.X_op
= O_absent
;
3156 if (is_immediate_prefix (*p
))
3161 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3163 if (kind
== AARCH64_MOD_MUL_VL
)
3164 /* For consistency, give MUL VL the same shift amount as an implicit
3166 operand
->shifter
.amount
= 1;
3167 else if (exp
.X_op
== O_absent
)
3169 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3171 set_syntax_error (_("missing shift amount"));
3174 operand
->shifter
.amount
= 0;
3176 else if (exp
.X_op
!= O_constant
)
3178 set_syntax_error (_("constant shift amount required"));
3181 /* For parsing purposes, MUL #n has no inherent range. The range
3182 depends on the operand and will be checked by operand-specific
3184 else if (kind
!= AARCH64_MOD_MUL
3185 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3187 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3192 operand
->shifter
.amount
= exp
.X_add_number
;
3193 operand
->shifter
.amount_present
= 1;
3196 operand
->shifter
.operator_present
= 1;
3197 operand
->shifter
.kind
= kind
;
3203 /* Parse a <shifter_operand> for a data processing instruction:
3206 #<immediate>, LSL #imm
3208 Validation of immediate operands is deferred to md_apply_fix.
3210 Return TRUE on success; otherwise return FALSE. */
3213 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3214 enum parse_shift_mode mode
)
3218 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3223 /* Accept an immediate expression. */
3224 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3227 /* Accept optional LSL for arithmetic immediate values. */
3228 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3229 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3232 /* Not accept any shifter for logical immediate values. */
3233 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3234 && parse_shift (&p
, operand
, mode
))
3236 set_syntax_error (_("unexpected shift operator"));
3244 /* Parse a <shifter_operand> for a data processing instruction:
3249 #<immediate>, LSL #imm
3251 where <shift> is handled by parse_shift above, and the last two
3252 cases are handled by the function above.
3254 Validation of immediate operands is deferred to md_apply_fix.
3256 Return TRUE on success; otherwise return FALSE. */
3259 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3260 enum parse_shift_mode mode
)
3262 const reg_entry
*reg
;
3263 aarch64_opnd_qualifier_t qualifier
;
3264 enum aarch64_operand_class opd_class
3265 = aarch64_get_operand_class (operand
->type
);
3267 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3270 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3272 set_syntax_error (_("unexpected register in the immediate operand"));
3276 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3278 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3282 operand
->reg
.regno
= reg
->number
;
3283 operand
->qualifier
= qualifier
;
3285 /* Accept optional shift operation on register. */
3286 if (! skip_past_comma (str
))
3289 if (! parse_shift (str
, operand
, mode
))
3294 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3297 (_("integer register expected in the extended/shifted operand "
3302 /* We have a shifted immediate variable. */
3303 return parse_shifter_operand_imm (str
, operand
, mode
);
3306 /* Return TRUE on success; return FALSE otherwise. */
3309 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3310 enum parse_shift_mode mode
)
3314 /* Determine if we have the sequence of characters #: or just :
3315 coming next. If we do, then we check for a :rello: relocation
3316 modifier. If we don't, punt the whole lot to
3317 parse_shifter_operand. */
3319 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3321 struct reloc_table_entry
*entry
;
3329 /* Try to parse a relocation. Anything else is an error. */
3330 if (!(entry
= find_reloc_table_entry (str
)))
3332 set_syntax_error (_("unknown relocation modifier"));
3336 if (entry
->add_type
== 0)
3339 (_("this relocation modifier is not allowed on this instruction"));
3343 /* Save str before we decompose it. */
3346 /* Next, we parse the expression. */
3347 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3350 /* Record the relocation type (use the ADD variant here). */
3351 inst
.reloc
.type
= entry
->add_type
;
3352 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3354 /* If str is empty, we've reached the end, stop here. */
3358 /* Otherwise, we have a shifted reloc modifier, so rewind to
3359 recover the variable name and continue parsing for the shifter. */
3361 return parse_shifter_operand_imm (str
, operand
, mode
);
3364 return parse_shifter_operand (str
, operand
, mode
);
3367 /* Parse all forms of an address expression. Information is written
3368 to *OPERAND and/or inst.reloc.
3370 The A64 instruction set has the following addressing modes:
3373 [base] // in SIMD ld/st structure
3374 [base{,#0}] // in ld/st exclusive
3376 [base,Xm{,LSL #imm}]
3377 [base,Xm,SXTX {#imm}]
3378 [base,Wm,(S|U)XTW {#imm}]
3383 [base],Xm // in SIMD ld/st structure
3384 PC-relative (literal)
3388 [base,Zm.D{,LSL #imm}]
3389 [base,Zm.S,(S|U)XTW {#imm}]
3390 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3393 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3394 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3395 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3397 (As a convenience, the notation "=immediate" is permitted in conjunction
3398 with the pc-relative literal load instructions to automatically place an
3399 immediate value or symbolic address in a nearby literal pool and generate
3400 a hidden label which references it.)
3402 Upon a successful parsing, the address structure in *OPERAND will be
3403 filled in the following way:
3405 .base_regno = <base>
3406 .offset.is_reg // 1 if the offset is a register
3408 .offset.regno = <Rm>
3410 For different addressing modes defined in the A64 ISA:
3413 .pcrel=0; .preind=1; .postind=0; .writeback=0
3415 .pcrel=0; .preind=1; .postind=0; .writeback=1
3417 .pcrel=0; .preind=0; .postind=1; .writeback=1
3418 PC-relative (literal)
3419 .pcrel=1; .preind=1; .postind=0; .writeback=0
3421 The shift/extension information, if any, will be stored in .shifter.
3422 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3423 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3424 corresponding register.
3426 BASE_TYPE says which types of base register should be accepted and
3427 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3428 is the type of shifter that is allowed for immediate offsets,
3429 or SHIFTED_NONE if none.
3431 In all other respects, it is the caller's responsibility to check
3432 for addressing modes not supported by the instruction, and to set
3436 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3437 aarch64_opnd_qualifier_t
*base_qualifier
,
3438 aarch64_opnd_qualifier_t
*offset_qualifier
,
3439 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3440 enum parse_shift_mode imm_shift_mode
)
3443 const reg_entry
*reg
;
3444 expressionS
*exp
= &inst
.reloc
.exp
;
3446 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3447 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3448 if (! skip_past_char (&p
, '['))
3450 /* =immediate or label. */
3451 operand
->addr
.pcrel
= 1;
3452 operand
->addr
.preind
= 1;
3454 /* #:<reloc_op>:<symbol> */
3455 skip_past_char (&p
, '#');
3456 if (skip_past_char (&p
, ':'))
3458 bfd_reloc_code_real_type ty
;
3459 struct reloc_table_entry
*entry
;
3461 /* Try to parse a relocation modifier. Anything else is
3463 entry
= find_reloc_table_entry (&p
);
3466 set_syntax_error (_("unknown relocation modifier"));
3470 switch (operand
->type
)
3472 case AARCH64_OPND_ADDR_PCREL21
:
3474 ty
= entry
->adr_type
;
3478 ty
= entry
->ld_literal_type
;
3485 (_("this relocation modifier is not allowed on this "
3491 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3493 set_syntax_error (_("invalid relocation expression"));
3497 /* #:<reloc_op>:<expr> */
3498 /* Record the relocation type. */
3499 inst
.reloc
.type
= ty
;
3500 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3505 if (skip_past_char (&p
, '='))
3506 /* =immediate; need to generate the literal in the literal pool. */
3507 inst
.gen_lit_pool
= 1;
3509 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3511 set_syntax_error (_("invalid address"));
3522 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3523 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3525 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3528 operand
->addr
.base_regno
= reg
->number
;
3531 if (skip_past_comma (&p
))
3534 operand
->addr
.preind
= 1;
3536 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3539 if (!aarch64_check_reg_type (reg
, offset_type
))
3541 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3546 operand
->addr
.offset
.regno
= reg
->number
;
3547 operand
->addr
.offset
.is_reg
= 1;
3548 /* Shifted index. */
3549 if (skip_past_comma (&p
))
3552 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3553 /* Use the diagnostics set in parse_shift, so not set new
3554 error message here. */
3558 [base,Xm{,LSL #imm}]
3559 [base,Xm,SXTX {#imm}]
3560 [base,Wm,(S|U)XTW {#imm}] */
3561 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3562 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3563 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3565 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3567 set_syntax_error (_("invalid use of 32-bit register offset"));
3570 if (aarch64_get_qualifier_esize (*base_qualifier
)
3571 != aarch64_get_qualifier_esize (*offset_qualifier
))
3573 set_syntax_error (_("offset has different size from base"));
3577 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3579 set_syntax_error (_("invalid use of 64-bit register offset"));
3585 /* [Xn,#:<reloc_op>:<symbol> */
3586 skip_past_char (&p
, '#');
3587 if (skip_past_char (&p
, ':'))
3589 struct reloc_table_entry
*entry
;
3591 /* Try to parse a relocation modifier. Anything else is
3593 if (!(entry
= find_reloc_table_entry (&p
)))
3595 set_syntax_error (_("unknown relocation modifier"));
3599 if (entry
->ldst_type
== 0)
3602 (_("this relocation modifier is not allowed on this "
3607 /* [Xn,#:<reloc_op>: */
3608 /* We now have the group relocation table entry corresponding to
3609 the name in the assembler source. Next, we parse the
3611 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3613 set_syntax_error (_("invalid relocation expression"));
3617 /* [Xn,#:<reloc_op>:<expr> */
3618 /* Record the load/store relocation type. */
3619 inst
.reloc
.type
= entry
->ldst_type
;
3620 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3624 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3626 set_syntax_error (_("invalid expression in the address"));
3630 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3631 /* [Xn,<expr>,<shifter> */
3632 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3638 if (! skip_past_char (&p
, ']'))
3640 set_syntax_error (_("']' expected"));
3644 if (skip_past_char (&p
, '!'))
3646 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3648 set_syntax_error (_("register offset not allowed in pre-indexed "
3649 "addressing mode"));
3653 operand
->addr
.writeback
= 1;
3655 else if (skip_past_comma (&p
))
3658 operand
->addr
.postind
= 1;
3659 operand
->addr
.writeback
= 1;
3661 if (operand
->addr
.preind
)
3663 set_syntax_error (_("cannot combine pre- and post-indexing"));
3667 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3671 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3673 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3677 operand
->addr
.offset
.regno
= reg
->number
;
3678 operand
->addr
.offset
.is_reg
= 1;
3680 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3683 set_syntax_error (_("invalid expression in the address"));
3688 /* If at this point neither .preind nor .postind is set, we have a
3689 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3690 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3692 if (operand
->addr
.writeback
)
3695 set_syntax_error (_("missing offset in the pre-indexed address"));
3699 operand
->addr
.preind
= 1;
3700 inst
.reloc
.exp
.X_op
= O_constant
;
3701 inst
.reloc
.exp
.X_add_number
= 0;
3708 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3711 parse_address (char **str
, aarch64_opnd_info
*operand
)
3713 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3714 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3715 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3718 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3719 The arguments have the same meaning as for parse_address_main.
3720 Return TRUE on success. */
3722 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3723 aarch64_opnd_qualifier_t
*base_qualifier
,
3724 aarch64_opnd_qualifier_t
*offset_qualifier
)
3726 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3727 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3731 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3732 Return TRUE on success; otherwise return FALSE. */
3734 parse_half (char **str
, int *internal_fixup_p
)
3738 skip_past_char (&p
, '#');
3740 gas_assert (internal_fixup_p
);
3741 *internal_fixup_p
= 0;
3745 struct reloc_table_entry
*entry
;
3747 /* Try to parse a relocation. Anything else is an error. */
3749 if (!(entry
= find_reloc_table_entry (&p
)))
3751 set_syntax_error (_("unknown relocation modifier"));
3755 if (entry
->movw_type
== 0)
3758 (_("this relocation modifier is not allowed on this instruction"));
3762 inst
.reloc
.type
= entry
->movw_type
;
3765 *internal_fixup_p
= 1;
3767 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3774 /* Parse an operand for an ADRP instruction:
3776 Return TRUE on success; otherwise return FALSE. */
3779 parse_adrp (char **str
)
3786 struct reloc_table_entry
*entry
;
3788 /* Try to parse a relocation. Anything else is an error. */
3790 if (!(entry
= find_reloc_table_entry (&p
)))
3792 set_syntax_error (_("unknown relocation modifier"));
3796 if (entry
->adrp_type
== 0)
3799 (_("this relocation modifier is not allowed on this instruction"));
3803 inst
.reloc
.type
= entry
->adrp_type
;
3806 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3808 inst
.reloc
.pc_rel
= 1;
3810 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3817 /* Miscellaneous. */
3819 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3820 of SIZE tokens in which index I gives the token for field value I,
3821 or is null if field value I is invalid. REG_TYPE says which register
3822 names should be treated as registers rather than as symbolic immediates.
3824 Return true on success, moving *STR past the operand and storing the
3825 field value in *VAL. */
3828 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3829 size_t size
, aarch64_reg_type reg_type
)
3835 /* Match C-like tokens. */
3837 while (ISALNUM (*q
))
3840 for (i
= 0; i
< size
; ++i
)
3842 && strncasecmp (array
[i
], p
, q
- p
) == 0
3843 && array
[i
][q
- p
] == 0)
3850 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3853 if (exp
.X_op
== O_constant
3854 && (uint64_t) exp
.X_add_number
< size
)
3856 *val
= exp
.X_add_number
;
3861 /* Use the default error for this operand. */
3865 /* Parse an option for a preload instruction. Returns the encoding for the
3866 option, or PARSE_FAIL. */
3869 parse_pldop (char **str
)
3872 const struct aarch64_name_value_pair
*o
;
3875 while (ISALNUM (*q
))
3878 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3886 /* Parse an option for a barrier instruction. Returns the encoding for the
3887 option, or PARSE_FAIL. */
3890 parse_barrier (char **str
)
3893 const asm_barrier_opt
*o
;
3896 while (ISALPHA (*q
))
3899 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3907 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3908 return 0 if successful. Otherwise return PARSE_FAIL. */
3911 parse_barrier_psb (char **str
,
3912 const struct aarch64_name_value_pair
** hint_opt
)
3915 const struct aarch64_name_value_pair
*o
;
3918 while (ISALPHA (*q
))
3921 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3924 set_fatal_syntax_error
3925 ( _("unknown or missing option to PSB"));
3929 if (o
->value
!= 0x11)
3931 /* PSB only accepts option name 'CSYNC'. */
3933 (_("the specified option is not accepted for PSB"));
3942 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3943 Returns the encoding for the option, or PARSE_FAIL.
3945 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3946 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3948 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3949 field, otherwise as a system register.
3953 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3954 int imple_defined_p
, int pstatefield_p
)
3958 const aarch64_sys_reg
*o
;
3962 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3964 *p
++ = TOLOWER (*q
);
3966 /* Assert that BUF be large enough. */
3967 gas_assert (p
- buf
== q
- *str
);
3969 o
= hash_find (sys_regs
, buf
);
3972 if (!imple_defined_p
)
3976 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3977 unsigned int op0
, op1
, cn
, cm
, op2
;
3979 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3982 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3984 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3989 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3990 as_bad (_("selected processor does not support PSTATE field "
3992 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3993 as_bad (_("selected processor does not support system register "
3995 if (aarch64_sys_reg_deprecated_p (o
))
3996 as_warn (_("system register name '%s' is deprecated and may be "
3997 "removed in a future release"), buf
);
4005 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4006 for the option, or NULL. */
4008 static const aarch64_sys_ins_reg
*
4009 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4013 const aarch64_sys_ins_reg
*o
;
4016 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4018 *p
++ = TOLOWER (*q
);
4021 o
= hash_find (sys_ins_regs
, buf
);
4025 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4026 as_bad (_("selected processor does not support system register "
4033 #define po_char_or_fail(chr) do { \
4034 if (! skip_past_char (&str, chr)) \
4038 #define po_reg_or_fail(regtype) do { \
4039 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4040 if (val == PARSE_FAIL) \
4042 set_default_error (); \
4047 #define po_int_reg_or_fail(reg_type) do { \
4048 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4049 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4051 set_default_error (); \
4054 info->reg.regno = reg->number; \
4055 info->qualifier = qualifier; \
4058 #define po_imm_nc_or_fail() do { \
4059 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4063 #define po_imm_or_fail(min, max) do { \
4064 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4066 if (val < min || val > max) \
4068 set_fatal_syntax_error (_("immediate value out of range "\
4069 #min " to "#max)); \
4074 #define po_enum_or_fail(array) do { \
4075 if (!parse_enum_string (&str, &val, array, \
4076 ARRAY_SIZE (array), imm_reg_type)) \
4080 #define po_misc_or_fail(expr) do { \
4085 /* encode the 12-bit imm field of Add/sub immediate */
4086 static inline uint32_t
4087 encode_addsub_imm (uint32_t imm
)
4092 /* encode the shift amount field of Add/sub immediate */
4093 static inline uint32_t
4094 encode_addsub_imm_shift_amount (uint32_t cnt
)
4100 /* encode the imm field of Adr instruction */
4101 static inline uint32_t
4102 encode_adr_imm (uint32_t imm
)
4104 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4105 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4108 /* encode the immediate field of Move wide immediate */
4109 static inline uint32_t
4110 encode_movw_imm (uint32_t imm
)
4115 /* encode the 26-bit offset of unconditional branch */
4116 static inline uint32_t
4117 encode_branch_ofs_26 (uint32_t ofs
)
4119 return ofs
& ((1 << 26) - 1);
4122 /* encode the 19-bit offset of conditional branch and compare & branch */
4123 static inline uint32_t
4124 encode_cond_branch_ofs_19 (uint32_t ofs
)
4126 return (ofs
& ((1 << 19) - 1)) << 5;
4129 /* encode the 19-bit offset of ld literal */
4130 static inline uint32_t
4131 encode_ld_lit_ofs_19 (uint32_t ofs
)
4133 return (ofs
& ((1 << 19) - 1)) << 5;
4136 /* Encode the 14-bit offset of test & branch. */
4137 static inline uint32_t
4138 encode_tst_branch_ofs_14 (uint32_t ofs
)
4140 return (ofs
& ((1 << 14) - 1)) << 5;
4143 /* Encode the 16-bit imm field of svc/hvc/smc. */
4144 static inline uint32_t
4145 encode_svc_imm (uint32_t imm
)
4150 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4151 static inline uint32_t
4152 reencode_addsub_switch_add_sub (uint32_t opcode
)
4154 return opcode
^ (1 << 30);
4157 static inline uint32_t
4158 reencode_movzn_to_movz (uint32_t opcode
)
4160 return opcode
| (1 << 30);
4163 static inline uint32_t
4164 reencode_movzn_to_movn (uint32_t opcode
)
4166 return opcode
& ~(1 << 30);
4169 /* Overall per-instruction processing. */
4171 /* We need to be able to fix up arbitrary expressions in some statements.
4172 This is so that we can handle symbols that are an arbitrary distance from
4173 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4174 which returns part of an address in a form which will be valid for
4175 a data instruction. We do this by pushing the expression into a symbol
4176 in the expr_section, and creating a fix for that. */
4179 fix_new_aarch64 (fragS
* frag
,
4181 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4191 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4195 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4202 /* Diagnostics on operands errors. */
4204 /* By default, output verbose error message.
4205 Disable the verbose error message by -mno-verbose-error. */
4206 static int verbose_error_p
= 1;
4208 #ifdef DEBUG_AARCH64
4209 /* N.B. this is only for the purpose of debugging. */
4210 const char* operand_mismatch_kind_names
[] =
4213 "AARCH64_OPDE_RECOVERABLE",
4214 "AARCH64_OPDE_SYNTAX_ERROR",
4215 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4216 "AARCH64_OPDE_INVALID_VARIANT",
4217 "AARCH64_OPDE_OUT_OF_RANGE",
4218 "AARCH64_OPDE_UNALIGNED",
4219 "AARCH64_OPDE_REG_LIST",
4220 "AARCH64_OPDE_OTHER_ERROR",
4222 #endif /* DEBUG_AARCH64 */
4224 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4226 When multiple errors of different kinds are found in the same assembly
4227 line, only the error of the highest severity will be picked up for
4228 issuing the diagnostics. */
4230 static inline bfd_boolean
4231 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4232 enum aarch64_operand_error_kind rhs
)
4234 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4235 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4236 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4237 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4238 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4239 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4240 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4241 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4245 /* Helper routine to get the mnemonic name from the assembly instruction
4246 line; should only be called for the diagnosis purpose, as there is
4247 string copy operation involved, which may affect the runtime
4248 performance if used in elsewhere. */
4251 get_mnemonic_name (const char *str
)
4253 static char mnemonic
[32];
4256 /* Get the first 15 bytes and assume that the full name is included. */
4257 strncpy (mnemonic
, str
, 31);
4258 mnemonic
[31] = '\0';
4260 /* Scan up to the end of the mnemonic, which must end in white space,
4261 '.', or end of string. */
4262 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4267 /* Append '...' to the truncated long name. */
4268 if (ptr
- mnemonic
== 31)
4269 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4275 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4277 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4278 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4281 /* Data structures storing one user error in the assembly code related to
4284 struct operand_error_record
4286 const aarch64_opcode
*opcode
;
4287 aarch64_operand_error detail
;
4288 struct operand_error_record
*next
;
4291 typedef struct operand_error_record operand_error_record
;
4293 struct operand_errors
4295 operand_error_record
*head
;
4296 operand_error_record
*tail
;
4299 typedef struct operand_errors operand_errors
;
4301 /* Top-level data structure reporting user errors for the current line of
4303 The way md_assemble works is that all opcodes sharing the same mnemonic
4304 name are iterated to find a match to the assembly line. In this data
4305 structure, each of the such opcodes will have one operand_error_record
4306 allocated and inserted. In other words, excessive errors related with
4307 a single opcode are disregarded. */
4308 operand_errors operand_error_report
;
4310 /* Free record nodes. */
4311 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4313 /* Initialize the data structure that stores the operand mismatch
4314 information on assembling one line of the assembly code. */
4316 init_operand_error_report (void)
4318 if (operand_error_report
.head
!= NULL
)
4320 gas_assert (operand_error_report
.tail
!= NULL
);
4321 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4322 free_opnd_error_record_nodes
= operand_error_report
.head
;
4323 operand_error_report
.head
= NULL
;
4324 operand_error_report
.tail
= NULL
;
4327 gas_assert (operand_error_report
.tail
== NULL
);
4330 /* Return TRUE if some operand error has been recorded during the
4331 parsing of the current assembly line using the opcode *OPCODE;
4332 otherwise return FALSE. */
4333 static inline bfd_boolean
4334 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4336 operand_error_record
*record
= operand_error_report
.head
;
4337 return record
&& record
->opcode
== opcode
;
4340 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4341 OPCODE field is initialized with OPCODE.
4342 N.B. only one record for each opcode, i.e. the maximum of one error is
4343 recorded for each instruction template. */
4346 add_operand_error_record (const operand_error_record
* new_record
)
4348 const aarch64_opcode
*opcode
= new_record
->opcode
;
4349 operand_error_record
* record
= operand_error_report
.head
;
4351 /* The record may have been created for this opcode. If not, we need
4353 if (! opcode_has_operand_error_p (opcode
))
4355 /* Get one empty record. */
4356 if (free_opnd_error_record_nodes
== NULL
)
4358 record
= XNEW (operand_error_record
);
4362 record
= free_opnd_error_record_nodes
;
4363 free_opnd_error_record_nodes
= record
->next
;
4365 record
->opcode
= opcode
;
4366 /* Insert at the head. */
4367 record
->next
= operand_error_report
.head
;
4368 operand_error_report
.head
= record
;
4369 if (operand_error_report
.tail
== NULL
)
4370 operand_error_report
.tail
= record
;
4372 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4373 && record
->detail
.index
<= new_record
->detail
.index
4374 && operand_error_higher_severity_p (record
->detail
.kind
,
4375 new_record
->detail
.kind
))
4377 /* In the case of multiple errors found on operands related with a
4378 single opcode, only record the error of the leftmost operand and
4379 only if the error is of higher severity. */
4380 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4381 " the existing error %s on operand %d",
4382 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4383 new_record
->detail
.index
,
4384 operand_mismatch_kind_names
[record
->detail
.kind
],
4385 record
->detail
.index
);
4389 record
->detail
= new_record
->detail
;
4393 record_operand_error_info (const aarch64_opcode
*opcode
,
4394 aarch64_operand_error
*error_info
)
4396 operand_error_record record
;
4397 record
.opcode
= opcode
;
4398 record
.detail
= *error_info
;
4399 add_operand_error_record (&record
);
4402 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4403 error message *ERROR, for operand IDX (count from 0). */
4406 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4407 enum aarch64_operand_error_kind kind
,
4410 aarch64_operand_error info
;
4411 memset(&info
, 0, sizeof (info
));
4415 record_operand_error_info (opcode
, &info
);
4419 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4420 enum aarch64_operand_error_kind kind
,
4421 const char* error
, const int *extra_data
)
4423 aarch64_operand_error info
;
4427 info
.data
[0] = extra_data
[0];
4428 info
.data
[1] = extra_data
[1];
4429 info
.data
[2] = extra_data
[2];
4430 record_operand_error_info (opcode
, &info
);
4434 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4435 const char* error
, int lower_bound
,
4438 int data
[3] = {lower_bound
, upper_bound
, 0};
4439 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4443 /* Remove the operand error record for *OPCODE. */
4444 static void ATTRIBUTE_UNUSED
4445 remove_operand_error_record (const aarch64_opcode
*opcode
)
4447 if (opcode_has_operand_error_p (opcode
))
4449 operand_error_record
* record
= operand_error_report
.head
;
4450 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4451 operand_error_report
.head
= record
->next
;
4452 record
->next
= free_opnd_error_record_nodes
;
4453 free_opnd_error_record_nodes
= record
;
4454 if (operand_error_report
.head
== NULL
)
4456 gas_assert (operand_error_report
.tail
== record
);
4457 operand_error_report
.tail
= NULL
;
4462 /* Given the instruction in *INSTR, return the index of the best matched
4463 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4465 Return -1 if there is no qualifier sequence; return the first match
4466 if there is multiple matches found. */
4469 find_best_match (const aarch64_inst
*instr
,
4470 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4472 int i
, num_opnds
, max_num_matched
, idx
;
4474 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4477 DEBUG_TRACE ("no operand");
4481 max_num_matched
= 0;
4484 /* For each pattern. */
4485 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4488 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4490 /* Most opcodes has much fewer patterns in the list. */
4491 if (empty_qualifier_sequence_p (qualifiers
))
4493 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4497 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4498 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4501 if (num_matched
> max_num_matched
)
4503 max_num_matched
= num_matched
;
4508 DEBUG_TRACE ("return with %d", idx
);
4512 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4513 corresponding operands in *INSTR. */
4516 assign_qualifier_sequence (aarch64_inst
*instr
,
4517 const aarch64_opnd_qualifier_t
*qualifiers
)
4520 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4521 gas_assert (num_opnds
);
4522 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4523 instr
->operands
[i
].qualifier
= *qualifiers
;
4526 /* Print operands for the diagnosis purpose. */
4529 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4530 const aarch64_opnd_info
*opnds
)
4534 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4538 /* We regard the opcode operand info more, however we also look into
4539 the inst->operands to support the disassembling of the optional
4541 The two operand code should be the same in all cases, apart from
4542 when the operand can be optional. */
4543 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4544 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4547 /* Generate the operand string in STR. */
4548 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4552 strcat (buf
, i
== 0 ? " " : ", ");
4554 /* Append the operand string. */
4559 /* Send to stderr a string as information. */
4562 output_info (const char *format
, ...)
4568 file
= as_where (&line
);
4572 fprintf (stderr
, "%s:%u: ", file
, line
);
4574 fprintf (stderr
, "%s: ", file
);
4576 fprintf (stderr
, _("Info: "));
4577 va_start (args
, format
);
4578 vfprintf (stderr
, format
, args
);
4580 (void) putc ('\n', stderr
);
4583 /* Output one operand error record. */
4586 output_operand_error_record (const operand_error_record
*record
, char *str
)
4588 const aarch64_operand_error
*detail
= &record
->detail
;
4589 int idx
= detail
->index
;
4590 const aarch64_opcode
*opcode
= record
->opcode
;
4591 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4592 : AARCH64_OPND_NIL
);
4594 switch (detail
->kind
)
4596 case AARCH64_OPDE_NIL
:
4600 case AARCH64_OPDE_SYNTAX_ERROR
:
4601 case AARCH64_OPDE_RECOVERABLE
:
4602 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4603 case AARCH64_OPDE_OTHER_ERROR
:
4604 /* Use the prepared error message if there is, otherwise use the
4605 operand description string to describe the error. */
4606 if (detail
->error
!= NULL
)
4609 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4611 as_bad (_("%s at operand %d -- `%s'"),
4612 detail
->error
, idx
+ 1, str
);
4616 gas_assert (idx
>= 0);
4617 as_bad (_("operand %d must be %s -- `%s'"), idx
+ 1,
4618 aarch64_get_operand_desc (opd_code
), str
);
4622 case AARCH64_OPDE_INVALID_VARIANT
:
4623 as_bad (_("operand mismatch -- `%s'"), str
);
4624 if (verbose_error_p
)
4626 /* We will try to correct the erroneous instruction and also provide
4627 more information e.g. all other valid variants.
4629 The string representation of the corrected instruction and other
4630 valid variants are generated by
4632 1) obtaining the intermediate representation of the erroneous
4634 2) manipulating the IR, e.g. replacing the operand qualifier;
4635 3) printing out the instruction by calling the printer functions
4636 shared with the disassembler.
4638 The limitation of this method is that the exact input assembly
4639 line cannot be accurately reproduced in some cases, for example an
4640 optional operand present in the actual assembly line will be
4641 omitted in the output; likewise for the optional syntax rules,
4642 e.g. the # before the immediate. Another limitation is that the
4643 assembly symbols and relocation operations in the assembly line
4644 currently cannot be printed out in the error report. Last but not
4645 least, when there is other error(s) co-exist with this error, the
4646 'corrected' instruction may be still incorrect, e.g. given
4647 'ldnp h0,h1,[x0,#6]!'
4648 this diagnosis will provide the version:
4649 'ldnp s0,s1,[x0,#6]!'
4650 which is still not right. */
4651 size_t len
= strlen (get_mnemonic_name (str
));
4655 aarch64_inst
*inst_base
= &inst
.base
;
4656 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4659 reset_aarch64_instruction (&inst
);
4660 inst_base
->opcode
= opcode
;
4662 /* Reset the error report so that there is no side effect on the
4663 following operand parsing. */
4664 init_operand_error_report ();
4667 result
= parse_operands (str
+ len
, opcode
)
4668 && programmer_friendly_fixup (&inst
);
4669 gas_assert (result
);
4670 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4672 gas_assert (!result
);
4674 /* Find the most matched qualifier sequence. */
4675 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4676 gas_assert (qlf_idx
> -1);
4678 /* Assign the qualifiers. */
4679 assign_qualifier_sequence (inst_base
,
4680 opcode
->qualifiers_list
[qlf_idx
]);
4682 /* Print the hint. */
4683 output_info (_(" did you mean this?"));
4684 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4685 print_operands (buf
, opcode
, inst_base
->operands
);
4686 output_info (_(" %s"), buf
);
4688 /* Print out other variant(s) if there is any. */
4690 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4691 output_info (_(" other valid variant(s):"));
4693 /* For each pattern. */
4694 qualifiers_list
= opcode
->qualifiers_list
;
4695 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4697 /* Most opcodes has much fewer patterns in the list.
4698 First NIL qualifier indicates the end in the list. */
4699 if (empty_qualifier_sequence_p (*qualifiers_list
))
4704 /* Mnemonics name. */
4705 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4707 /* Assign the qualifiers. */
4708 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4710 /* Print instruction. */
4711 print_operands (buf
, opcode
, inst_base
->operands
);
4713 output_info (_(" %s"), buf
);
4719 case AARCH64_OPDE_UNTIED_OPERAND
:
4720 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4721 detail
->index
+ 1, str
);
4724 case AARCH64_OPDE_OUT_OF_RANGE
:
4725 if (detail
->data
[0] != detail
->data
[1])
4726 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4727 detail
->error
? detail
->error
: _("immediate value"),
4728 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4730 as_bad (_("%s must be %d at operand %d -- `%s'"),
4731 detail
->error
? detail
->error
: _("immediate value"),
4732 detail
->data
[0], idx
+ 1, str
);
4735 case AARCH64_OPDE_REG_LIST
:
4736 if (detail
->data
[0] == 1)
4737 as_bad (_("invalid number of registers in the list; "
4738 "only 1 register is expected at operand %d -- `%s'"),
4741 as_bad (_("invalid number of registers in the list; "
4742 "%d registers are expected at operand %d -- `%s'"),
4743 detail
->data
[0], idx
+ 1, str
);
4746 case AARCH64_OPDE_UNALIGNED
:
4747 as_bad (_("immediate value must be a multiple of "
4748 "%d at operand %d -- `%s'"),
4749 detail
->data
[0], idx
+ 1, str
);
4758 /* Process and output the error message about the operand mismatching.
4760 When this function is called, the operand error information had
4761 been collected for an assembly line and there will be multiple
4762 errors in the case of multiple instruction templates; output the
4763 error message that most closely describes the problem. */
4766 output_operand_error_report (char *str
)
4768 int largest_error_pos
;
4769 const char *msg
= NULL
;
4770 enum aarch64_operand_error_kind kind
;
4771 operand_error_record
*curr
;
4772 operand_error_record
*head
= operand_error_report
.head
;
4773 operand_error_record
*record
= NULL
;
4775 /* No error to report. */
4779 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4781 /* Only one error. */
4782 if (head
== operand_error_report
.tail
)
4784 DEBUG_TRACE ("single opcode entry with error kind: %s",
4785 operand_mismatch_kind_names
[head
->detail
.kind
]);
4786 output_operand_error_record (head
, str
);
4790 /* Find the error kind of the highest severity. */
4791 DEBUG_TRACE ("multiple opcode entries with error kind");
4792 kind
= AARCH64_OPDE_NIL
;
4793 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4795 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4796 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4797 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4798 kind
= curr
->detail
.kind
;
4800 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4802 /* Pick up one of errors of KIND to report. */
4803 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4804 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4806 if (curr
->detail
.kind
!= kind
)
4808 /* If there are multiple errors, pick up the one with the highest
4809 mismatching operand index. In the case of multiple errors with
4810 the equally highest operand index, pick up the first one or the
4811 first one with non-NULL error message. */
4812 if (curr
->detail
.index
> largest_error_pos
4813 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4814 && curr
->detail
.error
!= NULL
))
4816 largest_error_pos
= curr
->detail
.index
;
4818 msg
= record
->detail
.error
;
4822 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4823 DEBUG_TRACE ("Pick up error kind %s to report",
4824 operand_mismatch_kind_names
[record
->detail
.kind
]);
4827 output_operand_error_record (record
, str
);
4830 /* Write an AARCH64 instruction to buf - always little-endian. */
4832 put_aarch64_insn (char *buf
, uint32_t insn
)
4834 unsigned char *where
= (unsigned char *) buf
;
4836 where
[1] = insn
>> 8;
4837 where
[2] = insn
>> 16;
4838 where
[3] = insn
>> 24;
4842 get_aarch64_insn (char *buf
)
4844 unsigned char *where
= (unsigned char *) buf
;
4846 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4851 output_inst (struct aarch64_inst
*new_inst
)
4855 to
= frag_more (INSN_SIZE
);
4857 frag_now
->tc_frag_data
.recorded
= 1;
4859 put_aarch64_insn (to
, inst
.base
.value
);
4861 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4863 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4864 INSN_SIZE
, &inst
.reloc
.exp
,
4867 DEBUG_TRACE ("Prepared relocation fix up");
4868 /* Don't check the addend value against the instruction size,
4869 that's the job of our code in md_apply_fix(). */
4870 fixp
->fx_no_overflow
= 1;
4871 if (new_inst
!= NULL
)
4872 fixp
->tc_fix_data
.inst
= new_inst
;
4873 if (aarch64_gas_internal_fixup_p ())
4875 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4876 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4877 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4881 dwarf2_emit_insn (INSN_SIZE
);
4884 /* Link together opcodes of the same name. */
4888 aarch64_opcode
*opcode
;
4889 struct templates
*next
;
4892 typedef struct templates templates
;
4895 lookup_mnemonic (const char *start
, int len
)
4897 templates
*templ
= NULL
;
4899 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4903 /* Subroutine of md_assemble, responsible for looking up the primary
4904 opcode from the mnemonic the user wrote. STR points to the
4905 beginning of the mnemonic. */
4908 opcode_lookup (char **str
)
4910 char *end
, *base
, *dot
;
4911 const aarch64_cond
*cond
;
4915 /* Scan up to the end of the mnemonic, which must end in white space,
4916 '.', or end of string. */
4918 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4919 if (*end
== '.' && !dot
)
4922 if (end
== base
|| dot
== base
)
4925 inst
.cond
= COND_ALWAYS
;
4927 /* Handle a possible condition. */
4930 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
4933 inst
.cond
= cond
->value
;
4949 if (inst
.cond
== COND_ALWAYS
)
4951 /* Look for unaffixed mnemonic. */
4952 return lookup_mnemonic (base
, len
);
4956 /* append ".c" to mnemonic if conditional */
4957 memcpy (condname
, base
, len
);
4958 memcpy (condname
+ len
, ".c", 2);
4961 return lookup_mnemonic (base
, len
);
4967 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4968 to a corresponding operand qualifier. */
4970 static inline aarch64_opnd_qualifier_t
4971 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4973 /* Element size in bytes indexed by vector_el_type. */
4974 const unsigned char ele_size
[5]
4976 const unsigned int ele_base
[5] =
4978 AARCH64_OPND_QLF_V_4B
,
4979 AARCH64_OPND_QLF_V_2H
,
4980 AARCH64_OPND_QLF_V_2S
,
4981 AARCH64_OPND_QLF_V_1D
,
4982 AARCH64_OPND_QLF_V_1Q
4985 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4986 goto vectype_conversion_fail
;
4988 if (vectype
->type
== NT_zero
)
4989 return AARCH64_OPND_QLF_P_Z
;
4990 if (vectype
->type
== NT_merge
)
4991 return AARCH64_OPND_QLF_P_M
;
4993 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4995 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
4997 /* Special case S_4B. */
4998 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
4999 return AARCH64_OPND_QLF_S_4B
;
5001 /* Vector element register. */
5002 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5006 /* Vector register. */
5007 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5010 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5011 goto vectype_conversion_fail
;
5013 /* The conversion is by calculating the offset from the base operand
5014 qualifier for the vector type. The operand qualifiers are regular
5015 enough that the offset can established by shifting the vector width by
5016 a vector-type dependent amount. */
5018 if (vectype
->type
== NT_b
)
5020 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5022 else if (vectype
->type
>= NT_d
)
5027 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5028 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5029 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5033 vectype_conversion_fail
:
5034 first_error (_("bad vector arrangement type"));
5035 return AARCH64_OPND_QLF_NIL
;
5038 /* Process an optional operand that is found omitted from the assembly line.
5039 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5040 instruction's opcode entry while IDX is the index of this omitted operand.
5044 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5045 int idx
, aarch64_opnd_info
*operand
)
5047 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5048 gas_assert (optional_operand_p (opcode
, idx
));
5049 gas_assert (!operand
->present
);
5053 case AARCH64_OPND_Rd
:
5054 case AARCH64_OPND_Rn
:
5055 case AARCH64_OPND_Rm
:
5056 case AARCH64_OPND_Rt
:
5057 case AARCH64_OPND_Rt2
:
5058 case AARCH64_OPND_Rs
:
5059 case AARCH64_OPND_Ra
:
5060 case AARCH64_OPND_Rt_SYS
:
5061 case AARCH64_OPND_Rd_SP
:
5062 case AARCH64_OPND_Rn_SP
:
5063 case AARCH64_OPND_Rm_SP
:
5064 case AARCH64_OPND_Fd
:
5065 case AARCH64_OPND_Fn
:
5066 case AARCH64_OPND_Fm
:
5067 case AARCH64_OPND_Fa
:
5068 case AARCH64_OPND_Ft
:
5069 case AARCH64_OPND_Ft2
:
5070 case AARCH64_OPND_Sd
:
5071 case AARCH64_OPND_Sn
:
5072 case AARCH64_OPND_Sm
:
5073 case AARCH64_OPND_Va
:
5074 case AARCH64_OPND_Vd
:
5075 case AARCH64_OPND_Vn
:
5076 case AARCH64_OPND_Vm
:
5077 case AARCH64_OPND_VdD1
:
5078 case AARCH64_OPND_VnD1
:
5079 operand
->reg
.regno
= default_value
;
5082 case AARCH64_OPND_Ed
:
5083 case AARCH64_OPND_En
:
5084 case AARCH64_OPND_Em
:
5085 case AARCH64_OPND_SM3_IMM2
:
5086 operand
->reglane
.regno
= default_value
;
5089 case AARCH64_OPND_IDX
:
5090 case AARCH64_OPND_BIT_NUM
:
5091 case AARCH64_OPND_IMMR
:
5092 case AARCH64_OPND_IMMS
:
5093 case AARCH64_OPND_SHLL_IMM
:
5094 case AARCH64_OPND_IMM_VLSL
:
5095 case AARCH64_OPND_IMM_VLSR
:
5096 case AARCH64_OPND_CCMP_IMM
:
5097 case AARCH64_OPND_FBITS
:
5098 case AARCH64_OPND_UIMM4
:
5099 case AARCH64_OPND_UIMM3_OP1
:
5100 case AARCH64_OPND_UIMM3_OP2
:
5101 case AARCH64_OPND_IMM
:
5102 case AARCH64_OPND_IMM_2
:
5103 case AARCH64_OPND_WIDTH
:
5104 case AARCH64_OPND_UIMM7
:
5105 case AARCH64_OPND_NZCV
:
5106 case AARCH64_OPND_SVE_PATTERN
:
5107 case AARCH64_OPND_SVE_PRFOP
:
5108 operand
->imm
.value
= default_value
;
5111 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5112 operand
->imm
.value
= default_value
;
5113 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5114 operand
->shifter
.amount
= 1;
5117 case AARCH64_OPND_EXCEPTION
:
5118 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5121 case AARCH64_OPND_BARRIER_ISB
:
5122 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5129 /* Process the relocation type for move wide instructions.
5130 Return TRUE on success; otherwise return FALSE. */
5133 process_movw_reloc_info (void)
5138 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5140 if (inst
.base
.opcode
->op
== OP_MOVK
)
5141 switch (inst
.reloc
.type
)
5143 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5144 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5145 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5146 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5147 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5148 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5149 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5150 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5151 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5152 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5153 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5155 (_("the specified relocation type is not allowed for MOVK"));
5161 switch (inst
.reloc
.type
)
5163 case BFD_RELOC_AARCH64_MOVW_G0
:
5164 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5165 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5166 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5167 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5168 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5169 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5170 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5171 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5172 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5173 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5174 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5175 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5178 case BFD_RELOC_AARCH64_MOVW_G1
:
5179 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5180 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5181 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5182 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5183 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5184 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5185 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5186 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5187 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5188 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5189 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5190 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5193 case BFD_RELOC_AARCH64_MOVW_G2
:
5194 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5195 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5196 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5197 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5198 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5199 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5202 set_fatal_syntax_error
5203 (_("the specified relocation type is not allowed for 32-bit "
5209 case BFD_RELOC_AARCH64_MOVW_G3
:
5210 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5213 set_fatal_syntax_error
5214 (_("the specified relocation type is not allowed for 32-bit "
5221 /* More cases should be added when more MOVW-related relocation types
5222 are supported in GAS. */
5223 gas_assert (aarch64_gas_internal_fixup_p ());
5224 /* The shift amount should have already been set by the parser. */
5227 inst
.base
.operands
[1].shifter
.amount
= shift
;
5231 /* A primitive log calculator. */
5233 static inline unsigned int
5234 get_logsz (unsigned int size
)
5236 const unsigned char ls
[16] =
5237 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5243 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5244 return ls
[size
- 1];
5247 /* Determine and return the real reloc type code for an instruction
5248 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5250 static inline bfd_reloc_code_real_type
5251 ldst_lo12_determine_real_reloc_type (void)
5254 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5255 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5257 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
5259 BFD_RELOC_AARCH64_LDST8_LO12
,
5260 BFD_RELOC_AARCH64_LDST16_LO12
,
5261 BFD_RELOC_AARCH64_LDST32_LO12
,
5262 BFD_RELOC_AARCH64_LDST64_LO12
,
5263 BFD_RELOC_AARCH64_LDST128_LO12
5266 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5267 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5268 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5269 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5270 BFD_RELOC_AARCH64_NONE
5273 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5274 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5275 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5276 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5277 BFD_RELOC_AARCH64_NONE
5281 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5282 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5284 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
5285 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5287 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5289 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5291 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5293 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5294 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5295 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5296 gas_assert (logsz
<= 3);
5298 gas_assert (logsz
<= 4);
5300 /* In reloc.c, these pseudo relocation types should be defined in similar
5301 order as above reloc_ldst_lo12 array. Because the array index calculation
5302 below relies on this. */
5303 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5306 /* Check whether a register list REGINFO is valid. The registers must be
5307 numbered in increasing order (modulo 32), in increments of one or two.
5309 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5312 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5315 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5317 uint32_t i
, nb_regs
, prev_regno
, incr
;
5319 nb_regs
= 1 + (reginfo
& 0x3);
5321 prev_regno
= reginfo
& 0x1f;
5322 incr
= accept_alternate
? 2 : 1;
5324 for (i
= 1; i
< nb_regs
; ++i
)
5326 uint32_t curr_regno
;
5328 curr_regno
= reginfo
& 0x1f;
5329 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5331 prev_regno
= curr_regno
;
5337 /* Generic instruction operand parser. This does no encoding and no
5338 semantic validation; it merely squirrels values away in the inst
5339 structure. Returns TRUE or FALSE depending on whether the
5340 specified grammar matched. */
5343 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5346 char *backtrack_pos
= 0;
5347 const enum aarch64_opnd
*operands
= opcode
->operands
;
5348 aarch64_reg_type imm_reg_type
;
5351 skip_whitespace (str
);
5353 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5354 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5356 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5358 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5361 const reg_entry
*reg
;
5362 int comma_skipped_p
= 0;
5363 aarch64_reg_type rtype
;
5364 struct vector_type_el vectype
;
5365 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5366 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5367 aarch64_reg_type reg_type
;
5369 DEBUG_TRACE ("parse operand %d", i
);
5371 /* Assign the operand code. */
5372 info
->type
= operands
[i
];
5374 if (optional_operand_p (opcode
, i
))
5376 /* Remember where we are in case we need to backtrack. */
5377 gas_assert (!backtrack_pos
);
5378 backtrack_pos
= str
;
5381 /* Expect comma between operands; the backtrack mechanism will take
5382 care of cases of omitted optional operand. */
5383 if (i
> 0 && ! skip_past_char (&str
, ','))
5385 set_syntax_error (_("comma expected between operands"));
5389 comma_skipped_p
= 1;
5391 switch (operands
[i
])
5393 case AARCH64_OPND_Rd
:
5394 case AARCH64_OPND_Rn
:
5395 case AARCH64_OPND_Rm
:
5396 case AARCH64_OPND_Rt
:
5397 case AARCH64_OPND_Rt2
:
5398 case AARCH64_OPND_Rs
:
5399 case AARCH64_OPND_Ra
:
5400 case AARCH64_OPND_Rt_SYS
:
5401 case AARCH64_OPND_PAIRREG
:
5402 case AARCH64_OPND_SVE_Rm
:
5403 po_int_reg_or_fail (REG_TYPE_R_Z
);
5406 case AARCH64_OPND_Rd_SP
:
5407 case AARCH64_OPND_Rn_SP
:
5408 case AARCH64_OPND_SVE_Rn_SP
:
5409 case AARCH64_OPND_Rm_SP
:
5410 po_int_reg_or_fail (REG_TYPE_R_SP
);
5413 case AARCH64_OPND_Rm_EXT
:
5414 case AARCH64_OPND_Rm_SFT
:
5415 po_misc_or_fail (parse_shifter_operand
5416 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5418 : SHIFTED_LOGIC_IMM
)));
5419 if (!info
->shifter
.operator_present
)
5421 /* Default to LSL if not present. Libopcodes prefers shifter
5422 kind to be explicit. */
5423 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5424 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5425 /* For Rm_EXT, libopcodes will carry out further check on whether
5426 or not stack pointer is used in the instruction (Recall that
5427 "the extend operator is not optional unless at least one of
5428 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5432 case AARCH64_OPND_Fd
:
5433 case AARCH64_OPND_Fn
:
5434 case AARCH64_OPND_Fm
:
5435 case AARCH64_OPND_Fa
:
5436 case AARCH64_OPND_Ft
:
5437 case AARCH64_OPND_Ft2
:
5438 case AARCH64_OPND_Sd
:
5439 case AARCH64_OPND_Sn
:
5440 case AARCH64_OPND_Sm
:
5441 case AARCH64_OPND_SVE_VZn
:
5442 case AARCH64_OPND_SVE_Vd
:
5443 case AARCH64_OPND_SVE_Vm
:
5444 case AARCH64_OPND_SVE_Vn
:
5445 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5446 if (val
== PARSE_FAIL
)
5448 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5451 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5453 info
->reg
.regno
= val
;
5454 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5457 case AARCH64_OPND_SVE_Pd
:
5458 case AARCH64_OPND_SVE_Pg3
:
5459 case AARCH64_OPND_SVE_Pg4_5
:
5460 case AARCH64_OPND_SVE_Pg4_10
:
5461 case AARCH64_OPND_SVE_Pg4_16
:
5462 case AARCH64_OPND_SVE_Pm
:
5463 case AARCH64_OPND_SVE_Pn
:
5464 case AARCH64_OPND_SVE_Pt
:
5465 reg_type
= REG_TYPE_PN
;
5468 case AARCH64_OPND_SVE_Za_5
:
5469 case AARCH64_OPND_SVE_Za_16
:
5470 case AARCH64_OPND_SVE_Zd
:
5471 case AARCH64_OPND_SVE_Zm_5
:
5472 case AARCH64_OPND_SVE_Zm_16
:
5473 case AARCH64_OPND_SVE_Zn
:
5474 case AARCH64_OPND_SVE_Zt
:
5475 reg_type
= REG_TYPE_ZN
;
5478 case AARCH64_OPND_Va
:
5479 case AARCH64_OPND_Vd
:
5480 case AARCH64_OPND_Vn
:
5481 case AARCH64_OPND_Vm
:
5482 reg_type
= REG_TYPE_VN
;
5484 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5485 if (val
== PARSE_FAIL
)
5487 first_error (_(get_reg_expected_msg (reg_type
)));
5490 if (vectype
.defined
& NTA_HASINDEX
)
5493 info
->reg
.regno
= val
;
5494 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5495 && vectype
.type
== NT_invtype
)
5496 /* Unqualified Pn and Zn registers are allowed in certain
5497 contexts. Rely on F_STRICT qualifier checking to catch
5499 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5502 info
->qualifier
= vectype_to_qualifier (&vectype
);
5503 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5508 case AARCH64_OPND_VdD1
:
5509 case AARCH64_OPND_VnD1
:
5510 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5511 if (val
== PARSE_FAIL
)
5513 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5516 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5518 set_fatal_syntax_error
5519 (_("the top half of a 128-bit FP/SIMD register is expected"));
5522 info
->reg
.regno
= val
;
5523 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5524 here; it is correct for the purpose of encoding/decoding since
5525 only the register number is explicitly encoded in the related
5526 instructions, although this appears a bit hacky. */
5527 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5530 case AARCH64_OPND_SVE_Zm3_INDEX
:
5531 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5532 case AARCH64_OPND_SVE_Zm4_INDEX
:
5533 case AARCH64_OPND_SVE_Zn_INDEX
:
5534 reg_type
= REG_TYPE_ZN
;
5535 goto vector_reg_index
;
5537 case AARCH64_OPND_Ed
:
5538 case AARCH64_OPND_En
:
5539 case AARCH64_OPND_Em
:
5540 case AARCH64_OPND_SM3_IMM2
:
5541 reg_type
= REG_TYPE_VN
;
5543 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5544 if (val
== PARSE_FAIL
)
5546 first_error (_(get_reg_expected_msg (reg_type
)));
5549 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5552 info
->reglane
.regno
= val
;
5553 info
->reglane
.index
= vectype
.index
;
5554 info
->qualifier
= vectype_to_qualifier (&vectype
);
5555 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5559 case AARCH64_OPND_SVE_ZnxN
:
5560 case AARCH64_OPND_SVE_ZtxN
:
5561 reg_type
= REG_TYPE_ZN
;
5562 goto vector_reg_list
;
5564 case AARCH64_OPND_LVn
:
5565 case AARCH64_OPND_LVt
:
5566 case AARCH64_OPND_LVt_AL
:
5567 case AARCH64_OPND_LEt
:
5568 reg_type
= REG_TYPE_VN
;
5570 if (reg_type
== REG_TYPE_ZN
5571 && get_opcode_dependent_value (opcode
) == 1
5574 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5575 if (val
== PARSE_FAIL
)
5577 first_error (_(get_reg_expected_msg (reg_type
)));
5580 info
->reglist
.first_regno
= val
;
5581 info
->reglist
.num_regs
= 1;
5585 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5586 if (val
== PARSE_FAIL
)
5588 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5590 set_fatal_syntax_error (_("invalid register list"));
5593 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5594 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5596 if (operands
[i
] == AARCH64_OPND_LEt
)
5598 if (!(vectype
.defined
& NTA_HASINDEX
))
5600 info
->reglist
.has_index
= 1;
5601 info
->reglist
.index
= vectype
.index
;
5605 if (vectype
.defined
& NTA_HASINDEX
)
5607 if (!(vectype
.defined
& NTA_HASTYPE
))
5609 if (reg_type
== REG_TYPE_ZN
)
5610 set_fatal_syntax_error (_("missing type suffix"));
5614 info
->qualifier
= vectype_to_qualifier (&vectype
);
5615 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5619 case AARCH64_OPND_CRn
:
5620 case AARCH64_OPND_CRm
:
5622 char prefix
= *(str
++);
5623 if (prefix
!= 'c' && prefix
!= 'C')
5626 po_imm_nc_or_fail ();
5629 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5632 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5633 info
->imm
.value
= val
;
5637 case AARCH64_OPND_SHLL_IMM
:
5638 case AARCH64_OPND_IMM_VLSR
:
5639 po_imm_or_fail (1, 64);
5640 info
->imm
.value
= val
;
5643 case AARCH64_OPND_CCMP_IMM
:
5644 case AARCH64_OPND_SIMM5
:
5645 case AARCH64_OPND_FBITS
:
5646 case AARCH64_OPND_UIMM4
:
5647 case AARCH64_OPND_UIMM3_OP1
:
5648 case AARCH64_OPND_UIMM3_OP2
:
5649 case AARCH64_OPND_IMM_VLSL
:
5650 case AARCH64_OPND_IMM
:
5651 case AARCH64_OPND_IMM_2
:
5652 case AARCH64_OPND_WIDTH
:
5653 case AARCH64_OPND_SVE_INV_LIMM
:
5654 case AARCH64_OPND_SVE_LIMM
:
5655 case AARCH64_OPND_SVE_LIMM_MOV
:
5656 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5657 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5658 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5659 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5660 case AARCH64_OPND_SVE_SIMM5
:
5661 case AARCH64_OPND_SVE_SIMM5B
:
5662 case AARCH64_OPND_SVE_SIMM6
:
5663 case AARCH64_OPND_SVE_SIMM8
:
5664 case AARCH64_OPND_SVE_UIMM3
:
5665 case AARCH64_OPND_SVE_UIMM7
:
5666 case AARCH64_OPND_SVE_UIMM8
:
5667 case AARCH64_OPND_SVE_UIMM8_53
:
5668 case AARCH64_OPND_IMM_ROT1
:
5669 case AARCH64_OPND_IMM_ROT2
:
5670 case AARCH64_OPND_IMM_ROT3
:
5671 case AARCH64_OPND_SVE_IMM_ROT1
:
5672 case AARCH64_OPND_SVE_IMM_ROT2
:
5673 po_imm_nc_or_fail ();
5674 info
->imm
.value
= val
;
5677 case AARCH64_OPND_SVE_AIMM
:
5678 case AARCH64_OPND_SVE_ASIMM
:
5679 po_imm_nc_or_fail ();
5680 info
->imm
.value
= val
;
5681 skip_whitespace (str
);
5682 if (skip_past_comma (&str
))
5683 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5685 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5688 case AARCH64_OPND_SVE_PATTERN
:
5689 po_enum_or_fail (aarch64_sve_pattern_array
);
5690 info
->imm
.value
= val
;
5693 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5694 po_enum_or_fail (aarch64_sve_pattern_array
);
5695 info
->imm
.value
= val
;
5696 if (skip_past_comma (&str
)
5697 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5699 if (!info
->shifter
.operator_present
)
5701 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5702 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5703 info
->shifter
.amount
= 1;
5707 case AARCH64_OPND_SVE_PRFOP
:
5708 po_enum_or_fail (aarch64_sve_prfop_array
);
5709 info
->imm
.value
= val
;
5712 case AARCH64_OPND_UIMM7
:
5713 po_imm_or_fail (0, 127);
5714 info
->imm
.value
= val
;
5717 case AARCH64_OPND_IDX
:
5718 case AARCH64_OPND_MASK
:
5719 case AARCH64_OPND_BIT_NUM
:
5720 case AARCH64_OPND_IMMR
:
5721 case AARCH64_OPND_IMMS
:
5722 po_imm_or_fail (0, 63);
5723 info
->imm
.value
= val
;
5726 case AARCH64_OPND_IMM0
:
5727 po_imm_nc_or_fail ();
5730 set_fatal_syntax_error (_("immediate zero expected"));
5733 info
->imm
.value
= 0;
5736 case AARCH64_OPND_FPIMM0
:
5739 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5740 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5741 it is probably not worth the effort to support it. */
5742 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5745 || !(res2
= parse_constant_immediate (&str
, &val
,
5748 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5750 info
->imm
.value
= 0;
5751 info
->imm
.is_fp
= 1;
5754 set_fatal_syntax_error (_("immediate zero expected"));
5758 case AARCH64_OPND_IMM_MOV
:
5761 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5762 reg_name_p (str
, REG_TYPE_VN
))
5765 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5767 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5768 later. fix_mov_imm_insn will try to determine a machine
5769 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5770 message if the immediate cannot be moved by a single
5772 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5773 inst
.base
.operands
[i
].skip
= 1;
5777 case AARCH64_OPND_SIMD_IMM
:
5778 case AARCH64_OPND_SIMD_IMM_SFT
:
5779 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5781 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5783 /* need_libopcodes_p */ 1,
5786 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5787 shift, we don't check it here; we leave the checking to
5788 the libopcodes (operand_general_constraint_met_p). By
5789 doing this, we achieve better diagnostics. */
5790 if (skip_past_comma (&str
)
5791 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5793 if (!info
->shifter
.operator_present
5794 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5796 /* Default to LSL if not present. Libopcodes prefers shifter
5797 kind to be explicit. */
5798 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5799 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5803 case AARCH64_OPND_FPIMM
:
5804 case AARCH64_OPND_SIMD_FPIMM
:
5805 case AARCH64_OPND_SVE_FPIMM8
:
5810 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5811 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5812 || !aarch64_imm_float_p (qfloat
))
5815 set_fatal_syntax_error (_("invalid floating-point"
5819 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5820 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5824 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5825 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5826 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5831 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5832 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5835 set_fatal_syntax_error (_("invalid floating-point"
5839 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5840 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5844 case AARCH64_OPND_LIMM
:
5845 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5846 SHIFTED_LOGIC_IMM
));
5847 if (info
->shifter
.operator_present
)
5849 set_fatal_syntax_error
5850 (_("shift not allowed for bitmask immediate"));
5853 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5855 /* need_libopcodes_p */ 1,
5859 case AARCH64_OPND_AIMM
:
5860 if (opcode
->op
== OP_ADD
)
5861 /* ADD may have relocation types. */
5862 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5863 SHIFTED_ARITH_IMM
));
5865 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5866 SHIFTED_ARITH_IMM
));
5867 switch (inst
.reloc
.type
)
5869 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5870 info
->shifter
.amount
= 12;
5872 case BFD_RELOC_UNUSED
:
5873 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5874 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5875 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5876 inst
.reloc
.pc_rel
= 0;
5881 info
->imm
.value
= 0;
5882 if (!info
->shifter
.operator_present
)
5884 /* Default to LSL if not present. Libopcodes prefers shifter
5885 kind to be explicit. */
5886 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5887 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5891 case AARCH64_OPND_HALF
:
5893 /* #<imm16> or relocation. */
5894 int internal_fixup_p
;
5895 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5896 if (internal_fixup_p
)
5897 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5898 skip_whitespace (str
);
5899 if (skip_past_comma (&str
))
5901 /* {, LSL #<shift>} */
5902 if (! aarch64_gas_internal_fixup_p ())
5904 set_fatal_syntax_error (_("can't mix relocation modifier "
5905 "with explicit shift"));
5908 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5911 inst
.base
.operands
[i
].shifter
.amount
= 0;
5912 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5913 inst
.base
.operands
[i
].imm
.value
= 0;
5914 if (! process_movw_reloc_info ())
5919 case AARCH64_OPND_EXCEPTION
:
5920 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5922 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5924 /* need_libopcodes_p */ 0,
5928 case AARCH64_OPND_NZCV
:
5930 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5934 info
->imm
.value
= nzcv
->value
;
5937 po_imm_or_fail (0, 15);
5938 info
->imm
.value
= val
;
5942 case AARCH64_OPND_COND
:
5943 case AARCH64_OPND_COND1
:
5948 while (ISALPHA (*str
));
5949 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
5950 if (info
->cond
== NULL
)
5952 set_syntax_error (_("invalid condition"));
5955 else if (operands
[i
] == AARCH64_OPND_COND1
5956 && (info
->cond
->value
& 0xe) == 0xe)
5958 /* Do not allow AL or NV. */
5959 set_default_error ();
5965 case AARCH64_OPND_ADDR_ADRP
:
5966 po_misc_or_fail (parse_adrp (&str
));
5967 /* Clear the value as operand needs to be relocated. */
5968 info
->imm
.value
= 0;
5971 case AARCH64_OPND_ADDR_PCREL14
:
5972 case AARCH64_OPND_ADDR_PCREL19
:
5973 case AARCH64_OPND_ADDR_PCREL21
:
5974 case AARCH64_OPND_ADDR_PCREL26
:
5975 po_misc_or_fail (parse_address (&str
, info
));
5976 if (!info
->addr
.pcrel
)
5978 set_syntax_error (_("invalid pc-relative address"));
5981 if (inst
.gen_lit_pool
5982 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5984 /* Only permit "=value" in the literal load instructions.
5985 The literal will be generated by programmer_friendly_fixup. */
5986 set_syntax_error (_("invalid use of \"=immediate\""));
5989 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5991 set_syntax_error (_("unrecognized relocation suffix"));
5994 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5996 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5997 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6001 info
->imm
.value
= 0;
6002 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6003 switch (opcode
->iclass
)
6007 /* e.g. CBZ or B.COND */
6008 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6009 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6013 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6014 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6018 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6020 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6021 : BFD_RELOC_AARCH64_JUMP26
;
6024 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6025 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6028 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6029 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6035 inst
.reloc
.pc_rel
= 1;
6039 case AARCH64_OPND_ADDR_SIMPLE
:
6040 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6042 /* [<Xn|SP>{, #<simm>}] */
6044 /* First use the normal address-parsing routines, to get
6045 the usual syntax errors. */
6046 po_misc_or_fail (parse_address (&str
, info
));
6047 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6048 || !info
->addr
.preind
|| info
->addr
.postind
6049 || info
->addr
.writeback
)
6051 set_syntax_error (_("invalid addressing mode"));
6055 /* Then retry, matching the specific syntax of these addresses. */
6057 po_char_or_fail ('[');
6058 po_reg_or_fail (REG_TYPE_R64_SP
);
6059 /* Accept optional ", #0". */
6060 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6061 && skip_past_char (&str
, ','))
6063 skip_past_char (&str
, '#');
6064 if (! skip_past_char (&str
, '0'))
6066 set_fatal_syntax_error
6067 (_("the optional immediate offset can only be 0"));
6071 po_char_or_fail (']');
6075 case AARCH64_OPND_ADDR_REGOFF
:
6076 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6077 po_misc_or_fail (parse_address (&str
, info
));
6079 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6080 || !info
->addr
.preind
|| info
->addr
.postind
6081 || info
->addr
.writeback
)
6083 set_syntax_error (_("invalid addressing mode"));
6086 if (!info
->shifter
.operator_present
)
6088 /* Default to LSL if not present. Libopcodes prefers shifter
6089 kind to be explicit. */
6090 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6091 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6093 /* Qualifier to be deduced by libopcodes. */
6096 case AARCH64_OPND_ADDR_SIMM7
:
6097 po_misc_or_fail (parse_address (&str
, info
));
6098 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6099 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6101 set_syntax_error (_("invalid addressing mode"));
6104 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6106 set_syntax_error (_("relocation not allowed"));
6109 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6111 /* need_libopcodes_p */ 1,
6115 case AARCH64_OPND_ADDR_SIMM9
:
6116 case AARCH64_OPND_ADDR_SIMM9_2
:
6117 po_misc_or_fail (parse_address (&str
, info
));
6118 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6119 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6120 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6121 && info
->addr
.writeback
))
6123 set_syntax_error (_("invalid addressing mode"));
6126 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6128 set_syntax_error (_("relocation not allowed"));
6131 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6133 /* need_libopcodes_p */ 1,
6137 case AARCH64_OPND_ADDR_SIMM10
:
6138 case AARCH64_OPND_ADDR_OFFSET
:
6139 po_misc_or_fail (parse_address (&str
, info
));
6140 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6141 || !info
->addr
.preind
|| info
->addr
.postind
)
6143 set_syntax_error (_("invalid addressing mode"));
6146 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6148 set_syntax_error (_("relocation not allowed"));
6151 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6153 /* need_libopcodes_p */ 1,
6157 case AARCH64_OPND_ADDR_UIMM12
:
6158 po_misc_or_fail (parse_address (&str
, info
));
6159 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6160 || !info
->addr
.preind
|| info
->addr
.writeback
)
6162 set_syntax_error (_("invalid addressing mode"));
6165 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6166 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6167 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6169 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6171 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
6172 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6173 /* Leave qualifier to be determined by libopcodes. */
6176 case AARCH64_OPND_SIMD_ADDR_POST
:
6177 /* [<Xn|SP>], <Xm|#<amount>> */
6178 po_misc_or_fail (parse_address (&str
, info
));
6179 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6181 set_syntax_error (_("invalid addressing mode"));
6184 if (!info
->addr
.offset
.is_reg
)
6186 if (inst
.reloc
.exp
.X_op
== O_constant
)
6187 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6190 set_fatal_syntax_error
6191 (_("writeback value must be an immediate constant"));
6198 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6199 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6200 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6201 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6202 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6203 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6204 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6205 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6206 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6207 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6208 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6209 /* [X<n>{, #imm, MUL VL}]
6211 but recognizing SVE registers. */
6212 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6213 &offset_qualifier
));
6214 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6216 set_syntax_error (_("invalid addressing mode"));
6220 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6221 || !info
->addr
.preind
|| info
->addr
.writeback
)
6223 set_syntax_error (_("invalid addressing mode"));
6226 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6227 || inst
.reloc
.exp
.X_op
!= O_constant
)
6229 /* Make sure this has priority over
6230 "invalid addressing mode". */
6231 set_fatal_syntax_error (_("constant offset required"));
6234 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6237 case AARCH64_OPND_SVE_ADDR_R
:
6238 /* [<Xn|SP>{, <R><m>}]
6239 but recognizing SVE registers. */
6240 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6241 &offset_qualifier
));
6242 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6244 offset_qualifier
= AARCH64_OPND_QLF_X
;
6245 info
->addr
.offset
.is_reg
= 1;
6246 info
->addr
.offset
.regno
= 31;
6248 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6249 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6251 set_syntax_error (_("invalid addressing mode"));
6256 case AARCH64_OPND_SVE_ADDR_RR
:
6257 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6258 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6259 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6260 case AARCH64_OPND_SVE_ADDR_RX
:
6261 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6262 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6263 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6264 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6265 but recognizing SVE registers. */
6266 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6267 &offset_qualifier
));
6268 if (base_qualifier
!= AARCH64_OPND_QLF_X
6269 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6271 set_syntax_error (_("invalid addressing mode"));
6276 case AARCH64_OPND_SVE_ADDR_RZ
:
6277 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6278 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6279 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6280 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6281 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6282 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6283 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6284 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6285 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6286 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6287 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6288 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6289 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6290 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6291 &offset_qualifier
));
6292 if (base_qualifier
!= AARCH64_OPND_QLF_X
6293 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6294 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6296 set_syntax_error (_("invalid addressing mode"));
6299 info
->qualifier
= offset_qualifier
;
6302 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6303 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6304 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6305 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6306 /* [Z<n>.<T>{, #imm}] */
6307 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6308 &offset_qualifier
));
6309 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6310 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6312 set_syntax_error (_("invalid addressing mode"));
6315 info
->qualifier
= base_qualifier
;
6318 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6319 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6320 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6321 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6322 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6326 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6328 here since we get better error messages by leaving it to
6329 the qualifier checking routines. */
6330 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6331 &offset_qualifier
));
6332 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6333 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6334 || offset_qualifier
!= base_qualifier
)
6336 set_syntax_error (_("invalid addressing mode"));
6339 info
->qualifier
= base_qualifier
;
6342 case AARCH64_OPND_SYSREG
:
6343 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
6346 set_syntax_error (_("unknown or missing system register name"));
6349 inst
.base
.operands
[i
].sysreg
= val
;
6352 case AARCH64_OPND_PSTATEFIELD
:
6353 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
6356 set_syntax_error (_("unknown or missing PSTATE field name"));
6359 inst
.base
.operands
[i
].pstatefield
= val
;
6362 case AARCH64_OPND_SYSREG_IC
:
6363 inst
.base
.operands
[i
].sysins_op
=
6364 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6366 case AARCH64_OPND_SYSREG_DC
:
6367 inst
.base
.operands
[i
].sysins_op
=
6368 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6370 case AARCH64_OPND_SYSREG_AT
:
6371 inst
.base
.operands
[i
].sysins_op
=
6372 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6374 case AARCH64_OPND_SYSREG_TLBI
:
6375 inst
.base
.operands
[i
].sysins_op
=
6376 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6378 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6380 set_fatal_syntax_error ( _("unknown or missing operation name"));
6385 case AARCH64_OPND_BARRIER
:
6386 case AARCH64_OPND_BARRIER_ISB
:
6387 val
= parse_barrier (&str
);
6388 if (val
!= PARSE_FAIL
6389 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6391 /* ISB only accepts options name 'sy'. */
6393 (_("the specified option is not accepted in ISB"));
6394 /* Turn off backtrack as this optional operand is present. */
6398 /* This is an extension to accept a 0..15 immediate. */
6399 if (val
== PARSE_FAIL
)
6400 po_imm_or_fail (0, 15);
6401 info
->barrier
= aarch64_barrier_options
+ val
;
6404 case AARCH64_OPND_PRFOP
:
6405 val
= parse_pldop (&str
);
6406 /* This is an extension to accept a 0..31 immediate. */
6407 if (val
== PARSE_FAIL
)
6408 po_imm_or_fail (0, 31);
6409 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6412 case AARCH64_OPND_BARRIER_PSB
:
6413 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6414 if (val
== PARSE_FAIL
)
6419 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6422 /* If we get here, this operand was successfully parsed. */
6423 inst
.base
.operands
[i
].present
= 1;
6427 /* The parse routine should already have set the error, but in case
6428 not, set a default one here. */
6430 set_default_error ();
6432 if (! backtrack_pos
)
6433 goto parse_operands_return
;
6436 /* We reach here because this operand is marked as optional, and
6437 either no operand was supplied or the operand was supplied but it
6438 was syntactically incorrect. In the latter case we report an
6439 error. In the former case we perform a few more checks before
6440 dropping through to the code to insert the default operand. */
6442 char *tmp
= backtrack_pos
;
6443 char endchar
= END_OF_INSN
;
6445 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6447 skip_past_char (&tmp
, ',');
6449 if (*tmp
!= endchar
)
6450 /* The user has supplied an operand in the wrong format. */
6451 goto parse_operands_return
;
6453 /* Make sure there is not a comma before the optional operand.
6454 For example the fifth operand of 'sys' is optional:
6456 sys #0,c0,c0,#0, <--- wrong
6457 sys #0,c0,c0,#0 <--- correct. */
6458 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6460 set_fatal_syntax_error
6461 (_("unexpected comma before the omitted optional operand"));
6462 goto parse_operands_return
;
6466 /* Reaching here means we are dealing with an optional operand that is
6467 omitted from the assembly line. */
6468 gas_assert (optional_operand_p (opcode
, i
));
6470 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6472 /* Try again, skipping the optional operand at backtrack_pos. */
6473 str
= backtrack_pos
;
6476 /* Clear any error record after the omitted optional operand has been
6477 successfully handled. */
6481 /* Check if we have parsed all the operands. */
6482 if (*str
!= '\0' && ! error_p ())
6484 /* Set I to the index of the last present operand; this is
6485 for the purpose of diagnostics. */
6486 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6488 set_fatal_syntax_error
6489 (_("unexpected characters following instruction"));
6492 parse_operands_return
:
6496 DEBUG_TRACE ("parsing FAIL: %s - %s",
6497 operand_mismatch_kind_names
[get_error_kind ()],
6498 get_error_message ());
6499 /* Record the operand error properly; this is useful when there
6500 are multiple instruction templates for a mnemonic name, so that
6501 later on, we can select the error that most closely describes
6503 record_operand_error (opcode
, i
, get_error_kind (),
6504 get_error_message ());
6509 DEBUG_TRACE ("parsing SUCCESS");
6514 /* It does some fix-up to provide some programmer friendly feature while
6515 keeping the libopcodes happy, i.e. libopcodes only accepts
6516 the preferred architectural syntax.
6517 Return FALSE if there is any failure; otherwise return TRUE. */
6520 programmer_friendly_fixup (aarch64_instruction
*instr
)
6522 aarch64_inst
*base
= &instr
->base
;
6523 const aarch64_opcode
*opcode
= base
->opcode
;
6524 enum aarch64_op op
= opcode
->op
;
6525 aarch64_opnd_info
*operands
= base
->operands
;
6527 DEBUG_TRACE ("enter");
6529 switch (opcode
->iclass
)
6532 /* TBNZ Xn|Wn, #uimm6, label
6533 Test and Branch Not Zero: conditionally jumps to label if bit number
6534 uimm6 in register Xn is not zero. The bit number implies the width of
6535 the register, which may be written and should be disassembled as Wn if
6536 uimm is less than 32. */
6537 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6539 if (operands
[1].imm
.value
>= 32)
6541 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6545 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6549 /* LDR Wt, label | =value
6550 As a convenience assemblers will typically permit the notation
6551 "=value" in conjunction with the pc-relative literal load instructions
6552 to automatically place an immediate value or symbolic address in a
6553 nearby literal pool and generate a hidden label which references it.
6554 ISREG has been set to 0 in the case of =value. */
6555 if (instr
->gen_lit_pool
6556 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6558 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6559 if (op
== OP_LDRSW_LIT
)
6561 if (instr
->reloc
.exp
.X_op
!= O_constant
6562 && instr
->reloc
.exp
.X_op
!= O_big
6563 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6565 record_operand_error (opcode
, 1,
6566 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6567 _("constant expression expected"));
6570 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6572 record_operand_error (opcode
, 1,
6573 AARCH64_OPDE_OTHER_ERROR
,
6574 _("literal pool insertion failed"));
6582 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6583 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6584 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6585 A programmer-friendly assembler should accept a destination Xd in
6586 place of Wd, however that is not the preferred form for disassembly.
6588 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6589 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6590 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6591 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6596 /* In the 64-bit form, the final register operand is written as Wm
6597 for all but the (possibly omitted) UXTX/LSL and SXTX
6599 As a programmer-friendly assembler, we accept e.g.
6600 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6601 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6602 int idx
= aarch64_operand_index (opcode
->operands
,
6603 AARCH64_OPND_Rm_EXT
);
6604 gas_assert (idx
== 1 || idx
== 2);
6605 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6606 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6607 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6608 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6609 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6610 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6618 DEBUG_TRACE ("exit with SUCCESS");
6622 /* Check for loads and stores that will cause unpredictable behavior. */
6625 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6627 aarch64_inst
*base
= &instr
->base
;
6628 const aarch64_opcode
*opcode
= base
->opcode
;
6629 const aarch64_opnd_info
*opnds
= base
->operands
;
6630 switch (opcode
->iclass
)
6637 /* Loading/storing the base register is unpredictable if writeback. */
6638 if ((aarch64_get_operand_class (opnds
[0].type
)
6639 == AARCH64_OPND_CLASS_INT_REG
)
6640 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6641 && opnds
[1].addr
.base_regno
!= REG_SP
6642 && opnds
[1].addr
.writeback
)
6643 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6646 case ldstnapair_offs
:
6647 case ldstpair_indexed
:
6648 /* Loading/storing the base register is unpredictable if writeback. */
6649 if ((aarch64_get_operand_class (opnds
[0].type
)
6650 == AARCH64_OPND_CLASS_INT_REG
)
6651 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6652 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6653 && opnds
[2].addr
.base_regno
!= REG_SP
6654 && opnds
[2].addr
.writeback
)
6655 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6656 /* Load operations must load different registers. */
6657 if ((opcode
->opcode
& (1 << 22))
6658 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6659 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6666 /* A wrapper function to interface with libopcodes on encoding and
6667 record the error message if there is any.
6669 Return TRUE on success; otherwise return FALSE. */
6672 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6675 aarch64_operand_error error_info
;
6676 error_info
.kind
= AARCH64_OPDE_NIL
;
6677 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
6681 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6682 record_operand_error_info (opcode
, &error_info
);
6687 #ifdef DEBUG_AARCH64
6689 dump_opcode_operands (const aarch64_opcode
*opcode
)
6692 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6694 aarch64_verbose ("\t\t opnd%d: %s", i
,
6695 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6696 ? aarch64_get_operand_name (opcode
->operands
[i
])
6697 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6701 #endif /* DEBUG_AARCH64 */
6703 /* This is the guts of the machine-dependent assembler. STR points to a
6704 machine dependent instruction. This function is supposed to emit
6705 the frags/bytes it assembles to. */
6708 md_assemble (char *str
)
6711 templates
*template;
6712 aarch64_opcode
*opcode
;
6713 aarch64_inst
*inst_base
;
6714 unsigned saved_cond
;
6716 /* Align the previous label if needed. */
6717 if (last_label_seen
!= NULL
)
6719 symbol_set_frag (last_label_seen
, frag_now
);
6720 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6721 S_SET_SEGMENT (last_label_seen
, now_seg
);
6724 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6726 DEBUG_TRACE ("\n\n");
6727 DEBUG_TRACE ("==============================");
6728 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6730 template = opcode_lookup (&p
);
6733 /* It wasn't an instruction, but it might be a register alias of
6734 the form alias .req reg directive. */
6735 if (!create_register_alias (str
, p
))
6736 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6741 skip_whitespace (p
);
6744 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6745 get_mnemonic_name (str
), str
);
6749 init_operand_error_report ();
6751 /* Sections are assumed to start aligned. In executable section, there is no
6752 MAP_DATA symbol pending. So we only align the address during
6753 MAP_DATA --> MAP_INSN transition.
6754 For other sections, this is not guaranteed. */
6755 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6756 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6757 frag_align_code (2, 0);
6759 saved_cond
= inst
.cond
;
6760 reset_aarch64_instruction (&inst
);
6761 inst
.cond
= saved_cond
;
6763 /* Iterate through all opcode entries with the same mnemonic name. */
6766 opcode
= template->opcode
;
6768 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6769 #ifdef DEBUG_AARCH64
6771 dump_opcode_operands (opcode
);
6772 #endif /* DEBUG_AARCH64 */
6774 mapping_state (MAP_INSN
);
6776 inst_base
= &inst
.base
;
6777 inst_base
->opcode
= opcode
;
6779 /* Truly conditionally executed instructions, e.g. b.cond. */
6780 if (opcode
->flags
& F_COND
)
6782 gas_assert (inst
.cond
!= COND_ALWAYS
);
6783 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6784 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6786 else if (inst
.cond
!= COND_ALWAYS
)
6788 /* It shouldn't arrive here, where the assembly looks like a
6789 conditional instruction but the found opcode is unconditional. */
6794 if (parse_operands (p
, opcode
)
6795 && programmer_friendly_fixup (&inst
)
6796 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6798 /* Check that this instruction is supported for this CPU. */
6799 if (!opcode
->avariant
6800 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6802 as_bad (_("selected processor does not support `%s'"), str
);
6806 warn_unpredictable_ldst (&inst
, str
);
6808 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6809 || !inst
.reloc
.need_libopcodes_p
)
6813 /* If there is relocation generated for the instruction,
6814 store the instruction information for the future fix-up. */
6815 struct aarch64_inst
*copy
;
6816 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6817 copy
= XNEW (struct aarch64_inst
);
6818 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6824 template = template->next
;
6825 if (template != NULL
)
6827 reset_aarch64_instruction (&inst
);
6828 inst
.cond
= saved_cond
;
6831 while (template != NULL
);
6833 /* Issue the error messages if any. */
6834 output_operand_error_report (str
);
6837 /* Various frobbings of labels and their addresses. */
6840 aarch64_start_line_hook (void)
6842 last_label_seen
= NULL
;
6846 aarch64_frob_label (symbolS
* sym
)
6848 last_label_seen
= sym
;
6850 dwarf2_emit_label (sym
);
6854 aarch64_data_in_code (void)
6856 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6858 *input_line_pointer
= '/';
6859 input_line_pointer
+= 5;
6860 *input_line_pointer
= 0;
6868 aarch64_canonicalize_symbol_name (char *name
)
6872 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6873 *(name
+ len
- 5) = 0;
6878 /* Table of all register names defined by default. The user can
6879 define additional names with .req. Note that all register names
6880 should appear in both upper and lowercase variants. Some registers
6881 also have mixed-case names. */
6883 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6884 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
6885 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6886 #define REGSET16(p,t) \
6887 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6888 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6889 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6890 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6891 #define REGSET31(p,t) \
6893 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6894 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6895 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6896 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6897 #define REGSET(p,t) \
6898 REGSET31(p,t), REGNUM(p,31,t)
6900 /* These go into aarch64_reg_hsh hash-table. */
6901 static const reg_entry reg_names
[] = {
6902 /* Integer registers. */
6903 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6904 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6906 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
6907 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
6908 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
6909 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
6910 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6911 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6913 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6914 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6916 /* Floating-point single precision registers. */
6917 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6919 /* Floating-point double precision registers. */
6920 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6922 /* Floating-point half precision registers. */
6923 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6925 /* Floating-point byte precision registers. */
6926 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6928 /* Floating-point quad precision registers. */
6929 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6931 /* FP/SIMD registers. */
6932 REGSET (v
, VN
), REGSET (V
, VN
),
6934 /* SVE vector registers. */
6935 REGSET (z
, ZN
), REGSET (Z
, ZN
),
6937 /* SVE predicate registers. */
6938 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
6956 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6957 static const asm_nzcv nzcv_names
[] = {
6958 {"nzcv", B (n
, z
, c
, v
)},
6959 {"nzcV", B (n
, z
, c
, V
)},
6960 {"nzCv", B (n
, z
, C
, v
)},
6961 {"nzCV", B (n
, z
, C
, V
)},
6962 {"nZcv", B (n
, Z
, c
, v
)},
6963 {"nZcV", B (n
, Z
, c
, V
)},
6964 {"nZCv", B (n
, Z
, C
, v
)},
6965 {"nZCV", B (n
, Z
, C
, V
)},
6966 {"Nzcv", B (N
, z
, c
, v
)},
6967 {"NzcV", B (N
, z
, c
, V
)},
6968 {"NzCv", B (N
, z
, C
, v
)},
6969 {"NzCV", B (N
, z
, C
, V
)},
6970 {"NZcv", B (N
, Z
, c
, v
)},
6971 {"NZcV", B (N
, Z
, c
, V
)},
6972 {"NZCv", B (N
, Z
, C
, v
)},
6973 {"NZCV", B (N
, Z
, C
, V
)}
6986 /* MD interface: bits in the object file. */
6988 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6989 for use in the a.out file, and stores them in the array pointed to by buf.
6990 This knows about the endian-ness of the target machine and does
6991 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6992 2 (short) and 4 (long) Floating numbers are put out as a series of
6993 LITTLENUMS (shorts, here at least). */
6996 md_number_to_chars (char *buf
, valueT val
, int n
)
6998 if (target_big_endian
)
6999 number_to_chars_bigendian (buf
, val
, n
);
7001 number_to_chars_littleendian (buf
, val
, n
);
7004 /* MD interface: Sections. */
7006 /* Estimate the size of a frag before relaxing. Assume everything fits in
7010 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7016 /* Round up a section size to the appropriate boundary. */
7019 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7024 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7025 of an rs_align_code fragment.
7027 Here we fill the frag with the appropriate info for padding the
7028 output stream. The resulting frag will consist of a fixed (fr_fix)
7029 and of a repeating (fr_var) part.
7031 The fixed content is always emitted before the repeating content and
7032 these two parts are used as follows in constructing the output:
7033 - the fixed part will be used to align to a valid instruction word
7034 boundary, in case that we start at a misaligned address; as no
7035 executable instruction can live at the misaligned location, we
7036 simply fill with zeros;
7037 - the variable part will be used to cover the remaining padding and
7038 we fill using the AArch64 NOP instruction.
7040 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7041 enough storage space for up to 3 bytes for padding the back to a valid
7042 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7045 aarch64_handle_align (fragS
* fragP
)
7047 /* NOP = d503201f */
7048 /* AArch64 instructions are always little-endian. */
7049 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7051 int bytes
, fix
, noop_size
;
7054 if (fragP
->fr_type
!= rs_align_code
)
7057 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7058 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7061 gas_assert (fragP
->tc_frag_data
.recorded
);
7064 noop_size
= sizeof (aarch64_noop
);
7066 fix
= bytes
& (noop_size
- 1);
7070 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7074 fragP
->fr_fix
+= fix
;
7078 memcpy (p
, aarch64_noop
, noop_size
);
7079 fragP
->fr_var
= noop_size
;
7082 /* Perform target specific initialisation of a frag.
7083 Note - despite the name this initialisation is not done when the frag
7084 is created, but only when its type is assigned. A frag can be created
7085 and used a long time before its type is set, so beware of assuming that
7086 this initialisation is performed first. */
7090 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7091 int max_chars ATTRIBUTE_UNUSED
)
7095 #else /* OBJ_ELF is defined. */
7097 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7099 /* Record a mapping symbol for alignment frags. We will delete this
7100 later if the alignment ends up empty. */
7101 if (!fragP
->tc_frag_data
.recorded
)
7102 fragP
->tc_frag_data
.recorded
= 1;
7104 /* PR 21809: Do not set a mapping state for debug sections
7105 - it just confuses other tools. */
7106 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
7109 switch (fragP
->fr_type
)
7113 mapping_state_2 (MAP_DATA
, max_chars
);
7116 /* PR 20364: We can get alignment frags in code sections,
7117 so do not just assume that we should use the MAP_DATA state. */
7118 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7121 mapping_state_2 (MAP_INSN
, max_chars
);
7128 /* Initialize the DWARF-2 unwind information for this procedure. */
7131 tc_aarch64_frame_initial_instructions (void)
7133 cfi_add_CFA_def_cfa (REG_SP
, 0);
7135 #endif /* OBJ_ELF */
7137 /* Convert REGNAME to a DWARF-2 register number. */
7140 tc_aarch64_regname_to_dw2regnum (char *regname
)
7142 const reg_entry
*reg
= parse_reg (®name
);
7148 case REG_TYPE_SP_32
:
7149 case REG_TYPE_SP_64
:
7159 return reg
->number
+ 64;
7167 /* Implement DWARF2_ADDR_SIZE. */
7170 aarch64_dwarf2_addr_size (void)
7172 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7176 return bfd_arch_bits_per_address (stdoutput
) / 8;
7179 /* MD interface: Symbol and relocation handling. */
7181 /* Return the address within the segment that a PC-relative fixup is
7182 relative to. For AArch64 PC-relative fixups applied to instructions
7183 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7186 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7188 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7190 /* If this is pc-relative and we are going to emit a relocation
7191 then we just want to put out any pipeline compensation that the linker
7192 will need. Otherwise we want to use the calculated base. */
7194 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7195 || aarch64_force_relocation (fixP
)))
7198 /* AArch64 should be consistent for all pc-relative relocations. */
7199 return base
+ AARCH64_PCREL_OFFSET
;
7202 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7203 Otherwise we have no need to default values of symbols. */
7206 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7209 if (name
[0] == '_' && name
[1] == 'G'
7210 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7214 if (symbol_find (name
))
7215 as_bad (_("GOT already in the symbol table"));
7217 GOT_symbol
= symbol_new (name
, undefined_section
,
7218 (valueT
) 0, &zero_address_frag
);
7228 /* Return non-zero if the indicated VALUE has overflowed the maximum
7229 range expressible by a unsigned number with the indicated number of
7233 unsigned_overflow (valueT value
, unsigned bits
)
7236 if (bits
>= sizeof (valueT
) * 8)
7238 lim
= (valueT
) 1 << bits
;
7239 return (value
>= lim
);
7243 /* Return non-zero if the indicated VALUE has overflowed the maximum
7244 range expressible by an signed number with the indicated number of
7248 signed_overflow (offsetT value
, unsigned bits
)
7251 if (bits
>= sizeof (offsetT
) * 8)
7253 lim
= (offsetT
) 1 << (bits
- 1);
7254 return (value
< -lim
|| value
>= lim
);
7257 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7258 unsigned immediate offset load/store instruction, try to encode it as
7259 an unscaled, 9-bit, signed immediate offset load/store instruction.
7260 Return TRUE if it is successful; otherwise return FALSE.
7262 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7263 in response to the standard LDR/STR mnemonics when the immediate offset is
7264 unambiguous, i.e. when it is negative or unaligned. */
7267 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7270 enum aarch64_op new_op
;
7271 const aarch64_opcode
*new_opcode
;
7273 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7275 switch (instr
->opcode
->op
)
7277 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7278 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7279 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7280 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7281 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7282 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7283 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7284 case OP_STR_POS
: new_op
= OP_STUR
; break;
7285 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7286 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7287 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7288 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7289 default: new_op
= OP_NIL
; break;
7292 if (new_op
== OP_NIL
)
7295 new_opcode
= aarch64_get_opcode (new_op
);
7296 gas_assert (new_opcode
!= NULL
);
7298 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7299 instr
->opcode
->op
, new_opcode
->op
);
7301 aarch64_replace_opcode (instr
, new_opcode
);
7303 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7304 qualifier matching may fail because the out-of-date qualifier will
7305 prevent the operand being updated with a new and correct qualifier. */
7306 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7307 AARCH64_OPND_ADDR_SIMM9
);
7308 gas_assert (idx
== 1);
7309 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7311 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7313 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
7319 /* Called by fix_insn to fix a MOV immediate alias instruction.
7321 Operand for a generic move immediate instruction, which is an alias
7322 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7323 a 32-bit/64-bit immediate value into general register. An assembler error
7324 shall result if the immediate cannot be created by a single one of these
7325 instructions. If there is a choice, then to ensure reversability an
7326 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7329 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7331 const aarch64_opcode
*opcode
;
7333 /* Need to check if the destination is SP/ZR. The check has to be done
7334 before any aarch64_replace_opcode. */
7335 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7336 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7338 instr
->operands
[1].imm
.value
= value
;
7339 instr
->operands
[1].skip
= 0;
7343 /* Try the MOVZ alias. */
7344 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7345 aarch64_replace_opcode (instr
, opcode
);
7346 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7347 &instr
->value
, NULL
, NULL
))
7349 put_aarch64_insn (buf
, instr
->value
);
7352 /* Try the MOVK alias. */
7353 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7354 aarch64_replace_opcode (instr
, opcode
);
7355 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7356 &instr
->value
, NULL
, NULL
))
7358 put_aarch64_insn (buf
, instr
->value
);
7363 if (try_mov_bitmask_p
)
7365 /* Try the ORR alias. */
7366 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7367 aarch64_replace_opcode (instr
, opcode
);
7368 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7369 &instr
->value
, NULL
, NULL
))
7371 put_aarch64_insn (buf
, instr
->value
);
7376 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7377 _("immediate cannot be moved by a single instruction"));
7380 /* An instruction operand which is immediate related may have symbol used
7381 in the assembly, e.g.
7384 .set u32, 0x00ffff00
7386 At the time when the assembly instruction is parsed, a referenced symbol,
7387 like 'u32' in the above example may not have been seen; a fixS is created
7388 in such a case and is handled here after symbols have been resolved.
7389 Instruction is fixed up with VALUE using the information in *FIXP plus
7390 extra information in FLAGS.
7392 This function is called by md_apply_fix to fix up instructions that need
7393 a fix-up described above but does not involve any linker-time relocation. */
7396 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7400 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7401 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7402 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7406 /* Now the instruction is about to be fixed-up, so the operand that
7407 was previously marked as 'ignored' needs to be unmarked in order
7408 to get the encoding done properly. */
7409 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7410 new_inst
->operands
[idx
].skip
= 0;
7413 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7417 case AARCH64_OPND_EXCEPTION
:
7418 if (unsigned_overflow (value
, 16))
7419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7420 _("immediate out of range"));
7421 insn
= get_aarch64_insn (buf
);
7422 insn
|= encode_svc_imm (value
);
7423 put_aarch64_insn (buf
, insn
);
7426 case AARCH64_OPND_AIMM
:
7427 /* ADD or SUB with immediate.
7428 NOTE this assumes we come here with a add/sub shifted reg encoding
7429 3 322|2222|2 2 2 21111 111111
7430 1 098|7654|3 2 1 09876 543210 98765 43210
7431 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7432 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7433 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7434 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7436 3 322|2222|2 2 221111111111
7437 1 098|7654|3 2 109876543210 98765 43210
7438 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7439 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7440 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7441 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7442 Fields sf Rn Rd are already set. */
7443 insn
= get_aarch64_insn (buf
);
7447 insn
= reencode_addsub_switch_add_sub (insn
);
7451 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7452 && unsigned_overflow (value
, 12))
7454 /* Try to shift the value by 12 to make it fit. */
7455 if (((value
>> 12) << 12) == value
7456 && ! unsigned_overflow (value
, 12 + 12))
7459 insn
|= encode_addsub_imm_shift_amount (1);
7463 if (unsigned_overflow (value
, 12))
7464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7465 _("immediate out of range"));
7467 insn
|= encode_addsub_imm (value
);
7469 put_aarch64_insn (buf
, insn
);
7472 case AARCH64_OPND_SIMD_IMM
:
7473 case AARCH64_OPND_SIMD_IMM_SFT
:
7474 case AARCH64_OPND_LIMM
:
7475 /* Bit mask immediate. */
7476 gas_assert (new_inst
!= NULL
);
7477 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7478 new_inst
->operands
[idx
].imm
.value
= value
;
7479 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7480 &new_inst
->value
, NULL
, NULL
))
7481 put_aarch64_insn (buf
, new_inst
->value
);
7483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7484 _("invalid immediate"));
7487 case AARCH64_OPND_HALF
:
7488 /* 16-bit unsigned immediate. */
7489 if (unsigned_overflow (value
, 16))
7490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7491 _("immediate out of range"));
7492 insn
= get_aarch64_insn (buf
);
7493 insn
|= encode_movw_imm (value
& 0xffff);
7494 put_aarch64_insn (buf
, insn
);
7497 case AARCH64_OPND_IMM_MOV
:
7498 /* Operand for a generic move immediate instruction, which is
7499 an alias instruction that generates a single MOVZ, MOVN or ORR
7500 instruction to loads a 32-bit/64-bit immediate value into general
7501 register. An assembler error shall result if the immediate cannot be
7502 created by a single one of these instructions. If there is a choice,
7503 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7504 and MOVZ or MOVN to ORR. */
7505 gas_assert (new_inst
!= NULL
);
7506 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7509 case AARCH64_OPND_ADDR_SIMM7
:
7510 case AARCH64_OPND_ADDR_SIMM9
:
7511 case AARCH64_OPND_ADDR_SIMM9_2
:
7512 case AARCH64_OPND_ADDR_SIMM10
:
7513 case AARCH64_OPND_ADDR_UIMM12
:
7514 /* Immediate offset in an address. */
7515 insn
= get_aarch64_insn (buf
);
7517 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7518 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7519 || new_inst
->opcode
->operands
[2] == opnd
);
7521 /* Get the index of the address operand. */
7522 if (new_inst
->opcode
->operands
[1] == opnd
)
7523 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7526 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7529 /* Update the resolved offset value. */
7530 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7532 /* Encode/fix-up. */
7533 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7534 &new_inst
->value
, NULL
, NULL
))
7536 put_aarch64_insn (buf
, new_inst
->value
);
7539 else if (new_inst
->opcode
->iclass
== ldst_pos
7540 && try_to_encode_as_unscaled_ldst (new_inst
))
7542 put_aarch64_insn (buf
, new_inst
->value
);
7546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7547 _("immediate offset out of range"));
7552 as_fatal (_("unhandled operand code %d"), opnd
);
7556 /* Apply a fixup (fixP) to segment data, once it has been determined
7557 by our caller that we have all the info we need to fix it up.
7559 Parameter valP is the pointer to the value of the bits. */
7562 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7564 offsetT value
= *valP
;
7566 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7568 unsigned flags
= fixP
->fx_addnumber
;
7570 DEBUG_TRACE ("\n\n");
7571 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7572 DEBUG_TRACE ("Enter md_apply_fix");
7574 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7576 /* Note whether this will delete the relocation. */
7578 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7581 /* Process the relocations. */
7582 switch (fixP
->fx_r_type
)
7584 case BFD_RELOC_NONE
:
7585 /* This will need to go in the object file. */
7590 case BFD_RELOC_8_PCREL
:
7591 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7592 md_number_to_chars (buf
, value
, 1);
7596 case BFD_RELOC_16_PCREL
:
7597 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7598 md_number_to_chars (buf
, value
, 2);
7602 case BFD_RELOC_32_PCREL
:
7603 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7604 md_number_to_chars (buf
, value
, 4);
7608 case BFD_RELOC_64_PCREL
:
7609 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7610 md_number_to_chars (buf
, value
, 8);
7613 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7614 /* We claim that these fixups have been processed here, even if
7615 in fact we generate an error because we do not have a reloc
7616 for them, so tc_gen_reloc() will reject them. */
7618 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7620 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7621 _("undefined symbol %s used as an immediate value"),
7622 S_GET_NAME (fixP
->fx_addsy
));
7623 goto apply_fix_return
;
7625 fix_insn (fixP
, flags
, value
);
7628 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7629 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7633 _("pc-relative load offset not word aligned"));
7634 if (signed_overflow (value
, 21))
7635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7636 _("pc-relative load offset out of range"));
7637 insn
= get_aarch64_insn (buf
);
7638 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7639 put_aarch64_insn (buf
, insn
);
7643 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7644 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7646 if (signed_overflow (value
, 21))
7647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7648 _("pc-relative address offset out of range"));
7649 insn
= get_aarch64_insn (buf
);
7650 insn
|= encode_adr_imm (value
);
7651 put_aarch64_insn (buf
, insn
);
7655 case BFD_RELOC_AARCH64_BRANCH19
:
7656 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7660 _("conditional branch target not word aligned"));
7661 if (signed_overflow (value
, 21))
7662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7663 _("conditional branch out of range"));
7664 insn
= get_aarch64_insn (buf
);
7665 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7666 put_aarch64_insn (buf
, insn
);
7670 case BFD_RELOC_AARCH64_TSTBR14
:
7671 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7675 _("conditional branch target not word aligned"));
7676 if (signed_overflow (value
, 16))
7677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7678 _("conditional branch out of range"));
7679 insn
= get_aarch64_insn (buf
);
7680 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7681 put_aarch64_insn (buf
, insn
);
7685 case BFD_RELOC_AARCH64_CALL26
:
7686 case BFD_RELOC_AARCH64_JUMP26
:
7687 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7691 _("branch target not word aligned"));
7692 if (signed_overflow (value
, 28))
7693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7694 _("branch out of range"));
7695 insn
= get_aarch64_insn (buf
);
7696 insn
|= encode_branch_ofs_26 (value
>> 2);
7697 put_aarch64_insn (buf
, insn
);
7701 case BFD_RELOC_AARCH64_MOVW_G0
:
7702 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7703 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7704 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7705 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7706 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7709 case BFD_RELOC_AARCH64_MOVW_G1
:
7710 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7711 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7712 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7713 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7714 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7717 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7719 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7720 /* Should always be exported to object file, see
7721 aarch64_force_relocation(). */
7722 gas_assert (!fixP
->fx_done
);
7723 gas_assert (seg
->use_rela_p
);
7725 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7727 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7728 /* Should always be exported to object file, see
7729 aarch64_force_relocation(). */
7730 gas_assert (!fixP
->fx_done
);
7731 gas_assert (seg
->use_rela_p
);
7733 case BFD_RELOC_AARCH64_MOVW_G2
:
7734 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7735 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7736 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7737 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
7740 case BFD_RELOC_AARCH64_MOVW_G3
:
7741 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
7744 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7746 insn
= get_aarch64_insn (buf
);
7750 /* REL signed addend must fit in 16 bits */
7751 if (signed_overflow (value
, 16))
7752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7753 _("offset out of range"));
7757 /* Check for overflow and scale. */
7758 switch (fixP
->fx_r_type
)
7760 case BFD_RELOC_AARCH64_MOVW_G0
:
7761 case BFD_RELOC_AARCH64_MOVW_G1
:
7762 case BFD_RELOC_AARCH64_MOVW_G2
:
7763 case BFD_RELOC_AARCH64_MOVW_G3
:
7764 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7765 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7766 if (unsigned_overflow (value
, scale
+ 16))
7767 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7768 _("unsigned value out of range"));
7770 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7771 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7772 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7773 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7774 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7775 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7776 /* NOTE: We can only come here with movz or movn. */
7777 if (signed_overflow (value
, scale
+ 16))
7778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7779 _("signed value out of range"));
7782 /* Force use of MOVN. */
7784 insn
= reencode_movzn_to_movn (insn
);
7788 /* Force use of MOVZ. */
7789 insn
= reencode_movzn_to_movz (insn
);
7793 /* Unchecked relocations. */
7799 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7800 insn
|= encode_movw_imm (value
& 0xffff);
7802 put_aarch64_insn (buf
, insn
);
7806 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7807 fixP
->fx_r_type
= (ilp32_p
7808 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7809 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7810 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7811 /* Should always be exported to object file, see
7812 aarch64_force_relocation(). */
7813 gas_assert (!fixP
->fx_done
);
7814 gas_assert (seg
->use_rela_p
);
7817 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7818 fixP
->fx_r_type
= (ilp32_p
7819 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7820 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
7821 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7822 /* Should always be exported to object file, see
7823 aarch64_force_relocation(). */
7824 gas_assert (!fixP
->fx_done
);
7825 gas_assert (seg
->use_rela_p
);
7828 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
7829 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7830 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7831 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7832 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
7833 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7834 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7835 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7836 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7837 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7838 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7839 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7840 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7841 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7842 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7843 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7844 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7845 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7846 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7847 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7848 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7849 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7850 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7851 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7852 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7853 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7854 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7855 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7856 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7857 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7858 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7859 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7860 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7861 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7862 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7863 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7864 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7865 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7866 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7867 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7868 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7869 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7870 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7871 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7872 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7873 /* Should always be exported to object file, see
7874 aarch64_force_relocation(). */
7875 gas_assert (!fixP
->fx_done
);
7876 gas_assert (seg
->use_rela_p
);
7879 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7880 /* Should always be exported to object file, see
7881 aarch64_force_relocation(). */
7882 fixP
->fx_r_type
= (ilp32_p
7883 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7884 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7885 gas_assert (!fixP
->fx_done
);
7886 gas_assert (seg
->use_rela_p
);
7889 case BFD_RELOC_AARCH64_ADD_LO12
:
7890 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7891 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7892 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7893 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7894 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7895 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7896 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7897 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7898 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7899 case BFD_RELOC_AARCH64_LDST128_LO12
:
7900 case BFD_RELOC_AARCH64_LDST16_LO12
:
7901 case BFD_RELOC_AARCH64_LDST32_LO12
:
7902 case BFD_RELOC_AARCH64_LDST64_LO12
:
7903 case BFD_RELOC_AARCH64_LDST8_LO12
:
7904 /* Should always be exported to object file, see
7905 aarch64_force_relocation(). */
7906 gas_assert (!fixP
->fx_done
);
7907 gas_assert (seg
->use_rela_p
);
7910 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7911 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7912 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7915 case BFD_RELOC_UNUSED
:
7916 /* An error will already have been reported. */
7920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7921 _("unexpected %s fixup"),
7922 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7927 /* Free the allocated the struct aarch64_inst.
7928 N.B. currently there are very limited number of fix-up types actually use
7929 this field, so the impact on the performance should be minimal . */
7930 if (fixP
->tc_fix_data
.inst
!= NULL
)
7931 free (fixP
->tc_fix_data
.inst
);
7936 /* Translate internal representation of relocation info to BFD target
7940 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7943 bfd_reloc_code_real_type code
;
7945 reloc
= XNEW (arelent
);
7947 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7948 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7949 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7953 if (section
->use_rela_p
)
7954 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7956 fixp
->fx_offset
= reloc
->address
;
7958 reloc
->addend
= fixp
->fx_offset
;
7960 code
= fixp
->fx_r_type
;
7965 code
= BFD_RELOC_16_PCREL
;
7970 code
= BFD_RELOC_32_PCREL
;
7975 code
= BFD_RELOC_64_PCREL
;
7982 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7983 if (reloc
->howto
== NULL
)
7985 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7987 ("cannot represent %s relocation in this object file format"),
7988 bfd_get_reloc_code_name (code
));
7995 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7998 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8000 bfd_reloc_code_real_type type
;
8004 FIXME: @@ Should look at CPU word size. */
8011 type
= BFD_RELOC_16
;
8014 type
= BFD_RELOC_32
;
8017 type
= BFD_RELOC_64
;
8020 as_bad (_("cannot do %u-byte relocation"), size
);
8021 type
= BFD_RELOC_UNUSED
;
8025 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8029 aarch64_force_relocation (struct fix
*fixp
)
8031 switch (fixp
->fx_r_type
)
8033 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8034 /* Perform these "immediate" internal relocations
8035 even if the symbol is extern or weak. */
8038 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8039 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8040 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8041 /* Pseudo relocs that need to be fixed up according to
8045 case BFD_RELOC_AARCH64_ADD_LO12
:
8046 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8047 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8048 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8049 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8050 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8051 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8052 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8053 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8054 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8055 case BFD_RELOC_AARCH64_LDST128_LO12
:
8056 case BFD_RELOC_AARCH64_LDST16_LO12
:
8057 case BFD_RELOC_AARCH64_LDST32_LO12
:
8058 case BFD_RELOC_AARCH64_LDST64_LO12
:
8059 case BFD_RELOC_AARCH64_LDST8_LO12
:
8060 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8061 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8062 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8063 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8064 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8065 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8066 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8067 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8068 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8069 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8070 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8071 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8072 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8073 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8074 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8075 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8076 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8077 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8078 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8079 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8080 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8081 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8082 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8083 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8084 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8085 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8086 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8087 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8088 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8089 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8090 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8091 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8092 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8093 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8094 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8095 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8096 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8097 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8098 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8099 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8100 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8101 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8102 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8103 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8104 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8105 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8106 /* Always leave these relocations for the linker. */
8113 return generic_force_reloc (fixp
);
8118 /* Implement md_after_parse_args. This is the earliest time we need to decide
8119 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8122 aarch64_after_parse_args (void)
8124 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8127 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8128 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8129 aarch64_abi
= AARCH64_ABI_ILP32
;
8131 aarch64_abi
= AARCH64_ABI_LP64
;
8135 elf64_aarch64_target_format (void)
8137 if (strcmp (TARGET_OS
, "cloudabi") == 0)
8139 /* FIXME: What to do for ilp32_p ? */
8140 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
8142 if (target_big_endian
)
8143 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8145 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8149 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8151 elf_frob_symbol (symp
, puntp
);
8155 /* MD interface: Finalization. */
8157 /* A good place to do this, although this was probably not intended
8158 for this kind of use. We need to dump the literal pool before
8159 references are made to a null symbol pointer. */
8162 aarch64_cleanup (void)
8166 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8168 /* Put it at the end of the relevant section. */
8169 subseg_set (pool
->section
, pool
->sub_section
);
8175 /* Remove any excess mapping symbols generated for alignment frags in
8176 SEC. We may have created a mapping symbol before a zero byte
8177 alignment; remove it if there's a mapping symbol after the
8180 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8181 void *dummy ATTRIBUTE_UNUSED
)
8183 segment_info_type
*seginfo
= seg_info (sec
);
8186 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8189 for (fragp
= seginfo
->frchainP
->frch_root
;
8190 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8192 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8193 fragS
*next
= fragp
->fr_next
;
8195 /* Variable-sized frags have been converted to fixed size by
8196 this point. But if this was variable-sized to start with,
8197 there will be a fixed-size frag after it. So don't handle
8199 if (sym
== NULL
|| next
== NULL
)
8202 if (S_GET_VALUE (sym
) < next
->fr_address
)
8203 /* Not at the end of this frag. */
8205 know (S_GET_VALUE (sym
) == next
->fr_address
);
8209 if (next
->tc_frag_data
.first_map
!= NULL
)
8211 /* Next frag starts with a mapping symbol. Discard this
8213 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8217 if (next
->fr_next
== NULL
)
8219 /* This mapping symbol is at the end of the section. Discard
8221 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8222 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8226 /* As long as we have empty frags without any mapping symbols,
8228 /* If the next frag is non-empty and does not start with a
8229 mapping symbol, then this mapping symbol is required. */
8230 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8233 next
= next
->fr_next
;
8235 while (next
!= NULL
);
8240 /* Adjust the symbol table. */
8243 aarch64_adjust_symtab (void)
8246 /* Remove any overlapping mapping symbols generated by alignment frags. */
8247 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8248 /* Now do generic ELF adjustments. */
8249 elf_adjust_symtab ();
8254 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8256 const char *hash_err
;
8258 hash_err
= hash_insert (table
, key
, value
);
8260 printf ("Internal Error: Can't hash %s\n", key
);
8264 fill_instruction_hash_table (void)
8266 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8268 while (opcode
->name
!= NULL
)
8270 templates
*templ
, *new_templ
;
8271 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8273 new_templ
= XNEW (templates
);
8274 new_templ
->opcode
= opcode
;
8275 new_templ
->next
= NULL
;
8278 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8281 new_templ
->next
= templ
->next
;
8282 templ
->next
= new_templ
;
8289 convert_to_upper (char *dst
, const char *src
, size_t num
)
8292 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8293 *dst
= TOUPPER (*src
);
8297 /* Assume STR point to a lower-case string, allocate, convert and return
8298 the corresponding upper-case string. */
8299 static inline const char*
8300 get_upper_str (const char *str
)
8303 size_t len
= strlen (str
);
8304 ret
= XNEWVEC (char, len
+ 1);
8305 convert_to_upper (ret
, str
, len
);
8309 /* MD interface: Initialization. */
8317 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8318 || (aarch64_cond_hsh
= hash_new ()) == NULL
8319 || (aarch64_shift_hsh
= hash_new ()) == NULL
8320 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8321 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8322 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8323 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8324 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8325 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8326 || (aarch64_reg_hsh
= hash_new ()) == NULL
8327 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8328 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8329 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8330 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8331 as_fatal (_("virtual memory exhausted"));
8333 fill_instruction_hash_table ();
8335 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8336 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8337 (void *) (aarch64_sys_regs
+ i
));
8339 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8340 checked_hash_insert (aarch64_pstatefield_hsh
,
8341 aarch64_pstatefields
[i
].name
,
8342 (void *) (aarch64_pstatefields
+ i
));
8344 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8345 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8346 aarch64_sys_regs_ic
[i
].name
,
8347 (void *) (aarch64_sys_regs_ic
+ i
));
8349 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8350 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8351 aarch64_sys_regs_dc
[i
].name
,
8352 (void *) (aarch64_sys_regs_dc
+ i
));
8354 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8355 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8356 aarch64_sys_regs_at
[i
].name
,
8357 (void *) (aarch64_sys_regs_at
+ i
));
8359 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8360 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8361 aarch64_sys_regs_tlbi
[i
].name
,
8362 (void *) (aarch64_sys_regs_tlbi
+ i
));
8364 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8365 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8366 (void *) (reg_names
+ i
));
8368 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8369 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8370 (void *) (nzcv_names
+ i
));
8372 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8374 const char *name
= aarch64_operand_modifiers
[i
].name
;
8375 checked_hash_insert (aarch64_shift_hsh
, name
,
8376 (void *) (aarch64_operand_modifiers
+ i
));
8377 /* Also hash the name in the upper case. */
8378 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8379 (void *) (aarch64_operand_modifiers
+ i
));
8382 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8385 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8386 the same condition code. */
8387 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8389 const char *name
= aarch64_conds
[i
].names
[j
];
8392 checked_hash_insert (aarch64_cond_hsh
, name
,
8393 (void *) (aarch64_conds
+ i
));
8394 /* Also hash the name in the upper case. */
8395 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8396 (void *) (aarch64_conds
+ i
));
8400 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8402 const char *name
= aarch64_barrier_options
[i
].name
;
8403 /* Skip xx00 - the unallocated values of option. */
8406 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8407 (void *) (aarch64_barrier_options
+ i
));
8408 /* Also hash the name in the upper case. */
8409 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8410 (void *) (aarch64_barrier_options
+ i
));
8413 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8415 const char* name
= aarch64_prfops
[i
].name
;
8416 /* Skip the unallocated hint encodings. */
8419 checked_hash_insert (aarch64_pldop_hsh
, name
,
8420 (void *) (aarch64_prfops
+ i
));
8421 /* Also hash the name in the upper case. */
8422 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8423 (void *) (aarch64_prfops
+ i
));
8426 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8428 const char* name
= aarch64_hint_options
[i
].name
;
8430 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8431 (void *) (aarch64_hint_options
+ i
));
8432 /* Also hash the name in the upper case. */
8433 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8434 (void *) (aarch64_hint_options
+ i
));
8437 /* Set the cpu variant based on the command-line options. */
8439 mcpu_cpu_opt
= march_cpu_opt
;
8442 mcpu_cpu_opt
= &cpu_default
;
8444 cpu_variant
= *mcpu_cpu_opt
;
8446 /* Record the CPU type. */
8447 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8449 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8452 /* Command line processing. */
8454 const char *md_shortopts
= "m:";
8456 #ifdef AARCH64_BI_ENDIAN
8457 #define OPTION_EB (OPTION_MD_BASE + 0)
8458 #define OPTION_EL (OPTION_MD_BASE + 1)
8460 #if TARGET_BYTES_BIG_ENDIAN
8461 #define OPTION_EB (OPTION_MD_BASE + 0)
8463 #define OPTION_EL (OPTION_MD_BASE + 1)
8467 struct option md_longopts
[] = {
8469 {"EB", no_argument
, NULL
, OPTION_EB
},
8472 {"EL", no_argument
, NULL
, OPTION_EL
},
8474 {NULL
, no_argument
, NULL
, 0}
8477 size_t md_longopts_size
= sizeof (md_longopts
);
8479 struct aarch64_option_table
8481 const char *option
; /* Option name to match. */
8482 const char *help
; /* Help information. */
8483 int *var
; /* Variable to change. */
8484 int value
; /* What to change it to. */
8485 char *deprecated
; /* If non-null, print this message. */
8488 static struct aarch64_option_table aarch64_opts
[] = {
8489 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8490 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8492 #ifdef DEBUG_AARCH64
8493 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8494 #endif /* DEBUG_AARCH64 */
8495 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8497 {"mno-verbose-error", N_("do not output verbose error messages"),
8498 &verbose_error_p
, 0, NULL
},
8499 {NULL
, NULL
, NULL
, 0, NULL
}
8502 struct aarch64_cpu_option_table
8505 const aarch64_feature_set value
;
8506 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8508 const char *canonical_name
;
8511 /* This list should, at a minimum, contain all the cpu names
8512 recognized by GCC. */
8513 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8514 {"all", AARCH64_ANY
, NULL
},
8515 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8516 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8517 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8518 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8519 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8520 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8521 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8522 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8523 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8524 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8525 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8526 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8528 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8529 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8531 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8532 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8533 "Samsung Exynos M1"},
8534 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8535 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8536 | AARCH64_FEATURE_RDMA
),
8538 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8539 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8540 | AARCH64_FEATURE_RDMA
),
8541 "Qualcomm QDF24XX"},
8542 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_3
,
8543 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8544 "Qualcomm Saphira"},
8545 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8546 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8548 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8549 AARCH64_FEATURE_CRYPTO
),
8551 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8552 in earlier releases and is superseded by 'xgene1' in all
8554 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8555 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8556 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8557 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8558 {"generic", AARCH64_ARCH_V8
, NULL
},
8560 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8563 struct aarch64_arch_option_table
8566 const aarch64_feature_set value
;
8569 /* This list should, at a minimum, contain all the architecture names
8570 recognized by GCC. */
8571 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8572 {"all", AARCH64_ANY
},
8573 {"armv8-a", AARCH64_ARCH_V8
},
8574 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8575 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8576 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8577 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8578 {NULL
, AARCH64_ARCH_NONE
}
8581 /* ISA extensions. */
8582 struct aarch64_option_cpu_value_table
8585 const aarch64_feature_set value
;
8586 const aarch64_feature_set require
; /* Feature dependencies. */
8589 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8590 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8592 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8593 | AARCH64_FEATURE_AES
8594 | AARCH64_FEATURE_SHA2
, 0),
8595 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8596 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8598 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8600 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8601 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8602 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8604 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8606 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8608 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8609 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8610 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8611 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8612 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8613 AARCH64_FEATURE (AARCH64_FEATURE_FP
8614 | AARCH64_FEATURE_F16
, 0)},
8615 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8617 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8618 AARCH64_FEATURE (AARCH64_FEATURE_F16
8619 | AARCH64_FEATURE_SIMD
8620 | AARCH64_FEATURE_COMPNUM
, 0)},
8621 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8622 AARCH64_FEATURE (AARCH64_FEATURE_F16
8623 | AARCH64_FEATURE_SIMD
, 0)},
8624 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8626 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8628 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8630 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8632 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8634 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8635 | AARCH64_FEATURE_SHA3
, 0),
8637 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8640 struct aarch64_long_option_table
8642 const char *option
; /* Substring to match. */
8643 const char *help
; /* Help information. */
8644 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8645 char *deprecated
; /* If non-null, print this message. */
8648 /* Transitive closure of features depending on set. */
8649 static aarch64_feature_set
8650 aarch64_feature_disable_set (aarch64_feature_set set
)
8652 const struct aarch64_option_cpu_value_table
*opt
;
8653 aarch64_feature_set prev
= 0;
8655 while (prev
!= set
) {
8657 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8658 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8659 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8664 /* Transitive closure of dependencies of set. */
8665 static aarch64_feature_set
8666 aarch64_feature_enable_set (aarch64_feature_set set
)
8668 const struct aarch64_option_cpu_value_table
*opt
;
8669 aarch64_feature_set prev
= 0;
8671 while (prev
!= set
) {
8673 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8674 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8675 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8681 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8682 bfd_boolean ext_only
)
8684 /* We insist on extensions being added before being removed. We achieve
8685 this by using the ADDING_VALUE variable to indicate whether we are
8686 adding an extension (1) or removing it (0) and only allowing it to
8687 change in the order -1 -> 1 -> 0. */
8688 int adding_value
= -1;
8689 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8691 /* Copy the feature set, so that we can modify it. */
8695 while (str
!= NULL
&& *str
!= 0)
8697 const struct aarch64_option_cpu_value_table
*opt
;
8698 const char *ext
= NULL
;
8705 as_bad (_("invalid architectural extension"));
8709 ext
= strchr (++str
, '+');
8715 optlen
= strlen (str
);
8717 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8719 if (adding_value
!= 0)
8724 else if (optlen
> 0)
8726 if (adding_value
== -1)
8728 else if (adding_value
!= 1)
8730 as_bad (_("must specify extensions to add before specifying "
8731 "those to remove"));
8738 as_bad (_("missing architectural extension"));
8742 gas_assert (adding_value
!= -1);
8744 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8745 if (strncmp (opt
->name
, str
, optlen
) == 0)
8747 aarch64_feature_set set
;
8749 /* Add or remove the extension. */
8752 set
= aarch64_feature_enable_set (opt
->value
);
8753 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8757 set
= aarch64_feature_disable_set (opt
->value
);
8758 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8763 if (opt
->name
== NULL
)
8765 as_bad (_("unknown architectural extension `%s'"), str
);
8776 aarch64_parse_cpu (const char *str
)
8778 const struct aarch64_cpu_option_table
*opt
;
8779 const char *ext
= strchr (str
, '+');
8785 optlen
= strlen (str
);
8789 as_bad (_("missing cpu name `%s'"), str
);
8793 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8794 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8796 mcpu_cpu_opt
= &opt
->value
;
8798 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
8803 as_bad (_("unknown cpu `%s'"), str
);
8808 aarch64_parse_arch (const char *str
)
8810 const struct aarch64_arch_option_table
*opt
;
8811 const char *ext
= strchr (str
, '+');
8817 optlen
= strlen (str
);
8821 as_bad (_("missing architecture name `%s'"), str
);
8825 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8826 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8828 march_cpu_opt
= &opt
->value
;
8830 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8835 as_bad (_("unknown architecture `%s'\n"), str
);
8840 struct aarch64_option_abi_value_table
8843 enum aarch64_abi_type value
;
8846 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8847 {"ilp32", AARCH64_ABI_ILP32
},
8848 {"lp64", AARCH64_ABI_LP64
},
8852 aarch64_parse_abi (const char *str
)
8858 as_bad (_("missing abi name `%s'"), str
);
8862 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8863 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8865 aarch64_abi
= aarch64_abis
[i
].value
;
8869 as_bad (_("unknown abi `%s'\n"), str
);
8873 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8875 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8876 aarch64_parse_abi
, NULL
},
8877 #endif /* OBJ_ELF */
8878 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8879 aarch64_parse_cpu
, NULL
},
8880 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8881 aarch64_parse_arch
, NULL
},
8882 {NULL
, NULL
, 0, NULL
}
8886 md_parse_option (int c
, const char *arg
)
8888 struct aarch64_option_table
*opt
;
8889 struct aarch64_long_option_table
*lopt
;
8895 target_big_endian
= 1;
8901 target_big_endian
= 0;
8906 /* Listing option. Just ignore these, we don't support additional
8911 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8913 if (c
== opt
->option
[0]
8914 && ((arg
== NULL
&& opt
->option
[1] == 0)
8915 || streq (arg
, opt
->option
+ 1)))
8917 /* If the option is deprecated, tell the user. */
8918 if (opt
->deprecated
!= NULL
)
8919 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8920 arg
? arg
: "", _(opt
->deprecated
));
8922 if (opt
->var
!= NULL
)
8923 *opt
->var
= opt
->value
;
8929 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8931 /* These options are expected to have an argument. */
8932 if (c
== lopt
->option
[0]
8934 && strncmp (arg
, lopt
->option
+ 1,
8935 strlen (lopt
->option
+ 1)) == 0)
8937 /* If the option is deprecated, tell the user. */
8938 if (lopt
->deprecated
!= NULL
)
8939 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8940 _(lopt
->deprecated
));
8942 /* Call the sup-option parser. */
8943 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8954 md_show_usage (FILE * fp
)
8956 struct aarch64_option_table
*opt
;
8957 struct aarch64_long_option_table
*lopt
;
8959 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8961 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8962 if (opt
->help
!= NULL
)
8963 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8965 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8966 if (lopt
->help
!= NULL
)
8967 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8971 -EB assemble code for a big-endian cpu\n"));
8976 -EL assemble code for a little-endian cpu\n"));
8980 /* Parse a .cpu directive. */
8983 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8985 const struct aarch64_cpu_option_table
*opt
;
8991 name
= input_line_pointer
;
8992 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8993 input_line_pointer
++;
8994 saved_char
= *input_line_pointer
;
8995 *input_line_pointer
= 0;
8997 ext
= strchr (name
, '+');
9000 optlen
= ext
- name
;
9002 optlen
= strlen (name
);
9004 /* Skip the first "all" entry. */
9005 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9006 if (strlen (opt
->name
) == optlen
9007 && strncmp (name
, opt
->name
, optlen
) == 0)
9009 mcpu_cpu_opt
= &opt
->value
;
9011 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9014 cpu_variant
= *mcpu_cpu_opt
;
9016 *input_line_pointer
= saved_char
;
9017 demand_empty_rest_of_line ();
9020 as_bad (_("unknown cpu `%s'"), name
);
9021 *input_line_pointer
= saved_char
;
9022 ignore_rest_of_line ();
9026 /* Parse a .arch directive. */
9029 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9031 const struct aarch64_arch_option_table
*opt
;
9037 name
= input_line_pointer
;
9038 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9039 input_line_pointer
++;
9040 saved_char
= *input_line_pointer
;
9041 *input_line_pointer
= 0;
9043 ext
= strchr (name
, '+');
9046 optlen
= ext
- name
;
9048 optlen
= strlen (name
);
9050 /* Skip the first "all" entry. */
9051 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9052 if (strlen (opt
->name
) == optlen
9053 && strncmp (name
, opt
->name
, optlen
) == 0)
9055 mcpu_cpu_opt
= &opt
->value
;
9057 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9060 cpu_variant
= *mcpu_cpu_opt
;
9062 *input_line_pointer
= saved_char
;
9063 demand_empty_rest_of_line ();
9067 as_bad (_("unknown architecture `%s'\n"), name
);
9068 *input_line_pointer
= saved_char
;
9069 ignore_rest_of_line ();
9072 /* Parse a .arch_extension directive. */
9075 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9078 char *ext
= input_line_pointer
;;
9080 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9081 input_line_pointer
++;
9082 saved_char
= *input_line_pointer
;
9083 *input_line_pointer
= 0;
9085 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9088 cpu_variant
= *mcpu_cpu_opt
;
9090 *input_line_pointer
= saved_char
;
9091 demand_empty_rest_of_line ();
9094 /* Copy symbol information. */
9097 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9099 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);