1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in vector_type_el. */
91 #define NTA_HASINDEX 2
95 enum vector_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Macros to define the register types and masks for the purpose
253 #undef AARCH64_REG_TYPES
254 #define AARCH64_REG_TYPES \
255 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
256 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
257 BASIC_REG_TYPE(SP_32) /* wsp */ \
258 BASIC_REG_TYPE(SP_64) /* sp */ \
259 BASIC_REG_TYPE(Z_32) /* wzr */ \
260 BASIC_REG_TYPE(Z_64) /* xzr */ \
261 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
262 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
263 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
264 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
265 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
266 BASIC_REG_TYPE(CN) /* c[0-7] */ \
267 BASIC_REG_TYPE(VN) /* v[0-31] */ \
268 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
269 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
270 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
271 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
272 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
273 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
274 /* Typecheck: any [BHSDQ]P FP. */ \
275 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
276 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
277 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
278 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
279 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
280 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
281 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
282 /* Any integer register; used for error messages only. */ \
283 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
284 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
285 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
286 /* Pseudo type to mark the end of the enumerator sequence. */ \
289 #undef BASIC_REG_TYPE
290 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
291 #undef MULTI_REG_TYPE
292 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
294 /* Register type enumerators. */
295 typedef enum aarch64_reg_type_
297 /* A list of REG_TYPE_*. */
301 #undef BASIC_REG_TYPE
302 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
304 #define REG_TYPE(T) (1 << REG_TYPE_##T)
305 #undef MULTI_REG_TYPE
306 #define MULTI_REG_TYPE(T,V) V,
308 /* Structure for a hash table entry for a register. */
312 unsigned char number
;
313 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
314 unsigned char builtin
;
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
409 static struct hash_control
*aarch64_hint_opt_hsh
;
411 /* Stuff needed to resolve the label ambiguity
420 static symbolS
*last_label_seen
;
422 /* Literal pool structure. Held on a per-section
423 and per-sub-section basis. */
425 #define MAX_LITERAL_POOL_SIZE 1024
426 typedef struct literal_expression
429 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
430 LITTLENUM_TYPE
* bignum
;
431 } literal_expression
;
433 typedef struct literal_pool
435 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
436 unsigned int next_free_entry
;
442 struct literal_pool
*next
;
445 /* Pointer to a linked list of literal pools. */
446 static literal_pool
*list_of_pools
= NULL
;
450 /* This array holds the chars that always start a comment. If the
451 pre-processor is disabled, these aren't very useful. */
452 const char comment_chars
[] = "";
454 /* This array holds the chars that only start a comment at the beginning of
455 a line. If the line seems to have the form '# 123 filename'
456 .line and .file directives will appear in the pre-processed output. */
457 /* Note that input_file.c hand checks for '#' at the beginning of the
458 first line of the input file. This is because the compiler outputs
459 #NO_APP at the beginning of its output. */
460 /* Also note that comments like this one will always work. */
461 const char line_comment_chars
[] = "#";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant
466 from exp in floating point numbers. */
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant. */
473 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
475 /* Prefix character that indicates the start of an immediate value. */
476 #define is_immediate_prefix(C) ((C) == '#')
478 /* Separator character handling. */
480 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
482 static inline bfd_boolean
483 skip_past_char (char **str
, char c
)
494 #define skip_past_comma(str) skip_past_char (str, ',')
496 /* Arithmetic expressions (possibly involving symbols). */
498 static bfd_boolean in_my_get_expression_p
= FALSE
;
500 /* Third argument to my_get_expression. */
501 #define GE_NO_PREFIX 0
502 #define GE_OPT_PREFIX 1
504 /* Return TRUE if the string pointed by *STR is successfully parsed
505 as an valid expression; *EP will be filled with the information of
506 such an expression. Otherwise return FALSE. */
509 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
514 int prefix_present_p
= 0;
521 if (is_immediate_prefix (**str
))
524 prefix_present_p
= 1;
531 memset (ep
, 0, sizeof (expressionS
));
533 save_in
= input_line_pointer
;
534 input_line_pointer
= *str
;
535 in_my_get_expression_p
= TRUE
;
536 seg
= expression (ep
);
537 in_my_get_expression_p
= FALSE
;
539 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
541 /* We found a bad expression in md_operand(). */
542 *str
= input_line_pointer
;
543 input_line_pointer
= save_in
;
544 if (prefix_present_p
&& ! error_p ())
545 set_fatal_syntax_error (_("bad expression"));
547 set_first_syntax_error (_("bad expression"));
552 if (seg
!= absolute_section
553 && seg
!= text_section
554 && seg
!= data_section
555 && seg
!= bss_section
&& seg
!= undefined_section
)
557 set_syntax_error (_("bad segment"));
558 *str
= input_line_pointer
;
559 input_line_pointer
= save_in
;
566 *str
= input_line_pointer
;
567 input_line_pointer
= save_in
;
571 /* Turn a string in input_line_pointer into a floating point constant
572 of type TYPE, and store the appropriate bytes in *LITP. The number
573 of LITTLENUMS emitted is stored in *SIZEP. An error message is
574 returned, or NULL on OK. */
577 md_atof (int type
, char *litP
, int *sizeP
)
579 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
582 /* We handle all bad expressions here, so that we can report the faulty
583 instruction in the error message. */
585 md_operand (expressionS
* exp
)
587 if (in_my_get_expression_p
)
588 exp
->X_op
= O_illegal
;
591 /* Immediate values. */
593 /* Errors may be set multiple times during parsing or bit encoding
594 (particularly in the Neon bits), but usually the earliest error which is set
595 will be the most meaningful. Avoid overwriting it with later (cascading)
596 errors by calling this function. */
599 first_error (const char *error
)
602 set_syntax_error (error
);
605 /* Similiar to first_error, but this function accepts formatted error
608 first_error_fmt (const char *format
, ...)
613 /* N.B. this single buffer will not cause error messages for different
614 instructions to pollute each other; this is because at the end of
615 processing of each assembly line, error message if any will be
616 collected by as_bad. */
617 static char buffer
[size
];
621 int ret ATTRIBUTE_UNUSED
;
622 va_start (args
, format
);
623 ret
= vsnprintf (buffer
, size
, format
, args
);
624 know (ret
<= size
- 1 && ret
>= 0);
626 set_syntax_error (buffer
);
630 /* Register parsing. */
632 /* Generic register parser which is called by other specialized
634 CCP points to what should be the beginning of a register name.
635 If it is indeed a valid register name, advance CCP over it and
636 return the reg_entry structure; otherwise return NULL.
637 It does not issue diagnostics. */
640 parse_reg (char **ccp
)
646 #ifdef REGISTER_PREFIX
647 if (*start
!= REGISTER_PREFIX
)
653 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
658 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
660 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
669 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
672 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
674 if (reg
->type
== type
)
679 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
680 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
681 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
682 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
683 case REG_TYPE_VN
: /* Vector register. */
684 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
685 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
686 == reg_type_masks
[reg
->type
]);
688 as_fatal ("unhandled type %d", type
);
693 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
694 Return the register number otherwise. *ISREG32 is set to one if the
695 register is 32-bit wide; *ISREGZERO is set to one if the register is
696 of type Z_32 or Z_64.
697 Note that this function does not issue any diagnostics. */
700 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
701 int *isreg32
, int *isregzero
)
704 const reg_entry
*reg
= parse_reg (&str
);
709 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
718 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
723 *isreg32
= reg
->type
== REG_TYPE_R_32
;
730 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
742 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
743 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
744 otherwise return FALSE.
746 Accept only one occurrence of:
747 8b 16b 2h 4h 8h 2s 4s 1d 2d
750 parse_vector_type_for_operand (struct vector_type_el
*parsed_type
, char **str
)
754 unsigned element_size
;
755 enum vector_el_type type
;
765 width
= strtoul (ptr
, &ptr
, 10);
766 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
768 first_error_fmt (_("bad size %d in vector width specifier"), width
);
773 switch (TOLOWER (*ptr
))
801 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
803 first_error (_("missing element size"));
806 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
807 && !(width
== 2 && element_size
== 16))
810 ("invalid element size %d and vector size combination %c"),
816 parsed_type
->type
= type
;
817 parsed_type
->width
= width
;
824 /* Parse a register of the type TYPE.
826 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
827 name or the parsed register is not of TYPE.
829 Otherwise return the register number, and optionally fill in the actual
830 type of the register in *RTYPE when multiple alternatives were given, and
831 return the register shape and element index information in *TYPEINFO.
833 IN_REG_LIST should be set with TRUE if the caller is parsing a register
837 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
838 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
841 const reg_entry
*reg
= parse_reg (&str
);
842 struct vector_type_el atype
;
843 struct vector_type_el parsetype
;
844 bfd_boolean is_typed_vecreg
= FALSE
;
847 atype
.type
= NT_invtype
;
855 set_default_error ();
859 if (! aarch64_check_reg_type (reg
, type
))
861 DEBUG_TRACE ("reg type check failed");
862 set_default_error ();
867 if (type
== REG_TYPE_VN
&& *str
== '.')
869 if (!parse_vector_type_for_operand (&parsetype
, &str
))
872 /* Register if of the form Vn.[bhsdq]. */
873 is_typed_vecreg
= TRUE
;
875 if (parsetype
.width
== 0)
876 /* Expect index. In the new scheme we cannot have
877 Vn.[bhsdq] represent a scalar. Therefore any
878 Vn.[bhsdq] should have an index following it.
879 Except in reglists ofcourse. */
880 atype
.defined
|= NTA_HASINDEX
;
882 atype
.defined
|= NTA_HASTYPE
;
884 atype
.type
= parsetype
.type
;
885 atype
.width
= parsetype
.width
;
888 if (skip_past_char (&str
, '['))
892 /* Reject Sn[index] syntax. */
893 if (!is_typed_vecreg
)
895 first_error (_("this type of register can't be indexed"));
899 if (in_reg_list
== TRUE
)
901 first_error (_("index not allowed inside register list"));
905 atype
.defined
|= NTA_HASINDEX
;
907 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
909 if (exp
.X_op
!= O_constant
)
911 first_error (_("constant expression required"));
915 if (! skip_past_char (&str
, ']'))
918 atype
.index
= exp
.X_add_number
;
920 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
922 /* Indexed vector register expected. */
923 first_error (_("indexed vector register expected"));
927 /* A vector reg Vn should be typed or indexed. */
928 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
930 first_error (_("invalid use of vector register"));
946 Return the register number on success; return PARSE_FAIL otherwise.
948 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
949 the register (e.g. NEON double or quad reg when either has been requested).
951 If this is a NEON vector register with additional type information, fill
952 in the struct pointed to by VECTYPE (if non-NULL).
954 This parser does not handle register list. */
957 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
958 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
960 struct vector_type_el atype
;
962 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
963 /*in_reg_list= */ FALSE
);
965 if (reg
== PARSE_FAIL
)
976 static inline bfd_boolean
977 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
981 && e1
.defined
== e2
.defined
982 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
985 /* This function parses a list of vector registers of type TYPE.
986 On success, it returns the parsed register list information in the
987 following encoded format:
989 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
990 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
992 The information of the register shape and/or index is returned in
995 It returns PARSE_FAIL if the register list is invalid.
997 The list contains one to four registers.
998 Each register can be one of:
1001 All <T> should be identical.
1002 All <index> should be identical.
1003 There are restrictions on <Vt> numbers which are checked later
1004 (by reg_list_valid_p). */
1007 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1008 struct vector_type_el
*vectype
)
1012 struct vector_type_el typeinfo
, typeinfo_first
;
1017 bfd_boolean error
= FALSE
;
1018 bfd_boolean expect_index
= FALSE
;
1022 set_syntax_error (_("expecting {"));
1028 typeinfo_first
.defined
= 0;
1029 typeinfo_first
.type
= NT_invtype
;
1030 typeinfo_first
.width
= -1;
1031 typeinfo_first
.index
= 0;
1040 str
++; /* skip over '-' */
1043 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1044 /*in_reg_list= */ TRUE
);
1045 if (val
== PARSE_FAIL
)
1047 set_first_syntax_error (_("invalid vector register in list"));
1051 /* reject [bhsd]n */
1052 if (typeinfo
.defined
== 0)
1054 set_first_syntax_error (_("invalid scalar register in list"));
1059 if (typeinfo
.defined
& NTA_HASINDEX
)
1060 expect_index
= TRUE
;
1064 if (val
< val_range
)
1066 set_first_syntax_error
1067 (_("invalid range in vector register list"));
1076 typeinfo_first
= typeinfo
;
1077 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1079 set_first_syntax_error
1080 (_("type mismatch in vector register list"));
1085 for (i
= val_range
; i
<= val
; i
++)
1087 ret_val
|= i
<< (5 * nb_regs
);
1092 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1094 skip_whitespace (str
);
1097 set_first_syntax_error (_("end of vector register list not found"));
1102 skip_whitespace (str
);
1106 if (skip_past_char (&str
, '['))
1110 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1111 if (exp
.X_op
!= O_constant
)
1113 set_first_syntax_error (_("constant expression required."));
1116 if (! skip_past_char (&str
, ']'))
1119 typeinfo_first
.index
= exp
.X_add_number
;
1123 set_first_syntax_error (_("expected index"));
1130 set_first_syntax_error (_("too many registers in vector register list"));
1133 else if (nb_regs
== 0)
1135 set_first_syntax_error (_("empty vector register list"));
1141 *vectype
= typeinfo_first
;
1143 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1146 /* Directives: register aliases. */
1149 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1154 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1157 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1160 /* Only warn about a redefinition if it's not defined as the
1162 else if (new->number
!= number
|| new->type
!= type
)
1163 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1168 name
= xstrdup (str
);
1169 new = XNEW (reg_entry
);
1172 new->number
= number
;
1174 new->builtin
= FALSE
;
1176 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1182 /* Look for the .req directive. This is of the form:
1184 new_register_name .req existing_register_name
1186 If we find one, or if it looks sufficiently like one that we want to
1187 handle any error here, return TRUE. Otherwise return FALSE. */
1190 create_register_alias (char *newname
, char *p
)
1192 const reg_entry
*old
;
1193 char *oldname
, *nbuf
;
1196 /* The input scrubber ensures that whitespace after the mnemonic is
1197 collapsed to single spaces. */
1199 if (strncmp (oldname
, " .req ", 6) != 0)
1203 if (*oldname
== '\0')
1206 old
= hash_find (aarch64_reg_hsh
, oldname
);
1209 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1213 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1214 the desired alias name, and p points to its end. If not, then
1215 the desired alias name is in the global original_case_string. */
1216 #ifdef TC_CASE_SENSITIVE
1219 newname
= original_case_string
;
1220 nlen
= strlen (newname
);
1223 nbuf
= xmemdup0 (newname
, nlen
);
1225 /* Create aliases under the new name as stated; an all-lowercase
1226 version of the new name; and an all-uppercase version of the new
1228 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1230 for (p
= nbuf
; *p
; p
++)
1233 if (strncmp (nbuf
, newname
, nlen
))
1235 /* If this attempt to create an additional alias fails, do not bother
1236 trying to create the all-lower case alias. We will fail and issue
1237 a second, duplicate error message. This situation arises when the
1238 programmer does something like:
1241 The second .req creates the "Foo" alias but then fails to create
1242 the artificial FOO alias because it has already been created by the
1244 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1255 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1262 /* Should never be called, as .req goes between the alias and the
1263 register name, not at the beginning of the line. */
1265 s_req (int a ATTRIBUTE_UNUSED
)
1267 as_bad (_("invalid syntax for .req directive"));
1270 /* The .unreq directive deletes an alias which was previously defined
1271 by .req. For example:
1277 s_unreq (int a ATTRIBUTE_UNUSED
)
1282 name
= input_line_pointer
;
1284 while (*input_line_pointer
!= 0
1285 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1286 ++input_line_pointer
;
1288 saved_char
= *input_line_pointer
;
1289 *input_line_pointer
= 0;
1292 as_bad (_("invalid syntax for .unreq directive"));
1295 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1298 as_bad (_("unknown register alias '%s'"), name
);
1299 else if (reg
->builtin
)
1300 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1307 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1308 free ((char *) reg
->name
);
1311 /* Also locate the all upper case and all lower case versions.
1312 Do not complain if we cannot find one or the other as it
1313 was probably deleted above. */
1315 nbuf
= strdup (name
);
1316 for (p
= nbuf
; *p
; p
++)
1318 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1321 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1322 free ((char *) reg
->name
);
1326 for (p
= nbuf
; *p
; p
++)
1328 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1331 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1332 free ((char *) reg
->name
);
1340 *input_line_pointer
= saved_char
;
1341 demand_empty_rest_of_line ();
1344 /* Directives: Instruction set selection. */
1347 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1348 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1349 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1350 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1352 /* Create a new mapping symbol for the transition to STATE. */
1355 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1358 const char *symname
;
1365 type
= BSF_NO_FLAGS
;
1369 type
= BSF_NO_FLAGS
;
1375 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1376 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1378 /* Save the mapping symbols for future reference. Also check that
1379 we do not place two mapping symbols at the same offset within a
1380 frag. We'll handle overlap between frags in
1381 check_mapping_symbols.
1383 If .fill or other data filling directive generates zero sized data,
1384 the mapping symbol for the following code will have the same value
1385 as the one generated for the data filling directive. In this case,
1386 we replace the old symbol with the new one at the same address. */
1389 if (frag
->tc_frag_data
.first_map
!= NULL
)
1391 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1392 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1395 frag
->tc_frag_data
.first_map
= symbolP
;
1397 if (frag
->tc_frag_data
.last_map
!= NULL
)
1399 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1400 S_GET_VALUE (symbolP
));
1401 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1402 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1405 frag
->tc_frag_data
.last_map
= symbolP
;
1408 /* We must sometimes convert a region marked as code to data during
1409 code alignment, if an odd number of bytes have to be padded. The
1410 code mapping symbol is pushed to an aligned address. */
1413 insert_data_mapping_symbol (enum mstate state
,
1414 valueT value
, fragS
* frag
, offsetT bytes
)
1416 /* If there was already a mapping symbol, remove it. */
1417 if (frag
->tc_frag_data
.last_map
!= NULL
1418 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1419 frag
->fr_address
+ value
)
1421 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1425 know (frag
->tc_frag_data
.first_map
== symp
);
1426 frag
->tc_frag_data
.first_map
= NULL
;
1428 frag
->tc_frag_data
.last_map
= NULL
;
1429 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1432 make_mapping_symbol (MAP_DATA
, value
, frag
);
1433 make_mapping_symbol (state
, value
+ bytes
, frag
);
1436 static void mapping_state_2 (enum mstate state
, int max_chars
);
1438 /* Set the mapping state to STATE. Only call this when about to
1439 emit some STATE bytes to the file. */
1442 mapping_state (enum mstate state
)
1444 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1446 if (state
== MAP_INSN
)
1447 /* AArch64 instructions require 4-byte alignment. When emitting
1448 instructions into any section, record the appropriate section
1450 record_alignment (now_seg
, 2);
1452 if (mapstate
== state
)
1453 /* The mapping symbol has already been emitted.
1454 There is nothing else to do. */
1457 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1458 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1459 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1460 evaluated later in the next else. */
1462 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1464 /* Only add the symbol if the offset is > 0:
1465 if we're at the first frag, check it's size > 0;
1466 if we're not at the first frag, then for sure
1467 the offset is > 0. */
1468 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1469 const int add_symbol
= (frag_now
!= frag_first
)
1470 || (frag_now_fix () > 0);
1473 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1477 mapping_state_2 (state
, 0);
1480 /* Same as mapping_state, but MAX_CHARS bytes have already been
1481 allocated. Put the mapping symbol that far back. */
1484 mapping_state_2 (enum mstate state
, int max_chars
)
1486 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1488 if (!SEG_NORMAL (now_seg
))
1491 if (mapstate
== state
)
1492 /* The mapping symbol has already been emitted.
1493 There is nothing else to do. */
1496 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1497 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1500 #define mapping_state(x) /* nothing */
1501 #define mapping_state_2(x, y) /* nothing */
1504 /* Directives: sectioning and alignment. */
1507 s_bss (int ignore ATTRIBUTE_UNUSED
)
1509 /* We don't support putting frags in the BSS segment, we fake it by
1510 marking in_bss, then looking at s_skip for clues. */
1511 subseg_set (bss_section
, 0);
1512 demand_empty_rest_of_line ();
1513 mapping_state (MAP_DATA
);
1517 s_even (int ignore ATTRIBUTE_UNUSED
)
1519 /* Never make frag if expect extra pass. */
1521 frag_align (1, 0, 0);
1523 record_alignment (now_seg
, 1);
1525 demand_empty_rest_of_line ();
1528 /* Directives: Literal pools. */
1530 static literal_pool
*
1531 find_literal_pool (int size
)
1535 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1537 if (pool
->section
== now_seg
1538 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1545 static literal_pool
*
1546 find_or_make_literal_pool (int size
)
1548 /* Next literal pool ID number. */
1549 static unsigned int latest_pool_num
= 1;
1552 pool
= find_literal_pool (size
);
1556 /* Create a new pool. */
1557 pool
= XNEW (literal_pool
);
1561 /* Currently we always put the literal pool in the current text
1562 section. If we were generating "small" model code where we
1563 knew that all code and initialised data was within 1MB then
1564 we could output literals to mergeable, read-only data
1567 pool
->next_free_entry
= 0;
1568 pool
->section
= now_seg
;
1569 pool
->sub_section
= now_subseg
;
1571 pool
->next
= list_of_pools
;
1572 pool
->symbol
= NULL
;
1574 /* Add it to the list. */
1575 list_of_pools
= pool
;
1578 /* New pools, and emptied pools, will have a NULL symbol. */
1579 if (pool
->symbol
== NULL
)
1581 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1582 (valueT
) 0, &zero_address_frag
);
1583 pool
->id
= latest_pool_num
++;
1590 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1591 Return TRUE on success, otherwise return FALSE. */
1593 add_to_lit_pool (expressionS
*exp
, int size
)
1598 pool
= find_or_make_literal_pool (size
);
1600 /* Check if this literal value is already in the pool. */
1601 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1603 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1605 if ((litexp
->X_op
== exp
->X_op
)
1606 && (exp
->X_op
== O_constant
)
1607 && (litexp
->X_add_number
== exp
->X_add_number
)
1608 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1611 if ((litexp
->X_op
== exp
->X_op
)
1612 && (exp
->X_op
== O_symbol
)
1613 && (litexp
->X_add_number
== exp
->X_add_number
)
1614 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1615 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1619 /* Do we need to create a new entry? */
1620 if (entry
== pool
->next_free_entry
)
1622 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1624 set_syntax_error (_("literal pool overflow"));
1628 pool
->literals
[entry
].exp
= *exp
;
1629 pool
->next_free_entry
+= 1;
1630 if (exp
->X_op
== O_big
)
1632 /* PR 16688: Bignums are held in a single global array. We must
1633 copy and preserve that value now, before it is overwritten. */
1634 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1636 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1637 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1640 pool
->literals
[entry
].bignum
= NULL
;
1643 exp
->X_op
= O_symbol
;
1644 exp
->X_add_number
= ((int) entry
) * size
;
1645 exp
->X_add_symbol
= pool
->symbol
;
1650 /* Can't use symbol_new here, so have to create a symbol and then at
1651 a later date assign it a value. Thats what these functions do. */
1654 symbol_locate (symbolS
* symbolP
,
1655 const char *name
,/* It is copied, the caller can modify. */
1656 segT segment
, /* Segment identifier (SEG_<something>). */
1657 valueT valu
, /* Symbol value. */
1658 fragS
* frag
) /* Associated fragment. */
1661 char *preserved_copy_of_name
;
1663 name_length
= strlen (name
) + 1; /* +1 for \0. */
1664 obstack_grow (¬es
, name
, name_length
);
1665 preserved_copy_of_name
= obstack_finish (¬es
);
1667 #ifdef tc_canonicalize_symbol_name
1668 preserved_copy_of_name
=
1669 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1672 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1674 S_SET_SEGMENT (symbolP
, segment
);
1675 S_SET_VALUE (symbolP
, valu
);
1676 symbol_clear_list_pointers (symbolP
);
1678 symbol_set_frag (symbolP
, frag
);
1680 /* Link to end of symbol chain. */
1682 extern int symbol_table_frozen
;
1684 if (symbol_table_frozen
)
1688 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1690 obj_symbol_new_hook (symbolP
);
1692 #ifdef tc_symbol_new_hook
1693 tc_symbol_new_hook (symbolP
);
1697 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1698 #endif /* DEBUG_SYMS */
1703 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1710 for (align
= 2; align
<= 4; align
++)
1712 int size
= 1 << align
;
1714 pool
= find_literal_pool (size
);
1715 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1718 /* Align pool as you have word accesses.
1719 Only make a frag if we have to. */
1721 frag_align (align
, 0, 0);
1723 mapping_state (MAP_DATA
);
1725 record_alignment (now_seg
, align
);
1727 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1729 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1730 (valueT
) frag_now_fix (), frag_now
);
1731 symbol_table_insert (pool
->symbol
);
1733 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1735 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1737 if (exp
->X_op
== O_big
)
1739 /* PR 16688: Restore the global bignum value. */
1740 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1741 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1742 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1745 /* First output the expression in the instruction to the pool. */
1746 emit_expr (exp
, size
); /* .word|.xword */
1748 if (exp
->X_op
== O_big
)
1750 free (pool
->literals
[entry
].bignum
);
1751 pool
->literals
[entry
].bignum
= NULL
;
1755 /* Mark the pool as empty. */
1756 pool
->next_free_entry
= 0;
1757 pool
->symbol
= NULL
;
1762 /* Forward declarations for functions below, in the MD interface
1764 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1765 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1767 /* Directives: Data. */
1768 /* N.B. the support for relocation suffix in this directive needs to be
1769 implemented properly. */
1772 s_aarch64_elf_cons (int nbytes
)
1776 #ifdef md_flush_pending_output
1777 md_flush_pending_output ();
1780 if (is_it_end_of_statement ())
1782 demand_empty_rest_of_line ();
1786 #ifdef md_cons_align
1787 md_cons_align (nbytes
);
1790 mapping_state (MAP_DATA
);
1793 struct reloc_table_entry
*reloc
;
1797 if (exp
.X_op
!= O_symbol
)
1798 emit_expr (&exp
, (unsigned int) nbytes
);
1801 skip_past_char (&input_line_pointer
, '#');
1802 if (skip_past_char (&input_line_pointer
, ':'))
1804 reloc
= find_reloc_table_entry (&input_line_pointer
);
1806 as_bad (_("unrecognized relocation suffix"));
1808 as_bad (_("unimplemented relocation suffix"));
1809 ignore_rest_of_line ();
1813 emit_expr (&exp
, (unsigned int) nbytes
);
1816 while (*input_line_pointer
++ == ',');
1818 /* Put terminator back into stream. */
1819 input_line_pointer
--;
1820 demand_empty_rest_of_line ();
1823 #endif /* OBJ_ELF */
1825 /* Output a 32-bit word, but mark as an instruction. */
1828 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1832 #ifdef md_flush_pending_output
1833 md_flush_pending_output ();
1836 if (is_it_end_of_statement ())
1838 demand_empty_rest_of_line ();
1842 /* Sections are assumed to start aligned. In executable section, there is no
1843 MAP_DATA symbol pending. So we only align the address during
1844 MAP_DATA --> MAP_INSN transition.
1845 For other sections, this is not guaranteed. */
1846 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1847 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1848 frag_align_code (2, 0);
1851 mapping_state (MAP_INSN
);
1857 if (exp
.X_op
!= O_constant
)
1859 as_bad (_("constant expression required"));
1860 ignore_rest_of_line ();
1864 if (target_big_endian
)
1866 unsigned int val
= exp
.X_add_number
;
1867 exp
.X_add_number
= SWAP_32 (val
);
1869 emit_expr (&exp
, 4);
1871 while (*input_line_pointer
++ == ',');
1873 /* Put terminator back into stream. */
1874 input_line_pointer
--;
1875 demand_empty_rest_of_line ();
1879 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1882 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1888 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1889 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1891 demand_empty_rest_of_line ();
1894 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1897 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1901 /* Since we're just labelling the code, there's no need to define a
1904 /* Make sure there is enough room in this frag for the following
1905 blr. This trick only works if the blr follows immediately after
1906 the .tlsdesc directive. */
1908 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1909 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1911 demand_empty_rest_of_line ();
1914 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1917 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
1923 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1924 BFD_RELOC_AARCH64_TLSDESC_LDR
);
1926 demand_empty_rest_of_line ();
1928 #endif /* OBJ_ELF */
1930 static void s_aarch64_arch (int);
1931 static void s_aarch64_cpu (int);
1932 static void s_aarch64_arch_extension (int);
1934 /* This table describes all the machine specific pseudo-ops the assembler
1935 has to support. The fields are:
1936 pseudo-op name without dot
1937 function to call to execute this pseudo-op
1938 Integer arg to pass to the function. */
1940 const pseudo_typeS md_pseudo_table
[] = {
1941 /* Never called because '.req' does not start a line. */
1943 {"unreq", s_unreq
, 0},
1945 {"even", s_even
, 0},
1946 {"ltorg", s_ltorg
, 0},
1947 {"pool", s_ltorg
, 0},
1948 {"cpu", s_aarch64_cpu
, 0},
1949 {"arch", s_aarch64_arch
, 0},
1950 {"arch_extension", s_aarch64_arch_extension
, 0},
1951 {"inst", s_aarch64_inst
, 0},
1953 {"tlsdescadd", s_tlsdescadd
, 0},
1954 {"tlsdesccall", s_tlsdesccall
, 0},
1955 {"tlsdescldr", s_tlsdescldr
, 0},
1956 {"word", s_aarch64_elf_cons
, 4},
1957 {"long", s_aarch64_elf_cons
, 4},
1958 {"xword", s_aarch64_elf_cons
, 8},
1959 {"dword", s_aarch64_elf_cons
, 8},
1965 /* Check whether STR points to a register name followed by a comma or the
1966 end of line; REG_TYPE indicates which register types are checked
1967 against. Return TRUE if STR is such a register name; otherwise return
1968 FALSE. The function does not intend to produce any diagnostics, but since
1969 the register parser aarch64_reg_parse, which is called by this function,
1970 does produce diagnostics, we call clear_error to clear any diagnostics
1971 that may be generated by aarch64_reg_parse.
1972 Also, the function returns FALSE directly if there is any user error
1973 present at the function entry. This prevents the existing diagnostics
1974 state from being spoiled.
1975 The function currently serves parse_constant_immediate and
1976 parse_big_immediate only. */
1978 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1982 /* Prevent the diagnostics state from being spoiled. */
1986 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1988 /* Clear the parsing error that may be set by the reg parser. */
1991 if (reg
== PARSE_FAIL
)
1994 skip_whitespace (str
);
1995 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2001 /* Parser functions used exclusively in instruction operands. */
2003 /* Parse an immediate expression which may not be constant.
2005 To prevent the expression parser from pushing a register name
2006 into the symbol table as an undefined symbol, firstly a check is
2007 done to find out whether STR is a register of type REG_TYPE followed
2008 by a comma or the end of line. Return FALSE if STR is such a string. */
2011 parse_immediate_expression (char **str
, expressionS
*exp
,
2012 aarch64_reg_type reg_type
)
2014 if (reg_name_p (*str
, reg_type
))
2016 set_recoverable_error (_("immediate operand required"));
2020 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2022 if (exp
->X_op
== O_absent
)
2024 set_fatal_syntax_error (_("missing immediate expression"));
2031 /* Constant immediate-value read function for use in insn parsing.
2032 STR points to the beginning of the immediate (with the optional
2033 leading #); *VAL receives the value. REG_TYPE says which register
2034 names should be treated as registers rather than as symbolic immediates.
2036 Return TRUE on success; otherwise return FALSE. */
2039 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2043 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2046 if (exp
.X_op
!= O_constant
)
2048 set_syntax_error (_("constant expression required"));
2052 *val
= exp
.X_add_number
;
2057 encode_imm_float_bits (uint32_t imm
)
2059 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2060 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2063 /* Return TRUE if the single-precision floating-point value encoded in IMM
2064 can be expressed in the AArch64 8-bit signed floating-point format with
2065 3-bit exponent and normalized 4 bits of precision; in other words, the
2066 floating-point value must be expressable as
2067 (+/-) n / 16 * power (2, r)
2068 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2071 aarch64_imm_float_p (uint32_t imm
)
2073 /* If a single-precision floating-point value has the following bit
2074 pattern, it can be expressed in the AArch64 8-bit floating-point
2077 3 32222222 2221111111111
2078 1 09876543 21098765432109876543210
2079 n Eeeeeexx xxxx0000000000000000000
2081 where n, e and each x are either 0 or 1 independently, with
2086 /* Prepare the pattern for 'Eeeeee'. */
2087 if (((imm
>> 30) & 0x1) == 0)
2088 pattern
= 0x3e000000;
2090 pattern
= 0x40000000;
2092 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2093 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2096 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2097 as an IEEE float without any loss of precision. Store the value in
2101 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2103 /* If a double-precision floating-point value has the following bit
2104 pattern, it can be expressed in a float:
2106 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2107 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2108 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2110 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2111 if Eeee_eeee != 1111_1111
2113 where n, e, s and S are either 0 or 1 independently and where ~ is the
2117 uint32_t high32
= imm
>> 32;
2118 uint32_t low32
= imm
;
2120 /* Lower 29 bits need to be 0s. */
2121 if ((imm
& 0x1fffffff) != 0)
2124 /* Prepare the pattern for 'Eeeeeeeee'. */
2125 if (((high32
>> 30) & 0x1) == 0)
2126 pattern
= 0x38000000;
2128 pattern
= 0x40000000;
2131 if ((high32
& 0x78000000) != pattern
)
2134 /* Check Eeee_eeee != 1111_1111. */
2135 if ((high32
& 0x7ff00000) == 0x47f00000)
2138 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2139 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2140 | (low32
>> 29)); /* 3 S bits. */
2144 /* Parse a floating-point immediate. Return TRUE on success and return the
2145 value in *IMMED in the format of IEEE754 single-precision encoding.
2146 *CCP points to the start of the string; DP_P is TRUE when the immediate
2147 is expected to be in double-precision (N.B. this only matters when
2148 hexadecimal representation is involved). REG_TYPE says which register
2149 names should be treated as registers rather than as symbolic immediates.
2151 N.B. 0.0 is accepted by this function. */
2154 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2155 aarch64_reg_type reg_type
)
2159 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2160 int found_fpchar
= 0;
2162 unsigned fpword
= 0;
2163 bfd_boolean hex_p
= FALSE
;
2165 skip_past_char (&str
, '#');
2168 skip_whitespace (fpnum
);
2170 if (strncmp (fpnum
, "0x", 2) == 0)
2172 /* Support the hexadecimal representation of the IEEE754 encoding.
2173 Double-precision is expected when DP_P is TRUE, otherwise the
2174 representation should be in single-precision. */
2175 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2180 if (!can_convert_double_to_float (val
, &fpword
))
2183 else if ((uint64_t) val
> 0xffffffff)
2192 /* We must not accidentally parse an integer as a floating-point number.
2193 Make sure that the value we parse is not an integer by checking for
2194 special characters '.' or 'e'. */
2195 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2196 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2210 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2213 /* Our FP word must be 32 bits (single-precision FP). */
2214 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2216 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2221 if (aarch64_imm_float_p (fpword
) || fpword
== 0)
2229 set_fatal_syntax_error (_("invalid floating-point constant"));
2233 /* Less-generic immediate-value read function with the possibility of loading
2234 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2237 To prevent the expression parser from pushing a register name into the
2238 symbol table as an undefined symbol, a check is firstly done to find
2239 out whether STR is a register of type REG_TYPE followed by a comma or
2240 the end of line. Return FALSE if STR is such a register. */
2243 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2247 if (reg_name_p (ptr
, reg_type
))
2249 set_syntax_error (_("immediate operand required"));
2253 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2255 if (inst
.reloc
.exp
.X_op
== O_constant
)
2256 *imm
= inst
.reloc
.exp
.X_add_number
;
2263 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2264 if NEED_LIBOPCODES is non-zero, the fixup will need
2265 assistance from the libopcodes. */
2268 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2269 const aarch64_opnd_info
*operand
,
2270 int need_libopcodes_p
)
2272 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2273 reloc
->opnd
= operand
->type
;
2274 if (need_libopcodes_p
)
2275 reloc
->need_libopcodes_p
= 1;
2278 /* Return TRUE if the instruction needs to be fixed up later internally by
2279 the GAS; otherwise return FALSE. */
2281 static inline bfd_boolean
2282 aarch64_gas_internal_fixup_p (void)
2284 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2287 /* Assign the immediate value to the relavant field in *OPERAND if
2288 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2289 needs an internal fixup in a later stage.
2290 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2291 IMM.VALUE that may get assigned with the constant. */
2293 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2294 aarch64_opnd_info
*operand
,
2296 int need_libopcodes_p
,
2299 if (reloc
->exp
.X_op
== O_constant
)
2302 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2304 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2305 reloc
->type
= BFD_RELOC_UNUSED
;
2309 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2310 /* Tell libopcodes to ignore this operand or not. This is helpful
2311 when one of the operands needs to be fixed up later but we need
2312 libopcodes to check the other operands. */
2313 operand
->skip
= skip_p
;
2317 /* Relocation modifiers. Each entry in the table contains the textual
2318 name for the relocation which may be placed before a symbol used as
2319 a load/store offset, or add immediate. It must be surrounded by a
2320 leading and trailing colon, for example:
2322 ldr x0, [x1, #:rello:varsym]
2323 add x0, x1, #:rello:varsym */
2325 struct reloc_table_entry
2329 bfd_reloc_code_real_type adr_type
;
2330 bfd_reloc_code_real_type adrp_type
;
2331 bfd_reloc_code_real_type movw_type
;
2332 bfd_reloc_code_real_type add_type
;
2333 bfd_reloc_code_real_type ldst_type
;
2334 bfd_reloc_code_real_type ld_literal_type
;
2337 static struct reloc_table_entry reloc_table
[] = {
2338 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2343 BFD_RELOC_AARCH64_ADD_LO12
,
2344 BFD_RELOC_AARCH64_LDST_LO12
,
2347 /* Higher 21 bits of pc-relative page offset: ADRP */
2350 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2356 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2359 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2365 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2369 BFD_RELOC_AARCH64_MOVW_G0
,
2374 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2378 BFD_RELOC_AARCH64_MOVW_G0_S
,
2383 /* Less significant bits 0-15 of address/value: MOVK, no check */
2387 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2392 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2396 BFD_RELOC_AARCH64_MOVW_G1
,
2401 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2405 BFD_RELOC_AARCH64_MOVW_G1_S
,
2410 /* Less significant bits 16-31 of address/value: MOVK, no check */
2414 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2419 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2423 BFD_RELOC_AARCH64_MOVW_G2
,
2428 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2432 BFD_RELOC_AARCH64_MOVW_G2_S
,
2437 /* Less significant bits 32-47 of address/value: MOVK, no check */
2441 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2446 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2450 BFD_RELOC_AARCH64_MOVW_G3
,
2455 /* Get to the page containing GOT entry for a symbol. */
2458 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2462 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2464 /* 12 bit offset into the page containing GOT entry for that symbol. */
2470 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2473 /* 0-15 bits of address/value: MOVk, no check. */
2477 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2482 /* Most significant bits 16-31 of address/value: MOVZ. */
2486 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2491 /* 15 bit offset into the page containing GOT entry for that symbol. */
2497 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2500 /* Get to the page containing GOT TLS entry for a symbol */
2501 {"gottprel_g0_nc", 0,
2504 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2509 /* Get to the page containing GOT TLS entry for a symbol */
2513 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2518 /* Get to the page containing GOT TLS entry for a symbol */
2520 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2521 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2527 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2532 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2536 /* Lower 16 bits address/value: MOVk. */
2540 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2545 /* Most significant bits 16-31 of address/value: MOVZ. */
2549 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2554 /* Get to the page containing GOT TLS entry for a symbol */
2556 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2557 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2561 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2563 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2568 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2569 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2572 /* Get to the page containing GOT TLS entry for a symbol.
2573 The same as GD, we allocate two consecutive GOT slots
2574 for module index and module offset, the only difference
2575 with GD is the module offset should be intialized to
2576 zero without any outstanding runtime relocation. */
2578 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2579 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2585 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2586 {"tlsldm_lo12_nc", 0,
2590 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2594 /* 12 bit offset into the module TLS base address. */
2599 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2600 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2603 /* Same as dtprel_lo12, no overflow check. */
2604 {"dtprel_lo12_nc", 0,
2608 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2609 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2612 /* bits[23:12] of offset to the module TLS base address. */
2617 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2621 /* bits[15:0] of offset to the module TLS base address. */
2625 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2630 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2634 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2639 /* bits[31:16] of offset to the module TLS base address. */
2643 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2648 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2652 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2657 /* bits[47:32] of offset to the module TLS base address. */
2661 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2666 /* Lower 16 bit offset into GOT entry for a symbol */
2667 {"tlsdesc_off_g0_nc", 0,
2670 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2675 /* Higher 16 bit offset into GOT entry for a symbol */
2676 {"tlsdesc_off_g1", 0,
2679 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2684 /* Get to the page containing GOT TLS entry for a symbol */
2687 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2691 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2693 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2694 {"gottprel_lo12", 0,
2699 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2702 /* Get tp offset for a symbol. */
2707 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2711 /* Get tp offset for a symbol. */
2716 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2720 /* Get tp offset for a symbol. */
2725 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2729 /* Get tp offset for a symbol. */
2730 {"tprel_lo12_nc", 0,
2734 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2738 /* Most significant bits 32-47 of address/value: MOVZ. */
2742 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2747 /* Most significant bits 16-31 of address/value: MOVZ. */
2751 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2756 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2760 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2765 /* Most significant bits 0-15 of address/value: MOVZ. */
2769 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2774 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2778 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2783 /* 15bit offset from got entry to base address of GOT table. */
2789 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2792 /* 14bit offset from got entry to base address of GOT table. */
2798 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2802 /* Given the address of a pointer pointing to the textual name of a
2803 relocation as may appear in assembler source, attempt to find its
2804 details in reloc_table. The pointer will be updated to the character
2805 after the trailing colon. On failure, NULL will be returned;
2806 otherwise return the reloc_table_entry. */
2808 static struct reloc_table_entry
*
2809 find_reloc_table_entry (char **str
)
2812 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2814 int length
= strlen (reloc_table
[i
].name
);
2816 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2817 && (*str
)[length
] == ':')
2819 *str
+= (length
+ 1);
2820 return &reloc_table
[i
];
2827 /* Mode argument to parse_shift and parser_shifter_operand. */
2828 enum parse_shift_mode
2830 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2832 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2834 SHIFTED_LSL
, /* bare "lsl #n" */
2835 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2836 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2839 /* Parse a <shift> operator on an AArch64 data processing instruction.
2840 Return TRUE on success; otherwise return FALSE. */
2842 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2844 const struct aarch64_name_value_pair
*shift_op
;
2845 enum aarch64_modifier_kind kind
;
2851 for (p
= *str
; ISALPHA (*p
); p
++)
2856 set_syntax_error (_("shift expression expected"));
2860 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2862 if (shift_op
== NULL
)
2864 set_syntax_error (_("shift operator expected"));
2868 kind
= aarch64_get_operand_modifier (shift_op
);
2870 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2872 set_syntax_error (_("invalid use of 'MSL'"));
2878 case SHIFTED_LOGIC_IMM
:
2879 if (aarch64_extend_operator_p (kind
) == TRUE
)
2881 set_syntax_error (_("extending shift is not permitted"));
2886 case SHIFTED_ARITH_IMM
:
2887 if (kind
== AARCH64_MOD_ROR
)
2889 set_syntax_error (_("'ROR' shift is not permitted"));
2895 if (kind
!= AARCH64_MOD_LSL
)
2897 set_syntax_error (_("only 'LSL' shift is permitted"));
2902 case SHIFTED_REG_OFFSET
:
2903 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2904 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2906 set_fatal_syntax_error
2907 (_("invalid shift for the register offset addressing mode"));
2912 case SHIFTED_LSL_MSL
:
2913 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2915 set_syntax_error (_("invalid shift operator"));
2924 /* Whitespace can appear here if the next thing is a bare digit. */
2925 skip_whitespace (p
);
2927 /* Parse shift amount. */
2929 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2930 exp
.X_op
= O_absent
;
2933 if (is_immediate_prefix (*p
))
2938 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2940 if (exp
.X_op
== O_absent
)
2942 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2944 set_syntax_error (_("missing shift amount"));
2947 operand
->shifter
.amount
= 0;
2949 else if (exp
.X_op
!= O_constant
)
2951 set_syntax_error (_("constant shift amount required"));
2954 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2956 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2961 operand
->shifter
.amount
= exp
.X_add_number
;
2962 operand
->shifter
.amount_present
= 1;
2965 operand
->shifter
.operator_present
= 1;
2966 operand
->shifter
.kind
= kind
;
2972 /* Parse a <shifter_operand> for a data processing instruction:
2975 #<immediate>, LSL #imm
2977 Validation of immediate operands is deferred to md_apply_fix.
2979 Return TRUE on success; otherwise return FALSE. */
2982 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2983 enum parse_shift_mode mode
)
2987 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2992 /* Accept an immediate expression. */
2993 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2996 /* Accept optional LSL for arithmetic immediate values. */
2997 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2998 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3001 /* Not accept any shifter for logical immediate values. */
3002 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3003 && parse_shift (&p
, operand
, mode
))
3005 set_syntax_error (_("unexpected shift operator"));
3013 /* Parse a <shifter_operand> for a data processing instruction:
3018 #<immediate>, LSL #imm
3020 where <shift> is handled by parse_shift above, and the last two
3021 cases are handled by the function above.
3023 Validation of immediate operands is deferred to md_apply_fix.
3025 Return TRUE on success; otherwise return FALSE. */
3028 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3029 enum parse_shift_mode mode
)
3032 int isreg32
, isregzero
;
3033 enum aarch64_operand_class opd_class
3034 = aarch64_get_operand_class (operand
->type
);
3037 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
3039 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3041 set_syntax_error (_("unexpected register in the immediate operand"));
3045 if (!isregzero
&& reg
== REG_SP
)
3047 set_syntax_error (BAD_SP
);
3051 operand
->reg
.regno
= reg
;
3052 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
3054 /* Accept optional shift operation on register. */
3055 if (! skip_past_comma (str
))
3058 if (! parse_shift (str
, operand
, mode
))
3063 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3066 (_("integer register expected in the extended/shifted operand "
3071 /* We have a shifted immediate variable. */
3072 return parse_shifter_operand_imm (str
, operand
, mode
);
3075 /* Return TRUE on success; return FALSE otherwise. */
3078 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3079 enum parse_shift_mode mode
)
3083 /* Determine if we have the sequence of characters #: or just :
3084 coming next. If we do, then we check for a :rello: relocation
3085 modifier. If we don't, punt the whole lot to
3086 parse_shifter_operand. */
3088 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3090 struct reloc_table_entry
*entry
;
3098 /* Try to parse a relocation. Anything else is an error. */
3099 if (!(entry
= find_reloc_table_entry (str
)))
3101 set_syntax_error (_("unknown relocation modifier"));
3105 if (entry
->add_type
== 0)
3108 (_("this relocation modifier is not allowed on this instruction"));
3112 /* Save str before we decompose it. */
3115 /* Next, we parse the expression. */
3116 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3119 /* Record the relocation type (use the ADD variant here). */
3120 inst
.reloc
.type
= entry
->add_type
;
3121 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3123 /* If str is empty, we've reached the end, stop here. */
3127 /* Otherwise, we have a shifted reloc modifier, so rewind to
3128 recover the variable name and continue parsing for the shifter. */
3130 return parse_shifter_operand_imm (str
, operand
, mode
);
3133 return parse_shifter_operand (str
, operand
, mode
);
3136 /* Parse all forms of an address expression. Information is written
3137 to *OPERAND and/or inst.reloc.
3139 The A64 instruction set has the following addressing modes:
3142 [base] // in SIMD ld/st structure
3143 [base{,#0}] // in ld/st exclusive
3145 [base,Xm{,LSL #imm}]
3146 [base,Xm,SXTX {#imm}]
3147 [base,Wm,(S|U)XTW {#imm}]
3152 [base],Xm // in SIMD ld/st structure
3153 PC-relative (literal)
3157 (As a convenience, the notation "=immediate" is permitted in conjunction
3158 with the pc-relative literal load instructions to automatically place an
3159 immediate value or symbolic address in a nearby literal pool and generate
3160 a hidden label which references it.)
3162 Upon a successful parsing, the address structure in *OPERAND will be
3163 filled in the following way:
3165 .base_regno = <base>
3166 .offset.is_reg // 1 if the offset is a register
3168 .offset.regno = <Rm>
3170 For different addressing modes defined in the A64 ISA:
3173 .pcrel=0; .preind=1; .postind=0; .writeback=0
3175 .pcrel=0; .preind=1; .postind=0; .writeback=1
3177 .pcrel=0; .preind=0; .postind=1; .writeback=1
3178 PC-relative (literal)
3179 .pcrel=1; .preind=1; .postind=0; .writeback=0
3181 The shift/extension information, if any, will be stored in .shifter.
3183 It is the caller's responsibility to check for addressing modes not
3184 supported by the instruction, and to set inst.reloc.type. */
3187 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3188 int accept_reg_post_index
)
3192 int isreg32
, isregzero
;
3193 expressionS
*exp
= &inst
.reloc
.exp
;
3195 if (! skip_past_char (&p
, '['))
3197 /* =immediate or label. */
3198 operand
->addr
.pcrel
= 1;
3199 operand
->addr
.preind
= 1;
3201 /* #:<reloc_op>:<symbol> */
3202 skip_past_char (&p
, '#');
3203 if (reloc
&& skip_past_char (&p
, ':'))
3205 bfd_reloc_code_real_type ty
;
3206 struct reloc_table_entry
*entry
;
3208 /* Try to parse a relocation modifier. Anything else is
3210 entry
= find_reloc_table_entry (&p
);
3213 set_syntax_error (_("unknown relocation modifier"));
3217 switch (operand
->type
)
3219 case AARCH64_OPND_ADDR_PCREL21
:
3221 ty
= entry
->adr_type
;
3225 ty
= entry
->ld_literal_type
;
3232 (_("this relocation modifier is not allowed on this "
3238 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3240 set_syntax_error (_("invalid relocation expression"));
3244 /* #:<reloc_op>:<expr> */
3245 /* Record the relocation type. */
3246 inst
.reloc
.type
= ty
;
3247 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3252 if (skip_past_char (&p
, '='))
3253 /* =immediate; need to generate the literal in the literal pool. */
3254 inst
.gen_lit_pool
= 1;
3256 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3258 set_syntax_error (_("invalid address"));
3269 /* Accept SP and reject ZR */
3270 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3271 if (reg
== PARSE_FAIL
|| isreg32
)
3273 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3276 operand
->addr
.base_regno
= reg
;
3279 if (skip_past_comma (&p
))
3282 operand
->addr
.preind
= 1;
3284 /* Reject SP and accept ZR */
3285 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3286 if (reg
!= PARSE_FAIL
)
3289 operand
->addr
.offset
.regno
= reg
;
3290 operand
->addr
.offset
.is_reg
= 1;
3291 /* Shifted index. */
3292 if (skip_past_comma (&p
))
3295 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3296 /* Use the diagnostics set in parse_shift, so not set new
3297 error message here. */
3301 [base,Xm{,LSL #imm}]
3302 [base,Xm,SXTX {#imm}]
3303 [base,Wm,(S|U)XTW {#imm}] */
3304 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3305 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3306 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3310 set_syntax_error (_("invalid use of 32-bit register offset"));
3316 set_syntax_error (_("invalid use of 64-bit register offset"));
3322 /* [Xn,#:<reloc_op>:<symbol> */
3323 skip_past_char (&p
, '#');
3324 if (reloc
&& skip_past_char (&p
, ':'))
3326 struct reloc_table_entry
*entry
;
3328 /* Try to parse a relocation modifier. Anything else is
3330 if (!(entry
= find_reloc_table_entry (&p
)))
3332 set_syntax_error (_("unknown relocation modifier"));
3336 if (entry
->ldst_type
== 0)
3339 (_("this relocation modifier is not allowed on this "
3344 /* [Xn,#:<reloc_op>: */
3345 /* We now have the group relocation table entry corresponding to
3346 the name in the assembler source. Next, we parse the
3348 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3350 set_syntax_error (_("invalid relocation expression"));
3354 /* [Xn,#:<reloc_op>:<expr> */
3355 /* Record the load/store relocation type. */
3356 inst
.reloc
.type
= entry
->ldst_type
;
3357 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3359 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3361 set_syntax_error (_("invalid expression in the address"));
3368 if (! skip_past_char (&p
, ']'))
3370 set_syntax_error (_("']' expected"));
3374 if (skip_past_char (&p
, '!'))
3376 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3378 set_syntax_error (_("register offset not allowed in pre-indexed "
3379 "addressing mode"));
3383 operand
->addr
.writeback
= 1;
3385 else if (skip_past_comma (&p
))
3388 operand
->addr
.postind
= 1;
3389 operand
->addr
.writeback
= 1;
3391 if (operand
->addr
.preind
)
3393 set_syntax_error (_("cannot combine pre- and post-indexing"));
3397 if (accept_reg_post_index
3398 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3399 &isregzero
)) != PARSE_FAIL
)
3404 set_syntax_error (_("invalid 32-bit register offset"));
3407 operand
->addr
.offset
.regno
= reg
;
3408 operand
->addr
.offset
.is_reg
= 1;
3410 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3413 set_syntax_error (_("invalid expression in the address"));
3418 /* If at this point neither .preind nor .postind is set, we have a
3419 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3420 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3422 if (operand
->addr
.writeback
)
3425 set_syntax_error (_("missing offset in the pre-indexed address"));
3428 operand
->addr
.preind
= 1;
3429 inst
.reloc
.exp
.X_op
= O_constant
;
3430 inst
.reloc
.exp
.X_add_number
= 0;
3437 /* Return TRUE on success; otherwise return FALSE. */
3439 parse_address (char **str
, aarch64_opnd_info
*operand
,
3440 int accept_reg_post_index
)
3442 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3445 /* Return TRUE on success; otherwise return FALSE. */
3447 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3449 return parse_address_main (str
, operand
, 1, 0);
3452 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3453 Return TRUE on success; otherwise return FALSE. */
3455 parse_half (char **str
, int *internal_fixup_p
)
3459 skip_past_char (&p
, '#');
3461 gas_assert (internal_fixup_p
);
3462 *internal_fixup_p
= 0;
3466 struct reloc_table_entry
*entry
;
3468 /* Try to parse a relocation. Anything else is an error. */
3470 if (!(entry
= find_reloc_table_entry (&p
)))
3472 set_syntax_error (_("unknown relocation modifier"));
3476 if (entry
->movw_type
== 0)
3479 (_("this relocation modifier is not allowed on this instruction"));
3483 inst
.reloc
.type
= entry
->movw_type
;
3486 *internal_fixup_p
= 1;
3488 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3495 /* Parse an operand for an ADRP instruction:
3497 Return TRUE on success; otherwise return FALSE. */
3500 parse_adrp (char **str
)
3507 struct reloc_table_entry
*entry
;
3509 /* Try to parse a relocation. Anything else is an error. */
3511 if (!(entry
= find_reloc_table_entry (&p
)))
3513 set_syntax_error (_("unknown relocation modifier"));
3517 if (entry
->adrp_type
== 0)
3520 (_("this relocation modifier is not allowed on this instruction"));
3524 inst
.reloc
.type
= entry
->adrp_type
;
3527 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3529 inst
.reloc
.pc_rel
= 1;
3531 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3538 /* Miscellaneous. */
3540 /* Parse an option for a preload instruction. Returns the encoding for the
3541 option, or PARSE_FAIL. */
3544 parse_pldop (char **str
)
3547 const struct aarch64_name_value_pair
*o
;
3550 while (ISALNUM (*q
))
3553 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3561 /* Parse an option for a barrier instruction. Returns the encoding for the
3562 option, or PARSE_FAIL. */
3565 parse_barrier (char **str
)
3568 const asm_barrier_opt
*o
;
3571 while (ISALPHA (*q
))
3574 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3582 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3583 return 0 if successful. Otherwise return PARSE_FAIL. */
3586 parse_barrier_psb (char **str
,
3587 const struct aarch64_name_value_pair
** hint_opt
)
3590 const struct aarch64_name_value_pair
*o
;
3593 while (ISALPHA (*q
))
3596 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3599 set_fatal_syntax_error
3600 ( _("unknown or missing option to PSB"));
3604 if (o
->value
!= 0x11)
3606 /* PSB only accepts option name 'CSYNC'. */
3608 (_("the specified option is not accepted for PSB"));
3617 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3618 Returns the encoding for the option, or PARSE_FAIL.
3620 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3621 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3623 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3624 field, otherwise as a system register.
3628 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3629 int imple_defined_p
, int pstatefield_p
)
3633 const aarch64_sys_reg
*o
;
3637 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3639 *p
++ = TOLOWER (*q
);
3641 /* Assert that BUF be large enough. */
3642 gas_assert (p
- buf
== q
- *str
);
3644 o
= hash_find (sys_regs
, buf
);
3647 if (!imple_defined_p
)
3651 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3652 unsigned int op0
, op1
, cn
, cm
, op2
;
3654 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3657 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3659 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3664 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3665 as_bad (_("selected processor does not support PSTATE field "
3667 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3668 as_bad (_("selected processor does not support system register "
3670 if (aarch64_sys_reg_deprecated_p (o
))
3671 as_warn (_("system register name '%s' is deprecated and may be "
3672 "removed in a future release"), buf
);
3680 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3681 for the option, or NULL. */
3683 static const aarch64_sys_ins_reg
*
3684 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3688 const aarch64_sys_ins_reg
*o
;
3691 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3693 *p
++ = TOLOWER (*q
);
3696 o
= hash_find (sys_ins_regs
, buf
);
3700 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3701 as_bad (_("selected processor does not support system register "
3708 #define po_char_or_fail(chr) do { \
3709 if (! skip_past_char (&str, chr)) \
3713 #define po_reg_or_fail(regtype) do { \
3714 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3715 if (val == PARSE_FAIL) \
3717 set_default_error (); \
3722 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3723 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3724 &isreg32, &isregzero); \
3725 if (val == PARSE_FAIL) \
3727 set_default_error (); \
3730 info->reg.regno = val; \
3732 info->qualifier = AARCH64_OPND_QLF_W; \
3734 info->qualifier = AARCH64_OPND_QLF_X; \
3737 #define po_imm_nc_or_fail() do { \
3738 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3742 #define po_imm_or_fail(min, max) do { \
3743 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3745 if (val < min || val > max) \
3747 set_fatal_syntax_error (_("immediate value out of range "\
3748 #min " to "#max)); \
3753 #define po_misc_or_fail(expr) do { \
3758 /* encode the 12-bit imm field of Add/sub immediate */
3759 static inline uint32_t
3760 encode_addsub_imm (uint32_t imm
)
3765 /* encode the shift amount field of Add/sub immediate */
3766 static inline uint32_t
3767 encode_addsub_imm_shift_amount (uint32_t cnt
)
3773 /* encode the imm field of Adr instruction */
3774 static inline uint32_t
3775 encode_adr_imm (uint32_t imm
)
3777 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3778 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3781 /* encode the immediate field of Move wide immediate */
3782 static inline uint32_t
3783 encode_movw_imm (uint32_t imm
)
3788 /* encode the 26-bit offset of unconditional branch */
3789 static inline uint32_t
3790 encode_branch_ofs_26 (uint32_t ofs
)
3792 return ofs
& ((1 << 26) - 1);
3795 /* encode the 19-bit offset of conditional branch and compare & branch */
3796 static inline uint32_t
3797 encode_cond_branch_ofs_19 (uint32_t ofs
)
3799 return (ofs
& ((1 << 19) - 1)) << 5;
3802 /* encode the 19-bit offset of ld literal */
3803 static inline uint32_t
3804 encode_ld_lit_ofs_19 (uint32_t ofs
)
3806 return (ofs
& ((1 << 19) - 1)) << 5;
3809 /* Encode the 14-bit offset of test & branch. */
3810 static inline uint32_t
3811 encode_tst_branch_ofs_14 (uint32_t ofs
)
3813 return (ofs
& ((1 << 14) - 1)) << 5;
3816 /* Encode the 16-bit imm field of svc/hvc/smc. */
3817 static inline uint32_t
3818 encode_svc_imm (uint32_t imm
)
3823 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3824 static inline uint32_t
3825 reencode_addsub_switch_add_sub (uint32_t opcode
)
3827 return opcode
^ (1 << 30);
3830 static inline uint32_t
3831 reencode_movzn_to_movz (uint32_t opcode
)
3833 return opcode
| (1 << 30);
3836 static inline uint32_t
3837 reencode_movzn_to_movn (uint32_t opcode
)
3839 return opcode
& ~(1 << 30);
3842 /* Overall per-instruction processing. */
3844 /* We need to be able to fix up arbitrary expressions in some statements.
3845 This is so that we can handle symbols that are an arbitrary distance from
3846 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3847 which returns part of an address in a form which will be valid for
3848 a data instruction. We do this by pushing the expression into a symbol
3849 in the expr_section, and creating a fix for that. */
3852 fix_new_aarch64 (fragS
* frag
,
3854 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3864 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3868 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3875 /* Diagnostics on operands errors. */
3877 /* By default, output verbose error message.
3878 Disable the verbose error message by -mno-verbose-error. */
3879 static int verbose_error_p
= 1;
3881 #ifdef DEBUG_AARCH64
3882 /* N.B. this is only for the purpose of debugging. */
3883 const char* operand_mismatch_kind_names
[] =
3886 "AARCH64_OPDE_RECOVERABLE",
3887 "AARCH64_OPDE_SYNTAX_ERROR",
3888 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3889 "AARCH64_OPDE_INVALID_VARIANT",
3890 "AARCH64_OPDE_OUT_OF_RANGE",
3891 "AARCH64_OPDE_UNALIGNED",
3892 "AARCH64_OPDE_REG_LIST",
3893 "AARCH64_OPDE_OTHER_ERROR",
3895 #endif /* DEBUG_AARCH64 */
3897 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3899 When multiple errors of different kinds are found in the same assembly
3900 line, only the error of the highest severity will be picked up for
3901 issuing the diagnostics. */
3903 static inline bfd_boolean
3904 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3905 enum aarch64_operand_error_kind rhs
)
3907 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3908 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3909 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3910 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3911 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3912 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3913 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3914 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3918 /* Helper routine to get the mnemonic name from the assembly instruction
3919 line; should only be called for the diagnosis purpose, as there is
3920 string copy operation involved, which may affect the runtime
3921 performance if used in elsewhere. */
3924 get_mnemonic_name (const char *str
)
3926 static char mnemonic
[32];
3929 /* Get the first 15 bytes and assume that the full name is included. */
3930 strncpy (mnemonic
, str
, 31);
3931 mnemonic
[31] = '\0';
3933 /* Scan up to the end of the mnemonic, which must end in white space,
3934 '.', or end of string. */
3935 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3940 /* Append '...' to the truncated long name. */
3941 if (ptr
- mnemonic
== 31)
3942 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3948 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3950 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3951 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3954 /* Data strutures storing one user error in the assembly code related to
3957 struct operand_error_record
3959 const aarch64_opcode
*opcode
;
3960 aarch64_operand_error detail
;
3961 struct operand_error_record
*next
;
3964 typedef struct operand_error_record operand_error_record
;
3966 struct operand_errors
3968 operand_error_record
*head
;
3969 operand_error_record
*tail
;
3972 typedef struct operand_errors operand_errors
;
3974 /* Top-level data structure reporting user errors for the current line of
3976 The way md_assemble works is that all opcodes sharing the same mnemonic
3977 name are iterated to find a match to the assembly line. In this data
3978 structure, each of the such opcodes will have one operand_error_record
3979 allocated and inserted. In other words, excessive errors related with
3980 a single opcode are disregarded. */
3981 operand_errors operand_error_report
;
3983 /* Free record nodes. */
3984 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3986 /* Initialize the data structure that stores the operand mismatch
3987 information on assembling one line of the assembly code. */
3989 init_operand_error_report (void)
3991 if (operand_error_report
.head
!= NULL
)
3993 gas_assert (operand_error_report
.tail
!= NULL
);
3994 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3995 free_opnd_error_record_nodes
= operand_error_report
.head
;
3996 operand_error_report
.head
= NULL
;
3997 operand_error_report
.tail
= NULL
;
4000 gas_assert (operand_error_report
.tail
== NULL
);
4003 /* Return TRUE if some operand error has been recorded during the
4004 parsing of the current assembly line using the opcode *OPCODE;
4005 otherwise return FALSE. */
4006 static inline bfd_boolean
4007 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4009 operand_error_record
*record
= operand_error_report
.head
;
4010 return record
&& record
->opcode
== opcode
;
4013 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4014 OPCODE field is initialized with OPCODE.
4015 N.B. only one record for each opcode, i.e. the maximum of one error is
4016 recorded for each instruction template. */
4019 add_operand_error_record (const operand_error_record
* new_record
)
4021 const aarch64_opcode
*opcode
= new_record
->opcode
;
4022 operand_error_record
* record
= operand_error_report
.head
;
4024 /* The record may have been created for this opcode. If not, we need
4026 if (! opcode_has_operand_error_p (opcode
))
4028 /* Get one empty record. */
4029 if (free_opnd_error_record_nodes
== NULL
)
4031 record
= XNEW (operand_error_record
);
4035 record
= free_opnd_error_record_nodes
;
4036 free_opnd_error_record_nodes
= record
->next
;
4038 record
->opcode
= opcode
;
4039 /* Insert at the head. */
4040 record
->next
= operand_error_report
.head
;
4041 operand_error_report
.head
= record
;
4042 if (operand_error_report
.tail
== NULL
)
4043 operand_error_report
.tail
= record
;
4045 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4046 && record
->detail
.index
<= new_record
->detail
.index
4047 && operand_error_higher_severity_p (record
->detail
.kind
,
4048 new_record
->detail
.kind
))
4050 /* In the case of multiple errors found on operands related with a
4051 single opcode, only record the error of the leftmost operand and
4052 only if the error is of higher severity. */
4053 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4054 " the existing error %s on operand %d",
4055 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4056 new_record
->detail
.index
,
4057 operand_mismatch_kind_names
[record
->detail
.kind
],
4058 record
->detail
.index
);
4062 record
->detail
= new_record
->detail
;
4066 record_operand_error_info (const aarch64_opcode
*opcode
,
4067 aarch64_operand_error
*error_info
)
4069 operand_error_record record
;
4070 record
.opcode
= opcode
;
4071 record
.detail
= *error_info
;
4072 add_operand_error_record (&record
);
4075 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4076 error message *ERROR, for operand IDX (count from 0). */
4079 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4080 enum aarch64_operand_error_kind kind
,
4083 aarch64_operand_error info
;
4084 memset(&info
, 0, sizeof (info
));
4088 record_operand_error_info (opcode
, &info
);
4092 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4093 enum aarch64_operand_error_kind kind
,
4094 const char* error
, const int *extra_data
)
4096 aarch64_operand_error info
;
4100 info
.data
[0] = extra_data
[0];
4101 info
.data
[1] = extra_data
[1];
4102 info
.data
[2] = extra_data
[2];
4103 record_operand_error_info (opcode
, &info
);
4107 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4108 const char* error
, int lower_bound
,
4111 int data
[3] = {lower_bound
, upper_bound
, 0};
4112 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4116 /* Remove the operand error record for *OPCODE. */
4117 static void ATTRIBUTE_UNUSED
4118 remove_operand_error_record (const aarch64_opcode
*opcode
)
4120 if (opcode_has_operand_error_p (opcode
))
4122 operand_error_record
* record
= operand_error_report
.head
;
4123 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4124 operand_error_report
.head
= record
->next
;
4125 record
->next
= free_opnd_error_record_nodes
;
4126 free_opnd_error_record_nodes
= record
;
4127 if (operand_error_report
.head
== NULL
)
4129 gas_assert (operand_error_report
.tail
== record
);
4130 operand_error_report
.tail
= NULL
;
4135 /* Given the instruction in *INSTR, return the index of the best matched
4136 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4138 Return -1 if there is no qualifier sequence; return the first match
4139 if there is multiple matches found. */
4142 find_best_match (const aarch64_inst
*instr
,
4143 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4145 int i
, num_opnds
, max_num_matched
, idx
;
4147 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4150 DEBUG_TRACE ("no operand");
4154 max_num_matched
= 0;
4157 /* For each pattern. */
4158 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4161 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4163 /* Most opcodes has much fewer patterns in the list. */
4164 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4166 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4167 if (i
!= 0 && idx
== -1)
4168 /* If nothing has been matched, return the 1st sequence. */
4173 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4174 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4177 if (num_matched
> max_num_matched
)
4179 max_num_matched
= num_matched
;
4184 DEBUG_TRACE ("return with %d", idx
);
4188 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4189 corresponding operands in *INSTR. */
4192 assign_qualifier_sequence (aarch64_inst
*instr
,
4193 const aarch64_opnd_qualifier_t
*qualifiers
)
4196 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4197 gas_assert (num_opnds
);
4198 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4199 instr
->operands
[i
].qualifier
= *qualifiers
;
4202 /* Print operands for the diagnosis purpose. */
4205 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4206 const aarch64_opnd_info
*opnds
)
4210 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4214 /* We regard the opcode operand info more, however we also look into
4215 the inst->operands to support the disassembling of the optional
4217 The two operand code should be the same in all cases, apart from
4218 when the operand can be optional. */
4219 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4220 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4223 /* Generate the operand string in STR. */
4224 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4228 strcat (buf
, i
== 0 ? " " : ",");
4230 /* Append the operand string. */
4235 /* Send to stderr a string as information. */
4238 output_info (const char *format
, ...)
4244 file
= as_where (&line
);
4248 fprintf (stderr
, "%s:%u: ", file
, line
);
4250 fprintf (stderr
, "%s: ", file
);
4252 fprintf (stderr
, _("Info: "));
4253 va_start (args
, format
);
4254 vfprintf (stderr
, format
, args
);
4256 (void) putc ('\n', stderr
);
4259 /* Output one operand error record. */
4262 output_operand_error_record (const operand_error_record
*record
, char *str
)
4264 const aarch64_operand_error
*detail
= &record
->detail
;
4265 int idx
= detail
->index
;
4266 const aarch64_opcode
*opcode
= record
->opcode
;
4267 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4268 : AARCH64_OPND_NIL
);
4270 switch (detail
->kind
)
4272 case AARCH64_OPDE_NIL
:
4276 case AARCH64_OPDE_SYNTAX_ERROR
:
4277 case AARCH64_OPDE_RECOVERABLE
:
4278 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4279 case AARCH64_OPDE_OTHER_ERROR
:
4280 /* Use the prepared error message if there is, otherwise use the
4281 operand description string to describe the error. */
4282 if (detail
->error
!= NULL
)
4285 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4287 as_bad (_("%s at operand %d -- `%s'"),
4288 detail
->error
, idx
+ 1, str
);
4292 gas_assert (idx
>= 0);
4293 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4294 aarch64_get_operand_desc (opd_code
), str
);
4298 case AARCH64_OPDE_INVALID_VARIANT
:
4299 as_bad (_("operand mismatch -- `%s'"), str
);
4300 if (verbose_error_p
)
4302 /* We will try to correct the erroneous instruction and also provide
4303 more information e.g. all other valid variants.
4305 The string representation of the corrected instruction and other
4306 valid variants are generated by
4308 1) obtaining the intermediate representation of the erroneous
4310 2) manipulating the IR, e.g. replacing the operand qualifier;
4311 3) printing out the instruction by calling the printer functions
4312 shared with the disassembler.
4314 The limitation of this method is that the exact input assembly
4315 line cannot be accurately reproduced in some cases, for example an
4316 optional operand present in the actual assembly line will be
4317 omitted in the output; likewise for the optional syntax rules,
4318 e.g. the # before the immediate. Another limitation is that the
4319 assembly symbols and relocation operations in the assembly line
4320 currently cannot be printed out in the error report. Last but not
4321 least, when there is other error(s) co-exist with this error, the
4322 'corrected' instruction may be still incorrect, e.g. given
4323 'ldnp h0,h1,[x0,#6]!'
4324 this diagnosis will provide the version:
4325 'ldnp s0,s1,[x0,#6]!'
4326 which is still not right. */
4327 size_t len
= strlen (get_mnemonic_name (str
));
4331 aarch64_inst
*inst_base
= &inst
.base
;
4332 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4335 reset_aarch64_instruction (&inst
);
4336 inst_base
->opcode
= opcode
;
4338 /* Reset the error report so that there is no side effect on the
4339 following operand parsing. */
4340 init_operand_error_report ();
4343 result
= parse_operands (str
+ len
, opcode
)
4344 && programmer_friendly_fixup (&inst
);
4345 gas_assert (result
);
4346 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4348 gas_assert (!result
);
4350 /* Find the most matched qualifier sequence. */
4351 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4352 gas_assert (qlf_idx
> -1);
4354 /* Assign the qualifiers. */
4355 assign_qualifier_sequence (inst_base
,
4356 opcode
->qualifiers_list
[qlf_idx
]);
4358 /* Print the hint. */
4359 output_info (_(" did you mean this?"));
4360 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4361 print_operands (buf
, opcode
, inst_base
->operands
);
4362 output_info (_(" %s"), buf
);
4364 /* Print out other variant(s) if there is any. */
4366 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4367 output_info (_(" other valid variant(s):"));
4369 /* For each pattern. */
4370 qualifiers_list
= opcode
->qualifiers_list
;
4371 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4373 /* Most opcodes has much fewer patterns in the list.
4374 First NIL qualifier indicates the end in the list. */
4375 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4380 /* Mnemonics name. */
4381 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4383 /* Assign the qualifiers. */
4384 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4386 /* Print instruction. */
4387 print_operands (buf
, opcode
, inst_base
->operands
);
4389 output_info (_(" %s"), buf
);
4395 case AARCH64_OPDE_OUT_OF_RANGE
:
4396 if (detail
->data
[0] != detail
->data
[1])
4397 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4398 detail
->error
? detail
->error
: _("immediate value"),
4399 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4401 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4402 detail
->error
? detail
->error
: _("immediate value"),
4403 detail
->data
[0], idx
+ 1, str
);
4406 case AARCH64_OPDE_REG_LIST
:
4407 if (detail
->data
[0] == 1)
4408 as_bad (_("invalid number of registers in the list; "
4409 "only 1 register is expected at operand %d -- `%s'"),
4412 as_bad (_("invalid number of registers in the list; "
4413 "%d registers are expected at operand %d -- `%s'"),
4414 detail
->data
[0], idx
+ 1, str
);
4417 case AARCH64_OPDE_UNALIGNED
:
4418 as_bad (_("immediate value should be a multiple of "
4419 "%d at operand %d -- `%s'"),
4420 detail
->data
[0], idx
+ 1, str
);
4429 /* Process and output the error message about the operand mismatching.
4431 When this function is called, the operand error information had
4432 been collected for an assembly line and there will be multiple
4433 errors in the case of mulitple instruction templates; output the
4434 error message that most closely describes the problem. */
4437 output_operand_error_report (char *str
)
4439 int largest_error_pos
;
4440 const char *msg
= NULL
;
4441 enum aarch64_operand_error_kind kind
;
4442 operand_error_record
*curr
;
4443 operand_error_record
*head
= operand_error_report
.head
;
4444 operand_error_record
*record
= NULL
;
4446 /* No error to report. */
4450 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4452 /* Only one error. */
4453 if (head
== operand_error_report
.tail
)
4455 DEBUG_TRACE ("single opcode entry with error kind: %s",
4456 operand_mismatch_kind_names
[head
->detail
.kind
]);
4457 output_operand_error_record (head
, str
);
4461 /* Find the error kind of the highest severity. */
4462 DEBUG_TRACE ("multiple opcode entres with error kind");
4463 kind
= AARCH64_OPDE_NIL
;
4464 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4466 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4467 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4468 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4469 kind
= curr
->detail
.kind
;
4471 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4473 /* Pick up one of errors of KIND to report. */
4474 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4475 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4477 if (curr
->detail
.kind
!= kind
)
4479 /* If there are multiple errors, pick up the one with the highest
4480 mismatching operand index. In the case of multiple errors with
4481 the equally highest operand index, pick up the first one or the
4482 first one with non-NULL error message. */
4483 if (curr
->detail
.index
> largest_error_pos
4484 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4485 && curr
->detail
.error
!= NULL
))
4487 largest_error_pos
= curr
->detail
.index
;
4489 msg
= record
->detail
.error
;
4493 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4494 DEBUG_TRACE ("Pick up error kind %s to report",
4495 operand_mismatch_kind_names
[record
->detail
.kind
]);
4498 output_operand_error_record (record
, str
);
4501 /* Write an AARCH64 instruction to buf - always little-endian. */
4503 put_aarch64_insn (char *buf
, uint32_t insn
)
4505 unsigned char *where
= (unsigned char *) buf
;
4507 where
[1] = insn
>> 8;
4508 where
[2] = insn
>> 16;
4509 where
[3] = insn
>> 24;
4513 get_aarch64_insn (char *buf
)
4515 unsigned char *where
= (unsigned char *) buf
;
4517 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4522 output_inst (struct aarch64_inst
*new_inst
)
4526 to
= frag_more (INSN_SIZE
);
4528 frag_now
->tc_frag_data
.recorded
= 1;
4530 put_aarch64_insn (to
, inst
.base
.value
);
4532 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4534 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4535 INSN_SIZE
, &inst
.reloc
.exp
,
4538 DEBUG_TRACE ("Prepared relocation fix up");
4539 /* Don't check the addend value against the instruction size,
4540 that's the job of our code in md_apply_fix(). */
4541 fixp
->fx_no_overflow
= 1;
4542 if (new_inst
!= NULL
)
4543 fixp
->tc_fix_data
.inst
= new_inst
;
4544 if (aarch64_gas_internal_fixup_p ())
4546 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4547 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4548 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4552 dwarf2_emit_insn (INSN_SIZE
);
4555 /* Link together opcodes of the same name. */
4559 aarch64_opcode
*opcode
;
4560 struct templates
*next
;
4563 typedef struct templates templates
;
4566 lookup_mnemonic (const char *start
, int len
)
4568 templates
*templ
= NULL
;
4570 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4574 /* Subroutine of md_assemble, responsible for looking up the primary
4575 opcode from the mnemonic the user wrote. STR points to the
4576 beginning of the mnemonic. */
4579 opcode_lookup (char **str
)
4582 const aarch64_cond
*cond
;
4586 /* Scan up to the end of the mnemonic, which must end in white space,
4587 '.', or end of string. */
4588 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4595 inst
.cond
= COND_ALWAYS
;
4597 /* Handle a possible condition. */
4600 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4603 inst
.cond
= cond
->value
;
4617 if (inst
.cond
== COND_ALWAYS
)
4619 /* Look for unaffixed mnemonic. */
4620 return lookup_mnemonic (base
, len
);
4624 /* append ".c" to mnemonic if conditional */
4625 memcpy (condname
, base
, len
);
4626 memcpy (condname
+ len
, ".c", 2);
4629 return lookup_mnemonic (base
, len
);
4635 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4636 to a corresponding operand qualifier. */
4638 static inline aarch64_opnd_qualifier_t
4639 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4641 /* Element size in bytes indexed by vector_el_type. */
4642 const unsigned char ele_size
[5]
4644 const unsigned int ele_base
[5] =
4646 AARCH64_OPND_QLF_V_8B
,
4647 AARCH64_OPND_QLF_V_2H
,
4648 AARCH64_OPND_QLF_V_2S
,
4649 AARCH64_OPND_QLF_V_1D
,
4650 AARCH64_OPND_QLF_V_1Q
4653 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4654 goto vectype_conversion_fail
;
4656 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4658 if (vectype
->defined
& NTA_HASINDEX
)
4659 /* Vector element register. */
4660 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4663 /* Vector register. */
4664 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4667 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4668 goto vectype_conversion_fail
;
4670 /* The conversion is by calculating the offset from the base operand
4671 qualifier for the vector type. The operand qualifiers are regular
4672 enough that the offset can established by shifting the vector width by
4673 a vector-type dependent amount. */
4675 if (vectype
->type
== NT_b
)
4677 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4679 else if (vectype
->type
>= NT_d
)
4684 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4685 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4686 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4690 vectype_conversion_fail
:
4691 first_error (_("bad vector arrangement type"));
4692 return AARCH64_OPND_QLF_NIL
;
4695 /* Process an optional operand that is found omitted from the assembly line.
4696 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4697 instruction's opcode entry while IDX is the index of this omitted operand.
4701 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4702 int idx
, aarch64_opnd_info
*operand
)
4704 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4705 gas_assert (optional_operand_p (opcode
, idx
));
4706 gas_assert (!operand
->present
);
4710 case AARCH64_OPND_Rd
:
4711 case AARCH64_OPND_Rn
:
4712 case AARCH64_OPND_Rm
:
4713 case AARCH64_OPND_Rt
:
4714 case AARCH64_OPND_Rt2
:
4715 case AARCH64_OPND_Rs
:
4716 case AARCH64_OPND_Ra
:
4717 case AARCH64_OPND_Rt_SYS
:
4718 case AARCH64_OPND_Rd_SP
:
4719 case AARCH64_OPND_Rn_SP
:
4720 case AARCH64_OPND_Fd
:
4721 case AARCH64_OPND_Fn
:
4722 case AARCH64_OPND_Fm
:
4723 case AARCH64_OPND_Fa
:
4724 case AARCH64_OPND_Ft
:
4725 case AARCH64_OPND_Ft2
:
4726 case AARCH64_OPND_Sd
:
4727 case AARCH64_OPND_Sn
:
4728 case AARCH64_OPND_Sm
:
4729 case AARCH64_OPND_Vd
:
4730 case AARCH64_OPND_Vn
:
4731 case AARCH64_OPND_Vm
:
4732 case AARCH64_OPND_VdD1
:
4733 case AARCH64_OPND_VnD1
:
4734 operand
->reg
.regno
= default_value
;
4737 case AARCH64_OPND_Ed
:
4738 case AARCH64_OPND_En
:
4739 case AARCH64_OPND_Em
:
4740 operand
->reglane
.regno
= default_value
;
4743 case AARCH64_OPND_IDX
:
4744 case AARCH64_OPND_BIT_NUM
:
4745 case AARCH64_OPND_IMMR
:
4746 case AARCH64_OPND_IMMS
:
4747 case AARCH64_OPND_SHLL_IMM
:
4748 case AARCH64_OPND_IMM_VLSL
:
4749 case AARCH64_OPND_IMM_VLSR
:
4750 case AARCH64_OPND_CCMP_IMM
:
4751 case AARCH64_OPND_FBITS
:
4752 case AARCH64_OPND_UIMM4
:
4753 case AARCH64_OPND_UIMM3_OP1
:
4754 case AARCH64_OPND_UIMM3_OP2
:
4755 case AARCH64_OPND_IMM
:
4756 case AARCH64_OPND_WIDTH
:
4757 case AARCH64_OPND_UIMM7
:
4758 case AARCH64_OPND_NZCV
:
4759 operand
->imm
.value
= default_value
;
4762 case AARCH64_OPND_EXCEPTION
:
4763 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4766 case AARCH64_OPND_BARRIER_ISB
:
4767 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4774 /* Process the relocation type for move wide instructions.
4775 Return TRUE on success; otherwise return FALSE. */
4778 process_movw_reloc_info (void)
4783 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4785 if (inst
.base
.opcode
->op
== OP_MOVK
)
4786 switch (inst
.reloc
.type
)
4788 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4789 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4790 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4791 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4792 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4793 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4794 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4796 (_("the specified relocation type is not allowed for MOVK"));
4802 switch (inst
.reloc
.type
)
4804 case BFD_RELOC_AARCH64_MOVW_G0
:
4805 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4806 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4807 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4808 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
4809 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
4810 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
4811 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4812 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4813 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4814 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4817 case BFD_RELOC_AARCH64_MOVW_G1
:
4818 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4819 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4820 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4821 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
4822 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4823 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
4824 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4825 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4826 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4827 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4830 case BFD_RELOC_AARCH64_MOVW_G2
:
4831 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4832 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4833 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4834 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4837 set_fatal_syntax_error
4838 (_("the specified relocation type is not allowed for 32-bit "
4844 case BFD_RELOC_AARCH64_MOVW_G3
:
4847 set_fatal_syntax_error
4848 (_("the specified relocation type is not allowed for 32-bit "
4855 /* More cases should be added when more MOVW-related relocation types
4856 are supported in GAS. */
4857 gas_assert (aarch64_gas_internal_fixup_p ());
4858 /* The shift amount should have already been set by the parser. */
4861 inst
.base
.operands
[1].shifter
.amount
= shift
;
4865 /* A primitive log caculator. */
4867 static inline unsigned int
4868 get_logsz (unsigned int size
)
4870 const unsigned char ls
[16] =
4871 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4877 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4878 return ls
[size
- 1];
4881 /* Determine and return the real reloc type code for an instruction
4882 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4884 static inline bfd_reloc_code_real_type
4885 ldst_lo12_determine_real_reloc_type (void)
4888 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4889 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4891 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4893 BFD_RELOC_AARCH64_LDST8_LO12
,
4894 BFD_RELOC_AARCH64_LDST16_LO12
,
4895 BFD_RELOC_AARCH64_LDST32_LO12
,
4896 BFD_RELOC_AARCH64_LDST64_LO12
,
4897 BFD_RELOC_AARCH64_LDST128_LO12
4900 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4901 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4902 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4903 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4904 BFD_RELOC_AARCH64_NONE
4907 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4908 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4909 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4910 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4911 BFD_RELOC_AARCH64_NONE
4915 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4916 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4918 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4919 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4921 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4923 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4925 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4927 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4928 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4929 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4930 gas_assert (logsz
<= 3);
4932 gas_assert (logsz
<= 4);
4934 /* In reloc.c, these pseudo relocation types should be defined in similar
4935 order as above reloc_ldst_lo12 array. Because the array index calcuation
4936 below relies on this. */
4937 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4940 /* Check whether a register list REGINFO is valid. The registers must be
4941 numbered in increasing order (modulo 32), in increments of one or two.
4943 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4946 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4949 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4951 uint32_t i
, nb_regs
, prev_regno
, incr
;
4953 nb_regs
= 1 + (reginfo
& 0x3);
4955 prev_regno
= reginfo
& 0x1f;
4956 incr
= accept_alternate
? 2 : 1;
4958 for (i
= 1; i
< nb_regs
; ++i
)
4960 uint32_t curr_regno
;
4962 curr_regno
= reginfo
& 0x1f;
4963 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4965 prev_regno
= curr_regno
;
4971 /* Generic instruction operand parser. This does no encoding and no
4972 semantic validation; it merely squirrels values away in the inst
4973 structure. Returns TRUE or FALSE depending on whether the
4974 specified grammar matched. */
4977 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4980 char *backtrack_pos
= 0;
4981 const enum aarch64_opnd
*operands
= opcode
->operands
;
4982 aarch64_reg_type imm_reg_type
;
4985 skip_whitespace (str
);
4987 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
4989 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4992 int isreg32
, isregzero
;
4993 int comma_skipped_p
= 0;
4994 aarch64_reg_type rtype
;
4995 struct vector_type_el vectype
;
4996 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4998 DEBUG_TRACE ("parse operand %d", i
);
5000 /* Assign the operand code. */
5001 info
->type
= operands
[i
];
5003 if (optional_operand_p (opcode
, i
))
5005 /* Remember where we are in case we need to backtrack. */
5006 gas_assert (!backtrack_pos
);
5007 backtrack_pos
= str
;
5010 /* Expect comma between operands; the backtrack mechanizm will take
5011 care of cases of omitted optional operand. */
5012 if (i
> 0 && ! skip_past_char (&str
, ','))
5014 set_syntax_error (_("comma expected between operands"));
5018 comma_skipped_p
= 1;
5020 switch (operands
[i
])
5022 case AARCH64_OPND_Rd
:
5023 case AARCH64_OPND_Rn
:
5024 case AARCH64_OPND_Rm
:
5025 case AARCH64_OPND_Rt
:
5026 case AARCH64_OPND_Rt2
:
5027 case AARCH64_OPND_Rs
:
5028 case AARCH64_OPND_Ra
:
5029 case AARCH64_OPND_Rt_SYS
:
5030 case AARCH64_OPND_PAIRREG
:
5031 po_int_reg_or_fail (1, 0);
5034 case AARCH64_OPND_Rd_SP
:
5035 case AARCH64_OPND_Rn_SP
:
5036 po_int_reg_or_fail (0, 1);
5039 case AARCH64_OPND_Rm_EXT
:
5040 case AARCH64_OPND_Rm_SFT
:
5041 po_misc_or_fail (parse_shifter_operand
5042 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5044 : SHIFTED_LOGIC_IMM
)));
5045 if (!info
->shifter
.operator_present
)
5047 /* Default to LSL if not present. Libopcodes prefers shifter
5048 kind to be explicit. */
5049 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5050 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5051 /* For Rm_EXT, libopcodes will carry out further check on whether
5052 or not stack pointer is used in the instruction (Recall that
5053 "the extend operator is not optional unless at least one of
5054 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5058 case AARCH64_OPND_Fd
:
5059 case AARCH64_OPND_Fn
:
5060 case AARCH64_OPND_Fm
:
5061 case AARCH64_OPND_Fa
:
5062 case AARCH64_OPND_Ft
:
5063 case AARCH64_OPND_Ft2
:
5064 case AARCH64_OPND_Sd
:
5065 case AARCH64_OPND_Sn
:
5066 case AARCH64_OPND_Sm
:
5067 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5068 if (val
== PARSE_FAIL
)
5070 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5073 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5075 info
->reg
.regno
= val
;
5076 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5079 case AARCH64_OPND_Vd
:
5080 case AARCH64_OPND_Vn
:
5081 case AARCH64_OPND_Vm
:
5082 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5083 if (val
== PARSE_FAIL
)
5085 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5088 if (vectype
.defined
& NTA_HASINDEX
)
5091 info
->reg
.regno
= val
;
5092 info
->qualifier
= vectype_to_qualifier (&vectype
);
5093 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5097 case AARCH64_OPND_VdD1
:
5098 case AARCH64_OPND_VnD1
:
5099 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5100 if (val
== PARSE_FAIL
)
5102 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5105 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5107 set_fatal_syntax_error
5108 (_("the top half of a 128-bit FP/SIMD register is expected"));
5111 info
->reg
.regno
= val
;
5112 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5113 here; it is correct for the purpose of encoding/decoding since
5114 only the register number is explicitly encoded in the related
5115 instructions, although this appears a bit hacky. */
5116 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5119 case AARCH64_OPND_Ed
:
5120 case AARCH64_OPND_En
:
5121 case AARCH64_OPND_Em
:
5122 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5123 if (val
== PARSE_FAIL
)
5125 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5128 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5131 info
->reglane
.regno
= val
;
5132 info
->reglane
.index
= vectype
.index
;
5133 info
->qualifier
= vectype_to_qualifier (&vectype
);
5134 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5138 case AARCH64_OPND_LVn
:
5139 case AARCH64_OPND_LVt
:
5140 case AARCH64_OPND_LVt_AL
:
5141 case AARCH64_OPND_LEt
:
5142 if ((val
= parse_vector_reg_list (&str
, REG_TYPE_VN
,
5143 &vectype
)) == PARSE_FAIL
)
5145 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5147 set_fatal_syntax_error (_("invalid register list"));
5150 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5151 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5152 if (operands
[i
] == AARCH64_OPND_LEt
)
5154 if (!(vectype
.defined
& NTA_HASINDEX
))
5156 info
->reglist
.has_index
= 1;
5157 info
->reglist
.index
= vectype
.index
;
5159 else if (!(vectype
.defined
& NTA_HASTYPE
))
5161 info
->qualifier
= vectype_to_qualifier (&vectype
);
5162 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5166 case AARCH64_OPND_Cn
:
5167 case AARCH64_OPND_Cm
:
5168 po_reg_or_fail (REG_TYPE_CN
);
5171 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5174 inst
.base
.operands
[i
].reg
.regno
= val
;
5177 case AARCH64_OPND_SHLL_IMM
:
5178 case AARCH64_OPND_IMM_VLSR
:
5179 po_imm_or_fail (1, 64);
5180 info
->imm
.value
= val
;
5183 case AARCH64_OPND_CCMP_IMM
:
5184 case AARCH64_OPND_FBITS
:
5185 case AARCH64_OPND_UIMM4
:
5186 case AARCH64_OPND_UIMM3_OP1
:
5187 case AARCH64_OPND_UIMM3_OP2
:
5188 case AARCH64_OPND_IMM_VLSL
:
5189 case AARCH64_OPND_IMM
:
5190 case AARCH64_OPND_WIDTH
:
5191 po_imm_nc_or_fail ();
5192 info
->imm
.value
= val
;
5195 case AARCH64_OPND_UIMM7
:
5196 po_imm_or_fail (0, 127);
5197 info
->imm
.value
= val
;
5200 case AARCH64_OPND_IDX
:
5201 case AARCH64_OPND_BIT_NUM
:
5202 case AARCH64_OPND_IMMR
:
5203 case AARCH64_OPND_IMMS
:
5204 po_imm_or_fail (0, 63);
5205 info
->imm
.value
= val
;
5208 case AARCH64_OPND_IMM0
:
5209 po_imm_nc_or_fail ();
5212 set_fatal_syntax_error (_("immediate zero expected"));
5215 info
->imm
.value
= 0;
5218 case AARCH64_OPND_FPIMM0
:
5221 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5222 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5223 it is probably not worth the effort to support it. */
5224 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5226 && !(res2
= parse_constant_immediate (&str
, &val
,
5229 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5231 info
->imm
.value
= 0;
5232 info
->imm
.is_fp
= 1;
5235 set_fatal_syntax_error (_("immediate zero expected"));
5239 case AARCH64_OPND_IMM_MOV
:
5242 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5243 reg_name_p (str
, REG_TYPE_VN
))
5246 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5248 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5249 later. fix_mov_imm_insn will try to determine a machine
5250 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5251 message if the immediate cannot be moved by a single
5253 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5254 inst
.base
.operands
[i
].skip
= 1;
5258 case AARCH64_OPND_SIMD_IMM
:
5259 case AARCH64_OPND_SIMD_IMM_SFT
:
5260 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5262 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5264 /* need_libopcodes_p */ 1,
5267 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5268 shift, we don't check it here; we leave the checking to
5269 the libopcodes (operand_general_constraint_met_p). By
5270 doing this, we achieve better diagnostics. */
5271 if (skip_past_comma (&str
)
5272 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5274 if (!info
->shifter
.operator_present
5275 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5277 /* Default to LSL if not present. Libopcodes prefers shifter
5278 kind to be explicit. */
5279 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5280 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5284 case AARCH64_OPND_FPIMM
:
5285 case AARCH64_OPND_SIMD_FPIMM
:
5289 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5291 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5295 set_fatal_syntax_error (_("invalid floating-point constant"));
5298 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5299 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5303 case AARCH64_OPND_LIMM
:
5304 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5305 SHIFTED_LOGIC_IMM
));
5306 if (info
->shifter
.operator_present
)
5308 set_fatal_syntax_error
5309 (_("shift not allowed for bitmask immediate"));
5312 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5314 /* need_libopcodes_p */ 1,
5318 case AARCH64_OPND_AIMM
:
5319 if (opcode
->op
== OP_ADD
)
5320 /* ADD may have relocation types. */
5321 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5322 SHIFTED_ARITH_IMM
));
5324 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5325 SHIFTED_ARITH_IMM
));
5326 switch (inst
.reloc
.type
)
5328 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5329 info
->shifter
.amount
= 12;
5331 case BFD_RELOC_UNUSED
:
5332 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5333 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5334 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5335 inst
.reloc
.pc_rel
= 0;
5340 info
->imm
.value
= 0;
5341 if (!info
->shifter
.operator_present
)
5343 /* Default to LSL if not present. Libopcodes prefers shifter
5344 kind to be explicit. */
5345 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5346 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5350 case AARCH64_OPND_HALF
:
5352 /* #<imm16> or relocation. */
5353 int internal_fixup_p
;
5354 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5355 if (internal_fixup_p
)
5356 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5357 skip_whitespace (str
);
5358 if (skip_past_comma (&str
))
5360 /* {, LSL #<shift>} */
5361 if (! aarch64_gas_internal_fixup_p ())
5363 set_fatal_syntax_error (_("can't mix relocation modifier "
5364 "with explicit shift"));
5367 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5370 inst
.base
.operands
[i
].shifter
.amount
= 0;
5371 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5372 inst
.base
.operands
[i
].imm
.value
= 0;
5373 if (! process_movw_reloc_info ())
5378 case AARCH64_OPND_EXCEPTION
:
5379 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5381 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5383 /* need_libopcodes_p */ 0,
5387 case AARCH64_OPND_NZCV
:
5389 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5393 info
->imm
.value
= nzcv
->value
;
5396 po_imm_or_fail (0, 15);
5397 info
->imm
.value
= val
;
5401 case AARCH64_OPND_COND
:
5402 case AARCH64_OPND_COND1
:
5403 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5405 if (info
->cond
== NULL
)
5407 set_syntax_error (_("invalid condition"));
5410 else if (operands
[i
] == AARCH64_OPND_COND1
5411 && (info
->cond
->value
& 0xe) == 0xe)
5413 /* Not allow AL or NV. */
5414 set_default_error ();
5419 case AARCH64_OPND_ADDR_ADRP
:
5420 po_misc_or_fail (parse_adrp (&str
));
5421 /* Clear the value as operand needs to be relocated. */
5422 info
->imm
.value
= 0;
5425 case AARCH64_OPND_ADDR_PCREL14
:
5426 case AARCH64_OPND_ADDR_PCREL19
:
5427 case AARCH64_OPND_ADDR_PCREL21
:
5428 case AARCH64_OPND_ADDR_PCREL26
:
5429 po_misc_or_fail (parse_address_reloc (&str
, info
));
5430 if (!info
->addr
.pcrel
)
5432 set_syntax_error (_("invalid pc-relative address"));
5435 if (inst
.gen_lit_pool
5436 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5438 /* Only permit "=value" in the literal load instructions.
5439 The literal will be generated by programmer_friendly_fixup. */
5440 set_syntax_error (_("invalid use of \"=immediate\""));
5443 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5445 set_syntax_error (_("unrecognized relocation suffix"));
5448 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5450 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5451 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5455 info
->imm
.value
= 0;
5456 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5457 switch (opcode
->iclass
)
5461 /* e.g. CBZ or B.COND */
5462 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5463 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5467 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5468 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5472 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5474 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5475 : BFD_RELOC_AARCH64_JUMP26
;
5478 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5479 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5482 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5483 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5489 inst
.reloc
.pc_rel
= 1;
5493 case AARCH64_OPND_ADDR_SIMPLE
:
5494 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5495 /* [<Xn|SP>{, #<simm>}] */
5496 po_char_or_fail ('[');
5497 po_reg_or_fail (REG_TYPE_R64_SP
);
5498 /* Accept optional ", #0". */
5499 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5500 && skip_past_char (&str
, ','))
5502 skip_past_char (&str
, '#');
5503 if (! skip_past_char (&str
, '0'))
5505 set_fatal_syntax_error
5506 (_("the optional immediate offset can only be 0"));
5510 po_char_or_fail (']');
5511 info
->addr
.base_regno
= val
;
5514 case AARCH64_OPND_ADDR_REGOFF
:
5515 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5516 po_misc_or_fail (parse_address (&str
, info
, 0));
5517 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5518 || !info
->addr
.preind
|| info
->addr
.postind
5519 || info
->addr
.writeback
)
5521 set_syntax_error (_("invalid addressing mode"));
5524 if (!info
->shifter
.operator_present
)
5526 /* Default to LSL if not present. Libopcodes prefers shifter
5527 kind to be explicit. */
5528 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5529 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5531 /* Qualifier to be deduced by libopcodes. */
5534 case AARCH64_OPND_ADDR_SIMM7
:
5535 po_misc_or_fail (parse_address (&str
, info
, 0));
5536 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5537 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5539 set_syntax_error (_("invalid addressing mode"));
5542 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5544 /* need_libopcodes_p */ 1,
5548 case AARCH64_OPND_ADDR_SIMM9
:
5549 case AARCH64_OPND_ADDR_SIMM9_2
:
5550 po_misc_or_fail (parse_address_reloc (&str
, info
));
5551 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5552 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5553 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5554 && info
->addr
.writeback
))
5556 set_syntax_error (_("invalid addressing mode"));
5559 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5561 set_syntax_error (_("relocation not allowed"));
5564 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5566 /* need_libopcodes_p */ 1,
5570 case AARCH64_OPND_ADDR_UIMM12
:
5571 po_misc_or_fail (parse_address_reloc (&str
, info
));
5572 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5573 || !info
->addr
.preind
|| info
->addr
.writeback
)
5575 set_syntax_error (_("invalid addressing mode"));
5578 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5579 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5580 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5582 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5584 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5585 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5586 /* Leave qualifier to be determined by libopcodes. */
5589 case AARCH64_OPND_SIMD_ADDR_POST
:
5590 /* [<Xn|SP>], <Xm|#<amount>> */
5591 po_misc_or_fail (parse_address (&str
, info
, 1));
5592 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5594 set_syntax_error (_("invalid addressing mode"));
5597 if (!info
->addr
.offset
.is_reg
)
5599 if (inst
.reloc
.exp
.X_op
== O_constant
)
5600 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5603 set_fatal_syntax_error
5604 (_("writeback value should be an immediate constant"));
5611 case AARCH64_OPND_SYSREG
:
5612 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5615 set_syntax_error (_("unknown or missing system register name"));
5618 inst
.base
.operands
[i
].sysreg
= val
;
5621 case AARCH64_OPND_PSTATEFIELD
:
5622 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5625 set_syntax_error (_("unknown or missing PSTATE field name"));
5628 inst
.base
.operands
[i
].pstatefield
= val
;
5631 case AARCH64_OPND_SYSREG_IC
:
5632 inst
.base
.operands
[i
].sysins_op
=
5633 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5635 case AARCH64_OPND_SYSREG_DC
:
5636 inst
.base
.operands
[i
].sysins_op
=
5637 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5639 case AARCH64_OPND_SYSREG_AT
:
5640 inst
.base
.operands
[i
].sysins_op
=
5641 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5643 case AARCH64_OPND_SYSREG_TLBI
:
5644 inst
.base
.operands
[i
].sysins_op
=
5645 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5647 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5649 set_fatal_syntax_error ( _("unknown or missing operation name"));
5654 case AARCH64_OPND_BARRIER
:
5655 case AARCH64_OPND_BARRIER_ISB
:
5656 val
= parse_barrier (&str
);
5657 if (val
!= PARSE_FAIL
5658 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5660 /* ISB only accepts options name 'sy'. */
5662 (_("the specified option is not accepted in ISB"));
5663 /* Turn off backtrack as this optional operand is present. */
5667 /* This is an extension to accept a 0..15 immediate. */
5668 if (val
== PARSE_FAIL
)
5669 po_imm_or_fail (0, 15);
5670 info
->barrier
= aarch64_barrier_options
+ val
;
5673 case AARCH64_OPND_PRFOP
:
5674 val
= parse_pldop (&str
);
5675 /* This is an extension to accept a 0..31 immediate. */
5676 if (val
== PARSE_FAIL
)
5677 po_imm_or_fail (0, 31);
5678 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5681 case AARCH64_OPND_BARRIER_PSB
:
5682 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
5683 if (val
== PARSE_FAIL
)
5688 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5691 /* If we get here, this operand was successfully parsed. */
5692 inst
.base
.operands
[i
].present
= 1;
5696 /* The parse routine should already have set the error, but in case
5697 not, set a default one here. */
5699 set_default_error ();
5701 if (! backtrack_pos
)
5702 goto parse_operands_return
;
5705 /* We reach here because this operand is marked as optional, and
5706 either no operand was supplied or the operand was supplied but it
5707 was syntactically incorrect. In the latter case we report an
5708 error. In the former case we perform a few more checks before
5709 dropping through to the code to insert the default operand. */
5711 char *tmp
= backtrack_pos
;
5712 char endchar
= END_OF_INSN
;
5714 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5716 skip_past_char (&tmp
, ',');
5718 if (*tmp
!= endchar
)
5719 /* The user has supplied an operand in the wrong format. */
5720 goto parse_operands_return
;
5722 /* Make sure there is not a comma before the optional operand.
5723 For example the fifth operand of 'sys' is optional:
5725 sys #0,c0,c0,#0, <--- wrong
5726 sys #0,c0,c0,#0 <--- correct. */
5727 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5729 set_fatal_syntax_error
5730 (_("unexpected comma before the omitted optional operand"));
5731 goto parse_operands_return
;
5735 /* Reaching here means we are dealing with an optional operand that is
5736 omitted from the assembly line. */
5737 gas_assert (optional_operand_p (opcode
, i
));
5739 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5741 /* Try again, skipping the optional operand at backtrack_pos. */
5742 str
= backtrack_pos
;
5745 /* Clear any error record after the omitted optional operand has been
5746 successfully handled. */
5750 /* Check if we have parsed all the operands. */
5751 if (*str
!= '\0' && ! error_p ())
5753 /* Set I to the index of the last present operand; this is
5754 for the purpose of diagnostics. */
5755 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5757 set_fatal_syntax_error
5758 (_("unexpected characters following instruction"));
5761 parse_operands_return
:
5765 DEBUG_TRACE ("parsing FAIL: %s - %s",
5766 operand_mismatch_kind_names
[get_error_kind ()],
5767 get_error_message ());
5768 /* Record the operand error properly; this is useful when there
5769 are multiple instruction templates for a mnemonic name, so that
5770 later on, we can select the error that most closely describes
5772 record_operand_error (opcode
, i
, get_error_kind (),
5773 get_error_message ());
5778 DEBUG_TRACE ("parsing SUCCESS");
5783 /* It does some fix-up to provide some programmer friendly feature while
5784 keeping the libopcodes happy, i.e. libopcodes only accepts
5785 the preferred architectural syntax.
5786 Return FALSE if there is any failure; otherwise return TRUE. */
5789 programmer_friendly_fixup (aarch64_instruction
*instr
)
5791 aarch64_inst
*base
= &instr
->base
;
5792 const aarch64_opcode
*opcode
= base
->opcode
;
5793 enum aarch64_op op
= opcode
->op
;
5794 aarch64_opnd_info
*operands
= base
->operands
;
5796 DEBUG_TRACE ("enter");
5798 switch (opcode
->iclass
)
5801 /* TBNZ Xn|Wn, #uimm6, label
5802 Test and Branch Not Zero: conditionally jumps to label if bit number
5803 uimm6 in register Xn is not zero. The bit number implies the width of
5804 the register, which may be written and should be disassembled as Wn if
5805 uimm is less than 32. */
5806 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5808 if (operands
[1].imm
.value
>= 32)
5810 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5814 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5818 /* LDR Wt, label | =value
5819 As a convenience assemblers will typically permit the notation
5820 "=value" in conjunction with the pc-relative literal load instructions
5821 to automatically place an immediate value or symbolic address in a
5822 nearby literal pool and generate a hidden label which references it.
5823 ISREG has been set to 0 in the case of =value. */
5824 if (instr
->gen_lit_pool
5825 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5827 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5828 if (op
== OP_LDRSW_LIT
)
5830 if (instr
->reloc
.exp
.X_op
!= O_constant
5831 && instr
->reloc
.exp
.X_op
!= O_big
5832 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5834 record_operand_error (opcode
, 1,
5835 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5836 _("constant expression expected"));
5839 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5841 record_operand_error (opcode
, 1,
5842 AARCH64_OPDE_OTHER_ERROR
,
5843 _("literal pool insertion failed"));
5851 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5852 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5853 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5854 A programmer-friendly assembler should accept a destination Xd in
5855 place of Wd, however that is not the preferred form for disassembly.
5857 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5858 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5859 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5860 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5865 /* In the 64-bit form, the final register operand is written as Wm
5866 for all but the (possibly omitted) UXTX/LSL and SXTX
5868 As a programmer-friendly assembler, we accept e.g.
5869 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5870 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5871 int idx
= aarch64_operand_index (opcode
->operands
,
5872 AARCH64_OPND_Rm_EXT
);
5873 gas_assert (idx
== 1 || idx
== 2);
5874 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5875 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5876 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5877 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5878 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5879 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5887 DEBUG_TRACE ("exit with SUCCESS");
5891 /* Check for loads and stores that will cause unpredictable behavior. */
5894 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5896 aarch64_inst
*base
= &instr
->base
;
5897 const aarch64_opcode
*opcode
= base
->opcode
;
5898 const aarch64_opnd_info
*opnds
= base
->operands
;
5899 switch (opcode
->iclass
)
5905 /* Loading/storing the base register is unpredictable if writeback. */
5906 if ((aarch64_get_operand_class (opnds
[0].type
)
5907 == AARCH64_OPND_CLASS_INT_REG
)
5908 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5909 && opnds
[1].addr
.base_regno
!= REG_SP
5910 && opnds
[1].addr
.writeback
)
5911 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5914 case ldstnapair_offs
:
5915 case ldstpair_indexed
:
5916 /* Loading/storing the base register is unpredictable if writeback. */
5917 if ((aarch64_get_operand_class (opnds
[0].type
)
5918 == AARCH64_OPND_CLASS_INT_REG
)
5919 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5920 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5921 && opnds
[2].addr
.base_regno
!= REG_SP
5922 && opnds
[2].addr
.writeback
)
5923 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5924 /* Load operations must load different registers. */
5925 if ((opcode
->opcode
& (1 << 22))
5926 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5927 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5934 /* A wrapper function to interface with libopcodes on encoding and
5935 record the error message if there is any.
5937 Return TRUE on success; otherwise return FALSE. */
5940 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5943 aarch64_operand_error error_info
;
5944 error_info
.kind
= AARCH64_OPDE_NIL
;
5945 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5949 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5950 record_operand_error_info (opcode
, &error_info
);
5955 #ifdef DEBUG_AARCH64
5957 dump_opcode_operands (const aarch64_opcode
*opcode
)
5960 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5962 aarch64_verbose ("\t\t opnd%d: %s", i
,
5963 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5964 ? aarch64_get_operand_name (opcode
->operands
[i
])
5965 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5969 #endif /* DEBUG_AARCH64 */
5971 /* This is the guts of the machine-dependent assembler. STR points to a
5972 machine dependent instruction. This function is supposed to emit
5973 the frags/bytes it assembles to. */
5976 md_assemble (char *str
)
5979 templates
*template;
5980 aarch64_opcode
*opcode
;
5981 aarch64_inst
*inst_base
;
5982 unsigned saved_cond
;
5984 /* Align the previous label if needed. */
5985 if (last_label_seen
!= NULL
)
5987 symbol_set_frag (last_label_seen
, frag_now
);
5988 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5989 S_SET_SEGMENT (last_label_seen
, now_seg
);
5992 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5994 DEBUG_TRACE ("\n\n");
5995 DEBUG_TRACE ("==============================");
5996 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5998 template = opcode_lookup (&p
);
6001 /* It wasn't an instruction, but it might be a register alias of
6002 the form alias .req reg directive. */
6003 if (!create_register_alias (str
, p
))
6004 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6009 skip_whitespace (p
);
6012 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6013 get_mnemonic_name (str
), str
);
6017 init_operand_error_report ();
6019 /* Sections are assumed to start aligned. In executable section, there is no
6020 MAP_DATA symbol pending. So we only align the address during
6021 MAP_DATA --> MAP_INSN transition.
6022 For other sections, this is not guaranteed. */
6023 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6024 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6025 frag_align_code (2, 0);
6027 saved_cond
= inst
.cond
;
6028 reset_aarch64_instruction (&inst
);
6029 inst
.cond
= saved_cond
;
6031 /* Iterate through all opcode entries with the same mnemonic name. */
6034 opcode
= template->opcode
;
6036 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6037 #ifdef DEBUG_AARCH64
6039 dump_opcode_operands (opcode
);
6040 #endif /* DEBUG_AARCH64 */
6042 mapping_state (MAP_INSN
);
6044 inst_base
= &inst
.base
;
6045 inst_base
->opcode
= opcode
;
6047 /* Truly conditionally executed instructions, e.g. b.cond. */
6048 if (opcode
->flags
& F_COND
)
6050 gas_assert (inst
.cond
!= COND_ALWAYS
);
6051 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6052 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6054 else if (inst
.cond
!= COND_ALWAYS
)
6056 /* It shouldn't arrive here, where the assembly looks like a
6057 conditional instruction but the found opcode is unconditional. */
6062 if (parse_operands (p
, opcode
)
6063 && programmer_friendly_fixup (&inst
)
6064 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6066 /* Check that this instruction is supported for this CPU. */
6067 if (!opcode
->avariant
6068 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6070 as_bad (_("selected processor does not support `%s'"), str
);
6074 warn_unpredictable_ldst (&inst
, str
);
6076 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6077 || !inst
.reloc
.need_libopcodes_p
)
6081 /* If there is relocation generated for the instruction,
6082 store the instruction information for the future fix-up. */
6083 struct aarch64_inst
*copy
;
6084 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6085 copy
= XNEW (struct aarch64_inst
);
6086 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6092 template = template->next
;
6093 if (template != NULL
)
6095 reset_aarch64_instruction (&inst
);
6096 inst
.cond
= saved_cond
;
6099 while (template != NULL
);
6101 /* Issue the error messages if any. */
6102 output_operand_error_report (str
);
6105 /* Various frobbings of labels and their addresses. */
6108 aarch64_start_line_hook (void)
6110 last_label_seen
= NULL
;
6114 aarch64_frob_label (symbolS
* sym
)
6116 last_label_seen
= sym
;
6118 dwarf2_emit_label (sym
);
6122 aarch64_data_in_code (void)
6124 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6126 *input_line_pointer
= '/';
6127 input_line_pointer
+= 5;
6128 *input_line_pointer
= 0;
6136 aarch64_canonicalize_symbol_name (char *name
)
6140 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6141 *(name
+ len
- 5) = 0;
6146 /* Table of all register names defined by default. The user can
6147 define additional names with .req. Note that all register names
6148 should appear in both upper and lowercase variants. Some registers
6149 also have mixed-case names. */
6151 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6152 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6153 #define REGSET31(p,t) \
6154 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6155 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6156 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6157 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6158 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6159 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6160 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6161 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6162 #define REGSET(p,t) \
6163 REGSET31(p,t), REGNUM(p,31,t)
6165 /* These go into aarch64_reg_hsh hash-table. */
6166 static const reg_entry reg_names
[] = {
6167 /* Integer registers. */
6168 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6169 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6171 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6172 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6174 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6175 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6177 /* Coprocessor register numbers. */
6178 REGSET (c
, CN
), REGSET (C
, CN
),
6180 /* Floating-point single precision registers. */
6181 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6183 /* Floating-point double precision registers. */
6184 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6186 /* Floating-point half precision registers. */
6187 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6189 /* Floating-point byte precision registers. */
6190 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6192 /* Floating-point quad precision registers. */
6193 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6195 /* FP/SIMD registers. */
6196 REGSET (v
, VN
), REGSET (V
, VN
),
6211 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6212 static const asm_nzcv nzcv_names
[] = {
6213 {"nzcv", B (n
, z
, c
, v
)},
6214 {"nzcV", B (n
, z
, c
, V
)},
6215 {"nzCv", B (n
, z
, C
, v
)},
6216 {"nzCV", B (n
, z
, C
, V
)},
6217 {"nZcv", B (n
, Z
, c
, v
)},
6218 {"nZcV", B (n
, Z
, c
, V
)},
6219 {"nZCv", B (n
, Z
, C
, v
)},
6220 {"nZCV", B (n
, Z
, C
, V
)},
6221 {"Nzcv", B (N
, z
, c
, v
)},
6222 {"NzcV", B (N
, z
, c
, V
)},
6223 {"NzCv", B (N
, z
, C
, v
)},
6224 {"NzCV", B (N
, z
, C
, V
)},
6225 {"NZcv", B (N
, Z
, c
, v
)},
6226 {"NZcV", B (N
, Z
, c
, V
)},
6227 {"NZCv", B (N
, Z
, C
, v
)},
6228 {"NZCV", B (N
, Z
, C
, V
)}
6241 /* MD interface: bits in the object file. */
6243 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6244 for use in the a.out file, and stores them in the array pointed to by buf.
6245 This knows about the endian-ness of the target machine and does
6246 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6247 2 (short) and 4 (long) Floating numbers are put out as a series of
6248 LITTLENUMS (shorts, here at least). */
6251 md_number_to_chars (char *buf
, valueT val
, int n
)
6253 if (target_big_endian
)
6254 number_to_chars_bigendian (buf
, val
, n
);
6256 number_to_chars_littleendian (buf
, val
, n
);
6259 /* MD interface: Sections. */
6261 /* Estimate the size of a frag before relaxing. Assume everything fits in
6265 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6271 /* Round up a section size to the appropriate boundary. */
6274 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6279 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6280 of an rs_align_code fragment.
6282 Here we fill the frag with the appropriate info for padding the
6283 output stream. The resulting frag will consist of a fixed (fr_fix)
6284 and of a repeating (fr_var) part.
6286 The fixed content is always emitted before the repeating content and
6287 these two parts are used as follows in constructing the output:
6288 - the fixed part will be used to align to a valid instruction word
6289 boundary, in case that we start at a misaligned address; as no
6290 executable instruction can live at the misaligned location, we
6291 simply fill with zeros;
6292 - the variable part will be used to cover the remaining padding and
6293 we fill using the AArch64 NOP instruction.
6295 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6296 enough storage space for up to 3 bytes for padding the back to a valid
6297 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6300 aarch64_handle_align (fragS
* fragP
)
6302 /* NOP = d503201f */
6303 /* AArch64 instructions are always little-endian. */
6304 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6306 int bytes
, fix
, noop_size
;
6309 if (fragP
->fr_type
!= rs_align_code
)
6312 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6313 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6316 gas_assert (fragP
->tc_frag_data
.recorded
);
6319 noop_size
= sizeof (aarch64_noop
);
6321 fix
= bytes
& (noop_size
- 1);
6325 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6329 fragP
->fr_fix
+= fix
;
6333 memcpy (p
, aarch64_noop
, noop_size
);
6334 fragP
->fr_var
= noop_size
;
6337 /* Perform target specific initialisation of a frag.
6338 Note - despite the name this initialisation is not done when the frag
6339 is created, but only when its type is assigned. A frag can be created
6340 and used a long time before its type is set, so beware of assuming that
6341 this initialisationis performed first. */
6345 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6346 int max_chars ATTRIBUTE_UNUSED
)
6350 #else /* OBJ_ELF is defined. */
6352 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6354 /* Record a mapping symbol for alignment frags. We will delete this
6355 later if the alignment ends up empty. */
6356 if (!fragP
->tc_frag_data
.recorded
)
6357 fragP
->tc_frag_data
.recorded
= 1;
6359 switch (fragP
->fr_type
)
6363 mapping_state_2 (MAP_DATA
, max_chars
);
6366 /* PR 20364: We can get alignment frags in code sections,
6367 so do not just assume that we should use the MAP_DATA state. */
6368 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
6371 mapping_state_2 (MAP_INSN
, max_chars
);
6378 /* Initialize the DWARF-2 unwind information for this procedure. */
6381 tc_aarch64_frame_initial_instructions (void)
6383 cfi_add_CFA_def_cfa (REG_SP
, 0);
6385 #endif /* OBJ_ELF */
6387 /* Convert REGNAME to a DWARF-2 register number. */
6390 tc_aarch64_regname_to_dw2regnum (char *regname
)
6392 const reg_entry
*reg
= parse_reg (®name
);
6398 case REG_TYPE_SP_32
:
6399 case REG_TYPE_SP_64
:
6409 return reg
->number
+ 64;
6417 /* Implement DWARF2_ADDR_SIZE. */
6420 aarch64_dwarf2_addr_size (void)
6422 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6426 return bfd_arch_bits_per_address (stdoutput
) / 8;
6429 /* MD interface: Symbol and relocation handling. */
6431 /* Return the address within the segment that a PC-relative fixup is
6432 relative to. For AArch64 PC-relative fixups applied to instructions
6433 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6436 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6438 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6440 /* If this is pc-relative and we are going to emit a relocation
6441 then we just want to put out any pipeline compensation that the linker
6442 will need. Otherwise we want to use the calculated base. */
6444 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6445 || aarch64_force_relocation (fixP
)))
6448 /* AArch64 should be consistent for all pc-relative relocations. */
6449 return base
+ AARCH64_PCREL_OFFSET
;
6452 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6453 Otherwise we have no need to default values of symbols. */
6456 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6459 if (name
[0] == '_' && name
[1] == 'G'
6460 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6464 if (symbol_find (name
))
6465 as_bad (_("GOT already in the symbol table"));
6467 GOT_symbol
= symbol_new (name
, undefined_section
,
6468 (valueT
) 0, &zero_address_frag
);
6478 /* Return non-zero if the indicated VALUE has overflowed the maximum
6479 range expressible by a unsigned number with the indicated number of
6483 unsigned_overflow (valueT value
, unsigned bits
)
6486 if (bits
>= sizeof (valueT
) * 8)
6488 lim
= (valueT
) 1 << bits
;
6489 return (value
>= lim
);
6493 /* Return non-zero if the indicated VALUE has overflowed the maximum
6494 range expressible by an signed number with the indicated number of
6498 signed_overflow (offsetT value
, unsigned bits
)
6501 if (bits
>= sizeof (offsetT
) * 8)
6503 lim
= (offsetT
) 1 << (bits
- 1);
6504 return (value
< -lim
|| value
>= lim
);
6507 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6508 unsigned immediate offset load/store instruction, try to encode it as
6509 an unscaled, 9-bit, signed immediate offset load/store instruction.
6510 Return TRUE if it is successful; otherwise return FALSE.
6512 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6513 in response to the standard LDR/STR mnemonics when the immediate offset is
6514 unambiguous, i.e. when it is negative or unaligned. */
6517 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6520 enum aarch64_op new_op
;
6521 const aarch64_opcode
*new_opcode
;
6523 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6525 switch (instr
->opcode
->op
)
6527 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6528 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6529 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6530 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6531 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6532 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6533 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6534 case OP_STR_POS
: new_op
= OP_STUR
; break;
6535 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6536 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6537 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6538 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6539 default: new_op
= OP_NIL
; break;
6542 if (new_op
== OP_NIL
)
6545 new_opcode
= aarch64_get_opcode (new_op
);
6546 gas_assert (new_opcode
!= NULL
);
6548 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6549 instr
->opcode
->op
, new_opcode
->op
);
6551 aarch64_replace_opcode (instr
, new_opcode
);
6553 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6554 qualifier matching may fail because the out-of-date qualifier will
6555 prevent the operand being updated with a new and correct qualifier. */
6556 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6557 AARCH64_OPND_ADDR_SIMM9
);
6558 gas_assert (idx
== 1);
6559 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6561 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6563 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6569 /* Called by fix_insn to fix a MOV immediate alias instruction.
6571 Operand for a generic move immediate instruction, which is an alias
6572 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6573 a 32-bit/64-bit immediate value into general register. An assembler error
6574 shall result if the immediate cannot be created by a single one of these
6575 instructions. If there is a choice, then to ensure reversability an
6576 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6579 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6581 const aarch64_opcode
*opcode
;
6583 /* Need to check if the destination is SP/ZR. The check has to be done
6584 before any aarch64_replace_opcode. */
6585 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6586 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6588 instr
->operands
[1].imm
.value
= value
;
6589 instr
->operands
[1].skip
= 0;
6593 /* Try the MOVZ alias. */
6594 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6595 aarch64_replace_opcode (instr
, opcode
);
6596 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6597 &instr
->value
, NULL
, NULL
))
6599 put_aarch64_insn (buf
, instr
->value
);
6602 /* Try the MOVK alias. */
6603 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6604 aarch64_replace_opcode (instr
, opcode
);
6605 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6606 &instr
->value
, NULL
, NULL
))
6608 put_aarch64_insn (buf
, instr
->value
);
6613 if (try_mov_bitmask_p
)
6615 /* Try the ORR alias. */
6616 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6617 aarch64_replace_opcode (instr
, opcode
);
6618 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6619 &instr
->value
, NULL
, NULL
))
6621 put_aarch64_insn (buf
, instr
->value
);
6626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6627 _("immediate cannot be moved by a single instruction"));
6630 /* An instruction operand which is immediate related may have symbol used
6631 in the assembly, e.g.
6634 .set u32, 0x00ffff00
6636 At the time when the assembly instruction is parsed, a referenced symbol,
6637 like 'u32' in the above example may not have been seen; a fixS is created
6638 in such a case and is handled here after symbols have been resolved.
6639 Instruction is fixed up with VALUE using the information in *FIXP plus
6640 extra information in FLAGS.
6642 This function is called by md_apply_fix to fix up instructions that need
6643 a fix-up described above but does not involve any linker-time relocation. */
6646 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6650 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6651 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6652 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6656 /* Now the instruction is about to be fixed-up, so the operand that
6657 was previously marked as 'ignored' needs to be unmarked in order
6658 to get the encoding done properly. */
6659 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6660 new_inst
->operands
[idx
].skip
= 0;
6663 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6667 case AARCH64_OPND_EXCEPTION
:
6668 if (unsigned_overflow (value
, 16))
6669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6670 _("immediate out of range"));
6671 insn
= get_aarch64_insn (buf
);
6672 insn
|= encode_svc_imm (value
);
6673 put_aarch64_insn (buf
, insn
);
6676 case AARCH64_OPND_AIMM
:
6677 /* ADD or SUB with immediate.
6678 NOTE this assumes we come here with a add/sub shifted reg encoding
6679 3 322|2222|2 2 2 21111 111111
6680 1 098|7654|3 2 1 09876 543210 98765 43210
6681 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6682 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6683 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6684 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6686 3 322|2222|2 2 221111111111
6687 1 098|7654|3 2 109876543210 98765 43210
6688 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6689 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6690 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6691 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6692 Fields sf Rn Rd are already set. */
6693 insn
= get_aarch64_insn (buf
);
6697 insn
= reencode_addsub_switch_add_sub (insn
);
6701 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6702 && unsigned_overflow (value
, 12))
6704 /* Try to shift the value by 12 to make it fit. */
6705 if (((value
>> 12) << 12) == value
6706 && ! unsigned_overflow (value
, 12 + 12))
6709 insn
|= encode_addsub_imm_shift_amount (1);
6713 if (unsigned_overflow (value
, 12))
6714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6715 _("immediate out of range"));
6717 insn
|= encode_addsub_imm (value
);
6719 put_aarch64_insn (buf
, insn
);
6722 case AARCH64_OPND_SIMD_IMM
:
6723 case AARCH64_OPND_SIMD_IMM_SFT
:
6724 case AARCH64_OPND_LIMM
:
6725 /* Bit mask immediate. */
6726 gas_assert (new_inst
!= NULL
);
6727 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6728 new_inst
->operands
[idx
].imm
.value
= value
;
6729 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6730 &new_inst
->value
, NULL
, NULL
))
6731 put_aarch64_insn (buf
, new_inst
->value
);
6733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6734 _("invalid immediate"));
6737 case AARCH64_OPND_HALF
:
6738 /* 16-bit unsigned immediate. */
6739 if (unsigned_overflow (value
, 16))
6740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6741 _("immediate out of range"));
6742 insn
= get_aarch64_insn (buf
);
6743 insn
|= encode_movw_imm (value
& 0xffff);
6744 put_aarch64_insn (buf
, insn
);
6747 case AARCH64_OPND_IMM_MOV
:
6748 /* Operand for a generic move immediate instruction, which is
6749 an alias instruction that generates a single MOVZ, MOVN or ORR
6750 instruction to loads a 32-bit/64-bit immediate value into general
6751 register. An assembler error shall result if the immediate cannot be
6752 created by a single one of these instructions. If there is a choice,
6753 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6754 and MOVZ or MOVN to ORR. */
6755 gas_assert (new_inst
!= NULL
);
6756 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6759 case AARCH64_OPND_ADDR_SIMM7
:
6760 case AARCH64_OPND_ADDR_SIMM9
:
6761 case AARCH64_OPND_ADDR_SIMM9_2
:
6762 case AARCH64_OPND_ADDR_UIMM12
:
6763 /* Immediate offset in an address. */
6764 insn
= get_aarch64_insn (buf
);
6766 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6767 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6768 || new_inst
->opcode
->operands
[2] == opnd
);
6770 /* Get the index of the address operand. */
6771 if (new_inst
->opcode
->operands
[1] == opnd
)
6772 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6775 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6778 /* Update the resolved offset value. */
6779 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6781 /* Encode/fix-up. */
6782 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6783 &new_inst
->value
, NULL
, NULL
))
6785 put_aarch64_insn (buf
, new_inst
->value
);
6788 else if (new_inst
->opcode
->iclass
== ldst_pos
6789 && try_to_encode_as_unscaled_ldst (new_inst
))
6791 put_aarch64_insn (buf
, new_inst
->value
);
6795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6796 _("immediate offset out of range"));
6801 as_fatal (_("unhandled operand code %d"), opnd
);
6805 /* Apply a fixup (fixP) to segment data, once it has been determined
6806 by our caller that we have all the info we need to fix it up.
6808 Parameter valP is the pointer to the value of the bits. */
6811 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6813 offsetT value
= *valP
;
6815 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6817 unsigned flags
= fixP
->fx_addnumber
;
6819 DEBUG_TRACE ("\n\n");
6820 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6821 DEBUG_TRACE ("Enter md_apply_fix");
6823 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6825 /* Note whether this will delete the relocation. */
6827 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6830 /* Process the relocations. */
6831 switch (fixP
->fx_r_type
)
6833 case BFD_RELOC_NONE
:
6834 /* This will need to go in the object file. */
6839 case BFD_RELOC_8_PCREL
:
6840 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6841 md_number_to_chars (buf
, value
, 1);
6845 case BFD_RELOC_16_PCREL
:
6846 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6847 md_number_to_chars (buf
, value
, 2);
6851 case BFD_RELOC_32_PCREL
:
6852 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6853 md_number_to_chars (buf
, value
, 4);
6857 case BFD_RELOC_64_PCREL
:
6858 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6859 md_number_to_chars (buf
, value
, 8);
6862 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6863 /* We claim that these fixups have been processed here, even if
6864 in fact we generate an error because we do not have a reloc
6865 for them, so tc_gen_reloc() will reject them. */
6867 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6870 _("undefined symbol %s used as an immediate value"),
6871 S_GET_NAME (fixP
->fx_addsy
));
6872 goto apply_fix_return
;
6874 fix_insn (fixP
, flags
, value
);
6877 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6878 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6882 _("pc-relative load offset not word aligned"));
6883 if (signed_overflow (value
, 21))
6884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6885 _("pc-relative load offset out of range"));
6886 insn
= get_aarch64_insn (buf
);
6887 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6888 put_aarch64_insn (buf
, insn
);
6892 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6893 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6895 if (signed_overflow (value
, 21))
6896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6897 _("pc-relative address offset out of range"));
6898 insn
= get_aarch64_insn (buf
);
6899 insn
|= encode_adr_imm (value
);
6900 put_aarch64_insn (buf
, insn
);
6904 case BFD_RELOC_AARCH64_BRANCH19
:
6905 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6909 _("conditional branch target not word aligned"));
6910 if (signed_overflow (value
, 21))
6911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6912 _("conditional branch out of range"));
6913 insn
= get_aarch64_insn (buf
);
6914 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6915 put_aarch64_insn (buf
, insn
);
6919 case BFD_RELOC_AARCH64_TSTBR14
:
6920 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6924 _("conditional branch target not word aligned"));
6925 if (signed_overflow (value
, 16))
6926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6927 _("conditional branch out of range"));
6928 insn
= get_aarch64_insn (buf
);
6929 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6930 put_aarch64_insn (buf
, insn
);
6934 case BFD_RELOC_AARCH64_CALL26
:
6935 case BFD_RELOC_AARCH64_JUMP26
:
6936 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6940 _("branch target not word aligned"));
6941 if (signed_overflow (value
, 28))
6942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6943 _("branch out of range"));
6944 insn
= get_aarch64_insn (buf
);
6945 insn
|= encode_branch_ofs_26 (value
>> 2);
6946 put_aarch64_insn (buf
, insn
);
6950 case BFD_RELOC_AARCH64_MOVW_G0
:
6951 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6952 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6953 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6956 case BFD_RELOC_AARCH64_MOVW_G1
:
6957 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6958 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6959 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6962 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6964 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6965 /* Should always be exported to object file, see
6966 aarch64_force_relocation(). */
6967 gas_assert (!fixP
->fx_done
);
6968 gas_assert (seg
->use_rela_p
);
6970 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6972 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6973 /* Should always be exported to object file, see
6974 aarch64_force_relocation(). */
6975 gas_assert (!fixP
->fx_done
);
6976 gas_assert (seg
->use_rela_p
);
6978 case BFD_RELOC_AARCH64_MOVW_G2
:
6979 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6980 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6983 case BFD_RELOC_AARCH64_MOVW_G3
:
6986 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6988 insn
= get_aarch64_insn (buf
);
6992 /* REL signed addend must fit in 16 bits */
6993 if (signed_overflow (value
, 16))
6994 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6995 _("offset out of range"));
6999 /* Check for overflow and scale. */
7000 switch (fixP
->fx_r_type
)
7002 case BFD_RELOC_AARCH64_MOVW_G0
:
7003 case BFD_RELOC_AARCH64_MOVW_G1
:
7004 case BFD_RELOC_AARCH64_MOVW_G2
:
7005 case BFD_RELOC_AARCH64_MOVW_G3
:
7006 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7007 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7008 if (unsigned_overflow (value
, scale
+ 16))
7009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7010 _("unsigned value out of range"));
7012 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7013 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7014 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7015 /* NOTE: We can only come here with movz or movn. */
7016 if (signed_overflow (value
, scale
+ 16))
7017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7018 _("signed value out of range"));
7021 /* Force use of MOVN. */
7023 insn
= reencode_movzn_to_movn (insn
);
7027 /* Force use of MOVZ. */
7028 insn
= reencode_movzn_to_movz (insn
);
7032 /* Unchecked relocations. */
7038 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7039 insn
|= encode_movw_imm (value
& 0xffff);
7041 put_aarch64_insn (buf
, insn
);
7045 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7046 fixP
->fx_r_type
= (ilp32_p
7047 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7048 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7049 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7050 /* Should always be exported to object file, see
7051 aarch64_force_relocation(). */
7052 gas_assert (!fixP
->fx_done
);
7053 gas_assert (seg
->use_rela_p
);
7056 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7057 fixP
->fx_r_type
= (ilp32_p
7058 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7059 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7060 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7061 /* Should always be exported to object file, see
7062 aarch64_force_relocation(). */
7063 gas_assert (!fixP
->fx_done
);
7064 gas_assert (seg
->use_rela_p
);
7067 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7068 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7069 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7070 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7071 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7072 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7073 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7074 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7075 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7076 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7077 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7078 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7079 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7080 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7081 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7082 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7083 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7084 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7085 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7086 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7087 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7088 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7089 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7090 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7091 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7092 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7093 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7094 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7095 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7096 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7097 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7098 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7099 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7100 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7101 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7102 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7103 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7104 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7105 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7106 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7107 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7108 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7109 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7110 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7111 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7112 /* Should always be exported to object file, see
7113 aarch64_force_relocation(). */
7114 gas_assert (!fixP
->fx_done
);
7115 gas_assert (seg
->use_rela_p
);
7118 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7119 /* Should always be exported to object file, see
7120 aarch64_force_relocation(). */
7121 fixP
->fx_r_type
= (ilp32_p
7122 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7123 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7124 gas_assert (!fixP
->fx_done
);
7125 gas_assert (seg
->use_rela_p
);
7128 case BFD_RELOC_AARCH64_ADD_LO12
:
7129 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7130 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7131 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7132 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7133 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7134 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7135 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7136 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7137 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7138 case BFD_RELOC_AARCH64_LDST128_LO12
:
7139 case BFD_RELOC_AARCH64_LDST16_LO12
:
7140 case BFD_RELOC_AARCH64_LDST32_LO12
:
7141 case BFD_RELOC_AARCH64_LDST64_LO12
:
7142 case BFD_RELOC_AARCH64_LDST8_LO12
:
7143 /* Should always be exported to object file, see
7144 aarch64_force_relocation(). */
7145 gas_assert (!fixP
->fx_done
);
7146 gas_assert (seg
->use_rela_p
);
7149 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7150 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7151 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7154 case BFD_RELOC_UNUSED
:
7155 /* An error will already have been reported. */
7159 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7160 _("unexpected %s fixup"),
7161 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7166 /* Free the allocated the struct aarch64_inst.
7167 N.B. currently there are very limited number of fix-up types actually use
7168 this field, so the impact on the performance should be minimal . */
7169 if (fixP
->tc_fix_data
.inst
!= NULL
)
7170 free (fixP
->tc_fix_data
.inst
);
7175 /* Translate internal representation of relocation info to BFD target
7179 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7182 bfd_reloc_code_real_type code
;
7184 reloc
= XNEW (arelent
);
7186 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7187 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7188 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7192 if (section
->use_rela_p
)
7193 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7195 fixp
->fx_offset
= reloc
->address
;
7197 reloc
->addend
= fixp
->fx_offset
;
7199 code
= fixp
->fx_r_type
;
7204 code
= BFD_RELOC_16_PCREL
;
7209 code
= BFD_RELOC_32_PCREL
;
7214 code
= BFD_RELOC_64_PCREL
;
7221 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7222 if (reloc
->howto
== NULL
)
7224 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7226 ("cannot represent %s relocation in this object file format"),
7227 bfd_get_reloc_code_name (code
));
7234 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7237 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7239 bfd_reloc_code_real_type type
;
7243 FIXME: @@ Should look at CPU word size. */
7250 type
= BFD_RELOC_16
;
7253 type
= BFD_RELOC_32
;
7256 type
= BFD_RELOC_64
;
7259 as_bad (_("cannot do %u-byte relocation"), size
);
7260 type
= BFD_RELOC_UNUSED
;
7264 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7268 aarch64_force_relocation (struct fix
*fixp
)
7270 switch (fixp
->fx_r_type
)
7272 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7273 /* Perform these "immediate" internal relocations
7274 even if the symbol is extern or weak. */
7277 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7278 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7279 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7280 /* Pseudo relocs that need to be fixed up according to
7284 case BFD_RELOC_AARCH64_ADD_LO12
:
7285 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7286 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7287 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7288 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7289 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7290 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7291 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7292 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7293 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7294 case BFD_RELOC_AARCH64_LDST128_LO12
:
7295 case BFD_RELOC_AARCH64_LDST16_LO12
:
7296 case BFD_RELOC_AARCH64_LDST32_LO12
:
7297 case BFD_RELOC_AARCH64_LDST64_LO12
:
7298 case BFD_RELOC_AARCH64_LDST8_LO12
:
7299 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7300 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7301 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7302 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7303 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7304 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7305 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7306 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7307 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7308 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7309 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7310 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7311 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7312 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7313 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7314 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7315 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7316 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7317 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7318 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7319 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7320 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7321 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7322 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7323 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7324 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7325 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7326 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7327 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7328 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7329 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7330 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7331 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7332 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7333 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7334 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7335 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7336 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7337 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7338 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7339 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7340 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7341 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7342 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7343 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7344 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7345 /* Always leave these relocations for the linker. */
7352 return generic_force_reloc (fixp
);
7358 elf64_aarch64_target_format (void)
7360 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7362 /* FIXME: What to do for ilp32_p ? */
7363 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7365 if (target_big_endian
)
7366 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7368 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7372 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7374 elf_frob_symbol (symp
, puntp
);
7378 /* MD interface: Finalization. */
7380 /* A good place to do this, although this was probably not intended
7381 for this kind of use. We need to dump the literal pool before
7382 references are made to a null symbol pointer. */
7385 aarch64_cleanup (void)
7389 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7391 /* Put it at the end of the relevant section. */
7392 subseg_set (pool
->section
, pool
->sub_section
);
7398 /* Remove any excess mapping symbols generated for alignment frags in
7399 SEC. We may have created a mapping symbol before a zero byte
7400 alignment; remove it if there's a mapping symbol after the
7403 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7404 void *dummy ATTRIBUTE_UNUSED
)
7406 segment_info_type
*seginfo
= seg_info (sec
);
7409 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7412 for (fragp
= seginfo
->frchainP
->frch_root
;
7413 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7415 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7416 fragS
*next
= fragp
->fr_next
;
7418 /* Variable-sized frags have been converted to fixed size by
7419 this point. But if this was variable-sized to start with,
7420 there will be a fixed-size frag after it. So don't handle
7422 if (sym
== NULL
|| next
== NULL
)
7425 if (S_GET_VALUE (sym
) < next
->fr_address
)
7426 /* Not at the end of this frag. */
7428 know (S_GET_VALUE (sym
) == next
->fr_address
);
7432 if (next
->tc_frag_data
.first_map
!= NULL
)
7434 /* Next frag starts with a mapping symbol. Discard this
7436 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7440 if (next
->fr_next
== NULL
)
7442 /* This mapping symbol is at the end of the section. Discard
7444 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7445 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7449 /* As long as we have empty frags without any mapping symbols,
7451 /* If the next frag is non-empty and does not start with a
7452 mapping symbol, then this mapping symbol is required. */
7453 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7456 next
= next
->fr_next
;
7458 while (next
!= NULL
);
7463 /* Adjust the symbol table. */
7466 aarch64_adjust_symtab (void)
7469 /* Remove any overlapping mapping symbols generated by alignment frags. */
7470 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7471 /* Now do generic ELF adjustments. */
7472 elf_adjust_symtab ();
7477 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7479 const char *hash_err
;
7481 hash_err
= hash_insert (table
, key
, value
);
7483 printf ("Internal Error: Can't hash %s\n", key
);
7487 fill_instruction_hash_table (void)
7489 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7491 while (opcode
->name
!= NULL
)
7493 templates
*templ
, *new_templ
;
7494 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7496 new_templ
= XNEW (templates
);
7497 new_templ
->opcode
= opcode
;
7498 new_templ
->next
= NULL
;
7501 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7504 new_templ
->next
= templ
->next
;
7505 templ
->next
= new_templ
;
7512 convert_to_upper (char *dst
, const char *src
, size_t num
)
7515 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7516 *dst
= TOUPPER (*src
);
7520 /* Assume STR point to a lower-case string, allocate, convert and return
7521 the corresponding upper-case string. */
7522 static inline const char*
7523 get_upper_str (const char *str
)
7526 size_t len
= strlen (str
);
7527 ret
= XNEWVEC (char, len
+ 1);
7528 convert_to_upper (ret
, str
, len
);
7532 /* MD interface: Initialization. */
7540 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7541 || (aarch64_cond_hsh
= hash_new ()) == NULL
7542 || (aarch64_shift_hsh
= hash_new ()) == NULL
7543 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7544 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7545 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7546 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7547 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7548 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7549 || (aarch64_reg_hsh
= hash_new ()) == NULL
7550 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7551 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7552 || (aarch64_pldop_hsh
= hash_new ()) == NULL
7553 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
7554 as_fatal (_("virtual memory exhausted"));
7556 fill_instruction_hash_table ();
7558 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7559 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7560 (void *) (aarch64_sys_regs
+ i
));
7562 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7563 checked_hash_insert (aarch64_pstatefield_hsh
,
7564 aarch64_pstatefields
[i
].name
,
7565 (void *) (aarch64_pstatefields
+ i
));
7567 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
7568 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7569 aarch64_sys_regs_ic
[i
].name
,
7570 (void *) (aarch64_sys_regs_ic
+ i
));
7572 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
7573 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7574 aarch64_sys_regs_dc
[i
].name
,
7575 (void *) (aarch64_sys_regs_dc
+ i
));
7577 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
7578 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7579 aarch64_sys_regs_at
[i
].name
,
7580 (void *) (aarch64_sys_regs_at
+ i
));
7582 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
7583 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7584 aarch64_sys_regs_tlbi
[i
].name
,
7585 (void *) (aarch64_sys_regs_tlbi
+ i
));
7587 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7588 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7589 (void *) (reg_names
+ i
));
7591 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7592 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7593 (void *) (nzcv_names
+ i
));
7595 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7597 const char *name
= aarch64_operand_modifiers
[i
].name
;
7598 checked_hash_insert (aarch64_shift_hsh
, name
,
7599 (void *) (aarch64_operand_modifiers
+ i
));
7600 /* Also hash the name in the upper case. */
7601 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7602 (void *) (aarch64_operand_modifiers
+ i
));
7605 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7608 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7609 the same condition code. */
7610 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7612 const char *name
= aarch64_conds
[i
].names
[j
];
7615 checked_hash_insert (aarch64_cond_hsh
, name
,
7616 (void *) (aarch64_conds
+ i
));
7617 /* Also hash the name in the upper case. */
7618 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7619 (void *) (aarch64_conds
+ i
));
7623 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7625 const char *name
= aarch64_barrier_options
[i
].name
;
7626 /* Skip xx00 - the unallocated values of option. */
7629 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7630 (void *) (aarch64_barrier_options
+ i
));
7631 /* Also hash the name in the upper case. */
7632 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7633 (void *) (aarch64_barrier_options
+ i
));
7636 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7638 const char* name
= aarch64_prfops
[i
].name
;
7639 /* Skip the unallocated hint encodings. */
7642 checked_hash_insert (aarch64_pldop_hsh
, name
,
7643 (void *) (aarch64_prfops
+ i
));
7644 /* Also hash the name in the upper case. */
7645 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7646 (void *) (aarch64_prfops
+ i
));
7649 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
7651 const char* name
= aarch64_hint_options
[i
].name
;
7653 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
7654 (void *) (aarch64_hint_options
+ i
));
7655 /* Also hash the name in the upper case. */
7656 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7657 (void *) (aarch64_hint_options
+ i
));
7660 /* Set the cpu variant based on the command-line options. */
7662 mcpu_cpu_opt
= march_cpu_opt
;
7665 mcpu_cpu_opt
= &cpu_default
;
7667 cpu_variant
= *mcpu_cpu_opt
;
7669 /* Record the CPU type. */
7670 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7672 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7675 /* Command line processing. */
7677 const char *md_shortopts
= "m:";
7679 #ifdef AARCH64_BI_ENDIAN
7680 #define OPTION_EB (OPTION_MD_BASE + 0)
7681 #define OPTION_EL (OPTION_MD_BASE + 1)
7683 #if TARGET_BYTES_BIG_ENDIAN
7684 #define OPTION_EB (OPTION_MD_BASE + 0)
7686 #define OPTION_EL (OPTION_MD_BASE + 1)
7690 struct option md_longopts
[] = {
7692 {"EB", no_argument
, NULL
, OPTION_EB
},
7695 {"EL", no_argument
, NULL
, OPTION_EL
},
7697 {NULL
, no_argument
, NULL
, 0}
7700 size_t md_longopts_size
= sizeof (md_longopts
);
7702 struct aarch64_option_table
7704 const char *option
; /* Option name to match. */
7705 const char *help
; /* Help information. */
7706 int *var
; /* Variable to change. */
7707 int value
; /* What to change it to. */
7708 char *deprecated
; /* If non-null, print this message. */
7711 static struct aarch64_option_table aarch64_opts
[] = {
7712 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7713 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7715 #ifdef DEBUG_AARCH64
7716 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7717 #endif /* DEBUG_AARCH64 */
7718 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7720 {"mno-verbose-error", N_("do not output verbose error messages"),
7721 &verbose_error_p
, 0, NULL
},
7722 {NULL
, NULL
, NULL
, 0, NULL
}
7725 struct aarch64_cpu_option_table
7728 const aarch64_feature_set value
;
7729 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7731 const char *canonical_name
;
7734 /* This list should, at a minimum, contain all the cpu names
7735 recognized by GCC. */
7736 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7737 {"all", AARCH64_ANY
, NULL
},
7738 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7739 AARCH64_FEATURE_CRC
), "Cortex-A35"},
7740 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7741 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7742 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7743 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7744 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7745 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7746 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7747 AARCH64_FEATURE_CRC
), "Cortex-A73"},
7748 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7749 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7750 "Samsung Exynos M1"},
7751 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7752 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7753 "Qualcomm QDF24XX"},
7754 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7755 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7757 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
7758 AARCH64_FEATURE_CRYPTO
),
7760 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7761 in earlier releases and is superseded by 'xgene1' in all
7763 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7764 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7765 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7766 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7767 {"generic", AARCH64_ARCH_V8
, NULL
},
7769 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7772 struct aarch64_arch_option_table
7775 const aarch64_feature_set value
;
7778 /* This list should, at a minimum, contain all the architecture names
7779 recognized by GCC. */
7780 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7781 {"all", AARCH64_ANY
},
7782 {"armv8-a", AARCH64_ARCH_V8
},
7783 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7784 {"armv8.2-a", AARCH64_ARCH_V8_2
},
7785 {NULL
, AARCH64_ARCH_NONE
}
7788 /* ISA extensions. */
7789 struct aarch64_option_cpu_value_table
7792 const aarch64_feature_set value
;
7793 const aarch64_feature_set require
; /* Feature dependencies. */
7796 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7797 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
7799 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
7801 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
7803 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
7805 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
7807 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
7809 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
7811 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
7813 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
7814 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7815 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
7816 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7817 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
7819 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
7822 struct aarch64_long_option_table
7824 const char *option
; /* Substring to match. */
7825 const char *help
; /* Help information. */
7826 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
7827 char *deprecated
; /* If non-null, print this message. */
7830 /* Transitive closure of features depending on set. */
7831 static aarch64_feature_set
7832 aarch64_feature_disable_set (aarch64_feature_set set
)
7834 const struct aarch64_option_cpu_value_table
*opt
;
7835 aarch64_feature_set prev
= 0;
7837 while (prev
!= set
) {
7839 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7840 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
7841 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
7846 /* Transitive closure of dependencies of set. */
7847 static aarch64_feature_set
7848 aarch64_feature_enable_set (aarch64_feature_set set
)
7850 const struct aarch64_option_cpu_value_table
*opt
;
7851 aarch64_feature_set prev
= 0;
7853 while (prev
!= set
) {
7855 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7856 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
7857 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
7863 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
7864 bfd_boolean ext_only
)
7866 /* We insist on extensions being added before being removed. We achieve
7867 this by using the ADDING_VALUE variable to indicate whether we are
7868 adding an extension (1) or removing it (0) and only allowing it to
7869 change in the order -1 -> 1 -> 0. */
7870 int adding_value
= -1;
7871 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
7873 /* Copy the feature set, so that we can modify it. */
7877 while (str
!= NULL
&& *str
!= 0)
7879 const struct aarch64_option_cpu_value_table
*opt
;
7880 const char *ext
= NULL
;
7887 as_bad (_("invalid architectural extension"));
7891 ext
= strchr (++str
, '+');
7897 optlen
= strlen (str
);
7899 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7901 if (adding_value
!= 0)
7906 else if (optlen
> 0)
7908 if (adding_value
== -1)
7910 else if (adding_value
!= 1)
7912 as_bad (_("must specify extensions to add before specifying "
7913 "those to remove"));
7920 as_bad (_("missing architectural extension"));
7924 gas_assert (adding_value
!= -1);
7926 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7927 if (strncmp (opt
->name
, str
, optlen
) == 0)
7929 aarch64_feature_set set
;
7931 /* Add or remove the extension. */
7934 set
= aarch64_feature_enable_set (opt
->value
);
7935 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
7939 set
= aarch64_feature_disable_set (opt
->value
);
7940 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
7945 if (opt
->name
== NULL
)
7947 as_bad (_("unknown architectural extension `%s'"), str
);
7958 aarch64_parse_cpu (const char *str
)
7960 const struct aarch64_cpu_option_table
*opt
;
7961 const char *ext
= strchr (str
, '+');
7967 optlen
= strlen (str
);
7971 as_bad (_("missing cpu name `%s'"), str
);
7975 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7976 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7978 mcpu_cpu_opt
= &opt
->value
;
7980 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7985 as_bad (_("unknown cpu `%s'"), str
);
7990 aarch64_parse_arch (const char *str
)
7992 const struct aarch64_arch_option_table
*opt
;
7993 const char *ext
= strchr (str
, '+');
7999 optlen
= strlen (str
);
8003 as_bad (_("missing architecture name `%s'"), str
);
8007 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8008 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8010 march_cpu_opt
= &opt
->value
;
8012 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8017 as_bad (_("unknown architecture `%s'\n"), str
);
8022 struct aarch64_option_abi_value_table
8025 enum aarch64_abi_type value
;
8028 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8029 {"ilp32", AARCH64_ABI_ILP32
},
8030 {"lp64", AARCH64_ABI_LP64
},
8034 aarch64_parse_abi (const char *str
)
8040 as_bad (_("missing abi name `%s'"), str
);
8044 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8045 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8047 aarch64_abi
= aarch64_abis
[i
].value
;
8051 as_bad (_("unknown abi `%s'\n"), str
);
8055 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8057 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8058 aarch64_parse_abi
, NULL
},
8059 #endif /* OBJ_ELF */
8060 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8061 aarch64_parse_cpu
, NULL
},
8062 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8063 aarch64_parse_arch
, NULL
},
8064 {NULL
, NULL
, 0, NULL
}
8068 md_parse_option (int c
, const char *arg
)
8070 struct aarch64_option_table
*opt
;
8071 struct aarch64_long_option_table
*lopt
;
8077 target_big_endian
= 1;
8083 target_big_endian
= 0;
8088 /* Listing option. Just ignore these, we don't support additional
8093 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8095 if (c
== opt
->option
[0]
8096 && ((arg
== NULL
&& opt
->option
[1] == 0)
8097 || streq (arg
, opt
->option
+ 1)))
8099 /* If the option is deprecated, tell the user. */
8100 if (opt
->deprecated
!= NULL
)
8101 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8102 arg
? arg
: "", _(opt
->deprecated
));
8104 if (opt
->var
!= NULL
)
8105 *opt
->var
= opt
->value
;
8111 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8113 /* These options are expected to have an argument. */
8114 if (c
== lopt
->option
[0]
8116 && strncmp (arg
, lopt
->option
+ 1,
8117 strlen (lopt
->option
+ 1)) == 0)
8119 /* If the option is deprecated, tell the user. */
8120 if (lopt
->deprecated
!= NULL
)
8121 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8122 _(lopt
->deprecated
));
8124 /* Call the sup-option parser. */
8125 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8136 md_show_usage (FILE * fp
)
8138 struct aarch64_option_table
*opt
;
8139 struct aarch64_long_option_table
*lopt
;
8141 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8143 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8144 if (opt
->help
!= NULL
)
8145 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8147 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8148 if (lopt
->help
!= NULL
)
8149 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8153 -EB assemble code for a big-endian cpu\n"));
8158 -EL assemble code for a little-endian cpu\n"));
8162 /* Parse a .cpu directive. */
8165 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8167 const struct aarch64_cpu_option_table
*opt
;
8173 name
= input_line_pointer
;
8174 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8175 input_line_pointer
++;
8176 saved_char
= *input_line_pointer
;
8177 *input_line_pointer
= 0;
8179 ext
= strchr (name
, '+');
8182 optlen
= ext
- name
;
8184 optlen
= strlen (name
);
8186 /* Skip the first "all" entry. */
8187 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8188 if (strlen (opt
->name
) == optlen
8189 && strncmp (name
, opt
->name
, optlen
) == 0)
8191 mcpu_cpu_opt
= &opt
->value
;
8193 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8196 cpu_variant
= *mcpu_cpu_opt
;
8198 *input_line_pointer
= saved_char
;
8199 demand_empty_rest_of_line ();
8202 as_bad (_("unknown cpu `%s'"), name
);
8203 *input_line_pointer
= saved_char
;
8204 ignore_rest_of_line ();
8208 /* Parse a .arch directive. */
8211 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8213 const struct aarch64_arch_option_table
*opt
;
8219 name
= input_line_pointer
;
8220 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8221 input_line_pointer
++;
8222 saved_char
= *input_line_pointer
;
8223 *input_line_pointer
= 0;
8225 ext
= strchr (name
, '+');
8228 optlen
= ext
- name
;
8230 optlen
= strlen (name
);
8232 /* Skip the first "all" entry. */
8233 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8234 if (strlen (opt
->name
) == optlen
8235 && strncmp (name
, opt
->name
, optlen
) == 0)
8237 mcpu_cpu_opt
= &opt
->value
;
8239 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8242 cpu_variant
= *mcpu_cpu_opt
;
8244 *input_line_pointer
= saved_char
;
8245 demand_empty_rest_of_line ();
8249 as_bad (_("unknown architecture `%s'\n"), name
);
8250 *input_line_pointer
= saved_char
;
8251 ignore_rest_of_line ();
8254 /* Parse a .arch_extension directive. */
8257 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8260 char *ext
= input_line_pointer
;;
8262 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8263 input_line_pointer
++;
8264 saved_char
= *input_line_pointer
;
8265 *input_line_pointer
= 0;
8267 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8270 cpu_variant
= *mcpu_cpu_opt
;
8272 *input_line_pointer
= saved_char
;
8273 demand_empty_rest_of_line ();
8276 /* Copy symbol information. */
8279 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8281 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);