1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
409 static struct hash_control
*aarch64_hint_opt_hsh
;
411 /* Stuff needed to resolve the label ambiguity
420 static symbolS
*last_label_seen
;
422 /* Literal pool structure. Held on a per-section
423 and per-sub-section basis. */
425 #define MAX_LITERAL_POOL_SIZE 1024
426 typedef struct literal_expression
429 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
430 LITTLENUM_TYPE
* bignum
;
431 } literal_expression
;
433 typedef struct literal_pool
435 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
436 unsigned int next_free_entry
;
442 struct literal_pool
*next
;
445 /* Pointer to a linked list of literal pools. */
446 static literal_pool
*list_of_pools
= NULL
;
450 /* This array holds the chars that always start a comment. If the
451 pre-processor is disabled, these aren't very useful. */
452 const char comment_chars
[] = "";
454 /* This array holds the chars that only start a comment at the beginning of
455 a line. If the line seems to have the form '# 123 filename'
456 .line and .file directives will appear in the pre-processed output. */
457 /* Note that input_file.c hand checks for '#' at the beginning of the
458 first line of the input file. This is because the compiler outputs
459 #NO_APP at the beginning of its output. */
460 /* Also note that comments like this one will always work. */
461 const char line_comment_chars
[] = "#";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant
466 from exp in floating point numbers. */
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant. */
473 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
475 /* Prefix character that indicates the start of an immediate value. */
476 #define is_immediate_prefix(C) ((C) == '#')
478 /* Separator character handling. */
480 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
482 static inline bfd_boolean
483 skip_past_char (char **str
, char c
)
494 #define skip_past_comma(str) skip_past_char (str, ',')
496 /* Arithmetic expressions (possibly involving symbols). */
498 static bfd_boolean in_my_get_expression_p
= FALSE
;
500 /* Third argument to my_get_expression. */
501 #define GE_NO_PREFIX 0
502 #define GE_OPT_PREFIX 1
504 /* Return TRUE if the string pointed by *STR is successfully parsed
505 as an valid expression; *EP will be filled with the information of
506 such an expression. Otherwise return FALSE. */
509 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
514 int prefix_present_p
= 0;
521 if (is_immediate_prefix (**str
))
524 prefix_present_p
= 1;
531 memset (ep
, 0, sizeof (expressionS
));
533 save_in
= input_line_pointer
;
534 input_line_pointer
= *str
;
535 in_my_get_expression_p
= TRUE
;
536 seg
= expression (ep
);
537 in_my_get_expression_p
= FALSE
;
539 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
541 /* We found a bad expression in md_operand(). */
542 *str
= input_line_pointer
;
543 input_line_pointer
= save_in
;
544 if (prefix_present_p
&& ! error_p ())
545 set_fatal_syntax_error (_("bad expression"));
547 set_first_syntax_error (_("bad expression"));
552 if (seg
!= absolute_section
553 && seg
!= text_section
554 && seg
!= data_section
555 && seg
!= bss_section
&& seg
!= undefined_section
)
557 set_syntax_error (_("bad segment"));
558 *str
= input_line_pointer
;
559 input_line_pointer
= save_in
;
566 *str
= input_line_pointer
;
567 input_line_pointer
= save_in
;
571 /* Turn a string in input_line_pointer into a floating point constant
572 of type TYPE, and store the appropriate bytes in *LITP. The number
573 of LITTLENUMS emitted is stored in *SIZEP. An error message is
574 returned, or NULL on OK. */
577 md_atof (int type
, char *litP
, int *sizeP
)
579 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
582 /* We handle all bad expressions here, so that we can report the faulty
583 instruction in the error message. */
585 md_operand (expressionS
* exp
)
587 if (in_my_get_expression_p
)
588 exp
->X_op
= O_illegal
;
591 /* Immediate values. */
593 /* Errors may be set multiple times during parsing or bit encoding
594 (particularly in the Neon bits), but usually the earliest error which is set
595 will be the most meaningful. Avoid overwriting it with later (cascading)
596 errors by calling this function. */
599 first_error (const char *error
)
602 set_syntax_error (error
);
605 /* Similiar to first_error, but this function accepts formatted error
608 first_error_fmt (const char *format
, ...)
613 /* N.B. this single buffer will not cause error messages for different
614 instructions to pollute each other; this is because at the end of
615 processing of each assembly line, error message if any will be
616 collected by as_bad. */
617 static char buffer
[size
];
621 int ret ATTRIBUTE_UNUSED
;
622 va_start (args
, format
);
623 ret
= vsnprintf (buffer
, size
, format
, args
);
624 know (ret
<= size
- 1 && ret
>= 0);
626 set_syntax_error (buffer
);
630 /* Register parsing. */
632 /* Generic register parser which is called by other specialized
634 CCP points to what should be the beginning of a register name.
635 If it is indeed a valid register name, advance CCP over it and
636 return the reg_entry structure; otherwise return NULL.
637 It does not issue diagnostics. */
640 parse_reg (char **ccp
)
646 #ifdef REGISTER_PREFIX
647 if (*start
!= REGISTER_PREFIX
)
653 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
658 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
660 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
669 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
672 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
674 if (reg
->type
== type
)
679 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
680 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
681 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
682 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
683 case REG_TYPE_VN
: /* Vector register. */
684 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
685 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
686 == reg_type_masks
[reg
->type
]);
688 as_fatal ("unhandled type %d", type
);
693 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
694 Return the register number otherwise. *ISREG32 is set to one if the
695 register is 32-bit wide; *ISREGZERO is set to one if the register is
696 of type Z_32 or Z_64.
697 Note that this function does not issue any diagnostics. */
700 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
701 int *isreg32
, int *isregzero
)
704 const reg_entry
*reg
= parse_reg (&str
);
709 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
718 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
723 *isreg32
= reg
->type
== REG_TYPE_R_32
;
730 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
742 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
743 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
744 otherwise return FALSE.
746 Accept only one occurrence of:
747 8b 16b 2h 4h 8h 2s 4s 1d 2d
750 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
754 unsigned element_size
;
755 enum neon_el_type type
;
765 width
= strtoul (ptr
, &ptr
, 10);
766 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
768 first_error_fmt (_("bad size %d in vector width specifier"), width
);
773 switch (TOLOWER (*ptr
))
801 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
803 first_error (_("missing element size"));
806 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
807 && !(width
== 2 && element_size
== 16))
810 ("invalid element size %d and vector size combination %c"),
816 parsed_type
->type
= type
;
817 parsed_type
->width
= width
;
824 /* Parse a single type, e.g. ".8b", leading period included.
825 Only applicable to Vn registers.
827 Return TRUE on success; otherwise return FALSE. */
829 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
835 if (! parse_neon_type_for_operand (vectype
, &str
))
837 first_error (_("vector type expected"));
849 /* Parse a register of the type TYPE.
851 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
852 name or the parsed register is not of TYPE.
854 Otherwise return the register number, and optionally fill in the actual
855 type of the register in *RTYPE when multiple alternatives were given, and
856 return the register shape and element index information in *TYPEINFO.
858 IN_REG_LIST should be set with TRUE if the caller is parsing a register
862 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
863 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
866 const reg_entry
*reg
= parse_reg (&str
);
867 struct neon_type_el atype
;
868 struct neon_type_el parsetype
;
869 bfd_boolean is_typed_vecreg
= FALSE
;
872 atype
.type
= NT_invtype
;
880 set_default_error ();
884 if (! aarch64_check_reg_type (reg
, type
))
886 DEBUG_TRACE ("reg type check failed");
887 set_default_error ();
892 if (type
== REG_TYPE_VN
893 && parse_neon_operand_type (&parsetype
, &str
))
895 /* Register if of the form Vn.[bhsdq]. */
896 is_typed_vecreg
= TRUE
;
898 if (parsetype
.width
== 0)
899 /* Expect index. In the new scheme we cannot have
900 Vn.[bhsdq] represent a scalar. Therefore any
901 Vn.[bhsdq] should have an index following it.
902 Except in reglists ofcourse. */
903 atype
.defined
|= NTA_HASINDEX
;
905 atype
.defined
|= NTA_HASTYPE
;
907 atype
.type
= parsetype
.type
;
908 atype
.width
= parsetype
.width
;
911 if (skip_past_char (&str
, '['))
915 /* Reject Sn[index] syntax. */
916 if (!is_typed_vecreg
)
918 first_error (_("this type of register can't be indexed"));
922 if (in_reg_list
== TRUE
)
924 first_error (_("index not allowed inside register list"));
928 atype
.defined
|= NTA_HASINDEX
;
930 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
932 if (exp
.X_op
!= O_constant
)
934 first_error (_("constant expression required"));
938 if (! skip_past_char (&str
, ']'))
941 atype
.index
= exp
.X_add_number
;
943 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
945 /* Indexed vector register expected. */
946 first_error (_("indexed vector register expected"));
950 /* A vector reg Vn should be typed or indexed. */
951 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
953 first_error (_("invalid use of vector register"));
969 Return the register number on success; return PARSE_FAIL otherwise.
971 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
972 the register (e.g. NEON double or quad reg when either has been requested).
974 If this is a NEON vector register with additional type information, fill
975 in the struct pointed to by VECTYPE (if non-NULL).
977 This parser does not handle register list. */
980 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
981 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
983 struct neon_type_el atype
;
985 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
986 /*in_reg_list= */ FALSE
);
988 if (reg
== PARSE_FAIL
)
999 static inline bfd_boolean
1000 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1004 && e1
.defined
== e2
.defined
1005 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1008 /* This function parses the NEON register list. On success, it returns
1009 the parsed register list information in the following encoded format:
1011 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1012 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1014 The information of the register shape and/or index is returned in
1017 It returns PARSE_FAIL if the register list is invalid.
1019 The list contains one to four registers.
1020 Each register can be one of:
1023 All <T> should be identical.
1024 All <index> should be identical.
1025 There are restrictions on <Vt> numbers which are checked later
1026 (by reg_list_valid_p). */
1029 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1033 struct neon_type_el typeinfo
, typeinfo_first
;
1038 bfd_boolean error
= FALSE
;
1039 bfd_boolean expect_index
= FALSE
;
1043 set_syntax_error (_("expecting {"));
1049 typeinfo_first
.defined
= 0;
1050 typeinfo_first
.type
= NT_invtype
;
1051 typeinfo_first
.width
= -1;
1052 typeinfo_first
.index
= 0;
1061 str
++; /* skip over '-' */
1064 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1065 /*in_reg_list= */ TRUE
);
1066 if (val
== PARSE_FAIL
)
1068 set_first_syntax_error (_("invalid vector register in list"));
1072 /* reject [bhsd]n */
1073 if (typeinfo
.defined
== 0)
1075 set_first_syntax_error (_("invalid scalar register in list"));
1080 if (typeinfo
.defined
& NTA_HASINDEX
)
1081 expect_index
= TRUE
;
1085 if (val
< val_range
)
1087 set_first_syntax_error
1088 (_("invalid range in vector register list"));
1097 typeinfo_first
= typeinfo
;
1098 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1100 set_first_syntax_error
1101 (_("type mismatch in vector register list"));
1106 for (i
= val_range
; i
<= val
; i
++)
1108 ret_val
|= i
<< (5 * nb_regs
);
1113 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1115 skip_whitespace (str
);
1118 set_first_syntax_error (_("end of vector register list not found"));
1123 skip_whitespace (str
);
1127 if (skip_past_char (&str
, '['))
1131 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1132 if (exp
.X_op
!= O_constant
)
1134 set_first_syntax_error (_("constant expression required."));
1137 if (! skip_past_char (&str
, ']'))
1140 typeinfo_first
.index
= exp
.X_add_number
;
1144 set_first_syntax_error (_("expected index"));
1151 set_first_syntax_error (_("too many registers in vector register list"));
1154 else if (nb_regs
== 0)
1156 set_first_syntax_error (_("empty vector register list"));
1162 *vectype
= typeinfo_first
;
1164 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1167 /* Directives: register aliases. */
1170 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1175 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1178 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1181 /* Only warn about a redefinition if it's not defined as the
1183 else if (new->number
!= number
|| new->type
!= type
)
1184 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1189 name
= xstrdup (str
);
1190 new = xmalloc (sizeof (reg_entry
));
1193 new->number
= number
;
1195 new->builtin
= FALSE
;
1197 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1203 /* Look for the .req directive. This is of the form:
1205 new_register_name .req existing_register_name
1207 If we find one, or if it looks sufficiently like one that we want to
1208 handle any error here, return TRUE. Otherwise return FALSE. */
1211 create_register_alias (char *newname
, char *p
)
1213 const reg_entry
*old
;
1214 char *oldname
, *nbuf
;
1217 /* The input scrubber ensures that whitespace after the mnemonic is
1218 collapsed to single spaces. */
1220 if (strncmp (oldname
, " .req ", 6) != 0)
1224 if (*oldname
== '\0')
1227 old
= hash_find (aarch64_reg_hsh
, oldname
);
1230 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1234 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1235 the desired alias name, and p points to its end. If not, then
1236 the desired alias name is in the global original_case_string. */
1237 #ifdef TC_CASE_SENSITIVE
1240 newname
= original_case_string
;
1241 nlen
= strlen (newname
);
1244 nbuf
= xmemdup0 (newname
, nlen
);
1246 /* Create aliases under the new name as stated; an all-lowercase
1247 version of the new name; and an all-uppercase version of the new
1249 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1256 /* If this attempt to create an additional alias fails, do not bother
1257 trying to create the all-lower case alias. We will fail and issue
1258 a second, duplicate error message. This situation arises when the
1259 programmer does something like:
1262 The second .req creates the "Foo" alias but then fails to create
1263 the artificial FOO alias because it has already been created by the
1265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1272 for (p
= nbuf
; *p
; p
++)
1275 if (strncmp (nbuf
, newname
, nlen
))
1276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1283 /* Should never be called, as .req goes between the alias and the
1284 register name, not at the beginning of the line. */
1286 s_req (int a ATTRIBUTE_UNUSED
)
1288 as_bad (_("invalid syntax for .req directive"));
1291 /* The .unreq directive deletes an alias which was previously defined
1292 by .req. For example:
1298 s_unreq (int a ATTRIBUTE_UNUSED
)
1303 name
= input_line_pointer
;
1305 while (*input_line_pointer
!= 0
1306 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1307 ++input_line_pointer
;
1309 saved_char
= *input_line_pointer
;
1310 *input_line_pointer
= 0;
1313 as_bad (_("invalid syntax for .unreq directive"));
1316 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1319 as_bad (_("unknown register alias '%s'"), name
);
1320 else if (reg
->builtin
)
1321 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1328 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1329 free ((char *) reg
->name
);
1332 /* Also locate the all upper case and all lower case versions.
1333 Do not complain if we cannot find one or the other as it
1334 was probably deleted above. */
1336 nbuf
= strdup (name
);
1337 for (p
= nbuf
; *p
; p
++)
1339 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1342 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1343 free ((char *) reg
->name
);
1347 for (p
= nbuf
; *p
; p
++)
1349 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1352 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1353 free ((char *) reg
->name
);
1361 *input_line_pointer
= saved_char
;
1362 demand_empty_rest_of_line ();
1365 /* Directives: Instruction set selection. */
1368 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1369 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1370 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1371 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1373 /* Create a new mapping symbol for the transition to STATE. */
1376 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1379 const char *symname
;
1386 type
= BSF_NO_FLAGS
;
1390 type
= BSF_NO_FLAGS
;
1396 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1397 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1399 /* Save the mapping symbols for future reference. Also check that
1400 we do not place two mapping symbols at the same offset within a
1401 frag. We'll handle overlap between frags in
1402 check_mapping_symbols.
1404 If .fill or other data filling directive generates zero sized data,
1405 the mapping symbol for the following code will have the same value
1406 as the one generated for the data filling directive. In this case,
1407 we replace the old symbol with the new one at the same address. */
1410 if (frag
->tc_frag_data
.first_map
!= NULL
)
1412 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1413 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1416 frag
->tc_frag_data
.first_map
= symbolP
;
1418 if (frag
->tc_frag_data
.last_map
!= NULL
)
1420 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1421 S_GET_VALUE (symbolP
));
1422 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1423 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1426 frag
->tc_frag_data
.last_map
= symbolP
;
1429 /* We must sometimes convert a region marked as code to data during
1430 code alignment, if an odd number of bytes have to be padded. The
1431 code mapping symbol is pushed to an aligned address. */
1434 insert_data_mapping_symbol (enum mstate state
,
1435 valueT value
, fragS
* frag
, offsetT bytes
)
1437 /* If there was already a mapping symbol, remove it. */
1438 if (frag
->tc_frag_data
.last_map
!= NULL
1439 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1440 frag
->fr_address
+ value
)
1442 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1446 know (frag
->tc_frag_data
.first_map
== symp
);
1447 frag
->tc_frag_data
.first_map
= NULL
;
1449 frag
->tc_frag_data
.last_map
= NULL
;
1450 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1453 make_mapping_symbol (MAP_DATA
, value
, frag
);
1454 make_mapping_symbol (state
, value
+ bytes
, frag
);
1457 static void mapping_state_2 (enum mstate state
, int max_chars
);
1459 /* Set the mapping state to STATE. Only call this when about to
1460 emit some STATE bytes to the file. */
1463 mapping_state (enum mstate state
)
1465 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1467 if (state
== MAP_INSN
)
1468 /* AArch64 instructions require 4-byte alignment. When emitting
1469 instructions into any section, record the appropriate section
1471 record_alignment (now_seg
, 2);
1473 if (mapstate
== state
)
1474 /* The mapping symbol has already been emitted.
1475 There is nothing else to do. */
1478 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1479 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1480 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1481 evaluated later in the next else. */
1483 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1485 /* Only add the symbol if the offset is > 0:
1486 if we're at the first frag, check it's size > 0;
1487 if we're not at the first frag, then for sure
1488 the offset is > 0. */
1489 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1490 const int add_symbol
= (frag_now
!= frag_first
)
1491 || (frag_now_fix () > 0);
1494 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1498 mapping_state_2 (state
, 0);
1501 /* Same as mapping_state, but MAX_CHARS bytes have already been
1502 allocated. Put the mapping symbol that far back. */
1505 mapping_state_2 (enum mstate state
, int max_chars
)
1507 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1509 if (!SEG_NORMAL (now_seg
))
1512 if (mapstate
== state
)
1513 /* The mapping symbol has already been emitted.
1514 There is nothing else to do. */
1517 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1518 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1521 #define mapping_state(x) /* nothing */
1522 #define mapping_state_2(x, y) /* nothing */
1525 /* Directives: sectioning and alignment. */
1528 s_bss (int ignore ATTRIBUTE_UNUSED
)
1530 /* We don't support putting frags in the BSS segment, we fake it by
1531 marking in_bss, then looking at s_skip for clues. */
1532 subseg_set (bss_section
, 0);
1533 demand_empty_rest_of_line ();
1534 mapping_state (MAP_DATA
);
1538 s_even (int ignore ATTRIBUTE_UNUSED
)
1540 /* Never make frag if expect extra pass. */
1542 frag_align (1, 0, 0);
1544 record_alignment (now_seg
, 1);
1546 demand_empty_rest_of_line ();
1549 /* Directives: Literal pools. */
1551 static literal_pool
*
1552 find_literal_pool (int size
)
1556 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1558 if (pool
->section
== now_seg
1559 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1566 static literal_pool
*
1567 find_or_make_literal_pool (int size
)
1569 /* Next literal pool ID number. */
1570 static unsigned int latest_pool_num
= 1;
1573 pool
= find_literal_pool (size
);
1577 /* Create a new pool. */
1578 pool
= xmalloc (sizeof (*pool
));
1582 /* Currently we always put the literal pool in the current text
1583 section. If we were generating "small" model code where we
1584 knew that all code and initialised data was within 1MB then
1585 we could output literals to mergeable, read-only data
1588 pool
->next_free_entry
= 0;
1589 pool
->section
= now_seg
;
1590 pool
->sub_section
= now_subseg
;
1592 pool
->next
= list_of_pools
;
1593 pool
->symbol
= NULL
;
1595 /* Add it to the list. */
1596 list_of_pools
= pool
;
1599 /* New pools, and emptied pools, will have a NULL symbol. */
1600 if (pool
->symbol
== NULL
)
1602 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1603 (valueT
) 0, &zero_address_frag
);
1604 pool
->id
= latest_pool_num
++;
1611 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1612 Return TRUE on success, otherwise return FALSE. */
1614 add_to_lit_pool (expressionS
*exp
, int size
)
1619 pool
= find_or_make_literal_pool (size
);
1621 /* Check if this literal value is already in the pool. */
1622 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1624 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1626 if ((litexp
->X_op
== exp
->X_op
)
1627 && (exp
->X_op
== O_constant
)
1628 && (litexp
->X_add_number
== exp
->X_add_number
)
1629 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1632 if ((litexp
->X_op
== exp
->X_op
)
1633 && (exp
->X_op
== O_symbol
)
1634 && (litexp
->X_add_number
== exp
->X_add_number
)
1635 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1636 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1640 /* Do we need to create a new entry? */
1641 if (entry
== pool
->next_free_entry
)
1643 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1645 set_syntax_error (_("literal pool overflow"));
1649 pool
->literals
[entry
].exp
= *exp
;
1650 pool
->next_free_entry
+= 1;
1651 if (exp
->X_op
== O_big
)
1653 /* PR 16688: Bignums are held in a single global array. We must
1654 copy and preserve that value now, before it is overwritten. */
1655 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1656 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1657 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1660 pool
->literals
[entry
].bignum
= NULL
;
1663 exp
->X_op
= O_symbol
;
1664 exp
->X_add_number
= ((int) entry
) * size
;
1665 exp
->X_add_symbol
= pool
->symbol
;
1670 /* Can't use symbol_new here, so have to create a symbol and then at
1671 a later date assign it a value. Thats what these functions do. */
1674 symbol_locate (symbolS
* symbolP
,
1675 const char *name
,/* It is copied, the caller can modify. */
1676 segT segment
, /* Segment identifier (SEG_<something>). */
1677 valueT valu
, /* Symbol value. */
1678 fragS
* frag
) /* Associated fragment. */
1681 char *preserved_copy_of_name
;
1683 name_length
= strlen (name
) + 1; /* +1 for \0. */
1684 obstack_grow (¬es
, name
, name_length
);
1685 preserved_copy_of_name
= obstack_finish (¬es
);
1687 #ifdef tc_canonicalize_symbol_name
1688 preserved_copy_of_name
=
1689 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1692 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1694 S_SET_SEGMENT (symbolP
, segment
);
1695 S_SET_VALUE (symbolP
, valu
);
1696 symbol_clear_list_pointers (symbolP
);
1698 symbol_set_frag (symbolP
, frag
);
1700 /* Link to end of symbol chain. */
1702 extern int symbol_table_frozen
;
1704 if (symbol_table_frozen
)
1708 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1710 obj_symbol_new_hook (symbolP
);
1712 #ifdef tc_symbol_new_hook
1713 tc_symbol_new_hook (symbolP
);
1717 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1718 #endif /* DEBUG_SYMS */
1723 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1730 for (align
= 2; align
<= 4; align
++)
1732 int size
= 1 << align
;
1734 pool
= find_literal_pool (size
);
1735 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1738 mapping_state (MAP_DATA
);
1740 /* Align pool as you have word accesses.
1741 Only make a frag if we have to. */
1743 frag_align (align
, 0, 0);
1745 record_alignment (now_seg
, align
);
1747 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1749 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1750 (valueT
) frag_now_fix (), frag_now
);
1751 symbol_table_insert (pool
->symbol
);
1753 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1755 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1757 if (exp
->X_op
== O_big
)
1759 /* PR 16688: Restore the global bignum value. */
1760 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1761 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1762 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1765 /* First output the expression in the instruction to the pool. */
1766 emit_expr (exp
, size
); /* .word|.xword */
1768 if (exp
->X_op
== O_big
)
1770 free (pool
->literals
[entry
].bignum
);
1771 pool
->literals
[entry
].bignum
= NULL
;
1775 /* Mark the pool as empty. */
1776 pool
->next_free_entry
= 0;
1777 pool
->symbol
= NULL
;
1782 /* Forward declarations for functions below, in the MD interface
1784 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1785 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1787 /* Directives: Data. */
1788 /* N.B. the support for relocation suffix in this directive needs to be
1789 implemented properly. */
1792 s_aarch64_elf_cons (int nbytes
)
1796 #ifdef md_flush_pending_output
1797 md_flush_pending_output ();
1800 if (is_it_end_of_statement ())
1802 demand_empty_rest_of_line ();
1806 #ifdef md_cons_align
1807 md_cons_align (nbytes
);
1810 mapping_state (MAP_DATA
);
1813 struct reloc_table_entry
*reloc
;
1817 if (exp
.X_op
!= O_symbol
)
1818 emit_expr (&exp
, (unsigned int) nbytes
);
1821 skip_past_char (&input_line_pointer
, '#');
1822 if (skip_past_char (&input_line_pointer
, ':'))
1824 reloc
= find_reloc_table_entry (&input_line_pointer
);
1826 as_bad (_("unrecognized relocation suffix"));
1828 as_bad (_("unimplemented relocation suffix"));
1829 ignore_rest_of_line ();
1833 emit_expr (&exp
, (unsigned int) nbytes
);
1836 while (*input_line_pointer
++ == ',');
1838 /* Put terminator back into stream. */
1839 input_line_pointer
--;
1840 demand_empty_rest_of_line ();
1843 #endif /* OBJ_ELF */
1845 /* Output a 32-bit word, but mark as an instruction. */
1848 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1852 #ifdef md_flush_pending_output
1853 md_flush_pending_output ();
1856 if (is_it_end_of_statement ())
1858 demand_empty_rest_of_line ();
1862 /* Sections are assumed to start aligned. In executable section, there is no
1863 MAP_DATA symbol pending. So we only align the address during
1864 MAP_DATA --> MAP_INSN transition.
1865 For other sections, this is not guaranteed. */
1866 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1867 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1868 frag_align_code (2, 0);
1871 mapping_state (MAP_INSN
);
1877 if (exp
.X_op
!= O_constant
)
1879 as_bad (_("constant expression required"));
1880 ignore_rest_of_line ();
1884 if (target_big_endian
)
1886 unsigned int val
= exp
.X_add_number
;
1887 exp
.X_add_number
= SWAP_32 (val
);
1889 emit_expr (&exp
, 4);
1891 while (*input_line_pointer
++ == ',');
1893 /* Put terminator back into stream. */
1894 input_line_pointer
--;
1895 demand_empty_rest_of_line ();
1899 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1902 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1908 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1909 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1911 demand_empty_rest_of_line ();
1914 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1917 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1921 /* Since we're just labelling the code, there's no need to define a
1924 /* Make sure there is enough room in this frag for the following
1925 blr. This trick only works if the blr follows immediately after
1926 the .tlsdesc directive. */
1928 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1929 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1931 demand_empty_rest_of_line ();
1934 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1937 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
1943 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1944 BFD_RELOC_AARCH64_TLSDESC_LDR
);
1946 demand_empty_rest_of_line ();
1948 #endif /* OBJ_ELF */
1950 static void s_aarch64_arch (int);
1951 static void s_aarch64_cpu (int);
1952 static void s_aarch64_arch_extension (int);
1954 /* This table describes all the machine specific pseudo-ops the assembler
1955 has to support. The fields are:
1956 pseudo-op name without dot
1957 function to call to execute this pseudo-op
1958 Integer arg to pass to the function. */
1960 const pseudo_typeS md_pseudo_table
[] = {
1961 /* Never called because '.req' does not start a line. */
1963 {"unreq", s_unreq
, 0},
1965 {"even", s_even
, 0},
1966 {"ltorg", s_ltorg
, 0},
1967 {"pool", s_ltorg
, 0},
1968 {"cpu", s_aarch64_cpu
, 0},
1969 {"arch", s_aarch64_arch
, 0},
1970 {"arch_extension", s_aarch64_arch_extension
, 0},
1971 {"inst", s_aarch64_inst
, 0},
1973 {"tlsdescadd", s_tlsdescadd
, 0},
1974 {"tlsdesccall", s_tlsdesccall
, 0},
1975 {"tlsdescldr", s_tlsdescldr
, 0},
1976 {"word", s_aarch64_elf_cons
, 4},
1977 {"long", s_aarch64_elf_cons
, 4},
1978 {"xword", s_aarch64_elf_cons
, 8},
1979 {"dword", s_aarch64_elf_cons
, 8},
1985 /* Check whether STR points to a register name followed by a comma or the
1986 end of line; REG_TYPE indicates which register types are checked
1987 against. Return TRUE if STR is such a register name; otherwise return
1988 FALSE. The function does not intend to produce any diagnostics, but since
1989 the register parser aarch64_reg_parse, which is called by this function,
1990 does produce diagnostics, we call clear_error to clear any diagnostics
1991 that may be generated by aarch64_reg_parse.
1992 Also, the function returns FALSE directly if there is any user error
1993 present at the function entry. This prevents the existing diagnostics
1994 state from being spoiled.
1995 The function currently serves parse_constant_immediate and
1996 parse_big_immediate only. */
1998 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2002 /* Prevent the diagnostics state from being spoiled. */
2006 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2008 /* Clear the parsing error that may be set by the reg parser. */
2011 if (reg
== PARSE_FAIL
)
2014 skip_whitespace (str
);
2015 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2021 /* Parser functions used exclusively in instruction operands. */
2023 /* Parse an immediate expression which may not be constant.
2025 To prevent the expression parser from pushing a register name
2026 into the symbol table as an undefined symbol, firstly a check is
2027 done to find out whether STR is a valid register name followed
2028 by a comma or the end of line. Return FALSE if STR is such a
2032 parse_immediate_expression (char **str
, expressionS
*exp
)
2034 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2036 set_recoverable_error (_("immediate operand required"));
2040 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2042 if (exp
->X_op
== O_absent
)
2044 set_fatal_syntax_error (_("missing immediate expression"));
2051 /* Constant immediate-value read function for use in insn parsing.
2052 STR points to the beginning of the immediate (with the optional
2053 leading #); *VAL receives the value.
2055 Return TRUE on success; otherwise return FALSE. */
2058 parse_constant_immediate (char **str
, int64_t * val
)
2062 if (! parse_immediate_expression (str
, &exp
))
2065 if (exp
.X_op
!= O_constant
)
2067 set_syntax_error (_("constant expression required"));
2071 *val
= exp
.X_add_number
;
2076 encode_imm_float_bits (uint32_t imm
)
2078 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2079 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2082 /* Return TRUE if the single-precision floating-point value encoded in IMM
2083 can be expressed in the AArch64 8-bit signed floating-point format with
2084 3-bit exponent and normalized 4 bits of precision; in other words, the
2085 floating-point value must be expressable as
2086 (+/-) n / 16 * power (2, r)
2087 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2090 aarch64_imm_float_p (uint32_t imm
)
2092 /* If a single-precision floating-point value has the following bit
2093 pattern, it can be expressed in the AArch64 8-bit floating-point
2096 3 32222222 2221111111111
2097 1 09876543 21098765432109876543210
2098 n Eeeeeexx xxxx0000000000000000000
2100 where n, e and each x are either 0 or 1 independently, with
2105 /* Prepare the pattern for 'Eeeeee'. */
2106 if (((imm
>> 30) & 0x1) == 0)
2107 pattern
= 0x3e000000;
2109 pattern
= 0x40000000;
2111 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2112 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2115 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2117 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2118 8-bit signed floating-point format with 3-bit exponent and normalized 4
2119 bits of precision (i.e. can be used in an FMOV instruction); return the
2120 equivalent single-precision encoding in *FPWORD.
2122 Otherwise return FALSE. */
2125 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2127 /* If a double-precision floating-point value has the following bit
2128 pattern, it can be expressed in the AArch64 8-bit floating-point
2131 6 66655555555 554444444...21111111111
2132 3 21098765432 109876543...098765432109876543210
2133 n Eeeeeeeeexx xxxx00000...000000000000000000000
2135 where n, e and each x are either 0 or 1 independently, with
2139 uint32_t high32
= imm
>> 32;
2141 /* Lower 32 bits need to be 0s. */
2142 if ((imm
& 0xffffffff) != 0)
2145 /* Prepare the pattern for 'Eeeeeeeee'. */
2146 if (((high32
>> 30) & 0x1) == 0)
2147 pattern
= 0x3fc00000;
2149 pattern
= 0x40000000;
2151 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2152 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2154 /* Convert to the single-precision encoding.
2156 n Eeeeeeeeexx xxxx00000...000000000000000000000
2158 n Eeeeeexx xxxx0000000000000000000. */
2159 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2160 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2167 /* Parse a floating-point immediate. Return TRUE on success and return the
2168 value in *IMMED in the format of IEEE754 single-precision encoding.
2169 *CCP points to the start of the string; DP_P is TRUE when the immediate
2170 is expected to be in double-precision (N.B. this only matters when
2171 hexadecimal representation is involved).
2173 N.B. 0.0 is accepted by this function. */
2176 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2180 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2181 int found_fpchar
= 0;
2183 unsigned fpword
= 0;
2184 bfd_boolean hex_p
= FALSE
;
2186 skip_past_char (&str
, '#');
2189 skip_whitespace (fpnum
);
2191 if (strncmp (fpnum
, "0x", 2) == 0)
2193 /* Support the hexadecimal representation of the IEEE754 encoding.
2194 Double-precision is expected when DP_P is TRUE, otherwise the
2195 representation should be in single-precision. */
2196 if (! parse_constant_immediate (&str
, &val
))
2201 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2204 else if ((uint64_t) val
> 0xffffffff)
2213 /* We must not accidentally parse an integer as a floating-point number.
2214 Make sure that the value we parse is not an integer by checking for
2215 special characters '.' or 'e'. */
2216 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2217 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2231 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2234 /* Our FP word must be 32 bits (single-precision FP). */
2235 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2237 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2242 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2250 set_fatal_syntax_error (_("invalid floating-point constant"));
2254 /* Less-generic immediate-value read function with the possibility of loading
2255 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2258 To prevent the expression parser from pushing a register name into the
2259 symbol table as an undefined symbol, a check is firstly done to find
2260 out whether STR is a valid register name followed by a comma or the end
2261 of line. Return FALSE if STR is such a register. */
2264 parse_big_immediate (char **str
, int64_t *imm
)
2268 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2270 set_syntax_error (_("immediate operand required"));
2274 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2276 if (inst
.reloc
.exp
.X_op
== O_constant
)
2277 *imm
= inst
.reloc
.exp
.X_add_number
;
2284 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2285 if NEED_LIBOPCODES is non-zero, the fixup will need
2286 assistance from the libopcodes. */
2289 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2290 const aarch64_opnd_info
*operand
,
2291 int need_libopcodes_p
)
2293 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2294 reloc
->opnd
= operand
->type
;
2295 if (need_libopcodes_p
)
2296 reloc
->need_libopcodes_p
= 1;
2299 /* Return TRUE if the instruction needs to be fixed up later internally by
2300 the GAS; otherwise return FALSE. */
2302 static inline bfd_boolean
2303 aarch64_gas_internal_fixup_p (void)
2305 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2308 /* Assign the immediate value to the relavant field in *OPERAND if
2309 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2310 needs an internal fixup in a later stage.
2311 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2312 IMM.VALUE that may get assigned with the constant. */
2314 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2315 aarch64_opnd_info
*operand
,
2317 int need_libopcodes_p
,
2320 if (reloc
->exp
.X_op
== O_constant
)
2323 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2325 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2326 reloc
->type
= BFD_RELOC_UNUSED
;
2330 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2331 /* Tell libopcodes to ignore this operand or not. This is helpful
2332 when one of the operands needs to be fixed up later but we need
2333 libopcodes to check the other operands. */
2334 operand
->skip
= skip_p
;
2338 /* Relocation modifiers. Each entry in the table contains the textual
2339 name for the relocation which may be placed before a symbol used as
2340 a load/store offset, or add immediate. It must be surrounded by a
2341 leading and trailing colon, for example:
2343 ldr x0, [x1, #:rello:varsym]
2344 add x0, x1, #:rello:varsym */
2346 struct reloc_table_entry
2350 bfd_reloc_code_real_type adr_type
;
2351 bfd_reloc_code_real_type adrp_type
;
2352 bfd_reloc_code_real_type movw_type
;
2353 bfd_reloc_code_real_type add_type
;
2354 bfd_reloc_code_real_type ldst_type
;
2355 bfd_reloc_code_real_type ld_literal_type
;
2358 static struct reloc_table_entry reloc_table
[] = {
2359 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2364 BFD_RELOC_AARCH64_ADD_LO12
,
2365 BFD_RELOC_AARCH64_LDST_LO12
,
2368 /* Higher 21 bits of pc-relative page offset: ADRP */
2371 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2377 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2380 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2386 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2390 BFD_RELOC_AARCH64_MOVW_G0
,
2395 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2399 BFD_RELOC_AARCH64_MOVW_G0_S
,
2404 /* Less significant bits 0-15 of address/value: MOVK, no check */
2408 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2413 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2417 BFD_RELOC_AARCH64_MOVW_G1
,
2422 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2426 BFD_RELOC_AARCH64_MOVW_G1_S
,
2431 /* Less significant bits 16-31 of address/value: MOVK, no check */
2435 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2440 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2444 BFD_RELOC_AARCH64_MOVW_G2
,
2449 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2453 BFD_RELOC_AARCH64_MOVW_G2_S
,
2458 /* Less significant bits 32-47 of address/value: MOVK, no check */
2462 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2467 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2471 BFD_RELOC_AARCH64_MOVW_G3
,
2476 /* Get to the page containing GOT entry for a symbol. */
2479 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2483 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2485 /* 12 bit offset into the page containing GOT entry for that symbol. */
2491 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2494 /* 0-15 bits of address/value: MOVk, no check. */
2498 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2503 /* Most significant bits 16-31 of address/value: MOVZ. */
2507 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2512 /* 15 bit offset into the page containing GOT entry for that symbol. */
2518 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2521 /* Get to the page containing GOT TLS entry for a symbol */
2522 {"gottprel_g0_nc", 0,
2525 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2530 /* Get to the page containing GOT TLS entry for a symbol */
2534 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2539 /* Get to the page containing GOT TLS entry for a symbol */
2541 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2542 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2548 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2553 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2557 /* Lower 16 bits address/value: MOVk. */
2561 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2566 /* Most significant bits 16-31 of address/value: MOVZ. */
2570 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2575 /* Get to the page containing GOT TLS entry for a symbol */
2577 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2578 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2582 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2584 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2589 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2590 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2593 /* Get to the page containing GOT TLS entry for a symbol.
2594 The same as GD, we allocate two consecutive GOT slots
2595 for module index and module offset, the only difference
2596 with GD is the module offset should be intialized to
2597 zero without any outstanding runtime relocation. */
2599 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2600 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2606 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2607 {"tlsldm_lo12_nc", 0,
2611 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2615 /* 12 bit offset into the module TLS base address. */
2620 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2621 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2624 /* Same as dtprel_lo12, no overflow check. */
2625 {"dtprel_lo12_nc", 0,
2629 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2630 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2633 /* bits[23:12] of offset to the module TLS base address. */
2638 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2642 /* bits[15:0] of offset to the module TLS base address. */
2646 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2651 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2655 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2660 /* bits[31:16] of offset to the module TLS base address. */
2664 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2669 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2673 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2678 /* bits[47:32] of offset to the module TLS base address. */
2682 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2687 /* Lower 16 bit offset into GOT entry for a symbol */
2688 {"tlsdesc_off_g0_nc", 0,
2691 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2696 /* Higher 16 bit offset into GOT entry for a symbol */
2697 {"tlsdesc_off_g1", 0,
2700 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2705 /* Get to the page containing GOT TLS entry for a symbol */
2708 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2712 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2714 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2715 {"gottprel_lo12", 0,
2720 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2723 /* Get tp offset for a symbol. */
2728 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2732 /* Get tp offset for a symbol. */
2737 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2741 /* Get tp offset for a symbol. */
2746 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2750 /* Get tp offset for a symbol. */
2751 {"tprel_lo12_nc", 0,
2755 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2759 /* Most significant bits 32-47 of address/value: MOVZ. */
2763 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2768 /* Most significant bits 16-31 of address/value: MOVZ. */
2772 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2777 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2781 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2786 /* Most significant bits 0-15 of address/value: MOVZ. */
2790 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2795 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2799 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2804 /* 15bit offset from got entry to base address of GOT table. */
2810 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2813 /* 14bit offset from got entry to base address of GOT table. */
2819 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2823 /* Given the address of a pointer pointing to the textual name of a
2824 relocation as may appear in assembler source, attempt to find its
2825 details in reloc_table. The pointer will be updated to the character
2826 after the trailing colon. On failure, NULL will be returned;
2827 otherwise return the reloc_table_entry. */
2829 static struct reloc_table_entry
*
2830 find_reloc_table_entry (char **str
)
2833 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2835 int length
= strlen (reloc_table
[i
].name
);
2837 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2838 && (*str
)[length
] == ':')
2840 *str
+= (length
+ 1);
2841 return &reloc_table
[i
];
2848 /* Mode argument to parse_shift and parser_shifter_operand. */
2849 enum parse_shift_mode
2851 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2853 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2855 SHIFTED_LSL
, /* bare "lsl #n" */
2856 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2857 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2860 /* Parse a <shift> operator on an AArch64 data processing instruction.
2861 Return TRUE on success; otherwise return FALSE. */
2863 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2865 const struct aarch64_name_value_pair
*shift_op
;
2866 enum aarch64_modifier_kind kind
;
2872 for (p
= *str
; ISALPHA (*p
); p
++)
2877 set_syntax_error (_("shift expression expected"));
2881 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2883 if (shift_op
== NULL
)
2885 set_syntax_error (_("shift operator expected"));
2889 kind
= aarch64_get_operand_modifier (shift_op
);
2891 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2893 set_syntax_error (_("invalid use of 'MSL'"));
2899 case SHIFTED_LOGIC_IMM
:
2900 if (aarch64_extend_operator_p (kind
) == TRUE
)
2902 set_syntax_error (_("extending shift is not permitted"));
2907 case SHIFTED_ARITH_IMM
:
2908 if (kind
== AARCH64_MOD_ROR
)
2910 set_syntax_error (_("'ROR' shift is not permitted"));
2916 if (kind
!= AARCH64_MOD_LSL
)
2918 set_syntax_error (_("only 'LSL' shift is permitted"));
2923 case SHIFTED_REG_OFFSET
:
2924 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2925 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2927 set_fatal_syntax_error
2928 (_("invalid shift for the register offset addressing mode"));
2933 case SHIFTED_LSL_MSL
:
2934 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2936 set_syntax_error (_("invalid shift operator"));
2945 /* Whitespace can appear here if the next thing is a bare digit. */
2946 skip_whitespace (p
);
2948 /* Parse shift amount. */
2950 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2951 exp
.X_op
= O_absent
;
2954 if (is_immediate_prefix (*p
))
2959 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2961 if (exp
.X_op
== O_absent
)
2963 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2965 set_syntax_error (_("missing shift amount"));
2968 operand
->shifter
.amount
= 0;
2970 else if (exp
.X_op
!= O_constant
)
2972 set_syntax_error (_("constant shift amount required"));
2975 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2977 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2982 operand
->shifter
.amount
= exp
.X_add_number
;
2983 operand
->shifter
.amount_present
= 1;
2986 operand
->shifter
.operator_present
= 1;
2987 operand
->shifter
.kind
= kind
;
2993 /* Parse a <shifter_operand> for a data processing instruction:
2996 #<immediate>, LSL #imm
2998 Validation of immediate operands is deferred to md_apply_fix.
3000 Return TRUE on success; otherwise return FALSE. */
3003 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3004 enum parse_shift_mode mode
)
3008 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3013 /* Accept an immediate expression. */
3014 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3017 /* Accept optional LSL for arithmetic immediate values. */
3018 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3019 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3022 /* Not accept any shifter for logical immediate values. */
3023 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3024 && parse_shift (&p
, operand
, mode
))
3026 set_syntax_error (_("unexpected shift operator"));
3034 /* Parse a <shifter_operand> for a data processing instruction:
3039 #<immediate>, LSL #imm
3041 where <shift> is handled by parse_shift above, and the last two
3042 cases are handled by the function above.
3044 Validation of immediate operands is deferred to md_apply_fix.
3046 Return TRUE on success; otherwise return FALSE. */
3049 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3050 enum parse_shift_mode mode
)
3053 int isreg32
, isregzero
;
3054 enum aarch64_operand_class opd_class
3055 = aarch64_get_operand_class (operand
->type
);
3058 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
3060 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3062 set_syntax_error (_("unexpected register in the immediate operand"));
3066 if (!isregzero
&& reg
== REG_SP
)
3068 set_syntax_error (BAD_SP
);
3072 operand
->reg
.regno
= reg
;
3073 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
3075 /* Accept optional shift operation on register. */
3076 if (! skip_past_comma (str
))
3079 if (! parse_shift (str
, operand
, mode
))
3084 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3087 (_("integer register expected in the extended/shifted operand "
3092 /* We have a shifted immediate variable. */
3093 return parse_shifter_operand_imm (str
, operand
, mode
);
3096 /* Return TRUE on success; return FALSE otherwise. */
3099 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3100 enum parse_shift_mode mode
)
3104 /* Determine if we have the sequence of characters #: or just :
3105 coming next. If we do, then we check for a :rello: relocation
3106 modifier. If we don't, punt the whole lot to
3107 parse_shifter_operand. */
3109 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3111 struct reloc_table_entry
*entry
;
3119 /* Try to parse a relocation. Anything else is an error. */
3120 if (!(entry
= find_reloc_table_entry (str
)))
3122 set_syntax_error (_("unknown relocation modifier"));
3126 if (entry
->add_type
== 0)
3129 (_("this relocation modifier is not allowed on this instruction"));
3133 /* Save str before we decompose it. */
3136 /* Next, we parse the expression. */
3137 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3140 /* Record the relocation type (use the ADD variant here). */
3141 inst
.reloc
.type
= entry
->add_type
;
3142 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3144 /* If str is empty, we've reached the end, stop here. */
3148 /* Otherwise, we have a shifted reloc modifier, so rewind to
3149 recover the variable name and continue parsing for the shifter. */
3151 return parse_shifter_operand_imm (str
, operand
, mode
);
3154 return parse_shifter_operand (str
, operand
, mode
);
3157 /* Parse all forms of an address expression. Information is written
3158 to *OPERAND and/or inst.reloc.
3160 The A64 instruction set has the following addressing modes:
3163 [base] // in SIMD ld/st structure
3164 [base{,#0}] // in ld/st exclusive
3166 [base,Xm{,LSL #imm}]
3167 [base,Xm,SXTX {#imm}]
3168 [base,Wm,(S|U)XTW {#imm}]
3173 [base],Xm // in SIMD ld/st structure
3174 PC-relative (literal)
3178 (As a convenience, the notation "=immediate" is permitted in conjunction
3179 with the pc-relative literal load instructions to automatically place an
3180 immediate value or symbolic address in a nearby literal pool and generate
3181 a hidden label which references it.)
3183 Upon a successful parsing, the address structure in *OPERAND will be
3184 filled in the following way:
3186 .base_regno = <base>
3187 .offset.is_reg // 1 if the offset is a register
3189 .offset.regno = <Rm>
3191 For different addressing modes defined in the A64 ISA:
3194 .pcrel=0; .preind=1; .postind=0; .writeback=0
3196 .pcrel=0; .preind=1; .postind=0; .writeback=1
3198 .pcrel=0; .preind=0; .postind=1; .writeback=1
3199 PC-relative (literal)
3200 .pcrel=1; .preind=1; .postind=0; .writeback=0
3202 The shift/extension information, if any, will be stored in .shifter.
3204 It is the caller's responsibility to check for addressing modes not
3205 supported by the instruction, and to set inst.reloc.type. */
3208 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3209 int accept_reg_post_index
)
3213 int isreg32
, isregzero
;
3214 expressionS
*exp
= &inst
.reloc
.exp
;
3216 if (! skip_past_char (&p
, '['))
3218 /* =immediate or label. */
3219 operand
->addr
.pcrel
= 1;
3220 operand
->addr
.preind
= 1;
3222 /* #:<reloc_op>:<symbol> */
3223 skip_past_char (&p
, '#');
3224 if (reloc
&& skip_past_char (&p
, ':'))
3226 bfd_reloc_code_real_type ty
;
3227 struct reloc_table_entry
*entry
;
3229 /* Try to parse a relocation modifier. Anything else is
3231 entry
= find_reloc_table_entry (&p
);
3234 set_syntax_error (_("unknown relocation modifier"));
3238 switch (operand
->type
)
3240 case AARCH64_OPND_ADDR_PCREL21
:
3242 ty
= entry
->adr_type
;
3246 ty
= entry
->ld_literal_type
;
3253 (_("this relocation modifier is not allowed on this "
3259 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3261 set_syntax_error (_("invalid relocation expression"));
3265 /* #:<reloc_op>:<expr> */
3266 /* Record the relocation type. */
3267 inst
.reloc
.type
= ty
;
3268 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3273 if (skip_past_char (&p
, '='))
3274 /* =immediate; need to generate the literal in the literal pool. */
3275 inst
.gen_lit_pool
= 1;
3277 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3279 set_syntax_error (_("invalid address"));
3290 /* Accept SP and reject ZR */
3291 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3292 if (reg
== PARSE_FAIL
|| isreg32
)
3294 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3297 operand
->addr
.base_regno
= reg
;
3300 if (skip_past_comma (&p
))
3303 operand
->addr
.preind
= 1;
3305 /* Reject SP and accept ZR */
3306 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3307 if (reg
!= PARSE_FAIL
)
3310 operand
->addr
.offset
.regno
= reg
;
3311 operand
->addr
.offset
.is_reg
= 1;
3312 /* Shifted index. */
3313 if (skip_past_comma (&p
))
3316 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3317 /* Use the diagnostics set in parse_shift, so not set new
3318 error message here. */
3322 [base,Xm{,LSL #imm}]
3323 [base,Xm,SXTX {#imm}]
3324 [base,Wm,(S|U)XTW {#imm}] */
3325 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3326 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3327 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3331 set_syntax_error (_("invalid use of 32-bit register offset"));
3337 set_syntax_error (_("invalid use of 64-bit register offset"));
3343 /* [Xn,#:<reloc_op>:<symbol> */
3344 skip_past_char (&p
, '#');
3345 if (reloc
&& skip_past_char (&p
, ':'))
3347 struct reloc_table_entry
*entry
;
3349 /* Try to parse a relocation modifier. Anything else is
3351 if (!(entry
= find_reloc_table_entry (&p
)))
3353 set_syntax_error (_("unknown relocation modifier"));
3357 if (entry
->ldst_type
== 0)
3360 (_("this relocation modifier is not allowed on this "
3365 /* [Xn,#:<reloc_op>: */
3366 /* We now have the group relocation table entry corresponding to
3367 the name in the assembler source. Next, we parse the
3369 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3371 set_syntax_error (_("invalid relocation expression"));
3375 /* [Xn,#:<reloc_op>:<expr> */
3376 /* Record the load/store relocation type. */
3377 inst
.reloc
.type
= entry
->ldst_type
;
3378 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3380 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3382 set_syntax_error (_("invalid expression in the address"));
3389 if (! skip_past_char (&p
, ']'))
3391 set_syntax_error (_("']' expected"));
3395 if (skip_past_char (&p
, '!'))
3397 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3399 set_syntax_error (_("register offset not allowed in pre-indexed "
3400 "addressing mode"));
3404 operand
->addr
.writeback
= 1;
3406 else if (skip_past_comma (&p
))
3409 operand
->addr
.postind
= 1;
3410 operand
->addr
.writeback
= 1;
3412 if (operand
->addr
.preind
)
3414 set_syntax_error (_("cannot combine pre- and post-indexing"));
3418 if (accept_reg_post_index
3419 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3420 &isregzero
)) != PARSE_FAIL
)
3425 set_syntax_error (_("invalid 32-bit register offset"));
3428 operand
->addr
.offset
.regno
= reg
;
3429 operand
->addr
.offset
.is_reg
= 1;
3431 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3434 set_syntax_error (_("invalid expression in the address"));
3439 /* If at this point neither .preind nor .postind is set, we have a
3440 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3441 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3443 if (operand
->addr
.writeback
)
3446 set_syntax_error (_("missing offset in the pre-indexed address"));
3449 operand
->addr
.preind
= 1;
3450 inst
.reloc
.exp
.X_op
= O_constant
;
3451 inst
.reloc
.exp
.X_add_number
= 0;
3458 /* Return TRUE on success; otherwise return FALSE. */
3460 parse_address (char **str
, aarch64_opnd_info
*operand
,
3461 int accept_reg_post_index
)
3463 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3466 /* Return TRUE on success; otherwise return FALSE. */
3468 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3470 return parse_address_main (str
, operand
, 1, 0);
3473 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3474 Return TRUE on success; otherwise return FALSE. */
3476 parse_half (char **str
, int *internal_fixup_p
)
3480 skip_past_char (&p
, '#');
3482 gas_assert (internal_fixup_p
);
3483 *internal_fixup_p
= 0;
3487 struct reloc_table_entry
*entry
;
3489 /* Try to parse a relocation. Anything else is an error. */
3491 if (!(entry
= find_reloc_table_entry (&p
)))
3493 set_syntax_error (_("unknown relocation modifier"));
3497 if (entry
->movw_type
== 0)
3500 (_("this relocation modifier is not allowed on this instruction"));
3504 inst
.reloc
.type
= entry
->movw_type
;
3507 *internal_fixup_p
= 1;
3509 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3516 /* Parse an operand for an ADRP instruction:
3518 Return TRUE on success; otherwise return FALSE. */
3521 parse_adrp (char **str
)
3528 struct reloc_table_entry
*entry
;
3530 /* Try to parse a relocation. Anything else is an error. */
3532 if (!(entry
= find_reloc_table_entry (&p
)))
3534 set_syntax_error (_("unknown relocation modifier"));
3538 if (entry
->adrp_type
== 0)
3541 (_("this relocation modifier is not allowed on this instruction"));
3545 inst
.reloc
.type
= entry
->adrp_type
;
3548 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3550 inst
.reloc
.pc_rel
= 1;
3552 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3559 /* Miscellaneous. */
3561 /* Parse an option for a preload instruction. Returns the encoding for the
3562 option, or PARSE_FAIL. */
3565 parse_pldop (char **str
)
3568 const struct aarch64_name_value_pair
*o
;
3571 while (ISALNUM (*q
))
3574 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3582 /* Parse an option for a barrier instruction. Returns the encoding for the
3583 option, or PARSE_FAIL. */
3586 parse_barrier (char **str
)
3589 const asm_barrier_opt
*o
;
3592 while (ISALPHA (*q
))
3595 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3603 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3604 return 0 if successful. Otherwise return PARSE_FAIL. */
3607 parse_barrier_psb (char **str
,
3608 const struct aarch64_name_value_pair
** hint_opt
)
3611 const struct aarch64_name_value_pair
*o
;
3614 while (ISALPHA (*q
))
3617 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3620 set_fatal_syntax_error
3621 ( _("unknown or missing option to PSB"));
3625 if (o
->value
!= 0x11)
3627 /* PSB only accepts option name 'CSYNC'. */
3629 (_("the specified option is not accepted for PSB"));
3638 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3639 Returns the encoding for the option, or PARSE_FAIL.
3641 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3642 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3644 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3645 field, otherwise as a system register.
3649 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3650 int imple_defined_p
, int pstatefield_p
)
3654 const aarch64_sys_reg
*o
;
3658 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3660 *p
++ = TOLOWER (*q
);
3662 /* Assert that BUF be large enough. */
3663 gas_assert (p
- buf
== q
- *str
);
3665 o
= hash_find (sys_regs
, buf
);
3668 if (!imple_defined_p
)
3672 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3673 unsigned int op0
, op1
, cn
, cm
, op2
;
3675 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3678 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3680 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3685 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3686 as_bad (_("selected processor does not support PSTATE field "
3688 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3689 as_bad (_("selected processor does not support system register "
3691 if (aarch64_sys_reg_deprecated_p (o
))
3692 as_warn (_("system register name '%s' is deprecated and may be "
3693 "removed in a future release"), buf
);
3701 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3702 for the option, or NULL. */
3704 static const aarch64_sys_ins_reg
*
3705 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3709 const aarch64_sys_ins_reg
*o
;
3712 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3714 *p
++ = TOLOWER (*q
);
3717 o
= hash_find (sys_ins_regs
, buf
);
3721 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3722 as_bad (_("selected processor does not support system register "
3729 #define po_char_or_fail(chr) do { \
3730 if (! skip_past_char (&str, chr)) \
3734 #define po_reg_or_fail(regtype) do { \
3735 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3736 if (val == PARSE_FAIL) \
3738 set_default_error (); \
3743 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3744 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3745 &isreg32, &isregzero); \
3746 if (val == PARSE_FAIL) \
3748 set_default_error (); \
3751 info->reg.regno = val; \
3753 info->qualifier = AARCH64_OPND_QLF_W; \
3755 info->qualifier = AARCH64_OPND_QLF_X; \
3758 #define po_imm_nc_or_fail() do { \
3759 if (! parse_constant_immediate (&str, &val)) \
3763 #define po_imm_or_fail(min, max) do { \
3764 if (! parse_constant_immediate (&str, &val)) \
3766 if (val < min || val > max) \
3768 set_fatal_syntax_error (_("immediate value out of range "\
3769 #min " to "#max)); \
3774 #define po_misc_or_fail(expr) do { \
3779 /* encode the 12-bit imm field of Add/sub immediate */
3780 static inline uint32_t
3781 encode_addsub_imm (uint32_t imm
)
3786 /* encode the shift amount field of Add/sub immediate */
3787 static inline uint32_t
3788 encode_addsub_imm_shift_amount (uint32_t cnt
)
3794 /* encode the imm field of Adr instruction */
3795 static inline uint32_t
3796 encode_adr_imm (uint32_t imm
)
3798 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3799 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3802 /* encode the immediate field of Move wide immediate */
3803 static inline uint32_t
3804 encode_movw_imm (uint32_t imm
)
3809 /* encode the 26-bit offset of unconditional branch */
3810 static inline uint32_t
3811 encode_branch_ofs_26 (uint32_t ofs
)
3813 return ofs
& ((1 << 26) - 1);
3816 /* encode the 19-bit offset of conditional branch and compare & branch */
3817 static inline uint32_t
3818 encode_cond_branch_ofs_19 (uint32_t ofs
)
3820 return (ofs
& ((1 << 19) - 1)) << 5;
3823 /* encode the 19-bit offset of ld literal */
3824 static inline uint32_t
3825 encode_ld_lit_ofs_19 (uint32_t ofs
)
3827 return (ofs
& ((1 << 19) - 1)) << 5;
3830 /* Encode the 14-bit offset of test & branch. */
3831 static inline uint32_t
3832 encode_tst_branch_ofs_14 (uint32_t ofs
)
3834 return (ofs
& ((1 << 14) - 1)) << 5;
3837 /* Encode the 16-bit imm field of svc/hvc/smc. */
3838 static inline uint32_t
3839 encode_svc_imm (uint32_t imm
)
3844 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3845 static inline uint32_t
3846 reencode_addsub_switch_add_sub (uint32_t opcode
)
3848 return opcode
^ (1 << 30);
3851 static inline uint32_t
3852 reencode_movzn_to_movz (uint32_t opcode
)
3854 return opcode
| (1 << 30);
3857 static inline uint32_t
3858 reencode_movzn_to_movn (uint32_t opcode
)
3860 return opcode
& ~(1 << 30);
3863 /* Overall per-instruction processing. */
3865 /* We need to be able to fix up arbitrary expressions in some statements.
3866 This is so that we can handle symbols that are an arbitrary distance from
3867 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3868 which returns part of an address in a form which will be valid for
3869 a data instruction. We do this by pushing the expression into a symbol
3870 in the expr_section, and creating a fix for that. */
3873 fix_new_aarch64 (fragS
* frag
,
3875 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3885 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3889 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3896 /* Diagnostics on operands errors. */
3898 /* By default, output verbose error message.
3899 Disable the verbose error message by -mno-verbose-error. */
3900 static int verbose_error_p
= 1;
3902 #ifdef DEBUG_AARCH64
3903 /* N.B. this is only for the purpose of debugging. */
3904 const char* operand_mismatch_kind_names
[] =
3907 "AARCH64_OPDE_RECOVERABLE",
3908 "AARCH64_OPDE_SYNTAX_ERROR",
3909 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3910 "AARCH64_OPDE_INVALID_VARIANT",
3911 "AARCH64_OPDE_OUT_OF_RANGE",
3912 "AARCH64_OPDE_UNALIGNED",
3913 "AARCH64_OPDE_REG_LIST",
3914 "AARCH64_OPDE_OTHER_ERROR",
3916 #endif /* DEBUG_AARCH64 */
3918 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3920 When multiple errors of different kinds are found in the same assembly
3921 line, only the error of the highest severity will be picked up for
3922 issuing the diagnostics. */
3924 static inline bfd_boolean
3925 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3926 enum aarch64_operand_error_kind rhs
)
3928 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3929 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3930 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3931 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3932 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3933 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3934 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3935 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3939 /* Helper routine to get the mnemonic name from the assembly instruction
3940 line; should only be called for the diagnosis purpose, as there is
3941 string copy operation involved, which may affect the runtime
3942 performance if used in elsewhere. */
3945 get_mnemonic_name (const char *str
)
3947 static char mnemonic
[32];
3950 /* Get the first 15 bytes and assume that the full name is included. */
3951 strncpy (mnemonic
, str
, 31);
3952 mnemonic
[31] = '\0';
3954 /* Scan up to the end of the mnemonic, which must end in white space,
3955 '.', or end of string. */
3956 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3961 /* Append '...' to the truncated long name. */
3962 if (ptr
- mnemonic
== 31)
3963 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3969 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3971 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3972 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3975 /* Data strutures storing one user error in the assembly code related to
3978 struct operand_error_record
3980 const aarch64_opcode
*opcode
;
3981 aarch64_operand_error detail
;
3982 struct operand_error_record
*next
;
3985 typedef struct operand_error_record operand_error_record
;
3987 struct operand_errors
3989 operand_error_record
*head
;
3990 operand_error_record
*tail
;
3993 typedef struct operand_errors operand_errors
;
3995 /* Top-level data structure reporting user errors for the current line of
3997 The way md_assemble works is that all opcodes sharing the same mnemonic
3998 name are iterated to find a match to the assembly line. In this data
3999 structure, each of the such opcodes will have one operand_error_record
4000 allocated and inserted. In other words, excessive errors related with
4001 a single opcode are disregarded. */
4002 operand_errors operand_error_report
;
4004 /* Free record nodes. */
4005 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4007 /* Initialize the data structure that stores the operand mismatch
4008 information on assembling one line of the assembly code. */
4010 init_operand_error_report (void)
4012 if (operand_error_report
.head
!= NULL
)
4014 gas_assert (operand_error_report
.tail
!= NULL
);
4015 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4016 free_opnd_error_record_nodes
= operand_error_report
.head
;
4017 operand_error_report
.head
= NULL
;
4018 operand_error_report
.tail
= NULL
;
4021 gas_assert (operand_error_report
.tail
== NULL
);
4024 /* Return TRUE if some operand error has been recorded during the
4025 parsing of the current assembly line using the opcode *OPCODE;
4026 otherwise return FALSE. */
4027 static inline bfd_boolean
4028 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4030 operand_error_record
*record
= operand_error_report
.head
;
4031 return record
&& record
->opcode
== opcode
;
4034 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4035 OPCODE field is initialized with OPCODE.
4036 N.B. only one record for each opcode, i.e. the maximum of one error is
4037 recorded for each instruction template. */
4040 add_operand_error_record (const operand_error_record
* new_record
)
4042 const aarch64_opcode
*opcode
= new_record
->opcode
;
4043 operand_error_record
* record
= operand_error_report
.head
;
4045 /* The record may have been created for this opcode. If not, we need
4047 if (! opcode_has_operand_error_p (opcode
))
4049 /* Get one empty record. */
4050 if (free_opnd_error_record_nodes
== NULL
)
4052 record
= XNEW (operand_error_record
);
4056 record
= free_opnd_error_record_nodes
;
4057 free_opnd_error_record_nodes
= record
->next
;
4059 record
->opcode
= opcode
;
4060 /* Insert at the head. */
4061 record
->next
= operand_error_report
.head
;
4062 operand_error_report
.head
= record
;
4063 if (operand_error_report
.tail
== NULL
)
4064 operand_error_report
.tail
= record
;
4066 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4067 && record
->detail
.index
<= new_record
->detail
.index
4068 && operand_error_higher_severity_p (record
->detail
.kind
,
4069 new_record
->detail
.kind
))
4071 /* In the case of multiple errors found on operands related with a
4072 single opcode, only record the error of the leftmost operand and
4073 only if the error is of higher severity. */
4074 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4075 " the existing error %s on operand %d",
4076 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4077 new_record
->detail
.index
,
4078 operand_mismatch_kind_names
[record
->detail
.kind
],
4079 record
->detail
.index
);
4083 record
->detail
= new_record
->detail
;
4087 record_operand_error_info (const aarch64_opcode
*opcode
,
4088 aarch64_operand_error
*error_info
)
4090 operand_error_record record
;
4091 record
.opcode
= opcode
;
4092 record
.detail
= *error_info
;
4093 add_operand_error_record (&record
);
4096 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4097 error message *ERROR, for operand IDX (count from 0). */
4100 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4101 enum aarch64_operand_error_kind kind
,
4104 aarch64_operand_error info
;
4105 memset(&info
, 0, sizeof (info
));
4109 record_operand_error_info (opcode
, &info
);
4113 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4114 enum aarch64_operand_error_kind kind
,
4115 const char* error
, const int *extra_data
)
4117 aarch64_operand_error info
;
4121 info
.data
[0] = extra_data
[0];
4122 info
.data
[1] = extra_data
[1];
4123 info
.data
[2] = extra_data
[2];
4124 record_operand_error_info (opcode
, &info
);
4128 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4129 const char* error
, int lower_bound
,
4132 int data
[3] = {lower_bound
, upper_bound
, 0};
4133 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4137 /* Remove the operand error record for *OPCODE. */
4138 static void ATTRIBUTE_UNUSED
4139 remove_operand_error_record (const aarch64_opcode
*opcode
)
4141 if (opcode_has_operand_error_p (opcode
))
4143 operand_error_record
* record
= operand_error_report
.head
;
4144 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4145 operand_error_report
.head
= record
->next
;
4146 record
->next
= free_opnd_error_record_nodes
;
4147 free_opnd_error_record_nodes
= record
;
4148 if (operand_error_report
.head
== NULL
)
4150 gas_assert (operand_error_report
.tail
== record
);
4151 operand_error_report
.tail
= NULL
;
4156 /* Given the instruction in *INSTR, return the index of the best matched
4157 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4159 Return -1 if there is no qualifier sequence; return the first match
4160 if there is multiple matches found. */
4163 find_best_match (const aarch64_inst
*instr
,
4164 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4166 int i
, num_opnds
, max_num_matched
, idx
;
4168 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4171 DEBUG_TRACE ("no operand");
4175 max_num_matched
= 0;
4178 /* For each pattern. */
4179 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4182 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4184 /* Most opcodes has much fewer patterns in the list. */
4185 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4187 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4188 if (i
!= 0 && idx
== -1)
4189 /* If nothing has been matched, return the 1st sequence. */
4194 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4195 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4198 if (num_matched
> max_num_matched
)
4200 max_num_matched
= num_matched
;
4205 DEBUG_TRACE ("return with %d", idx
);
4209 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4210 corresponding operands in *INSTR. */
4213 assign_qualifier_sequence (aarch64_inst
*instr
,
4214 const aarch64_opnd_qualifier_t
*qualifiers
)
4217 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4218 gas_assert (num_opnds
);
4219 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4220 instr
->operands
[i
].qualifier
= *qualifiers
;
4223 /* Print operands for the diagnosis purpose. */
4226 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4227 const aarch64_opnd_info
*opnds
)
4231 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4233 const size_t size
= 128;
4236 /* We regard the opcode operand info more, however we also look into
4237 the inst->operands to support the disassembling of the optional
4239 The two operand code should be the same in all cases, apart from
4240 when the operand can be optional. */
4241 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4242 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4245 /* Generate the operand string in STR. */
4246 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
4250 strcat (buf
, i
== 0 ? " " : ",");
4252 /* Append the operand string. */
4257 /* Send to stderr a string as information. */
4260 output_info (const char *format
, ...)
4266 file
= as_where (&line
);
4270 fprintf (stderr
, "%s:%u: ", file
, line
);
4272 fprintf (stderr
, "%s: ", file
);
4274 fprintf (stderr
, _("Info: "));
4275 va_start (args
, format
);
4276 vfprintf (stderr
, format
, args
);
4278 (void) putc ('\n', stderr
);
4281 /* Output one operand error record. */
4284 output_operand_error_record (const operand_error_record
*record
, char *str
)
4286 const aarch64_operand_error
*detail
= &record
->detail
;
4287 int idx
= detail
->index
;
4288 const aarch64_opcode
*opcode
= record
->opcode
;
4289 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4290 : AARCH64_OPND_NIL
);
4292 switch (detail
->kind
)
4294 case AARCH64_OPDE_NIL
:
4298 case AARCH64_OPDE_SYNTAX_ERROR
:
4299 case AARCH64_OPDE_RECOVERABLE
:
4300 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4301 case AARCH64_OPDE_OTHER_ERROR
:
4302 /* Use the prepared error message if there is, otherwise use the
4303 operand description string to describe the error. */
4304 if (detail
->error
!= NULL
)
4307 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4309 as_bad (_("%s at operand %d -- `%s'"),
4310 detail
->error
, idx
+ 1, str
);
4314 gas_assert (idx
>= 0);
4315 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4316 aarch64_get_operand_desc (opd_code
), str
);
4320 case AARCH64_OPDE_INVALID_VARIANT
:
4321 as_bad (_("operand mismatch -- `%s'"), str
);
4322 if (verbose_error_p
)
4324 /* We will try to correct the erroneous instruction and also provide
4325 more information e.g. all other valid variants.
4327 The string representation of the corrected instruction and other
4328 valid variants are generated by
4330 1) obtaining the intermediate representation of the erroneous
4332 2) manipulating the IR, e.g. replacing the operand qualifier;
4333 3) printing out the instruction by calling the printer functions
4334 shared with the disassembler.
4336 The limitation of this method is that the exact input assembly
4337 line cannot be accurately reproduced in some cases, for example an
4338 optional operand present in the actual assembly line will be
4339 omitted in the output; likewise for the optional syntax rules,
4340 e.g. the # before the immediate. Another limitation is that the
4341 assembly symbols and relocation operations in the assembly line
4342 currently cannot be printed out in the error report. Last but not
4343 least, when there is other error(s) co-exist with this error, the
4344 'corrected' instruction may be still incorrect, e.g. given
4345 'ldnp h0,h1,[x0,#6]!'
4346 this diagnosis will provide the version:
4347 'ldnp s0,s1,[x0,#6]!'
4348 which is still not right. */
4349 size_t len
= strlen (get_mnemonic_name (str
));
4352 const size_t size
= 2048;
4354 aarch64_inst
*inst_base
= &inst
.base
;
4355 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4358 reset_aarch64_instruction (&inst
);
4359 inst_base
->opcode
= opcode
;
4361 /* Reset the error report so that there is no side effect on the
4362 following operand parsing. */
4363 init_operand_error_report ();
4366 result
= parse_operands (str
+ len
, opcode
)
4367 && programmer_friendly_fixup (&inst
);
4368 gas_assert (result
);
4369 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4371 gas_assert (!result
);
4373 /* Find the most matched qualifier sequence. */
4374 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4375 gas_assert (qlf_idx
> -1);
4377 /* Assign the qualifiers. */
4378 assign_qualifier_sequence (inst_base
,
4379 opcode
->qualifiers_list
[qlf_idx
]);
4381 /* Print the hint. */
4382 output_info (_(" did you mean this?"));
4383 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4384 print_operands (buf
, opcode
, inst_base
->operands
);
4385 output_info (_(" %s"), buf
);
4387 /* Print out other variant(s) if there is any. */
4389 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4390 output_info (_(" other valid variant(s):"));
4392 /* For each pattern. */
4393 qualifiers_list
= opcode
->qualifiers_list
;
4394 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4396 /* Most opcodes has much fewer patterns in the list.
4397 First NIL qualifier indicates the end in the list. */
4398 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4403 /* Mnemonics name. */
4404 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4406 /* Assign the qualifiers. */
4407 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4409 /* Print instruction. */
4410 print_operands (buf
, opcode
, inst_base
->operands
);
4412 output_info (_(" %s"), buf
);
4418 case AARCH64_OPDE_OUT_OF_RANGE
:
4419 if (detail
->data
[0] != detail
->data
[1])
4420 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4421 detail
->error
? detail
->error
: _("immediate value"),
4422 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4424 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4425 detail
->error
? detail
->error
: _("immediate value"),
4426 detail
->data
[0], idx
+ 1, str
);
4429 case AARCH64_OPDE_REG_LIST
:
4430 if (detail
->data
[0] == 1)
4431 as_bad (_("invalid number of registers in the list; "
4432 "only 1 register is expected at operand %d -- `%s'"),
4435 as_bad (_("invalid number of registers in the list; "
4436 "%d registers are expected at operand %d -- `%s'"),
4437 detail
->data
[0], idx
+ 1, str
);
4440 case AARCH64_OPDE_UNALIGNED
:
4441 as_bad (_("immediate value should be a multiple of "
4442 "%d at operand %d -- `%s'"),
4443 detail
->data
[0], idx
+ 1, str
);
4452 /* Process and output the error message about the operand mismatching.
4454 When this function is called, the operand error information had
4455 been collected for an assembly line and there will be multiple
4456 errors in the case of mulitple instruction templates; output the
4457 error message that most closely describes the problem. */
4460 output_operand_error_report (char *str
)
4462 int largest_error_pos
;
4463 const char *msg
= NULL
;
4464 enum aarch64_operand_error_kind kind
;
4465 operand_error_record
*curr
;
4466 operand_error_record
*head
= operand_error_report
.head
;
4467 operand_error_record
*record
= NULL
;
4469 /* No error to report. */
4473 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4475 /* Only one error. */
4476 if (head
== operand_error_report
.tail
)
4478 DEBUG_TRACE ("single opcode entry with error kind: %s",
4479 operand_mismatch_kind_names
[head
->detail
.kind
]);
4480 output_operand_error_record (head
, str
);
4484 /* Find the error kind of the highest severity. */
4485 DEBUG_TRACE ("multiple opcode entres with error kind");
4486 kind
= AARCH64_OPDE_NIL
;
4487 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4489 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4490 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4491 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4492 kind
= curr
->detail
.kind
;
4494 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4496 /* Pick up one of errors of KIND to report. */
4497 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4498 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4500 if (curr
->detail
.kind
!= kind
)
4502 /* If there are multiple errors, pick up the one with the highest
4503 mismatching operand index. In the case of multiple errors with
4504 the equally highest operand index, pick up the first one or the
4505 first one with non-NULL error message. */
4506 if (curr
->detail
.index
> largest_error_pos
4507 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4508 && curr
->detail
.error
!= NULL
))
4510 largest_error_pos
= curr
->detail
.index
;
4512 msg
= record
->detail
.error
;
4516 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4517 DEBUG_TRACE ("Pick up error kind %s to report",
4518 operand_mismatch_kind_names
[record
->detail
.kind
]);
4521 output_operand_error_record (record
, str
);
4524 /* Write an AARCH64 instruction to buf - always little-endian. */
4526 put_aarch64_insn (char *buf
, uint32_t insn
)
4528 unsigned char *where
= (unsigned char *) buf
;
4530 where
[1] = insn
>> 8;
4531 where
[2] = insn
>> 16;
4532 where
[3] = insn
>> 24;
4536 get_aarch64_insn (char *buf
)
4538 unsigned char *where
= (unsigned char *) buf
;
4540 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4545 output_inst (struct aarch64_inst
*new_inst
)
4549 to
= frag_more (INSN_SIZE
);
4551 frag_now
->tc_frag_data
.recorded
= 1;
4553 put_aarch64_insn (to
, inst
.base
.value
);
4555 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4557 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4558 INSN_SIZE
, &inst
.reloc
.exp
,
4561 DEBUG_TRACE ("Prepared relocation fix up");
4562 /* Don't check the addend value against the instruction size,
4563 that's the job of our code in md_apply_fix(). */
4564 fixp
->fx_no_overflow
= 1;
4565 if (new_inst
!= NULL
)
4566 fixp
->tc_fix_data
.inst
= new_inst
;
4567 if (aarch64_gas_internal_fixup_p ())
4569 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4570 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4571 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4575 dwarf2_emit_insn (INSN_SIZE
);
4578 /* Link together opcodes of the same name. */
4582 aarch64_opcode
*opcode
;
4583 struct templates
*next
;
4586 typedef struct templates templates
;
4589 lookup_mnemonic (const char *start
, int len
)
4591 templates
*templ
= NULL
;
4593 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4597 /* Subroutine of md_assemble, responsible for looking up the primary
4598 opcode from the mnemonic the user wrote. STR points to the
4599 beginning of the mnemonic. */
4602 opcode_lookup (char **str
)
4605 const aarch64_cond
*cond
;
4609 /* Scan up to the end of the mnemonic, which must end in white space,
4610 '.', or end of string. */
4611 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4618 inst
.cond
= COND_ALWAYS
;
4620 /* Handle a possible condition. */
4623 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4626 inst
.cond
= cond
->value
;
4640 if (inst
.cond
== COND_ALWAYS
)
4642 /* Look for unaffixed mnemonic. */
4643 return lookup_mnemonic (base
, len
);
4647 /* append ".c" to mnemonic if conditional */
4648 memcpy (condname
, base
, len
);
4649 memcpy (condname
+ len
, ".c", 2);
4652 return lookup_mnemonic (base
, len
);
4658 /* Internal helper routine converting a vector neon_type_el structure
4659 *VECTYPE to a corresponding operand qualifier. */
4661 static inline aarch64_opnd_qualifier_t
4662 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4664 /* Element size in bytes indexed by neon_el_type. */
4665 const unsigned char ele_size
[5]
4667 const unsigned int ele_base
[5] =
4669 AARCH64_OPND_QLF_V_8B
,
4670 AARCH64_OPND_QLF_V_2H
,
4671 AARCH64_OPND_QLF_V_2S
,
4672 AARCH64_OPND_QLF_V_1D
,
4673 AARCH64_OPND_QLF_V_1Q
4676 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4677 goto vectype_conversion_fail
;
4679 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4681 if (vectype
->defined
& NTA_HASINDEX
)
4682 /* Vector element register. */
4683 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4686 /* Vector register. */
4687 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4690 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4691 goto vectype_conversion_fail
;
4693 /* The conversion is by calculating the offset from the base operand
4694 qualifier for the vector type. The operand qualifiers are regular
4695 enough that the offset can established by shifting the vector width by
4696 a vector-type dependent amount. */
4698 if (vectype
->type
== NT_b
)
4700 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4702 else if (vectype
->type
>= NT_d
)
4707 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4708 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4709 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4713 vectype_conversion_fail
:
4714 first_error (_("bad vector arrangement type"));
4715 return AARCH64_OPND_QLF_NIL
;
4718 /* Process an optional operand that is found omitted from the assembly line.
4719 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4720 instruction's opcode entry while IDX is the index of this omitted operand.
4724 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4725 int idx
, aarch64_opnd_info
*operand
)
4727 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4728 gas_assert (optional_operand_p (opcode
, idx
));
4729 gas_assert (!operand
->present
);
4733 case AARCH64_OPND_Rd
:
4734 case AARCH64_OPND_Rn
:
4735 case AARCH64_OPND_Rm
:
4736 case AARCH64_OPND_Rt
:
4737 case AARCH64_OPND_Rt2
:
4738 case AARCH64_OPND_Rs
:
4739 case AARCH64_OPND_Ra
:
4740 case AARCH64_OPND_Rt_SYS
:
4741 case AARCH64_OPND_Rd_SP
:
4742 case AARCH64_OPND_Rn_SP
:
4743 case AARCH64_OPND_Fd
:
4744 case AARCH64_OPND_Fn
:
4745 case AARCH64_OPND_Fm
:
4746 case AARCH64_OPND_Fa
:
4747 case AARCH64_OPND_Ft
:
4748 case AARCH64_OPND_Ft2
:
4749 case AARCH64_OPND_Sd
:
4750 case AARCH64_OPND_Sn
:
4751 case AARCH64_OPND_Sm
:
4752 case AARCH64_OPND_Vd
:
4753 case AARCH64_OPND_Vn
:
4754 case AARCH64_OPND_Vm
:
4755 case AARCH64_OPND_VdD1
:
4756 case AARCH64_OPND_VnD1
:
4757 operand
->reg
.regno
= default_value
;
4760 case AARCH64_OPND_Ed
:
4761 case AARCH64_OPND_En
:
4762 case AARCH64_OPND_Em
:
4763 operand
->reglane
.regno
= default_value
;
4766 case AARCH64_OPND_IDX
:
4767 case AARCH64_OPND_BIT_NUM
:
4768 case AARCH64_OPND_IMMR
:
4769 case AARCH64_OPND_IMMS
:
4770 case AARCH64_OPND_SHLL_IMM
:
4771 case AARCH64_OPND_IMM_VLSL
:
4772 case AARCH64_OPND_IMM_VLSR
:
4773 case AARCH64_OPND_CCMP_IMM
:
4774 case AARCH64_OPND_FBITS
:
4775 case AARCH64_OPND_UIMM4
:
4776 case AARCH64_OPND_UIMM3_OP1
:
4777 case AARCH64_OPND_UIMM3_OP2
:
4778 case AARCH64_OPND_IMM
:
4779 case AARCH64_OPND_WIDTH
:
4780 case AARCH64_OPND_UIMM7
:
4781 case AARCH64_OPND_NZCV
:
4782 operand
->imm
.value
= default_value
;
4785 case AARCH64_OPND_EXCEPTION
:
4786 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4789 case AARCH64_OPND_BARRIER_ISB
:
4790 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4797 /* Process the relocation type for move wide instructions.
4798 Return TRUE on success; otherwise return FALSE. */
4801 process_movw_reloc_info (void)
4806 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4808 if (inst
.base
.opcode
->op
== OP_MOVK
)
4809 switch (inst
.reloc
.type
)
4811 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4812 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4813 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4814 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4815 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4816 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4817 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4819 (_("the specified relocation type is not allowed for MOVK"));
4825 switch (inst
.reloc
.type
)
4827 case BFD_RELOC_AARCH64_MOVW_G0
:
4828 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4829 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4830 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4831 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
4832 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
4833 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
4834 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4835 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4836 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4837 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4840 case BFD_RELOC_AARCH64_MOVW_G1
:
4841 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4842 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4843 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4844 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
4845 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4846 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
4847 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4848 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4849 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4850 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4853 case BFD_RELOC_AARCH64_MOVW_G2
:
4854 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4855 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4856 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4857 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4860 set_fatal_syntax_error
4861 (_("the specified relocation type is not allowed for 32-bit "
4867 case BFD_RELOC_AARCH64_MOVW_G3
:
4870 set_fatal_syntax_error
4871 (_("the specified relocation type is not allowed for 32-bit "
4878 /* More cases should be added when more MOVW-related relocation types
4879 are supported in GAS. */
4880 gas_assert (aarch64_gas_internal_fixup_p ());
4881 /* The shift amount should have already been set by the parser. */
4884 inst
.base
.operands
[1].shifter
.amount
= shift
;
4888 /* A primitive log caculator. */
4890 static inline unsigned int
4891 get_logsz (unsigned int size
)
4893 const unsigned char ls
[16] =
4894 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4900 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4901 return ls
[size
- 1];
4904 /* Determine and return the real reloc type code for an instruction
4905 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4907 static inline bfd_reloc_code_real_type
4908 ldst_lo12_determine_real_reloc_type (void)
4911 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4912 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4914 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4916 BFD_RELOC_AARCH64_LDST8_LO12
,
4917 BFD_RELOC_AARCH64_LDST16_LO12
,
4918 BFD_RELOC_AARCH64_LDST32_LO12
,
4919 BFD_RELOC_AARCH64_LDST64_LO12
,
4920 BFD_RELOC_AARCH64_LDST128_LO12
4923 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4924 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4925 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4926 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4927 BFD_RELOC_AARCH64_NONE
4930 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4931 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4932 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4933 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4934 BFD_RELOC_AARCH64_NONE
4938 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4939 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4941 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4942 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4944 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4946 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4948 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4950 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4951 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4952 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4953 gas_assert (logsz
<= 3);
4955 gas_assert (logsz
<= 4);
4957 /* In reloc.c, these pseudo relocation types should be defined in similar
4958 order as above reloc_ldst_lo12 array. Because the array index calcuation
4959 below relies on this. */
4960 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4963 /* Check whether a register list REGINFO is valid. The registers must be
4964 numbered in increasing order (modulo 32), in increments of one or two.
4966 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4969 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4972 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4974 uint32_t i
, nb_regs
, prev_regno
, incr
;
4976 nb_regs
= 1 + (reginfo
& 0x3);
4978 prev_regno
= reginfo
& 0x1f;
4979 incr
= accept_alternate
? 2 : 1;
4981 for (i
= 1; i
< nb_regs
; ++i
)
4983 uint32_t curr_regno
;
4985 curr_regno
= reginfo
& 0x1f;
4986 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4988 prev_regno
= curr_regno
;
4994 /* Generic instruction operand parser. This does no encoding and no
4995 semantic validation; it merely squirrels values away in the inst
4996 structure. Returns TRUE or FALSE depending on whether the
4997 specified grammar matched. */
5000 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5003 char *backtrack_pos
= 0;
5004 const enum aarch64_opnd
*operands
= opcode
->operands
;
5007 skip_whitespace (str
);
5009 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5012 int isreg32
, isregzero
;
5013 int comma_skipped_p
= 0;
5014 aarch64_reg_type rtype
;
5015 struct neon_type_el vectype
;
5016 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5018 DEBUG_TRACE ("parse operand %d", i
);
5020 /* Assign the operand code. */
5021 info
->type
= operands
[i
];
5023 if (optional_operand_p (opcode
, i
))
5025 /* Remember where we are in case we need to backtrack. */
5026 gas_assert (!backtrack_pos
);
5027 backtrack_pos
= str
;
5030 /* Expect comma between operands; the backtrack mechanizm will take
5031 care of cases of omitted optional operand. */
5032 if (i
> 0 && ! skip_past_char (&str
, ','))
5034 set_syntax_error (_("comma expected between operands"));
5038 comma_skipped_p
= 1;
5040 switch (operands
[i
])
5042 case AARCH64_OPND_Rd
:
5043 case AARCH64_OPND_Rn
:
5044 case AARCH64_OPND_Rm
:
5045 case AARCH64_OPND_Rt
:
5046 case AARCH64_OPND_Rt2
:
5047 case AARCH64_OPND_Rs
:
5048 case AARCH64_OPND_Ra
:
5049 case AARCH64_OPND_Rt_SYS
:
5050 case AARCH64_OPND_PAIRREG
:
5051 po_int_reg_or_fail (1, 0);
5054 case AARCH64_OPND_Rd_SP
:
5055 case AARCH64_OPND_Rn_SP
:
5056 po_int_reg_or_fail (0, 1);
5059 case AARCH64_OPND_Rm_EXT
:
5060 case AARCH64_OPND_Rm_SFT
:
5061 po_misc_or_fail (parse_shifter_operand
5062 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5064 : SHIFTED_LOGIC_IMM
)));
5065 if (!info
->shifter
.operator_present
)
5067 /* Default to LSL if not present. Libopcodes prefers shifter
5068 kind to be explicit. */
5069 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5070 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5071 /* For Rm_EXT, libopcodes will carry out further check on whether
5072 or not stack pointer is used in the instruction (Recall that
5073 "the extend operator is not optional unless at least one of
5074 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5078 case AARCH64_OPND_Fd
:
5079 case AARCH64_OPND_Fn
:
5080 case AARCH64_OPND_Fm
:
5081 case AARCH64_OPND_Fa
:
5082 case AARCH64_OPND_Ft
:
5083 case AARCH64_OPND_Ft2
:
5084 case AARCH64_OPND_Sd
:
5085 case AARCH64_OPND_Sn
:
5086 case AARCH64_OPND_Sm
:
5087 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5088 if (val
== PARSE_FAIL
)
5090 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5093 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5095 info
->reg
.regno
= val
;
5096 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5099 case AARCH64_OPND_Vd
:
5100 case AARCH64_OPND_Vn
:
5101 case AARCH64_OPND_Vm
:
5102 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5103 if (val
== PARSE_FAIL
)
5105 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5108 if (vectype
.defined
& NTA_HASINDEX
)
5111 info
->reg
.regno
= val
;
5112 info
->qualifier
= vectype_to_qualifier (&vectype
);
5113 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5117 case AARCH64_OPND_VdD1
:
5118 case AARCH64_OPND_VnD1
:
5119 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5120 if (val
== PARSE_FAIL
)
5122 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5125 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5127 set_fatal_syntax_error
5128 (_("the top half of a 128-bit FP/SIMD register is expected"));
5131 info
->reg
.regno
= val
;
5132 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5133 here; it is correct for the purpose of encoding/decoding since
5134 only the register number is explicitly encoded in the related
5135 instructions, although this appears a bit hacky. */
5136 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5139 case AARCH64_OPND_Ed
:
5140 case AARCH64_OPND_En
:
5141 case AARCH64_OPND_Em
:
5142 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5143 if (val
== PARSE_FAIL
)
5145 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5148 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5151 info
->reglane
.regno
= val
;
5152 info
->reglane
.index
= vectype
.index
;
5153 info
->qualifier
= vectype_to_qualifier (&vectype
);
5154 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5158 case AARCH64_OPND_LVn
:
5159 case AARCH64_OPND_LVt
:
5160 case AARCH64_OPND_LVt_AL
:
5161 case AARCH64_OPND_LEt
:
5162 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
5164 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5166 set_fatal_syntax_error (_("invalid register list"));
5169 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5170 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5171 if (operands
[i
] == AARCH64_OPND_LEt
)
5173 if (!(vectype
.defined
& NTA_HASINDEX
))
5175 info
->reglist
.has_index
= 1;
5176 info
->reglist
.index
= vectype
.index
;
5178 else if (!(vectype
.defined
& NTA_HASTYPE
))
5180 info
->qualifier
= vectype_to_qualifier (&vectype
);
5181 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5185 case AARCH64_OPND_Cn
:
5186 case AARCH64_OPND_Cm
:
5187 po_reg_or_fail (REG_TYPE_CN
);
5190 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5193 inst
.base
.operands
[i
].reg
.regno
= val
;
5196 case AARCH64_OPND_SHLL_IMM
:
5197 case AARCH64_OPND_IMM_VLSR
:
5198 po_imm_or_fail (1, 64);
5199 info
->imm
.value
= val
;
5202 case AARCH64_OPND_CCMP_IMM
:
5203 case AARCH64_OPND_FBITS
:
5204 case AARCH64_OPND_UIMM4
:
5205 case AARCH64_OPND_UIMM3_OP1
:
5206 case AARCH64_OPND_UIMM3_OP2
:
5207 case AARCH64_OPND_IMM_VLSL
:
5208 case AARCH64_OPND_IMM
:
5209 case AARCH64_OPND_WIDTH
:
5210 po_imm_nc_or_fail ();
5211 info
->imm
.value
= val
;
5214 case AARCH64_OPND_UIMM7
:
5215 po_imm_or_fail (0, 127);
5216 info
->imm
.value
= val
;
5219 case AARCH64_OPND_IDX
:
5220 case AARCH64_OPND_BIT_NUM
:
5221 case AARCH64_OPND_IMMR
:
5222 case AARCH64_OPND_IMMS
:
5223 po_imm_or_fail (0, 63);
5224 info
->imm
.value
= val
;
5227 case AARCH64_OPND_IMM0
:
5228 po_imm_nc_or_fail ();
5231 set_fatal_syntax_error (_("immediate zero expected"));
5234 info
->imm
.value
= 0;
5237 case AARCH64_OPND_FPIMM0
:
5240 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5241 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5242 it is probably not worth the effort to support it. */
5243 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
5244 && !(res2
= parse_constant_immediate (&str
, &val
)))
5246 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5248 info
->imm
.value
= 0;
5249 info
->imm
.is_fp
= 1;
5252 set_fatal_syntax_error (_("immediate zero expected"));
5256 case AARCH64_OPND_IMM_MOV
:
5259 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5260 reg_name_p (str
, REG_TYPE_VN
))
5263 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5265 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5266 later. fix_mov_imm_insn will try to determine a machine
5267 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5268 message if the immediate cannot be moved by a single
5270 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5271 inst
.base
.operands
[i
].skip
= 1;
5275 case AARCH64_OPND_SIMD_IMM
:
5276 case AARCH64_OPND_SIMD_IMM_SFT
:
5277 if (! parse_big_immediate (&str
, &val
))
5279 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5281 /* need_libopcodes_p */ 1,
5284 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5285 shift, we don't check it here; we leave the checking to
5286 the libopcodes (operand_general_constraint_met_p). By
5287 doing this, we achieve better diagnostics. */
5288 if (skip_past_comma (&str
)
5289 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5291 if (!info
->shifter
.operator_present
5292 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5294 /* Default to LSL if not present. Libopcodes prefers shifter
5295 kind to be explicit. */
5296 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5297 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5301 case AARCH64_OPND_FPIMM
:
5302 case AARCH64_OPND_SIMD_FPIMM
:
5306 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5308 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5312 set_fatal_syntax_error (_("invalid floating-point constant"));
5315 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5316 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5320 case AARCH64_OPND_LIMM
:
5321 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5322 SHIFTED_LOGIC_IMM
));
5323 if (info
->shifter
.operator_present
)
5325 set_fatal_syntax_error
5326 (_("shift not allowed for bitmask immediate"));
5329 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5331 /* need_libopcodes_p */ 1,
5335 case AARCH64_OPND_AIMM
:
5336 if (opcode
->op
== OP_ADD
)
5337 /* ADD may have relocation types. */
5338 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5339 SHIFTED_ARITH_IMM
));
5341 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5342 SHIFTED_ARITH_IMM
));
5343 switch (inst
.reloc
.type
)
5345 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5346 info
->shifter
.amount
= 12;
5348 case BFD_RELOC_UNUSED
:
5349 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5350 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5351 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5352 inst
.reloc
.pc_rel
= 0;
5357 info
->imm
.value
= 0;
5358 if (!info
->shifter
.operator_present
)
5360 /* Default to LSL if not present. Libopcodes prefers shifter
5361 kind to be explicit. */
5362 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5363 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5367 case AARCH64_OPND_HALF
:
5369 /* #<imm16> or relocation. */
5370 int internal_fixup_p
;
5371 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5372 if (internal_fixup_p
)
5373 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5374 skip_whitespace (str
);
5375 if (skip_past_comma (&str
))
5377 /* {, LSL #<shift>} */
5378 if (! aarch64_gas_internal_fixup_p ())
5380 set_fatal_syntax_error (_("can't mix relocation modifier "
5381 "with explicit shift"));
5384 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5387 inst
.base
.operands
[i
].shifter
.amount
= 0;
5388 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5389 inst
.base
.operands
[i
].imm
.value
= 0;
5390 if (! process_movw_reloc_info ())
5395 case AARCH64_OPND_EXCEPTION
:
5396 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5397 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5399 /* need_libopcodes_p */ 0,
5403 case AARCH64_OPND_NZCV
:
5405 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5409 info
->imm
.value
= nzcv
->value
;
5412 po_imm_or_fail (0, 15);
5413 info
->imm
.value
= val
;
5417 case AARCH64_OPND_COND
:
5418 case AARCH64_OPND_COND1
:
5419 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5421 if (info
->cond
== NULL
)
5423 set_syntax_error (_("invalid condition"));
5426 else if (operands
[i
] == AARCH64_OPND_COND1
5427 && (info
->cond
->value
& 0xe) == 0xe)
5429 /* Not allow AL or NV. */
5430 set_default_error ();
5435 case AARCH64_OPND_ADDR_ADRP
:
5436 po_misc_or_fail (parse_adrp (&str
));
5437 /* Clear the value as operand needs to be relocated. */
5438 info
->imm
.value
= 0;
5441 case AARCH64_OPND_ADDR_PCREL14
:
5442 case AARCH64_OPND_ADDR_PCREL19
:
5443 case AARCH64_OPND_ADDR_PCREL21
:
5444 case AARCH64_OPND_ADDR_PCREL26
:
5445 po_misc_or_fail (parse_address_reloc (&str
, info
));
5446 if (!info
->addr
.pcrel
)
5448 set_syntax_error (_("invalid pc-relative address"));
5451 if (inst
.gen_lit_pool
5452 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5454 /* Only permit "=value" in the literal load instructions.
5455 The literal will be generated by programmer_friendly_fixup. */
5456 set_syntax_error (_("invalid use of \"=immediate\""));
5459 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5461 set_syntax_error (_("unrecognized relocation suffix"));
5464 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5466 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5467 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5471 info
->imm
.value
= 0;
5472 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5473 switch (opcode
->iclass
)
5477 /* e.g. CBZ or B.COND */
5478 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5479 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5483 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5484 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5488 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5490 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5491 : BFD_RELOC_AARCH64_JUMP26
;
5494 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5495 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5498 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5499 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5505 inst
.reloc
.pc_rel
= 1;
5509 case AARCH64_OPND_ADDR_SIMPLE
:
5510 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5511 /* [<Xn|SP>{, #<simm>}] */
5512 po_char_or_fail ('[');
5513 po_reg_or_fail (REG_TYPE_R64_SP
);
5514 /* Accept optional ", #0". */
5515 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5516 && skip_past_char (&str
, ','))
5518 skip_past_char (&str
, '#');
5519 if (! skip_past_char (&str
, '0'))
5521 set_fatal_syntax_error
5522 (_("the optional immediate offset can only be 0"));
5526 po_char_or_fail (']');
5527 info
->addr
.base_regno
= val
;
5530 case AARCH64_OPND_ADDR_REGOFF
:
5531 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5532 po_misc_or_fail (parse_address (&str
, info
, 0));
5533 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5534 || !info
->addr
.preind
|| info
->addr
.postind
5535 || info
->addr
.writeback
)
5537 set_syntax_error (_("invalid addressing mode"));
5540 if (!info
->shifter
.operator_present
)
5542 /* Default to LSL if not present. Libopcodes prefers shifter
5543 kind to be explicit. */
5544 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5545 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5547 /* Qualifier to be deduced by libopcodes. */
5550 case AARCH64_OPND_ADDR_SIMM7
:
5551 po_misc_or_fail (parse_address (&str
, info
, 0));
5552 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5553 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5555 set_syntax_error (_("invalid addressing mode"));
5558 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5560 /* need_libopcodes_p */ 1,
5564 case AARCH64_OPND_ADDR_SIMM9
:
5565 case AARCH64_OPND_ADDR_SIMM9_2
:
5566 po_misc_or_fail (parse_address_reloc (&str
, info
));
5567 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5568 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5569 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5570 && info
->addr
.writeback
))
5572 set_syntax_error (_("invalid addressing mode"));
5575 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5577 set_syntax_error (_("relocation not allowed"));
5580 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5582 /* need_libopcodes_p */ 1,
5586 case AARCH64_OPND_ADDR_UIMM12
:
5587 po_misc_or_fail (parse_address_reloc (&str
, info
));
5588 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5589 || !info
->addr
.preind
|| info
->addr
.writeback
)
5591 set_syntax_error (_("invalid addressing mode"));
5594 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5595 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5596 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5598 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5600 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5601 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5602 /* Leave qualifier to be determined by libopcodes. */
5605 case AARCH64_OPND_SIMD_ADDR_POST
:
5606 /* [<Xn|SP>], <Xm|#<amount>> */
5607 po_misc_or_fail (parse_address (&str
, info
, 1));
5608 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5610 set_syntax_error (_("invalid addressing mode"));
5613 if (!info
->addr
.offset
.is_reg
)
5615 if (inst
.reloc
.exp
.X_op
== O_constant
)
5616 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5619 set_fatal_syntax_error
5620 (_("writeback value should be an immediate constant"));
5627 case AARCH64_OPND_SYSREG
:
5628 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5631 set_syntax_error (_("unknown or missing system register name"));
5634 inst
.base
.operands
[i
].sysreg
= val
;
5637 case AARCH64_OPND_PSTATEFIELD
:
5638 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5641 set_syntax_error (_("unknown or missing PSTATE field name"));
5644 inst
.base
.operands
[i
].pstatefield
= val
;
5647 case AARCH64_OPND_SYSREG_IC
:
5648 inst
.base
.operands
[i
].sysins_op
=
5649 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5651 case AARCH64_OPND_SYSREG_DC
:
5652 inst
.base
.operands
[i
].sysins_op
=
5653 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5655 case AARCH64_OPND_SYSREG_AT
:
5656 inst
.base
.operands
[i
].sysins_op
=
5657 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5659 case AARCH64_OPND_SYSREG_TLBI
:
5660 inst
.base
.operands
[i
].sysins_op
=
5661 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5663 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5665 set_fatal_syntax_error ( _("unknown or missing operation name"));
5670 case AARCH64_OPND_BARRIER
:
5671 case AARCH64_OPND_BARRIER_ISB
:
5672 val
= parse_barrier (&str
);
5673 if (val
!= PARSE_FAIL
5674 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5676 /* ISB only accepts options name 'sy'. */
5678 (_("the specified option is not accepted in ISB"));
5679 /* Turn off backtrack as this optional operand is present. */
5683 /* This is an extension to accept a 0..15 immediate. */
5684 if (val
== PARSE_FAIL
)
5685 po_imm_or_fail (0, 15);
5686 info
->barrier
= aarch64_barrier_options
+ val
;
5689 case AARCH64_OPND_PRFOP
:
5690 val
= parse_pldop (&str
);
5691 /* This is an extension to accept a 0..31 immediate. */
5692 if (val
== PARSE_FAIL
)
5693 po_imm_or_fail (0, 31);
5694 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5697 case AARCH64_OPND_BARRIER_PSB
:
5698 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
5699 if (val
== PARSE_FAIL
)
5704 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5707 /* If we get here, this operand was successfully parsed. */
5708 inst
.base
.operands
[i
].present
= 1;
5712 /* The parse routine should already have set the error, but in case
5713 not, set a default one here. */
5715 set_default_error ();
5717 if (! backtrack_pos
)
5718 goto parse_operands_return
;
5721 /* We reach here because this operand is marked as optional, and
5722 either no operand was supplied or the operand was supplied but it
5723 was syntactically incorrect. In the latter case we report an
5724 error. In the former case we perform a few more checks before
5725 dropping through to the code to insert the default operand. */
5727 char *tmp
= backtrack_pos
;
5728 char endchar
= END_OF_INSN
;
5730 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5732 skip_past_char (&tmp
, ',');
5734 if (*tmp
!= endchar
)
5735 /* The user has supplied an operand in the wrong format. */
5736 goto parse_operands_return
;
5738 /* Make sure there is not a comma before the optional operand.
5739 For example the fifth operand of 'sys' is optional:
5741 sys #0,c0,c0,#0, <--- wrong
5742 sys #0,c0,c0,#0 <--- correct. */
5743 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5745 set_fatal_syntax_error
5746 (_("unexpected comma before the omitted optional operand"));
5747 goto parse_operands_return
;
5751 /* Reaching here means we are dealing with an optional operand that is
5752 omitted from the assembly line. */
5753 gas_assert (optional_operand_p (opcode
, i
));
5755 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5757 /* Try again, skipping the optional operand at backtrack_pos. */
5758 str
= backtrack_pos
;
5761 /* Clear any error record after the omitted optional operand has been
5762 successfully handled. */
5766 /* Check if we have parsed all the operands. */
5767 if (*str
!= '\0' && ! error_p ())
5769 /* Set I to the index of the last present operand; this is
5770 for the purpose of diagnostics. */
5771 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5773 set_fatal_syntax_error
5774 (_("unexpected characters following instruction"));
5777 parse_operands_return
:
5781 DEBUG_TRACE ("parsing FAIL: %s - %s",
5782 operand_mismatch_kind_names
[get_error_kind ()],
5783 get_error_message ());
5784 /* Record the operand error properly; this is useful when there
5785 are multiple instruction templates for a mnemonic name, so that
5786 later on, we can select the error that most closely describes
5788 record_operand_error (opcode
, i
, get_error_kind (),
5789 get_error_message ());
5794 DEBUG_TRACE ("parsing SUCCESS");
5799 /* It does some fix-up to provide some programmer friendly feature while
5800 keeping the libopcodes happy, i.e. libopcodes only accepts
5801 the preferred architectural syntax.
5802 Return FALSE if there is any failure; otherwise return TRUE. */
5805 programmer_friendly_fixup (aarch64_instruction
*instr
)
5807 aarch64_inst
*base
= &instr
->base
;
5808 const aarch64_opcode
*opcode
= base
->opcode
;
5809 enum aarch64_op op
= opcode
->op
;
5810 aarch64_opnd_info
*operands
= base
->operands
;
5812 DEBUG_TRACE ("enter");
5814 switch (opcode
->iclass
)
5817 /* TBNZ Xn|Wn, #uimm6, label
5818 Test and Branch Not Zero: conditionally jumps to label if bit number
5819 uimm6 in register Xn is not zero. The bit number implies the width of
5820 the register, which may be written and should be disassembled as Wn if
5821 uimm is less than 32. */
5822 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5824 if (operands
[1].imm
.value
>= 32)
5826 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5830 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5834 /* LDR Wt, label | =value
5835 As a convenience assemblers will typically permit the notation
5836 "=value" in conjunction with the pc-relative literal load instructions
5837 to automatically place an immediate value or symbolic address in a
5838 nearby literal pool and generate a hidden label which references it.
5839 ISREG has been set to 0 in the case of =value. */
5840 if (instr
->gen_lit_pool
5841 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5843 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5844 if (op
== OP_LDRSW_LIT
)
5846 if (instr
->reloc
.exp
.X_op
!= O_constant
5847 && instr
->reloc
.exp
.X_op
!= O_big
5848 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5850 record_operand_error (opcode
, 1,
5851 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5852 _("constant expression expected"));
5855 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5857 record_operand_error (opcode
, 1,
5858 AARCH64_OPDE_OTHER_ERROR
,
5859 _("literal pool insertion failed"));
5867 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5868 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5869 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5870 A programmer-friendly assembler should accept a destination Xd in
5871 place of Wd, however that is not the preferred form for disassembly.
5873 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5874 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5875 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5876 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5881 /* In the 64-bit form, the final register operand is written as Wm
5882 for all but the (possibly omitted) UXTX/LSL and SXTX
5884 As a programmer-friendly assembler, we accept e.g.
5885 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5886 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5887 int idx
= aarch64_operand_index (opcode
->operands
,
5888 AARCH64_OPND_Rm_EXT
);
5889 gas_assert (idx
== 1 || idx
== 2);
5890 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5891 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5892 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5893 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5894 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5895 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5903 DEBUG_TRACE ("exit with SUCCESS");
5907 /* Check for loads and stores that will cause unpredictable behavior. */
5910 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5912 aarch64_inst
*base
= &instr
->base
;
5913 const aarch64_opcode
*opcode
= base
->opcode
;
5914 const aarch64_opnd_info
*opnds
= base
->operands
;
5915 switch (opcode
->iclass
)
5921 /* Loading/storing the base register is unpredictable if writeback. */
5922 if ((aarch64_get_operand_class (opnds
[0].type
)
5923 == AARCH64_OPND_CLASS_INT_REG
)
5924 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5925 && opnds
[1].addr
.base_regno
!= REG_SP
5926 && opnds
[1].addr
.writeback
)
5927 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5930 case ldstnapair_offs
:
5931 case ldstpair_indexed
:
5932 /* Loading/storing the base register is unpredictable if writeback. */
5933 if ((aarch64_get_operand_class (opnds
[0].type
)
5934 == AARCH64_OPND_CLASS_INT_REG
)
5935 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5936 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5937 && opnds
[2].addr
.base_regno
!= REG_SP
5938 && opnds
[2].addr
.writeback
)
5939 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5940 /* Load operations must load different registers. */
5941 if ((opcode
->opcode
& (1 << 22))
5942 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5943 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5950 /* A wrapper function to interface with libopcodes on encoding and
5951 record the error message if there is any.
5953 Return TRUE on success; otherwise return FALSE. */
5956 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5959 aarch64_operand_error error_info
;
5960 error_info
.kind
= AARCH64_OPDE_NIL
;
5961 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5965 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5966 record_operand_error_info (opcode
, &error_info
);
5971 #ifdef DEBUG_AARCH64
5973 dump_opcode_operands (const aarch64_opcode
*opcode
)
5976 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5978 aarch64_verbose ("\t\t opnd%d: %s", i
,
5979 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5980 ? aarch64_get_operand_name (opcode
->operands
[i
])
5981 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5985 #endif /* DEBUG_AARCH64 */
5987 /* This is the guts of the machine-dependent assembler. STR points to a
5988 machine dependent instruction. This function is supposed to emit
5989 the frags/bytes it assembles to. */
5992 md_assemble (char *str
)
5995 templates
*template;
5996 aarch64_opcode
*opcode
;
5997 aarch64_inst
*inst_base
;
5998 unsigned saved_cond
;
6000 /* Align the previous label if needed. */
6001 if (last_label_seen
!= NULL
)
6003 symbol_set_frag (last_label_seen
, frag_now
);
6004 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6005 S_SET_SEGMENT (last_label_seen
, now_seg
);
6008 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6010 DEBUG_TRACE ("\n\n");
6011 DEBUG_TRACE ("==============================");
6012 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6014 template = opcode_lookup (&p
);
6017 /* It wasn't an instruction, but it might be a register alias of
6018 the form alias .req reg directive. */
6019 if (!create_register_alias (str
, p
))
6020 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6025 skip_whitespace (p
);
6028 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6029 get_mnemonic_name (str
), str
);
6033 init_operand_error_report ();
6035 /* Sections are assumed to start aligned. In executable section, there is no
6036 MAP_DATA symbol pending. So we only align the address during
6037 MAP_DATA --> MAP_INSN transition.
6038 For other sections, this is not guaranteed. */
6039 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6040 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6041 frag_align_code (2, 0);
6043 saved_cond
= inst
.cond
;
6044 reset_aarch64_instruction (&inst
);
6045 inst
.cond
= saved_cond
;
6047 /* Iterate through all opcode entries with the same mnemonic name. */
6050 opcode
= template->opcode
;
6052 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6053 #ifdef DEBUG_AARCH64
6055 dump_opcode_operands (opcode
);
6056 #endif /* DEBUG_AARCH64 */
6058 mapping_state (MAP_INSN
);
6060 inst_base
= &inst
.base
;
6061 inst_base
->opcode
= opcode
;
6063 /* Truly conditionally executed instructions, e.g. b.cond. */
6064 if (opcode
->flags
& F_COND
)
6066 gas_assert (inst
.cond
!= COND_ALWAYS
);
6067 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6068 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6070 else if (inst
.cond
!= COND_ALWAYS
)
6072 /* It shouldn't arrive here, where the assembly looks like a
6073 conditional instruction but the found opcode is unconditional. */
6078 if (parse_operands (p
, opcode
)
6079 && programmer_friendly_fixup (&inst
)
6080 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6082 /* Check that this instruction is supported for this CPU. */
6083 if (!opcode
->avariant
6084 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
6086 as_bad (_("selected processor does not support `%s'"), str
);
6090 warn_unpredictable_ldst (&inst
, str
);
6092 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6093 || !inst
.reloc
.need_libopcodes_p
)
6097 /* If there is relocation generated for the instruction,
6098 store the instruction information for the future fix-up. */
6099 struct aarch64_inst
*copy
;
6100 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6101 copy
= XNEW (struct aarch64_inst
);
6102 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6108 template = template->next
;
6109 if (template != NULL
)
6111 reset_aarch64_instruction (&inst
);
6112 inst
.cond
= saved_cond
;
6115 while (template != NULL
);
6117 /* Issue the error messages if any. */
6118 output_operand_error_report (str
);
6121 /* Various frobbings of labels and their addresses. */
6124 aarch64_start_line_hook (void)
6126 last_label_seen
= NULL
;
6130 aarch64_frob_label (symbolS
* sym
)
6132 last_label_seen
= sym
;
6134 dwarf2_emit_label (sym
);
6138 aarch64_data_in_code (void)
6140 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6142 *input_line_pointer
= '/';
6143 input_line_pointer
+= 5;
6144 *input_line_pointer
= 0;
6152 aarch64_canonicalize_symbol_name (char *name
)
6156 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6157 *(name
+ len
- 5) = 0;
6162 /* Table of all register names defined by default. The user can
6163 define additional names with .req. Note that all register names
6164 should appear in both upper and lowercase variants. Some registers
6165 also have mixed-case names. */
6167 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6168 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6169 #define REGSET31(p,t) \
6170 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6171 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6172 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6173 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6174 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6175 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6176 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6177 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6178 #define REGSET(p,t) \
6179 REGSET31(p,t), REGNUM(p,31,t)
6181 /* These go into aarch64_reg_hsh hash-table. */
6182 static const reg_entry reg_names
[] = {
6183 /* Integer registers. */
6184 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6185 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6187 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6188 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6190 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6191 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6193 /* Coprocessor register numbers. */
6194 REGSET (c
, CN
), REGSET (C
, CN
),
6196 /* Floating-point single precision registers. */
6197 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6199 /* Floating-point double precision registers. */
6200 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6202 /* Floating-point half precision registers. */
6203 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6205 /* Floating-point byte precision registers. */
6206 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6208 /* Floating-point quad precision registers. */
6209 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6211 /* FP/SIMD registers. */
6212 REGSET (v
, VN
), REGSET (V
, VN
),
6227 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6228 static const asm_nzcv nzcv_names
[] = {
6229 {"nzcv", B (n
, z
, c
, v
)},
6230 {"nzcV", B (n
, z
, c
, V
)},
6231 {"nzCv", B (n
, z
, C
, v
)},
6232 {"nzCV", B (n
, z
, C
, V
)},
6233 {"nZcv", B (n
, Z
, c
, v
)},
6234 {"nZcV", B (n
, Z
, c
, V
)},
6235 {"nZCv", B (n
, Z
, C
, v
)},
6236 {"nZCV", B (n
, Z
, C
, V
)},
6237 {"Nzcv", B (N
, z
, c
, v
)},
6238 {"NzcV", B (N
, z
, c
, V
)},
6239 {"NzCv", B (N
, z
, C
, v
)},
6240 {"NzCV", B (N
, z
, C
, V
)},
6241 {"NZcv", B (N
, Z
, c
, v
)},
6242 {"NZcV", B (N
, Z
, c
, V
)},
6243 {"NZCv", B (N
, Z
, C
, v
)},
6244 {"NZCV", B (N
, Z
, C
, V
)}
6257 /* MD interface: bits in the object file. */
6259 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6260 for use in the a.out file, and stores them in the array pointed to by buf.
6261 This knows about the endian-ness of the target machine and does
6262 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6263 2 (short) and 4 (long) Floating numbers are put out as a series of
6264 LITTLENUMS (shorts, here at least). */
6267 md_number_to_chars (char *buf
, valueT val
, int n
)
6269 if (target_big_endian
)
6270 number_to_chars_bigendian (buf
, val
, n
);
6272 number_to_chars_littleendian (buf
, val
, n
);
6275 /* MD interface: Sections. */
6277 /* Estimate the size of a frag before relaxing. Assume everything fits in
6281 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6287 /* Round up a section size to the appropriate boundary. */
6290 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6295 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6296 of an rs_align_code fragment.
6298 Here we fill the frag with the appropriate info for padding the
6299 output stream. The resulting frag will consist of a fixed (fr_fix)
6300 and of a repeating (fr_var) part.
6302 The fixed content is always emitted before the repeating content and
6303 these two parts are used as follows in constructing the output:
6304 - the fixed part will be used to align to a valid instruction word
6305 boundary, in case that we start at a misaligned address; as no
6306 executable instruction can live at the misaligned location, we
6307 simply fill with zeros;
6308 - the variable part will be used to cover the remaining padding and
6309 we fill using the AArch64 NOP instruction.
6311 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6312 enough storage space for up to 3 bytes for padding the back to a valid
6313 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6316 aarch64_handle_align (fragS
* fragP
)
6318 /* NOP = d503201f */
6319 /* AArch64 instructions are always little-endian. */
6320 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6322 int bytes
, fix
, noop_size
;
6325 if (fragP
->fr_type
!= rs_align_code
)
6328 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6329 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6332 gas_assert (fragP
->tc_frag_data
.recorded
);
6335 noop_size
= sizeof (aarch64_noop
);
6337 fix
= bytes
& (noop_size
- 1);
6341 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6345 fragP
->fr_fix
+= fix
;
6349 memcpy (p
, aarch64_noop
, noop_size
);
6350 fragP
->fr_var
= noop_size
;
6353 /* Perform target specific initialisation of a frag.
6354 Note - despite the name this initialisation is not done when the frag
6355 is created, but only when its type is assigned. A frag can be created
6356 and used a long time before its type is set, so beware of assuming that
6357 this initialisationis performed first. */
6361 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6362 int max_chars ATTRIBUTE_UNUSED
)
6366 #else /* OBJ_ELF is defined. */
6368 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6370 /* Record a mapping symbol for alignment frags. We will delete this
6371 later if the alignment ends up empty. */
6372 if (!fragP
->tc_frag_data
.recorded
)
6373 fragP
->tc_frag_data
.recorded
= 1;
6375 switch (fragP
->fr_type
)
6380 mapping_state_2 (MAP_DATA
, max_chars
);
6383 mapping_state_2 (MAP_INSN
, max_chars
);
6390 /* Initialize the DWARF-2 unwind information for this procedure. */
6393 tc_aarch64_frame_initial_instructions (void)
6395 cfi_add_CFA_def_cfa (REG_SP
, 0);
6397 #endif /* OBJ_ELF */
6399 /* Convert REGNAME to a DWARF-2 register number. */
6402 tc_aarch64_regname_to_dw2regnum (char *regname
)
6404 const reg_entry
*reg
= parse_reg (®name
);
6410 case REG_TYPE_SP_32
:
6411 case REG_TYPE_SP_64
:
6421 return reg
->number
+ 64;
6429 /* Implement DWARF2_ADDR_SIZE. */
6432 aarch64_dwarf2_addr_size (void)
6434 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6438 return bfd_arch_bits_per_address (stdoutput
) / 8;
6441 /* MD interface: Symbol and relocation handling. */
6443 /* Return the address within the segment that a PC-relative fixup is
6444 relative to. For AArch64 PC-relative fixups applied to instructions
6445 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6448 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6450 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6452 /* If this is pc-relative and we are going to emit a relocation
6453 then we just want to put out any pipeline compensation that the linker
6454 will need. Otherwise we want to use the calculated base. */
6456 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6457 || aarch64_force_relocation (fixP
)))
6460 /* AArch64 should be consistent for all pc-relative relocations. */
6461 return base
+ AARCH64_PCREL_OFFSET
;
6464 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6465 Otherwise we have no need to default values of symbols. */
6468 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6471 if (name
[0] == '_' && name
[1] == 'G'
6472 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6476 if (symbol_find (name
))
6477 as_bad (_("GOT already in the symbol table"));
6479 GOT_symbol
= symbol_new (name
, undefined_section
,
6480 (valueT
) 0, &zero_address_frag
);
6490 /* Return non-zero if the indicated VALUE has overflowed the maximum
6491 range expressible by a unsigned number with the indicated number of
6495 unsigned_overflow (valueT value
, unsigned bits
)
6498 if (bits
>= sizeof (valueT
) * 8)
6500 lim
= (valueT
) 1 << bits
;
6501 return (value
>= lim
);
6505 /* Return non-zero if the indicated VALUE has overflowed the maximum
6506 range expressible by an signed number with the indicated number of
6510 signed_overflow (offsetT value
, unsigned bits
)
6513 if (bits
>= sizeof (offsetT
) * 8)
6515 lim
= (offsetT
) 1 << (bits
- 1);
6516 return (value
< -lim
|| value
>= lim
);
6519 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6520 unsigned immediate offset load/store instruction, try to encode it as
6521 an unscaled, 9-bit, signed immediate offset load/store instruction.
6522 Return TRUE if it is successful; otherwise return FALSE.
6524 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6525 in response to the standard LDR/STR mnemonics when the immediate offset is
6526 unambiguous, i.e. when it is negative or unaligned. */
6529 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6532 enum aarch64_op new_op
;
6533 const aarch64_opcode
*new_opcode
;
6535 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6537 switch (instr
->opcode
->op
)
6539 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6540 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6541 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6542 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6543 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6544 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6545 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6546 case OP_STR_POS
: new_op
= OP_STUR
; break;
6547 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6548 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6549 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6550 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6551 default: new_op
= OP_NIL
; break;
6554 if (new_op
== OP_NIL
)
6557 new_opcode
= aarch64_get_opcode (new_op
);
6558 gas_assert (new_opcode
!= NULL
);
6560 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6561 instr
->opcode
->op
, new_opcode
->op
);
6563 aarch64_replace_opcode (instr
, new_opcode
);
6565 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6566 qualifier matching may fail because the out-of-date qualifier will
6567 prevent the operand being updated with a new and correct qualifier. */
6568 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6569 AARCH64_OPND_ADDR_SIMM9
);
6570 gas_assert (idx
== 1);
6571 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6573 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6575 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6581 /* Called by fix_insn to fix a MOV immediate alias instruction.
6583 Operand for a generic move immediate instruction, which is an alias
6584 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6585 a 32-bit/64-bit immediate value into general register. An assembler error
6586 shall result if the immediate cannot be created by a single one of these
6587 instructions. If there is a choice, then to ensure reversability an
6588 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6591 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6593 const aarch64_opcode
*opcode
;
6595 /* Need to check if the destination is SP/ZR. The check has to be done
6596 before any aarch64_replace_opcode. */
6597 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6598 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6600 instr
->operands
[1].imm
.value
= value
;
6601 instr
->operands
[1].skip
= 0;
6605 /* Try the MOVZ alias. */
6606 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6607 aarch64_replace_opcode (instr
, opcode
);
6608 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6609 &instr
->value
, NULL
, NULL
))
6611 put_aarch64_insn (buf
, instr
->value
);
6614 /* Try the MOVK alias. */
6615 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6616 aarch64_replace_opcode (instr
, opcode
);
6617 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6618 &instr
->value
, NULL
, NULL
))
6620 put_aarch64_insn (buf
, instr
->value
);
6625 if (try_mov_bitmask_p
)
6627 /* Try the ORR alias. */
6628 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6629 aarch64_replace_opcode (instr
, opcode
);
6630 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6631 &instr
->value
, NULL
, NULL
))
6633 put_aarch64_insn (buf
, instr
->value
);
6638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6639 _("immediate cannot be moved by a single instruction"));
6642 /* An instruction operand which is immediate related may have symbol used
6643 in the assembly, e.g.
6646 .set u32, 0x00ffff00
6648 At the time when the assembly instruction is parsed, a referenced symbol,
6649 like 'u32' in the above example may not have been seen; a fixS is created
6650 in such a case and is handled here after symbols have been resolved.
6651 Instruction is fixed up with VALUE using the information in *FIXP plus
6652 extra information in FLAGS.
6654 This function is called by md_apply_fix to fix up instructions that need
6655 a fix-up described above but does not involve any linker-time relocation. */
6658 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6662 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6663 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6664 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6668 /* Now the instruction is about to be fixed-up, so the operand that
6669 was previously marked as 'ignored' needs to be unmarked in order
6670 to get the encoding done properly. */
6671 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6672 new_inst
->operands
[idx
].skip
= 0;
6675 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6679 case AARCH64_OPND_EXCEPTION
:
6680 if (unsigned_overflow (value
, 16))
6681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6682 _("immediate out of range"));
6683 insn
= get_aarch64_insn (buf
);
6684 insn
|= encode_svc_imm (value
);
6685 put_aarch64_insn (buf
, insn
);
6688 case AARCH64_OPND_AIMM
:
6689 /* ADD or SUB with immediate.
6690 NOTE this assumes we come here with a add/sub shifted reg encoding
6691 3 322|2222|2 2 2 21111 111111
6692 1 098|7654|3 2 1 09876 543210 98765 43210
6693 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6694 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6695 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6696 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6698 3 322|2222|2 2 221111111111
6699 1 098|7654|3 2 109876543210 98765 43210
6700 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6701 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6702 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6703 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6704 Fields sf Rn Rd are already set. */
6705 insn
= get_aarch64_insn (buf
);
6709 insn
= reencode_addsub_switch_add_sub (insn
);
6713 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6714 && unsigned_overflow (value
, 12))
6716 /* Try to shift the value by 12 to make it fit. */
6717 if (((value
>> 12) << 12) == value
6718 && ! unsigned_overflow (value
, 12 + 12))
6721 insn
|= encode_addsub_imm_shift_amount (1);
6725 if (unsigned_overflow (value
, 12))
6726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6727 _("immediate out of range"));
6729 insn
|= encode_addsub_imm (value
);
6731 put_aarch64_insn (buf
, insn
);
6734 case AARCH64_OPND_SIMD_IMM
:
6735 case AARCH64_OPND_SIMD_IMM_SFT
:
6736 case AARCH64_OPND_LIMM
:
6737 /* Bit mask immediate. */
6738 gas_assert (new_inst
!= NULL
);
6739 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6740 new_inst
->operands
[idx
].imm
.value
= value
;
6741 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6742 &new_inst
->value
, NULL
, NULL
))
6743 put_aarch64_insn (buf
, new_inst
->value
);
6745 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6746 _("invalid immediate"));
6749 case AARCH64_OPND_HALF
:
6750 /* 16-bit unsigned immediate. */
6751 if (unsigned_overflow (value
, 16))
6752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6753 _("immediate out of range"));
6754 insn
= get_aarch64_insn (buf
);
6755 insn
|= encode_movw_imm (value
& 0xffff);
6756 put_aarch64_insn (buf
, insn
);
6759 case AARCH64_OPND_IMM_MOV
:
6760 /* Operand for a generic move immediate instruction, which is
6761 an alias instruction that generates a single MOVZ, MOVN or ORR
6762 instruction to loads a 32-bit/64-bit immediate value into general
6763 register. An assembler error shall result if the immediate cannot be
6764 created by a single one of these instructions. If there is a choice,
6765 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6766 and MOVZ or MOVN to ORR. */
6767 gas_assert (new_inst
!= NULL
);
6768 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6771 case AARCH64_OPND_ADDR_SIMM7
:
6772 case AARCH64_OPND_ADDR_SIMM9
:
6773 case AARCH64_OPND_ADDR_SIMM9_2
:
6774 case AARCH64_OPND_ADDR_UIMM12
:
6775 /* Immediate offset in an address. */
6776 insn
= get_aarch64_insn (buf
);
6778 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6779 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6780 || new_inst
->opcode
->operands
[2] == opnd
);
6782 /* Get the index of the address operand. */
6783 if (new_inst
->opcode
->operands
[1] == opnd
)
6784 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6787 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6790 /* Update the resolved offset value. */
6791 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6793 /* Encode/fix-up. */
6794 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6795 &new_inst
->value
, NULL
, NULL
))
6797 put_aarch64_insn (buf
, new_inst
->value
);
6800 else if (new_inst
->opcode
->iclass
== ldst_pos
6801 && try_to_encode_as_unscaled_ldst (new_inst
))
6803 put_aarch64_insn (buf
, new_inst
->value
);
6807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6808 _("immediate offset out of range"));
6813 as_fatal (_("unhandled operand code %d"), opnd
);
6817 /* Apply a fixup (fixP) to segment data, once it has been determined
6818 by our caller that we have all the info we need to fix it up.
6820 Parameter valP is the pointer to the value of the bits. */
6823 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6825 offsetT value
= *valP
;
6827 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6829 unsigned flags
= fixP
->fx_addnumber
;
6831 DEBUG_TRACE ("\n\n");
6832 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6833 DEBUG_TRACE ("Enter md_apply_fix");
6835 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6837 /* Note whether this will delete the relocation. */
6839 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6842 /* Process the relocations. */
6843 switch (fixP
->fx_r_type
)
6845 case BFD_RELOC_NONE
:
6846 /* This will need to go in the object file. */
6851 case BFD_RELOC_8_PCREL
:
6852 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6853 md_number_to_chars (buf
, value
, 1);
6857 case BFD_RELOC_16_PCREL
:
6858 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6859 md_number_to_chars (buf
, value
, 2);
6863 case BFD_RELOC_32_PCREL
:
6864 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6865 md_number_to_chars (buf
, value
, 4);
6869 case BFD_RELOC_64_PCREL
:
6870 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6871 md_number_to_chars (buf
, value
, 8);
6874 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6875 /* We claim that these fixups have been processed here, even if
6876 in fact we generate an error because we do not have a reloc
6877 for them, so tc_gen_reloc() will reject them. */
6879 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6882 _("undefined symbol %s used as an immediate value"),
6883 S_GET_NAME (fixP
->fx_addsy
));
6884 goto apply_fix_return
;
6886 fix_insn (fixP
, flags
, value
);
6889 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6890 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6893 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6894 _("pc-relative load offset not word aligned"));
6895 if (signed_overflow (value
, 21))
6896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6897 _("pc-relative load offset out of range"));
6898 insn
= get_aarch64_insn (buf
);
6899 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6900 put_aarch64_insn (buf
, insn
);
6904 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6905 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6907 if (signed_overflow (value
, 21))
6908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6909 _("pc-relative address offset out of range"));
6910 insn
= get_aarch64_insn (buf
);
6911 insn
|= encode_adr_imm (value
);
6912 put_aarch64_insn (buf
, insn
);
6916 case BFD_RELOC_AARCH64_BRANCH19
:
6917 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6921 _("conditional branch target not word aligned"));
6922 if (signed_overflow (value
, 21))
6923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6924 _("conditional branch out of range"));
6925 insn
= get_aarch64_insn (buf
);
6926 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6927 put_aarch64_insn (buf
, insn
);
6931 case BFD_RELOC_AARCH64_TSTBR14
:
6932 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6936 _("conditional branch target not word aligned"));
6937 if (signed_overflow (value
, 16))
6938 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6939 _("conditional branch out of range"));
6940 insn
= get_aarch64_insn (buf
);
6941 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6942 put_aarch64_insn (buf
, insn
);
6946 case BFD_RELOC_AARCH64_CALL26
:
6947 case BFD_RELOC_AARCH64_JUMP26
:
6948 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6952 _("branch target not word aligned"));
6953 if (signed_overflow (value
, 28))
6954 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6955 _("branch out of range"));
6956 insn
= get_aarch64_insn (buf
);
6957 insn
|= encode_branch_ofs_26 (value
>> 2);
6958 put_aarch64_insn (buf
, insn
);
6962 case BFD_RELOC_AARCH64_MOVW_G0
:
6963 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6964 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6965 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6968 case BFD_RELOC_AARCH64_MOVW_G1
:
6969 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6970 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6971 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6974 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6976 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6977 /* Should always be exported to object file, see
6978 aarch64_force_relocation(). */
6979 gas_assert (!fixP
->fx_done
);
6980 gas_assert (seg
->use_rela_p
);
6982 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6984 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6985 /* Should always be exported to object file, see
6986 aarch64_force_relocation(). */
6987 gas_assert (!fixP
->fx_done
);
6988 gas_assert (seg
->use_rela_p
);
6990 case BFD_RELOC_AARCH64_MOVW_G2
:
6991 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6992 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6995 case BFD_RELOC_AARCH64_MOVW_G3
:
6998 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7000 insn
= get_aarch64_insn (buf
);
7004 /* REL signed addend must fit in 16 bits */
7005 if (signed_overflow (value
, 16))
7006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7007 _("offset out of range"));
7011 /* Check for overflow and scale. */
7012 switch (fixP
->fx_r_type
)
7014 case BFD_RELOC_AARCH64_MOVW_G0
:
7015 case BFD_RELOC_AARCH64_MOVW_G1
:
7016 case BFD_RELOC_AARCH64_MOVW_G2
:
7017 case BFD_RELOC_AARCH64_MOVW_G3
:
7018 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7019 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7020 if (unsigned_overflow (value
, scale
+ 16))
7021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7022 _("unsigned value out of range"));
7024 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7025 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7026 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7027 /* NOTE: We can only come here with movz or movn. */
7028 if (signed_overflow (value
, scale
+ 16))
7029 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7030 _("signed value out of range"));
7033 /* Force use of MOVN. */
7035 insn
= reencode_movzn_to_movn (insn
);
7039 /* Force use of MOVZ. */
7040 insn
= reencode_movzn_to_movz (insn
);
7044 /* Unchecked relocations. */
7050 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7051 insn
|= encode_movw_imm (value
& 0xffff);
7053 put_aarch64_insn (buf
, insn
);
7057 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7058 fixP
->fx_r_type
= (ilp32_p
7059 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7060 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7061 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7062 /* Should always be exported to object file, see
7063 aarch64_force_relocation(). */
7064 gas_assert (!fixP
->fx_done
);
7065 gas_assert (seg
->use_rela_p
);
7068 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7069 fixP
->fx_r_type
= (ilp32_p
7070 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7071 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7072 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7073 /* Should always be exported to object file, see
7074 aarch64_force_relocation(). */
7075 gas_assert (!fixP
->fx_done
);
7076 gas_assert (seg
->use_rela_p
);
7079 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7080 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7081 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7082 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7083 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7084 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7085 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7086 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7087 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7088 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7089 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7090 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7091 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7092 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7093 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7094 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7095 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7096 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7097 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7098 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7099 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7100 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7101 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7102 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7103 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7104 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7105 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7106 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7107 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7108 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7109 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7110 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7111 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7112 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7113 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7114 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7115 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7116 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7117 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7118 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7119 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7120 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7121 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7122 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7123 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7124 /* Should always be exported to object file, see
7125 aarch64_force_relocation(). */
7126 gas_assert (!fixP
->fx_done
);
7127 gas_assert (seg
->use_rela_p
);
7130 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7131 /* Should always be exported to object file, see
7132 aarch64_force_relocation(). */
7133 fixP
->fx_r_type
= (ilp32_p
7134 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7135 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7136 gas_assert (!fixP
->fx_done
);
7137 gas_assert (seg
->use_rela_p
);
7140 case BFD_RELOC_AARCH64_ADD_LO12
:
7141 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7142 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7143 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7144 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7145 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7146 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7147 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7148 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7149 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7150 case BFD_RELOC_AARCH64_LDST128_LO12
:
7151 case BFD_RELOC_AARCH64_LDST16_LO12
:
7152 case BFD_RELOC_AARCH64_LDST32_LO12
:
7153 case BFD_RELOC_AARCH64_LDST64_LO12
:
7154 case BFD_RELOC_AARCH64_LDST8_LO12
:
7155 /* Should always be exported to object file, see
7156 aarch64_force_relocation(). */
7157 gas_assert (!fixP
->fx_done
);
7158 gas_assert (seg
->use_rela_p
);
7161 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7162 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7163 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7166 case BFD_RELOC_UNUSED
:
7167 /* An error will already have been reported. */
7171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7172 _("unexpected %s fixup"),
7173 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7178 /* Free the allocated the struct aarch64_inst.
7179 N.B. currently there are very limited number of fix-up types actually use
7180 this field, so the impact on the performance should be minimal . */
7181 if (fixP
->tc_fix_data
.inst
!= NULL
)
7182 free (fixP
->tc_fix_data
.inst
);
7187 /* Translate internal representation of relocation info to BFD target
7191 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7194 bfd_reloc_code_real_type code
;
7196 reloc
= XNEW (arelent
);
7198 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7199 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7200 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7204 if (section
->use_rela_p
)
7205 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7207 fixp
->fx_offset
= reloc
->address
;
7209 reloc
->addend
= fixp
->fx_offset
;
7211 code
= fixp
->fx_r_type
;
7216 code
= BFD_RELOC_16_PCREL
;
7221 code
= BFD_RELOC_32_PCREL
;
7226 code
= BFD_RELOC_64_PCREL
;
7233 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7234 if (reloc
->howto
== NULL
)
7236 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7238 ("cannot represent %s relocation in this object file format"),
7239 bfd_get_reloc_code_name (code
));
7246 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7249 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7251 bfd_reloc_code_real_type type
;
7255 FIXME: @@ Should look at CPU word size. */
7262 type
= BFD_RELOC_16
;
7265 type
= BFD_RELOC_32
;
7268 type
= BFD_RELOC_64
;
7271 as_bad (_("cannot do %u-byte relocation"), size
);
7272 type
= BFD_RELOC_UNUSED
;
7276 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7280 aarch64_force_relocation (struct fix
*fixp
)
7282 switch (fixp
->fx_r_type
)
7284 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7285 /* Perform these "immediate" internal relocations
7286 even if the symbol is extern or weak. */
7289 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7290 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7291 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7292 /* Pseudo relocs that need to be fixed up according to
7296 case BFD_RELOC_AARCH64_ADD_LO12
:
7297 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7298 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7299 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7300 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7301 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7302 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7303 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7304 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7305 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7306 case BFD_RELOC_AARCH64_LDST128_LO12
:
7307 case BFD_RELOC_AARCH64_LDST16_LO12
:
7308 case BFD_RELOC_AARCH64_LDST32_LO12
:
7309 case BFD_RELOC_AARCH64_LDST64_LO12
:
7310 case BFD_RELOC_AARCH64_LDST8_LO12
:
7311 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7312 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7313 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7314 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7315 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7316 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7317 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7318 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7319 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7320 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7321 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7322 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7323 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7324 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7325 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7326 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7327 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7328 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7329 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7330 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7331 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7332 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7333 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7334 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7335 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7336 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7337 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7338 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7339 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7340 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7341 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7342 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7343 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7344 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7345 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7346 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7347 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7348 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7349 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7350 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7351 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7352 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7353 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7354 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7355 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7356 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7357 /* Always leave these relocations for the linker. */
7364 return generic_force_reloc (fixp
);
7370 elf64_aarch64_target_format (void)
7372 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7374 /* FIXME: What to do for ilp32_p ? */
7375 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7377 if (target_big_endian
)
7378 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7380 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7384 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7386 elf_frob_symbol (symp
, puntp
);
7390 /* MD interface: Finalization. */
7392 /* A good place to do this, although this was probably not intended
7393 for this kind of use. We need to dump the literal pool before
7394 references are made to a null symbol pointer. */
7397 aarch64_cleanup (void)
7401 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7403 /* Put it at the end of the relevant section. */
7404 subseg_set (pool
->section
, pool
->sub_section
);
7410 /* Remove any excess mapping symbols generated for alignment frags in
7411 SEC. We may have created a mapping symbol before a zero byte
7412 alignment; remove it if there's a mapping symbol after the
7415 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7416 void *dummy ATTRIBUTE_UNUSED
)
7418 segment_info_type
*seginfo
= seg_info (sec
);
7421 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7424 for (fragp
= seginfo
->frchainP
->frch_root
;
7425 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7427 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7428 fragS
*next
= fragp
->fr_next
;
7430 /* Variable-sized frags have been converted to fixed size by
7431 this point. But if this was variable-sized to start with,
7432 there will be a fixed-size frag after it. So don't handle
7434 if (sym
== NULL
|| next
== NULL
)
7437 if (S_GET_VALUE (sym
) < next
->fr_address
)
7438 /* Not at the end of this frag. */
7440 know (S_GET_VALUE (sym
) == next
->fr_address
);
7444 if (next
->tc_frag_data
.first_map
!= NULL
)
7446 /* Next frag starts with a mapping symbol. Discard this
7448 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7452 if (next
->fr_next
== NULL
)
7454 /* This mapping symbol is at the end of the section. Discard
7456 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7457 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7461 /* As long as we have empty frags without any mapping symbols,
7463 /* If the next frag is non-empty and does not start with a
7464 mapping symbol, then this mapping symbol is required. */
7465 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7468 next
= next
->fr_next
;
7470 while (next
!= NULL
);
7475 /* Adjust the symbol table. */
7478 aarch64_adjust_symtab (void)
7481 /* Remove any overlapping mapping symbols generated by alignment frags. */
7482 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7483 /* Now do generic ELF adjustments. */
7484 elf_adjust_symtab ();
7489 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7491 const char *hash_err
;
7493 hash_err
= hash_insert (table
, key
, value
);
7495 printf ("Internal Error: Can't hash %s\n", key
);
7499 fill_instruction_hash_table (void)
7501 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7503 while (opcode
->name
!= NULL
)
7505 templates
*templ
, *new_templ
;
7506 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7508 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7509 new_templ
->opcode
= opcode
;
7510 new_templ
->next
= NULL
;
7513 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7516 new_templ
->next
= templ
->next
;
7517 templ
->next
= new_templ
;
7524 convert_to_upper (char *dst
, const char *src
, size_t num
)
7527 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7528 *dst
= TOUPPER (*src
);
7532 /* Assume STR point to a lower-case string, allocate, convert and return
7533 the corresponding upper-case string. */
7534 static inline const char*
7535 get_upper_str (const char *str
)
7538 size_t len
= strlen (str
);
7539 ret
= XNEWVEC (char, len
+ 1);
7540 convert_to_upper (ret
, str
, len
);
7544 /* MD interface: Initialization. */
7552 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7553 || (aarch64_cond_hsh
= hash_new ()) == NULL
7554 || (aarch64_shift_hsh
= hash_new ()) == NULL
7555 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7556 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7557 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7558 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7559 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7560 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7561 || (aarch64_reg_hsh
= hash_new ()) == NULL
7562 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7563 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7564 || (aarch64_pldop_hsh
= hash_new ()) == NULL
7565 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
7566 as_fatal (_("virtual memory exhausted"));
7568 fill_instruction_hash_table ();
7570 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7571 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7572 (void *) (aarch64_sys_regs
+ i
));
7574 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7575 checked_hash_insert (aarch64_pstatefield_hsh
,
7576 aarch64_pstatefields
[i
].name
,
7577 (void *) (aarch64_pstatefields
+ i
));
7579 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
7580 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7581 aarch64_sys_regs_ic
[i
].name
,
7582 (void *) (aarch64_sys_regs_ic
+ i
));
7584 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
7585 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7586 aarch64_sys_regs_dc
[i
].name
,
7587 (void *) (aarch64_sys_regs_dc
+ i
));
7589 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
7590 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7591 aarch64_sys_regs_at
[i
].name
,
7592 (void *) (aarch64_sys_regs_at
+ i
));
7594 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
7595 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7596 aarch64_sys_regs_tlbi
[i
].name
,
7597 (void *) (aarch64_sys_regs_tlbi
+ i
));
7599 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7600 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7601 (void *) (reg_names
+ i
));
7603 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7604 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7605 (void *) (nzcv_names
+ i
));
7607 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7609 const char *name
= aarch64_operand_modifiers
[i
].name
;
7610 checked_hash_insert (aarch64_shift_hsh
, name
,
7611 (void *) (aarch64_operand_modifiers
+ i
));
7612 /* Also hash the name in the upper case. */
7613 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7614 (void *) (aarch64_operand_modifiers
+ i
));
7617 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7620 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7621 the same condition code. */
7622 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7624 const char *name
= aarch64_conds
[i
].names
[j
];
7627 checked_hash_insert (aarch64_cond_hsh
, name
,
7628 (void *) (aarch64_conds
+ i
));
7629 /* Also hash the name in the upper case. */
7630 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7631 (void *) (aarch64_conds
+ i
));
7635 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7637 const char *name
= aarch64_barrier_options
[i
].name
;
7638 /* Skip xx00 - the unallocated values of option. */
7641 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7642 (void *) (aarch64_barrier_options
+ i
));
7643 /* Also hash the name in the upper case. */
7644 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7645 (void *) (aarch64_barrier_options
+ i
));
7648 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7650 const char* name
= aarch64_prfops
[i
].name
;
7651 /* Skip the unallocated hint encodings. */
7654 checked_hash_insert (aarch64_pldop_hsh
, name
,
7655 (void *) (aarch64_prfops
+ i
));
7656 /* Also hash the name in the upper case. */
7657 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7658 (void *) (aarch64_prfops
+ i
));
7661 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
7663 const char* name
= aarch64_hint_options
[i
].name
;
7665 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
7666 (void *) (aarch64_hint_options
+ i
));
7667 /* Also hash the name in the upper case. */
7668 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7669 (void *) (aarch64_hint_options
+ i
));
7672 /* Set the cpu variant based on the command-line options. */
7674 mcpu_cpu_opt
= march_cpu_opt
;
7677 mcpu_cpu_opt
= &cpu_default
;
7679 cpu_variant
= *mcpu_cpu_opt
;
7681 /* Record the CPU type. */
7682 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7684 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7687 /* Command line processing. */
7689 const char *md_shortopts
= "m:";
7691 #ifdef AARCH64_BI_ENDIAN
7692 #define OPTION_EB (OPTION_MD_BASE + 0)
7693 #define OPTION_EL (OPTION_MD_BASE + 1)
7695 #if TARGET_BYTES_BIG_ENDIAN
7696 #define OPTION_EB (OPTION_MD_BASE + 0)
7698 #define OPTION_EL (OPTION_MD_BASE + 1)
7702 struct option md_longopts
[] = {
7704 {"EB", no_argument
, NULL
, OPTION_EB
},
7707 {"EL", no_argument
, NULL
, OPTION_EL
},
7709 {NULL
, no_argument
, NULL
, 0}
7712 size_t md_longopts_size
= sizeof (md_longopts
);
7714 struct aarch64_option_table
7716 const char *option
; /* Option name to match. */
7717 const char *help
; /* Help information. */
7718 int *var
; /* Variable to change. */
7719 int value
; /* What to change it to. */
7720 char *deprecated
; /* If non-null, print this message. */
7723 static struct aarch64_option_table aarch64_opts
[] = {
7724 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7725 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7727 #ifdef DEBUG_AARCH64
7728 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7729 #endif /* DEBUG_AARCH64 */
7730 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7732 {"mno-verbose-error", N_("do not output verbose error messages"),
7733 &verbose_error_p
, 0, NULL
},
7734 {NULL
, NULL
, NULL
, 0, NULL
}
7737 struct aarch64_cpu_option_table
7740 const aarch64_feature_set value
;
7741 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7743 const char *canonical_name
;
7746 /* This list should, at a minimum, contain all the cpu names
7747 recognized by GCC. */
7748 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7749 {"all", AARCH64_ANY
, NULL
},
7750 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7751 AARCH64_FEATURE_CRC
), "Cortex-A35"},
7752 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7753 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7754 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7755 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7756 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7757 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7758 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7759 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7760 "Samsung Exynos M1"},
7761 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7762 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7763 "Qualcomm QDF24XX"},
7764 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7765 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7767 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7768 in earlier releases and is superseded by 'xgene1' in all
7770 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7771 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7772 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7773 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7774 {"generic", AARCH64_ARCH_V8
, NULL
},
7776 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7779 struct aarch64_arch_option_table
7782 const aarch64_feature_set value
;
7785 /* This list should, at a minimum, contain all the architecture names
7786 recognized by GCC. */
7787 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7788 {"all", AARCH64_ANY
},
7789 {"armv8-a", AARCH64_ARCH_V8
},
7790 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7791 {"armv8.2-a", AARCH64_ARCH_V8_2
},
7792 {NULL
, AARCH64_ARCH_NONE
}
7795 /* ISA extensions. */
7796 struct aarch64_option_cpu_value_table
7799 const aarch64_feature_set value
;
7802 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7803 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7804 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7805 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7806 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7807 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7808 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0)},
7809 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0)},
7810 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0)},
7811 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7812 | AARCH64_FEATURE_RDMA
, 0)},
7813 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
7814 | AARCH64_FEATURE_FP
, 0)},
7815 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0)},
7816 {NULL
, AARCH64_ARCH_NONE
}
7819 struct aarch64_long_option_table
7821 const char *option
; /* Substring to match. */
7822 const char *help
; /* Help information. */
7823 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
7824 char *deprecated
; /* If non-null, print this message. */
7828 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
7829 bfd_boolean ext_only
)
7831 /* We insist on extensions being added before being removed. We achieve
7832 this by using the ADDING_VALUE variable to indicate whether we are
7833 adding an extension (1) or removing it (0) and only allowing it to
7834 change in the order -1 -> 1 -> 0. */
7835 int adding_value
= -1;
7836 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
7838 /* Copy the feature set, so that we can modify it. */
7842 while (str
!= NULL
&& *str
!= 0)
7844 const struct aarch64_option_cpu_value_table
*opt
;
7845 const char *ext
= NULL
;
7852 as_bad (_("invalid architectural extension"));
7856 ext
= strchr (++str
, '+');
7862 optlen
= strlen (str
);
7864 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7866 if (adding_value
!= 0)
7871 else if (optlen
> 0)
7873 if (adding_value
== -1)
7875 else if (adding_value
!= 1)
7877 as_bad (_("must specify extensions to add before specifying "
7878 "those to remove"));
7885 as_bad (_("missing architectural extension"));
7889 gas_assert (adding_value
!= -1);
7891 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7892 if (strncmp (opt
->name
, str
, optlen
) == 0)
7894 /* Add or remove the extension. */
7896 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7898 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7902 if (opt
->name
== NULL
)
7904 as_bad (_("unknown architectural extension `%s'"), str
);
7915 aarch64_parse_cpu (const char *str
)
7917 const struct aarch64_cpu_option_table
*opt
;
7918 const char *ext
= strchr (str
, '+');
7924 optlen
= strlen (str
);
7928 as_bad (_("missing cpu name `%s'"), str
);
7932 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7933 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7935 mcpu_cpu_opt
= &opt
->value
;
7937 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7942 as_bad (_("unknown cpu `%s'"), str
);
7947 aarch64_parse_arch (const char *str
)
7949 const struct aarch64_arch_option_table
*opt
;
7950 const char *ext
= strchr (str
, '+');
7956 optlen
= strlen (str
);
7960 as_bad (_("missing architecture name `%s'"), str
);
7964 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7965 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7967 march_cpu_opt
= &opt
->value
;
7969 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7974 as_bad (_("unknown architecture `%s'\n"), str
);
7979 struct aarch64_option_abi_value_table
7982 enum aarch64_abi_type value
;
7985 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7986 {"ilp32", AARCH64_ABI_ILP32
},
7987 {"lp64", AARCH64_ABI_LP64
},
7992 aarch64_parse_abi (const char *str
)
7994 const struct aarch64_option_abi_value_table
*opt
;
7995 size_t optlen
= strlen (str
);
7999 as_bad (_("missing abi name `%s'"), str
);
8003 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
8004 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8006 aarch64_abi
= opt
->value
;
8010 as_bad (_("unknown abi `%s'\n"), str
);
8014 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8016 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8017 aarch64_parse_abi
, NULL
},
8018 #endif /* OBJ_ELF */
8019 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8020 aarch64_parse_cpu
, NULL
},
8021 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8022 aarch64_parse_arch
, NULL
},
8023 {NULL
, NULL
, 0, NULL
}
8027 md_parse_option (int c
, const char *arg
)
8029 struct aarch64_option_table
*opt
;
8030 struct aarch64_long_option_table
*lopt
;
8036 target_big_endian
= 1;
8042 target_big_endian
= 0;
8047 /* Listing option. Just ignore these, we don't support additional
8052 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8054 if (c
== opt
->option
[0]
8055 && ((arg
== NULL
&& opt
->option
[1] == 0)
8056 || streq (arg
, opt
->option
+ 1)))
8058 /* If the option is deprecated, tell the user. */
8059 if (opt
->deprecated
!= NULL
)
8060 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8061 arg
? arg
: "", _(opt
->deprecated
));
8063 if (opt
->var
!= NULL
)
8064 *opt
->var
= opt
->value
;
8070 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8072 /* These options are expected to have an argument. */
8073 if (c
== lopt
->option
[0]
8075 && strncmp (arg
, lopt
->option
+ 1,
8076 strlen (lopt
->option
+ 1)) == 0)
8078 /* If the option is deprecated, tell the user. */
8079 if (lopt
->deprecated
!= NULL
)
8080 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8081 _(lopt
->deprecated
));
8083 /* Call the sup-option parser. */
8084 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8095 md_show_usage (FILE * fp
)
8097 struct aarch64_option_table
*opt
;
8098 struct aarch64_long_option_table
*lopt
;
8100 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8102 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8103 if (opt
->help
!= NULL
)
8104 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8106 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8107 if (lopt
->help
!= NULL
)
8108 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8112 -EB assemble code for a big-endian cpu\n"));
8117 -EL assemble code for a little-endian cpu\n"));
8121 /* Parse a .cpu directive. */
8124 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8126 const struct aarch64_cpu_option_table
*opt
;
8132 name
= input_line_pointer
;
8133 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8134 input_line_pointer
++;
8135 saved_char
= *input_line_pointer
;
8136 *input_line_pointer
= 0;
8138 ext
= strchr (name
, '+');
8141 optlen
= ext
- name
;
8143 optlen
= strlen (name
);
8145 /* Skip the first "all" entry. */
8146 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8147 if (strlen (opt
->name
) == optlen
8148 && strncmp (name
, opt
->name
, optlen
) == 0)
8150 mcpu_cpu_opt
= &opt
->value
;
8152 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8155 cpu_variant
= *mcpu_cpu_opt
;
8157 *input_line_pointer
= saved_char
;
8158 demand_empty_rest_of_line ();
8161 as_bad (_("unknown cpu `%s'"), name
);
8162 *input_line_pointer
= saved_char
;
8163 ignore_rest_of_line ();
8167 /* Parse a .arch directive. */
8170 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8172 const struct aarch64_arch_option_table
*opt
;
8178 name
= input_line_pointer
;
8179 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8180 input_line_pointer
++;
8181 saved_char
= *input_line_pointer
;
8182 *input_line_pointer
= 0;
8184 ext
= strchr (name
, '+');
8187 optlen
= ext
- name
;
8189 optlen
= strlen (name
);
8191 /* Skip the first "all" entry. */
8192 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8193 if (strlen (opt
->name
) == optlen
8194 && strncmp (name
, opt
->name
, optlen
) == 0)
8196 mcpu_cpu_opt
= &opt
->value
;
8198 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8201 cpu_variant
= *mcpu_cpu_opt
;
8203 *input_line_pointer
= saved_char
;
8204 demand_empty_rest_of_line ();
8208 as_bad (_("unknown architecture `%s'\n"), name
);
8209 *input_line_pointer
= saved_char
;
8210 ignore_rest_of_line ();
8213 /* Parse a .arch_extension directive. */
8216 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8219 char *ext
= input_line_pointer
;;
8221 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8222 input_line_pointer
++;
8223 saved_char
= *input_line_pointer
;
8224 *input_line_pointer
= 0;
8226 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8229 cpu_variant
= *mcpu_cpu_opt
;
8231 *input_line_pointer
= saved_char
;
8232 demand_empty_rest_of_line ();
8235 /* Copy symbol information. */
8238 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8240 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);