1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
71 #define DEFAULT_ARCH "aarch64"
74 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
75 static const char *default_arch
= DEFAULT_ARCH
;
77 /* AArch64 ABI for the output file. */
78 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
80 /* When non-zero, program to a 32-bit model, in which the C data types
81 int, long and all pointer types are 32-bit objects (ILP32); or to a
82 64-bit model, in which the C int type is 32-bits but the C long type
83 and all pointer types are 64-bit objects (LP64). */
84 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
99 /* Bits for DEFINED field in vector_type_el. */
100 #define NTA_HASTYPE 1
101 #define NTA_HASINDEX 2
102 #define NTA_HASVARWIDTH 4
104 struct vector_type_el
106 enum vector_el_type type
;
107 unsigned char defined
;
112 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
116 bfd_reloc_code_real_type type
;
119 enum aarch64_opnd opnd
;
121 unsigned need_libopcodes_p
: 1;
124 struct aarch64_instruction
126 /* libopcodes structure for instruction intermediate representation. */
128 /* Record assembly errors found during the parsing. */
131 enum aarch64_operand_error_kind kind
;
134 /* The condition that appears in the assembly line. */
136 /* Relocation information (including the GAS internal fixup). */
138 /* Need to generate an immediate in the literal pool. */
139 unsigned gen_lit_pool
: 1;
142 typedef struct aarch64_instruction aarch64_instruction
;
144 static aarch64_instruction inst
;
146 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
147 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
149 /* Diagnostics inline function utilities.
151 These are lightweight utilities which should only be called by parse_operands
152 and other parsers. GAS processes each assembly line by parsing it against
153 instruction template(s), in the case of multiple templates (for the same
154 mnemonic name), those templates are tried one by one until one succeeds or
155 all fail. An assembly line may fail a few templates before being
156 successfully parsed; an error saved here in most cases is not a user error
157 but an error indicating the current template is not the right template.
158 Therefore it is very important that errors can be saved at a low cost during
159 the parsing; we don't want to slow down the whole parsing by recording
160 non-user errors in detail.
162 Remember that the objective is to help GAS pick up the most appropriate
163 error message in the case of multiple templates, e.g. FMOV which has 8
169 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
170 inst
.parsing_error
.error
= NULL
;
173 static inline bfd_boolean
176 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
179 static inline const char *
180 get_error_message (void)
182 return inst
.parsing_error
.error
;
185 static inline enum aarch64_operand_error_kind
186 get_error_kind (void)
188 return inst
.parsing_error
.kind
;
192 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
194 inst
.parsing_error
.kind
= kind
;
195 inst
.parsing_error
.error
= error
;
199 set_recoverable_error (const char *error
)
201 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
204 /* Use the DESC field of the corresponding aarch64_operand entry to compose
205 the error message. */
207 set_default_error (void)
209 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
213 set_syntax_error (const char *error
)
215 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
219 set_first_syntax_error (const char *error
)
222 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
226 set_fatal_syntax_error (const char *error
)
228 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
231 /* Number of littlenums required to hold an extended precision number. */
232 #define MAX_LITTLENUMS 6
234 /* Return value for certain parsers when the parsing fails; those parsers
235 return the information of the parsed result, e.g. register number, on
237 #define PARSE_FAIL -1
239 /* This is an invalid condition code that means no conditional field is
241 #define COND_ALWAYS 0x10
245 const char *template;
251 const char *template;
258 bfd_reloc_code_real_type reloc
;
261 /* Macros to define the register types and masks for the purpose
264 #undef AARCH64_REG_TYPES
265 #define AARCH64_REG_TYPES \
266 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
267 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
268 BASIC_REG_TYPE(SP_32) /* wsp */ \
269 BASIC_REG_TYPE(SP_64) /* sp */ \
270 BASIC_REG_TYPE(Z_32) /* wzr */ \
271 BASIC_REG_TYPE(Z_64) /* xzr */ \
272 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
273 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
274 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
275 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
276 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
277 BASIC_REG_TYPE(VN) /* v[0-31] */ \
278 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
279 BASIC_REG_TYPE(PN) /* p[0-15] */ \
280 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
281 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
282 /* Typecheck: same, plus SVE registers. */ \
283 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
285 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
286 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
287 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
288 /* Typecheck: same, plus SVE registers. */ \
289 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
292 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
293 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
295 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
296 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
298 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
299 /* Typecheck: any [BHSDQ]P FP. */ \
300 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
301 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
302 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
305 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
306 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
307 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
308 be used for SVE instructions, since Zn and Pn are valid symbols \
309 in other contexts. */ \
310 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
312 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
313 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
314 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
315 | REG_TYPE(ZN) | REG_TYPE(PN)) \
316 /* Any integer register; used for error messages only. */ \
317 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
320 /* Pseudo type to mark the end of the enumerator sequence. */ \
323 #undef BASIC_REG_TYPE
324 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
325 #undef MULTI_REG_TYPE
326 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
328 /* Register type enumerators. */
329 typedef enum aarch64_reg_type_
331 /* A list of REG_TYPE_*. */
335 #undef BASIC_REG_TYPE
336 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
338 #define REG_TYPE(T) (1 << REG_TYPE_##T)
339 #undef MULTI_REG_TYPE
340 #define MULTI_REG_TYPE(T,V) V,
342 /* Structure for a hash table entry for a register. */
346 unsigned char number
;
347 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
348 unsigned char builtin
;
351 /* Values indexed by aarch64_reg_type to assist the type checking. */
352 static const unsigned reg_type_masks
[] =
357 #undef BASIC_REG_TYPE
359 #undef MULTI_REG_TYPE
360 #undef AARCH64_REG_TYPES
362 /* Diagnostics used when we don't get a register of the expected type.
363 Note: this has to synchronized with aarch64_reg_type definitions
366 get_reg_expected_msg (aarch64_reg_type reg_type
)
373 msg
= N_("integer 32-bit register expected");
376 msg
= N_("integer 64-bit register expected");
379 msg
= N_("integer register expected");
381 case REG_TYPE_R64_SP
:
382 msg
= N_("64-bit integer or SP register expected");
384 case REG_TYPE_SVE_BASE
:
385 msg
= N_("base register expected");
388 msg
= N_("integer or zero register expected");
390 case REG_TYPE_SVE_OFFSET
:
391 msg
= N_("offset register expected");
394 msg
= N_("integer or SP register expected");
396 case REG_TYPE_R_Z_SP
:
397 msg
= N_("integer, zero or SP register expected");
400 msg
= N_("8-bit SIMD scalar register expected");
403 msg
= N_("16-bit SIMD scalar or floating-point half precision "
404 "register expected");
407 msg
= N_("32-bit SIMD scalar or floating-point single precision "
408 "register expected");
411 msg
= N_("64-bit SIMD scalar or floating-point double precision "
412 "register expected");
415 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
416 "register expected");
418 case REG_TYPE_R_Z_BHSDQ_V
:
419 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
420 msg
= N_("register expected");
422 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
423 msg
= N_("SIMD scalar or floating-point register expected");
425 case REG_TYPE_VN
: /* any V reg */
426 msg
= N_("vector register expected");
429 msg
= N_("SVE vector register expected");
432 msg
= N_("SVE predicate register expected");
435 as_fatal (_("invalid register type %d"), reg_type
);
440 /* Some well known registers that we refer to directly elsewhere. */
443 /* Instructions take 4 bytes in the object file. */
446 static struct hash_control
*aarch64_ops_hsh
;
447 static struct hash_control
*aarch64_cond_hsh
;
448 static struct hash_control
*aarch64_shift_hsh
;
449 static struct hash_control
*aarch64_sys_regs_hsh
;
450 static struct hash_control
*aarch64_pstatefield_hsh
;
451 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
452 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
453 static struct hash_control
*aarch64_sys_regs_at_hsh
;
454 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
455 static struct hash_control
*aarch64_reg_hsh
;
456 static struct hash_control
*aarch64_barrier_opt_hsh
;
457 static struct hash_control
*aarch64_nzcv_hsh
;
458 static struct hash_control
*aarch64_pldop_hsh
;
459 static struct hash_control
*aarch64_hint_opt_hsh
;
461 /* Stuff needed to resolve the label ambiguity
470 static symbolS
*last_label_seen
;
472 /* Literal pool structure. Held on a per-section
473 and per-sub-section basis. */
475 #define MAX_LITERAL_POOL_SIZE 1024
476 typedef struct literal_expression
479 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
480 LITTLENUM_TYPE
* bignum
;
481 } literal_expression
;
483 typedef struct literal_pool
485 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
486 unsigned int next_free_entry
;
492 struct literal_pool
*next
;
495 /* Pointer to a linked list of literal pools. */
496 static literal_pool
*list_of_pools
= NULL
;
500 /* This array holds the chars that always start a comment. If the
501 pre-processor is disabled, these aren't very useful. */
502 const char comment_chars
[] = "";
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output. */
507 /* Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output. */
510 /* Also note that comments like this one will always work. */
511 const char line_comment_chars
[] = "#";
513 const char line_separator_chars
[] = ";";
515 /* Chars that can be used to separate mant
516 from exp in floating point numbers. */
517 const char EXP_CHARS
[] = "eE";
519 /* Chars that mean this number is a floating point constant. */
523 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
525 /* Prefix character that indicates the start of an immediate value. */
526 #define is_immediate_prefix(C) ((C) == '#')
528 /* Separator character handling. */
530 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
532 static inline bfd_boolean
533 skip_past_char (char **str
, char c
)
544 #define skip_past_comma(str) skip_past_char (str, ',')
546 /* Arithmetic expressions (possibly involving symbols). */
548 static bfd_boolean in_my_get_expression_p
= FALSE
;
550 /* Third argument to my_get_expression. */
551 #define GE_NO_PREFIX 0
552 #define GE_OPT_PREFIX 1
554 /* Return TRUE if the string pointed by *STR is successfully parsed
555 as an valid expression; *EP will be filled with the information of
556 such an expression. Otherwise return FALSE. */
559 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
564 int prefix_present_p
= 0;
571 if (is_immediate_prefix (**str
))
574 prefix_present_p
= 1;
581 memset (ep
, 0, sizeof (expressionS
));
583 save_in
= input_line_pointer
;
584 input_line_pointer
= *str
;
585 in_my_get_expression_p
= TRUE
;
586 seg
= expression (ep
);
587 in_my_get_expression_p
= FALSE
;
589 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
591 /* We found a bad expression in md_operand(). */
592 *str
= input_line_pointer
;
593 input_line_pointer
= save_in
;
594 if (prefix_present_p
&& ! error_p ())
595 set_fatal_syntax_error (_("bad expression"));
597 set_first_syntax_error (_("bad expression"));
602 if (seg
!= absolute_section
603 && seg
!= text_section
604 && seg
!= data_section
605 && seg
!= bss_section
&& seg
!= undefined_section
)
607 set_syntax_error (_("bad segment"));
608 *str
= input_line_pointer
;
609 input_line_pointer
= save_in
;
616 *str
= input_line_pointer
;
617 input_line_pointer
= save_in
;
621 /* Turn a string in input_line_pointer into a floating point constant
622 of type TYPE, and store the appropriate bytes in *LITP. The number
623 of LITTLENUMS emitted is stored in *SIZEP. An error message is
624 returned, or NULL on OK. */
627 md_atof (int type
, char *litP
, int *sizeP
)
629 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
632 /* We handle all bad expressions here, so that we can report the faulty
633 instruction in the error message. */
635 md_operand (expressionS
* exp
)
637 if (in_my_get_expression_p
)
638 exp
->X_op
= O_illegal
;
641 /* Immediate values. */
643 /* Errors may be set multiple times during parsing or bit encoding
644 (particularly in the Neon bits), but usually the earliest error which is set
645 will be the most meaningful. Avoid overwriting it with later (cascading)
646 errors by calling this function. */
649 first_error (const char *error
)
652 set_syntax_error (error
);
655 /* Similar to first_error, but this function accepts formatted error
658 first_error_fmt (const char *format
, ...)
663 /* N.B. this single buffer will not cause error messages for different
664 instructions to pollute each other; this is because at the end of
665 processing of each assembly line, error message if any will be
666 collected by as_bad. */
667 static char buffer
[size
];
671 int ret ATTRIBUTE_UNUSED
;
672 va_start (args
, format
);
673 ret
= vsnprintf (buffer
, size
, format
, args
);
674 know (ret
<= size
- 1 && ret
>= 0);
676 set_syntax_error (buffer
);
680 /* Register parsing. */
682 /* Generic register parser which is called by other specialized
684 CCP points to what should be the beginning of a register name.
685 If it is indeed a valid register name, advance CCP over it and
686 return the reg_entry structure; otherwise return NULL.
687 It does not issue diagnostics. */
690 parse_reg (char **ccp
)
696 #ifdef REGISTER_PREFIX
697 if (*start
!= REGISTER_PREFIX
)
703 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
708 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
710 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
719 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
722 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
724 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
727 /* Try to parse a base or offset register. Allow SVE base and offset
728 registers if REG_TYPE includes SVE registers. Return the register
729 entry on success, setting *QUALIFIER to the register qualifier.
730 Return null otherwise.
732 Note that this function does not issue any diagnostics. */
734 static const reg_entry
*
735 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
736 aarch64_opnd_qualifier_t
*qualifier
)
739 const reg_entry
*reg
= parse_reg (&str
);
749 *qualifier
= AARCH64_OPND_QLF_W
;
755 *qualifier
= AARCH64_OPND_QLF_X
;
759 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
762 switch (TOLOWER (str
[1]))
765 *qualifier
= AARCH64_OPND_QLF_S_S
;
768 *qualifier
= AARCH64_OPND_QLF_S_D
;
785 /* Try to parse a base or offset register. Return the register entry
786 on success, setting *QUALIFIER to the register qualifier. Return null
789 Note that this function does not issue any diagnostics. */
791 static const reg_entry
*
792 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
794 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
797 /* Parse the qualifier of a vector register or vector element of type
798 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
799 succeeds; otherwise return FALSE.
801 Accept only one occurrence of:
802 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
805 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
806 struct vector_type_el
*parsed_type
, char **str
)
810 unsigned element_size
;
811 enum vector_el_type type
;
814 gas_assert (*ptr
== '.');
817 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
822 width
= strtoul (ptr
, &ptr
, 10);
823 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
825 first_error_fmt (_("bad size %d in vector width specifier"), width
);
830 switch (TOLOWER (*ptr
))
849 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
858 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
860 first_error (_("missing element size"));
863 if (width
!= 0 && width
* element_size
!= 64
864 && width
* element_size
!= 128
865 && !(width
== 2 && element_size
== 16)
866 && !(width
== 4 && element_size
== 8))
869 ("invalid element size %d and vector size combination %c"),
875 parsed_type
->type
= type
;
876 parsed_type
->width
= width
;
883 /* *STR contains an SVE zero/merge predication suffix. Parse it into
884 *PARSED_TYPE and point *STR at the end of the suffix. */
887 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
892 gas_assert (*ptr
== '/');
894 switch (TOLOWER (*ptr
))
897 parsed_type
->type
= NT_zero
;
900 parsed_type
->type
= NT_merge
;
903 if (*ptr
!= '\0' && *ptr
!= ',')
904 first_error_fmt (_("unexpected character `%c' in predication type"),
907 first_error (_("missing predication type"));
910 parsed_type
->width
= 0;
915 /* Parse a register of the type TYPE.
917 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
918 name or the parsed register is not of TYPE.
920 Otherwise return the register number, and optionally fill in the actual
921 type of the register in *RTYPE when multiple alternatives were given, and
922 return the register shape and element index information in *TYPEINFO.
924 IN_REG_LIST should be set with TRUE if the caller is parsing a register
928 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
929 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
932 const reg_entry
*reg
= parse_reg (&str
);
933 struct vector_type_el atype
;
934 struct vector_type_el parsetype
;
935 bfd_boolean is_typed_vecreg
= FALSE
;
938 atype
.type
= NT_invtype
;
946 set_default_error ();
950 if (! aarch64_check_reg_type (reg
, type
))
952 DEBUG_TRACE ("reg type check failed");
953 set_default_error ();
958 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
959 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
963 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
968 if (!parse_predication_for_operand (&parsetype
, &str
))
972 /* Register if of the form Vn.[bhsdq]. */
973 is_typed_vecreg
= TRUE
;
975 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
977 /* The width is always variable; we don't allow an integer width
979 gas_assert (parsetype
.width
== 0);
980 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
982 else if (parsetype
.width
== 0)
983 /* Expect index. In the new scheme we cannot have
984 Vn.[bhsdq] represent a scalar. Therefore any
985 Vn.[bhsdq] should have an index following it.
986 Except in reglists of course. */
987 atype
.defined
|= NTA_HASINDEX
;
989 atype
.defined
|= NTA_HASTYPE
;
991 atype
.type
= parsetype
.type
;
992 atype
.width
= parsetype
.width
;
995 if (skip_past_char (&str
, '['))
999 /* Reject Sn[index] syntax. */
1000 if (!is_typed_vecreg
)
1002 first_error (_("this type of register can't be indexed"));
1008 first_error (_("index not allowed inside register list"));
1012 atype
.defined
|= NTA_HASINDEX
;
1014 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1016 if (exp
.X_op
!= O_constant
)
1018 first_error (_("constant expression required"));
1022 if (! skip_past_char (&str
, ']'))
1025 atype
.index
= exp
.X_add_number
;
1027 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1029 /* Indexed vector register expected. */
1030 first_error (_("indexed vector register expected"));
1034 /* A vector reg Vn should be typed or indexed. */
1035 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1037 first_error (_("invalid use of vector register"));
1053 Return the register number on success; return PARSE_FAIL otherwise.
1055 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1056 the register (e.g. NEON double or quad reg when either has been requested).
1058 If this is a NEON vector register with additional type information, fill
1059 in the struct pointed to by VECTYPE (if non-NULL).
1061 This parser does not handle register list. */
1064 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1065 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1067 struct vector_type_el atype
;
1069 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1070 /*in_reg_list= */ FALSE
);
1072 if (reg
== PARSE_FAIL
)
1083 static inline bfd_boolean
1084 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1088 && e1
.defined
== e2
.defined
1089 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1092 /* This function parses a list of vector registers of type TYPE.
1093 On success, it returns the parsed register list information in the
1094 following encoded format:
1096 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1097 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1099 The information of the register shape and/or index is returned in
1102 It returns PARSE_FAIL if the register list is invalid.
1104 The list contains one to four registers.
1105 Each register can be one of:
1108 All <T> should be identical.
1109 All <index> should be identical.
1110 There are restrictions on <Vt> numbers which are checked later
1111 (by reg_list_valid_p). */
1114 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1115 struct vector_type_el
*vectype
)
1119 struct vector_type_el typeinfo
, typeinfo_first
;
1124 bfd_boolean error
= FALSE
;
1125 bfd_boolean expect_index
= FALSE
;
1129 set_syntax_error (_("expecting {"));
1135 typeinfo_first
.defined
= 0;
1136 typeinfo_first
.type
= NT_invtype
;
1137 typeinfo_first
.width
= -1;
1138 typeinfo_first
.index
= 0;
1147 str
++; /* skip over '-' */
1150 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1151 /*in_reg_list= */ TRUE
);
1152 if (val
== PARSE_FAIL
)
1154 set_first_syntax_error (_("invalid vector register in list"));
1158 /* reject [bhsd]n */
1159 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1161 set_first_syntax_error (_("invalid scalar register in list"));
1166 if (typeinfo
.defined
& NTA_HASINDEX
)
1167 expect_index
= TRUE
;
1171 if (val
< val_range
)
1173 set_first_syntax_error
1174 (_("invalid range in vector register list"));
1183 typeinfo_first
= typeinfo
;
1184 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1186 set_first_syntax_error
1187 (_("type mismatch in vector register list"));
1192 for (i
= val_range
; i
<= val
; i
++)
1194 ret_val
|= i
<< (5 * nb_regs
);
1199 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1201 skip_whitespace (str
);
1204 set_first_syntax_error (_("end of vector register list not found"));
1209 skip_whitespace (str
);
1213 if (skip_past_char (&str
, '['))
1217 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1218 if (exp
.X_op
!= O_constant
)
1220 set_first_syntax_error (_("constant expression required."));
1223 if (! skip_past_char (&str
, ']'))
1226 typeinfo_first
.index
= exp
.X_add_number
;
1230 set_first_syntax_error (_("expected index"));
1237 set_first_syntax_error (_("too many registers in vector register list"));
1240 else if (nb_regs
== 0)
1242 set_first_syntax_error (_("empty vector register list"));
1248 *vectype
= typeinfo_first
;
1250 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1253 /* Directives: register aliases. */
1256 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1261 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1264 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1267 /* Only warn about a redefinition if it's not defined as the
1269 else if (new->number
!= number
|| new->type
!= type
)
1270 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1275 name
= xstrdup (str
);
1276 new = XNEW (reg_entry
);
1279 new->number
= number
;
1281 new->builtin
= FALSE
;
1283 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1289 /* Look for the .req directive. This is of the form:
1291 new_register_name .req existing_register_name
1293 If we find one, or if it looks sufficiently like one that we want to
1294 handle any error here, return TRUE. Otherwise return FALSE. */
1297 create_register_alias (char *newname
, char *p
)
1299 const reg_entry
*old
;
1300 char *oldname
, *nbuf
;
1303 /* The input scrubber ensures that whitespace after the mnemonic is
1304 collapsed to single spaces. */
1306 if (strncmp (oldname
, " .req ", 6) != 0)
1310 if (*oldname
== '\0')
1313 old
= hash_find (aarch64_reg_hsh
, oldname
);
1316 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1320 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1321 the desired alias name, and p points to its end. If not, then
1322 the desired alias name is in the global original_case_string. */
1323 #ifdef TC_CASE_SENSITIVE
1326 newname
= original_case_string
;
1327 nlen
= strlen (newname
);
1330 nbuf
= xmemdup0 (newname
, nlen
);
1332 /* Create aliases under the new name as stated; an all-lowercase
1333 version of the new name; and an all-uppercase version of the new
1335 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1337 for (p
= nbuf
; *p
; p
++)
1340 if (strncmp (nbuf
, newname
, nlen
))
1342 /* If this attempt to create an additional alias fails, do not bother
1343 trying to create the all-lower case alias. We will fail and issue
1344 a second, duplicate error message. This situation arises when the
1345 programmer does something like:
1348 The second .req creates the "Foo" alias but then fails to create
1349 the artificial FOO alias because it has already been created by the
1351 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1358 for (p
= nbuf
; *p
; p
++)
1361 if (strncmp (nbuf
, newname
, nlen
))
1362 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1369 /* Should never be called, as .req goes between the alias and the
1370 register name, not at the beginning of the line. */
1372 s_req (int a ATTRIBUTE_UNUSED
)
1374 as_bad (_("invalid syntax for .req directive"));
1377 /* The .unreq directive deletes an alias which was previously defined
1378 by .req. For example:
1384 s_unreq (int a ATTRIBUTE_UNUSED
)
1389 name
= input_line_pointer
;
1391 while (*input_line_pointer
!= 0
1392 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1393 ++input_line_pointer
;
1395 saved_char
= *input_line_pointer
;
1396 *input_line_pointer
= 0;
1399 as_bad (_("invalid syntax for .unreq directive"));
1402 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1405 as_bad (_("unknown register alias '%s'"), name
);
1406 else if (reg
->builtin
)
1407 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1414 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1415 free ((char *) reg
->name
);
1418 /* Also locate the all upper case and all lower case versions.
1419 Do not complain if we cannot find one or the other as it
1420 was probably deleted above. */
1422 nbuf
= strdup (name
);
1423 for (p
= nbuf
; *p
; p
++)
1425 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1428 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1429 free ((char *) reg
->name
);
1433 for (p
= nbuf
; *p
; p
++)
1435 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1438 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1439 free ((char *) reg
->name
);
1447 *input_line_pointer
= saved_char
;
1448 demand_empty_rest_of_line ();
1451 /* Directives: Instruction set selection. */
1454 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1455 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1456 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1457 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1459 /* Create a new mapping symbol for the transition to STATE. */
1462 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1465 const char *symname
;
1472 type
= BSF_NO_FLAGS
;
1476 type
= BSF_NO_FLAGS
;
1482 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1483 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1485 /* Save the mapping symbols for future reference. Also check that
1486 we do not place two mapping symbols at the same offset within a
1487 frag. We'll handle overlap between frags in
1488 check_mapping_symbols.
1490 If .fill or other data filling directive generates zero sized data,
1491 the mapping symbol for the following code will have the same value
1492 as the one generated for the data filling directive. In this case,
1493 we replace the old symbol with the new one at the same address. */
1496 if (frag
->tc_frag_data
.first_map
!= NULL
)
1498 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1499 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1502 frag
->tc_frag_data
.first_map
= symbolP
;
1504 if (frag
->tc_frag_data
.last_map
!= NULL
)
1506 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1507 S_GET_VALUE (symbolP
));
1508 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1509 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1512 frag
->tc_frag_data
.last_map
= symbolP
;
1515 /* We must sometimes convert a region marked as code to data during
1516 code alignment, if an odd number of bytes have to be padded. The
1517 code mapping symbol is pushed to an aligned address. */
1520 insert_data_mapping_symbol (enum mstate state
,
1521 valueT value
, fragS
* frag
, offsetT bytes
)
1523 /* If there was already a mapping symbol, remove it. */
1524 if (frag
->tc_frag_data
.last_map
!= NULL
1525 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1526 frag
->fr_address
+ value
)
1528 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1532 know (frag
->tc_frag_data
.first_map
== symp
);
1533 frag
->tc_frag_data
.first_map
= NULL
;
1535 frag
->tc_frag_data
.last_map
= NULL
;
1536 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1539 make_mapping_symbol (MAP_DATA
, value
, frag
);
1540 make_mapping_symbol (state
, value
+ bytes
, frag
);
1543 static void mapping_state_2 (enum mstate state
, int max_chars
);
1545 /* Set the mapping state to STATE. Only call this when about to
1546 emit some STATE bytes to the file. */
1549 mapping_state (enum mstate state
)
1551 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1553 if (state
== MAP_INSN
)
1554 /* AArch64 instructions require 4-byte alignment. When emitting
1555 instructions into any section, record the appropriate section
1557 record_alignment (now_seg
, 2);
1559 if (mapstate
== state
)
1560 /* The mapping symbol has already been emitted.
1561 There is nothing else to do. */
1564 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1565 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1566 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1567 evaluated later in the next else. */
1569 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1571 /* Only add the symbol if the offset is > 0:
1572 if we're at the first frag, check it's size > 0;
1573 if we're not at the first frag, then for sure
1574 the offset is > 0. */
1575 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1576 const int add_symbol
= (frag_now
!= frag_first
)
1577 || (frag_now_fix () > 0);
1580 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1584 mapping_state_2 (state
, 0);
1587 /* Same as mapping_state, but MAX_CHARS bytes have already been
1588 allocated. Put the mapping symbol that far back. */
1591 mapping_state_2 (enum mstate state
, int max_chars
)
1593 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1595 if (!SEG_NORMAL (now_seg
))
1598 if (mapstate
== state
)
1599 /* The mapping symbol has already been emitted.
1600 There is nothing else to do. */
1603 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1604 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1607 #define mapping_state(x) /* nothing */
1608 #define mapping_state_2(x, y) /* nothing */
1611 /* Directives: sectioning and alignment. */
1614 s_bss (int ignore ATTRIBUTE_UNUSED
)
1616 /* We don't support putting frags in the BSS segment, we fake it by
1617 marking in_bss, then looking at s_skip for clues. */
1618 subseg_set (bss_section
, 0);
1619 demand_empty_rest_of_line ();
1620 mapping_state (MAP_DATA
);
1624 s_even (int ignore ATTRIBUTE_UNUSED
)
1626 /* Never make frag if expect extra pass. */
1628 frag_align (1, 0, 0);
1630 record_alignment (now_seg
, 1);
1632 demand_empty_rest_of_line ();
1635 /* Directives: Literal pools. */
1637 static literal_pool
*
1638 find_literal_pool (int size
)
1642 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1644 if (pool
->section
== now_seg
1645 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1652 static literal_pool
*
1653 find_or_make_literal_pool (int size
)
1655 /* Next literal pool ID number. */
1656 static unsigned int latest_pool_num
= 1;
1659 pool
= find_literal_pool (size
);
1663 /* Create a new pool. */
1664 pool
= XNEW (literal_pool
);
1668 /* Currently we always put the literal pool in the current text
1669 section. If we were generating "small" model code where we
1670 knew that all code and initialised data was within 1MB then
1671 we could output literals to mergeable, read-only data
1674 pool
->next_free_entry
= 0;
1675 pool
->section
= now_seg
;
1676 pool
->sub_section
= now_subseg
;
1678 pool
->next
= list_of_pools
;
1679 pool
->symbol
= NULL
;
1681 /* Add it to the list. */
1682 list_of_pools
= pool
;
1685 /* New pools, and emptied pools, will have a NULL symbol. */
1686 if (pool
->symbol
== NULL
)
1688 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1689 (valueT
) 0, &zero_address_frag
);
1690 pool
->id
= latest_pool_num
++;
1697 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1698 Return TRUE on success, otherwise return FALSE. */
1700 add_to_lit_pool (expressionS
*exp
, int size
)
1705 pool
= find_or_make_literal_pool (size
);
1707 /* Check if this literal value is already in the pool. */
1708 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1710 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1712 if ((litexp
->X_op
== exp
->X_op
)
1713 && (exp
->X_op
== O_constant
)
1714 && (litexp
->X_add_number
== exp
->X_add_number
)
1715 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1718 if ((litexp
->X_op
== exp
->X_op
)
1719 && (exp
->X_op
== O_symbol
)
1720 && (litexp
->X_add_number
== exp
->X_add_number
)
1721 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1722 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1726 /* Do we need to create a new entry? */
1727 if (entry
== pool
->next_free_entry
)
1729 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1731 set_syntax_error (_("literal pool overflow"));
1735 pool
->literals
[entry
].exp
= *exp
;
1736 pool
->next_free_entry
+= 1;
1737 if (exp
->X_op
== O_big
)
1739 /* PR 16688: Bignums are held in a single global array. We must
1740 copy and preserve that value now, before it is overwritten. */
1741 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1743 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1744 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1747 pool
->literals
[entry
].bignum
= NULL
;
1750 exp
->X_op
= O_symbol
;
1751 exp
->X_add_number
= ((int) entry
) * size
;
1752 exp
->X_add_symbol
= pool
->symbol
;
1757 /* Can't use symbol_new here, so have to create a symbol and then at
1758 a later date assign it a value. That's what these functions do. */
1761 symbol_locate (symbolS
* symbolP
,
1762 const char *name
,/* It is copied, the caller can modify. */
1763 segT segment
, /* Segment identifier (SEG_<something>). */
1764 valueT valu
, /* Symbol value. */
1765 fragS
* frag
) /* Associated fragment. */
1768 char *preserved_copy_of_name
;
1770 name_length
= strlen (name
) + 1; /* +1 for \0. */
1771 obstack_grow (¬es
, name
, name_length
);
1772 preserved_copy_of_name
= obstack_finish (¬es
);
1774 #ifdef tc_canonicalize_symbol_name
1775 preserved_copy_of_name
=
1776 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1779 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1781 S_SET_SEGMENT (symbolP
, segment
);
1782 S_SET_VALUE (symbolP
, valu
);
1783 symbol_clear_list_pointers (symbolP
);
1785 symbol_set_frag (symbolP
, frag
);
1787 /* Link to end of symbol chain. */
1789 extern int symbol_table_frozen
;
1791 if (symbol_table_frozen
)
1795 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1797 obj_symbol_new_hook (symbolP
);
1799 #ifdef tc_symbol_new_hook
1800 tc_symbol_new_hook (symbolP
);
1804 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1805 #endif /* DEBUG_SYMS */
1810 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1817 for (align
= 2; align
<= 4; align
++)
1819 int size
= 1 << align
;
1821 pool
= find_literal_pool (size
);
1822 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1825 /* Align pool as you have word accesses.
1826 Only make a frag if we have to. */
1828 frag_align (align
, 0, 0);
1830 mapping_state (MAP_DATA
);
1832 record_alignment (now_seg
, align
);
1834 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1836 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1837 (valueT
) frag_now_fix (), frag_now
);
1838 symbol_table_insert (pool
->symbol
);
1840 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1842 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1844 if (exp
->X_op
== O_big
)
1846 /* PR 16688: Restore the global bignum value. */
1847 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1848 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1849 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1852 /* First output the expression in the instruction to the pool. */
1853 emit_expr (exp
, size
); /* .word|.xword */
1855 if (exp
->X_op
== O_big
)
1857 free (pool
->literals
[entry
].bignum
);
1858 pool
->literals
[entry
].bignum
= NULL
;
1862 /* Mark the pool as empty. */
1863 pool
->next_free_entry
= 0;
1864 pool
->symbol
= NULL
;
1869 /* Forward declarations for functions below, in the MD interface
1871 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1872 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1874 /* Directives: Data. */
1875 /* N.B. the support for relocation suffix in this directive needs to be
1876 implemented properly. */
1879 s_aarch64_elf_cons (int nbytes
)
1883 #ifdef md_flush_pending_output
1884 md_flush_pending_output ();
1887 if (is_it_end_of_statement ())
1889 demand_empty_rest_of_line ();
1893 #ifdef md_cons_align
1894 md_cons_align (nbytes
);
1897 mapping_state (MAP_DATA
);
1900 struct reloc_table_entry
*reloc
;
1904 if (exp
.X_op
!= O_symbol
)
1905 emit_expr (&exp
, (unsigned int) nbytes
);
1908 skip_past_char (&input_line_pointer
, '#');
1909 if (skip_past_char (&input_line_pointer
, ':'))
1911 reloc
= find_reloc_table_entry (&input_line_pointer
);
1913 as_bad (_("unrecognized relocation suffix"));
1915 as_bad (_("unimplemented relocation suffix"));
1916 ignore_rest_of_line ();
1920 emit_expr (&exp
, (unsigned int) nbytes
);
1923 while (*input_line_pointer
++ == ',');
1925 /* Put terminator back into stream. */
1926 input_line_pointer
--;
1927 demand_empty_rest_of_line ();
1930 #endif /* OBJ_ELF */
1932 /* Output a 32-bit word, but mark as an instruction. */
1935 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1939 #ifdef md_flush_pending_output
1940 md_flush_pending_output ();
1943 if (is_it_end_of_statement ())
1945 demand_empty_rest_of_line ();
1949 /* Sections are assumed to start aligned. In executable section, there is no
1950 MAP_DATA symbol pending. So we only align the address during
1951 MAP_DATA --> MAP_INSN transition.
1952 For other sections, this is not guaranteed. */
1953 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1954 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1955 frag_align_code (2, 0);
1958 mapping_state (MAP_INSN
);
1964 if (exp
.X_op
!= O_constant
)
1966 as_bad (_("constant expression required"));
1967 ignore_rest_of_line ();
1971 if (target_big_endian
)
1973 unsigned int val
= exp
.X_add_number
;
1974 exp
.X_add_number
= SWAP_32 (val
);
1976 emit_expr (&exp
, 4);
1978 while (*input_line_pointer
++ == ',');
1980 /* Put terminator back into stream. */
1981 input_line_pointer
--;
1982 demand_empty_rest_of_line ();
1986 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1989 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1995 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1996 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1998 demand_empty_rest_of_line ();
2001 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2004 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2008 /* Since we're just labelling the code, there's no need to define a
2011 /* Make sure there is enough room in this frag for the following
2012 blr. This trick only works if the blr follows immediately after
2013 the .tlsdesc directive. */
2015 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2016 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2018 demand_empty_rest_of_line ();
2021 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2024 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2030 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2031 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2033 demand_empty_rest_of_line ();
2035 #endif /* OBJ_ELF */
2037 static void s_aarch64_arch (int);
2038 static void s_aarch64_cpu (int);
2039 static void s_aarch64_arch_extension (int);
2041 /* This table describes all the machine specific pseudo-ops the assembler
2042 has to support. The fields are:
2043 pseudo-op name without dot
2044 function to call to execute this pseudo-op
2045 Integer arg to pass to the function. */
2047 const pseudo_typeS md_pseudo_table
[] = {
2048 /* Never called because '.req' does not start a line. */
2050 {"unreq", s_unreq
, 0},
2052 {"even", s_even
, 0},
2053 {"ltorg", s_ltorg
, 0},
2054 {"pool", s_ltorg
, 0},
2055 {"cpu", s_aarch64_cpu
, 0},
2056 {"arch", s_aarch64_arch
, 0},
2057 {"arch_extension", s_aarch64_arch_extension
, 0},
2058 {"inst", s_aarch64_inst
, 0},
2060 {"tlsdescadd", s_tlsdescadd
, 0},
2061 {"tlsdesccall", s_tlsdesccall
, 0},
2062 {"tlsdescldr", s_tlsdescldr
, 0},
2063 {"word", s_aarch64_elf_cons
, 4},
2064 {"long", s_aarch64_elf_cons
, 4},
2065 {"xword", s_aarch64_elf_cons
, 8},
2066 {"dword", s_aarch64_elf_cons
, 8},
2072 /* Check whether STR points to a register name followed by a comma or the
2073 end of line; REG_TYPE indicates which register types are checked
2074 against. Return TRUE if STR is such a register name; otherwise return
2075 FALSE. The function does not intend to produce any diagnostics, but since
2076 the register parser aarch64_reg_parse, which is called by this function,
2077 does produce diagnostics, we call clear_error to clear any diagnostics
2078 that may be generated by aarch64_reg_parse.
2079 Also, the function returns FALSE directly if there is any user error
2080 present at the function entry. This prevents the existing diagnostics
2081 state from being spoiled.
2082 The function currently serves parse_constant_immediate and
2083 parse_big_immediate only. */
2085 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2089 /* Prevent the diagnostics state from being spoiled. */
2093 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2095 /* Clear the parsing error that may be set by the reg parser. */
2098 if (reg
== PARSE_FAIL
)
2101 skip_whitespace (str
);
2102 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2108 /* Parser functions used exclusively in instruction operands. */
2110 /* Parse an immediate expression which may not be constant.
2112 To prevent the expression parser from pushing a register name
2113 into the symbol table as an undefined symbol, firstly a check is
2114 done to find out whether STR is a register of type REG_TYPE followed
2115 by a comma or the end of line. Return FALSE if STR is such a string. */
2118 parse_immediate_expression (char **str
, expressionS
*exp
,
2119 aarch64_reg_type reg_type
)
2121 if (reg_name_p (*str
, reg_type
))
2123 set_recoverable_error (_("immediate operand required"));
2127 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2129 if (exp
->X_op
== O_absent
)
2131 set_fatal_syntax_error (_("missing immediate expression"));
2138 /* Constant immediate-value read function for use in insn parsing.
2139 STR points to the beginning of the immediate (with the optional
2140 leading #); *VAL receives the value. REG_TYPE says which register
2141 names should be treated as registers rather than as symbolic immediates.
2143 Return TRUE on success; otherwise return FALSE. */
2146 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2150 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2153 if (exp
.X_op
!= O_constant
)
2155 set_syntax_error (_("constant expression required"));
2159 *val
= exp
.X_add_number
;
2164 encode_imm_float_bits (uint32_t imm
)
2166 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2167 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2170 /* Return TRUE if the single-precision floating-point value encoded in IMM
2171 can be expressed in the AArch64 8-bit signed floating-point format with
2172 3-bit exponent and normalized 4 bits of precision; in other words, the
2173 floating-point value must be expressable as
2174 (+/-) n / 16 * power (2, r)
2175 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2178 aarch64_imm_float_p (uint32_t imm
)
2180 /* If a single-precision floating-point value has the following bit
2181 pattern, it can be expressed in the AArch64 8-bit floating-point
2184 3 32222222 2221111111111
2185 1 09876543 21098765432109876543210
2186 n Eeeeeexx xxxx0000000000000000000
2188 where n, e and each x are either 0 or 1 independently, with
2193 /* Prepare the pattern for 'Eeeeee'. */
2194 if (((imm
>> 30) & 0x1) == 0)
2195 pattern
= 0x3e000000;
2197 pattern
= 0x40000000;
2199 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2200 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2203 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2204 as an IEEE float without any loss of precision. Store the value in
2208 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2210 /* If a double-precision floating-point value has the following bit
2211 pattern, it can be expressed in a float:
2213 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2214 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2215 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2217 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2218 if Eeee_eeee != 1111_1111
2220 where n, e, s and S are either 0 or 1 independently and where ~ is the
2224 uint32_t high32
= imm
>> 32;
2225 uint32_t low32
= imm
;
2227 /* Lower 29 bits need to be 0s. */
2228 if ((imm
& 0x1fffffff) != 0)
2231 /* Prepare the pattern for 'Eeeeeeeee'. */
2232 if (((high32
>> 30) & 0x1) == 0)
2233 pattern
= 0x38000000;
2235 pattern
= 0x40000000;
2238 if ((high32
& 0x78000000) != pattern
)
2241 /* Check Eeee_eeee != 1111_1111. */
2242 if ((high32
& 0x7ff00000) == 0x47f00000)
2245 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2246 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2247 | (low32
>> 29)); /* 3 S bits. */
2251 /* Return true if we should treat OPERAND as a double-precision
2252 floating-point operand rather than a single-precision one. */
2254 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2256 /* Check for unsuffixed SVE registers, which are allowed
2257 for LDR and STR but not in instructions that require an
2258 immediate. We get better error messages if we arbitrarily
2259 pick one size, parse the immediate normally, and then
2260 report the match failure in the normal way. */
2261 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2262 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2265 /* Parse a floating-point immediate. Return TRUE on success and return the
2266 value in *IMMED in the format of IEEE754 single-precision encoding.
2267 *CCP points to the start of the string; DP_P is TRUE when the immediate
2268 is expected to be in double-precision (N.B. this only matters when
2269 hexadecimal representation is involved). REG_TYPE says which register
2270 names should be treated as registers rather than as symbolic immediates.
2272 This routine accepts any IEEE float; it is up to the callers to reject
2276 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2277 aarch64_reg_type reg_type
)
2281 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2282 int found_fpchar
= 0;
2284 unsigned fpword
= 0;
2285 bfd_boolean hex_p
= FALSE
;
2287 skip_past_char (&str
, '#');
2290 skip_whitespace (fpnum
);
2292 if (strncmp (fpnum
, "0x", 2) == 0)
2294 /* Support the hexadecimal representation of the IEEE754 encoding.
2295 Double-precision is expected when DP_P is TRUE, otherwise the
2296 representation should be in single-precision. */
2297 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2302 if (!can_convert_double_to_float (val
, &fpword
))
2305 else if ((uint64_t) val
> 0xffffffff)
2314 if (reg_name_p (str
, reg_type
))
2316 set_recoverable_error (_("immediate operand required"));
2320 /* We must not accidentally parse an integer as a floating-point number.
2321 Make sure that the value we parse is not an integer by checking for
2322 special characters '.' or 'e'. */
2323 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2324 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2338 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2341 /* Our FP word must be 32 bits (single-precision FP). */
2342 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2344 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2354 set_fatal_syntax_error (_("invalid floating-point constant"));
2358 /* Less-generic immediate-value read function with the possibility of loading
2359 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2362 To prevent the expression parser from pushing a register name into the
2363 symbol table as an undefined symbol, a check is firstly done to find
2364 out whether STR is a register of type REG_TYPE followed by a comma or
2365 the end of line. Return FALSE if STR is such a register. */
2368 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2372 if (reg_name_p (ptr
, reg_type
))
2374 set_syntax_error (_("immediate operand required"));
2378 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2380 if (inst
.reloc
.exp
.X_op
== O_constant
)
2381 *imm
= inst
.reloc
.exp
.X_add_number
;
2388 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2389 if NEED_LIBOPCODES is non-zero, the fixup will need
2390 assistance from the libopcodes. */
2393 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2394 const aarch64_opnd_info
*operand
,
2395 int need_libopcodes_p
)
2397 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2398 reloc
->opnd
= operand
->type
;
2399 if (need_libopcodes_p
)
2400 reloc
->need_libopcodes_p
= 1;
2403 /* Return TRUE if the instruction needs to be fixed up later internally by
2404 the GAS; otherwise return FALSE. */
2406 static inline bfd_boolean
2407 aarch64_gas_internal_fixup_p (void)
2409 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2412 /* Assign the immediate value to the relevant field in *OPERAND if
2413 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2414 needs an internal fixup in a later stage.
2415 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2416 IMM.VALUE that may get assigned with the constant. */
2418 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2419 aarch64_opnd_info
*operand
,
2421 int need_libopcodes_p
,
2424 if (reloc
->exp
.X_op
== O_constant
)
2427 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2429 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2430 reloc
->type
= BFD_RELOC_UNUSED
;
2434 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2435 /* Tell libopcodes to ignore this operand or not. This is helpful
2436 when one of the operands needs to be fixed up later but we need
2437 libopcodes to check the other operands. */
2438 operand
->skip
= skip_p
;
2442 /* Relocation modifiers. Each entry in the table contains the textual
2443 name for the relocation which may be placed before a symbol used as
2444 a load/store offset, or add immediate. It must be surrounded by a
2445 leading and trailing colon, for example:
2447 ldr x0, [x1, #:rello:varsym]
2448 add x0, x1, #:rello:varsym */
2450 struct reloc_table_entry
2454 bfd_reloc_code_real_type adr_type
;
2455 bfd_reloc_code_real_type adrp_type
;
2456 bfd_reloc_code_real_type movw_type
;
2457 bfd_reloc_code_real_type add_type
;
2458 bfd_reloc_code_real_type ldst_type
;
2459 bfd_reloc_code_real_type ld_literal_type
;
2462 static struct reloc_table_entry reloc_table
[] = {
2463 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2468 BFD_RELOC_AARCH64_ADD_LO12
,
2469 BFD_RELOC_AARCH64_LDST_LO12
,
2472 /* Higher 21 bits of pc-relative page offset: ADRP */
2475 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2481 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2484 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2490 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2494 BFD_RELOC_AARCH64_MOVW_G0
,
2499 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2503 BFD_RELOC_AARCH64_MOVW_G0_S
,
2508 /* Less significant bits 0-15 of address/value: MOVK, no check */
2512 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2517 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2521 BFD_RELOC_AARCH64_MOVW_G1
,
2526 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2530 BFD_RELOC_AARCH64_MOVW_G1_S
,
2535 /* Less significant bits 16-31 of address/value: MOVK, no check */
2539 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2544 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2548 BFD_RELOC_AARCH64_MOVW_G2
,
2553 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2557 BFD_RELOC_AARCH64_MOVW_G2_S
,
2562 /* Less significant bits 32-47 of address/value: MOVK, no check */
2566 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2571 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2575 BFD_RELOC_AARCH64_MOVW_G3
,
2580 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2584 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2589 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2593 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2598 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2602 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2607 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2611 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2616 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2620 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2625 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2629 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2634 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2638 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2643 /* Get to the page containing GOT entry for a symbol. */
2646 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2650 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2652 /* 12 bit offset into the page containing GOT entry for that symbol. */
2658 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2661 /* 0-15 bits of address/value: MOVk, no check. */
2665 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2670 /* Most significant bits 16-31 of address/value: MOVZ. */
2674 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2679 /* 15 bit offset into the page containing GOT entry for that symbol. */
2685 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2688 /* Get to the page containing GOT TLS entry for a symbol */
2689 {"gottprel_g0_nc", 0,
2692 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2697 /* Get to the page containing GOT TLS entry for a symbol */
2701 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2706 /* Get to the page containing GOT TLS entry for a symbol */
2708 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2709 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2715 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2720 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2724 /* Lower 16 bits address/value: MOVk. */
2728 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2733 /* Most significant bits 16-31 of address/value: MOVZ. */
2737 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2742 /* Get to the page containing GOT TLS entry for a symbol */
2744 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2745 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2749 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2751 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2756 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2757 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2760 /* Get to the page containing GOT TLS entry for a symbol.
2761 The same as GD, we allocate two consecutive GOT slots
2762 for module index and module offset, the only difference
2763 with GD is the module offset should be initialized to
2764 zero without any outstanding runtime relocation. */
2766 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2767 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2773 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2774 {"tlsldm_lo12_nc", 0,
2778 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2782 /* 12 bit offset into the module TLS base address. */
2787 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2788 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2791 /* Same as dtprel_lo12, no overflow check. */
2792 {"dtprel_lo12_nc", 0,
2796 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2797 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2800 /* bits[23:12] of offset to the module TLS base address. */
2805 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2809 /* bits[15:0] of offset to the module TLS base address. */
2813 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2818 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2822 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2827 /* bits[31:16] of offset to the module TLS base address. */
2831 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2836 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2840 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2845 /* bits[47:32] of offset to the module TLS base address. */
2849 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2854 /* Lower 16 bit offset into GOT entry for a symbol */
2855 {"tlsdesc_off_g0_nc", 0,
2858 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2863 /* Higher 16 bit offset into GOT entry for a symbol */
2864 {"tlsdesc_off_g1", 0,
2867 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2872 /* Get to the page containing GOT TLS entry for a symbol */
2875 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2879 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2881 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2882 {"gottprel_lo12", 0,
2887 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2890 /* Get tp offset for a symbol. */
2895 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2899 /* Get tp offset for a symbol. */
2904 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2908 /* Get tp offset for a symbol. */
2913 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2917 /* Get tp offset for a symbol. */
2918 {"tprel_lo12_nc", 0,
2922 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2926 /* Most significant bits 32-47 of address/value: MOVZ. */
2930 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2935 /* Most significant bits 16-31 of address/value: MOVZ. */
2939 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2944 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2948 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2953 /* Most significant bits 0-15 of address/value: MOVZ. */
2957 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2962 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2966 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2971 /* 15bit offset from got entry to base address of GOT table. */
2977 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2980 /* 14bit offset from got entry to base address of GOT table. */
2986 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2990 /* Given the address of a pointer pointing to the textual name of a
2991 relocation as may appear in assembler source, attempt to find its
2992 details in reloc_table. The pointer will be updated to the character
2993 after the trailing colon. On failure, NULL will be returned;
2994 otherwise return the reloc_table_entry. */
2996 static struct reloc_table_entry
*
2997 find_reloc_table_entry (char **str
)
3000 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3002 int length
= strlen (reloc_table
[i
].name
);
3004 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3005 && (*str
)[length
] == ':')
3007 *str
+= (length
+ 1);
3008 return &reloc_table
[i
];
3015 /* Mode argument to parse_shift and parser_shifter_operand. */
3016 enum parse_shift_mode
3018 SHIFTED_NONE
, /* no shifter allowed */
3019 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3021 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3023 SHIFTED_LSL
, /* bare "lsl #n" */
3024 SHIFTED_MUL
, /* bare "mul #n" */
3025 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3026 SHIFTED_MUL_VL
, /* "mul vl" */
3027 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3030 /* Parse a <shift> operator on an AArch64 data processing instruction.
3031 Return TRUE on success; otherwise return FALSE. */
3033 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3035 const struct aarch64_name_value_pair
*shift_op
;
3036 enum aarch64_modifier_kind kind
;
3042 for (p
= *str
; ISALPHA (*p
); p
++)
3047 set_syntax_error (_("shift expression expected"));
3051 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3053 if (shift_op
== NULL
)
3055 set_syntax_error (_("shift operator expected"));
3059 kind
= aarch64_get_operand_modifier (shift_op
);
3061 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3063 set_syntax_error (_("invalid use of 'MSL'"));
3067 if (kind
== AARCH64_MOD_MUL
3068 && mode
!= SHIFTED_MUL
3069 && mode
!= SHIFTED_MUL_VL
)
3071 set_syntax_error (_("invalid use of 'MUL'"));
3077 case SHIFTED_LOGIC_IMM
:
3078 if (aarch64_extend_operator_p (kind
))
3080 set_syntax_error (_("extending shift is not permitted"));
3085 case SHIFTED_ARITH_IMM
:
3086 if (kind
== AARCH64_MOD_ROR
)
3088 set_syntax_error (_("'ROR' shift is not permitted"));
3094 if (kind
!= AARCH64_MOD_LSL
)
3096 set_syntax_error (_("only 'LSL' shift is permitted"));
3102 if (kind
!= AARCH64_MOD_MUL
)
3104 set_syntax_error (_("only 'MUL' is permitted"));
3109 case SHIFTED_MUL_VL
:
3110 /* "MUL VL" consists of two separate tokens. Require the first
3111 token to be "MUL" and look for a following "VL". */
3112 if (kind
== AARCH64_MOD_MUL
)
3114 skip_whitespace (p
);
3115 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3118 kind
= AARCH64_MOD_MUL_VL
;
3122 set_syntax_error (_("only 'MUL VL' is permitted"));
3125 case SHIFTED_REG_OFFSET
:
3126 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3127 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3129 set_fatal_syntax_error
3130 (_("invalid shift for the register offset addressing mode"));
3135 case SHIFTED_LSL_MSL
:
3136 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3138 set_syntax_error (_("invalid shift operator"));
3147 /* Whitespace can appear here if the next thing is a bare digit. */
3148 skip_whitespace (p
);
3150 /* Parse shift amount. */
3152 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3153 exp
.X_op
= O_absent
;
3156 if (is_immediate_prefix (*p
))
3161 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3163 if (kind
== AARCH64_MOD_MUL_VL
)
3164 /* For consistency, give MUL VL the same shift amount as an implicit
3166 operand
->shifter
.amount
= 1;
3167 else if (exp
.X_op
== O_absent
)
3169 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3171 set_syntax_error (_("missing shift amount"));
3174 operand
->shifter
.amount
= 0;
3176 else if (exp
.X_op
!= O_constant
)
3178 set_syntax_error (_("constant shift amount required"));
3181 /* For parsing purposes, MUL #n has no inherent range. The range
3182 depends on the operand and will be checked by operand-specific
3184 else if (kind
!= AARCH64_MOD_MUL
3185 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3187 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3192 operand
->shifter
.amount
= exp
.X_add_number
;
3193 operand
->shifter
.amount_present
= 1;
3196 operand
->shifter
.operator_present
= 1;
3197 operand
->shifter
.kind
= kind
;
3203 /* Parse a <shifter_operand> for a data processing instruction:
3206 #<immediate>, LSL #imm
3208 Validation of immediate operands is deferred to md_apply_fix.
3210 Return TRUE on success; otherwise return FALSE. */
3213 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3214 enum parse_shift_mode mode
)
3218 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3223 /* Accept an immediate expression. */
3224 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3227 /* Accept optional LSL for arithmetic immediate values. */
3228 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3229 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3232 /* Not accept any shifter for logical immediate values. */
3233 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3234 && parse_shift (&p
, operand
, mode
))
3236 set_syntax_error (_("unexpected shift operator"));
3244 /* Parse a <shifter_operand> for a data processing instruction:
3249 #<immediate>, LSL #imm
3251 where <shift> is handled by parse_shift above, and the last two
3252 cases are handled by the function above.
3254 Validation of immediate operands is deferred to md_apply_fix.
3256 Return TRUE on success; otherwise return FALSE. */
3259 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3260 enum parse_shift_mode mode
)
3262 const reg_entry
*reg
;
3263 aarch64_opnd_qualifier_t qualifier
;
3264 enum aarch64_operand_class opd_class
3265 = aarch64_get_operand_class (operand
->type
);
3267 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3270 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3272 set_syntax_error (_("unexpected register in the immediate operand"));
3276 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3278 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3282 operand
->reg
.regno
= reg
->number
;
3283 operand
->qualifier
= qualifier
;
3285 /* Accept optional shift operation on register. */
3286 if (! skip_past_comma (str
))
3289 if (! parse_shift (str
, operand
, mode
))
3294 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3297 (_("integer register expected in the extended/shifted operand "
3302 /* We have a shifted immediate variable. */
3303 return parse_shifter_operand_imm (str
, operand
, mode
);
3306 /* Return TRUE on success; return FALSE otherwise. */
3309 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3310 enum parse_shift_mode mode
)
3314 /* Determine if we have the sequence of characters #: or just :
3315 coming next. If we do, then we check for a :rello: relocation
3316 modifier. If we don't, punt the whole lot to
3317 parse_shifter_operand. */
3319 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3321 struct reloc_table_entry
*entry
;
3329 /* Try to parse a relocation. Anything else is an error. */
3330 if (!(entry
= find_reloc_table_entry (str
)))
3332 set_syntax_error (_("unknown relocation modifier"));
3336 if (entry
->add_type
== 0)
3339 (_("this relocation modifier is not allowed on this instruction"));
3343 /* Save str before we decompose it. */
3346 /* Next, we parse the expression. */
3347 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3350 /* Record the relocation type (use the ADD variant here). */
3351 inst
.reloc
.type
= entry
->add_type
;
3352 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3354 /* If str is empty, we've reached the end, stop here. */
3358 /* Otherwise, we have a shifted reloc modifier, so rewind to
3359 recover the variable name and continue parsing for the shifter. */
3361 return parse_shifter_operand_imm (str
, operand
, mode
);
3364 return parse_shifter_operand (str
, operand
, mode
);
3367 /* Parse all forms of an address expression. Information is written
3368 to *OPERAND and/or inst.reloc.
3370 The A64 instruction set has the following addressing modes:
3373 [base] // in SIMD ld/st structure
3374 [base{,#0}] // in ld/st exclusive
3376 [base,Xm{,LSL #imm}]
3377 [base,Xm,SXTX {#imm}]
3378 [base,Wm,(S|U)XTW {#imm}]
3383 [base],Xm // in SIMD ld/st structure
3384 PC-relative (literal)
3388 [base,Zm.D{,LSL #imm}]
3389 [base,Zm.S,(S|U)XTW {#imm}]
3390 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3393 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3394 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3395 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3397 (As a convenience, the notation "=immediate" is permitted in conjunction
3398 with the pc-relative literal load instructions to automatically place an
3399 immediate value or symbolic address in a nearby literal pool and generate
3400 a hidden label which references it.)
3402 Upon a successful parsing, the address structure in *OPERAND will be
3403 filled in the following way:
3405 .base_regno = <base>
3406 .offset.is_reg // 1 if the offset is a register
3408 .offset.regno = <Rm>
3410 For different addressing modes defined in the A64 ISA:
3413 .pcrel=0; .preind=1; .postind=0; .writeback=0
3415 .pcrel=0; .preind=1; .postind=0; .writeback=1
3417 .pcrel=0; .preind=0; .postind=1; .writeback=1
3418 PC-relative (literal)
3419 .pcrel=1; .preind=1; .postind=0; .writeback=0
3421 The shift/extension information, if any, will be stored in .shifter.
3422 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3423 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3424 corresponding register.
3426 BASE_TYPE says which types of base register should be accepted and
3427 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3428 is the type of shifter that is allowed for immediate offsets,
3429 or SHIFTED_NONE if none.
3431 In all other respects, it is the caller's responsibility to check
3432 for addressing modes not supported by the instruction, and to set
3436 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3437 aarch64_opnd_qualifier_t
*base_qualifier
,
3438 aarch64_opnd_qualifier_t
*offset_qualifier
,
3439 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3440 enum parse_shift_mode imm_shift_mode
)
3443 const reg_entry
*reg
;
3444 expressionS
*exp
= &inst
.reloc
.exp
;
3446 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3447 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3448 if (! skip_past_char (&p
, '['))
3450 /* =immediate or label. */
3451 operand
->addr
.pcrel
= 1;
3452 operand
->addr
.preind
= 1;
3454 /* #:<reloc_op>:<symbol> */
3455 skip_past_char (&p
, '#');
3456 if (skip_past_char (&p
, ':'))
3458 bfd_reloc_code_real_type ty
;
3459 struct reloc_table_entry
*entry
;
3461 /* Try to parse a relocation modifier. Anything else is
3463 entry
= find_reloc_table_entry (&p
);
3466 set_syntax_error (_("unknown relocation modifier"));
3470 switch (operand
->type
)
3472 case AARCH64_OPND_ADDR_PCREL21
:
3474 ty
= entry
->adr_type
;
3478 ty
= entry
->ld_literal_type
;
3485 (_("this relocation modifier is not allowed on this "
3491 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3493 set_syntax_error (_("invalid relocation expression"));
3497 /* #:<reloc_op>:<expr> */
3498 /* Record the relocation type. */
3499 inst
.reloc
.type
= ty
;
3500 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3505 if (skip_past_char (&p
, '='))
3506 /* =immediate; need to generate the literal in the literal pool. */
3507 inst
.gen_lit_pool
= 1;
3509 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3511 set_syntax_error (_("invalid address"));
3522 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3523 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3525 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3528 operand
->addr
.base_regno
= reg
->number
;
3531 if (skip_past_comma (&p
))
3534 operand
->addr
.preind
= 1;
3536 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3539 if (!aarch64_check_reg_type (reg
, offset_type
))
3541 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3546 operand
->addr
.offset
.regno
= reg
->number
;
3547 operand
->addr
.offset
.is_reg
= 1;
3548 /* Shifted index. */
3549 if (skip_past_comma (&p
))
3552 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3553 /* Use the diagnostics set in parse_shift, so not set new
3554 error message here. */
3558 [base,Xm{,LSL #imm}]
3559 [base,Xm,SXTX {#imm}]
3560 [base,Wm,(S|U)XTW {#imm}] */
3561 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3562 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3563 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3565 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3567 set_syntax_error (_("invalid use of 32-bit register offset"));
3570 if (aarch64_get_qualifier_esize (*base_qualifier
)
3571 != aarch64_get_qualifier_esize (*offset_qualifier
))
3573 set_syntax_error (_("offset has different size from base"));
3577 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3579 set_syntax_error (_("invalid use of 64-bit register offset"));
3585 /* [Xn,#:<reloc_op>:<symbol> */
3586 skip_past_char (&p
, '#');
3587 if (skip_past_char (&p
, ':'))
3589 struct reloc_table_entry
*entry
;
3591 /* Try to parse a relocation modifier. Anything else is
3593 if (!(entry
= find_reloc_table_entry (&p
)))
3595 set_syntax_error (_("unknown relocation modifier"));
3599 if (entry
->ldst_type
== 0)
3602 (_("this relocation modifier is not allowed on this "
3607 /* [Xn,#:<reloc_op>: */
3608 /* We now have the group relocation table entry corresponding to
3609 the name in the assembler source. Next, we parse the
3611 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3613 set_syntax_error (_("invalid relocation expression"));
3617 /* [Xn,#:<reloc_op>:<expr> */
3618 /* Record the load/store relocation type. */
3619 inst
.reloc
.type
= entry
->ldst_type
;
3620 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3624 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3626 set_syntax_error (_("invalid expression in the address"));
3630 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3631 /* [Xn,<expr>,<shifter> */
3632 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3638 if (! skip_past_char (&p
, ']'))
3640 set_syntax_error (_("']' expected"));
3644 if (skip_past_char (&p
, '!'))
3646 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3648 set_syntax_error (_("register offset not allowed in pre-indexed "
3649 "addressing mode"));
3653 operand
->addr
.writeback
= 1;
3655 else if (skip_past_comma (&p
))
3658 operand
->addr
.postind
= 1;
3659 operand
->addr
.writeback
= 1;
3661 if (operand
->addr
.preind
)
3663 set_syntax_error (_("cannot combine pre- and post-indexing"));
3667 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3671 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3673 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3677 operand
->addr
.offset
.regno
= reg
->number
;
3678 operand
->addr
.offset
.is_reg
= 1;
3680 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3683 set_syntax_error (_("invalid expression in the address"));
3688 /* If at this point neither .preind nor .postind is set, we have a
3689 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3690 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3692 if (operand
->addr
.writeback
)
3695 set_syntax_error (_("missing offset in the pre-indexed address"));
3698 operand
->addr
.preind
= 1;
3699 inst
.reloc
.exp
.X_op
= O_constant
;
3700 inst
.reloc
.exp
.X_add_number
= 0;
3707 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3710 parse_address (char **str
, aarch64_opnd_info
*operand
)
3712 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3713 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3714 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3717 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3718 The arguments have the same meaning as for parse_address_main.
3719 Return TRUE on success. */
3721 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3722 aarch64_opnd_qualifier_t
*base_qualifier
,
3723 aarch64_opnd_qualifier_t
*offset_qualifier
)
3725 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3726 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3730 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3731 Return TRUE on success; otherwise return FALSE. */
3733 parse_half (char **str
, int *internal_fixup_p
)
3737 skip_past_char (&p
, '#');
3739 gas_assert (internal_fixup_p
);
3740 *internal_fixup_p
= 0;
3744 struct reloc_table_entry
*entry
;
3746 /* Try to parse a relocation. Anything else is an error. */
3748 if (!(entry
= find_reloc_table_entry (&p
)))
3750 set_syntax_error (_("unknown relocation modifier"));
3754 if (entry
->movw_type
== 0)
3757 (_("this relocation modifier is not allowed on this instruction"));
3761 inst
.reloc
.type
= entry
->movw_type
;
3764 *internal_fixup_p
= 1;
3766 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3773 /* Parse an operand for an ADRP instruction:
3775 Return TRUE on success; otherwise return FALSE. */
3778 parse_adrp (char **str
)
3785 struct reloc_table_entry
*entry
;
3787 /* Try to parse a relocation. Anything else is an error. */
3789 if (!(entry
= find_reloc_table_entry (&p
)))
3791 set_syntax_error (_("unknown relocation modifier"));
3795 if (entry
->adrp_type
== 0)
3798 (_("this relocation modifier is not allowed on this instruction"));
3802 inst
.reloc
.type
= entry
->adrp_type
;
3805 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3807 inst
.reloc
.pc_rel
= 1;
3809 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3816 /* Miscellaneous. */
3818 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3819 of SIZE tokens in which index I gives the token for field value I,
3820 or is null if field value I is invalid. REG_TYPE says which register
3821 names should be treated as registers rather than as symbolic immediates.
3823 Return true on success, moving *STR past the operand and storing the
3824 field value in *VAL. */
3827 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3828 size_t size
, aarch64_reg_type reg_type
)
3834 /* Match C-like tokens. */
3836 while (ISALNUM (*q
))
3839 for (i
= 0; i
< size
; ++i
)
3841 && strncasecmp (array
[i
], p
, q
- p
) == 0
3842 && array
[i
][q
- p
] == 0)
3849 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3852 if (exp
.X_op
== O_constant
3853 && (uint64_t) exp
.X_add_number
< size
)
3855 *val
= exp
.X_add_number
;
3860 /* Use the default error for this operand. */
3864 /* Parse an option for a preload instruction. Returns the encoding for the
3865 option, or PARSE_FAIL. */
3868 parse_pldop (char **str
)
3871 const struct aarch64_name_value_pair
*o
;
3874 while (ISALNUM (*q
))
3877 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3885 /* Parse an option for a barrier instruction. Returns the encoding for the
3886 option, or PARSE_FAIL. */
3889 parse_barrier (char **str
)
3892 const asm_barrier_opt
*o
;
3895 while (ISALPHA (*q
))
3898 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3906 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3907 return 0 if successful. Otherwise return PARSE_FAIL. */
3910 parse_barrier_psb (char **str
,
3911 const struct aarch64_name_value_pair
** hint_opt
)
3914 const struct aarch64_name_value_pair
*o
;
3917 while (ISALPHA (*q
))
3920 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3923 set_fatal_syntax_error
3924 ( _("unknown or missing option to PSB"));
3928 if (o
->value
!= 0x11)
3930 /* PSB only accepts option name 'CSYNC'. */
3932 (_("the specified option is not accepted for PSB"));
3941 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3942 Returns the encoding for the option, or PARSE_FAIL.
3944 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3945 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3947 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3948 field, otherwise as a system register.
3952 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3953 int imple_defined_p
, int pstatefield_p
)
3957 const aarch64_sys_reg
*o
;
3961 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3963 *p
++ = TOLOWER (*q
);
3965 /* Assert that BUF be large enough. */
3966 gas_assert (p
- buf
== q
- *str
);
3968 o
= hash_find (sys_regs
, buf
);
3971 if (!imple_defined_p
)
3975 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3976 unsigned int op0
, op1
, cn
, cm
, op2
;
3978 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3981 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3983 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3988 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3989 as_bad (_("selected processor does not support PSTATE field "
3991 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3992 as_bad (_("selected processor does not support system register "
3994 if (aarch64_sys_reg_deprecated_p (o
))
3995 as_warn (_("system register name '%s' is deprecated and may be "
3996 "removed in a future release"), buf
);
4004 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4005 for the option, or NULL. */
4007 static const aarch64_sys_ins_reg
*
4008 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4012 const aarch64_sys_ins_reg
*o
;
4015 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4017 *p
++ = TOLOWER (*q
);
4020 o
= hash_find (sys_ins_regs
, buf
);
4024 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4025 as_bad (_("selected processor does not support system register "
4032 #define po_char_or_fail(chr) do { \
4033 if (! skip_past_char (&str, chr)) \
4037 #define po_reg_or_fail(regtype) do { \
4038 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4039 if (val == PARSE_FAIL) \
4041 set_default_error (); \
4046 #define po_int_reg_or_fail(reg_type) do { \
4047 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4048 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4050 set_default_error (); \
4053 info->reg.regno = reg->number; \
4054 info->qualifier = qualifier; \
4057 #define po_imm_nc_or_fail() do { \
4058 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4062 #define po_imm_or_fail(min, max) do { \
4063 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4065 if (val < min || val > max) \
4067 set_fatal_syntax_error (_("immediate value out of range "\
4068 #min " to "#max)); \
4073 #define po_enum_or_fail(array) do { \
4074 if (!parse_enum_string (&str, &val, array, \
4075 ARRAY_SIZE (array), imm_reg_type)) \
4079 #define po_misc_or_fail(expr) do { \
4084 /* encode the 12-bit imm field of Add/sub immediate */
4085 static inline uint32_t
4086 encode_addsub_imm (uint32_t imm
)
4091 /* encode the shift amount field of Add/sub immediate */
4092 static inline uint32_t
4093 encode_addsub_imm_shift_amount (uint32_t cnt
)
4099 /* encode the imm field of Adr instruction */
4100 static inline uint32_t
4101 encode_adr_imm (uint32_t imm
)
4103 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4104 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4107 /* encode the immediate field of Move wide immediate */
4108 static inline uint32_t
4109 encode_movw_imm (uint32_t imm
)
4114 /* encode the 26-bit offset of unconditional branch */
4115 static inline uint32_t
4116 encode_branch_ofs_26 (uint32_t ofs
)
4118 return ofs
& ((1 << 26) - 1);
4121 /* encode the 19-bit offset of conditional branch and compare & branch */
4122 static inline uint32_t
4123 encode_cond_branch_ofs_19 (uint32_t ofs
)
4125 return (ofs
& ((1 << 19) - 1)) << 5;
4128 /* encode the 19-bit offset of ld literal */
4129 static inline uint32_t
4130 encode_ld_lit_ofs_19 (uint32_t ofs
)
4132 return (ofs
& ((1 << 19) - 1)) << 5;
4135 /* Encode the 14-bit offset of test & branch. */
4136 static inline uint32_t
4137 encode_tst_branch_ofs_14 (uint32_t ofs
)
4139 return (ofs
& ((1 << 14) - 1)) << 5;
4142 /* Encode the 16-bit imm field of svc/hvc/smc. */
4143 static inline uint32_t
4144 encode_svc_imm (uint32_t imm
)
4149 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4150 static inline uint32_t
4151 reencode_addsub_switch_add_sub (uint32_t opcode
)
4153 return opcode
^ (1 << 30);
4156 static inline uint32_t
4157 reencode_movzn_to_movz (uint32_t opcode
)
4159 return opcode
| (1 << 30);
4162 static inline uint32_t
4163 reencode_movzn_to_movn (uint32_t opcode
)
4165 return opcode
& ~(1 << 30);
4168 /* Overall per-instruction processing. */
4170 /* We need to be able to fix up arbitrary expressions in some statements.
4171 This is so that we can handle symbols that are an arbitrary distance from
4172 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4173 which returns part of an address in a form which will be valid for
4174 a data instruction. We do this by pushing the expression into a symbol
4175 in the expr_section, and creating a fix for that. */
4178 fix_new_aarch64 (fragS
* frag
,
4180 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4190 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4194 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4201 /* Diagnostics on operands errors. */
4203 /* By default, output verbose error message.
4204 Disable the verbose error message by -mno-verbose-error. */
4205 static int verbose_error_p
= 1;
4207 #ifdef DEBUG_AARCH64
4208 /* N.B. this is only for the purpose of debugging. */
4209 const char* operand_mismatch_kind_names
[] =
4212 "AARCH64_OPDE_RECOVERABLE",
4213 "AARCH64_OPDE_SYNTAX_ERROR",
4214 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4215 "AARCH64_OPDE_INVALID_VARIANT",
4216 "AARCH64_OPDE_OUT_OF_RANGE",
4217 "AARCH64_OPDE_UNALIGNED",
4218 "AARCH64_OPDE_REG_LIST",
4219 "AARCH64_OPDE_OTHER_ERROR",
4221 #endif /* DEBUG_AARCH64 */
4223 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4225 When multiple errors of different kinds are found in the same assembly
4226 line, only the error of the highest severity will be picked up for
4227 issuing the diagnostics. */
4229 static inline bfd_boolean
4230 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4231 enum aarch64_operand_error_kind rhs
)
4233 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4234 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4235 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4236 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4237 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4238 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4239 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4240 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4244 /* Helper routine to get the mnemonic name from the assembly instruction
4245 line; should only be called for the diagnosis purpose, as there is
4246 string copy operation involved, which may affect the runtime
4247 performance if used in elsewhere. */
4250 get_mnemonic_name (const char *str
)
4252 static char mnemonic
[32];
4255 /* Get the first 15 bytes and assume that the full name is included. */
4256 strncpy (mnemonic
, str
, 31);
4257 mnemonic
[31] = '\0';
4259 /* Scan up to the end of the mnemonic, which must end in white space,
4260 '.', or end of string. */
4261 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4266 /* Append '...' to the truncated long name. */
4267 if (ptr
- mnemonic
== 31)
4268 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4274 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4276 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4277 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4280 /* Data structures storing one user error in the assembly code related to
4283 struct operand_error_record
4285 const aarch64_opcode
*opcode
;
4286 aarch64_operand_error detail
;
4287 struct operand_error_record
*next
;
4290 typedef struct operand_error_record operand_error_record
;
4292 struct operand_errors
4294 operand_error_record
*head
;
4295 operand_error_record
*tail
;
4298 typedef struct operand_errors operand_errors
;
4300 /* Top-level data structure reporting user errors for the current line of
4302 The way md_assemble works is that all opcodes sharing the same mnemonic
4303 name are iterated to find a match to the assembly line. In this data
4304 structure, each of the such opcodes will have one operand_error_record
4305 allocated and inserted. In other words, excessive errors related with
4306 a single opcode are disregarded. */
4307 operand_errors operand_error_report
;
4309 /* Free record nodes. */
4310 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4312 /* Initialize the data structure that stores the operand mismatch
4313 information on assembling one line of the assembly code. */
4315 init_operand_error_report (void)
4317 if (operand_error_report
.head
!= NULL
)
4319 gas_assert (operand_error_report
.tail
!= NULL
);
4320 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4321 free_opnd_error_record_nodes
= operand_error_report
.head
;
4322 operand_error_report
.head
= NULL
;
4323 operand_error_report
.tail
= NULL
;
4326 gas_assert (operand_error_report
.tail
== NULL
);
4329 /* Return TRUE if some operand error has been recorded during the
4330 parsing of the current assembly line using the opcode *OPCODE;
4331 otherwise return FALSE. */
4332 static inline bfd_boolean
4333 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4335 operand_error_record
*record
= operand_error_report
.head
;
4336 return record
&& record
->opcode
== opcode
;
4339 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4340 OPCODE field is initialized with OPCODE.
4341 N.B. only one record for each opcode, i.e. the maximum of one error is
4342 recorded for each instruction template. */
4345 add_operand_error_record (const operand_error_record
* new_record
)
4347 const aarch64_opcode
*opcode
= new_record
->opcode
;
4348 operand_error_record
* record
= operand_error_report
.head
;
4350 /* The record may have been created for this opcode. If not, we need
4352 if (! opcode_has_operand_error_p (opcode
))
4354 /* Get one empty record. */
4355 if (free_opnd_error_record_nodes
== NULL
)
4357 record
= XNEW (operand_error_record
);
4361 record
= free_opnd_error_record_nodes
;
4362 free_opnd_error_record_nodes
= record
->next
;
4364 record
->opcode
= opcode
;
4365 /* Insert at the head. */
4366 record
->next
= operand_error_report
.head
;
4367 operand_error_report
.head
= record
;
4368 if (operand_error_report
.tail
== NULL
)
4369 operand_error_report
.tail
= record
;
4371 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4372 && record
->detail
.index
<= new_record
->detail
.index
4373 && operand_error_higher_severity_p (record
->detail
.kind
,
4374 new_record
->detail
.kind
))
4376 /* In the case of multiple errors found on operands related with a
4377 single opcode, only record the error of the leftmost operand and
4378 only if the error is of higher severity. */
4379 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4380 " the existing error %s on operand %d",
4381 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4382 new_record
->detail
.index
,
4383 operand_mismatch_kind_names
[record
->detail
.kind
],
4384 record
->detail
.index
);
4388 record
->detail
= new_record
->detail
;
4392 record_operand_error_info (const aarch64_opcode
*opcode
,
4393 aarch64_operand_error
*error_info
)
4395 operand_error_record record
;
4396 record
.opcode
= opcode
;
4397 record
.detail
= *error_info
;
4398 add_operand_error_record (&record
);
4401 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4402 error message *ERROR, for operand IDX (count from 0). */
4405 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4406 enum aarch64_operand_error_kind kind
,
4409 aarch64_operand_error info
;
4410 memset(&info
, 0, sizeof (info
));
4414 record_operand_error_info (opcode
, &info
);
4418 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4419 enum aarch64_operand_error_kind kind
,
4420 const char* error
, const int *extra_data
)
4422 aarch64_operand_error info
;
4426 info
.data
[0] = extra_data
[0];
4427 info
.data
[1] = extra_data
[1];
4428 info
.data
[2] = extra_data
[2];
4429 record_operand_error_info (opcode
, &info
);
4433 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4434 const char* error
, int lower_bound
,
4437 int data
[3] = {lower_bound
, upper_bound
, 0};
4438 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4442 /* Remove the operand error record for *OPCODE. */
4443 static void ATTRIBUTE_UNUSED
4444 remove_operand_error_record (const aarch64_opcode
*opcode
)
4446 if (opcode_has_operand_error_p (opcode
))
4448 operand_error_record
* record
= operand_error_report
.head
;
4449 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4450 operand_error_report
.head
= record
->next
;
4451 record
->next
= free_opnd_error_record_nodes
;
4452 free_opnd_error_record_nodes
= record
;
4453 if (operand_error_report
.head
== NULL
)
4455 gas_assert (operand_error_report
.tail
== record
);
4456 operand_error_report
.tail
= NULL
;
4461 /* Given the instruction in *INSTR, return the index of the best matched
4462 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4464 Return -1 if there is no qualifier sequence; return the first match
4465 if there is multiple matches found. */
4468 find_best_match (const aarch64_inst
*instr
,
4469 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4471 int i
, num_opnds
, max_num_matched
, idx
;
4473 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4476 DEBUG_TRACE ("no operand");
4480 max_num_matched
= 0;
4483 /* For each pattern. */
4484 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4487 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4489 /* Most opcodes has much fewer patterns in the list. */
4490 if (empty_qualifier_sequence_p (qualifiers
))
4492 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4496 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4497 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4500 if (num_matched
> max_num_matched
)
4502 max_num_matched
= num_matched
;
4507 DEBUG_TRACE ("return with %d", idx
);
4511 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4512 corresponding operands in *INSTR. */
4515 assign_qualifier_sequence (aarch64_inst
*instr
,
4516 const aarch64_opnd_qualifier_t
*qualifiers
)
4519 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4520 gas_assert (num_opnds
);
4521 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4522 instr
->operands
[i
].qualifier
= *qualifiers
;
4525 /* Print operands for the diagnosis purpose. */
4528 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4529 const aarch64_opnd_info
*opnds
)
4533 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4537 /* We regard the opcode operand info more, however we also look into
4538 the inst->operands to support the disassembling of the optional
4540 The two operand code should be the same in all cases, apart from
4541 when the operand can be optional. */
4542 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4543 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4546 /* Generate the operand string in STR. */
4547 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4551 strcat (buf
, i
== 0 ? " " : ", ");
4553 /* Append the operand string. */
4558 /* Send to stderr a string as information. */
4561 output_info (const char *format
, ...)
4567 file
= as_where (&line
);
4571 fprintf (stderr
, "%s:%u: ", file
, line
);
4573 fprintf (stderr
, "%s: ", file
);
4575 fprintf (stderr
, _("Info: "));
4576 va_start (args
, format
);
4577 vfprintf (stderr
, format
, args
);
4579 (void) putc ('\n', stderr
);
4582 /* Output one operand error record. */
4585 output_operand_error_record (const operand_error_record
*record
, char *str
)
4587 const aarch64_operand_error
*detail
= &record
->detail
;
4588 int idx
= detail
->index
;
4589 const aarch64_opcode
*opcode
= record
->opcode
;
4590 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4591 : AARCH64_OPND_NIL
);
4593 switch (detail
->kind
)
4595 case AARCH64_OPDE_NIL
:
4599 case AARCH64_OPDE_SYNTAX_ERROR
:
4600 case AARCH64_OPDE_RECOVERABLE
:
4601 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4602 case AARCH64_OPDE_OTHER_ERROR
:
4603 /* Use the prepared error message if there is, otherwise use the
4604 operand description string to describe the error. */
4605 if (detail
->error
!= NULL
)
4608 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4610 as_bad (_("%s at operand %d -- `%s'"),
4611 detail
->error
, idx
+ 1, str
);
4615 gas_assert (idx
>= 0);
4616 as_bad (_("operand %d must be %s -- `%s'"), idx
+ 1,
4617 aarch64_get_operand_desc (opd_code
), str
);
4621 case AARCH64_OPDE_INVALID_VARIANT
:
4622 as_bad (_("operand mismatch -- `%s'"), str
);
4623 if (verbose_error_p
)
4625 /* We will try to correct the erroneous instruction and also provide
4626 more information e.g. all other valid variants.
4628 The string representation of the corrected instruction and other
4629 valid variants are generated by
4631 1) obtaining the intermediate representation of the erroneous
4633 2) manipulating the IR, e.g. replacing the operand qualifier;
4634 3) printing out the instruction by calling the printer functions
4635 shared with the disassembler.
4637 The limitation of this method is that the exact input assembly
4638 line cannot be accurately reproduced in some cases, for example an
4639 optional operand present in the actual assembly line will be
4640 omitted in the output; likewise for the optional syntax rules,
4641 e.g. the # before the immediate. Another limitation is that the
4642 assembly symbols and relocation operations in the assembly line
4643 currently cannot be printed out in the error report. Last but not
4644 least, when there is other error(s) co-exist with this error, the
4645 'corrected' instruction may be still incorrect, e.g. given
4646 'ldnp h0,h1,[x0,#6]!'
4647 this diagnosis will provide the version:
4648 'ldnp s0,s1,[x0,#6]!'
4649 which is still not right. */
4650 size_t len
= strlen (get_mnemonic_name (str
));
4654 aarch64_inst
*inst_base
= &inst
.base
;
4655 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4658 reset_aarch64_instruction (&inst
);
4659 inst_base
->opcode
= opcode
;
4661 /* Reset the error report so that there is no side effect on the
4662 following operand parsing. */
4663 init_operand_error_report ();
4666 result
= parse_operands (str
+ len
, opcode
)
4667 && programmer_friendly_fixup (&inst
);
4668 gas_assert (result
);
4669 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4671 gas_assert (!result
);
4673 /* Find the most matched qualifier sequence. */
4674 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4675 gas_assert (qlf_idx
> -1);
4677 /* Assign the qualifiers. */
4678 assign_qualifier_sequence (inst_base
,
4679 opcode
->qualifiers_list
[qlf_idx
]);
4681 /* Print the hint. */
4682 output_info (_(" did you mean this?"));
4683 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4684 print_operands (buf
, opcode
, inst_base
->operands
);
4685 output_info (_(" %s"), buf
);
4687 /* Print out other variant(s) if there is any. */
4689 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4690 output_info (_(" other valid variant(s):"));
4692 /* For each pattern. */
4693 qualifiers_list
= opcode
->qualifiers_list
;
4694 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4696 /* Most opcodes has much fewer patterns in the list.
4697 First NIL qualifier indicates the end in the list. */
4698 if (empty_qualifier_sequence_p (*qualifiers_list
))
4703 /* Mnemonics name. */
4704 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4706 /* Assign the qualifiers. */
4707 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4709 /* Print instruction. */
4710 print_operands (buf
, opcode
, inst_base
->operands
);
4712 output_info (_(" %s"), buf
);
4718 case AARCH64_OPDE_UNTIED_OPERAND
:
4719 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4720 detail
->index
+ 1, str
);
4723 case AARCH64_OPDE_OUT_OF_RANGE
:
4724 if (detail
->data
[0] != detail
->data
[1])
4725 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4726 detail
->error
? detail
->error
: _("immediate value"),
4727 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4729 as_bad (_("%s must be %d at operand %d -- `%s'"),
4730 detail
->error
? detail
->error
: _("immediate value"),
4731 detail
->data
[0], idx
+ 1, str
);
4734 case AARCH64_OPDE_REG_LIST
:
4735 if (detail
->data
[0] == 1)
4736 as_bad (_("invalid number of registers in the list; "
4737 "only 1 register is expected at operand %d -- `%s'"),
4740 as_bad (_("invalid number of registers in the list; "
4741 "%d registers are expected at operand %d -- `%s'"),
4742 detail
->data
[0], idx
+ 1, str
);
4745 case AARCH64_OPDE_UNALIGNED
:
4746 as_bad (_("immediate value must be a multiple of "
4747 "%d at operand %d -- `%s'"),
4748 detail
->data
[0], idx
+ 1, str
);
4757 /* Process and output the error message about the operand mismatching.
4759 When this function is called, the operand error information had
4760 been collected for an assembly line and there will be multiple
4761 errors in the case of multiple instruction templates; output the
4762 error message that most closely describes the problem. */
4765 output_operand_error_report (char *str
)
4767 int largest_error_pos
;
4768 const char *msg
= NULL
;
4769 enum aarch64_operand_error_kind kind
;
4770 operand_error_record
*curr
;
4771 operand_error_record
*head
= operand_error_report
.head
;
4772 operand_error_record
*record
= NULL
;
4774 /* No error to report. */
4778 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4780 /* Only one error. */
4781 if (head
== operand_error_report
.tail
)
4783 DEBUG_TRACE ("single opcode entry with error kind: %s",
4784 operand_mismatch_kind_names
[head
->detail
.kind
]);
4785 output_operand_error_record (head
, str
);
4789 /* Find the error kind of the highest severity. */
4790 DEBUG_TRACE ("multiple opcode entries with error kind");
4791 kind
= AARCH64_OPDE_NIL
;
4792 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4794 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4795 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4796 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4797 kind
= curr
->detail
.kind
;
4799 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4801 /* Pick up one of errors of KIND to report. */
4802 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4803 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4805 if (curr
->detail
.kind
!= kind
)
4807 /* If there are multiple errors, pick up the one with the highest
4808 mismatching operand index. In the case of multiple errors with
4809 the equally highest operand index, pick up the first one or the
4810 first one with non-NULL error message. */
4811 if (curr
->detail
.index
> largest_error_pos
4812 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4813 && curr
->detail
.error
!= NULL
))
4815 largest_error_pos
= curr
->detail
.index
;
4817 msg
= record
->detail
.error
;
4821 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4822 DEBUG_TRACE ("Pick up error kind %s to report",
4823 operand_mismatch_kind_names
[record
->detail
.kind
]);
4826 output_operand_error_record (record
, str
);
4829 /* Write an AARCH64 instruction to buf - always little-endian. */
4831 put_aarch64_insn (char *buf
, uint32_t insn
)
4833 unsigned char *where
= (unsigned char *) buf
;
4835 where
[1] = insn
>> 8;
4836 where
[2] = insn
>> 16;
4837 where
[3] = insn
>> 24;
4841 get_aarch64_insn (char *buf
)
4843 unsigned char *where
= (unsigned char *) buf
;
4845 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4850 output_inst (struct aarch64_inst
*new_inst
)
4854 to
= frag_more (INSN_SIZE
);
4856 frag_now
->tc_frag_data
.recorded
= 1;
4858 put_aarch64_insn (to
, inst
.base
.value
);
4860 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4862 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4863 INSN_SIZE
, &inst
.reloc
.exp
,
4866 DEBUG_TRACE ("Prepared relocation fix up");
4867 /* Don't check the addend value against the instruction size,
4868 that's the job of our code in md_apply_fix(). */
4869 fixp
->fx_no_overflow
= 1;
4870 if (new_inst
!= NULL
)
4871 fixp
->tc_fix_data
.inst
= new_inst
;
4872 if (aarch64_gas_internal_fixup_p ())
4874 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4875 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4876 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4880 dwarf2_emit_insn (INSN_SIZE
);
4883 /* Link together opcodes of the same name. */
4887 aarch64_opcode
*opcode
;
4888 struct templates
*next
;
4891 typedef struct templates templates
;
4894 lookup_mnemonic (const char *start
, int len
)
4896 templates
*templ
= NULL
;
4898 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4902 /* Subroutine of md_assemble, responsible for looking up the primary
4903 opcode from the mnemonic the user wrote. STR points to the
4904 beginning of the mnemonic. */
4907 opcode_lookup (char **str
)
4909 char *end
, *base
, *dot
;
4910 const aarch64_cond
*cond
;
4914 /* Scan up to the end of the mnemonic, which must end in white space,
4915 '.', or end of string. */
4917 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4918 if (*end
== '.' && !dot
)
4921 if (end
== base
|| dot
== base
)
4924 inst
.cond
= COND_ALWAYS
;
4926 /* Handle a possible condition. */
4929 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
4932 inst
.cond
= cond
->value
;
4948 if (inst
.cond
== COND_ALWAYS
)
4950 /* Look for unaffixed mnemonic. */
4951 return lookup_mnemonic (base
, len
);
4955 /* append ".c" to mnemonic if conditional */
4956 memcpy (condname
, base
, len
);
4957 memcpy (condname
+ len
, ".c", 2);
4960 return lookup_mnemonic (base
, len
);
4966 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4967 to a corresponding operand qualifier. */
4969 static inline aarch64_opnd_qualifier_t
4970 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4972 /* Element size in bytes indexed by vector_el_type. */
4973 const unsigned char ele_size
[5]
4975 const unsigned int ele_base
[5] =
4977 AARCH64_OPND_QLF_V_4B
,
4978 AARCH64_OPND_QLF_V_2H
,
4979 AARCH64_OPND_QLF_V_2S
,
4980 AARCH64_OPND_QLF_V_1D
,
4981 AARCH64_OPND_QLF_V_1Q
4984 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4985 goto vectype_conversion_fail
;
4987 if (vectype
->type
== NT_zero
)
4988 return AARCH64_OPND_QLF_P_Z
;
4989 if (vectype
->type
== NT_merge
)
4990 return AARCH64_OPND_QLF_P_M
;
4992 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4994 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
4996 /* Special case S_4B. */
4997 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
4998 return AARCH64_OPND_QLF_S_4B
;
5000 /* Vector element register. */
5001 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5005 /* Vector register. */
5006 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5009 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5010 goto vectype_conversion_fail
;
5012 /* The conversion is by calculating the offset from the base operand
5013 qualifier for the vector type. The operand qualifiers are regular
5014 enough that the offset can established by shifting the vector width by
5015 a vector-type dependent amount. */
5017 if (vectype
->type
== NT_b
)
5019 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5021 else if (vectype
->type
>= NT_d
)
5026 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5027 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5028 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5032 vectype_conversion_fail
:
5033 first_error (_("bad vector arrangement type"));
5034 return AARCH64_OPND_QLF_NIL
;
5037 /* Process an optional operand that is found omitted from the assembly line.
5038 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5039 instruction's opcode entry while IDX is the index of this omitted operand.
5043 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5044 int idx
, aarch64_opnd_info
*operand
)
5046 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5047 gas_assert (optional_operand_p (opcode
, idx
));
5048 gas_assert (!operand
->present
);
5052 case AARCH64_OPND_Rd
:
5053 case AARCH64_OPND_Rn
:
5054 case AARCH64_OPND_Rm
:
5055 case AARCH64_OPND_Rt
:
5056 case AARCH64_OPND_Rt2
:
5057 case AARCH64_OPND_Rs
:
5058 case AARCH64_OPND_Ra
:
5059 case AARCH64_OPND_Rt_SYS
:
5060 case AARCH64_OPND_Rd_SP
:
5061 case AARCH64_OPND_Rn_SP
:
5062 case AARCH64_OPND_Rm_SP
:
5063 case AARCH64_OPND_Fd
:
5064 case AARCH64_OPND_Fn
:
5065 case AARCH64_OPND_Fm
:
5066 case AARCH64_OPND_Fa
:
5067 case AARCH64_OPND_Ft
:
5068 case AARCH64_OPND_Ft2
:
5069 case AARCH64_OPND_Sd
:
5070 case AARCH64_OPND_Sn
:
5071 case AARCH64_OPND_Sm
:
5072 case AARCH64_OPND_Va
:
5073 case AARCH64_OPND_Vd
:
5074 case AARCH64_OPND_Vn
:
5075 case AARCH64_OPND_Vm
:
5076 case AARCH64_OPND_VdD1
:
5077 case AARCH64_OPND_VnD1
:
5078 operand
->reg
.regno
= default_value
;
5081 case AARCH64_OPND_Ed
:
5082 case AARCH64_OPND_En
:
5083 case AARCH64_OPND_Em
:
5084 case AARCH64_OPND_SM3_IMM2
:
5085 operand
->reglane
.regno
= default_value
;
5088 case AARCH64_OPND_IDX
:
5089 case AARCH64_OPND_BIT_NUM
:
5090 case AARCH64_OPND_IMMR
:
5091 case AARCH64_OPND_IMMS
:
5092 case AARCH64_OPND_SHLL_IMM
:
5093 case AARCH64_OPND_IMM_VLSL
:
5094 case AARCH64_OPND_IMM_VLSR
:
5095 case AARCH64_OPND_CCMP_IMM
:
5096 case AARCH64_OPND_FBITS
:
5097 case AARCH64_OPND_UIMM4
:
5098 case AARCH64_OPND_UIMM3_OP1
:
5099 case AARCH64_OPND_UIMM3_OP2
:
5100 case AARCH64_OPND_IMM
:
5101 case AARCH64_OPND_IMM_2
:
5102 case AARCH64_OPND_WIDTH
:
5103 case AARCH64_OPND_UIMM7
:
5104 case AARCH64_OPND_NZCV
:
5105 case AARCH64_OPND_SVE_PATTERN
:
5106 case AARCH64_OPND_SVE_PRFOP
:
5107 operand
->imm
.value
= default_value
;
5110 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5111 operand
->imm
.value
= default_value
;
5112 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5113 operand
->shifter
.amount
= 1;
5116 case AARCH64_OPND_EXCEPTION
:
5117 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5120 case AARCH64_OPND_BARRIER_ISB
:
5121 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5128 /* Process the relocation type for move wide instructions.
5129 Return TRUE on success; otherwise return FALSE. */
5132 process_movw_reloc_info (void)
5137 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5139 if (inst
.base
.opcode
->op
== OP_MOVK
)
5140 switch (inst
.reloc
.type
)
5142 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5143 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5144 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5145 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5146 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5147 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5148 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5149 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5150 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5151 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5152 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5154 (_("the specified relocation type is not allowed for MOVK"));
5160 switch (inst
.reloc
.type
)
5162 case BFD_RELOC_AARCH64_MOVW_G0
:
5163 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5164 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5165 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5166 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5167 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5168 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5169 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5170 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5171 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5172 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5173 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5174 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5177 case BFD_RELOC_AARCH64_MOVW_G1
:
5178 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5179 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5180 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5181 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5182 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5183 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5184 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5185 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5186 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5187 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5188 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5189 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5192 case BFD_RELOC_AARCH64_MOVW_G2
:
5193 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5194 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5195 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5196 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5197 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5198 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5201 set_fatal_syntax_error
5202 (_("the specified relocation type is not allowed for 32-bit "
5208 case BFD_RELOC_AARCH64_MOVW_G3
:
5209 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5212 set_fatal_syntax_error
5213 (_("the specified relocation type is not allowed for 32-bit "
5220 /* More cases should be added when more MOVW-related relocation types
5221 are supported in GAS. */
5222 gas_assert (aarch64_gas_internal_fixup_p ());
5223 /* The shift amount should have already been set by the parser. */
5226 inst
.base
.operands
[1].shifter
.amount
= shift
;
5230 /* A primitive log calculator. */
5232 static inline unsigned int
5233 get_logsz (unsigned int size
)
5235 const unsigned char ls
[16] =
5236 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5242 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5243 return ls
[size
- 1];
5246 /* Determine and return the real reloc type code for an instruction
5247 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5249 static inline bfd_reloc_code_real_type
5250 ldst_lo12_determine_real_reloc_type (void)
5253 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5254 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5256 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
5258 BFD_RELOC_AARCH64_LDST8_LO12
,
5259 BFD_RELOC_AARCH64_LDST16_LO12
,
5260 BFD_RELOC_AARCH64_LDST32_LO12
,
5261 BFD_RELOC_AARCH64_LDST64_LO12
,
5262 BFD_RELOC_AARCH64_LDST128_LO12
5265 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5266 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5267 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5268 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5269 BFD_RELOC_AARCH64_NONE
5272 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5273 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5274 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5275 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5276 BFD_RELOC_AARCH64_NONE
5280 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5281 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5283 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
5284 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5286 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5288 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5290 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5292 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5293 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5294 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5295 gas_assert (logsz
<= 3);
5297 gas_assert (logsz
<= 4);
5299 /* In reloc.c, these pseudo relocation types should be defined in similar
5300 order as above reloc_ldst_lo12 array. Because the array index calculation
5301 below relies on this. */
5302 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5305 /* Check whether a register list REGINFO is valid. The registers must be
5306 numbered in increasing order (modulo 32), in increments of one or two.
5308 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5311 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5314 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5316 uint32_t i
, nb_regs
, prev_regno
, incr
;
5318 nb_regs
= 1 + (reginfo
& 0x3);
5320 prev_regno
= reginfo
& 0x1f;
5321 incr
= accept_alternate
? 2 : 1;
5323 for (i
= 1; i
< nb_regs
; ++i
)
5325 uint32_t curr_regno
;
5327 curr_regno
= reginfo
& 0x1f;
5328 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5330 prev_regno
= curr_regno
;
5336 /* Generic instruction operand parser. This does no encoding and no
5337 semantic validation; it merely squirrels values away in the inst
5338 structure. Returns TRUE or FALSE depending on whether the
5339 specified grammar matched. */
5342 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5345 char *backtrack_pos
= 0;
5346 const enum aarch64_opnd
*operands
= opcode
->operands
;
5347 aarch64_reg_type imm_reg_type
;
5350 skip_whitespace (str
);
5352 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5353 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5355 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5357 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5360 const reg_entry
*reg
;
5361 int comma_skipped_p
= 0;
5362 aarch64_reg_type rtype
;
5363 struct vector_type_el vectype
;
5364 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5365 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5366 aarch64_reg_type reg_type
;
5368 DEBUG_TRACE ("parse operand %d", i
);
5370 /* Assign the operand code. */
5371 info
->type
= operands
[i
];
5373 if (optional_operand_p (opcode
, i
))
5375 /* Remember where we are in case we need to backtrack. */
5376 gas_assert (!backtrack_pos
);
5377 backtrack_pos
= str
;
5380 /* Expect comma between operands; the backtrack mechanism will take
5381 care of cases of omitted optional operand. */
5382 if (i
> 0 && ! skip_past_char (&str
, ','))
5384 set_syntax_error (_("comma expected between operands"));
5388 comma_skipped_p
= 1;
5390 switch (operands
[i
])
5392 case AARCH64_OPND_Rd
:
5393 case AARCH64_OPND_Rn
:
5394 case AARCH64_OPND_Rm
:
5395 case AARCH64_OPND_Rt
:
5396 case AARCH64_OPND_Rt2
:
5397 case AARCH64_OPND_Rs
:
5398 case AARCH64_OPND_Ra
:
5399 case AARCH64_OPND_Rt_SYS
:
5400 case AARCH64_OPND_PAIRREG
:
5401 case AARCH64_OPND_SVE_Rm
:
5402 po_int_reg_or_fail (REG_TYPE_R_Z
);
5405 case AARCH64_OPND_Rd_SP
:
5406 case AARCH64_OPND_Rn_SP
:
5407 case AARCH64_OPND_SVE_Rn_SP
:
5408 case AARCH64_OPND_Rm_SP
:
5409 po_int_reg_or_fail (REG_TYPE_R_SP
);
5412 case AARCH64_OPND_Rm_EXT
:
5413 case AARCH64_OPND_Rm_SFT
:
5414 po_misc_or_fail (parse_shifter_operand
5415 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5417 : SHIFTED_LOGIC_IMM
)));
5418 if (!info
->shifter
.operator_present
)
5420 /* Default to LSL if not present. Libopcodes prefers shifter
5421 kind to be explicit. */
5422 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5423 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5424 /* For Rm_EXT, libopcodes will carry out further check on whether
5425 or not stack pointer is used in the instruction (Recall that
5426 "the extend operator is not optional unless at least one of
5427 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5431 case AARCH64_OPND_Fd
:
5432 case AARCH64_OPND_Fn
:
5433 case AARCH64_OPND_Fm
:
5434 case AARCH64_OPND_Fa
:
5435 case AARCH64_OPND_Ft
:
5436 case AARCH64_OPND_Ft2
:
5437 case AARCH64_OPND_Sd
:
5438 case AARCH64_OPND_Sn
:
5439 case AARCH64_OPND_Sm
:
5440 case AARCH64_OPND_SVE_VZn
:
5441 case AARCH64_OPND_SVE_Vd
:
5442 case AARCH64_OPND_SVE_Vm
:
5443 case AARCH64_OPND_SVE_Vn
:
5444 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5445 if (val
== PARSE_FAIL
)
5447 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5450 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5452 info
->reg
.regno
= val
;
5453 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5456 case AARCH64_OPND_SVE_Pd
:
5457 case AARCH64_OPND_SVE_Pg3
:
5458 case AARCH64_OPND_SVE_Pg4_5
:
5459 case AARCH64_OPND_SVE_Pg4_10
:
5460 case AARCH64_OPND_SVE_Pg4_16
:
5461 case AARCH64_OPND_SVE_Pm
:
5462 case AARCH64_OPND_SVE_Pn
:
5463 case AARCH64_OPND_SVE_Pt
:
5464 reg_type
= REG_TYPE_PN
;
5467 case AARCH64_OPND_SVE_Za_5
:
5468 case AARCH64_OPND_SVE_Za_16
:
5469 case AARCH64_OPND_SVE_Zd
:
5470 case AARCH64_OPND_SVE_Zm_5
:
5471 case AARCH64_OPND_SVE_Zm_16
:
5472 case AARCH64_OPND_SVE_Zn
:
5473 case AARCH64_OPND_SVE_Zt
:
5474 reg_type
= REG_TYPE_ZN
;
5477 case AARCH64_OPND_Va
:
5478 case AARCH64_OPND_Vd
:
5479 case AARCH64_OPND_Vn
:
5480 case AARCH64_OPND_Vm
:
5481 reg_type
= REG_TYPE_VN
;
5483 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5484 if (val
== PARSE_FAIL
)
5486 first_error (_(get_reg_expected_msg (reg_type
)));
5489 if (vectype
.defined
& NTA_HASINDEX
)
5492 info
->reg
.regno
= val
;
5493 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5494 && vectype
.type
== NT_invtype
)
5495 /* Unqualified Pn and Zn registers are allowed in certain
5496 contexts. Rely on F_STRICT qualifier checking to catch
5498 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5501 info
->qualifier
= vectype_to_qualifier (&vectype
);
5502 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5507 case AARCH64_OPND_VdD1
:
5508 case AARCH64_OPND_VnD1
:
5509 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5510 if (val
== PARSE_FAIL
)
5512 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5515 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5517 set_fatal_syntax_error
5518 (_("the top half of a 128-bit FP/SIMD register is expected"));
5521 info
->reg
.regno
= val
;
5522 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5523 here; it is correct for the purpose of encoding/decoding since
5524 only the register number is explicitly encoded in the related
5525 instructions, although this appears a bit hacky. */
5526 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5529 case AARCH64_OPND_SVE_Zm3_INDEX
:
5530 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5531 case AARCH64_OPND_SVE_Zm4_INDEX
:
5532 case AARCH64_OPND_SVE_Zn_INDEX
:
5533 reg_type
= REG_TYPE_ZN
;
5534 goto vector_reg_index
;
5536 case AARCH64_OPND_Ed
:
5537 case AARCH64_OPND_En
:
5538 case AARCH64_OPND_Em
:
5539 case AARCH64_OPND_SM3_IMM2
:
5540 reg_type
= REG_TYPE_VN
;
5542 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5543 if (val
== PARSE_FAIL
)
5545 first_error (_(get_reg_expected_msg (reg_type
)));
5548 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5551 info
->reglane
.regno
= val
;
5552 info
->reglane
.index
= vectype
.index
;
5553 info
->qualifier
= vectype_to_qualifier (&vectype
);
5554 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5558 case AARCH64_OPND_SVE_ZnxN
:
5559 case AARCH64_OPND_SVE_ZtxN
:
5560 reg_type
= REG_TYPE_ZN
;
5561 goto vector_reg_list
;
5563 case AARCH64_OPND_LVn
:
5564 case AARCH64_OPND_LVt
:
5565 case AARCH64_OPND_LVt_AL
:
5566 case AARCH64_OPND_LEt
:
5567 reg_type
= REG_TYPE_VN
;
5569 if (reg_type
== REG_TYPE_ZN
5570 && get_opcode_dependent_value (opcode
) == 1
5573 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5574 if (val
== PARSE_FAIL
)
5576 first_error (_(get_reg_expected_msg (reg_type
)));
5579 info
->reglist
.first_regno
= val
;
5580 info
->reglist
.num_regs
= 1;
5584 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5585 if (val
== PARSE_FAIL
)
5587 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5589 set_fatal_syntax_error (_("invalid register list"));
5592 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5593 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5595 if (operands
[i
] == AARCH64_OPND_LEt
)
5597 if (!(vectype
.defined
& NTA_HASINDEX
))
5599 info
->reglist
.has_index
= 1;
5600 info
->reglist
.index
= vectype
.index
;
5604 if (vectype
.defined
& NTA_HASINDEX
)
5606 if (!(vectype
.defined
& NTA_HASTYPE
))
5608 if (reg_type
== REG_TYPE_ZN
)
5609 set_fatal_syntax_error (_("missing type suffix"));
5613 info
->qualifier
= vectype_to_qualifier (&vectype
);
5614 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5618 case AARCH64_OPND_CRn
:
5619 case AARCH64_OPND_CRm
:
5621 char prefix
= *(str
++);
5622 if (prefix
!= 'c' && prefix
!= 'C')
5625 po_imm_nc_or_fail ();
5628 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5631 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5632 info
->imm
.value
= val
;
5636 case AARCH64_OPND_SHLL_IMM
:
5637 case AARCH64_OPND_IMM_VLSR
:
5638 po_imm_or_fail (1, 64);
5639 info
->imm
.value
= val
;
5642 case AARCH64_OPND_CCMP_IMM
:
5643 case AARCH64_OPND_SIMM5
:
5644 case AARCH64_OPND_FBITS
:
5645 case AARCH64_OPND_UIMM4
:
5646 case AARCH64_OPND_UIMM3_OP1
:
5647 case AARCH64_OPND_UIMM3_OP2
:
5648 case AARCH64_OPND_IMM_VLSL
:
5649 case AARCH64_OPND_IMM
:
5650 case AARCH64_OPND_IMM_2
:
5651 case AARCH64_OPND_WIDTH
:
5652 case AARCH64_OPND_SVE_INV_LIMM
:
5653 case AARCH64_OPND_SVE_LIMM
:
5654 case AARCH64_OPND_SVE_LIMM_MOV
:
5655 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5656 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5657 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5658 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5659 case AARCH64_OPND_SVE_SIMM5
:
5660 case AARCH64_OPND_SVE_SIMM5B
:
5661 case AARCH64_OPND_SVE_SIMM6
:
5662 case AARCH64_OPND_SVE_SIMM8
:
5663 case AARCH64_OPND_SVE_UIMM3
:
5664 case AARCH64_OPND_SVE_UIMM7
:
5665 case AARCH64_OPND_SVE_UIMM8
:
5666 case AARCH64_OPND_SVE_UIMM8_53
:
5667 case AARCH64_OPND_IMM_ROT1
:
5668 case AARCH64_OPND_IMM_ROT2
:
5669 case AARCH64_OPND_IMM_ROT3
:
5670 case AARCH64_OPND_SVE_IMM_ROT1
:
5671 case AARCH64_OPND_SVE_IMM_ROT2
:
5672 po_imm_nc_or_fail ();
5673 info
->imm
.value
= val
;
5676 case AARCH64_OPND_SVE_AIMM
:
5677 case AARCH64_OPND_SVE_ASIMM
:
5678 po_imm_nc_or_fail ();
5679 info
->imm
.value
= val
;
5680 skip_whitespace (str
);
5681 if (skip_past_comma (&str
))
5682 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5684 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5687 case AARCH64_OPND_SVE_PATTERN
:
5688 po_enum_or_fail (aarch64_sve_pattern_array
);
5689 info
->imm
.value
= val
;
5692 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5693 po_enum_or_fail (aarch64_sve_pattern_array
);
5694 info
->imm
.value
= val
;
5695 if (skip_past_comma (&str
)
5696 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5698 if (!info
->shifter
.operator_present
)
5700 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5701 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5702 info
->shifter
.amount
= 1;
5706 case AARCH64_OPND_SVE_PRFOP
:
5707 po_enum_or_fail (aarch64_sve_prfop_array
);
5708 info
->imm
.value
= val
;
5711 case AARCH64_OPND_UIMM7
:
5712 po_imm_or_fail (0, 127);
5713 info
->imm
.value
= val
;
5716 case AARCH64_OPND_IDX
:
5717 case AARCH64_OPND_MASK
:
5718 case AARCH64_OPND_BIT_NUM
:
5719 case AARCH64_OPND_IMMR
:
5720 case AARCH64_OPND_IMMS
:
5721 po_imm_or_fail (0, 63);
5722 info
->imm
.value
= val
;
5725 case AARCH64_OPND_IMM0
:
5726 po_imm_nc_or_fail ();
5729 set_fatal_syntax_error (_("immediate zero expected"));
5732 info
->imm
.value
= 0;
5735 case AARCH64_OPND_FPIMM0
:
5738 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5739 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5740 it is probably not worth the effort to support it. */
5741 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5744 || !(res2
= parse_constant_immediate (&str
, &val
,
5747 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5749 info
->imm
.value
= 0;
5750 info
->imm
.is_fp
= 1;
5753 set_fatal_syntax_error (_("immediate zero expected"));
5757 case AARCH64_OPND_IMM_MOV
:
5760 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5761 reg_name_p (str
, REG_TYPE_VN
))
5764 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5766 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5767 later. fix_mov_imm_insn will try to determine a machine
5768 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5769 message if the immediate cannot be moved by a single
5771 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5772 inst
.base
.operands
[i
].skip
= 1;
5776 case AARCH64_OPND_SIMD_IMM
:
5777 case AARCH64_OPND_SIMD_IMM_SFT
:
5778 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5780 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5782 /* need_libopcodes_p */ 1,
5785 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5786 shift, we don't check it here; we leave the checking to
5787 the libopcodes (operand_general_constraint_met_p). By
5788 doing this, we achieve better diagnostics. */
5789 if (skip_past_comma (&str
)
5790 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5792 if (!info
->shifter
.operator_present
5793 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5795 /* Default to LSL if not present. Libopcodes prefers shifter
5796 kind to be explicit. */
5797 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5798 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5802 case AARCH64_OPND_FPIMM
:
5803 case AARCH64_OPND_SIMD_FPIMM
:
5804 case AARCH64_OPND_SVE_FPIMM8
:
5809 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5810 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5811 || !aarch64_imm_float_p (qfloat
))
5814 set_fatal_syntax_error (_("invalid floating-point"
5818 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5819 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5823 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5824 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5825 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5830 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5831 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5834 set_fatal_syntax_error (_("invalid floating-point"
5838 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5839 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5843 case AARCH64_OPND_LIMM
:
5844 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5845 SHIFTED_LOGIC_IMM
));
5846 if (info
->shifter
.operator_present
)
5848 set_fatal_syntax_error
5849 (_("shift not allowed for bitmask immediate"));
5852 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5854 /* need_libopcodes_p */ 1,
5858 case AARCH64_OPND_AIMM
:
5859 if (opcode
->op
== OP_ADD
)
5860 /* ADD may have relocation types. */
5861 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5862 SHIFTED_ARITH_IMM
));
5864 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5865 SHIFTED_ARITH_IMM
));
5866 switch (inst
.reloc
.type
)
5868 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5869 info
->shifter
.amount
= 12;
5871 case BFD_RELOC_UNUSED
:
5872 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5873 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5874 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5875 inst
.reloc
.pc_rel
= 0;
5880 info
->imm
.value
= 0;
5881 if (!info
->shifter
.operator_present
)
5883 /* Default to LSL if not present. Libopcodes prefers shifter
5884 kind to be explicit. */
5885 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5886 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5890 case AARCH64_OPND_HALF
:
5892 /* #<imm16> or relocation. */
5893 int internal_fixup_p
;
5894 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5895 if (internal_fixup_p
)
5896 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5897 skip_whitespace (str
);
5898 if (skip_past_comma (&str
))
5900 /* {, LSL #<shift>} */
5901 if (! aarch64_gas_internal_fixup_p ())
5903 set_fatal_syntax_error (_("can't mix relocation modifier "
5904 "with explicit shift"));
5907 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5910 inst
.base
.operands
[i
].shifter
.amount
= 0;
5911 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5912 inst
.base
.operands
[i
].imm
.value
= 0;
5913 if (! process_movw_reloc_info ())
5918 case AARCH64_OPND_EXCEPTION
:
5919 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5921 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5923 /* need_libopcodes_p */ 0,
5927 case AARCH64_OPND_NZCV
:
5929 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5933 info
->imm
.value
= nzcv
->value
;
5936 po_imm_or_fail (0, 15);
5937 info
->imm
.value
= val
;
5941 case AARCH64_OPND_COND
:
5942 case AARCH64_OPND_COND1
:
5947 while (ISALPHA (*str
));
5948 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
5949 if (info
->cond
== NULL
)
5951 set_syntax_error (_("invalid condition"));
5954 else if (operands
[i
] == AARCH64_OPND_COND1
5955 && (info
->cond
->value
& 0xe) == 0xe)
5957 /* Do not allow AL or NV. */
5958 set_default_error ();
5964 case AARCH64_OPND_ADDR_ADRP
:
5965 po_misc_or_fail (parse_adrp (&str
));
5966 /* Clear the value as operand needs to be relocated. */
5967 info
->imm
.value
= 0;
5970 case AARCH64_OPND_ADDR_PCREL14
:
5971 case AARCH64_OPND_ADDR_PCREL19
:
5972 case AARCH64_OPND_ADDR_PCREL21
:
5973 case AARCH64_OPND_ADDR_PCREL26
:
5974 po_misc_or_fail (parse_address (&str
, info
));
5975 if (!info
->addr
.pcrel
)
5977 set_syntax_error (_("invalid pc-relative address"));
5980 if (inst
.gen_lit_pool
5981 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5983 /* Only permit "=value" in the literal load instructions.
5984 The literal will be generated by programmer_friendly_fixup. */
5985 set_syntax_error (_("invalid use of \"=immediate\""));
5988 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5990 set_syntax_error (_("unrecognized relocation suffix"));
5993 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5995 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5996 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6000 info
->imm
.value
= 0;
6001 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6002 switch (opcode
->iclass
)
6006 /* e.g. CBZ or B.COND */
6007 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6008 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6012 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6013 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6017 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6019 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6020 : BFD_RELOC_AARCH64_JUMP26
;
6023 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6024 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6027 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6028 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6034 inst
.reloc
.pc_rel
= 1;
6038 case AARCH64_OPND_ADDR_SIMPLE
:
6039 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6041 /* [<Xn|SP>{, #<simm>}] */
6043 /* First use the normal address-parsing routines, to get
6044 the usual syntax errors. */
6045 po_misc_or_fail (parse_address (&str
, info
));
6046 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6047 || !info
->addr
.preind
|| info
->addr
.postind
6048 || info
->addr
.writeback
)
6050 set_syntax_error (_("invalid addressing mode"));
6054 /* Then retry, matching the specific syntax of these addresses. */
6056 po_char_or_fail ('[');
6057 po_reg_or_fail (REG_TYPE_R64_SP
);
6058 /* Accept optional ", #0". */
6059 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6060 && skip_past_char (&str
, ','))
6062 skip_past_char (&str
, '#');
6063 if (! skip_past_char (&str
, '0'))
6065 set_fatal_syntax_error
6066 (_("the optional immediate offset can only be 0"));
6070 po_char_or_fail (']');
6074 case AARCH64_OPND_ADDR_REGOFF
:
6075 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6076 po_misc_or_fail (parse_address (&str
, info
));
6078 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6079 || !info
->addr
.preind
|| info
->addr
.postind
6080 || info
->addr
.writeback
)
6082 set_syntax_error (_("invalid addressing mode"));
6085 if (!info
->shifter
.operator_present
)
6087 /* Default to LSL if not present. Libopcodes prefers shifter
6088 kind to be explicit. */
6089 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6090 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6092 /* Qualifier to be deduced by libopcodes. */
6095 case AARCH64_OPND_ADDR_SIMM7
:
6096 po_misc_or_fail (parse_address (&str
, info
));
6097 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6098 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6100 set_syntax_error (_("invalid addressing mode"));
6103 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6105 set_syntax_error (_("relocation not allowed"));
6108 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6110 /* need_libopcodes_p */ 1,
6114 case AARCH64_OPND_ADDR_SIMM9
:
6115 case AARCH64_OPND_ADDR_SIMM9_2
:
6116 po_misc_or_fail (parse_address (&str
, info
));
6117 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6118 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6119 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6120 && info
->addr
.writeback
))
6122 set_syntax_error (_("invalid addressing mode"));
6125 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6127 set_syntax_error (_("relocation not allowed"));
6130 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6132 /* need_libopcodes_p */ 1,
6136 case AARCH64_OPND_ADDR_SIMM10
:
6137 case AARCH64_OPND_ADDR_OFFSET
:
6138 po_misc_or_fail (parse_address (&str
, info
));
6139 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6140 || !info
->addr
.preind
|| info
->addr
.postind
)
6142 set_syntax_error (_("invalid addressing mode"));
6145 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6147 set_syntax_error (_("relocation not allowed"));
6150 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6152 /* need_libopcodes_p */ 1,
6156 case AARCH64_OPND_ADDR_UIMM12
:
6157 po_misc_or_fail (parse_address (&str
, info
));
6158 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6159 || !info
->addr
.preind
|| info
->addr
.writeback
)
6161 set_syntax_error (_("invalid addressing mode"));
6164 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6165 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6166 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6168 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6170 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
6171 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6172 /* Leave qualifier to be determined by libopcodes. */
6175 case AARCH64_OPND_SIMD_ADDR_POST
:
6176 /* [<Xn|SP>], <Xm|#<amount>> */
6177 po_misc_or_fail (parse_address (&str
, info
));
6178 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6180 set_syntax_error (_("invalid addressing mode"));
6183 if (!info
->addr
.offset
.is_reg
)
6185 if (inst
.reloc
.exp
.X_op
== O_constant
)
6186 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6189 set_fatal_syntax_error
6190 (_("writeback value must be an immediate constant"));
6197 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6198 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6199 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6200 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6201 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6202 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6203 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6204 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6205 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6206 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6207 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6208 /* [X<n>{, #imm, MUL VL}]
6210 but recognizing SVE registers. */
6211 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6212 &offset_qualifier
));
6213 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6215 set_syntax_error (_("invalid addressing mode"));
6219 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6220 || !info
->addr
.preind
|| info
->addr
.writeback
)
6222 set_syntax_error (_("invalid addressing mode"));
6225 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6226 || inst
.reloc
.exp
.X_op
!= O_constant
)
6228 /* Make sure this has priority over
6229 "invalid addressing mode". */
6230 set_fatal_syntax_error (_("constant offset required"));
6233 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6236 case AARCH64_OPND_SVE_ADDR_RR
:
6237 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6238 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6239 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6240 case AARCH64_OPND_SVE_ADDR_RX
:
6241 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6242 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6243 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6244 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6245 but recognizing SVE registers. */
6246 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6247 &offset_qualifier
));
6248 if (base_qualifier
!= AARCH64_OPND_QLF_X
6249 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6251 set_syntax_error (_("invalid addressing mode"));
6256 case AARCH64_OPND_SVE_ADDR_RZ
:
6257 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6258 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6259 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6260 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6261 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6262 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6263 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6264 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6265 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6266 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6267 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6268 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6269 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6270 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6271 &offset_qualifier
));
6272 if (base_qualifier
!= AARCH64_OPND_QLF_X
6273 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6274 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6276 set_syntax_error (_("invalid addressing mode"));
6279 info
->qualifier
= offset_qualifier
;
6282 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6283 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6284 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6285 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6286 /* [Z<n>.<T>{, #imm}] */
6287 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6288 &offset_qualifier
));
6289 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6290 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6292 set_syntax_error (_("invalid addressing mode"));
6295 info
->qualifier
= base_qualifier
;
6298 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6299 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6300 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6301 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6302 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6306 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6308 here since we get better error messages by leaving it to
6309 the qualifier checking routines. */
6310 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6311 &offset_qualifier
));
6312 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6313 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6314 || offset_qualifier
!= base_qualifier
)
6316 set_syntax_error (_("invalid addressing mode"));
6319 info
->qualifier
= base_qualifier
;
6322 case AARCH64_OPND_SYSREG
:
6323 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
6326 set_syntax_error (_("unknown or missing system register name"));
6329 inst
.base
.operands
[i
].sysreg
= val
;
6332 case AARCH64_OPND_PSTATEFIELD
:
6333 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
6336 set_syntax_error (_("unknown or missing PSTATE field name"));
6339 inst
.base
.operands
[i
].pstatefield
= val
;
6342 case AARCH64_OPND_SYSREG_IC
:
6343 inst
.base
.operands
[i
].sysins_op
=
6344 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6346 case AARCH64_OPND_SYSREG_DC
:
6347 inst
.base
.operands
[i
].sysins_op
=
6348 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6350 case AARCH64_OPND_SYSREG_AT
:
6351 inst
.base
.operands
[i
].sysins_op
=
6352 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6354 case AARCH64_OPND_SYSREG_TLBI
:
6355 inst
.base
.operands
[i
].sysins_op
=
6356 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6358 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6360 set_fatal_syntax_error ( _("unknown or missing operation name"));
6365 case AARCH64_OPND_BARRIER
:
6366 case AARCH64_OPND_BARRIER_ISB
:
6367 val
= parse_barrier (&str
);
6368 if (val
!= PARSE_FAIL
6369 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6371 /* ISB only accepts options name 'sy'. */
6373 (_("the specified option is not accepted in ISB"));
6374 /* Turn off backtrack as this optional operand is present. */
6378 /* This is an extension to accept a 0..15 immediate. */
6379 if (val
== PARSE_FAIL
)
6380 po_imm_or_fail (0, 15);
6381 info
->barrier
= aarch64_barrier_options
+ val
;
6384 case AARCH64_OPND_PRFOP
:
6385 val
= parse_pldop (&str
);
6386 /* This is an extension to accept a 0..31 immediate. */
6387 if (val
== PARSE_FAIL
)
6388 po_imm_or_fail (0, 31);
6389 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6392 case AARCH64_OPND_BARRIER_PSB
:
6393 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6394 if (val
== PARSE_FAIL
)
6399 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6402 /* If we get here, this operand was successfully parsed. */
6403 inst
.base
.operands
[i
].present
= 1;
6407 /* The parse routine should already have set the error, but in case
6408 not, set a default one here. */
6410 set_default_error ();
6412 if (! backtrack_pos
)
6413 goto parse_operands_return
;
6416 /* We reach here because this operand is marked as optional, and
6417 either no operand was supplied or the operand was supplied but it
6418 was syntactically incorrect. In the latter case we report an
6419 error. In the former case we perform a few more checks before
6420 dropping through to the code to insert the default operand. */
6422 char *tmp
= backtrack_pos
;
6423 char endchar
= END_OF_INSN
;
6425 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6427 skip_past_char (&tmp
, ',');
6429 if (*tmp
!= endchar
)
6430 /* The user has supplied an operand in the wrong format. */
6431 goto parse_operands_return
;
6433 /* Make sure there is not a comma before the optional operand.
6434 For example the fifth operand of 'sys' is optional:
6436 sys #0,c0,c0,#0, <--- wrong
6437 sys #0,c0,c0,#0 <--- correct. */
6438 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6440 set_fatal_syntax_error
6441 (_("unexpected comma before the omitted optional operand"));
6442 goto parse_operands_return
;
6446 /* Reaching here means we are dealing with an optional operand that is
6447 omitted from the assembly line. */
6448 gas_assert (optional_operand_p (opcode
, i
));
6450 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6452 /* Try again, skipping the optional operand at backtrack_pos. */
6453 str
= backtrack_pos
;
6456 /* Clear any error record after the omitted optional operand has been
6457 successfully handled. */
6461 /* Check if we have parsed all the operands. */
6462 if (*str
!= '\0' && ! error_p ())
6464 /* Set I to the index of the last present operand; this is
6465 for the purpose of diagnostics. */
6466 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6468 set_fatal_syntax_error
6469 (_("unexpected characters following instruction"));
6472 parse_operands_return
:
6476 DEBUG_TRACE ("parsing FAIL: %s - %s",
6477 operand_mismatch_kind_names
[get_error_kind ()],
6478 get_error_message ());
6479 /* Record the operand error properly; this is useful when there
6480 are multiple instruction templates for a mnemonic name, so that
6481 later on, we can select the error that most closely describes
6483 record_operand_error (opcode
, i
, get_error_kind (),
6484 get_error_message ());
6489 DEBUG_TRACE ("parsing SUCCESS");
6494 /* It does some fix-up to provide some programmer friendly feature while
6495 keeping the libopcodes happy, i.e. libopcodes only accepts
6496 the preferred architectural syntax.
6497 Return FALSE if there is any failure; otherwise return TRUE. */
6500 programmer_friendly_fixup (aarch64_instruction
*instr
)
6502 aarch64_inst
*base
= &instr
->base
;
6503 const aarch64_opcode
*opcode
= base
->opcode
;
6504 enum aarch64_op op
= opcode
->op
;
6505 aarch64_opnd_info
*operands
= base
->operands
;
6507 DEBUG_TRACE ("enter");
6509 switch (opcode
->iclass
)
6512 /* TBNZ Xn|Wn, #uimm6, label
6513 Test and Branch Not Zero: conditionally jumps to label if bit number
6514 uimm6 in register Xn is not zero. The bit number implies the width of
6515 the register, which may be written and should be disassembled as Wn if
6516 uimm is less than 32. */
6517 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6519 if (operands
[1].imm
.value
>= 32)
6521 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6525 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6529 /* LDR Wt, label | =value
6530 As a convenience assemblers will typically permit the notation
6531 "=value" in conjunction with the pc-relative literal load instructions
6532 to automatically place an immediate value or symbolic address in a
6533 nearby literal pool and generate a hidden label which references it.
6534 ISREG has been set to 0 in the case of =value. */
6535 if (instr
->gen_lit_pool
6536 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6538 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6539 if (op
== OP_LDRSW_LIT
)
6541 if (instr
->reloc
.exp
.X_op
!= O_constant
6542 && instr
->reloc
.exp
.X_op
!= O_big
6543 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6545 record_operand_error (opcode
, 1,
6546 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6547 _("constant expression expected"));
6550 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6552 record_operand_error (opcode
, 1,
6553 AARCH64_OPDE_OTHER_ERROR
,
6554 _("literal pool insertion failed"));
6562 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6563 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6564 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6565 A programmer-friendly assembler should accept a destination Xd in
6566 place of Wd, however that is not the preferred form for disassembly.
6568 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6569 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6570 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6571 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6576 /* In the 64-bit form, the final register operand is written as Wm
6577 for all but the (possibly omitted) UXTX/LSL and SXTX
6579 As a programmer-friendly assembler, we accept e.g.
6580 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6581 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6582 int idx
= aarch64_operand_index (opcode
->operands
,
6583 AARCH64_OPND_Rm_EXT
);
6584 gas_assert (idx
== 1 || idx
== 2);
6585 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6586 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6587 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6588 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6589 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6590 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6598 DEBUG_TRACE ("exit with SUCCESS");
6602 /* Check for loads and stores that will cause unpredictable behavior. */
6605 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6607 aarch64_inst
*base
= &instr
->base
;
6608 const aarch64_opcode
*opcode
= base
->opcode
;
6609 const aarch64_opnd_info
*opnds
= base
->operands
;
6610 switch (opcode
->iclass
)
6617 /* Loading/storing the base register is unpredictable if writeback. */
6618 if ((aarch64_get_operand_class (opnds
[0].type
)
6619 == AARCH64_OPND_CLASS_INT_REG
)
6620 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6621 && opnds
[1].addr
.base_regno
!= REG_SP
6622 && opnds
[1].addr
.writeback
)
6623 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6626 case ldstnapair_offs
:
6627 case ldstpair_indexed
:
6628 /* Loading/storing the base register is unpredictable if writeback. */
6629 if ((aarch64_get_operand_class (opnds
[0].type
)
6630 == AARCH64_OPND_CLASS_INT_REG
)
6631 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6632 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6633 && opnds
[2].addr
.base_regno
!= REG_SP
6634 && opnds
[2].addr
.writeback
)
6635 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6636 /* Load operations must load different registers. */
6637 if ((opcode
->opcode
& (1 << 22))
6638 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6639 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6646 /* A wrapper function to interface with libopcodes on encoding and
6647 record the error message if there is any.
6649 Return TRUE on success; otherwise return FALSE. */
6652 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6655 aarch64_operand_error error_info
;
6656 error_info
.kind
= AARCH64_OPDE_NIL
;
6657 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
6661 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6662 record_operand_error_info (opcode
, &error_info
);
6667 #ifdef DEBUG_AARCH64
6669 dump_opcode_operands (const aarch64_opcode
*opcode
)
6672 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6674 aarch64_verbose ("\t\t opnd%d: %s", i
,
6675 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6676 ? aarch64_get_operand_name (opcode
->operands
[i
])
6677 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6681 #endif /* DEBUG_AARCH64 */
6683 /* This is the guts of the machine-dependent assembler. STR points to a
6684 machine dependent instruction. This function is supposed to emit
6685 the frags/bytes it assembles to. */
6688 md_assemble (char *str
)
6691 templates
*template;
6692 aarch64_opcode
*opcode
;
6693 aarch64_inst
*inst_base
;
6694 unsigned saved_cond
;
6696 /* Align the previous label if needed. */
6697 if (last_label_seen
!= NULL
)
6699 symbol_set_frag (last_label_seen
, frag_now
);
6700 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6701 S_SET_SEGMENT (last_label_seen
, now_seg
);
6704 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6706 DEBUG_TRACE ("\n\n");
6707 DEBUG_TRACE ("==============================");
6708 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6710 template = opcode_lookup (&p
);
6713 /* It wasn't an instruction, but it might be a register alias of
6714 the form alias .req reg directive. */
6715 if (!create_register_alias (str
, p
))
6716 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6721 skip_whitespace (p
);
6724 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6725 get_mnemonic_name (str
), str
);
6729 init_operand_error_report ();
6731 /* Sections are assumed to start aligned. In executable section, there is no
6732 MAP_DATA symbol pending. So we only align the address during
6733 MAP_DATA --> MAP_INSN transition.
6734 For other sections, this is not guaranteed. */
6735 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6736 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6737 frag_align_code (2, 0);
6739 saved_cond
= inst
.cond
;
6740 reset_aarch64_instruction (&inst
);
6741 inst
.cond
= saved_cond
;
6743 /* Iterate through all opcode entries with the same mnemonic name. */
6746 opcode
= template->opcode
;
6748 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6749 #ifdef DEBUG_AARCH64
6751 dump_opcode_operands (opcode
);
6752 #endif /* DEBUG_AARCH64 */
6754 mapping_state (MAP_INSN
);
6756 inst_base
= &inst
.base
;
6757 inst_base
->opcode
= opcode
;
6759 /* Truly conditionally executed instructions, e.g. b.cond. */
6760 if (opcode
->flags
& F_COND
)
6762 gas_assert (inst
.cond
!= COND_ALWAYS
);
6763 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6764 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6766 else if (inst
.cond
!= COND_ALWAYS
)
6768 /* It shouldn't arrive here, where the assembly looks like a
6769 conditional instruction but the found opcode is unconditional. */
6774 if (parse_operands (p
, opcode
)
6775 && programmer_friendly_fixup (&inst
)
6776 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6778 /* Check that this instruction is supported for this CPU. */
6779 if (!opcode
->avariant
6780 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6782 as_bad (_("selected processor does not support `%s'"), str
);
6786 warn_unpredictable_ldst (&inst
, str
);
6788 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6789 || !inst
.reloc
.need_libopcodes_p
)
6793 /* If there is relocation generated for the instruction,
6794 store the instruction information for the future fix-up. */
6795 struct aarch64_inst
*copy
;
6796 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6797 copy
= XNEW (struct aarch64_inst
);
6798 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6804 template = template->next
;
6805 if (template != NULL
)
6807 reset_aarch64_instruction (&inst
);
6808 inst
.cond
= saved_cond
;
6811 while (template != NULL
);
6813 /* Issue the error messages if any. */
6814 output_operand_error_report (str
);
6817 /* Various frobbings of labels and their addresses. */
6820 aarch64_start_line_hook (void)
6822 last_label_seen
= NULL
;
6826 aarch64_frob_label (symbolS
* sym
)
6828 last_label_seen
= sym
;
6830 dwarf2_emit_label (sym
);
6834 aarch64_data_in_code (void)
6836 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6838 *input_line_pointer
= '/';
6839 input_line_pointer
+= 5;
6840 *input_line_pointer
= 0;
6848 aarch64_canonicalize_symbol_name (char *name
)
6852 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6853 *(name
+ len
- 5) = 0;
6858 /* Table of all register names defined by default. The user can
6859 define additional names with .req. Note that all register names
6860 should appear in both upper and lowercase variants. Some registers
6861 also have mixed-case names. */
6863 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6864 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
6865 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6866 #define REGSET16(p,t) \
6867 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6868 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6869 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6870 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6871 #define REGSET31(p,t) \
6873 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6874 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6875 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6876 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6877 #define REGSET(p,t) \
6878 REGSET31(p,t), REGNUM(p,31,t)
6880 /* These go into aarch64_reg_hsh hash-table. */
6881 static const reg_entry reg_names
[] = {
6882 /* Integer registers. */
6883 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6884 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6886 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
6887 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
6888 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
6889 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
6890 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6891 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6893 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6894 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6896 /* Floating-point single precision registers. */
6897 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6899 /* Floating-point double precision registers. */
6900 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6902 /* Floating-point half precision registers. */
6903 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6905 /* Floating-point byte precision registers. */
6906 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6908 /* Floating-point quad precision registers. */
6909 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6911 /* FP/SIMD registers. */
6912 REGSET (v
, VN
), REGSET (V
, VN
),
6914 /* SVE vector registers. */
6915 REGSET (z
, ZN
), REGSET (Z
, ZN
),
6917 /* SVE predicate registers. */
6918 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
6936 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6937 static const asm_nzcv nzcv_names
[] = {
6938 {"nzcv", B (n
, z
, c
, v
)},
6939 {"nzcV", B (n
, z
, c
, V
)},
6940 {"nzCv", B (n
, z
, C
, v
)},
6941 {"nzCV", B (n
, z
, C
, V
)},
6942 {"nZcv", B (n
, Z
, c
, v
)},
6943 {"nZcV", B (n
, Z
, c
, V
)},
6944 {"nZCv", B (n
, Z
, C
, v
)},
6945 {"nZCV", B (n
, Z
, C
, V
)},
6946 {"Nzcv", B (N
, z
, c
, v
)},
6947 {"NzcV", B (N
, z
, c
, V
)},
6948 {"NzCv", B (N
, z
, C
, v
)},
6949 {"NzCV", B (N
, z
, C
, V
)},
6950 {"NZcv", B (N
, Z
, c
, v
)},
6951 {"NZcV", B (N
, Z
, c
, V
)},
6952 {"NZCv", B (N
, Z
, C
, v
)},
6953 {"NZCV", B (N
, Z
, C
, V
)}
6966 /* MD interface: bits in the object file. */
6968 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6969 for use in the a.out file, and stores them in the array pointed to by buf.
6970 This knows about the endian-ness of the target machine and does
6971 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6972 2 (short) and 4 (long) Floating numbers are put out as a series of
6973 LITTLENUMS (shorts, here at least). */
6976 md_number_to_chars (char *buf
, valueT val
, int n
)
6978 if (target_big_endian
)
6979 number_to_chars_bigendian (buf
, val
, n
);
6981 number_to_chars_littleendian (buf
, val
, n
);
6984 /* MD interface: Sections. */
6986 /* Estimate the size of a frag before relaxing. Assume everything fits in
6990 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6996 /* Round up a section size to the appropriate boundary. */
6999 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7004 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7005 of an rs_align_code fragment.
7007 Here we fill the frag with the appropriate info for padding the
7008 output stream. The resulting frag will consist of a fixed (fr_fix)
7009 and of a repeating (fr_var) part.
7011 The fixed content is always emitted before the repeating content and
7012 these two parts are used as follows in constructing the output:
7013 - the fixed part will be used to align to a valid instruction word
7014 boundary, in case that we start at a misaligned address; as no
7015 executable instruction can live at the misaligned location, we
7016 simply fill with zeros;
7017 - the variable part will be used to cover the remaining padding and
7018 we fill using the AArch64 NOP instruction.
7020 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7021 enough storage space for up to 3 bytes for padding the back to a valid
7022 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7025 aarch64_handle_align (fragS
* fragP
)
7027 /* NOP = d503201f */
7028 /* AArch64 instructions are always little-endian. */
7029 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7031 int bytes
, fix
, noop_size
;
7034 if (fragP
->fr_type
!= rs_align_code
)
7037 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7038 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7041 gas_assert (fragP
->tc_frag_data
.recorded
);
7044 noop_size
= sizeof (aarch64_noop
);
7046 fix
= bytes
& (noop_size
- 1);
7050 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7054 fragP
->fr_fix
+= fix
;
7058 memcpy (p
, aarch64_noop
, noop_size
);
7059 fragP
->fr_var
= noop_size
;
7062 /* Perform target specific initialisation of a frag.
7063 Note - despite the name this initialisation is not done when the frag
7064 is created, but only when its type is assigned. A frag can be created
7065 and used a long time before its type is set, so beware of assuming that
7066 this initialisation is performed first. */
7070 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7071 int max_chars ATTRIBUTE_UNUSED
)
7075 #else /* OBJ_ELF is defined. */
7077 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7079 /* Record a mapping symbol for alignment frags. We will delete this
7080 later if the alignment ends up empty. */
7081 if (!fragP
->tc_frag_data
.recorded
)
7082 fragP
->tc_frag_data
.recorded
= 1;
7084 /* PR 21809: Do not set a mapping state for debug sections
7085 - it just confuses other tools. */
7086 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
7089 switch (fragP
->fr_type
)
7093 mapping_state_2 (MAP_DATA
, max_chars
);
7096 /* PR 20364: We can get alignment frags in code sections,
7097 so do not just assume that we should use the MAP_DATA state. */
7098 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7101 mapping_state_2 (MAP_INSN
, max_chars
);
7108 /* Initialize the DWARF-2 unwind information for this procedure. */
7111 tc_aarch64_frame_initial_instructions (void)
7113 cfi_add_CFA_def_cfa (REG_SP
, 0);
7115 #endif /* OBJ_ELF */
7117 /* Convert REGNAME to a DWARF-2 register number. */
7120 tc_aarch64_regname_to_dw2regnum (char *regname
)
7122 const reg_entry
*reg
= parse_reg (®name
);
7128 case REG_TYPE_SP_32
:
7129 case REG_TYPE_SP_64
:
7139 return reg
->number
+ 64;
7147 /* Implement DWARF2_ADDR_SIZE. */
7150 aarch64_dwarf2_addr_size (void)
7152 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7156 return bfd_arch_bits_per_address (stdoutput
) / 8;
7159 /* MD interface: Symbol and relocation handling. */
7161 /* Return the address within the segment that a PC-relative fixup is
7162 relative to. For AArch64 PC-relative fixups applied to instructions
7163 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7166 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7168 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7170 /* If this is pc-relative and we are going to emit a relocation
7171 then we just want to put out any pipeline compensation that the linker
7172 will need. Otherwise we want to use the calculated base. */
7174 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7175 || aarch64_force_relocation (fixP
)))
7178 /* AArch64 should be consistent for all pc-relative relocations. */
7179 return base
+ AARCH64_PCREL_OFFSET
;
7182 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7183 Otherwise we have no need to default values of symbols. */
7186 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7189 if (name
[0] == '_' && name
[1] == 'G'
7190 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7194 if (symbol_find (name
))
7195 as_bad (_("GOT already in the symbol table"));
7197 GOT_symbol
= symbol_new (name
, undefined_section
,
7198 (valueT
) 0, &zero_address_frag
);
7208 /* Return non-zero if the indicated VALUE has overflowed the maximum
7209 range expressible by a unsigned number with the indicated number of
7213 unsigned_overflow (valueT value
, unsigned bits
)
7216 if (bits
>= sizeof (valueT
) * 8)
7218 lim
= (valueT
) 1 << bits
;
7219 return (value
>= lim
);
7223 /* Return non-zero if the indicated VALUE has overflowed the maximum
7224 range expressible by an signed number with the indicated number of
7228 signed_overflow (offsetT value
, unsigned bits
)
7231 if (bits
>= sizeof (offsetT
) * 8)
7233 lim
= (offsetT
) 1 << (bits
- 1);
7234 return (value
< -lim
|| value
>= lim
);
7237 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7238 unsigned immediate offset load/store instruction, try to encode it as
7239 an unscaled, 9-bit, signed immediate offset load/store instruction.
7240 Return TRUE if it is successful; otherwise return FALSE.
7242 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7243 in response to the standard LDR/STR mnemonics when the immediate offset is
7244 unambiguous, i.e. when it is negative or unaligned. */
7247 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7250 enum aarch64_op new_op
;
7251 const aarch64_opcode
*new_opcode
;
7253 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7255 switch (instr
->opcode
->op
)
7257 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7258 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7259 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7260 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7261 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7262 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7263 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7264 case OP_STR_POS
: new_op
= OP_STUR
; break;
7265 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7266 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7267 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7268 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7269 default: new_op
= OP_NIL
; break;
7272 if (new_op
== OP_NIL
)
7275 new_opcode
= aarch64_get_opcode (new_op
);
7276 gas_assert (new_opcode
!= NULL
);
7278 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7279 instr
->opcode
->op
, new_opcode
->op
);
7281 aarch64_replace_opcode (instr
, new_opcode
);
7283 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7284 qualifier matching may fail because the out-of-date qualifier will
7285 prevent the operand being updated with a new and correct qualifier. */
7286 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7287 AARCH64_OPND_ADDR_SIMM9
);
7288 gas_assert (idx
== 1);
7289 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7291 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7293 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
7299 /* Called by fix_insn to fix a MOV immediate alias instruction.
7301 Operand for a generic move immediate instruction, which is an alias
7302 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7303 a 32-bit/64-bit immediate value into general register. An assembler error
7304 shall result if the immediate cannot be created by a single one of these
7305 instructions. If there is a choice, then to ensure reversability an
7306 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7309 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7311 const aarch64_opcode
*opcode
;
7313 /* Need to check if the destination is SP/ZR. The check has to be done
7314 before any aarch64_replace_opcode. */
7315 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7316 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7318 instr
->operands
[1].imm
.value
= value
;
7319 instr
->operands
[1].skip
= 0;
7323 /* Try the MOVZ alias. */
7324 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7325 aarch64_replace_opcode (instr
, opcode
);
7326 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7327 &instr
->value
, NULL
, NULL
))
7329 put_aarch64_insn (buf
, instr
->value
);
7332 /* Try the MOVK alias. */
7333 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7334 aarch64_replace_opcode (instr
, opcode
);
7335 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7336 &instr
->value
, NULL
, NULL
))
7338 put_aarch64_insn (buf
, instr
->value
);
7343 if (try_mov_bitmask_p
)
7345 /* Try the ORR alias. */
7346 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7347 aarch64_replace_opcode (instr
, opcode
);
7348 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7349 &instr
->value
, NULL
, NULL
))
7351 put_aarch64_insn (buf
, instr
->value
);
7356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7357 _("immediate cannot be moved by a single instruction"));
7360 /* An instruction operand which is immediate related may have symbol used
7361 in the assembly, e.g.
7364 .set u32, 0x00ffff00
7366 At the time when the assembly instruction is parsed, a referenced symbol,
7367 like 'u32' in the above example may not have been seen; a fixS is created
7368 in such a case and is handled here after symbols have been resolved.
7369 Instruction is fixed up with VALUE using the information in *FIXP plus
7370 extra information in FLAGS.
7372 This function is called by md_apply_fix to fix up instructions that need
7373 a fix-up described above but does not involve any linker-time relocation. */
7376 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7380 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7381 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7382 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7386 /* Now the instruction is about to be fixed-up, so the operand that
7387 was previously marked as 'ignored' needs to be unmarked in order
7388 to get the encoding done properly. */
7389 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7390 new_inst
->operands
[idx
].skip
= 0;
7393 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7397 case AARCH64_OPND_EXCEPTION
:
7398 if (unsigned_overflow (value
, 16))
7399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7400 _("immediate out of range"));
7401 insn
= get_aarch64_insn (buf
);
7402 insn
|= encode_svc_imm (value
);
7403 put_aarch64_insn (buf
, insn
);
7406 case AARCH64_OPND_AIMM
:
7407 /* ADD or SUB with immediate.
7408 NOTE this assumes we come here with a add/sub shifted reg encoding
7409 3 322|2222|2 2 2 21111 111111
7410 1 098|7654|3 2 1 09876 543210 98765 43210
7411 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7412 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7413 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7414 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7416 3 322|2222|2 2 221111111111
7417 1 098|7654|3 2 109876543210 98765 43210
7418 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7419 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7420 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7421 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7422 Fields sf Rn Rd are already set. */
7423 insn
= get_aarch64_insn (buf
);
7427 insn
= reencode_addsub_switch_add_sub (insn
);
7431 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7432 && unsigned_overflow (value
, 12))
7434 /* Try to shift the value by 12 to make it fit. */
7435 if (((value
>> 12) << 12) == value
7436 && ! unsigned_overflow (value
, 12 + 12))
7439 insn
|= encode_addsub_imm_shift_amount (1);
7443 if (unsigned_overflow (value
, 12))
7444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7445 _("immediate out of range"));
7447 insn
|= encode_addsub_imm (value
);
7449 put_aarch64_insn (buf
, insn
);
7452 case AARCH64_OPND_SIMD_IMM
:
7453 case AARCH64_OPND_SIMD_IMM_SFT
:
7454 case AARCH64_OPND_LIMM
:
7455 /* Bit mask immediate. */
7456 gas_assert (new_inst
!= NULL
);
7457 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7458 new_inst
->operands
[idx
].imm
.value
= value
;
7459 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7460 &new_inst
->value
, NULL
, NULL
))
7461 put_aarch64_insn (buf
, new_inst
->value
);
7463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7464 _("invalid immediate"));
7467 case AARCH64_OPND_HALF
:
7468 /* 16-bit unsigned immediate. */
7469 if (unsigned_overflow (value
, 16))
7470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7471 _("immediate out of range"));
7472 insn
= get_aarch64_insn (buf
);
7473 insn
|= encode_movw_imm (value
& 0xffff);
7474 put_aarch64_insn (buf
, insn
);
7477 case AARCH64_OPND_IMM_MOV
:
7478 /* Operand for a generic move immediate instruction, which is
7479 an alias instruction that generates a single MOVZ, MOVN or ORR
7480 instruction to loads a 32-bit/64-bit immediate value into general
7481 register. An assembler error shall result if the immediate cannot be
7482 created by a single one of these instructions. If there is a choice,
7483 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7484 and MOVZ or MOVN to ORR. */
7485 gas_assert (new_inst
!= NULL
);
7486 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7489 case AARCH64_OPND_ADDR_SIMM7
:
7490 case AARCH64_OPND_ADDR_SIMM9
:
7491 case AARCH64_OPND_ADDR_SIMM9_2
:
7492 case AARCH64_OPND_ADDR_SIMM10
:
7493 case AARCH64_OPND_ADDR_UIMM12
:
7494 /* Immediate offset in an address. */
7495 insn
= get_aarch64_insn (buf
);
7497 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7498 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7499 || new_inst
->opcode
->operands
[2] == opnd
);
7501 /* Get the index of the address operand. */
7502 if (new_inst
->opcode
->operands
[1] == opnd
)
7503 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7506 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7509 /* Update the resolved offset value. */
7510 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7512 /* Encode/fix-up. */
7513 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7514 &new_inst
->value
, NULL
, NULL
))
7516 put_aarch64_insn (buf
, new_inst
->value
);
7519 else if (new_inst
->opcode
->iclass
== ldst_pos
7520 && try_to_encode_as_unscaled_ldst (new_inst
))
7522 put_aarch64_insn (buf
, new_inst
->value
);
7526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7527 _("immediate offset out of range"));
7532 as_fatal (_("unhandled operand code %d"), opnd
);
7536 /* Apply a fixup (fixP) to segment data, once it has been determined
7537 by our caller that we have all the info we need to fix it up.
7539 Parameter valP is the pointer to the value of the bits. */
7542 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7544 offsetT value
= *valP
;
7546 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7548 unsigned flags
= fixP
->fx_addnumber
;
7550 DEBUG_TRACE ("\n\n");
7551 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7552 DEBUG_TRACE ("Enter md_apply_fix");
7554 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7556 /* Note whether this will delete the relocation. */
7558 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7561 /* Process the relocations. */
7562 switch (fixP
->fx_r_type
)
7564 case BFD_RELOC_NONE
:
7565 /* This will need to go in the object file. */
7570 case BFD_RELOC_8_PCREL
:
7571 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7572 md_number_to_chars (buf
, value
, 1);
7576 case BFD_RELOC_16_PCREL
:
7577 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7578 md_number_to_chars (buf
, value
, 2);
7582 case BFD_RELOC_32_PCREL
:
7583 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7584 md_number_to_chars (buf
, value
, 4);
7588 case BFD_RELOC_64_PCREL
:
7589 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7590 md_number_to_chars (buf
, value
, 8);
7593 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7594 /* We claim that these fixups have been processed here, even if
7595 in fact we generate an error because we do not have a reloc
7596 for them, so tc_gen_reloc() will reject them. */
7598 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7601 _("undefined symbol %s used as an immediate value"),
7602 S_GET_NAME (fixP
->fx_addsy
));
7603 goto apply_fix_return
;
7605 fix_insn (fixP
, flags
, value
);
7608 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7609 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7613 _("pc-relative load offset not word aligned"));
7614 if (signed_overflow (value
, 21))
7615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7616 _("pc-relative load offset out of range"));
7617 insn
= get_aarch64_insn (buf
);
7618 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7619 put_aarch64_insn (buf
, insn
);
7623 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7624 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7626 if (signed_overflow (value
, 21))
7627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7628 _("pc-relative address offset out of range"));
7629 insn
= get_aarch64_insn (buf
);
7630 insn
|= encode_adr_imm (value
);
7631 put_aarch64_insn (buf
, insn
);
7635 case BFD_RELOC_AARCH64_BRANCH19
:
7636 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7639 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7640 _("conditional branch target not word aligned"));
7641 if (signed_overflow (value
, 21))
7642 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7643 _("conditional branch out of range"));
7644 insn
= get_aarch64_insn (buf
);
7645 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7646 put_aarch64_insn (buf
, insn
);
7650 case BFD_RELOC_AARCH64_TSTBR14
:
7651 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7655 _("conditional branch target not word aligned"));
7656 if (signed_overflow (value
, 16))
7657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7658 _("conditional branch out of range"));
7659 insn
= get_aarch64_insn (buf
);
7660 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7661 put_aarch64_insn (buf
, insn
);
7665 case BFD_RELOC_AARCH64_CALL26
:
7666 case BFD_RELOC_AARCH64_JUMP26
:
7667 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7671 _("branch target not word aligned"));
7672 if (signed_overflow (value
, 28))
7673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7674 _("branch out of range"));
7675 insn
= get_aarch64_insn (buf
);
7676 insn
|= encode_branch_ofs_26 (value
>> 2);
7677 put_aarch64_insn (buf
, insn
);
7681 case BFD_RELOC_AARCH64_MOVW_G0
:
7682 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7683 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7684 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7685 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7686 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7689 case BFD_RELOC_AARCH64_MOVW_G1
:
7690 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7691 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7692 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7693 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7694 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7697 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7699 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7700 /* Should always be exported to object file, see
7701 aarch64_force_relocation(). */
7702 gas_assert (!fixP
->fx_done
);
7703 gas_assert (seg
->use_rela_p
);
7705 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7707 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7708 /* Should always be exported to object file, see
7709 aarch64_force_relocation(). */
7710 gas_assert (!fixP
->fx_done
);
7711 gas_assert (seg
->use_rela_p
);
7713 case BFD_RELOC_AARCH64_MOVW_G2
:
7714 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7715 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7716 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7717 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
7720 case BFD_RELOC_AARCH64_MOVW_G3
:
7721 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
7724 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7726 insn
= get_aarch64_insn (buf
);
7730 /* REL signed addend must fit in 16 bits */
7731 if (signed_overflow (value
, 16))
7732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7733 _("offset out of range"));
7737 /* Check for overflow and scale. */
7738 switch (fixP
->fx_r_type
)
7740 case BFD_RELOC_AARCH64_MOVW_G0
:
7741 case BFD_RELOC_AARCH64_MOVW_G1
:
7742 case BFD_RELOC_AARCH64_MOVW_G2
:
7743 case BFD_RELOC_AARCH64_MOVW_G3
:
7744 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7745 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7746 if (unsigned_overflow (value
, scale
+ 16))
7747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7748 _("unsigned value out of range"));
7750 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7751 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7752 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7753 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7754 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7755 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7756 /* NOTE: We can only come here with movz or movn. */
7757 if (signed_overflow (value
, scale
+ 16))
7758 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7759 _("signed value out of range"));
7762 /* Force use of MOVN. */
7764 insn
= reencode_movzn_to_movn (insn
);
7768 /* Force use of MOVZ. */
7769 insn
= reencode_movzn_to_movz (insn
);
7773 /* Unchecked relocations. */
7779 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7780 insn
|= encode_movw_imm (value
& 0xffff);
7782 put_aarch64_insn (buf
, insn
);
7786 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7787 fixP
->fx_r_type
= (ilp32_p
7788 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7789 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7790 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7791 /* Should always be exported to object file, see
7792 aarch64_force_relocation(). */
7793 gas_assert (!fixP
->fx_done
);
7794 gas_assert (seg
->use_rela_p
);
7797 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7798 fixP
->fx_r_type
= (ilp32_p
7799 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7800 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
7801 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7802 /* Should always be exported to object file, see
7803 aarch64_force_relocation(). */
7804 gas_assert (!fixP
->fx_done
);
7805 gas_assert (seg
->use_rela_p
);
7808 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
7809 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7810 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7811 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7812 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
7813 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7814 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7815 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7816 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7817 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7818 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7819 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7820 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7821 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7822 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7823 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7824 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7825 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7826 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7827 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7828 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7829 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7830 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7831 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7832 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7833 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7834 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7835 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7836 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7837 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7838 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7839 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7840 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7841 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7842 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7843 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7844 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7845 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7846 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7847 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7848 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7849 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7850 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7851 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7852 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7853 /* Should always be exported to object file, see
7854 aarch64_force_relocation(). */
7855 gas_assert (!fixP
->fx_done
);
7856 gas_assert (seg
->use_rela_p
);
7859 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7860 /* Should always be exported to object file, see
7861 aarch64_force_relocation(). */
7862 fixP
->fx_r_type
= (ilp32_p
7863 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7864 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7865 gas_assert (!fixP
->fx_done
);
7866 gas_assert (seg
->use_rela_p
);
7869 case BFD_RELOC_AARCH64_ADD_LO12
:
7870 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7871 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7872 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7873 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7874 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7875 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7876 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7877 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7878 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7879 case BFD_RELOC_AARCH64_LDST128_LO12
:
7880 case BFD_RELOC_AARCH64_LDST16_LO12
:
7881 case BFD_RELOC_AARCH64_LDST32_LO12
:
7882 case BFD_RELOC_AARCH64_LDST64_LO12
:
7883 case BFD_RELOC_AARCH64_LDST8_LO12
:
7884 /* Should always be exported to object file, see
7885 aarch64_force_relocation(). */
7886 gas_assert (!fixP
->fx_done
);
7887 gas_assert (seg
->use_rela_p
);
7890 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7891 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7892 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7895 case BFD_RELOC_UNUSED
:
7896 /* An error will already have been reported. */
7900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7901 _("unexpected %s fixup"),
7902 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7907 /* Free the allocated the struct aarch64_inst.
7908 N.B. currently there are very limited number of fix-up types actually use
7909 this field, so the impact on the performance should be minimal . */
7910 if (fixP
->tc_fix_data
.inst
!= NULL
)
7911 free (fixP
->tc_fix_data
.inst
);
7916 /* Translate internal representation of relocation info to BFD target
7920 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7923 bfd_reloc_code_real_type code
;
7925 reloc
= XNEW (arelent
);
7927 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7928 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7929 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7933 if (section
->use_rela_p
)
7934 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7936 fixp
->fx_offset
= reloc
->address
;
7938 reloc
->addend
= fixp
->fx_offset
;
7940 code
= fixp
->fx_r_type
;
7945 code
= BFD_RELOC_16_PCREL
;
7950 code
= BFD_RELOC_32_PCREL
;
7955 code
= BFD_RELOC_64_PCREL
;
7962 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7963 if (reloc
->howto
== NULL
)
7965 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7967 ("cannot represent %s relocation in this object file format"),
7968 bfd_get_reloc_code_name (code
));
7975 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7978 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7980 bfd_reloc_code_real_type type
;
7984 FIXME: @@ Should look at CPU word size. */
7991 type
= BFD_RELOC_16
;
7994 type
= BFD_RELOC_32
;
7997 type
= BFD_RELOC_64
;
8000 as_bad (_("cannot do %u-byte relocation"), size
);
8001 type
= BFD_RELOC_UNUSED
;
8005 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8009 aarch64_force_relocation (struct fix
*fixp
)
8011 switch (fixp
->fx_r_type
)
8013 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8014 /* Perform these "immediate" internal relocations
8015 even if the symbol is extern or weak. */
8018 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8019 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8020 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8021 /* Pseudo relocs that need to be fixed up according to
8025 case BFD_RELOC_AARCH64_ADD_LO12
:
8026 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8027 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8028 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8029 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8030 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8031 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8032 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8033 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8034 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8035 case BFD_RELOC_AARCH64_LDST128_LO12
:
8036 case BFD_RELOC_AARCH64_LDST16_LO12
:
8037 case BFD_RELOC_AARCH64_LDST32_LO12
:
8038 case BFD_RELOC_AARCH64_LDST64_LO12
:
8039 case BFD_RELOC_AARCH64_LDST8_LO12
:
8040 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8041 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8042 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8043 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8044 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8045 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8046 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8047 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8048 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8049 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8050 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8051 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8052 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8053 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8054 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8055 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8056 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8057 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8058 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8059 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8060 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8061 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8062 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8063 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8064 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8065 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8066 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8067 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8068 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8069 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8070 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8071 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8072 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8073 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8074 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8075 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8076 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8077 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8078 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8079 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8080 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8081 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8082 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8083 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8084 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8085 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8086 /* Always leave these relocations for the linker. */
8093 return generic_force_reloc (fixp
);
8098 /* Implement md_after_parse_args. This is the earliest time we need to decide
8099 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8102 aarch64_after_parse_args (void)
8104 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8107 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8108 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8109 aarch64_abi
= AARCH64_ABI_ILP32
;
8111 aarch64_abi
= AARCH64_ABI_LP64
;
8115 elf64_aarch64_target_format (void)
8117 if (strcmp (TARGET_OS
, "cloudabi") == 0)
8119 /* FIXME: What to do for ilp32_p ? */
8120 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
8122 if (target_big_endian
)
8123 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8125 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8129 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8131 elf_frob_symbol (symp
, puntp
);
8135 /* MD interface: Finalization. */
8137 /* A good place to do this, although this was probably not intended
8138 for this kind of use. We need to dump the literal pool before
8139 references are made to a null symbol pointer. */
8142 aarch64_cleanup (void)
8146 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8148 /* Put it at the end of the relevant section. */
8149 subseg_set (pool
->section
, pool
->sub_section
);
8155 /* Remove any excess mapping symbols generated for alignment frags in
8156 SEC. We may have created a mapping symbol before a zero byte
8157 alignment; remove it if there's a mapping symbol after the
8160 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8161 void *dummy ATTRIBUTE_UNUSED
)
8163 segment_info_type
*seginfo
= seg_info (sec
);
8166 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8169 for (fragp
= seginfo
->frchainP
->frch_root
;
8170 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8172 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8173 fragS
*next
= fragp
->fr_next
;
8175 /* Variable-sized frags have been converted to fixed size by
8176 this point. But if this was variable-sized to start with,
8177 there will be a fixed-size frag after it. So don't handle
8179 if (sym
== NULL
|| next
== NULL
)
8182 if (S_GET_VALUE (sym
) < next
->fr_address
)
8183 /* Not at the end of this frag. */
8185 know (S_GET_VALUE (sym
) == next
->fr_address
);
8189 if (next
->tc_frag_data
.first_map
!= NULL
)
8191 /* Next frag starts with a mapping symbol. Discard this
8193 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8197 if (next
->fr_next
== NULL
)
8199 /* This mapping symbol is at the end of the section. Discard
8201 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8202 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8206 /* As long as we have empty frags without any mapping symbols,
8208 /* If the next frag is non-empty and does not start with a
8209 mapping symbol, then this mapping symbol is required. */
8210 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8213 next
= next
->fr_next
;
8215 while (next
!= NULL
);
8220 /* Adjust the symbol table. */
8223 aarch64_adjust_symtab (void)
8226 /* Remove any overlapping mapping symbols generated by alignment frags. */
8227 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8228 /* Now do generic ELF adjustments. */
8229 elf_adjust_symtab ();
8234 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8236 const char *hash_err
;
8238 hash_err
= hash_insert (table
, key
, value
);
8240 printf ("Internal Error: Can't hash %s\n", key
);
8244 fill_instruction_hash_table (void)
8246 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8248 while (opcode
->name
!= NULL
)
8250 templates
*templ
, *new_templ
;
8251 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8253 new_templ
= XNEW (templates
);
8254 new_templ
->opcode
= opcode
;
8255 new_templ
->next
= NULL
;
8258 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8261 new_templ
->next
= templ
->next
;
8262 templ
->next
= new_templ
;
8269 convert_to_upper (char *dst
, const char *src
, size_t num
)
8272 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8273 *dst
= TOUPPER (*src
);
8277 /* Assume STR point to a lower-case string, allocate, convert and return
8278 the corresponding upper-case string. */
8279 static inline const char*
8280 get_upper_str (const char *str
)
8283 size_t len
= strlen (str
);
8284 ret
= XNEWVEC (char, len
+ 1);
8285 convert_to_upper (ret
, str
, len
);
8289 /* MD interface: Initialization. */
8297 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8298 || (aarch64_cond_hsh
= hash_new ()) == NULL
8299 || (aarch64_shift_hsh
= hash_new ()) == NULL
8300 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8301 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8302 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8303 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8304 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8305 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8306 || (aarch64_reg_hsh
= hash_new ()) == NULL
8307 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8308 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8309 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8310 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8311 as_fatal (_("virtual memory exhausted"));
8313 fill_instruction_hash_table ();
8315 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8316 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8317 (void *) (aarch64_sys_regs
+ i
));
8319 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8320 checked_hash_insert (aarch64_pstatefield_hsh
,
8321 aarch64_pstatefields
[i
].name
,
8322 (void *) (aarch64_pstatefields
+ i
));
8324 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8325 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8326 aarch64_sys_regs_ic
[i
].name
,
8327 (void *) (aarch64_sys_regs_ic
+ i
));
8329 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8330 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8331 aarch64_sys_regs_dc
[i
].name
,
8332 (void *) (aarch64_sys_regs_dc
+ i
));
8334 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8335 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8336 aarch64_sys_regs_at
[i
].name
,
8337 (void *) (aarch64_sys_regs_at
+ i
));
8339 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8340 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8341 aarch64_sys_regs_tlbi
[i
].name
,
8342 (void *) (aarch64_sys_regs_tlbi
+ i
));
8344 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8345 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8346 (void *) (reg_names
+ i
));
8348 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8349 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8350 (void *) (nzcv_names
+ i
));
8352 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8354 const char *name
= aarch64_operand_modifiers
[i
].name
;
8355 checked_hash_insert (aarch64_shift_hsh
, name
,
8356 (void *) (aarch64_operand_modifiers
+ i
));
8357 /* Also hash the name in the upper case. */
8358 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8359 (void *) (aarch64_operand_modifiers
+ i
));
8362 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8365 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8366 the same condition code. */
8367 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8369 const char *name
= aarch64_conds
[i
].names
[j
];
8372 checked_hash_insert (aarch64_cond_hsh
, name
,
8373 (void *) (aarch64_conds
+ i
));
8374 /* Also hash the name in the upper case. */
8375 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8376 (void *) (aarch64_conds
+ i
));
8380 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8382 const char *name
= aarch64_barrier_options
[i
].name
;
8383 /* Skip xx00 - the unallocated values of option. */
8386 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8387 (void *) (aarch64_barrier_options
+ i
));
8388 /* Also hash the name in the upper case. */
8389 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8390 (void *) (aarch64_barrier_options
+ i
));
8393 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8395 const char* name
= aarch64_prfops
[i
].name
;
8396 /* Skip the unallocated hint encodings. */
8399 checked_hash_insert (aarch64_pldop_hsh
, name
,
8400 (void *) (aarch64_prfops
+ i
));
8401 /* Also hash the name in the upper case. */
8402 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8403 (void *) (aarch64_prfops
+ i
));
8406 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8408 const char* name
= aarch64_hint_options
[i
].name
;
8410 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8411 (void *) (aarch64_hint_options
+ i
));
8412 /* Also hash the name in the upper case. */
8413 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8414 (void *) (aarch64_hint_options
+ i
));
8417 /* Set the cpu variant based on the command-line options. */
8419 mcpu_cpu_opt
= march_cpu_opt
;
8422 mcpu_cpu_opt
= &cpu_default
;
8424 cpu_variant
= *mcpu_cpu_opt
;
8426 /* Record the CPU type. */
8427 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8429 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8432 /* Command line processing. */
8434 const char *md_shortopts
= "m:";
8436 #ifdef AARCH64_BI_ENDIAN
8437 #define OPTION_EB (OPTION_MD_BASE + 0)
8438 #define OPTION_EL (OPTION_MD_BASE + 1)
8440 #if TARGET_BYTES_BIG_ENDIAN
8441 #define OPTION_EB (OPTION_MD_BASE + 0)
8443 #define OPTION_EL (OPTION_MD_BASE + 1)
8447 struct option md_longopts
[] = {
8449 {"EB", no_argument
, NULL
, OPTION_EB
},
8452 {"EL", no_argument
, NULL
, OPTION_EL
},
8454 {NULL
, no_argument
, NULL
, 0}
8457 size_t md_longopts_size
= sizeof (md_longopts
);
8459 struct aarch64_option_table
8461 const char *option
; /* Option name to match. */
8462 const char *help
; /* Help information. */
8463 int *var
; /* Variable to change. */
8464 int value
; /* What to change it to. */
8465 char *deprecated
; /* If non-null, print this message. */
8468 static struct aarch64_option_table aarch64_opts
[] = {
8469 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8470 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8472 #ifdef DEBUG_AARCH64
8473 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8474 #endif /* DEBUG_AARCH64 */
8475 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8477 {"mno-verbose-error", N_("do not output verbose error messages"),
8478 &verbose_error_p
, 0, NULL
},
8479 {NULL
, NULL
, NULL
, 0, NULL
}
8482 struct aarch64_cpu_option_table
8485 const aarch64_feature_set value
;
8486 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8488 const char *canonical_name
;
8491 /* This list should, at a minimum, contain all the cpu names
8492 recognized by GCC. */
8493 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8494 {"all", AARCH64_ANY
, NULL
},
8495 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8496 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8497 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8498 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8499 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8500 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8501 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8502 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8503 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8504 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8505 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8506 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8508 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8509 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8511 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8512 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8513 "Samsung Exynos M1"},
8514 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8515 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8516 | AARCH64_FEATURE_RDMA
),
8518 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8519 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8520 | AARCH64_FEATURE_RDMA
),
8521 "Qualcomm QDF24XX"},
8522 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_3
,
8523 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8524 "Qualcomm Saphira"},
8525 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8526 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8528 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8529 AARCH64_FEATURE_CRYPTO
),
8531 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8532 in earlier releases and is superseded by 'xgene1' in all
8534 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8535 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8536 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8537 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8538 {"generic", AARCH64_ARCH_V8
, NULL
},
8540 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8543 struct aarch64_arch_option_table
8546 const aarch64_feature_set value
;
8549 /* This list should, at a minimum, contain all the architecture names
8550 recognized by GCC. */
8551 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8552 {"all", AARCH64_ANY
},
8553 {"armv8-a", AARCH64_ARCH_V8
},
8554 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8555 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8556 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8557 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8558 {NULL
, AARCH64_ARCH_NONE
}
8561 /* ISA extensions. */
8562 struct aarch64_option_cpu_value_table
8565 const aarch64_feature_set value
;
8566 const aarch64_feature_set require
; /* Feature dependencies. */
8569 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8570 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8572 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8573 | AARCH64_FEATURE_AES
8574 | AARCH64_FEATURE_SHA2
, 0),
8575 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8576 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8578 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8580 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8581 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8582 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8584 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8586 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8588 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8589 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8590 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8591 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8592 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8593 AARCH64_FEATURE (AARCH64_FEATURE_FP
8594 | AARCH64_FEATURE_F16
, 0)},
8595 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8597 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8598 AARCH64_FEATURE (AARCH64_FEATURE_F16
8599 | AARCH64_FEATURE_SIMD
8600 | AARCH64_FEATURE_COMPNUM
, 0)},
8601 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8602 AARCH64_FEATURE (AARCH64_FEATURE_F16
8603 | AARCH64_FEATURE_SIMD
, 0)},
8604 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8606 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8608 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8610 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8612 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8614 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8615 | AARCH64_FEATURE_SHA3
, 0),
8617 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8620 struct aarch64_long_option_table
8622 const char *option
; /* Substring to match. */
8623 const char *help
; /* Help information. */
8624 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8625 char *deprecated
; /* If non-null, print this message. */
8628 /* Transitive closure of features depending on set. */
8629 static aarch64_feature_set
8630 aarch64_feature_disable_set (aarch64_feature_set set
)
8632 const struct aarch64_option_cpu_value_table
*opt
;
8633 aarch64_feature_set prev
= 0;
8635 while (prev
!= set
) {
8637 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8638 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8639 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8644 /* Transitive closure of dependencies of set. */
8645 static aarch64_feature_set
8646 aarch64_feature_enable_set (aarch64_feature_set set
)
8648 const struct aarch64_option_cpu_value_table
*opt
;
8649 aarch64_feature_set prev
= 0;
8651 while (prev
!= set
) {
8653 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8654 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8655 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8661 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8662 bfd_boolean ext_only
)
8664 /* We insist on extensions being added before being removed. We achieve
8665 this by using the ADDING_VALUE variable to indicate whether we are
8666 adding an extension (1) or removing it (0) and only allowing it to
8667 change in the order -1 -> 1 -> 0. */
8668 int adding_value
= -1;
8669 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8671 /* Copy the feature set, so that we can modify it. */
8675 while (str
!= NULL
&& *str
!= 0)
8677 const struct aarch64_option_cpu_value_table
*opt
;
8678 const char *ext
= NULL
;
8685 as_bad (_("invalid architectural extension"));
8689 ext
= strchr (++str
, '+');
8695 optlen
= strlen (str
);
8697 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8699 if (adding_value
!= 0)
8704 else if (optlen
> 0)
8706 if (adding_value
== -1)
8708 else if (adding_value
!= 1)
8710 as_bad (_("must specify extensions to add before specifying "
8711 "those to remove"));
8718 as_bad (_("missing architectural extension"));
8722 gas_assert (adding_value
!= -1);
8724 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8725 if (strncmp (opt
->name
, str
, optlen
) == 0)
8727 aarch64_feature_set set
;
8729 /* Add or remove the extension. */
8732 set
= aarch64_feature_enable_set (opt
->value
);
8733 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8737 set
= aarch64_feature_disable_set (opt
->value
);
8738 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8743 if (opt
->name
== NULL
)
8745 as_bad (_("unknown architectural extension `%s'"), str
);
8756 aarch64_parse_cpu (const char *str
)
8758 const struct aarch64_cpu_option_table
*opt
;
8759 const char *ext
= strchr (str
, '+');
8765 optlen
= strlen (str
);
8769 as_bad (_("missing cpu name `%s'"), str
);
8773 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8774 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8776 mcpu_cpu_opt
= &opt
->value
;
8778 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
8783 as_bad (_("unknown cpu `%s'"), str
);
8788 aarch64_parse_arch (const char *str
)
8790 const struct aarch64_arch_option_table
*opt
;
8791 const char *ext
= strchr (str
, '+');
8797 optlen
= strlen (str
);
8801 as_bad (_("missing architecture name `%s'"), str
);
8805 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8806 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8808 march_cpu_opt
= &opt
->value
;
8810 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8815 as_bad (_("unknown architecture `%s'\n"), str
);
8820 struct aarch64_option_abi_value_table
8823 enum aarch64_abi_type value
;
8826 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8827 {"ilp32", AARCH64_ABI_ILP32
},
8828 {"lp64", AARCH64_ABI_LP64
},
8832 aarch64_parse_abi (const char *str
)
8838 as_bad (_("missing abi name `%s'"), str
);
8842 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8843 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8845 aarch64_abi
= aarch64_abis
[i
].value
;
8849 as_bad (_("unknown abi `%s'\n"), str
);
8853 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8855 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8856 aarch64_parse_abi
, NULL
},
8857 #endif /* OBJ_ELF */
8858 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8859 aarch64_parse_cpu
, NULL
},
8860 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8861 aarch64_parse_arch
, NULL
},
8862 {NULL
, NULL
, 0, NULL
}
8866 md_parse_option (int c
, const char *arg
)
8868 struct aarch64_option_table
*opt
;
8869 struct aarch64_long_option_table
*lopt
;
8875 target_big_endian
= 1;
8881 target_big_endian
= 0;
8886 /* Listing option. Just ignore these, we don't support additional
8891 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8893 if (c
== opt
->option
[0]
8894 && ((arg
== NULL
&& opt
->option
[1] == 0)
8895 || streq (arg
, opt
->option
+ 1)))
8897 /* If the option is deprecated, tell the user. */
8898 if (opt
->deprecated
!= NULL
)
8899 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8900 arg
? arg
: "", _(opt
->deprecated
));
8902 if (opt
->var
!= NULL
)
8903 *opt
->var
= opt
->value
;
8909 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8911 /* These options are expected to have an argument. */
8912 if (c
== lopt
->option
[0]
8914 && strncmp (arg
, lopt
->option
+ 1,
8915 strlen (lopt
->option
+ 1)) == 0)
8917 /* If the option is deprecated, tell the user. */
8918 if (lopt
->deprecated
!= NULL
)
8919 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8920 _(lopt
->deprecated
));
8922 /* Call the sup-option parser. */
8923 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8934 md_show_usage (FILE * fp
)
8936 struct aarch64_option_table
*opt
;
8937 struct aarch64_long_option_table
*lopt
;
8939 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8941 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8942 if (opt
->help
!= NULL
)
8943 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8945 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8946 if (lopt
->help
!= NULL
)
8947 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8951 -EB assemble code for a big-endian cpu\n"));
8956 -EL assemble code for a little-endian cpu\n"));
8960 /* Parse a .cpu directive. */
8963 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8965 const struct aarch64_cpu_option_table
*opt
;
8971 name
= input_line_pointer
;
8972 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8973 input_line_pointer
++;
8974 saved_char
= *input_line_pointer
;
8975 *input_line_pointer
= 0;
8977 ext
= strchr (name
, '+');
8980 optlen
= ext
- name
;
8982 optlen
= strlen (name
);
8984 /* Skip the first "all" entry. */
8985 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8986 if (strlen (opt
->name
) == optlen
8987 && strncmp (name
, opt
->name
, optlen
) == 0)
8989 mcpu_cpu_opt
= &opt
->value
;
8991 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8994 cpu_variant
= *mcpu_cpu_opt
;
8996 *input_line_pointer
= saved_char
;
8997 demand_empty_rest_of_line ();
9000 as_bad (_("unknown cpu `%s'"), name
);
9001 *input_line_pointer
= saved_char
;
9002 ignore_rest_of_line ();
9006 /* Parse a .arch directive. */
9009 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9011 const struct aarch64_arch_option_table
*opt
;
9017 name
= input_line_pointer
;
9018 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9019 input_line_pointer
++;
9020 saved_char
= *input_line_pointer
;
9021 *input_line_pointer
= 0;
9023 ext
= strchr (name
, '+');
9026 optlen
= ext
- name
;
9028 optlen
= strlen (name
);
9030 /* Skip the first "all" entry. */
9031 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9032 if (strlen (opt
->name
) == optlen
9033 && strncmp (name
, opt
->name
, optlen
) == 0)
9035 mcpu_cpu_opt
= &opt
->value
;
9037 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9040 cpu_variant
= *mcpu_cpu_opt
;
9042 *input_line_pointer
= saved_char
;
9043 demand_empty_rest_of_line ();
9047 as_bad (_("unknown architecture `%s'\n"), name
);
9048 *input_line_pointer
= saved_char
;
9049 ignore_rest_of_line ();
9052 /* Parse a .arch_extension directive. */
9055 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9058 char *ext
= input_line_pointer
;;
9060 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9061 input_line_pointer
++;
9062 saved_char
= *input_line_pointer
;
9063 *input_line_pointer
= 0;
9065 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9068 cpu_variant
= *mcpu_cpu_opt
;
9070 *input_line_pointer
= saved_char
;
9071 demand_empty_rest_of_line ();
9074 /* Copy symbol information. */
9077 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9079 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);