1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
410 /* Stuff needed to resolve the label ambiguity
419 static symbolS
*last_label_seen
;
421 /* Literal pool structure. Held on a per-section
422 and per-sub-section basis. */
424 #define MAX_LITERAL_POOL_SIZE 1024
425 typedef struct literal_expression
428 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
429 LITTLENUM_TYPE
* bignum
;
430 } literal_expression
;
432 typedef struct literal_pool
434 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
435 unsigned int next_free_entry
;
441 struct literal_pool
*next
;
444 /* Pointer to a linked list of literal pools. */
445 static literal_pool
*list_of_pools
= NULL
;
449 /* This array holds the chars that always start a comment. If the
450 pre-processor is disabled, these aren't very useful. */
451 const char comment_chars
[] = "";
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output. */
456 /* Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output. */
459 /* Also note that comments like this one will always work. */
460 const char line_comment_chars
[] = "#";
462 const char line_separator_chars
[] = ";";
464 /* Chars that can be used to separate mant
465 from exp in floating point numbers. */
466 const char EXP_CHARS
[] = "eE";
468 /* Chars that mean this number is a floating point constant. */
472 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
474 /* Prefix character that indicates the start of an immediate value. */
475 #define is_immediate_prefix(C) ((C) == '#')
477 /* Separator character handling. */
479 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
481 static inline bfd_boolean
482 skip_past_char (char **str
, char c
)
493 #define skip_past_comma(str) skip_past_char (str, ',')
495 /* Arithmetic expressions (possibly involving symbols). */
497 static bfd_boolean in_my_get_expression_p
= FALSE
;
499 /* Third argument to my_get_expression. */
500 #define GE_NO_PREFIX 0
501 #define GE_OPT_PREFIX 1
503 /* Return TRUE if the string pointed by *STR is successfully parsed
504 as an valid expression; *EP will be filled with the information of
505 such an expression. Otherwise return FALSE. */
508 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
513 int prefix_present_p
= 0;
520 if (is_immediate_prefix (**str
))
523 prefix_present_p
= 1;
530 memset (ep
, 0, sizeof (expressionS
));
532 save_in
= input_line_pointer
;
533 input_line_pointer
= *str
;
534 in_my_get_expression_p
= TRUE
;
535 seg
= expression (ep
);
536 in_my_get_expression_p
= FALSE
;
538 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
540 /* We found a bad expression in md_operand(). */
541 *str
= input_line_pointer
;
542 input_line_pointer
= save_in
;
543 if (prefix_present_p
&& ! error_p ())
544 set_fatal_syntax_error (_("bad expression"));
546 set_first_syntax_error (_("bad expression"));
551 if (seg
!= absolute_section
552 && seg
!= text_section
553 && seg
!= data_section
554 && seg
!= bss_section
&& seg
!= undefined_section
)
556 set_syntax_error (_("bad segment"));
557 *str
= input_line_pointer
;
558 input_line_pointer
= save_in
;
565 *str
= input_line_pointer
;
566 input_line_pointer
= save_in
;
570 /* Turn a string in input_line_pointer into a floating point constant
571 of type TYPE, and store the appropriate bytes in *LITP. The number
572 of LITTLENUMS emitted is stored in *SIZEP. An error message is
573 returned, or NULL on OK. */
576 md_atof (int type
, char *litP
, int *sizeP
)
578 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
581 /* We handle all bad expressions here, so that we can report the faulty
582 instruction in the error message. */
584 md_operand (expressionS
* exp
)
586 if (in_my_get_expression_p
)
587 exp
->X_op
= O_illegal
;
590 /* Immediate values. */
592 /* Errors may be set multiple times during parsing or bit encoding
593 (particularly in the Neon bits), but usually the earliest error which is set
594 will be the most meaningful. Avoid overwriting it with later (cascading)
595 errors by calling this function. */
598 first_error (const char *error
)
601 set_syntax_error (error
);
604 /* Similiar to first_error, but this function accepts formatted error
607 first_error_fmt (const char *format
, ...)
612 /* N.B. this single buffer will not cause error messages for different
613 instructions to pollute each other; this is because at the end of
614 processing of each assembly line, error message if any will be
615 collected by as_bad. */
616 static char buffer
[size
];
620 int ret ATTRIBUTE_UNUSED
;
621 va_start (args
, format
);
622 ret
= vsnprintf (buffer
, size
, format
, args
);
623 know (ret
<= size
- 1 && ret
>= 0);
625 set_syntax_error (buffer
);
629 /* Register parsing. */
631 /* Generic register parser which is called by other specialized
633 CCP points to what should be the beginning of a register name.
634 If it is indeed a valid register name, advance CCP over it and
635 return the reg_entry structure; otherwise return NULL.
636 It does not issue diagnostics. */
639 parse_reg (char **ccp
)
645 #ifdef REGISTER_PREFIX
646 if (*start
!= REGISTER_PREFIX
)
652 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
657 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
659 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
668 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
671 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
673 if (reg
->type
== type
)
678 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
679 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
680 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
681 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
682 case REG_TYPE_VN
: /* Vector register. */
683 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
684 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
685 == reg_type_masks
[reg
->type
]);
687 as_fatal ("unhandled type %d", type
);
692 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
693 Return the register number otherwise. *ISREG32 is set to one if the
694 register is 32-bit wide; *ISREGZERO is set to one if the register is
695 of type Z_32 or Z_64.
696 Note that this function does not issue any diagnostics. */
699 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
700 int *isreg32
, int *isregzero
)
703 const reg_entry
*reg
= parse_reg (&str
);
708 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
717 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
722 *isreg32
= reg
->type
== REG_TYPE_R_32
;
729 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
741 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
742 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
743 otherwise return FALSE.
745 Accept only one occurrence of:
746 8b 16b 4h 8h 2s 4s 1d 2d
749 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
753 unsigned element_size
;
754 enum neon_el_type type
;
764 width
= strtoul (ptr
, &ptr
, 10);
765 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
767 first_error_fmt (_("bad size %d in vector width specifier"), width
);
772 switch (TOLOWER (*ptr
))
800 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
802 first_error (_("missing element size"));
805 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
808 ("invalid element size %d and vector size combination %c"),
814 parsed_type
->type
= type
;
815 parsed_type
->width
= width
;
822 /* Parse a single type, e.g. ".8b", leading period included.
823 Only applicable to Vn registers.
825 Return TRUE on success; otherwise return FALSE. */
827 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
833 if (! parse_neon_type_for_operand (vectype
, &str
))
835 first_error (_("vector type expected"));
847 /* Parse a register of the type TYPE.
849 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
850 name or the parsed register is not of TYPE.
852 Otherwise return the register number, and optionally fill in the actual
853 type of the register in *RTYPE when multiple alternatives were given, and
854 return the register shape and element index information in *TYPEINFO.
856 IN_REG_LIST should be set with TRUE if the caller is parsing a register
860 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
861 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
864 const reg_entry
*reg
= parse_reg (&str
);
865 struct neon_type_el atype
;
866 struct neon_type_el parsetype
;
867 bfd_boolean is_typed_vecreg
= FALSE
;
870 atype
.type
= NT_invtype
;
878 set_default_error ();
882 if (! aarch64_check_reg_type (reg
, type
))
884 DEBUG_TRACE ("reg type check failed");
885 set_default_error ();
890 if (type
== REG_TYPE_VN
891 && parse_neon_operand_type (&parsetype
, &str
))
893 /* Register if of the form Vn.[bhsdq]. */
894 is_typed_vecreg
= TRUE
;
896 if (parsetype
.width
== 0)
897 /* Expect index. In the new scheme we cannot have
898 Vn.[bhsdq] represent a scalar. Therefore any
899 Vn.[bhsdq] should have an index following it.
900 Except in reglists ofcourse. */
901 atype
.defined
|= NTA_HASINDEX
;
903 atype
.defined
|= NTA_HASTYPE
;
905 atype
.type
= parsetype
.type
;
906 atype
.width
= parsetype
.width
;
909 if (skip_past_char (&str
, '['))
913 /* Reject Sn[index] syntax. */
914 if (!is_typed_vecreg
)
916 first_error (_("this type of register can't be indexed"));
920 if (in_reg_list
== TRUE
)
922 first_error (_("index not allowed inside register list"));
926 atype
.defined
|= NTA_HASINDEX
;
928 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
930 if (exp
.X_op
!= O_constant
)
932 first_error (_("constant expression required"));
936 if (! skip_past_char (&str
, ']'))
939 atype
.index
= exp
.X_add_number
;
941 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
943 /* Indexed vector register expected. */
944 first_error (_("indexed vector register expected"));
948 /* A vector reg Vn should be typed or indexed. */
949 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
951 first_error (_("invalid use of vector register"));
967 Return the register number on success; return PARSE_FAIL otherwise.
969 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
970 the register (e.g. NEON double or quad reg when either has been requested).
972 If this is a NEON vector register with additional type information, fill
973 in the struct pointed to by VECTYPE (if non-NULL).
975 This parser does not handle register list. */
978 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
979 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
981 struct neon_type_el atype
;
983 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
984 /*in_reg_list= */ FALSE
);
986 if (reg
== PARSE_FAIL
)
997 static inline bfd_boolean
998 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1002 && e1
.defined
== e2
.defined
1003 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1006 /* This function parses the NEON register list. On success, it returns
1007 the parsed register list information in the following encoded format:
1009 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1010 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1012 The information of the register shape and/or index is returned in
1015 It returns PARSE_FAIL if the register list is invalid.
1017 The list contains one to four registers.
1018 Each register can be one of:
1021 All <T> should be identical.
1022 All <index> should be identical.
1023 There are restrictions on <Vt> numbers which are checked later
1024 (by reg_list_valid_p). */
1027 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1031 struct neon_type_el typeinfo
, typeinfo_first
;
1036 bfd_boolean error
= FALSE
;
1037 bfd_boolean expect_index
= FALSE
;
1041 set_syntax_error (_("expecting {"));
1047 typeinfo_first
.defined
= 0;
1048 typeinfo_first
.type
= NT_invtype
;
1049 typeinfo_first
.width
= -1;
1050 typeinfo_first
.index
= 0;
1059 str
++; /* skip over '-' */
1062 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1063 /*in_reg_list= */ TRUE
);
1064 if (val
== PARSE_FAIL
)
1066 set_first_syntax_error (_("invalid vector register in list"));
1070 /* reject [bhsd]n */
1071 if (typeinfo
.defined
== 0)
1073 set_first_syntax_error (_("invalid scalar register in list"));
1078 if (typeinfo
.defined
& NTA_HASINDEX
)
1079 expect_index
= TRUE
;
1083 if (val
< val_range
)
1085 set_first_syntax_error
1086 (_("invalid range in vector register list"));
1095 typeinfo_first
= typeinfo
;
1096 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1098 set_first_syntax_error
1099 (_("type mismatch in vector register list"));
1104 for (i
= val_range
; i
<= val
; i
++)
1106 ret_val
|= i
<< (5 * nb_regs
);
1111 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1113 skip_whitespace (str
);
1116 set_first_syntax_error (_("end of vector register list not found"));
1121 skip_whitespace (str
);
1125 if (skip_past_char (&str
, '['))
1129 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1130 if (exp
.X_op
!= O_constant
)
1132 set_first_syntax_error (_("constant expression required."));
1135 if (! skip_past_char (&str
, ']'))
1138 typeinfo_first
.index
= exp
.X_add_number
;
1142 set_first_syntax_error (_("expected index"));
1149 set_first_syntax_error (_("too many registers in vector register list"));
1152 else if (nb_regs
== 0)
1154 set_first_syntax_error (_("empty vector register list"));
1160 *vectype
= typeinfo_first
;
1162 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1165 /* Directives: register aliases. */
1168 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1173 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1176 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1179 /* Only warn about a redefinition if it's not defined as the
1181 else if (new->number
!= number
|| new->type
!= type
)
1182 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1187 name
= xstrdup (str
);
1188 new = xmalloc (sizeof (reg_entry
));
1191 new->number
= number
;
1193 new->builtin
= FALSE
;
1195 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1201 /* Look for the .req directive. This is of the form:
1203 new_register_name .req existing_register_name
1205 If we find one, or if it looks sufficiently like one that we want to
1206 handle any error here, return TRUE. Otherwise return FALSE. */
1209 create_register_alias (char *newname
, char *p
)
1211 const reg_entry
*old
;
1212 char *oldname
, *nbuf
;
1215 /* The input scrubber ensures that whitespace after the mnemonic is
1216 collapsed to single spaces. */
1218 if (strncmp (oldname
, " .req ", 6) != 0)
1222 if (*oldname
== '\0')
1225 old
= hash_find (aarch64_reg_hsh
, oldname
);
1228 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1232 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1233 the desired alias name, and p points to its end. If not, then
1234 the desired alias name is in the global original_case_string. */
1235 #ifdef TC_CASE_SENSITIVE
1238 newname
= original_case_string
;
1239 nlen
= strlen (newname
);
1242 nbuf
= alloca (nlen
+ 1);
1243 memcpy (nbuf
, newname
, nlen
);
1246 /* Create aliases under the new name as stated; an all-lowercase
1247 version of the new name; and an all-uppercase version of the new
1249 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1256 /* If this attempt to create an additional alias fails, do not bother
1257 trying to create the all-lower case alias. We will fail and issue
1258 a second, duplicate error message. This situation arises when the
1259 programmer does something like:
1262 The second .req creates the "Foo" alias but then fails to create
1263 the artificial FOO alias because it has already been created by the
1265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1269 for (p
= nbuf
; *p
; p
++)
1272 if (strncmp (nbuf
, newname
, nlen
))
1273 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1279 /* Should never be called, as .req goes between the alias and the
1280 register name, not at the beginning of the line. */
1282 s_req (int a ATTRIBUTE_UNUSED
)
1284 as_bad (_("invalid syntax for .req directive"));
1287 /* The .unreq directive deletes an alias which was previously defined
1288 by .req. For example:
1294 s_unreq (int a ATTRIBUTE_UNUSED
)
1299 name
= input_line_pointer
;
1301 while (*input_line_pointer
!= 0
1302 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1303 ++input_line_pointer
;
1305 saved_char
= *input_line_pointer
;
1306 *input_line_pointer
= 0;
1309 as_bad (_("invalid syntax for .unreq directive"));
1312 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1315 as_bad (_("unknown register alias '%s'"), name
);
1316 else if (reg
->builtin
)
1317 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1324 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1325 free ((char *) reg
->name
);
1328 /* Also locate the all upper case and all lower case versions.
1329 Do not complain if we cannot find one or the other as it
1330 was probably deleted above. */
1332 nbuf
= strdup (name
);
1333 for (p
= nbuf
; *p
; p
++)
1335 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1338 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1339 free ((char *) reg
->name
);
1343 for (p
= nbuf
; *p
; p
++)
1345 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1348 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1349 free ((char *) reg
->name
);
1357 *input_line_pointer
= saved_char
;
1358 demand_empty_rest_of_line ();
1361 /* Directives: Instruction set selection. */
1364 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1365 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1366 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1367 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1369 /* Create a new mapping symbol for the transition to STATE. */
1372 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1375 const char *symname
;
1382 type
= BSF_NO_FLAGS
;
1386 type
= BSF_NO_FLAGS
;
1392 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1393 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1395 /* Save the mapping symbols for future reference. Also check that
1396 we do not place two mapping symbols at the same offset within a
1397 frag. We'll handle overlap between frags in
1398 check_mapping_symbols.
1400 If .fill or other data filling directive generates zero sized data,
1401 the mapping symbol for the following code will have the same value
1402 as the one generated for the data filling directive. In this case,
1403 we replace the old symbol with the new one at the same address. */
1406 if (frag
->tc_frag_data
.first_map
!= NULL
)
1408 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1409 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1412 frag
->tc_frag_data
.first_map
= symbolP
;
1414 if (frag
->tc_frag_data
.last_map
!= NULL
)
1416 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1417 S_GET_VALUE (symbolP
));
1418 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1419 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1422 frag
->tc_frag_data
.last_map
= symbolP
;
1425 /* We must sometimes convert a region marked as code to data during
1426 code alignment, if an odd number of bytes have to be padded. The
1427 code mapping symbol is pushed to an aligned address. */
1430 insert_data_mapping_symbol (enum mstate state
,
1431 valueT value
, fragS
* frag
, offsetT bytes
)
1433 /* If there was already a mapping symbol, remove it. */
1434 if (frag
->tc_frag_data
.last_map
!= NULL
1435 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1436 frag
->fr_address
+ value
)
1438 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1442 know (frag
->tc_frag_data
.first_map
== symp
);
1443 frag
->tc_frag_data
.first_map
= NULL
;
1445 frag
->tc_frag_data
.last_map
= NULL
;
1446 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1449 make_mapping_symbol (MAP_DATA
, value
, frag
);
1450 make_mapping_symbol (state
, value
+ bytes
, frag
);
1453 static void mapping_state_2 (enum mstate state
, int max_chars
);
1455 /* Set the mapping state to STATE. Only call this when about to
1456 emit some STATE bytes to the file. */
1459 mapping_state (enum mstate state
)
1461 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1463 if (state
== MAP_INSN
)
1464 /* AArch64 instructions require 4-byte alignment. When emitting
1465 instructions into any section, record the appropriate section
1467 record_alignment (now_seg
, 2);
1469 if (mapstate
== state
)
1470 /* The mapping symbol has already been emitted.
1471 There is nothing else to do. */
1474 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1475 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1476 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1477 evaluated later in the next else. */
1479 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1481 /* Only add the symbol if the offset is > 0:
1482 if we're at the first frag, check it's size > 0;
1483 if we're not at the first frag, then for sure
1484 the offset is > 0. */
1485 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1486 const int add_symbol
= (frag_now
!= frag_first
)
1487 || (frag_now_fix () > 0);
1490 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1494 mapping_state_2 (state
, 0);
1497 /* Same as mapping_state, but MAX_CHARS bytes have already been
1498 allocated. Put the mapping symbol that far back. */
1501 mapping_state_2 (enum mstate state
, int max_chars
)
1503 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1505 if (!SEG_NORMAL (now_seg
))
1508 if (mapstate
== state
)
1509 /* The mapping symbol has already been emitted.
1510 There is nothing else to do. */
1513 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1514 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1517 #define mapping_state(x) /* nothing */
1518 #define mapping_state_2(x, y) /* nothing */
1521 /* Directives: sectioning and alignment. */
1524 s_bss (int ignore ATTRIBUTE_UNUSED
)
1526 /* We don't support putting frags in the BSS segment, we fake it by
1527 marking in_bss, then looking at s_skip for clues. */
1528 subseg_set (bss_section
, 0);
1529 demand_empty_rest_of_line ();
1530 mapping_state (MAP_DATA
);
1534 s_even (int ignore ATTRIBUTE_UNUSED
)
1536 /* Never make frag if expect extra pass. */
1538 frag_align (1, 0, 0);
1540 record_alignment (now_seg
, 1);
1542 demand_empty_rest_of_line ();
1545 /* Directives: Literal pools. */
1547 static literal_pool
*
1548 find_literal_pool (int size
)
1552 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1554 if (pool
->section
== now_seg
1555 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1562 static literal_pool
*
1563 find_or_make_literal_pool (int size
)
1565 /* Next literal pool ID number. */
1566 static unsigned int latest_pool_num
= 1;
1569 pool
= find_literal_pool (size
);
1573 /* Create a new pool. */
1574 pool
= xmalloc (sizeof (*pool
));
1578 /* Currently we always put the literal pool in the current text
1579 section. If we were generating "small" model code where we
1580 knew that all code and initialised data was within 1MB then
1581 we could output literals to mergeable, read-only data
1584 pool
->next_free_entry
= 0;
1585 pool
->section
= now_seg
;
1586 pool
->sub_section
= now_subseg
;
1588 pool
->next
= list_of_pools
;
1589 pool
->symbol
= NULL
;
1591 /* Add it to the list. */
1592 list_of_pools
= pool
;
1595 /* New pools, and emptied pools, will have a NULL symbol. */
1596 if (pool
->symbol
== NULL
)
1598 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1599 (valueT
) 0, &zero_address_frag
);
1600 pool
->id
= latest_pool_num
++;
1607 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1608 Return TRUE on success, otherwise return FALSE. */
1610 add_to_lit_pool (expressionS
*exp
, int size
)
1615 pool
= find_or_make_literal_pool (size
);
1617 /* Check if this literal value is already in the pool. */
1618 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1620 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1622 if ((litexp
->X_op
== exp
->X_op
)
1623 && (exp
->X_op
== O_constant
)
1624 && (litexp
->X_add_number
== exp
->X_add_number
)
1625 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1628 if ((litexp
->X_op
== exp
->X_op
)
1629 && (exp
->X_op
== O_symbol
)
1630 && (litexp
->X_add_number
== exp
->X_add_number
)
1631 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1632 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1636 /* Do we need to create a new entry? */
1637 if (entry
== pool
->next_free_entry
)
1639 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1641 set_syntax_error (_("literal pool overflow"));
1645 pool
->literals
[entry
].exp
= *exp
;
1646 pool
->next_free_entry
+= 1;
1647 if (exp
->X_op
== O_big
)
1649 /* PR 16688: Bignums are held in a single global array. We must
1650 copy and preserve that value now, before it is overwritten. */
1651 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1652 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1653 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1656 pool
->literals
[entry
].bignum
= NULL
;
1659 exp
->X_op
= O_symbol
;
1660 exp
->X_add_number
= ((int) entry
) * size
;
1661 exp
->X_add_symbol
= pool
->symbol
;
1666 /* Can't use symbol_new here, so have to create a symbol and then at
1667 a later date assign it a value. Thats what these functions do. */
1670 symbol_locate (symbolS
* symbolP
,
1671 const char *name
,/* It is copied, the caller can modify. */
1672 segT segment
, /* Segment identifier (SEG_<something>). */
1673 valueT valu
, /* Symbol value. */
1674 fragS
* frag
) /* Associated fragment. */
1677 char *preserved_copy_of_name
;
1679 name_length
= strlen (name
) + 1; /* +1 for \0. */
1680 obstack_grow (¬es
, name
, name_length
);
1681 preserved_copy_of_name
= obstack_finish (¬es
);
1683 #ifdef tc_canonicalize_symbol_name
1684 preserved_copy_of_name
=
1685 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1688 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1690 S_SET_SEGMENT (symbolP
, segment
);
1691 S_SET_VALUE (symbolP
, valu
);
1692 symbol_clear_list_pointers (symbolP
);
1694 symbol_set_frag (symbolP
, frag
);
1696 /* Link to end of symbol chain. */
1698 extern int symbol_table_frozen
;
1700 if (symbol_table_frozen
)
1704 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1706 obj_symbol_new_hook (symbolP
);
1708 #ifdef tc_symbol_new_hook
1709 tc_symbol_new_hook (symbolP
);
1713 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1714 #endif /* DEBUG_SYMS */
1719 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1726 for (align
= 2; align
<= 4; align
++)
1728 int size
= 1 << align
;
1730 pool
= find_literal_pool (size
);
1731 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1734 mapping_state (MAP_DATA
);
1736 /* Align pool as you have word accesses.
1737 Only make a frag if we have to. */
1739 frag_align (align
, 0, 0);
1741 record_alignment (now_seg
, align
);
1743 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1745 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1746 (valueT
) frag_now_fix (), frag_now
);
1747 symbol_table_insert (pool
->symbol
);
1749 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1751 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1753 if (exp
->X_op
== O_big
)
1755 /* PR 16688: Restore the global bignum value. */
1756 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1757 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1758 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1761 /* First output the expression in the instruction to the pool. */
1762 emit_expr (exp
, size
); /* .word|.xword */
1764 if (exp
->X_op
== O_big
)
1766 free (pool
->literals
[entry
].bignum
);
1767 pool
->literals
[entry
].bignum
= NULL
;
1771 /* Mark the pool as empty. */
1772 pool
->next_free_entry
= 0;
1773 pool
->symbol
= NULL
;
1778 /* Forward declarations for functions below, in the MD interface
1780 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1781 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1783 /* Directives: Data. */
1784 /* N.B. the support for relocation suffix in this directive needs to be
1785 implemented properly. */
1788 s_aarch64_elf_cons (int nbytes
)
1792 #ifdef md_flush_pending_output
1793 md_flush_pending_output ();
1796 if (is_it_end_of_statement ())
1798 demand_empty_rest_of_line ();
1802 #ifdef md_cons_align
1803 md_cons_align (nbytes
);
1806 mapping_state (MAP_DATA
);
1809 struct reloc_table_entry
*reloc
;
1813 if (exp
.X_op
!= O_symbol
)
1814 emit_expr (&exp
, (unsigned int) nbytes
);
1817 skip_past_char (&input_line_pointer
, '#');
1818 if (skip_past_char (&input_line_pointer
, ':'))
1820 reloc
= find_reloc_table_entry (&input_line_pointer
);
1822 as_bad (_("unrecognized relocation suffix"));
1824 as_bad (_("unimplemented relocation suffix"));
1825 ignore_rest_of_line ();
1829 emit_expr (&exp
, (unsigned int) nbytes
);
1832 while (*input_line_pointer
++ == ',');
1834 /* Put terminator back into stream. */
1835 input_line_pointer
--;
1836 demand_empty_rest_of_line ();
1839 #endif /* OBJ_ELF */
1841 /* Output a 32-bit word, but mark as an instruction. */
1844 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1848 #ifdef md_flush_pending_output
1849 md_flush_pending_output ();
1852 if (is_it_end_of_statement ())
1854 demand_empty_rest_of_line ();
1858 /* Sections are assumed to start aligned. In executable section, there is no
1859 MAP_DATA symbol pending. So we only align the address during
1860 MAP_DATA --> MAP_INSN transition.
1861 For other sections, this is not guaranteed. */
1862 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1863 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1864 frag_align_code (2, 0);
1867 mapping_state (MAP_INSN
);
1873 if (exp
.X_op
!= O_constant
)
1875 as_bad (_("constant expression required"));
1876 ignore_rest_of_line ();
1880 if (target_big_endian
)
1882 unsigned int val
= exp
.X_add_number
;
1883 exp
.X_add_number
= SWAP_32 (val
);
1885 emit_expr (&exp
, 4);
1887 while (*input_line_pointer
++ == ',');
1889 /* Put terminator back into stream. */
1890 input_line_pointer
--;
1891 demand_empty_rest_of_line ();
1895 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1898 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1902 /* Since we're just labelling the code, there's no need to define a
1905 /* Make sure there is enough room in this frag for the following
1906 blr. This trick only works if the blr follows immediately after
1907 the .tlsdesc directive. */
1909 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1910 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1912 demand_empty_rest_of_line ();
1914 #endif /* OBJ_ELF */
1916 static void s_aarch64_arch (int);
1917 static void s_aarch64_cpu (int);
1918 static void s_aarch64_arch_extension (int);
1920 /* This table describes all the machine specific pseudo-ops the assembler
1921 has to support. The fields are:
1922 pseudo-op name without dot
1923 function to call to execute this pseudo-op
1924 Integer arg to pass to the function. */
1926 const pseudo_typeS md_pseudo_table
[] = {
1927 /* Never called because '.req' does not start a line. */
1929 {"unreq", s_unreq
, 0},
1931 {"even", s_even
, 0},
1932 {"ltorg", s_ltorg
, 0},
1933 {"pool", s_ltorg
, 0},
1934 {"cpu", s_aarch64_cpu
, 0},
1935 {"arch", s_aarch64_arch
, 0},
1936 {"arch_extension", s_aarch64_arch_extension
, 0},
1937 {"inst", s_aarch64_inst
, 0},
1939 {"tlsdesccall", s_tlsdesccall
, 0},
1940 {"word", s_aarch64_elf_cons
, 4},
1941 {"long", s_aarch64_elf_cons
, 4},
1942 {"xword", s_aarch64_elf_cons
, 8},
1943 {"dword", s_aarch64_elf_cons
, 8},
1949 /* Check whether STR points to a register name followed by a comma or the
1950 end of line; REG_TYPE indicates which register types are checked
1951 against. Return TRUE if STR is such a register name; otherwise return
1952 FALSE. The function does not intend to produce any diagnostics, but since
1953 the register parser aarch64_reg_parse, which is called by this function,
1954 does produce diagnostics, we call clear_error to clear any diagnostics
1955 that may be generated by aarch64_reg_parse.
1956 Also, the function returns FALSE directly if there is any user error
1957 present at the function entry. This prevents the existing diagnostics
1958 state from being spoiled.
1959 The function currently serves parse_constant_immediate and
1960 parse_big_immediate only. */
1962 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1966 /* Prevent the diagnostics state from being spoiled. */
1970 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1972 /* Clear the parsing error that may be set by the reg parser. */
1975 if (reg
== PARSE_FAIL
)
1978 skip_whitespace (str
);
1979 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1985 /* Parser functions used exclusively in instruction operands. */
1987 /* Parse an immediate expression which may not be constant.
1989 To prevent the expression parser from pushing a register name
1990 into the symbol table as an undefined symbol, firstly a check is
1991 done to find out whether STR is a valid register name followed
1992 by a comma or the end of line. Return FALSE if STR is such a
1996 parse_immediate_expression (char **str
, expressionS
*exp
)
1998 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2000 set_recoverable_error (_("immediate operand required"));
2004 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2006 if (exp
->X_op
== O_absent
)
2008 set_fatal_syntax_error (_("missing immediate expression"));
2015 /* Constant immediate-value read function for use in insn parsing.
2016 STR points to the beginning of the immediate (with the optional
2017 leading #); *VAL receives the value.
2019 Return TRUE on success; otherwise return FALSE. */
2022 parse_constant_immediate (char **str
, int64_t * val
)
2026 if (! parse_immediate_expression (str
, &exp
))
2029 if (exp
.X_op
!= O_constant
)
2031 set_syntax_error (_("constant expression required"));
2035 *val
= exp
.X_add_number
;
2040 encode_imm_float_bits (uint32_t imm
)
2042 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2043 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2046 /* Return TRUE if the single-precision floating-point value encoded in IMM
2047 can be expressed in the AArch64 8-bit signed floating-point format with
2048 3-bit exponent and normalized 4 bits of precision; in other words, the
2049 floating-point value must be expressable as
2050 (+/-) n / 16 * power (2, r)
2051 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2054 aarch64_imm_float_p (uint32_t imm
)
2056 /* If a single-precision floating-point value has the following bit
2057 pattern, it can be expressed in the AArch64 8-bit floating-point
2060 3 32222222 2221111111111
2061 1 09876543 21098765432109876543210
2062 n Eeeeeexx xxxx0000000000000000000
2064 where n, e and each x are either 0 or 1 independently, with
2069 /* Prepare the pattern for 'Eeeeee'. */
2070 if (((imm
>> 30) & 0x1) == 0)
2071 pattern
= 0x3e000000;
2073 pattern
= 0x40000000;
2075 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2076 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2079 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2081 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2082 8-bit signed floating-point format with 3-bit exponent and normalized 4
2083 bits of precision (i.e. can be used in an FMOV instruction); return the
2084 equivalent single-precision encoding in *FPWORD.
2086 Otherwise return FALSE. */
2089 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2091 /* If a double-precision floating-point value has the following bit
2092 pattern, it can be expressed in the AArch64 8-bit floating-point
2095 6 66655555555 554444444...21111111111
2096 3 21098765432 109876543...098765432109876543210
2097 n Eeeeeeeeexx xxxx00000...000000000000000000000
2099 where n, e and each x are either 0 or 1 independently, with
2103 uint32_t high32
= imm
>> 32;
2105 /* Lower 32 bits need to be 0s. */
2106 if ((imm
& 0xffffffff) != 0)
2109 /* Prepare the pattern for 'Eeeeeeeee'. */
2110 if (((high32
>> 30) & 0x1) == 0)
2111 pattern
= 0x3fc00000;
2113 pattern
= 0x40000000;
2115 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2116 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2118 /* Convert to the single-precision encoding.
2120 n Eeeeeeeeexx xxxx00000...000000000000000000000
2122 n Eeeeeexx xxxx0000000000000000000. */
2123 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2124 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2131 /* Parse a floating-point immediate. Return TRUE on success and return the
2132 value in *IMMED in the format of IEEE754 single-precision encoding.
2133 *CCP points to the start of the string; DP_P is TRUE when the immediate
2134 is expected to be in double-precision (N.B. this only matters when
2135 hexadecimal representation is involved).
2137 N.B. 0.0 is accepted by this function. */
2140 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2144 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2145 int found_fpchar
= 0;
2147 unsigned fpword
= 0;
2148 bfd_boolean hex_p
= FALSE
;
2150 skip_past_char (&str
, '#');
2153 skip_whitespace (fpnum
);
2155 if (strncmp (fpnum
, "0x", 2) == 0)
2157 /* Support the hexadecimal representation of the IEEE754 encoding.
2158 Double-precision is expected when DP_P is TRUE, otherwise the
2159 representation should be in single-precision. */
2160 if (! parse_constant_immediate (&str
, &val
))
2165 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2168 else if ((uint64_t) val
> 0xffffffff)
2177 /* We must not accidentally parse an integer as a floating-point number.
2178 Make sure that the value we parse is not an integer by checking for
2179 special characters '.' or 'e'. */
2180 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2181 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2195 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2198 /* Our FP word must be 32 bits (single-precision FP). */
2199 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2201 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2206 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2214 set_fatal_syntax_error (_("invalid floating-point constant"));
2218 /* Less-generic immediate-value read function with the possibility of loading
2219 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2222 To prevent the expression parser from pushing a register name into the
2223 symbol table as an undefined symbol, a check is firstly done to find
2224 out whether STR is a valid register name followed by a comma or the end
2225 of line. Return FALSE if STR is such a register. */
2228 parse_big_immediate (char **str
, int64_t *imm
)
2232 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2234 set_syntax_error (_("immediate operand required"));
2238 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2240 if (inst
.reloc
.exp
.X_op
== O_constant
)
2241 *imm
= inst
.reloc
.exp
.X_add_number
;
2248 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2249 if NEED_LIBOPCODES is non-zero, the fixup will need
2250 assistance from the libopcodes. */
2253 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2254 const aarch64_opnd_info
*operand
,
2255 int need_libopcodes_p
)
2257 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2258 reloc
->opnd
= operand
->type
;
2259 if (need_libopcodes_p
)
2260 reloc
->need_libopcodes_p
= 1;
2263 /* Return TRUE if the instruction needs to be fixed up later internally by
2264 the GAS; otherwise return FALSE. */
2266 static inline bfd_boolean
2267 aarch64_gas_internal_fixup_p (void)
2269 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2272 /* Assign the immediate value to the relavant field in *OPERAND if
2273 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2274 needs an internal fixup in a later stage.
2275 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2276 IMM.VALUE that may get assigned with the constant. */
2278 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2279 aarch64_opnd_info
*operand
,
2281 int need_libopcodes_p
,
2284 if (reloc
->exp
.X_op
== O_constant
)
2287 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2289 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2290 reloc
->type
= BFD_RELOC_UNUSED
;
2294 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2295 /* Tell libopcodes to ignore this operand or not. This is helpful
2296 when one of the operands needs to be fixed up later but we need
2297 libopcodes to check the other operands. */
2298 operand
->skip
= skip_p
;
2302 /* Relocation modifiers. Each entry in the table contains the textual
2303 name for the relocation which may be placed before a symbol used as
2304 a load/store offset, or add immediate. It must be surrounded by a
2305 leading and trailing colon, for example:
2307 ldr x0, [x1, #:rello:varsym]
2308 add x0, x1, #:rello:varsym */
2310 struct reloc_table_entry
2314 bfd_reloc_code_real_type adr_type
;
2315 bfd_reloc_code_real_type adrp_type
;
2316 bfd_reloc_code_real_type movw_type
;
2317 bfd_reloc_code_real_type add_type
;
2318 bfd_reloc_code_real_type ldst_type
;
2319 bfd_reloc_code_real_type ld_literal_type
;
2322 static struct reloc_table_entry reloc_table
[] = {
2323 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2328 BFD_RELOC_AARCH64_ADD_LO12
,
2329 BFD_RELOC_AARCH64_LDST_LO12
,
2332 /* Higher 21 bits of pc-relative page offset: ADRP */
2335 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2341 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2344 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2350 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2354 BFD_RELOC_AARCH64_MOVW_G0
,
2359 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2363 BFD_RELOC_AARCH64_MOVW_G0_S
,
2368 /* Less significant bits 0-15 of address/value: MOVK, no check */
2372 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2377 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2381 BFD_RELOC_AARCH64_MOVW_G1
,
2386 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2390 BFD_RELOC_AARCH64_MOVW_G1_S
,
2395 /* Less significant bits 16-31 of address/value: MOVK, no check */
2399 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2404 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2408 BFD_RELOC_AARCH64_MOVW_G2
,
2413 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2417 BFD_RELOC_AARCH64_MOVW_G2_S
,
2422 /* Less significant bits 32-47 of address/value: MOVK, no check */
2426 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2431 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2435 BFD_RELOC_AARCH64_MOVW_G3
,
2440 /* Get to the page containing GOT entry for a symbol. */
2443 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2447 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2449 /* 12 bit offset into the page containing GOT entry for that symbol. */
2455 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2458 /* Get to the page containing GOT TLS entry for a symbol */
2460 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2461 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2467 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2472 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2476 /* Get to the page containing GOT TLS entry for a symbol */
2478 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2479 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2483 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2485 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2490 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2491 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2494 /* Get to the page containing GOT TLS entry for a symbol */
2497 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2501 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2503 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2504 {"gottprel_lo12", 0,
2509 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2512 /* Get tp offset for a symbol. */
2517 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2521 /* Get tp offset for a symbol. */
2526 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2530 /* Get tp offset for a symbol. */
2535 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2539 /* Get tp offset for a symbol. */
2540 {"tprel_lo12_nc", 0,
2544 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2548 /* Most significant bits 32-47 of address/value: MOVZ. */
2552 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2557 /* Most significant bits 16-31 of address/value: MOVZ. */
2561 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2566 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2570 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2575 /* Most significant bits 0-15 of address/value: MOVZ. */
2579 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2584 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2588 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2593 /* 15bit offset from got entry to base address of GOT table. */
2599 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2602 /* 14bit offset from got entry to base address of GOT table. */
2608 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2612 /* Given the address of a pointer pointing to the textual name of a
2613 relocation as may appear in assembler source, attempt to find its
2614 details in reloc_table. The pointer will be updated to the character
2615 after the trailing colon. On failure, NULL will be returned;
2616 otherwise return the reloc_table_entry. */
2618 static struct reloc_table_entry
*
2619 find_reloc_table_entry (char **str
)
2622 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2624 int length
= strlen (reloc_table
[i
].name
);
2626 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2627 && (*str
)[length
] == ':')
2629 *str
+= (length
+ 1);
2630 return &reloc_table
[i
];
2637 /* Mode argument to parse_shift and parser_shifter_operand. */
2638 enum parse_shift_mode
2640 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2642 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2644 SHIFTED_LSL
, /* bare "lsl #n" */
2645 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2646 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2649 /* Parse a <shift> operator on an AArch64 data processing instruction.
2650 Return TRUE on success; otherwise return FALSE. */
2652 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2654 const struct aarch64_name_value_pair
*shift_op
;
2655 enum aarch64_modifier_kind kind
;
2661 for (p
= *str
; ISALPHA (*p
); p
++)
2666 set_syntax_error (_("shift expression expected"));
2670 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2672 if (shift_op
== NULL
)
2674 set_syntax_error (_("shift operator expected"));
2678 kind
= aarch64_get_operand_modifier (shift_op
);
2680 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2682 set_syntax_error (_("invalid use of 'MSL'"));
2688 case SHIFTED_LOGIC_IMM
:
2689 if (aarch64_extend_operator_p (kind
) == TRUE
)
2691 set_syntax_error (_("extending shift is not permitted"));
2696 case SHIFTED_ARITH_IMM
:
2697 if (kind
== AARCH64_MOD_ROR
)
2699 set_syntax_error (_("'ROR' shift is not permitted"));
2705 if (kind
!= AARCH64_MOD_LSL
)
2707 set_syntax_error (_("only 'LSL' shift is permitted"));
2712 case SHIFTED_REG_OFFSET
:
2713 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2714 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2716 set_fatal_syntax_error
2717 (_("invalid shift for the register offset addressing mode"));
2722 case SHIFTED_LSL_MSL
:
2723 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2725 set_syntax_error (_("invalid shift operator"));
2734 /* Whitespace can appear here if the next thing is a bare digit. */
2735 skip_whitespace (p
);
2737 /* Parse shift amount. */
2739 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2740 exp
.X_op
= O_absent
;
2743 if (is_immediate_prefix (*p
))
2748 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2750 if (exp
.X_op
== O_absent
)
2752 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2754 set_syntax_error (_("missing shift amount"));
2757 operand
->shifter
.amount
= 0;
2759 else if (exp
.X_op
!= O_constant
)
2761 set_syntax_error (_("constant shift amount required"));
2764 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2766 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2771 operand
->shifter
.amount
= exp
.X_add_number
;
2772 operand
->shifter
.amount_present
= 1;
2775 operand
->shifter
.operator_present
= 1;
2776 operand
->shifter
.kind
= kind
;
2782 /* Parse a <shifter_operand> for a data processing instruction:
2785 #<immediate>, LSL #imm
2787 Validation of immediate operands is deferred to md_apply_fix.
2789 Return TRUE on success; otherwise return FALSE. */
2792 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2793 enum parse_shift_mode mode
)
2797 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2802 /* Accept an immediate expression. */
2803 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2806 /* Accept optional LSL for arithmetic immediate values. */
2807 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2808 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2811 /* Not accept any shifter for logical immediate values. */
2812 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2813 && parse_shift (&p
, operand
, mode
))
2815 set_syntax_error (_("unexpected shift operator"));
2823 /* Parse a <shifter_operand> for a data processing instruction:
2828 #<immediate>, LSL #imm
2830 where <shift> is handled by parse_shift above, and the last two
2831 cases are handled by the function above.
2833 Validation of immediate operands is deferred to md_apply_fix.
2835 Return TRUE on success; otherwise return FALSE. */
2838 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2839 enum parse_shift_mode mode
)
2842 int isreg32
, isregzero
;
2843 enum aarch64_operand_class opd_class
2844 = aarch64_get_operand_class (operand
->type
);
2847 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2849 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2851 set_syntax_error (_("unexpected register in the immediate operand"));
2855 if (!isregzero
&& reg
== REG_SP
)
2857 set_syntax_error (BAD_SP
);
2861 operand
->reg
.regno
= reg
;
2862 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2864 /* Accept optional shift operation on register. */
2865 if (! skip_past_comma (str
))
2868 if (! parse_shift (str
, operand
, mode
))
2873 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2876 (_("integer register expected in the extended/shifted operand "
2881 /* We have a shifted immediate variable. */
2882 return parse_shifter_operand_imm (str
, operand
, mode
);
2885 /* Return TRUE on success; return FALSE otherwise. */
2888 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
2889 enum parse_shift_mode mode
)
2893 /* Determine if we have the sequence of characters #: or just :
2894 coming next. If we do, then we check for a :rello: relocation
2895 modifier. If we don't, punt the whole lot to
2896 parse_shifter_operand. */
2898 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
2900 struct reloc_table_entry
*entry
;
2908 /* Try to parse a relocation. Anything else is an error. */
2909 if (!(entry
= find_reloc_table_entry (str
)))
2911 set_syntax_error (_("unknown relocation modifier"));
2915 if (entry
->add_type
== 0)
2918 (_("this relocation modifier is not allowed on this instruction"));
2922 /* Save str before we decompose it. */
2925 /* Next, we parse the expression. */
2926 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
2929 /* Record the relocation type (use the ADD variant here). */
2930 inst
.reloc
.type
= entry
->add_type
;
2931 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2933 /* If str is empty, we've reached the end, stop here. */
2937 /* Otherwise, we have a shifted reloc modifier, so rewind to
2938 recover the variable name and continue parsing for the shifter. */
2940 return parse_shifter_operand_imm (str
, operand
, mode
);
2943 return parse_shifter_operand (str
, operand
, mode
);
2946 /* Parse all forms of an address expression. Information is written
2947 to *OPERAND and/or inst.reloc.
2949 The A64 instruction set has the following addressing modes:
2952 [base] // in SIMD ld/st structure
2953 [base{,#0}] // in ld/st exclusive
2955 [base,Xm{,LSL #imm}]
2956 [base,Xm,SXTX {#imm}]
2957 [base,Wm,(S|U)XTW {#imm}]
2962 [base],Xm // in SIMD ld/st structure
2963 PC-relative (literal)
2967 (As a convenience, the notation "=immediate" is permitted in conjunction
2968 with the pc-relative literal load instructions to automatically place an
2969 immediate value or symbolic address in a nearby literal pool and generate
2970 a hidden label which references it.)
2972 Upon a successful parsing, the address structure in *OPERAND will be
2973 filled in the following way:
2975 .base_regno = <base>
2976 .offset.is_reg // 1 if the offset is a register
2978 .offset.regno = <Rm>
2980 For different addressing modes defined in the A64 ISA:
2983 .pcrel=0; .preind=1; .postind=0; .writeback=0
2985 .pcrel=0; .preind=1; .postind=0; .writeback=1
2987 .pcrel=0; .preind=0; .postind=1; .writeback=1
2988 PC-relative (literal)
2989 .pcrel=1; .preind=1; .postind=0; .writeback=0
2991 The shift/extension information, if any, will be stored in .shifter.
2993 It is the caller's responsibility to check for addressing modes not
2994 supported by the instruction, and to set inst.reloc.type. */
2997 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
2998 int accept_reg_post_index
)
3002 int isreg32
, isregzero
;
3003 expressionS
*exp
= &inst
.reloc
.exp
;
3005 if (! skip_past_char (&p
, '['))
3007 /* =immediate or label. */
3008 operand
->addr
.pcrel
= 1;
3009 operand
->addr
.preind
= 1;
3011 /* #:<reloc_op>:<symbol> */
3012 skip_past_char (&p
, '#');
3013 if (reloc
&& skip_past_char (&p
, ':'))
3015 bfd_reloc_code_real_type ty
;
3016 struct reloc_table_entry
*entry
;
3018 /* Try to parse a relocation modifier. Anything else is
3020 entry
= find_reloc_table_entry (&p
);
3023 set_syntax_error (_("unknown relocation modifier"));
3027 switch (operand
->type
)
3029 case AARCH64_OPND_ADDR_PCREL21
:
3031 ty
= entry
->adr_type
;
3035 ty
= entry
->ld_literal_type
;
3042 (_("this relocation modifier is not allowed on this "
3048 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3050 set_syntax_error (_("invalid relocation expression"));
3054 /* #:<reloc_op>:<expr> */
3055 /* Record the relocation type. */
3056 inst
.reloc
.type
= ty
;
3057 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3062 if (skip_past_char (&p
, '='))
3063 /* =immediate; need to generate the literal in the literal pool. */
3064 inst
.gen_lit_pool
= 1;
3066 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3068 set_syntax_error (_("invalid address"));
3079 /* Accept SP and reject ZR */
3080 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3081 if (reg
== PARSE_FAIL
|| isreg32
)
3083 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3086 operand
->addr
.base_regno
= reg
;
3089 if (skip_past_comma (&p
))
3092 operand
->addr
.preind
= 1;
3094 /* Reject SP and accept ZR */
3095 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3096 if (reg
!= PARSE_FAIL
)
3099 operand
->addr
.offset
.regno
= reg
;
3100 operand
->addr
.offset
.is_reg
= 1;
3101 /* Shifted index. */
3102 if (skip_past_comma (&p
))
3105 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3106 /* Use the diagnostics set in parse_shift, so not set new
3107 error message here. */
3111 [base,Xm{,LSL #imm}]
3112 [base,Xm,SXTX {#imm}]
3113 [base,Wm,(S|U)XTW {#imm}] */
3114 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3115 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3116 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3120 set_syntax_error (_("invalid use of 32-bit register offset"));
3126 set_syntax_error (_("invalid use of 64-bit register offset"));
3132 /* [Xn,#:<reloc_op>:<symbol> */
3133 skip_past_char (&p
, '#');
3134 if (reloc
&& skip_past_char (&p
, ':'))
3136 struct reloc_table_entry
*entry
;
3138 /* Try to parse a relocation modifier. Anything else is
3140 if (!(entry
= find_reloc_table_entry (&p
)))
3142 set_syntax_error (_("unknown relocation modifier"));
3146 if (entry
->ldst_type
== 0)
3149 (_("this relocation modifier is not allowed on this "
3154 /* [Xn,#:<reloc_op>: */
3155 /* We now have the group relocation table entry corresponding to
3156 the name in the assembler source. Next, we parse the
3158 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3160 set_syntax_error (_("invalid relocation expression"));
3164 /* [Xn,#:<reloc_op>:<expr> */
3165 /* Record the load/store relocation type. */
3166 inst
.reloc
.type
= entry
->ldst_type
;
3167 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3169 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3171 set_syntax_error (_("invalid expression in the address"));
3178 if (! skip_past_char (&p
, ']'))
3180 set_syntax_error (_("']' expected"));
3184 if (skip_past_char (&p
, '!'))
3186 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3188 set_syntax_error (_("register offset not allowed in pre-indexed "
3189 "addressing mode"));
3193 operand
->addr
.writeback
= 1;
3195 else if (skip_past_comma (&p
))
3198 operand
->addr
.postind
= 1;
3199 operand
->addr
.writeback
= 1;
3201 if (operand
->addr
.preind
)
3203 set_syntax_error (_("cannot combine pre- and post-indexing"));
3207 if (accept_reg_post_index
3208 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3209 &isregzero
)) != PARSE_FAIL
)
3214 set_syntax_error (_("invalid 32-bit register offset"));
3217 operand
->addr
.offset
.regno
= reg
;
3218 operand
->addr
.offset
.is_reg
= 1;
3220 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3223 set_syntax_error (_("invalid expression in the address"));
3228 /* If at this point neither .preind nor .postind is set, we have a
3229 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3230 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3232 if (operand
->addr
.writeback
)
3235 set_syntax_error (_("missing offset in the pre-indexed address"));
3238 operand
->addr
.preind
= 1;
3239 inst
.reloc
.exp
.X_op
= O_constant
;
3240 inst
.reloc
.exp
.X_add_number
= 0;
3247 /* Return TRUE on success; otherwise return FALSE. */
3249 parse_address (char **str
, aarch64_opnd_info
*operand
,
3250 int accept_reg_post_index
)
3252 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3255 /* Return TRUE on success; otherwise return FALSE. */
3257 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3259 return parse_address_main (str
, operand
, 1, 0);
3262 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3263 Return TRUE on success; otherwise return FALSE. */
3265 parse_half (char **str
, int *internal_fixup_p
)
3271 skip_past_char (&p
, '#');
3273 gas_assert (internal_fixup_p
);
3274 *internal_fixup_p
= 0;
3278 struct reloc_table_entry
*entry
;
3280 /* Try to parse a relocation. Anything else is an error. */
3282 if (!(entry
= find_reloc_table_entry (&p
)))
3284 set_syntax_error (_("unknown relocation modifier"));
3288 if (entry
->movw_type
== 0)
3291 (_("this relocation modifier is not allowed on this instruction"));
3295 inst
.reloc
.type
= entry
->movw_type
;
3298 *internal_fixup_p
= 1;
3300 /* Avoid parsing a register as a general symbol. */
3302 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3306 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3313 /* Parse an operand for an ADRP instruction:
3315 Return TRUE on success; otherwise return FALSE. */
3318 parse_adrp (char **str
)
3325 struct reloc_table_entry
*entry
;
3327 /* Try to parse a relocation. Anything else is an error. */
3329 if (!(entry
= find_reloc_table_entry (&p
)))
3331 set_syntax_error (_("unknown relocation modifier"));
3335 if (entry
->adrp_type
== 0)
3338 (_("this relocation modifier is not allowed on this instruction"));
3342 inst
.reloc
.type
= entry
->adrp_type
;
3345 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3347 inst
.reloc
.pc_rel
= 1;
3349 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3356 /* Miscellaneous. */
3358 /* Parse an option for a preload instruction. Returns the encoding for the
3359 option, or PARSE_FAIL. */
3362 parse_pldop (char **str
)
3365 const struct aarch64_name_value_pair
*o
;
3368 while (ISALNUM (*q
))
3371 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3379 /* Parse an option for a barrier instruction. Returns the encoding for the
3380 option, or PARSE_FAIL. */
3383 parse_barrier (char **str
)
3386 const asm_barrier_opt
*o
;
3389 while (ISALPHA (*q
))
3392 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3400 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3401 Returns the encoding for the option, or PARSE_FAIL.
3403 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3404 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3407 parse_sys_reg (char **str
, struct hash_control
*sys_regs
, int imple_defined_p
)
3411 const aarch64_sys_reg
*o
;
3415 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3417 *p
++ = TOLOWER (*q
);
3419 /* Assert that BUF be large enough. */
3420 gas_assert (p
- buf
== q
- *str
);
3422 o
= hash_find (sys_regs
, buf
);
3425 if (!imple_defined_p
)
3429 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3430 unsigned int op0
, op1
, cn
, cm
, op2
;
3432 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3435 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3437 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3442 if (aarch64_sys_reg_deprecated_p (o
))
3443 as_warn (_("system register name '%s' is deprecated and may be "
3444 "removed in a future release"), buf
);
3452 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3453 for the option, or NULL. */
3455 static const aarch64_sys_ins_reg
*
3456 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3460 const aarch64_sys_ins_reg
*o
;
3463 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3465 *p
++ = TOLOWER (*q
);
3468 o
= hash_find (sys_ins_regs
, buf
);
3476 #define po_char_or_fail(chr) do { \
3477 if (! skip_past_char (&str, chr)) \
3481 #define po_reg_or_fail(regtype) do { \
3482 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3483 if (val == PARSE_FAIL) \
3485 set_default_error (); \
3490 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3491 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3492 &isreg32, &isregzero); \
3493 if (val == PARSE_FAIL) \
3495 set_default_error (); \
3498 info->reg.regno = val; \
3500 info->qualifier = AARCH64_OPND_QLF_W; \
3502 info->qualifier = AARCH64_OPND_QLF_X; \
3505 #define po_imm_nc_or_fail() do { \
3506 if (! parse_constant_immediate (&str, &val)) \
3510 #define po_imm_or_fail(min, max) do { \
3511 if (! parse_constant_immediate (&str, &val)) \
3513 if (val < min || val > max) \
3515 set_fatal_syntax_error (_("immediate value out of range "\
3516 #min " to "#max)); \
3521 #define po_misc_or_fail(expr) do { \
3526 /* encode the 12-bit imm field of Add/sub immediate */
3527 static inline uint32_t
3528 encode_addsub_imm (uint32_t imm
)
3533 /* encode the shift amount field of Add/sub immediate */
3534 static inline uint32_t
3535 encode_addsub_imm_shift_amount (uint32_t cnt
)
3541 /* encode the imm field of Adr instruction */
3542 static inline uint32_t
3543 encode_adr_imm (uint32_t imm
)
3545 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3546 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3549 /* encode the immediate field of Move wide immediate */
3550 static inline uint32_t
3551 encode_movw_imm (uint32_t imm
)
3556 /* encode the 26-bit offset of unconditional branch */
3557 static inline uint32_t
3558 encode_branch_ofs_26 (uint32_t ofs
)
3560 return ofs
& ((1 << 26) - 1);
3563 /* encode the 19-bit offset of conditional branch and compare & branch */
3564 static inline uint32_t
3565 encode_cond_branch_ofs_19 (uint32_t ofs
)
3567 return (ofs
& ((1 << 19) - 1)) << 5;
3570 /* encode the 19-bit offset of ld literal */
3571 static inline uint32_t
3572 encode_ld_lit_ofs_19 (uint32_t ofs
)
3574 return (ofs
& ((1 << 19) - 1)) << 5;
3577 /* Encode the 14-bit offset of test & branch. */
3578 static inline uint32_t
3579 encode_tst_branch_ofs_14 (uint32_t ofs
)
3581 return (ofs
& ((1 << 14) - 1)) << 5;
3584 /* Encode the 16-bit imm field of svc/hvc/smc. */
3585 static inline uint32_t
3586 encode_svc_imm (uint32_t imm
)
3591 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3592 static inline uint32_t
3593 reencode_addsub_switch_add_sub (uint32_t opcode
)
3595 return opcode
^ (1 << 30);
3598 static inline uint32_t
3599 reencode_movzn_to_movz (uint32_t opcode
)
3601 return opcode
| (1 << 30);
3604 static inline uint32_t
3605 reencode_movzn_to_movn (uint32_t opcode
)
3607 return opcode
& ~(1 << 30);
3610 /* Overall per-instruction processing. */
3612 /* We need to be able to fix up arbitrary expressions in some statements.
3613 This is so that we can handle symbols that are an arbitrary distance from
3614 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3615 which returns part of an address in a form which will be valid for
3616 a data instruction. We do this by pushing the expression into a symbol
3617 in the expr_section, and creating a fix for that. */
3620 fix_new_aarch64 (fragS
* frag
,
3622 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3632 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3636 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3643 /* Diagnostics on operands errors. */
3645 /* By default, output verbose error message.
3646 Disable the verbose error message by -mno-verbose-error. */
3647 static int verbose_error_p
= 1;
3649 #ifdef DEBUG_AARCH64
3650 /* N.B. this is only for the purpose of debugging. */
3651 const char* operand_mismatch_kind_names
[] =
3654 "AARCH64_OPDE_RECOVERABLE",
3655 "AARCH64_OPDE_SYNTAX_ERROR",
3656 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3657 "AARCH64_OPDE_INVALID_VARIANT",
3658 "AARCH64_OPDE_OUT_OF_RANGE",
3659 "AARCH64_OPDE_UNALIGNED",
3660 "AARCH64_OPDE_REG_LIST",
3661 "AARCH64_OPDE_OTHER_ERROR",
3663 #endif /* DEBUG_AARCH64 */
3665 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3667 When multiple errors of different kinds are found in the same assembly
3668 line, only the error of the highest severity will be picked up for
3669 issuing the diagnostics. */
3671 static inline bfd_boolean
3672 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3673 enum aarch64_operand_error_kind rhs
)
3675 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3676 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3677 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3678 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3679 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3680 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3681 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3682 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3686 /* Helper routine to get the mnemonic name from the assembly instruction
3687 line; should only be called for the diagnosis purpose, as there is
3688 string copy operation involved, which may affect the runtime
3689 performance if used in elsewhere. */
3692 get_mnemonic_name (const char *str
)
3694 static char mnemonic
[32];
3697 /* Get the first 15 bytes and assume that the full name is included. */
3698 strncpy (mnemonic
, str
, 31);
3699 mnemonic
[31] = '\0';
3701 /* Scan up to the end of the mnemonic, which must end in white space,
3702 '.', or end of string. */
3703 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3708 /* Append '...' to the truncated long name. */
3709 if (ptr
- mnemonic
== 31)
3710 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3716 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3718 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3719 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3722 /* Data strutures storing one user error in the assembly code related to
3725 struct operand_error_record
3727 const aarch64_opcode
*opcode
;
3728 aarch64_operand_error detail
;
3729 struct operand_error_record
*next
;
3732 typedef struct operand_error_record operand_error_record
;
3734 struct operand_errors
3736 operand_error_record
*head
;
3737 operand_error_record
*tail
;
3740 typedef struct operand_errors operand_errors
;
3742 /* Top-level data structure reporting user errors for the current line of
3744 The way md_assemble works is that all opcodes sharing the same mnemonic
3745 name are iterated to find a match to the assembly line. In this data
3746 structure, each of the such opcodes will have one operand_error_record
3747 allocated and inserted. In other words, excessive errors related with
3748 a single opcode are disregarded. */
3749 operand_errors operand_error_report
;
3751 /* Free record nodes. */
3752 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3754 /* Initialize the data structure that stores the operand mismatch
3755 information on assembling one line of the assembly code. */
3757 init_operand_error_report (void)
3759 if (operand_error_report
.head
!= NULL
)
3761 gas_assert (operand_error_report
.tail
!= NULL
);
3762 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3763 free_opnd_error_record_nodes
= operand_error_report
.head
;
3764 operand_error_report
.head
= NULL
;
3765 operand_error_report
.tail
= NULL
;
3768 gas_assert (operand_error_report
.tail
== NULL
);
3771 /* Return TRUE if some operand error has been recorded during the
3772 parsing of the current assembly line using the opcode *OPCODE;
3773 otherwise return FALSE. */
3774 static inline bfd_boolean
3775 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3777 operand_error_record
*record
= operand_error_report
.head
;
3778 return record
&& record
->opcode
== opcode
;
3781 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3782 OPCODE field is initialized with OPCODE.
3783 N.B. only one record for each opcode, i.e. the maximum of one error is
3784 recorded for each instruction template. */
3787 add_operand_error_record (const operand_error_record
* new_record
)
3789 const aarch64_opcode
*opcode
= new_record
->opcode
;
3790 operand_error_record
* record
= operand_error_report
.head
;
3792 /* The record may have been created for this opcode. If not, we need
3794 if (! opcode_has_operand_error_p (opcode
))
3796 /* Get one empty record. */
3797 if (free_opnd_error_record_nodes
== NULL
)
3799 record
= xmalloc (sizeof (operand_error_record
));
3805 record
= free_opnd_error_record_nodes
;
3806 free_opnd_error_record_nodes
= record
->next
;
3808 record
->opcode
= opcode
;
3809 /* Insert at the head. */
3810 record
->next
= operand_error_report
.head
;
3811 operand_error_report
.head
= record
;
3812 if (operand_error_report
.tail
== NULL
)
3813 operand_error_report
.tail
= record
;
3815 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3816 && record
->detail
.index
<= new_record
->detail
.index
3817 && operand_error_higher_severity_p (record
->detail
.kind
,
3818 new_record
->detail
.kind
))
3820 /* In the case of multiple errors found on operands related with a
3821 single opcode, only record the error of the leftmost operand and
3822 only if the error is of higher severity. */
3823 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3824 " the existing error %s on operand %d",
3825 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3826 new_record
->detail
.index
,
3827 operand_mismatch_kind_names
[record
->detail
.kind
],
3828 record
->detail
.index
);
3832 record
->detail
= new_record
->detail
;
3836 record_operand_error_info (const aarch64_opcode
*opcode
,
3837 aarch64_operand_error
*error_info
)
3839 operand_error_record record
;
3840 record
.opcode
= opcode
;
3841 record
.detail
= *error_info
;
3842 add_operand_error_record (&record
);
3845 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3846 error message *ERROR, for operand IDX (count from 0). */
3849 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3850 enum aarch64_operand_error_kind kind
,
3853 aarch64_operand_error info
;
3854 memset(&info
, 0, sizeof (info
));
3858 record_operand_error_info (opcode
, &info
);
3862 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3863 enum aarch64_operand_error_kind kind
,
3864 const char* error
, const int *extra_data
)
3866 aarch64_operand_error info
;
3870 info
.data
[0] = extra_data
[0];
3871 info
.data
[1] = extra_data
[1];
3872 info
.data
[2] = extra_data
[2];
3873 record_operand_error_info (opcode
, &info
);
3877 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
3878 const char* error
, int lower_bound
,
3881 int data
[3] = {lower_bound
, upper_bound
, 0};
3882 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
3886 /* Remove the operand error record for *OPCODE. */
3887 static void ATTRIBUTE_UNUSED
3888 remove_operand_error_record (const aarch64_opcode
*opcode
)
3890 if (opcode_has_operand_error_p (opcode
))
3892 operand_error_record
* record
= operand_error_report
.head
;
3893 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
3894 operand_error_report
.head
= record
->next
;
3895 record
->next
= free_opnd_error_record_nodes
;
3896 free_opnd_error_record_nodes
= record
;
3897 if (operand_error_report
.head
== NULL
)
3899 gas_assert (operand_error_report
.tail
== record
);
3900 operand_error_report
.tail
= NULL
;
3905 /* Given the instruction in *INSTR, return the index of the best matched
3906 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3908 Return -1 if there is no qualifier sequence; return the first match
3909 if there is multiple matches found. */
3912 find_best_match (const aarch64_inst
*instr
,
3913 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
3915 int i
, num_opnds
, max_num_matched
, idx
;
3917 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3920 DEBUG_TRACE ("no operand");
3924 max_num_matched
= 0;
3927 /* For each pattern. */
3928 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
3931 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
3933 /* Most opcodes has much fewer patterns in the list. */
3934 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
3936 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
3937 if (i
!= 0 && idx
== -1)
3938 /* If nothing has been matched, return the 1st sequence. */
3943 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
3944 if (*qualifiers
== instr
->operands
[j
].qualifier
)
3947 if (num_matched
> max_num_matched
)
3949 max_num_matched
= num_matched
;
3954 DEBUG_TRACE ("return with %d", idx
);
3958 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3959 corresponding operands in *INSTR. */
3962 assign_qualifier_sequence (aarch64_inst
*instr
,
3963 const aarch64_opnd_qualifier_t
*qualifiers
)
3966 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3967 gas_assert (num_opnds
);
3968 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
3969 instr
->operands
[i
].qualifier
= *qualifiers
;
3972 /* Print operands for the diagnosis purpose. */
3975 print_operands (char *buf
, const aarch64_opcode
*opcode
,
3976 const aarch64_opnd_info
*opnds
)
3980 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
3982 const size_t size
= 128;
3985 /* We regard the opcode operand info more, however we also look into
3986 the inst->operands to support the disassembling of the optional
3988 The two operand code should be the same in all cases, apart from
3989 when the operand can be optional. */
3990 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
3991 || opnds
[i
].type
== AARCH64_OPND_NIL
)
3994 /* Generate the operand string in STR. */
3995 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
3999 strcat (buf
, i
== 0 ? " " : ",");
4001 /* Append the operand string. */
4006 /* Send to stderr a string as information. */
4009 output_info (const char *format
, ...)
4015 as_where (&file
, &line
);
4019 fprintf (stderr
, "%s:%u: ", file
, line
);
4021 fprintf (stderr
, "%s: ", file
);
4023 fprintf (stderr
, _("Info: "));
4024 va_start (args
, format
);
4025 vfprintf (stderr
, format
, args
);
4027 (void) putc ('\n', stderr
);
4030 /* Output one operand error record. */
4033 output_operand_error_record (const operand_error_record
*record
, char *str
)
4035 const aarch64_operand_error
*detail
= &record
->detail
;
4036 int idx
= detail
->index
;
4037 const aarch64_opcode
*opcode
= record
->opcode
;
4038 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4039 : AARCH64_OPND_NIL
);
4041 switch (detail
->kind
)
4043 case AARCH64_OPDE_NIL
:
4047 case AARCH64_OPDE_SYNTAX_ERROR
:
4048 case AARCH64_OPDE_RECOVERABLE
:
4049 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4050 case AARCH64_OPDE_OTHER_ERROR
:
4051 /* Use the prepared error message if there is, otherwise use the
4052 operand description string to describe the error. */
4053 if (detail
->error
!= NULL
)
4056 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4058 as_bad (_("%s at operand %d -- `%s'"),
4059 detail
->error
, idx
+ 1, str
);
4063 gas_assert (idx
>= 0);
4064 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4065 aarch64_get_operand_desc (opd_code
), str
);
4069 case AARCH64_OPDE_INVALID_VARIANT
:
4070 as_bad (_("operand mismatch -- `%s'"), str
);
4071 if (verbose_error_p
)
4073 /* We will try to correct the erroneous instruction and also provide
4074 more information e.g. all other valid variants.
4076 The string representation of the corrected instruction and other
4077 valid variants are generated by
4079 1) obtaining the intermediate representation of the erroneous
4081 2) manipulating the IR, e.g. replacing the operand qualifier;
4082 3) printing out the instruction by calling the printer functions
4083 shared with the disassembler.
4085 The limitation of this method is that the exact input assembly
4086 line cannot be accurately reproduced in some cases, for example an
4087 optional operand present in the actual assembly line will be
4088 omitted in the output; likewise for the optional syntax rules,
4089 e.g. the # before the immediate. Another limitation is that the
4090 assembly symbols and relocation operations in the assembly line
4091 currently cannot be printed out in the error report. Last but not
4092 least, when there is other error(s) co-exist with this error, the
4093 'corrected' instruction may be still incorrect, e.g. given
4094 'ldnp h0,h1,[x0,#6]!'
4095 this diagnosis will provide the version:
4096 'ldnp s0,s1,[x0,#6]!'
4097 which is still not right. */
4098 size_t len
= strlen (get_mnemonic_name (str
));
4101 const size_t size
= 2048;
4103 aarch64_inst
*inst_base
= &inst
.base
;
4104 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4107 reset_aarch64_instruction (&inst
);
4108 inst_base
->opcode
= opcode
;
4110 /* Reset the error report so that there is no side effect on the
4111 following operand parsing. */
4112 init_operand_error_report ();
4115 result
= parse_operands (str
+ len
, opcode
)
4116 && programmer_friendly_fixup (&inst
);
4117 gas_assert (result
);
4118 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4120 gas_assert (!result
);
4122 /* Find the most matched qualifier sequence. */
4123 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4124 gas_assert (qlf_idx
> -1);
4126 /* Assign the qualifiers. */
4127 assign_qualifier_sequence (inst_base
,
4128 opcode
->qualifiers_list
[qlf_idx
]);
4130 /* Print the hint. */
4131 output_info (_(" did you mean this?"));
4132 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4133 print_operands (buf
, opcode
, inst_base
->operands
);
4134 output_info (_(" %s"), buf
);
4136 /* Print out other variant(s) if there is any. */
4138 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4139 output_info (_(" other valid variant(s):"));
4141 /* For each pattern. */
4142 qualifiers_list
= opcode
->qualifiers_list
;
4143 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4145 /* Most opcodes has much fewer patterns in the list.
4146 First NIL qualifier indicates the end in the list. */
4147 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4152 /* Mnemonics name. */
4153 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4155 /* Assign the qualifiers. */
4156 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4158 /* Print instruction. */
4159 print_operands (buf
, opcode
, inst_base
->operands
);
4161 output_info (_(" %s"), buf
);
4167 case AARCH64_OPDE_OUT_OF_RANGE
:
4168 if (detail
->data
[0] != detail
->data
[1])
4169 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4170 detail
->error
? detail
->error
: _("immediate value"),
4171 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4173 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4174 detail
->error
? detail
->error
: _("immediate value"),
4175 detail
->data
[0], idx
+ 1, str
);
4178 case AARCH64_OPDE_REG_LIST
:
4179 if (detail
->data
[0] == 1)
4180 as_bad (_("invalid number of registers in the list; "
4181 "only 1 register is expected at operand %d -- `%s'"),
4184 as_bad (_("invalid number of registers in the list; "
4185 "%d registers are expected at operand %d -- `%s'"),
4186 detail
->data
[0], idx
+ 1, str
);
4189 case AARCH64_OPDE_UNALIGNED
:
4190 as_bad (_("immediate value should be a multiple of "
4191 "%d at operand %d -- `%s'"),
4192 detail
->data
[0], idx
+ 1, str
);
4201 /* Process and output the error message about the operand mismatching.
4203 When this function is called, the operand error information had
4204 been collected for an assembly line and there will be multiple
4205 errors in the case of mulitple instruction templates; output the
4206 error message that most closely describes the problem. */
4209 output_operand_error_report (char *str
)
4211 int largest_error_pos
;
4212 const char *msg
= NULL
;
4213 enum aarch64_operand_error_kind kind
;
4214 operand_error_record
*curr
;
4215 operand_error_record
*head
= operand_error_report
.head
;
4216 operand_error_record
*record
= NULL
;
4218 /* No error to report. */
4222 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4224 /* Only one error. */
4225 if (head
== operand_error_report
.tail
)
4227 DEBUG_TRACE ("single opcode entry with error kind: %s",
4228 operand_mismatch_kind_names
[head
->detail
.kind
]);
4229 output_operand_error_record (head
, str
);
4233 /* Find the error kind of the highest severity. */
4234 DEBUG_TRACE ("multiple opcode entres with error kind");
4235 kind
= AARCH64_OPDE_NIL
;
4236 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4238 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4239 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4240 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4241 kind
= curr
->detail
.kind
;
4243 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4245 /* Pick up one of errors of KIND to report. */
4246 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4247 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4249 if (curr
->detail
.kind
!= kind
)
4251 /* If there are multiple errors, pick up the one with the highest
4252 mismatching operand index. In the case of multiple errors with
4253 the equally highest operand index, pick up the first one or the
4254 first one with non-NULL error message. */
4255 if (curr
->detail
.index
> largest_error_pos
4256 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4257 && curr
->detail
.error
!= NULL
))
4259 largest_error_pos
= curr
->detail
.index
;
4261 msg
= record
->detail
.error
;
4265 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4266 DEBUG_TRACE ("Pick up error kind %s to report",
4267 operand_mismatch_kind_names
[record
->detail
.kind
]);
4270 output_operand_error_record (record
, str
);
4273 /* Write an AARCH64 instruction to buf - always little-endian. */
4275 put_aarch64_insn (char *buf
, uint32_t insn
)
4277 unsigned char *where
= (unsigned char *) buf
;
4279 where
[1] = insn
>> 8;
4280 where
[2] = insn
>> 16;
4281 where
[3] = insn
>> 24;
4285 get_aarch64_insn (char *buf
)
4287 unsigned char *where
= (unsigned char *) buf
;
4289 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4294 output_inst (struct aarch64_inst
*new_inst
)
4298 to
= frag_more (INSN_SIZE
);
4300 frag_now
->tc_frag_data
.recorded
= 1;
4302 put_aarch64_insn (to
, inst
.base
.value
);
4304 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4306 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4307 INSN_SIZE
, &inst
.reloc
.exp
,
4310 DEBUG_TRACE ("Prepared relocation fix up");
4311 /* Don't check the addend value against the instruction size,
4312 that's the job of our code in md_apply_fix(). */
4313 fixp
->fx_no_overflow
= 1;
4314 if (new_inst
!= NULL
)
4315 fixp
->tc_fix_data
.inst
= new_inst
;
4316 if (aarch64_gas_internal_fixup_p ())
4318 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4319 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4320 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4324 dwarf2_emit_insn (INSN_SIZE
);
4327 /* Link together opcodes of the same name. */
4331 aarch64_opcode
*opcode
;
4332 struct templates
*next
;
4335 typedef struct templates templates
;
4338 lookup_mnemonic (const char *start
, int len
)
4340 templates
*templ
= NULL
;
4342 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4346 /* Subroutine of md_assemble, responsible for looking up the primary
4347 opcode from the mnemonic the user wrote. STR points to the
4348 beginning of the mnemonic. */
4351 opcode_lookup (char **str
)
4354 const aarch64_cond
*cond
;
4358 /* Scan up to the end of the mnemonic, which must end in white space,
4359 '.', or end of string. */
4360 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4367 inst
.cond
= COND_ALWAYS
;
4369 /* Handle a possible condition. */
4372 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4375 inst
.cond
= cond
->value
;
4389 if (inst
.cond
== COND_ALWAYS
)
4391 /* Look for unaffixed mnemonic. */
4392 return lookup_mnemonic (base
, len
);
4396 /* append ".c" to mnemonic if conditional */
4397 memcpy (condname
, base
, len
);
4398 memcpy (condname
+ len
, ".c", 2);
4401 return lookup_mnemonic (base
, len
);
4407 /* Internal helper routine converting a vector neon_type_el structure
4408 *VECTYPE to a corresponding operand qualifier. */
4410 static inline aarch64_opnd_qualifier_t
4411 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4413 /* Element size in bytes indexed by neon_el_type. */
4414 const unsigned char ele_size
[5]
4417 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4418 goto vectype_conversion_fail
;
4420 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4422 if (vectype
->defined
& NTA_HASINDEX
)
4423 /* Vector element register. */
4424 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4427 /* Vector register. */
4428 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4430 if (reg_size
!= 16 && reg_size
!= 8)
4431 goto vectype_conversion_fail
;
4432 /* The conversion is calculated based on the relation of the order of
4433 qualifiers to the vector element size and vector register size. */
4434 offset
= (vectype
->type
== NT_q
)
4435 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4436 gas_assert (offset
<= 8);
4437 return AARCH64_OPND_QLF_V_8B
+ offset
;
4440 vectype_conversion_fail
:
4441 first_error (_("bad vector arrangement type"));
4442 return AARCH64_OPND_QLF_NIL
;
4445 /* Process an optional operand that is found omitted from the assembly line.
4446 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4447 instruction's opcode entry while IDX is the index of this omitted operand.
4451 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4452 int idx
, aarch64_opnd_info
*operand
)
4454 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4455 gas_assert (optional_operand_p (opcode
, idx
));
4456 gas_assert (!operand
->present
);
4460 case AARCH64_OPND_Rd
:
4461 case AARCH64_OPND_Rn
:
4462 case AARCH64_OPND_Rm
:
4463 case AARCH64_OPND_Rt
:
4464 case AARCH64_OPND_Rt2
:
4465 case AARCH64_OPND_Rs
:
4466 case AARCH64_OPND_Ra
:
4467 case AARCH64_OPND_Rt_SYS
:
4468 case AARCH64_OPND_Rd_SP
:
4469 case AARCH64_OPND_Rn_SP
:
4470 case AARCH64_OPND_Fd
:
4471 case AARCH64_OPND_Fn
:
4472 case AARCH64_OPND_Fm
:
4473 case AARCH64_OPND_Fa
:
4474 case AARCH64_OPND_Ft
:
4475 case AARCH64_OPND_Ft2
:
4476 case AARCH64_OPND_Sd
:
4477 case AARCH64_OPND_Sn
:
4478 case AARCH64_OPND_Sm
:
4479 case AARCH64_OPND_Vd
:
4480 case AARCH64_OPND_Vn
:
4481 case AARCH64_OPND_Vm
:
4482 case AARCH64_OPND_VdD1
:
4483 case AARCH64_OPND_VnD1
:
4484 operand
->reg
.regno
= default_value
;
4487 case AARCH64_OPND_Ed
:
4488 case AARCH64_OPND_En
:
4489 case AARCH64_OPND_Em
:
4490 operand
->reglane
.regno
= default_value
;
4493 case AARCH64_OPND_IDX
:
4494 case AARCH64_OPND_BIT_NUM
:
4495 case AARCH64_OPND_IMMR
:
4496 case AARCH64_OPND_IMMS
:
4497 case AARCH64_OPND_SHLL_IMM
:
4498 case AARCH64_OPND_IMM_VLSL
:
4499 case AARCH64_OPND_IMM_VLSR
:
4500 case AARCH64_OPND_CCMP_IMM
:
4501 case AARCH64_OPND_FBITS
:
4502 case AARCH64_OPND_UIMM4
:
4503 case AARCH64_OPND_UIMM3_OP1
:
4504 case AARCH64_OPND_UIMM3_OP2
:
4505 case AARCH64_OPND_IMM
:
4506 case AARCH64_OPND_WIDTH
:
4507 case AARCH64_OPND_UIMM7
:
4508 case AARCH64_OPND_NZCV
:
4509 operand
->imm
.value
= default_value
;
4512 case AARCH64_OPND_EXCEPTION
:
4513 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4516 case AARCH64_OPND_BARRIER_ISB
:
4517 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4524 /* Process the relocation type for move wide instructions.
4525 Return TRUE on success; otherwise return FALSE. */
4528 process_movw_reloc_info (void)
4533 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4535 if (inst
.base
.opcode
->op
== OP_MOVK
)
4536 switch (inst
.reloc
.type
)
4538 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4539 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4540 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4541 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4542 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4543 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4545 (_("the specified relocation type is not allowed for MOVK"));
4551 switch (inst
.reloc
.type
)
4553 case BFD_RELOC_AARCH64_MOVW_G0
:
4554 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4555 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4556 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4557 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4560 case BFD_RELOC_AARCH64_MOVW_G1
:
4561 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4562 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4563 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4564 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4567 case BFD_RELOC_AARCH64_MOVW_G2
:
4568 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4569 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4570 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4573 set_fatal_syntax_error
4574 (_("the specified relocation type is not allowed for 32-bit "
4580 case BFD_RELOC_AARCH64_MOVW_G3
:
4583 set_fatal_syntax_error
4584 (_("the specified relocation type is not allowed for 32-bit "
4591 /* More cases should be added when more MOVW-related relocation types
4592 are supported in GAS. */
4593 gas_assert (aarch64_gas_internal_fixup_p ());
4594 /* The shift amount should have already been set by the parser. */
4597 inst
.base
.operands
[1].shifter
.amount
= shift
;
4601 /* A primitive log caculator. */
4603 static inline unsigned int
4604 get_logsz (unsigned int size
)
4606 const unsigned char ls
[16] =
4607 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4613 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4614 return ls
[size
- 1];
4617 /* Determine and return the real reloc type code for an instruction
4618 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4620 static inline bfd_reloc_code_real_type
4621 ldst_lo12_determine_real_reloc_type (void)
4624 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4625 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4627 const bfd_reloc_code_real_type reloc_ldst_lo12
[5] = {
4628 BFD_RELOC_AARCH64_LDST8_LO12
, BFD_RELOC_AARCH64_LDST16_LO12
,
4629 BFD_RELOC_AARCH64_LDST32_LO12
, BFD_RELOC_AARCH64_LDST64_LO12
,
4630 BFD_RELOC_AARCH64_LDST128_LO12
4633 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
);
4634 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4636 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4638 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4640 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4642 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4643 gas_assert (logsz
>= 0 && logsz
<= 4);
4645 return reloc_ldst_lo12
[logsz
];
4648 /* Check whether a register list REGINFO is valid. The registers must be
4649 numbered in increasing order (modulo 32), in increments of one or two.
4651 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4654 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4657 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4659 uint32_t i
, nb_regs
, prev_regno
, incr
;
4661 nb_regs
= 1 + (reginfo
& 0x3);
4663 prev_regno
= reginfo
& 0x1f;
4664 incr
= accept_alternate
? 2 : 1;
4666 for (i
= 1; i
< nb_regs
; ++i
)
4668 uint32_t curr_regno
;
4670 curr_regno
= reginfo
& 0x1f;
4671 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4673 prev_regno
= curr_regno
;
4679 /* Generic instruction operand parser. This does no encoding and no
4680 semantic validation; it merely squirrels values away in the inst
4681 structure. Returns TRUE or FALSE depending on whether the
4682 specified grammar matched. */
4685 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4688 char *backtrack_pos
= 0;
4689 const enum aarch64_opnd
*operands
= opcode
->operands
;
4692 skip_whitespace (str
);
4694 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4697 int isreg32
, isregzero
;
4698 int comma_skipped_p
= 0;
4699 aarch64_reg_type rtype
;
4700 struct neon_type_el vectype
;
4701 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4703 DEBUG_TRACE ("parse operand %d", i
);
4705 /* Assign the operand code. */
4706 info
->type
= operands
[i
];
4708 if (optional_operand_p (opcode
, i
))
4710 /* Remember where we are in case we need to backtrack. */
4711 gas_assert (!backtrack_pos
);
4712 backtrack_pos
= str
;
4715 /* Expect comma between operands; the backtrack mechanizm will take
4716 care of cases of omitted optional operand. */
4717 if (i
> 0 && ! skip_past_char (&str
, ','))
4719 set_syntax_error (_("comma expected between operands"));
4723 comma_skipped_p
= 1;
4725 switch (operands
[i
])
4727 case AARCH64_OPND_Rd
:
4728 case AARCH64_OPND_Rn
:
4729 case AARCH64_OPND_Rm
:
4730 case AARCH64_OPND_Rt
:
4731 case AARCH64_OPND_Rt2
:
4732 case AARCH64_OPND_Rs
:
4733 case AARCH64_OPND_Ra
:
4734 case AARCH64_OPND_Rt_SYS
:
4735 case AARCH64_OPND_PAIRREG
:
4736 po_int_reg_or_fail (1, 0);
4739 case AARCH64_OPND_Rd_SP
:
4740 case AARCH64_OPND_Rn_SP
:
4741 po_int_reg_or_fail (0, 1);
4744 case AARCH64_OPND_Rm_EXT
:
4745 case AARCH64_OPND_Rm_SFT
:
4746 po_misc_or_fail (parse_shifter_operand
4747 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4749 : SHIFTED_LOGIC_IMM
)));
4750 if (!info
->shifter
.operator_present
)
4752 /* Default to LSL if not present. Libopcodes prefers shifter
4753 kind to be explicit. */
4754 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4755 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4756 /* For Rm_EXT, libopcodes will carry out further check on whether
4757 or not stack pointer is used in the instruction (Recall that
4758 "the extend operator is not optional unless at least one of
4759 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4763 case AARCH64_OPND_Fd
:
4764 case AARCH64_OPND_Fn
:
4765 case AARCH64_OPND_Fm
:
4766 case AARCH64_OPND_Fa
:
4767 case AARCH64_OPND_Ft
:
4768 case AARCH64_OPND_Ft2
:
4769 case AARCH64_OPND_Sd
:
4770 case AARCH64_OPND_Sn
:
4771 case AARCH64_OPND_Sm
:
4772 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4773 if (val
== PARSE_FAIL
)
4775 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4778 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4780 info
->reg
.regno
= val
;
4781 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4784 case AARCH64_OPND_Vd
:
4785 case AARCH64_OPND_Vn
:
4786 case AARCH64_OPND_Vm
:
4787 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4788 if (val
== PARSE_FAIL
)
4790 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4793 if (vectype
.defined
& NTA_HASINDEX
)
4796 info
->reg
.regno
= val
;
4797 info
->qualifier
= vectype_to_qualifier (&vectype
);
4798 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4802 case AARCH64_OPND_VdD1
:
4803 case AARCH64_OPND_VnD1
:
4804 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4805 if (val
== PARSE_FAIL
)
4807 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4810 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4812 set_fatal_syntax_error
4813 (_("the top half of a 128-bit FP/SIMD register is expected"));
4816 info
->reg
.regno
= val
;
4817 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4818 here; it is correct for the purpose of encoding/decoding since
4819 only the register number is explicitly encoded in the related
4820 instructions, although this appears a bit hacky. */
4821 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4824 case AARCH64_OPND_Ed
:
4825 case AARCH64_OPND_En
:
4826 case AARCH64_OPND_Em
:
4827 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4828 if (val
== PARSE_FAIL
)
4830 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4833 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
4836 info
->reglane
.regno
= val
;
4837 info
->reglane
.index
= vectype
.index
;
4838 info
->qualifier
= vectype_to_qualifier (&vectype
);
4839 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4843 case AARCH64_OPND_LVn
:
4844 case AARCH64_OPND_LVt
:
4845 case AARCH64_OPND_LVt_AL
:
4846 case AARCH64_OPND_LEt
:
4847 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
4849 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
4851 set_fatal_syntax_error (_("invalid register list"));
4854 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
4855 info
->reglist
.num_regs
= (val
& 0x3) + 1;
4856 if (operands
[i
] == AARCH64_OPND_LEt
)
4858 if (!(vectype
.defined
& NTA_HASINDEX
))
4860 info
->reglist
.has_index
= 1;
4861 info
->reglist
.index
= vectype
.index
;
4863 else if (!(vectype
.defined
& NTA_HASTYPE
))
4865 info
->qualifier
= vectype_to_qualifier (&vectype
);
4866 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4870 case AARCH64_OPND_Cn
:
4871 case AARCH64_OPND_Cm
:
4872 po_reg_or_fail (REG_TYPE_CN
);
4875 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
4878 inst
.base
.operands
[i
].reg
.regno
= val
;
4881 case AARCH64_OPND_SHLL_IMM
:
4882 case AARCH64_OPND_IMM_VLSR
:
4883 po_imm_or_fail (1, 64);
4884 info
->imm
.value
= val
;
4887 case AARCH64_OPND_CCMP_IMM
:
4888 case AARCH64_OPND_FBITS
:
4889 case AARCH64_OPND_UIMM4
:
4890 case AARCH64_OPND_UIMM3_OP1
:
4891 case AARCH64_OPND_UIMM3_OP2
:
4892 case AARCH64_OPND_IMM_VLSL
:
4893 case AARCH64_OPND_IMM
:
4894 case AARCH64_OPND_WIDTH
:
4895 po_imm_nc_or_fail ();
4896 info
->imm
.value
= val
;
4899 case AARCH64_OPND_UIMM7
:
4900 po_imm_or_fail (0, 127);
4901 info
->imm
.value
= val
;
4904 case AARCH64_OPND_IDX
:
4905 case AARCH64_OPND_BIT_NUM
:
4906 case AARCH64_OPND_IMMR
:
4907 case AARCH64_OPND_IMMS
:
4908 po_imm_or_fail (0, 63);
4909 info
->imm
.value
= val
;
4912 case AARCH64_OPND_IMM0
:
4913 po_imm_nc_or_fail ();
4916 set_fatal_syntax_error (_("immediate zero expected"));
4919 info
->imm
.value
= 0;
4922 case AARCH64_OPND_FPIMM0
:
4925 bfd_boolean res1
= FALSE
, res2
= FALSE
;
4926 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4927 it is probably not worth the effort to support it. */
4928 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
4929 && !(res2
= parse_constant_immediate (&str
, &val
)))
4931 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
4933 info
->imm
.value
= 0;
4934 info
->imm
.is_fp
= 1;
4937 set_fatal_syntax_error (_("immediate zero expected"));
4941 case AARCH64_OPND_IMM_MOV
:
4944 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
4945 reg_name_p (str
, REG_TYPE_VN
))
4948 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
4950 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4951 later. fix_mov_imm_insn will try to determine a machine
4952 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4953 message if the immediate cannot be moved by a single
4955 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
4956 inst
.base
.operands
[i
].skip
= 1;
4960 case AARCH64_OPND_SIMD_IMM
:
4961 case AARCH64_OPND_SIMD_IMM_SFT
:
4962 if (! parse_big_immediate (&str
, &val
))
4964 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4966 /* need_libopcodes_p */ 1,
4969 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4970 shift, we don't check it here; we leave the checking to
4971 the libopcodes (operand_general_constraint_met_p). By
4972 doing this, we achieve better diagnostics. */
4973 if (skip_past_comma (&str
)
4974 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
4976 if (!info
->shifter
.operator_present
4977 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
4979 /* Default to LSL if not present. Libopcodes prefers shifter
4980 kind to be explicit. */
4981 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4982 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4986 case AARCH64_OPND_FPIMM
:
4987 case AARCH64_OPND_SIMD_FPIMM
:
4991 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
4993 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
4997 set_fatal_syntax_error (_("invalid floating-point constant"));
5000 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5001 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5005 case AARCH64_OPND_LIMM
:
5006 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5007 SHIFTED_LOGIC_IMM
));
5008 if (info
->shifter
.operator_present
)
5010 set_fatal_syntax_error
5011 (_("shift not allowed for bitmask immediate"));
5014 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5016 /* need_libopcodes_p */ 1,
5020 case AARCH64_OPND_AIMM
:
5021 if (opcode
->op
== OP_ADD
)
5022 /* ADD may have relocation types. */
5023 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5024 SHIFTED_ARITH_IMM
));
5026 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5027 SHIFTED_ARITH_IMM
));
5028 switch (inst
.reloc
.type
)
5030 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5031 info
->shifter
.amount
= 12;
5033 case BFD_RELOC_UNUSED
:
5034 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5035 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5036 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5037 inst
.reloc
.pc_rel
= 0;
5042 info
->imm
.value
= 0;
5043 if (!info
->shifter
.operator_present
)
5045 /* Default to LSL if not present. Libopcodes prefers shifter
5046 kind to be explicit. */
5047 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5048 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5052 case AARCH64_OPND_HALF
:
5054 /* #<imm16> or relocation. */
5055 int internal_fixup_p
;
5056 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5057 if (internal_fixup_p
)
5058 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5059 skip_whitespace (str
);
5060 if (skip_past_comma (&str
))
5062 /* {, LSL #<shift>} */
5063 if (! aarch64_gas_internal_fixup_p ())
5065 set_fatal_syntax_error (_("can't mix relocation modifier "
5066 "with explicit shift"));
5069 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5072 inst
.base
.operands
[i
].shifter
.amount
= 0;
5073 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5074 inst
.base
.operands
[i
].imm
.value
= 0;
5075 if (! process_movw_reloc_info ())
5080 case AARCH64_OPND_EXCEPTION
:
5081 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5082 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5084 /* need_libopcodes_p */ 0,
5088 case AARCH64_OPND_NZCV
:
5090 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5094 info
->imm
.value
= nzcv
->value
;
5097 po_imm_or_fail (0, 15);
5098 info
->imm
.value
= val
;
5102 case AARCH64_OPND_COND
:
5103 case AARCH64_OPND_COND1
:
5104 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5106 if (info
->cond
== NULL
)
5108 set_syntax_error (_("invalid condition"));
5111 else if (operands
[i
] == AARCH64_OPND_COND1
5112 && (info
->cond
->value
& 0xe) == 0xe)
5114 /* Not allow AL or NV. */
5115 set_default_error ();
5120 case AARCH64_OPND_ADDR_ADRP
:
5121 po_misc_or_fail (parse_adrp (&str
));
5122 /* Clear the value as operand needs to be relocated. */
5123 info
->imm
.value
= 0;
5126 case AARCH64_OPND_ADDR_PCREL14
:
5127 case AARCH64_OPND_ADDR_PCREL19
:
5128 case AARCH64_OPND_ADDR_PCREL21
:
5129 case AARCH64_OPND_ADDR_PCREL26
:
5130 po_misc_or_fail (parse_address_reloc (&str
, info
));
5131 if (!info
->addr
.pcrel
)
5133 set_syntax_error (_("invalid pc-relative address"));
5136 if (inst
.gen_lit_pool
5137 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5139 /* Only permit "=value" in the literal load instructions.
5140 The literal will be generated by programmer_friendly_fixup. */
5141 set_syntax_error (_("invalid use of \"=immediate\""));
5144 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5146 set_syntax_error (_("unrecognized relocation suffix"));
5149 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5151 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5152 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5156 info
->imm
.value
= 0;
5157 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5158 switch (opcode
->iclass
)
5162 /* e.g. CBZ or B.COND */
5163 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5164 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5168 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5169 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5173 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5175 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5176 : BFD_RELOC_AARCH64_JUMP26
;
5179 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5180 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5183 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5184 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5190 inst
.reloc
.pc_rel
= 1;
5194 case AARCH64_OPND_ADDR_SIMPLE
:
5195 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5196 /* [<Xn|SP>{, #<simm>}] */
5197 po_char_or_fail ('[');
5198 po_reg_or_fail (REG_TYPE_R64_SP
);
5199 /* Accept optional ", #0". */
5200 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5201 && skip_past_char (&str
, ','))
5203 skip_past_char (&str
, '#');
5204 if (! skip_past_char (&str
, '0'))
5206 set_fatal_syntax_error
5207 (_("the optional immediate offset can only be 0"));
5211 po_char_or_fail (']');
5212 info
->addr
.base_regno
= val
;
5215 case AARCH64_OPND_ADDR_REGOFF
:
5216 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5217 po_misc_or_fail (parse_address (&str
, info
, 0));
5218 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5219 || !info
->addr
.preind
|| info
->addr
.postind
5220 || info
->addr
.writeback
)
5222 set_syntax_error (_("invalid addressing mode"));
5225 if (!info
->shifter
.operator_present
)
5227 /* Default to LSL if not present. Libopcodes prefers shifter
5228 kind to be explicit. */
5229 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5230 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5232 /* Qualifier to be deduced by libopcodes. */
5235 case AARCH64_OPND_ADDR_SIMM7
:
5236 po_misc_or_fail (parse_address (&str
, info
, 0));
5237 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5238 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5240 set_syntax_error (_("invalid addressing mode"));
5243 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5245 /* need_libopcodes_p */ 1,
5249 case AARCH64_OPND_ADDR_SIMM9
:
5250 case AARCH64_OPND_ADDR_SIMM9_2
:
5251 po_misc_or_fail (parse_address_reloc (&str
, info
));
5252 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5253 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5254 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5255 && info
->addr
.writeback
))
5257 set_syntax_error (_("invalid addressing mode"));
5260 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5262 set_syntax_error (_("relocation not allowed"));
5265 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5267 /* need_libopcodes_p */ 1,
5271 case AARCH64_OPND_ADDR_UIMM12
:
5272 po_misc_or_fail (parse_address_reloc (&str
, info
));
5273 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5274 || !info
->addr
.preind
|| info
->addr
.writeback
)
5276 set_syntax_error (_("invalid addressing mode"));
5279 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5280 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5281 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
)
5282 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5283 /* Leave qualifier to be determined by libopcodes. */
5286 case AARCH64_OPND_SIMD_ADDR_POST
:
5287 /* [<Xn|SP>], <Xm|#<amount>> */
5288 po_misc_or_fail (parse_address (&str
, info
, 1));
5289 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5291 set_syntax_error (_("invalid addressing mode"));
5294 if (!info
->addr
.offset
.is_reg
)
5296 if (inst
.reloc
.exp
.X_op
== O_constant
)
5297 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5300 set_fatal_syntax_error
5301 (_("writeback value should be an immediate constant"));
5308 case AARCH64_OPND_SYSREG
:
5309 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1))
5312 set_syntax_error (_("unknown or missing system register name"));
5315 inst
.base
.operands
[i
].sysreg
= val
;
5318 case AARCH64_OPND_PSTATEFIELD
:
5319 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0))
5322 set_syntax_error (_("unknown or missing PSTATE field name"));
5325 inst
.base
.operands
[i
].pstatefield
= val
;
5328 case AARCH64_OPND_SYSREG_IC
:
5329 inst
.base
.operands
[i
].sysins_op
=
5330 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5332 case AARCH64_OPND_SYSREG_DC
:
5333 inst
.base
.operands
[i
].sysins_op
=
5334 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5336 case AARCH64_OPND_SYSREG_AT
:
5337 inst
.base
.operands
[i
].sysins_op
=
5338 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5340 case AARCH64_OPND_SYSREG_TLBI
:
5341 inst
.base
.operands
[i
].sysins_op
=
5342 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5344 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5346 set_fatal_syntax_error ( _("unknown or missing operation name"));
5351 case AARCH64_OPND_BARRIER
:
5352 case AARCH64_OPND_BARRIER_ISB
:
5353 val
= parse_barrier (&str
);
5354 if (val
!= PARSE_FAIL
5355 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5357 /* ISB only accepts options name 'sy'. */
5359 (_("the specified option is not accepted in ISB"));
5360 /* Turn off backtrack as this optional operand is present. */
5364 /* This is an extension to accept a 0..15 immediate. */
5365 if (val
== PARSE_FAIL
)
5366 po_imm_or_fail (0, 15);
5367 info
->barrier
= aarch64_barrier_options
+ val
;
5370 case AARCH64_OPND_PRFOP
:
5371 val
= parse_pldop (&str
);
5372 /* This is an extension to accept a 0..31 immediate. */
5373 if (val
== PARSE_FAIL
)
5374 po_imm_or_fail (0, 31);
5375 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5379 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5382 /* If we get here, this operand was successfully parsed. */
5383 inst
.base
.operands
[i
].present
= 1;
5387 /* The parse routine should already have set the error, but in case
5388 not, set a default one here. */
5390 set_default_error ();
5392 if (! backtrack_pos
)
5393 goto parse_operands_return
;
5396 /* We reach here because this operand is marked as optional, and
5397 either no operand was supplied or the operand was supplied but it
5398 was syntactically incorrect. In the latter case we report an
5399 error. In the former case we perform a few more checks before
5400 dropping through to the code to insert the default operand. */
5402 char *tmp
= backtrack_pos
;
5403 char endchar
= END_OF_INSN
;
5405 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5407 skip_past_char (&tmp
, ',');
5409 if (*tmp
!= endchar
)
5410 /* The user has supplied an operand in the wrong format. */
5411 goto parse_operands_return
;
5413 /* Make sure there is not a comma before the optional operand.
5414 For example the fifth operand of 'sys' is optional:
5416 sys #0,c0,c0,#0, <--- wrong
5417 sys #0,c0,c0,#0 <--- correct. */
5418 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5420 set_fatal_syntax_error
5421 (_("unexpected comma before the omitted optional operand"));
5422 goto parse_operands_return
;
5426 /* Reaching here means we are dealing with an optional operand that is
5427 omitted from the assembly line. */
5428 gas_assert (optional_operand_p (opcode
, i
));
5430 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5432 /* Try again, skipping the optional operand at backtrack_pos. */
5433 str
= backtrack_pos
;
5436 /* Clear any error record after the omitted optional operand has been
5437 successfully handled. */
5441 /* Check if we have parsed all the operands. */
5442 if (*str
!= '\0' && ! error_p ())
5444 /* Set I to the index of the last present operand; this is
5445 for the purpose of diagnostics. */
5446 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5448 set_fatal_syntax_error
5449 (_("unexpected characters following instruction"));
5452 parse_operands_return
:
5456 DEBUG_TRACE ("parsing FAIL: %s - %s",
5457 operand_mismatch_kind_names
[get_error_kind ()],
5458 get_error_message ());
5459 /* Record the operand error properly; this is useful when there
5460 are multiple instruction templates for a mnemonic name, so that
5461 later on, we can select the error that most closely describes
5463 record_operand_error (opcode
, i
, get_error_kind (),
5464 get_error_message ());
5469 DEBUG_TRACE ("parsing SUCCESS");
5474 /* It does some fix-up to provide some programmer friendly feature while
5475 keeping the libopcodes happy, i.e. libopcodes only accepts
5476 the preferred architectural syntax.
5477 Return FALSE if there is any failure; otherwise return TRUE. */
5480 programmer_friendly_fixup (aarch64_instruction
*instr
)
5482 aarch64_inst
*base
= &instr
->base
;
5483 const aarch64_opcode
*opcode
= base
->opcode
;
5484 enum aarch64_op op
= opcode
->op
;
5485 aarch64_opnd_info
*operands
= base
->operands
;
5487 DEBUG_TRACE ("enter");
5489 switch (opcode
->iclass
)
5492 /* TBNZ Xn|Wn, #uimm6, label
5493 Test and Branch Not Zero: conditionally jumps to label if bit number
5494 uimm6 in register Xn is not zero. The bit number implies the width of
5495 the register, which may be written and should be disassembled as Wn if
5496 uimm is less than 32. */
5497 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5499 if (operands
[1].imm
.value
>= 32)
5501 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5505 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5509 /* LDR Wt, label | =value
5510 As a convenience assemblers will typically permit the notation
5511 "=value" in conjunction with the pc-relative literal load instructions
5512 to automatically place an immediate value or symbolic address in a
5513 nearby literal pool and generate a hidden label which references it.
5514 ISREG has been set to 0 in the case of =value. */
5515 if (instr
->gen_lit_pool
5516 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5518 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5519 if (op
== OP_LDRSW_LIT
)
5521 if (instr
->reloc
.exp
.X_op
!= O_constant
5522 && instr
->reloc
.exp
.X_op
!= O_big
5523 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5525 record_operand_error (opcode
, 1,
5526 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5527 _("constant expression expected"));
5530 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5532 record_operand_error (opcode
, 1,
5533 AARCH64_OPDE_OTHER_ERROR
,
5534 _("literal pool insertion failed"));
5542 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5543 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5544 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5545 A programmer-friendly assembler should accept a destination Xd in
5546 place of Wd, however that is not the preferred form for disassembly.
5548 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5549 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5550 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5551 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5556 /* In the 64-bit form, the final register operand is written as Wm
5557 for all but the (possibly omitted) UXTX/LSL and SXTX
5559 As a programmer-friendly assembler, we accept e.g.
5560 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5561 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5562 int idx
= aarch64_operand_index (opcode
->operands
,
5563 AARCH64_OPND_Rm_EXT
);
5564 gas_assert (idx
== 1 || idx
== 2);
5565 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5566 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5567 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5568 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5569 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5570 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5578 DEBUG_TRACE ("exit with SUCCESS");
5582 /* Check for loads and stores that will cause unpredictable behavior. */
5585 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5587 aarch64_inst
*base
= &instr
->base
;
5588 const aarch64_opcode
*opcode
= base
->opcode
;
5589 const aarch64_opnd_info
*opnds
= base
->operands
;
5590 switch (opcode
->iclass
)
5596 /* Loading/storing the base register is unpredictable if writeback. */
5597 if ((aarch64_get_operand_class (opnds
[0].type
)
5598 == AARCH64_OPND_CLASS_INT_REG
)
5599 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5600 && opnds
[1].addr
.base_regno
!= REG_SP
5601 && opnds
[1].addr
.writeback
)
5602 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5605 case ldstnapair_offs
:
5606 case ldstpair_indexed
:
5607 /* Loading/storing the base register is unpredictable if writeback. */
5608 if ((aarch64_get_operand_class (opnds
[0].type
)
5609 == AARCH64_OPND_CLASS_INT_REG
)
5610 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5611 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5612 && opnds
[2].addr
.base_regno
!= REG_SP
5613 && opnds
[2].addr
.writeback
)
5614 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5615 /* Load operations must load different registers. */
5616 if ((opcode
->opcode
& (1 << 22))
5617 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5618 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5625 /* A wrapper function to interface with libopcodes on encoding and
5626 record the error message if there is any.
5628 Return TRUE on success; otherwise return FALSE. */
5631 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5634 aarch64_operand_error error_info
;
5635 error_info
.kind
= AARCH64_OPDE_NIL
;
5636 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5640 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5641 record_operand_error_info (opcode
, &error_info
);
5646 #ifdef DEBUG_AARCH64
5648 dump_opcode_operands (const aarch64_opcode
*opcode
)
5651 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5653 aarch64_verbose ("\t\t opnd%d: %s", i
,
5654 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5655 ? aarch64_get_operand_name (opcode
->operands
[i
])
5656 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5660 #endif /* DEBUG_AARCH64 */
5662 /* This is the guts of the machine-dependent assembler. STR points to a
5663 machine dependent instruction. This function is supposed to emit
5664 the frags/bytes it assembles to. */
5667 md_assemble (char *str
)
5670 templates
*template;
5671 aarch64_opcode
*opcode
;
5672 aarch64_inst
*inst_base
;
5673 unsigned saved_cond
;
5675 /* Align the previous label if needed. */
5676 if (last_label_seen
!= NULL
)
5678 symbol_set_frag (last_label_seen
, frag_now
);
5679 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5680 S_SET_SEGMENT (last_label_seen
, now_seg
);
5683 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5685 DEBUG_TRACE ("\n\n");
5686 DEBUG_TRACE ("==============================");
5687 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5689 template = opcode_lookup (&p
);
5692 /* It wasn't an instruction, but it might be a register alias of
5693 the form alias .req reg directive. */
5694 if (!create_register_alias (str
, p
))
5695 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5700 skip_whitespace (p
);
5703 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5704 get_mnemonic_name (str
), str
);
5708 init_operand_error_report ();
5710 /* Sections are assumed to start aligned. In executable section, there is no
5711 MAP_DATA symbol pending. So we only align the address during
5712 MAP_DATA --> MAP_INSN transition.
5713 For other sections, this is not guaranteed. */
5714 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
5715 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
5716 frag_align_code (2, 0);
5718 saved_cond
= inst
.cond
;
5719 reset_aarch64_instruction (&inst
);
5720 inst
.cond
= saved_cond
;
5722 /* Iterate through all opcode entries with the same mnemonic name. */
5725 opcode
= template->opcode
;
5727 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5728 #ifdef DEBUG_AARCH64
5730 dump_opcode_operands (opcode
);
5731 #endif /* DEBUG_AARCH64 */
5733 mapping_state (MAP_INSN
);
5735 inst_base
= &inst
.base
;
5736 inst_base
->opcode
= opcode
;
5738 /* Truly conditionally executed instructions, e.g. b.cond. */
5739 if (opcode
->flags
& F_COND
)
5741 gas_assert (inst
.cond
!= COND_ALWAYS
);
5742 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5743 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5745 else if (inst
.cond
!= COND_ALWAYS
)
5747 /* It shouldn't arrive here, where the assembly looks like a
5748 conditional instruction but the found opcode is unconditional. */
5753 if (parse_operands (p
, opcode
)
5754 && programmer_friendly_fixup (&inst
)
5755 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5757 /* Check that this instruction is supported for this CPU. */
5758 if (!opcode
->avariant
5759 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5761 as_bad (_("selected processor does not support `%s'"), str
);
5765 warn_unpredictable_ldst (&inst
, str
);
5767 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5768 || !inst
.reloc
.need_libopcodes_p
)
5772 /* If there is relocation generated for the instruction,
5773 store the instruction information for the future fix-up. */
5774 struct aarch64_inst
*copy
;
5775 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5776 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5778 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5784 template = template->next
;
5785 if (template != NULL
)
5787 reset_aarch64_instruction (&inst
);
5788 inst
.cond
= saved_cond
;
5791 while (template != NULL
);
5793 /* Issue the error messages if any. */
5794 output_operand_error_report (str
);
5797 /* Various frobbings of labels and their addresses. */
5800 aarch64_start_line_hook (void)
5802 last_label_seen
= NULL
;
5806 aarch64_frob_label (symbolS
* sym
)
5808 last_label_seen
= sym
;
5810 dwarf2_emit_label (sym
);
5814 aarch64_data_in_code (void)
5816 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5818 *input_line_pointer
= '/';
5819 input_line_pointer
+= 5;
5820 *input_line_pointer
= 0;
5828 aarch64_canonicalize_symbol_name (char *name
)
5832 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
5833 *(name
+ len
- 5) = 0;
5838 /* Table of all register names defined by default. The user can
5839 define additional names with .req. Note that all register names
5840 should appear in both upper and lowercase variants. Some registers
5841 also have mixed-case names. */
5843 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5844 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5845 #define REGSET31(p,t) \
5846 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5847 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5848 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5849 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5850 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5851 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5852 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5853 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5854 #define REGSET(p,t) \
5855 REGSET31(p,t), REGNUM(p,31,t)
5857 /* These go into aarch64_reg_hsh hash-table. */
5858 static const reg_entry reg_names
[] = {
5859 /* Integer registers. */
5860 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
5861 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
5863 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
5864 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
5866 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
5867 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
5869 /* Coprocessor register numbers. */
5870 REGSET (c
, CN
), REGSET (C
, CN
),
5872 /* Floating-point single precision registers. */
5873 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
5875 /* Floating-point double precision registers. */
5876 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
5878 /* Floating-point half precision registers. */
5879 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
5881 /* Floating-point byte precision registers. */
5882 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
5884 /* Floating-point quad precision registers. */
5885 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
5887 /* FP/SIMD registers. */
5888 REGSET (v
, VN
), REGSET (V
, VN
),
5903 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5904 static const asm_nzcv nzcv_names
[] = {
5905 {"nzcv", B (n
, z
, c
, v
)},
5906 {"nzcV", B (n
, z
, c
, V
)},
5907 {"nzCv", B (n
, z
, C
, v
)},
5908 {"nzCV", B (n
, z
, C
, V
)},
5909 {"nZcv", B (n
, Z
, c
, v
)},
5910 {"nZcV", B (n
, Z
, c
, V
)},
5911 {"nZCv", B (n
, Z
, C
, v
)},
5912 {"nZCV", B (n
, Z
, C
, V
)},
5913 {"Nzcv", B (N
, z
, c
, v
)},
5914 {"NzcV", B (N
, z
, c
, V
)},
5915 {"NzCv", B (N
, z
, C
, v
)},
5916 {"NzCV", B (N
, z
, C
, V
)},
5917 {"NZcv", B (N
, Z
, c
, v
)},
5918 {"NZcV", B (N
, Z
, c
, V
)},
5919 {"NZCv", B (N
, Z
, C
, v
)},
5920 {"NZCV", B (N
, Z
, C
, V
)}
5933 /* MD interface: bits in the object file. */
5935 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5936 for use in the a.out file, and stores them in the array pointed to by buf.
5937 This knows about the endian-ness of the target machine and does
5938 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5939 2 (short) and 4 (long) Floating numbers are put out as a series of
5940 LITTLENUMS (shorts, here at least). */
5943 md_number_to_chars (char *buf
, valueT val
, int n
)
5945 if (target_big_endian
)
5946 number_to_chars_bigendian (buf
, val
, n
);
5948 number_to_chars_littleendian (buf
, val
, n
);
5951 /* MD interface: Sections. */
5953 /* Estimate the size of a frag before relaxing. Assume everything fits in
5957 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
5963 /* Round up a section size to the appropriate boundary. */
5966 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5971 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5972 of an rs_align_code fragment.
5974 Here we fill the frag with the appropriate info for padding the
5975 output stream. The resulting frag will consist of a fixed (fr_fix)
5976 and of a repeating (fr_var) part.
5978 The fixed content is always emitted before the repeating content and
5979 these two parts are used as follows in constructing the output:
5980 - the fixed part will be used to align to a valid instruction word
5981 boundary, in case that we start at a misaligned address; as no
5982 executable instruction can live at the misaligned location, we
5983 simply fill with zeros;
5984 - the variable part will be used to cover the remaining padding and
5985 we fill using the AArch64 NOP instruction.
5987 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
5988 enough storage space for up to 3 bytes for padding the back to a valid
5989 instruction alignment and exactly 4 bytes to store the NOP pattern. */
5992 aarch64_handle_align (fragS
* fragP
)
5994 /* NOP = d503201f */
5995 /* AArch64 instructions are always little-endian. */
5996 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5998 int bytes
, fix
, noop_size
;
6001 if (fragP
->fr_type
!= rs_align_code
)
6004 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6005 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6008 gas_assert (fragP
->tc_frag_data
.recorded
);
6011 noop_size
= sizeof (aarch64_noop
);
6013 fix
= bytes
& (noop_size
- 1);
6017 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6021 fragP
->fr_fix
+= fix
;
6025 memcpy (p
, aarch64_noop
, noop_size
);
6026 fragP
->fr_var
= noop_size
;
6029 /* Perform target specific initialisation of a frag.
6030 Note - despite the name this initialisation is not done when the frag
6031 is created, but only when its type is assigned. A frag can be created
6032 and used a long time before its type is set, so beware of assuming that
6033 this initialisationis performed first. */
6037 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6038 int max_chars ATTRIBUTE_UNUSED
)
6042 #else /* OBJ_ELF is defined. */
6044 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6046 /* Record a mapping symbol for alignment frags. We will delete this
6047 later if the alignment ends up empty. */
6048 if (!fragP
->tc_frag_data
.recorded
)
6049 fragP
->tc_frag_data
.recorded
= 1;
6051 switch (fragP
->fr_type
)
6056 mapping_state_2 (MAP_DATA
, max_chars
);
6059 mapping_state_2 (MAP_INSN
, max_chars
);
6066 /* Initialize the DWARF-2 unwind information for this procedure. */
6069 tc_aarch64_frame_initial_instructions (void)
6071 cfi_add_CFA_def_cfa (REG_SP
, 0);
6073 #endif /* OBJ_ELF */
6075 /* Convert REGNAME to a DWARF-2 register number. */
6078 tc_aarch64_regname_to_dw2regnum (char *regname
)
6080 const reg_entry
*reg
= parse_reg (®name
);
6086 case REG_TYPE_SP_32
:
6087 case REG_TYPE_SP_64
:
6097 return reg
->number
+ 64;
6105 /* Implement DWARF2_ADDR_SIZE. */
6108 aarch64_dwarf2_addr_size (void)
6110 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6114 return bfd_arch_bits_per_address (stdoutput
) / 8;
6117 /* MD interface: Symbol and relocation handling. */
6119 /* Return the address within the segment that a PC-relative fixup is
6120 relative to. For AArch64 PC-relative fixups applied to instructions
6121 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6124 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6126 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6128 /* If this is pc-relative and we are going to emit a relocation
6129 then we just want to put out any pipeline compensation that the linker
6130 will need. Otherwise we want to use the calculated base. */
6132 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6133 || aarch64_force_relocation (fixP
)))
6136 /* AArch64 should be consistent for all pc-relative relocations. */
6137 return base
+ AARCH64_PCREL_OFFSET
;
6140 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6141 Otherwise we have no need to default values of symbols. */
6144 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6147 if (name
[0] == '_' && name
[1] == 'G'
6148 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6152 if (symbol_find (name
))
6153 as_bad (_("GOT already in the symbol table"));
6155 GOT_symbol
= symbol_new (name
, undefined_section
,
6156 (valueT
) 0, &zero_address_frag
);
6166 /* Return non-zero if the indicated VALUE has overflowed the maximum
6167 range expressible by a unsigned number with the indicated number of
6171 unsigned_overflow (valueT value
, unsigned bits
)
6174 if (bits
>= sizeof (valueT
) * 8)
6176 lim
= (valueT
) 1 << bits
;
6177 return (value
>= lim
);
6181 /* Return non-zero if the indicated VALUE has overflowed the maximum
6182 range expressible by an signed number with the indicated number of
6186 signed_overflow (offsetT value
, unsigned bits
)
6189 if (bits
>= sizeof (offsetT
) * 8)
6191 lim
= (offsetT
) 1 << (bits
- 1);
6192 return (value
< -lim
|| value
>= lim
);
6195 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6196 unsigned immediate offset load/store instruction, try to encode it as
6197 an unscaled, 9-bit, signed immediate offset load/store instruction.
6198 Return TRUE if it is successful; otherwise return FALSE.
6200 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6201 in response to the standard LDR/STR mnemonics when the immediate offset is
6202 unambiguous, i.e. when it is negative or unaligned. */
6205 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6208 enum aarch64_op new_op
;
6209 const aarch64_opcode
*new_opcode
;
6211 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6213 switch (instr
->opcode
->op
)
6215 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6216 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6217 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6218 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6219 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6220 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6221 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6222 case OP_STR_POS
: new_op
= OP_STUR
; break;
6223 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6224 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6225 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6226 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6227 default: new_op
= OP_NIL
; break;
6230 if (new_op
== OP_NIL
)
6233 new_opcode
= aarch64_get_opcode (new_op
);
6234 gas_assert (new_opcode
!= NULL
);
6236 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6237 instr
->opcode
->op
, new_opcode
->op
);
6239 aarch64_replace_opcode (instr
, new_opcode
);
6241 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6242 qualifier matching may fail because the out-of-date qualifier will
6243 prevent the operand being updated with a new and correct qualifier. */
6244 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6245 AARCH64_OPND_ADDR_SIMM9
);
6246 gas_assert (idx
== 1);
6247 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6249 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6251 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6257 /* Called by fix_insn to fix a MOV immediate alias instruction.
6259 Operand for a generic move immediate instruction, which is an alias
6260 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6261 a 32-bit/64-bit immediate value into general register. An assembler error
6262 shall result if the immediate cannot be created by a single one of these
6263 instructions. If there is a choice, then to ensure reversability an
6264 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6267 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6269 const aarch64_opcode
*opcode
;
6271 /* Need to check if the destination is SP/ZR. The check has to be done
6272 before any aarch64_replace_opcode. */
6273 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6274 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6276 instr
->operands
[1].imm
.value
= value
;
6277 instr
->operands
[1].skip
= 0;
6281 /* Try the MOVZ alias. */
6282 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6283 aarch64_replace_opcode (instr
, opcode
);
6284 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6285 &instr
->value
, NULL
, NULL
))
6287 put_aarch64_insn (buf
, instr
->value
);
6290 /* Try the MOVK alias. */
6291 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6292 aarch64_replace_opcode (instr
, opcode
);
6293 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6294 &instr
->value
, NULL
, NULL
))
6296 put_aarch64_insn (buf
, instr
->value
);
6301 if (try_mov_bitmask_p
)
6303 /* Try the ORR alias. */
6304 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6305 aarch64_replace_opcode (instr
, opcode
);
6306 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6307 &instr
->value
, NULL
, NULL
))
6309 put_aarch64_insn (buf
, instr
->value
);
6314 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6315 _("immediate cannot be moved by a single instruction"));
6318 /* An instruction operand which is immediate related may have symbol used
6319 in the assembly, e.g.
6322 .set u32, 0x00ffff00
6324 At the time when the assembly instruction is parsed, a referenced symbol,
6325 like 'u32' in the above example may not have been seen; a fixS is created
6326 in such a case and is handled here after symbols have been resolved.
6327 Instruction is fixed up with VALUE using the information in *FIXP plus
6328 extra information in FLAGS.
6330 This function is called by md_apply_fix to fix up instructions that need
6331 a fix-up described above but does not involve any linker-time relocation. */
6334 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6338 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6339 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6340 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6344 /* Now the instruction is about to be fixed-up, so the operand that
6345 was previously marked as 'ignored' needs to be unmarked in order
6346 to get the encoding done properly. */
6347 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6348 new_inst
->operands
[idx
].skip
= 0;
6351 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6355 case AARCH64_OPND_EXCEPTION
:
6356 if (unsigned_overflow (value
, 16))
6357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6358 _("immediate out of range"));
6359 insn
= get_aarch64_insn (buf
);
6360 insn
|= encode_svc_imm (value
);
6361 put_aarch64_insn (buf
, insn
);
6364 case AARCH64_OPND_AIMM
:
6365 /* ADD or SUB with immediate.
6366 NOTE this assumes we come here with a add/sub shifted reg encoding
6367 3 322|2222|2 2 2 21111 111111
6368 1 098|7654|3 2 1 09876 543210 98765 43210
6369 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6370 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6371 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6372 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6374 3 322|2222|2 2 221111111111
6375 1 098|7654|3 2 109876543210 98765 43210
6376 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6377 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6378 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6379 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6380 Fields sf Rn Rd are already set. */
6381 insn
= get_aarch64_insn (buf
);
6385 insn
= reencode_addsub_switch_add_sub (insn
);
6389 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6390 && unsigned_overflow (value
, 12))
6392 /* Try to shift the value by 12 to make it fit. */
6393 if (((value
>> 12) << 12) == value
6394 && ! unsigned_overflow (value
, 12 + 12))
6397 insn
|= encode_addsub_imm_shift_amount (1);
6401 if (unsigned_overflow (value
, 12))
6402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6403 _("immediate out of range"));
6405 insn
|= encode_addsub_imm (value
);
6407 put_aarch64_insn (buf
, insn
);
6410 case AARCH64_OPND_SIMD_IMM
:
6411 case AARCH64_OPND_SIMD_IMM_SFT
:
6412 case AARCH64_OPND_LIMM
:
6413 /* Bit mask immediate. */
6414 gas_assert (new_inst
!= NULL
);
6415 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6416 new_inst
->operands
[idx
].imm
.value
= value
;
6417 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6418 &new_inst
->value
, NULL
, NULL
))
6419 put_aarch64_insn (buf
, new_inst
->value
);
6421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6422 _("invalid immediate"));
6425 case AARCH64_OPND_HALF
:
6426 /* 16-bit unsigned immediate. */
6427 if (unsigned_overflow (value
, 16))
6428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6429 _("immediate out of range"));
6430 insn
= get_aarch64_insn (buf
);
6431 insn
|= encode_movw_imm (value
& 0xffff);
6432 put_aarch64_insn (buf
, insn
);
6435 case AARCH64_OPND_IMM_MOV
:
6436 /* Operand for a generic move immediate instruction, which is
6437 an alias instruction that generates a single MOVZ, MOVN or ORR
6438 instruction to loads a 32-bit/64-bit immediate value into general
6439 register. An assembler error shall result if the immediate cannot be
6440 created by a single one of these instructions. If there is a choice,
6441 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6442 and MOVZ or MOVN to ORR. */
6443 gas_assert (new_inst
!= NULL
);
6444 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6447 case AARCH64_OPND_ADDR_SIMM7
:
6448 case AARCH64_OPND_ADDR_SIMM9
:
6449 case AARCH64_OPND_ADDR_SIMM9_2
:
6450 case AARCH64_OPND_ADDR_UIMM12
:
6451 /* Immediate offset in an address. */
6452 insn
= get_aarch64_insn (buf
);
6454 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6455 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6456 || new_inst
->opcode
->operands
[2] == opnd
);
6458 /* Get the index of the address operand. */
6459 if (new_inst
->opcode
->operands
[1] == opnd
)
6460 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6463 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6466 /* Update the resolved offset value. */
6467 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6469 /* Encode/fix-up. */
6470 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6471 &new_inst
->value
, NULL
, NULL
))
6473 put_aarch64_insn (buf
, new_inst
->value
);
6476 else if (new_inst
->opcode
->iclass
== ldst_pos
6477 && try_to_encode_as_unscaled_ldst (new_inst
))
6479 put_aarch64_insn (buf
, new_inst
->value
);
6483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6484 _("immediate offset out of range"));
6489 as_fatal (_("unhandled operand code %d"), opnd
);
6493 /* Apply a fixup (fixP) to segment data, once it has been determined
6494 by our caller that we have all the info we need to fix it up.
6496 Parameter valP is the pointer to the value of the bits. */
6499 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6501 offsetT value
= *valP
;
6503 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6505 unsigned flags
= fixP
->fx_addnumber
;
6507 DEBUG_TRACE ("\n\n");
6508 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6509 DEBUG_TRACE ("Enter md_apply_fix");
6511 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6513 /* Note whether this will delete the relocation. */
6515 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6518 /* Process the relocations. */
6519 switch (fixP
->fx_r_type
)
6521 case BFD_RELOC_NONE
:
6522 /* This will need to go in the object file. */
6527 case BFD_RELOC_8_PCREL
:
6528 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6529 md_number_to_chars (buf
, value
, 1);
6533 case BFD_RELOC_16_PCREL
:
6534 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6535 md_number_to_chars (buf
, value
, 2);
6539 case BFD_RELOC_32_PCREL
:
6540 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6541 md_number_to_chars (buf
, value
, 4);
6545 case BFD_RELOC_64_PCREL
:
6546 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6547 md_number_to_chars (buf
, value
, 8);
6550 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6551 /* We claim that these fixups have been processed here, even if
6552 in fact we generate an error because we do not have a reloc
6553 for them, so tc_gen_reloc() will reject them. */
6555 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6558 _("undefined symbol %s used as an immediate value"),
6559 S_GET_NAME (fixP
->fx_addsy
));
6560 goto apply_fix_return
;
6562 fix_insn (fixP
, flags
, value
);
6565 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6566 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6570 _("pc-relative load offset not word aligned"));
6571 if (signed_overflow (value
, 21))
6572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6573 _("pc-relative load offset out of range"));
6574 insn
= get_aarch64_insn (buf
);
6575 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6576 put_aarch64_insn (buf
, insn
);
6580 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6581 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6583 if (signed_overflow (value
, 21))
6584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6585 _("pc-relative address offset out of range"));
6586 insn
= get_aarch64_insn (buf
);
6587 insn
|= encode_adr_imm (value
);
6588 put_aarch64_insn (buf
, insn
);
6592 case BFD_RELOC_AARCH64_BRANCH19
:
6593 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6597 _("conditional branch target not word aligned"));
6598 if (signed_overflow (value
, 21))
6599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6600 _("conditional branch out of range"));
6601 insn
= get_aarch64_insn (buf
);
6602 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6603 put_aarch64_insn (buf
, insn
);
6607 case BFD_RELOC_AARCH64_TSTBR14
:
6608 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6612 _("conditional branch target not word aligned"));
6613 if (signed_overflow (value
, 16))
6614 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6615 _("conditional branch out of range"));
6616 insn
= get_aarch64_insn (buf
);
6617 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6618 put_aarch64_insn (buf
, insn
);
6622 case BFD_RELOC_AARCH64_CALL26
:
6623 case BFD_RELOC_AARCH64_JUMP26
:
6624 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6628 _("branch target not word aligned"));
6629 if (signed_overflow (value
, 28))
6630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6631 _("branch out of range"));
6632 insn
= get_aarch64_insn (buf
);
6633 insn
|= encode_branch_ofs_26 (value
>> 2);
6634 put_aarch64_insn (buf
, insn
);
6638 case BFD_RELOC_AARCH64_MOVW_G0
:
6639 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6640 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6643 case BFD_RELOC_AARCH64_MOVW_G1
:
6644 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6645 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6648 case BFD_RELOC_AARCH64_MOVW_G2
:
6649 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6650 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6653 case BFD_RELOC_AARCH64_MOVW_G3
:
6656 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6658 insn
= get_aarch64_insn (buf
);
6662 /* REL signed addend must fit in 16 bits */
6663 if (signed_overflow (value
, 16))
6664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6665 _("offset out of range"));
6669 /* Check for overflow and scale. */
6670 switch (fixP
->fx_r_type
)
6672 case BFD_RELOC_AARCH64_MOVW_G0
:
6673 case BFD_RELOC_AARCH64_MOVW_G1
:
6674 case BFD_RELOC_AARCH64_MOVW_G2
:
6675 case BFD_RELOC_AARCH64_MOVW_G3
:
6676 if (unsigned_overflow (value
, scale
+ 16))
6677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6678 _("unsigned value out of range"));
6680 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6681 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6682 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6683 /* NOTE: We can only come here with movz or movn. */
6684 if (signed_overflow (value
, scale
+ 16))
6685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6686 _("signed value out of range"));
6689 /* Force use of MOVN. */
6691 insn
= reencode_movzn_to_movn (insn
);
6695 /* Force use of MOVZ. */
6696 insn
= reencode_movzn_to_movz (insn
);
6700 /* Unchecked relocations. */
6706 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6707 insn
|= encode_movw_imm (value
& 0xffff);
6709 put_aarch64_insn (buf
, insn
);
6713 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6714 fixP
->fx_r_type
= (ilp32_p
6715 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6716 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
6717 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6718 /* Should always be exported to object file, see
6719 aarch64_force_relocation(). */
6720 gas_assert (!fixP
->fx_done
);
6721 gas_assert (seg
->use_rela_p
);
6724 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6725 fixP
->fx_r_type
= (ilp32_p
6726 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6727 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
6728 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6729 /* Should always be exported to object file, see
6730 aarch64_force_relocation(). */
6731 gas_assert (!fixP
->fx_done
);
6732 gas_assert (seg
->use_rela_p
);
6735 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6736 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6737 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6738 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6739 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6740 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6741 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6742 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6743 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6744 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6745 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6746 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6747 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6748 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6749 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6750 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6751 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6752 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6753 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6754 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6755 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6756 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6757 /* Should always be exported to object file, see
6758 aarch64_force_relocation(). */
6759 gas_assert (!fixP
->fx_done
);
6760 gas_assert (seg
->use_rela_p
);
6763 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6764 /* Should always be exported to object file, see
6765 aarch64_force_relocation(). */
6766 fixP
->fx_r_type
= (ilp32_p
6767 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6768 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
6769 gas_assert (!fixP
->fx_done
);
6770 gas_assert (seg
->use_rela_p
);
6773 case BFD_RELOC_AARCH64_ADD_LO12
:
6774 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6775 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6776 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6777 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6778 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6779 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
6780 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
6781 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6782 case BFD_RELOC_AARCH64_LDST128_LO12
:
6783 case BFD_RELOC_AARCH64_LDST16_LO12
:
6784 case BFD_RELOC_AARCH64_LDST32_LO12
:
6785 case BFD_RELOC_AARCH64_LDST64_LO12
:
6786 case BFD_RELOC_AARCH64_LDST8_LO12
:
6787 /* Should always be exported to object file, see
6788 aarch64_force_relocation(). */
6789 gas_assert (!fixP
->fx_done
);
6790 gas_assert (seg
->use_rela_p
);
6793 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6794 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6795 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6798 case BFD_RELOC_UNUSED
:
6799 /* An error will already have been reported. */
6803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6804 _("unexpected %s fixup"),
6805 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6810 /* Free the allocated the struct aarch64_inst.
6811 N.B. currently there are very limited number of fix-up types actually use
6812 this field, so the impact on the performance should be minimal . */
6813 if (fixP
->tc_fix_data
.inst
!= NULL
)
6814 free (fixP
->tc_fix_data
.inst
);
6819 /* Translate internal representation of relocation info to BFD target
6823 tc_gen_reloc (asection
* section
, fixS
* fixp
)
6826 bfd_reloc_code_real_type code
;
6828 reloc
= xmalloc (sizeof (arelent
));
6830 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
6831 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6832 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6836 if (section
->use_rela_p
)
6837 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
6839 fixp
->fx_offset
= reloc
->address
;
6841 reloc
->addend
= fixp
->fx_offset
;
6843 code
= fixp
->fx_r_type
;
6848 code
= BFD_RELOC_16_PCREL
;
6853 code
= BFD_RELOC_32_PCREL
;
6858 code
= BFD_RELOC_64_PCREL
;
6865 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6866 if (reloc
->howto
== NULL
)
6868 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6870 ("cannot represent %s relocation in this object file format"),
6871 bfd_get_reloc_code_name (code
));
6878 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6881 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
6883 bfd_reloc_code_real_type type
;
6887 FIXME: @@ Should look at CPU word size. */
6894 type
= BFD_RELOC_16
;
6897 type
= BFD_RELOC_32
;
6900 type
= BFD_RELOC_64
;
6903 as_bad (_("cannot do %u-byte relocation"), size
);
6904 type
= BFD_RELOC_UNUSED
;
6908 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6912 aarch64_force_relocation (struct fix
*fixp
)
6914 switch (fixp
->fx_r_type
)
6916 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6917 /* Perform these "immediate" internal relocations
6918 even if the symbol is extern or weak. */
6921 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6922 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6923 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6924 /* Pseudo relocs that need to be fixed up according to
6928 case BFD_RELOC_AARCH64_ADD_LO12
:
6929 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6930 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6931 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6932 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6933 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6934 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
6935 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
6936 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6937 case BFD_RELOC_AARCH64_LDST128_LO12
:
6938 case BFD_RELOC_AARCH64_LDST16_LO12
:
6939 case BFD_RELOC_AARCH64_LDST32_LO12
:
6940 case BFD_RELOC_AARCH64_LDST64_LO12
:
6941 case BFD_RELOC_AARCH64_LDST8_LO12
:
6942 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6943 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6944 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6945 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6946 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6947 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6948 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6949 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6950 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6951 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6952 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6953 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6954 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6955 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6956 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6957 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6958 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6959 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6960 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6961 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6962 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6963 /* Always leave these relocations for the linker. */
6970 return generic_force_reloc (fixp
);
6976 elf64_aarch64_target_format (void)
6978 if (target_big_endian
)
6979 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
6981 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
6985 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
6987 elf_frob_symbol (symp
, puntp
);
6991 /* MD interface: Finalization. */
6993 /* A good place to do this, although this was probably not intended
6994 for this kind of use. We need to dump the literal pool before
6995 references are made to a null symbol pointer. */
6998 aarch64_cleanup (void)
7002 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7004 /* Put it at the end of the relevant section. */
7005 subseg_set (pool
->section
, pool
->sub_section
);
7011 /* Remove any excess mapping symbols generated for alignment frags in
7012 SEC. We may have created a mapping symbol before a zero byte
7013 alignment; remove it if there's a mapping symbol after the
7016 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7017 void *dummy ATTRIBUTE_UNUSED
)
7019 segment_info_type
*seginfo
= seg_info (sec
);
7022 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7025 for (fragp
= seginfo
->frchainP
->frch_root
;
7026 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7028 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7029 fragS
*next
= fragp
->fr_next
;
7031 /* Variable-sized frags have been converted to fixed size by
7032 this point. But if this was variable-sized to start with,
7033 there will be a fixed-size frag after it. So don't handle
7035 if (sym
== NULL
|| next
== NULL
)
7038 if (S_GET_VALUE (sym
) < next
->fr_address
)
7039 /* Not at the end of this frag. */
7041 know (S_GET_VALUE (sym
) == next
->fr_address
);
7045 if (next
->tc_frag_data
.first_map
!= NULL
)
7047 /* Next frag starts with a mapping symbol. Discard this
7049 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7053 if (next
->fr_next
== NULL
)
7055 /* This mapping symbol is at the end of the section. Discard
7057 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7058 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7062 /* As long as we have empty frags without any mapping symbols,
7064 /* If the next frag is non-empty and does not start with a
7065 mapping symbol, then this mapping symbol is required. */
7066 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7069 next
= next
->fr_next
;
7071 while (next
!= NULL
);
7076 /* Adjust the symbol table. */
7079 aarch64_adjust_symtab (void)
7082 /* Remove any overlapping mapping symbols generated by alignment frags. */
7083 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7084 /* Now do generic ELF adjustments. */
7085 elf_adjust_symtab ();
7090 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7092 const char *hash_err
;
7094 hash_err
= hash_insert (table
, key
, value
);
7096 printf ("Internal Error: Can't hash %s\n", key
);
7100 fill_instruction_hash_table (void)
7102 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7104 while (opcode
->name
!= NULL
)
7106 templates
*templ
, *new_templ
;
7107 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7109 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7110 new_templ
->opcode
= opcode
;
7111 new_templ
->next
= NULL
;
7114 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7117 new_templ
->next
= templ
->next
;
7118 templ
->next
= new_templ
;
7125 convert_to_upper (char *dst
, const char *src
, size_t num
)
7128 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7129 *dst
= TOUPPER (*src
);
7133 /* Assume STR point to a lower-case string, allocate, convert and return
7134 the corresponding upper-case string. */
7135 static inline const char*
7136 get_upper_str (const char *str
)
7139 size_t len
= strlen (str
);
7140 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7142 convert_to_upper (ret
, str
, len
);
7146 /* MD interface: Initialization. */
7154 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7155 || (aarch64_cond_hsh
= hash_new ()) == NULL
7156 || (aarch64_shift_hsh
= hash_new ()) == NULL
7157 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7158 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7159 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7160 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7161 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7162 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7163 || (aarch64_reg_hsh
= hash_new ()) == NULL
7164 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7165 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7166 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
7167 as_fatal (_("virtual memory exhausted"));
7169 fill_instruction_hash_table ();
7171 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7172 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7173 (void *) (aarch64_sys_regs
+ i
));
7175 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7176 checked_hash_insert (aarch64_pstatefield_hsh
,
7177 aarch64_pstatefields
[i
].name
,
7178 (void *) (aarch64_pstatefields
+ i
));
7180 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
7181 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7182 aarch64_sys_regs_ic
[i
].template,
7183 (void *) (aarch64_sys_regs_ic
+ i
));
7185 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
7186 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7187 aarch64_sys_regs_dc
[i
].template,
7188 (void *) (aarch64_sys_regs_dc
+ i
));
7190 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
7191 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7192 aarch64_sys_regs_at
[i
].template,
7193 (void *) (aarch64_sys_regs_at
+ i
));
7195 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
7196 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7197 aarch64_sys_regs_tlbi
[i
].template,
7198 (void *) (aarch64_sys_regs_tlbi
+ i
));
7200 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7201 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7202 (void *) (reg_names
+ i
));
7204 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7205 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7206 (void *) (nzcv_names
+ i
));
7208 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7210 const char *name
= aarch64_operand_modifiers
[i
].name
;
7211 checked_hash_insert (aarch64_shift_hsh
, name
,
7212 (void *) (aarch64_operand_modifiers
+ i
));
7213 /* Also hash the name in the upper case. */
7214 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7215 (void *) (aarch64_operand_modifiers
+ i
));
7218 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7221 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7222 the same condition code. */
7223 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7225 const char *name
= aarch64_conds
[i
].names
[j
];
7228 checked_hash_insert (aarch64_cond_hsh
, name
,
7229 (void *) (aarch64_conds
+ i
));
7230 /* Also hash the name in the upper case. */
7231 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7232 (void *) (aarch64_conds
+ i
));
7236 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7238 const char *name
= aarch64_barrier_options
[i
].name
;
7239 /* Skip xx00 - the unallocated values of option. */
7242 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7243 (void *) (aarch64_barrier_options
+ i
));
7244 /* Also hash the name in the upper case. */
7245 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7246 (void *) (aarch64_barrier_options
+ i
));
7249 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7251 const char* name
= aarch64_prfops
[i
].name
;
7252 /* Skip the unallocated hint encodings. */
7255 checked_hash_insert (aarch64_pldop_hsh
, name
,
7256 (void *) (aarch64_prfops
+ i
));
7257 /* Also hash the name in the upper case. */
7258 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7259 (void *) (aarch64_prfops
+ i
));
7262 /* Set the cpu variant based on the command-line options. */
7264 mcpu_cpu_opt
= march_cpu_opt
;
7267 mcpu_cpu_opt
= &cpu_default
;
7269 cpu_variant
= *mcpu_cpu_opt
;
7271 /* Record the CPU type. */
7272 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7274 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7277 /* Command line processing. */
7279 const char *md_shortopts
= "m:";
7281 #ifdef AARCH64_BI_ENDIAN
7282 #define OPTION_EB (OPTION_MD_BASE + 0)
7283 #define OPTION_EL (OPTION_MD_BASE + 1)
7285 #if TARGET_BYTES_BIG_ENDIAN
7286 #define OPTION_EB (OPTION_MD_BASE + 0)
7288 #define OPTION_EL (OPTION_MD_BASE + 1)
7292 struct option md_longopts
[] = {
7294 {"EB", no_argument
, NULL
, OPTION_EB
},
7297 {"EL", no_argument
, NULL
, OPTION_EL
},
7299 {NULL
, no_argument
, NULL
, 0}
7302 size_t md_longopts_size
= sizeof (md_longopts
);
7304 struct aarch64_option_table
7306 char *option
; /* Option name to match. */
7307 char *help
; /* Help information. */
7308 int *var
; /* Variable to change. */
7309 int value
; /* What to change it to. */
7310 char *deprecated
; /* If non-null, print this message. */
7313 static struct aarch64_option_table aarch64_opts
[] = {
7314 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7315 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7317 #ifdef DEBUG_AARCH64
7318 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7319 #endif /* DEBUG_AARCH64 */
7320 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7322 {"mno-verbose-error", N_("do not output verbose error messages"),
7323 &verbose_error_p
, 0, NULL
},
7324 {NULL
, NULL
, NULL
, 0, NULL
}
7327 struct aarch64_cpu_option_table
7330 const aarch64_feature_set value
;
7331 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7333 const char *canonical_name
;
7336 /* This list should, at a minimum, contain all the cpu names
7337 recognized by GCC. */
7338 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7339 {"all", AARCH64_ANY
, NULL
},
7340 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7341 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7342 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7343 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7344 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7345 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7346 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7347 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7348 "Samsung Exynos M1"},
7349 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7350 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7352 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7353 in earlier releases and is superseded by 'xgene1' in all
7355 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7356 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7357 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7358 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7359 {"generic", AARCH64_ARCH_V8
, NULL
},
7361 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7364 struct aarch64_arch_option_table
7367 const aarch64_feature_set value
;
7370 /* This list should, at a minimum, contain all the architecture names
7371 recognized by GCC. */
7372 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7373 {"all", AARCH64_ANY
},
7374 {"armv8-a", AARCH64_ARCH_V8
},
7375 {NULL
, AARCH64_ARCH_NONE
}
7378 /* ISA extensions. */
7379 struct aarch64_option_cpu_value_table
7382 const aarch64_feature_set value
;
7385 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7386 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7387 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7388 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7389 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7390 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7391 {NULL
, AARCH64_ARCH_NONE
}
7394 struct aarch64_long_option_table
7396 char *option
; /* Substring to match. */
7397 char *help
; /* Help information. */
7398 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7399 char *deprecated
; /* If non-null, print this message. */
7403 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7404 bfd_boolean ext_only
)
7406 /* We insist on extensions being added before being removed. We achieve
7407 this by using the ADDING_VALUE variable to indicate whether we are
7408 adding an extension (1) or removing it (0) and only allowing it to
7409 change in the order -1 -> 1 -> 0. */
7410 int adding_value
= -1;
7411 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7413 /* Copy the feature set, so that we can modify it. */
7417 while (str
!= NULL
&& *str
!= 0)
7419 const struct aarch64_option_cpu_value_table
*opt
;
7427 as_bad (_("invalid architectural extension"));
7431 ext
= strchr (++str
, '+');
7437 optlen
= strlen (str
);
7439 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7441 if (adding_value
!= 0)
7446 else if (optlen
> 0)
7448 if (adding_value
== -1)
7450 else if (adding_value
!= 1)
7452 as_bad (_("must specify extensions to add before specifying "
7453 "those to remove"));
7460 as_bad (_("missing architectural extension"));
7464 gas_assert (adding_value
!= -1);
7466 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7467 if (strncmp (opt
->name
, str
, optlen
) == 0)
7469 /* Add or remove the extension. */
7471 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7473 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7477 if (opt
->name
== NULL
)
7479 as_bad (_("unknown architectural extension `%s'"), str
);
7490 aarch64_parse_cpu (char *str
)
7492 const struct aarch64_cpu_option_table
*opt
;
7493 char *ext
= strchr (str
, '+');
7499 optlen
= strlen (str
);
7503 as_bad (_("missing cpu name `%s'"), str
);
7507 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7508 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7510 mcpu_cpu_opt
= &opt
->value
;
7512 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7517 as_bad (_("unknown cpu `%s'"), str
);
7522 aarch64_parse_arch (char *str
)
7524 const struct aarch64_arch_option_table
*opt
;
7525 char *ext
= strchr (str
, '+');
7531 optlen
= strlen (str
);
7535 as_bad (_("missing architecture name `%s'"), str
);
7539 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7540 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7542 march_cpu_opt
= &opt
->value
;
7544 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7549 as_bad (_("unknown architecture `%s'\n"), str
);
7554 struct aarch64_option_abi_value_table
7557 enum aarch64_abi_type value
;
7560 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7561 {"ilp32", AARCH64_ABI_ILP32
},
7562 {"lp64", AARCH64_ABI_LP64
},
7567 aarch64_parse_abi (char *str
)
7569 const struct aarch64_option_abi_value_table
*opt
;
7570 size_t optlen
= strlen (str
);
7574 as_bad (_("missing abi name `%s'"), str
);
7578 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
7579 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7581 aarch64_abi
= opt
->value
;
7585 as_bad (_("unknown abi `%s'\n"), str
);
7589 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7591 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7592 aarch64_parse_abi
, NULL
},
7593 #endif /* OBJ_ELF */
7594 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7595 aarch64_parse_cpu
, NULL
},
7596 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7597 aarch64_parse_arch
, NULL
},
7598 {NULL
, NULL
, 0, NULL
}
7602 md_parse_option (int c
, char *arg
)
7604 struct aarch64_option_table
*opt
;
7605 struct aarch64_long_option_table
*lopt
;
7611 target_big_endian
= 1;
7617 target_big_endian
= 0;
7622 /* Listing option. Just ignore these, we don't support additional
7627 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7629 if (c
== opt
->option
[0]
7630 && ((arg
== NULL
&& opt
->option
[1] == 0)
7631 || streq (arg
, opt
->option
+ 1)))
7633 /* If the option is deprecated, tell the user. */
7634 if (opt
->deprecated
!= NULL
)
7635 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7636 arg
? arg
: "", _(opt
->deprecated
));
7638 if (opt
->var
!= NULL
)
7639 *opt
->var
= opt
->value
;
7645 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7647 /* These options are expected to have an argument. */
7648 if (c
== lopt
->option
[0]
7650 && strncmp (arg
, lopt
->option
+ 1,
7651 strlen (lopt
->option
+ 1)) == 0)
7653 /* If the option is deprecated, tell the user. */
7654 if (lopt
->deprecated
!= NULL
)
7655 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7656 _(lopt
->deprecated
));
7658 /* Call the sup-option parser. */
7659 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7670 md_show_usage (FILE * fp
)
7672 struct aarch64_option_table
*opt
;
7673 struct aarch64_long_option_table
*lopt
;
7675 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7677 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7678 if (opt
->help
!= NULL
)
7679 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7681 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7682 if (lopt
->help
!= NULL
)
7683 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7687 -EB assemble code for a big-endian cpu\n"));
7692 -EL assemble code for a little-endian cpu\n"));
7696 /* Parse a .cpu directive. */
7699 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7701 const struct aarch64_cpu_option_table
*opt
;
7707 name
= input_line_pointer
;
7708 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7709 input_line_pointer
++;
7710 saved_char
= *input_line_pointer
;
7711 *input_line_pointer
= 0;
7713 ext
= strchr (name
, '+');
7716 optlen
= ext
- name
;
7718 optlen
= strlen (name
);
7720 /* Skip the first "all" entry. */
7721 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7722 if (strlen (opt
->name
) == optlen
7723 && strncmp (name
, opt
->name
, optlen
) == 0)
7725 mcpu_cpu_opt
= &opt
->value
;
7727 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7730 cpu_variant
= *mcpu_cpu_opt
;
7732 *input_line_pointer
= saved_char
;
7733 demand_empty_rest_of_line ();
7736 as_bad (_("unknown cpu `%s'"), name
);
7737 *input_line_pointer
= saved_char
;
7738 ignore_rest_of_line ();
7742 /* Parse a .arch directive. */
7745 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7747 const struct aarch64_arch_option_table
*opt
;
7753 name
= input_line_pointer
;
7754 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7755 input_line_pointer
++;
7756 saved_char
= *input_line_pointer
;
7757 *input_line_pointer
= 0;
7759 ext
= strchr (name
, '+');
7762 optlen
= ext
- name
;
7764 optlen
= strlen (name
);
7766 /* Skip the first "all" entry. */
7767 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7768 if (strlen (opt
->name
) == optlen
7769 && strncmp (name
, opt
->name
, optlen
) == 0)
7771 mcpu_cpu_opt
= &opt
->value
;
7773 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7776 cpu_variant
= *mcpu_cpu_opt
;
7778 *input_line_pointer
= saved_char
;
7779 demand_empty_rest_of_line ();
7783 as_bad (_("unknown architecture `%s'\n"), name
);
7784 *input_line_pointer
= saved_char
;
7785 ignore_rest_of_line ();
7788 /* Parse a .arch_extension directive. */
7791 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
7794 char *ext
= input_line_pointer
;;
7796 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7797 input_line_pointer
++;
7798 saved_char
= *input_line_pointer
;
7799 *input_line_pointer
= 0;
7801 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
7804 cpu_variant
= *mcpu_cpu_opt
;
7806 *input_line_pointer
= saved_char
;
7807 demand_empty_rest_of_line ();
7810 /* Copy symbol information. */
7813 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
7815 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);