1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
410 /* Stuff needed to resolve the label ambiguity
419 static symbolS
*last_label_seen
;
421 /* Literal pool structure. Held on a per-section
422 and per-sub-section basis. */
424 #define MAX_LITERAL_POOL_SIZE 1024
425 typedef struct literal_expression
428 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
429 LITTLENUM_TYPE
* bignum
;
430 } literal_expression
;
432 typedef struct literal_pool
434 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
435 unsigned int next_free_entry
;
441 struct literal_pool
*next
;
444 /* Pointer to a linked list of literal pools. */
445 static literal_pool
*list_of_pools
= NULL
;
449 /* This array holds the chars that always start a comment. If the
450 pre-processor is disabled, these aren't very useful. */
451 const char comment_chars
[] = "";
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output. */
456 /* Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output. */
459 /* Also note that comments like this one will always work. */
460 const char line_comment_chars
[] = "#";
462 const char line_separator_chars
[] = ";";
464 /* Chars that can be used to separate mant
465 from exp in floating point numbers. */
466 const char EXP_CHARS
[] = "eE";
468 /* Chars that mean this number is a floating point constant. */
472 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
474 /* Prefix character that indicates the start of an immediate value. */
475 #define is_immediate_prefix(C) ((C) == '#')
477 /* Separator character handling. */
479 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
481 static inline bfd_boolean
482 skip_past_char (char **str
, char c
)
493 #define skip_past_comma(str) skip_past_char (str, ',')
495 /* Arithmetic expressions (possibly involving symbols). */
497 static bfd_boolean in_my_get_expression_p
= FALSE
;
499 /* Third argument to my_get_expression. */
500 #define GE_NO_PREFIX 0
501 #define GE_OPT_PREFIX 1
503 /* Return TRUE if the string pointed by *STR is successfully parsed
504 as an valid expression; *EP will be filled with the information of
505 such an expression. Otherwise return FALSE. */
508 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
513 int prefix_present_p
= 0;
520 if (is_immediate_prefix (**str
))
523 prefix_present_p
= 1;
530 memset (ep
, 0, sizeof (expressionS
));
532 save_in
= input_line_pointer
;
533 input_line_pointer
= *str
;
534 in_my_get_expression_p
= TRUE
;
535 seg
= expression (ep
);
536 in_my_get_expression_p
= FALSE
;
538 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
540 /* We found a bad expression in md_operand(). */
541 *str
= input_line_pointer
;
542 input_line_pointer
= save_in
;
543 if (prefix_present_p
&& ! error_p ())
544 set_fatal_syntax_error (_("bad expression"));
546 set_first_syntax_error (_("bad expression"));
551 if (seg
!= absolute_section
552 && seg
!= text_section
553 && seg
!= data_section
554 && seg
!= bss_section
&& seg
!= undefined_section
)
556 set_syntax_error (_("bad segment"));
557 *str
= input_line_pointer
;
558 input_line_pointer
= save_in
;
565 *str
= input_line_pointer
;
566 input_line_pointer
= save_in
;
570 /* Turn a string in input_line_pointer into a floating point constant
571 of type TYPE, and store the appropriate bytes in *LITP. The number
572 of LITTLENUMS emitted is stored in *SIZEP. An error message is
573 returned, or NULL on OK. */
576 md_atof (int type
, char *litP
, int *sizeP
)
578 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
581 /* We handle all bad expressions here, so that we can report the faulty
582 instruction in the error message. */
584 md_operand (expressionS
* exp
)
586 if (in_my_get_expression_p
)
587 exp
->X_op
= O_illegal
;
590 /* Immediate values. */
592 /* Errors may be set multiple times during parsing or bit encoding
593 (particularly in the Neon bits), but usually the earliest error which is set
594 will be the most meaningful. Avoid overwriting it with later (cascading)
595 errors by calling this function. */
598 first_error (const char *error
)
601 set_syntax_error (error
);
604 /* Similiar to first_error, but this function accepts formatted error
607 first_error_fmt (const char *format
, ...)
612 /* N.B. this single buffer will not cause error messages for different
613 instructions to pollute each other; this is because at the end of
614 processing of each assembly line, error message if any will be
615 collected by as_bad. */
616 static char buffer
[size
];
620 int ret ATTRIBUTE_UNUSED
;
621 va_start (args
, format
);
622 ret
= vsnprintf (buffer
, size
, format
, args
);
623 know (ret
<= size
- 1 && ret
>= 0);
625 set_syntax_error (buffer
);
629 /* Register parsing. */
631 /* Generic register parser which is called by other specialized
633 CCP points to what should be the beginning of a register name.
634 If it is indeed a valid register name, advance CCP over it and
635 return the reg_entry structure; otherwise return NULL.
636 It does not issue diagnostics. */
639 parse_reg (char **ccp
)
645 #ifdef REGISTER_PREFIX
646 if (*start
!= REGISTER_PREFIX
)
652 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
657 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
659 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
668 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
671 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
673 if (reg
->type
== type
)
678 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
679 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
680 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
681 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
682 case REG_TYPE_VN
: /* Vector register. */
683 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
684 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
685 == reg_type_masks
[reg
->type
]);
687 as_fatal ("unhandled type %d", type
);
692 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
693 Return the register number otherwise. *ISREG32 is set to one if the
694 register is 32-bit wide; *ISREGZERO is set to one if the register is
695 of type Z_32 or Z_64.
696 Note that this function does not issue any diagnostics. */
699 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
700 int *isreg32
, int *isregzero
)
703 const reg_entry
*reg
= parse_reg (&str
);
708 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
717 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
722 *isreg32
= reg
->type
== REG_TYPE_R_32
;
729 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
741 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
742 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
743 otherwise return FALSE.
745 Accept only one occurrence of:
746 8b 16b 4h 8h 2s 4s 1d 2d
749 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
753 unsigned element_size
;
754 enum neon_el_type type
;
764 width
= strtoul (ptr
, &ptr
, 10);
765 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
767 first_error_fmt (_("bad size %d in vector width specifier"), width
);
772 switch (TOLOWER (*ptr
))
800 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
802 first_error (_("missing element size"));
805 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
808 ("invalid element size %d and vector size combination %c"),
814 parsed_type
->type
= type
;
815 parsed_type
->width
= width
;
822 /* Parse a single type, e.g. ".8b", leading period included.
823 Only applicable to Vn registers.
825 Return TRUE on success; otherwise return FALSE. */
827 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
833 if (! parse_neon_type_for_operand (vectype
, &str
))
835 first_error (_("vector type expected"));
847 /* Parse a register of the type TYPE.
849 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
850 name or the parsed register is not of TYPE.
852 Otherwise return the register number, and optionally fill in the actual
853 type of the register in *RTYPE when multiple alternatives were given, and
854 return the register shape and element index information in *TYPEINFO.
856 IN_REG_LIST should be set with TRUE if the caller is parsing a register
860 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
861 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
864 const reg_entry
*reg
= parse_reg (&str
);
865 struct neon_type_el atype
;
866 struct neon_type_el parsetype
;
867 bfd_boolean is_typed_vecreg
= FALSE
;
870 atype
.type
= NT_invtype
;
878 set_default_error ();
882 if (! aarch64_check_reg_type (reg
, type
))
884 DEBUG_TRACE ("reg type check failed");
885 set_default_error ();
890 if (type
== REG_TYPE_VN
891 && parse_neon_operand_type (&parsetype
, &str
))
893 /* Register if of the form Vn.[bhsdq]. */
894 is_typed_vecreg
= TRUE
;
896 if (parsetype
.width
== 0)
897 /* Expect index. In the new scheme we cannot have
898 Vn.[bhsdq] represent a scalar. Therefore any
899 Vn.[bhsdq] should have an index following it.
900 Except in reglists ofcourse. */
901 atype
.defined
|= NTA_HASINDEX
;
903 atype
.defined
|= NTA_HASTYPE
;
905 atype
.type
= parsetype
.type
;
906 atype
.width
= parsetype
.width
;
909 if (skip_past_char (&str
, '['))
913 /* Reject Sn[index] syntax. */
914 if (!is_typed_vecreg
)
916 first_error (_("this type of register can't be indexed"));
920 if (in_reg_list
== TRUE
)
922 first_error (_("index not allowed inside register list"));
926 atype
.defined
|= NTA_HASINDEX
;
928 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
930 if (exp
.X_op
!= O_constant
)
932 first_error (_("constant expression required"));
936 if (! skip_past_char (&str
, ']'))
939 atype
.index
= exp
.X_add_number
;
941 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
943 /* Indexed vector register expected. */
944 first_error (_("indexed vector register expected"));
948 /* A vector reg Vn should be typed or indexed. */
949 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
951 first_error (_("invalid use of vector register"));
967 Return the register number on success; return PARSE_FAIL otherwise.
969 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
970 the register (e.g. NEON double or quad reg when either has been requested).
972 If this is a NEON vector register with additional type information, fill
973 in the struct pointed to by VECTYPE (if non-NULL).
975 This parser does not handle register list. */
978 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
979 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
981 struct neon_type_el atype
;
983 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
984 /*in_reg_list= */ FALSE
);
986 if (reg
== PARSE_FAIL
)
997 static inline bfd_boolean
998 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1002 && e1
.defined
== e2
.defined
1003 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1006 /* This function parses the NEON register list. On success, it returns
1007 the parsed register list information in the following encoded format:
1009 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1010 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1012 The information of the register shape and/or index is returned in
1015 It returns PARSE_FAIL if the register list is invalid.
1017 The list contains one to four registers.
1018 Each register can be one of:
1021 All <T> should be identical.
1022 All <index> should be identical.
1023 There are restrictions on <Vt> numbers which are checked later
1024 (by reg_list_valid_p). */
1027 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1031 struct neon_type_el typeinfo
, typeinfo_first
;
1036 bfd_boolean error
= FALSE
;
1037 bfd_boolean expect_index
= FALSE
;
1041 set_syntax_error (_("expecting {"));
1047 typeinfo_first
.defined
= 0;
1048 typeinfo_first
.type
= NT_invtype
;
1049 typeinfo_first
.width
= -1;
1050 typeinfo_first
.index
= 0;
1059 str
++; /* skip over '-' */
1062 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1063 /*in_reg_list= */ TRUE
);
1064 if (val
== PARSE_FAIL
)
1066 set_first_syntax_error (_("invalid vector register in list"));
1070 /* reject [bhsd]n */
1071 if (typeinfo
.defined
== 0)
1073 set_first_syntax_error (_("invalid scalar register in list"));
1078 if (typeinfo
.defined
& NTA_HASINDEX
)
1079 expect_index
= TRUE
;
1083 if (val
< val_range
)
1085 set_first_syntax_error
1086 (_("invalid range in vector register list"));
1095 typeinfo_first
= typeinfo
;
1096 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1098 set_first_syntax_error
1099 (_("type mismatch in vector register list"));
1104 for (i
= val_range
; i
<= val
; i
++)
1106 ret_val
|= i
<< (5 * nb_regs
);
1111 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1113 skip_whitespace (str
);
1116 set_first_syntax_error (_("end of vector register list not found"));
1121 skip_whitespace (str
);
1125 if (skip_past_char (&str
, '['))
1129 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1130 if (exp
.X_op
!= O_constant
)
1132 set_first_syntax_error (_("constant expression required."));
1135 if (! skip_past_char (&str
, ']'))
1138 typeinfo_first
.index
= exp
.X_add_number
;
1142 set_first_syntax_error (_("expected index"));
1149 set_first_syntax_error (_("too many registers in vector register list"));
1152 else if (nb_regs
== 0)
1154 set_first_syntax_error (_("empty vector register list"));
1160 *vectype
= typeinfo_first
;
1162 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1165 /* Directives: register aliases. */
1168 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1173 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1176 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1179 /* Only warn about a redefinition if it's not defined as the
1181 else if (new->number
!= number
|| new->type
!= type
)
1182 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1187 name
= xstrdup (str
);
1188 new = xmalloc (sizeof (reg_entry
));
1191 new->number
= number
;
1193 new->builtin
= FALSE
;
1195 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1201 /* Look for the .req directive. This is of the form:
1203 new_register_name .req existing_register_name
1205 If we find one, or if it looks sufficiently like one that we want to
1206 handle any error here, return TRUE. Otherwise return FALSE. */
1209 create_register_alias (char *newname
, char *p
)
1211 const reg_entry
*old
;
1212 char *oldname
, *nbuf
;
1215 /* The input scrubber ensures that whitespace after the mnemonic is
1216 collapsed to single spaces. */
1218 if (strncmp (oldname
, " .req ", 6) != 0)
1222 if (*oldname
== '\0')
1225 old
= hash_find (aarch64_reg_hsh
, oldname
);
1228 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1232 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1233 the desired alias name, and p points to its end. If not, then
1234 the desired alias name is in the global original_case_string. */
1235 #ifdef TC_CASE_SENSITIVE
1238 newname
= original_case_string
;
1239 nlen
= strlen (newname
);
1242 nbuf
= alloca (nlen
+ 1);
1243 memcpy (nbuf
, newname
, nlen
);
1246 /* Create aliases under the new name as stated; an all-lowercase
1247 version of the new name; and an all-uppercase version of the new
1249 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1256 /* If this attempt to create an additional alias fails, do not bother
1257 trying to create the all-lower case alias. We will fail and issue
1258 a second, duplicate error message. This situation arises when the
1259 programmer does something like:
1262 The second .req creates the "Foo" alias but then fails to create
1263 the artificial FOO alias because it has already been created by the
1265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1269 for (p
= nbuf
; *p
; p
++)
1272 if (strncmp (nbuf
, newname
, nlen
))
1273 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1279 /* Should never be called, as .req goes between the alias and the
1280 register name, not at the beginning of the line. */
1282 s_req (int a ATTRIBUTE_UNUSED
)
1284 as_bad (_("invalid syntax for .req directive"));
1287 /* The .unreq directive deletes an alias which was previously defined
1288 by .req. For example:
1294 s_unreq (int a ATTRIBUTE_UNUSED
)
1299 name
= input_line_pointer
;
1301 while (*input_line_pointer
!= 0
1302 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1303 ++input_line_pointer
;
1305 saved_char
= *input_line_pointer
;
1306 *input_line_pointer
= 0;
1309 as_bad (_("invalid syntax for .unreq directive"));
1312 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1315 as_bad (_("unknown register alias '%s'"), name
);
1316 else if (reg
->builtin
)
1317 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1324 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1325 free ((char *) reg
->name
);
1328 /* Also locate the all upper case and all lower case versions.
1329 Do not complain if we cannot find one or the other as it
1330 was probably deleted above. */
1332 nbuf
= strdup (name
);
1333 for (p
= nbuf
; *p
; p
++)
1335 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1338 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1339 free ((char *) reg
->name
);
1343 for (p
= nbuf
; *p
; p
++)
1345 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1348 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1349 free ((char *) reg
->name
);
1357 *input_line_pointer
= saved_char
;
1358 demand_empty_rest_of_line ();
1361 /* Directives: Instruction set selection. */
1364 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1365 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1366 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1367 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1369 /* Create a new mapping symbol for the transition to STATE. */
1372 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1375 const char *symname
;
1382 type
= BSF_NO_FLAGS
;
1386 type
= BSF_NO_FLAGS
;
1392 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1393 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1395 /* Save the mapping symbols for future reference. Also check that
1396 we do not place two mapping symbols at the same offset within a
1397 frag. We'll handle overlap between frags in
1398 check_mapping_symbols.
1400 If .fill or other data filling directive generates zero sized data,
1401 the mapping symbol for the following code will have the same value
1402 as the one generated for the data filling directive. In this case,
1403 we replace the old symbol with the new one at the same address. */
1406 if (frag
->tc_frag_data
.first_map
!= NULL
)
1408 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1409 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1412 frag
->tc_frag_data
.first_map
= symbolP
;
1414 if (frag
->tc_frag_data
.last_map
!= NULL
)
1416 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1417 S_GET_VALUE (symbolP
));
1418 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1419 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1422 frag
->tc_frag_data
.last_map
= symbolP
;
1425 /* We must sometimes convert a region marked as code to data during
1426 code alignment, if an odd number of bytes have to be padded. The
1427 code mapping symbol is pushed to an aligned address. */
1430 insert_data_mapping_symbol (enum mstate state
,
1431 valueT value
, fragS
* frag
, offsetT bytes
)
1433 /* If there was already a mapping symbol, remove it. */
1434 if (frag
->tc_frag_data
.last_map
!= NULL
1435 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1436 frag
->fr_address
+ value
)
1438 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1442 know (frag
->tc_frag_data
.first_map
== symp
);
1443 frag
->tc_frag_data
.first_map
= NULL
;
1445 frag
->tc_frag_data
.last_map
= NULL
;
1446 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1449 make_mapping_symbol (MAP_DATA
, value
, frag
);
1450 make_mapping_symbol (state
, value
+ bytes
, frag
);
1453 static void mapping_state_2 (enum mstate state
, int max_chars
);
1455 /* Set the mapping state to STATE. Only call this when about to
1456 emit some STATE bytes to the file. */
1459 mapping_state (enum mstate state
)
1461 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1463 if (state
== MAP_INSN
)
1464 /* AArch64 instructions require 4-byte alignment. When emitting
1465 instructions into any section, record the appropriate section
1467 record_alignment (now_seg
, 2);
1469 if (mapstate
== state
)
1470 /* The mapping symbol has already been emitted.
1471 There is nothing else to do. */
1474 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1475 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1476 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1477 evaluated later in the next else. */
1479 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1481 /* Only add the symbol if the offset is > 0:
1482 if we're at the first frag, check it's size > 0;
1483 if we're not at the first frag, then for sure
1484 the offset is > 0. */
1485 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1486 const int add_symbol
= (frag_now
!= frag_first
)
1487 || (frag_now_fix () > 0);
1490 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1494 mapping_state_2 (state
, 0);
1497 /* Same as mapping_state, but MAX_CHARS bytes have already been
1498 allocated. Put the mapping symbol that far back. */
1501 mapping_state_2 (enum mstate state
, int max_chars
)
1503 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1505 if (!SEG_NORMAL (now_seg
))
1508 if (mapstate
== state
)
1509 /* The mapping symbol has already been emitted.
1510 There is nothing else to do. */
1513 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1514 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1517 #define mapping_state(x) /* nothing */
1518 #define mapping_state_2(x, y) /* nothing */
1521 /* Directives: sectioning and alignment. */
1524 s_bss (int ignore ATTRIBUTE_UNUSED
)
1526 /* We don't support putting frags in the BSS segment, we fake it by
1527 marking in_bss, then looking at s_skip for clues. */
1528 subseg_set (bss_section
, 0);
1529 demand_empty_rest_of_line ();
1530 mapping_state (MAP_DATA
);
1534 s_even (int ignore ATTRIBUTE_UNUSED
)
1536 /* Never make frag if expect extra pass. */
1538 frag_align (1, 0, 0);
1540 record_alignment (now_seg
, 1);
1542 demand_empty_rest_of_line ();
1545 /* Directives: Literal pools. */
1547 static literal_pool
*
1548 find_literal_pool (int size
)
1552 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1554 if (pool
->section
== now_seg
1555 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1562 static literal_pool
*
1563 find_or_make_literal_pool (int size
)
1565 /* Next literal pool ID number. */
1566 static unsigned int latest_pool_num
= 1;
1569 pool
= find_literal_pool (size
);
1573 /* Create a new pool. */
1574 pool
= xmalloc (sizeof (*pool
));
1578 /* Currently we always put the literal pool in the current text
1579 section. If we were generating "small" model code where we
1580 knew that all code and initialised data was within 1MB then
1581 we could output literals to mergeable, read-only data
1584 pool
->next_free_entry
= 0;
1585 pool
->section
= now_seg
;
1586 pool
->sub_section
= now_subseg
;
1588 pool
->next
= list_of_pools
;
1589 pool
->symbol
= NULL
;
1591 /* Add it to the list. */
1592 list_of_pools
= pool
;
1595 /* New pools, and emptied pools, will have a NULL symbol. */
1596 if (pool
->symbol
== NULL
)
1598 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1599 (valueT
) 0, &zero_address_frag
);
1600 pool
->id
= latest_pool_num
++;
1607 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1608 Return TRUE on success, otherwise return FALSE. */
1610 add_to_lit_pool (expressionS
*exp
, int size
)
1615 pool
= find_or_make_literal_pool (size
);
1617 /* Check if this literal value is already in the pool. */
1618 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1620 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1622 if ((litexp
->X_op
== exp
->X_op
)
1623 && (exp
->X_op
== O_constant
)
1624 && (litexp
->X_add_number
== exp
->X_add_number
)
1625 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1628 if ((litexp
->X_op
== exp
->X_op
)
1629 && (exp
->X_op
== O_symbol
)
1630 && (litexp
->X_add_number
== exp
->X_add_number
)
1631 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1632 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1636 /* Do we need to create a new entry? */
1637 if (entry
== pool
->next_free_entry
)
1639 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1641 set_syntax_error (_("literal pool overflow"));
1645 pool
->literals
[entry
].exp
= *exp
;
1646 pool
->next_free_entry
+= 1;
1647 if (exp
->X_op
== O_big
)
1649 /* PR 16688: Bignums are held in a single global array. We must
1650 copy and preserve that value now, before it is overwritten. */
1651 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1652 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1653 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1656 pool
->literals
[entry
].bignum
= NULL
;
1659 exp
->X_op
= O_symbol
;
1660 exp
->X_add_number
= ((int) entry
) * size
;
1661 exp
->X_add_symbol
= pool
->symbol
;
1666 /* Can't use symbol_new here, so have to create a symbol and then at
1667 a later date assign it a value. Thats what these functions do. */
1670 symbol_locate (symbolS
* symbolP
,
1671 const char *name
,/* It is copied, the caller can modify. */
1672 segT segment
, /* Segment identifier (SEG_<something>). */
1673 valueT valu
, /* Symbol value. */
1674 fragS
* frag
) /* Associated fragment. */
1677 char *preserved_copy_of_name
;
1679 name_length
= strlen (name
) + 1; /* +1 for \0. */
1680 obstack_grow (¬es
, name
, name_length
);
1681 preserved_copy_of_name
= obstack_finish (¬es
);
1683 #ifdef tc_canonicalize_symbol_name
1684 preserved_copy_of_name
=
1685 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1688 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1690 S_SET_SEGMENT (symbolP
, segment
);
1691 S_SET_VALUE (symbolP
, valu
);
1692 symbol_clear_list_pointers (symbolP
);
1694 symbol_set_frag (symbolP
, frag
);
1696 /* Link to end of symbol chain. */
1698 extern int symbol_table_frozen
;
1700 if (symbol_table_frozen
)
1704 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1706 obj_symbol_new_hook (symbolP
);
1708 #ifdef tc_symbol_new_hook
1709 tc_symbol_new_hook (symbolP
);
1713 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1714 #endif /* DEBUG_SYMS */
1719 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1726 for (align
= 2; align
<= 4; align
++)
1728 int size
= 1 << align
;
1730 pool
= find_literal_pool (size
);
1731 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1734 mapping_state (MAP_DATA
);
1736 /* Align pool as you have word accesses.
1737 Only make a frag if we have to. */
1739 frag_align (align
, 0, 0);
1741 record_alignment (now_seg
, align
);
1743 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1745 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1746 (valueT
) frag_now_fix (), frag_now
);
1747 symbol_table_insert (pool
->symbol
);
1749 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1751 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1753 if (exp
->X_op
== O_big
)
1755 /* PR 16688: Restore the global bignum value. */
1756 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1757 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1758 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1761 /* First output the expression in the instruction to the pool. */
1762 emit_expr (exp
, size
); /* .word|.xword */
1764 if (exp
->X_op
== O_big
)
1766 free (pool
->literals
[entry
].bignum
);
1767 pool
->literals
[entry
].bignum
= NULL
;
1771 /* Mark the pool as empty. */
1772 pool
->next_free_entry
= 0;
1773 pool
->symbol
= NULL
;
1778 /* Forward declarations for functions below, in the MD interface
1780 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1781 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1783 /* Directives: Data. */
1784 /* N.B. the support for relocation suffix in this directive needs to be
1785 implemented properly. */
1788 s_aarch64_elf_cons (int nbytes
)
1792 #ifdef md_flush_pending_output
1793 md_flush_pending_output ();
1796 if (is_it_end_of_statement ())
1798 demand_empty_rest_of_line ();
1802 #ifdef md_cons_align
1803 md_cons_align (nbytes
);
1806 mapping_state (MAP_DATA
);
1809 struct reloc_table_entry
*reloc
;
1813 if (exp
.X_op
!= O_symbol
)
1814 emit_expr (&exp
, (unsigned int) nbytes
);
1817 skip_past_char (&input_line_pointer
, '#');
1818 if (skip_past_char (&input_line_pointer
, ':'))
1820 reloc
= find_reloc_table_entry (&input_line_pointer
);
1822 as_bad (_("unrecognized relocation suffix"));
1824 as_bad (_("unimplemented relocation suffix"));
1825 ignore_rest_of_line ();
1829 emit_expr (&exp
, (unsigned int) nbytes
);
1832 while (*input_line_pointer
++ == ',');
1834 /* Put terminator back into stream. */
1835 input_line_pointer
--;
1836 demand_empty_rest_of_line ();
1839 #endif /* OBJ_ELF */
1841 /* Output a 32-bit word, but mark as an instruction. */
1844 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1848 #ifdef md_flush_pending_output
1849 md_flush_pending_output ();
1852 if (is_it_end_of_statement ())
1854 demand_empty_rest_of_line ();
1858 /* Sections are assumed to start aligned. In executable section, there is no
1859 MAP_DATA symbol pending. So we only align the address during
1860 MAP_DATA --> MAP_INSN transition.
1861 For other sections, this is not guaranteed. */
1862 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1863 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1864 frag_align_code (2, 0);
1867 mapping_state (MAP_INSN
);
1873 if (exp
.X_op
!= O_constant
)
1875 as_bad (_("constant expression required"));
1876 ignore_rest_of_line ();
1880 if (target_big_endian
)
1882 unsigned int val
= exp
.X_add_number
;
1883 exp
.X_add_number
= SWAP_32 (val
);
1885 emit_expr (&exp
, 4);
1887 while (*input_line_pointer
++ == ',');
1889 /* Put terminator back into stream. */
1890 input_line_pointer
--;
1891 demand_empty_rest_of_line ();
1895 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1898 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1902 /* Since we're just labelling the code, there's no need to define a
1905 /* Make sure there is enough room in this frag for the following
1906 blr. This trick only works if the blr follows immediately after
1907 the .tlsdesc directive. */
1909 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1910 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1912 demand_empty_rest_of_line ();
1914 #endif /* OBJ_ELF */
1916 static void s_aarch64_arch (int);
1917 static void s_aarch64_cpu (int);
1918 static void s_aarch64_arch_extension (int);
1920 /* This table describes all the machine specific pseudo-ops the assembler
1921 has to support. The fields are:
1922 pseudo-op name without dot
1923 function to call to execute this pseudo-op
1924 Integer arg to pass to the function. */
1926 const pseudo_typeS md_pseudo_table
[] = {
1927 /* Never called because '.req' does not start a line. */
1929 {"unreq", s_unreq
, 0},
1931 {"even", s_even
, 0},
1932 {"ltorg", s_ltorg
, 0},
1933 {"pool", s_ltorg
, 0},
1934 {"cpu", s_aarch64_cpu
, 0},
1935 {"arch", s_aarch64_arch
, 0},
1936 {"arch_extension", s_aarch64_arch_extension
, 0},
1937 {"inst", s_aarch64_inst
, 0},
1939 {"tlsdesccall", s_tlsdesccall
, 0},
1940 {"word", s_aarch64_elf_cons
, 4},
1941 {"long", s_aarch64_elf_cons
, 4},
1942 {"xword", s_aarch64_elf_cons
, 8},
1943 {"dword", s_aarch64_elf_cons
, 8},
1949 /* Check whether STR points to a register name followed by a comma or the
1950 end of line; REG_TYPE indicates which register types are checked
1951 against. Return TRUE if STR is such a register name; otherwise return
1952 FALSE. The function does not intend to produce any diagnostics, but since
1953 the register parser aarch64_reg_parse, which is called by this function,
1954 does produce diagnostics, we call clear_error to clear any diagnostics
1955 that may be generated by aarch64_reg_parse.
1956 Also, the function returns FALSE directly if there is any user error
1957 present at the function entry. This prevents the existing diagnostics
1958 state from being spoiled.
1959 The function currently serves parse_constant_immediate and
1960 parse_big_immediate only. */
1962 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1966 /* Prevent the diagnostics state from being spoiled. */
1970 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1972 /* Clear the parsing error that may be set by the reg parser. */
1975 if (reg
== PARSE_FAIL
)
1978 skip_whitespace (str
);
1979 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1985 /* Parser functions used exclusively in instruction operands. */
1987 /* Parse an immediate expression which may not be constant.
1989 To prevent the expression parser from pushing a register name
1990 into the symbol table as an undefined symbol, firstly a check is
1991 done to find out whether STR is a valid register name followed
1992 by a comma or the end of line. Return FALSE if STR is such a
1996 parse_immediate_expression (char **str
, expressionS
*exp
)
1998 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2000 set_recoverable_error (_("immediate operand required"));
2004 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2006 if (exp
->X_op
== O_absent
)
2008 set_fatal_syntax_error (_("missing immediate expression"));
2015 /* Constant immediate-value read function for use in insn parsing.
2016 STR points to the beginning of the immediate (with the optional
2017 leading #); *VAL receives the value.
2019 Return TRUE on success; otherwise return FALSE. */
2022 parse_constant_immediate (char **str
, int64_t * val
)
2026 if (! parse_immediate_expression (str
, &exp
))
2029 if (exp
.X_op
!= O_constant
)
2031 set_syntax_error (_("constant expression required"));
2035 *val
= exp
.X_add_number
;
2040 encode_imm_float_bits (uint32_t imm
)
2042 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2043 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2046 /* Return TRUE if the single-precision floating-point value encoded in IMM
2047 can be expressed in the AArch64 8-bit signed floating-point format with
2048 3-bit exponent and normalized 4 bits of precision; in other words, the
2049 floating-point value must be expressable as
2050 (+/-) n / 16 * power (2, r)
2051 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2054 aarch64_imm_float_p (uint32_t imm
)
2056 /* If a single-precision floating-point value has the following bit
2057 pattern, it can be expressed in the AArch64 8-bit floating-point
2060 3 32222222 2221111111111
2061 1 09876543 21098765432109876543210
2062 n Eeeeeexx xxxx0000000000000000000
2064 where n, e and each x are either 0 or 1 independently, with
2069 /* Prepare the pattern for 'Eeeeee'. */
2070 if (((imm
>> 30) & 0x1) == 0)
2071 pattern
= 0x3e000000;
2073 pattern
= 0x40000000;
2075 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2076 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2079 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2081 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2082 8-bit signed floating-point format with 3-bit exponent and normalized 4
2083 bits of precision (i.e. can be used in an FMOV instruction); return the
2084 equivalent single-precision encoding in *FPWORD.
2086 Otherwise return FALSE. */
2089 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2091 /* If a double-precision floating-point value has the following bit
2092 pattern, it can be expressed in the AArch64 8-bit floating-point
2095 6 66655555555 554444444...21111111111
2096 3 21098765432 109876543...098765432109876543210
2097 n Eeeeeeeeexx xxxx00000...000000000000000000000
2099 where n, e and each x are either 0 or 1 independently, with
2103 uint32_t high32
= imm
>> 32;
2105 /* Lower 32 bits need to be 0s. */
2106 if ((imm
& 0xffffffff) != 0)
2109 /* Prepare the pattern for 'Eeeeeeeee'. */
2110 if (((high32
>> 30) & 0x1) == 0)
2111 pattern
= 0x3fc00000;
2113 pattern
= 0x40000000;
2115 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2116 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2118 /* Convert to the single-precision encoding.
2120 n Eeeeeeeeexx xxxx00000...000000000000000000000
2122 n Eeeeeexx xxxx0000000000000000000. */
2123 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2124 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2131 /* Parse a floating-point immediate. Return TRUE on success and return the
2132 value in *IMMED in the format of IEEE754 single-precision encoding.
2133 *CCP points to the start of the string; DP_P is TRUE when the immediate
2134 is expected to be in double-precision (N.B. this only matters when
2135 hexadecimal representation is involved).
2137 N.B. 0.0 is accepted by this function. */
2140 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2144 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2145 int found_fpchar
= 0;
2147 unsigned fpword
= 0;
2148 bfd_boolean hex_p
= FALSE
;
2150 skip_past_char (&str
, '#');
2153 skip_whitespace (fpnum
);
2155 if (strncmp (fpnum
, "0x", 2) == 0)
2157 /* Support the hexadecimal representation of the IEEE754 encoding.
2158 Double-precision is expected when DP_P is TRUE, otherwise the
2159 representation should be in single-precision. */
2160 if (! parse_constant_immediate (&str
, &val
))
2165 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2168 else if ((uint64_t) val
> 0xffffffff)
2177 /* We must not accidentally parse an integer as a floating-point number.
2178 Make sure that the value we parse is not an integer by checking for
2179 special characters '.' or 'e'. */
2180 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2181 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2195 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2198 /* Our FP word must be 32 bits (single-precision FP). */
2199 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2201 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2206 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2214 set_fatal_syntax_error (_("invalid floating-point constant"));
2218 /* Less-generic immediate-value read function with the possibility of loading
2219 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2222 To prevent the expression parser from pushing a register name into the
2223 symbol table as an undefined symbol, a check is firstly done to find
2224 out whether STR is a valid register name followed by a comma or the end
2225 of line. Return FALSE if STR is such a register. */
2228 parse_big_immediate (char **str
, int64_t *imm
)
2232 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2234 set_syntax_error (_("immediate operand required"));
2238 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2240 if (inst
.reloc
.exp
.X_op
== O_constant
)
2241 *imm
= inst
.reloc
.exp
.X_add_number
;
2248 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2249 if NEED_LIBOPCODES is non-zero, the fixup will need
2250 assistance from the libopcodes. */
2253 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2254 const aarch64_opnd_info
*operand
,
2255 int need_libopcodes_p
)
2257 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2258 reloc
->opnd
= operand
->type
;
2259 if (need_libopcodes_p
)
2260 reloc
->need_libopcodes_p
= 1;
2263 /* Return TRUE if the instruction needs to be fixed up later internally by
2264 the GAS; otherwise return FALSE. */
2266 static inline bfd_boolean
2267 aarch64_gas_internal_fixup_p (void)
2269 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2272 /* Assign the immediate value to the relavant field in *OPERAND if
2273 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2274 needs an internal fixup in a later stage.
2275 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2276 IMM.VALUE that may get assigned with the constant. */
2278 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2279 aarch64_opnd_info
*operand
,
2281 int need_libopcodes_p
,
2284 if (reloc
->exp
.X_op
== O_constant
)
2287 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2289 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2290 reloc
->type
= BFD_RELOC_UNUSED
;
2294 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2295 /* Tell libopcodes to ignore this operand or not. This is helpful
2296 when one of the operands needs to be fixed up later but we need
2297 libopcodes to check the other operands. */
2298 operand
->skip
= skip_p
;
2302 /* Relocation modifiers. Each entry in the table contains the textual
2303 name for the relocation which may be placed before a symbol used as
2304 a load/store offset, or add immediate. It must be surrounded by a
2305 leading and trailing colon, for example:
2307 ldr x0, [x1, #:rello:varsym]
2308 add x0, x1, #:rello:varsym */
2310 struct reloc_table_entry
2314 bfd_reloc_code_real_type adr_type
;
2315 bfd_reloc_code_real_type adrp_type
;
2316 bfd_reloc_code_real_type movw_type
;
2317 bfd_reloc_code_real_type add_type
;
2318 bfd_reloc_code_real_type ldst_type
;
2319 bfd_reloc_code_real_type ld_literal_type
;
2322 static struct reloc_table_entry reloc_table
[] = {
2323 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2328 BFD_RELOC_AARCH64_ADD_LO12
,
2329 BFD_RELOC_AARCH64_LDST_LO12
,
2332 /* Higher 21 bits of pc-relative page offset: ADRP */
2335 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2341 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2344 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2350 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2354 BFD_RELOC_AARCH64_MOVW_G0
,
2359 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2363 BFD_RELOC_AARCH64_MOVW_G0_S
,
2368 /* Less significant bits 0-15 of address/value: MOVK, no check */
2372 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2377 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2381 BFD_RELOC_AARCH64_MOVW_G1
,
2386 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2390 BFD_RELOC_AARCH64_MOVW_G1_S
,
2395 /* Less significant bits 16-31 of address/value: MOVK, no check */
2399 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2404 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2408 BFD_RELOC_AARCH64_MOVW_G2
,
2413 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2417 BFD_RELOC_AARCH64_MOVW_G2_S
,
2422 /* Less significant bits 32-47 of address/value: MOVK, no check */
2426 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2431 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2435 BFD_RELOC_AARCH64_MOVW_G3
,
2440 /* Get to the page containing GOT entry for a symbol. */
2443 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2447 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2449 /* 12 bit offset into the page containing GOT entry for that symbol. */
2455 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2458 /* Get to the page containing GOT TLS entry for a symbol */
2460 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2461 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2467 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2472 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2476 /* Get to the page containing GOT TLS entry for a symbol */
2478 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2479 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2483 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2485 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2490 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2491 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2494 /* Get to the page containing GOT TLS entry for a symbol */
2497 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2501 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2503 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2504 {"gottprel_lo12", 0,
2509 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2512 /* Get tp offset for a symbol. */
2517 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2521 /* Get tp offset for a symbol. */
2526 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2530 /* Get tp offset for a symbol. */
2535 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2539 /* Get tp offset for a symbol. */
2540 {"tprel_lo12_nc", 0,
2544 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2548 /* Most significant bits 32-47 of address/value: MOVZ. */
2552 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2557 /* Most significant bits 16-31 of address/value: MOVZ. */
2561 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2566 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2570 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2575 /* Most significant bits 0-15 of address/value: MOVZ. */
2579 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2584 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2588 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2594 /* Given the address of a pointer pointing to the textual name of a
2595 relocation as may appear in assembler source, attempt to find its
2596 details in reloc_table. The pointer will be updated to the character
2597 after the trailing colon. On failure, NULL will be returned;
2598 otherwise return the reloc_table_entry. */
2600 static struct reloc_table_entry
*
2601 find_reloc_table_entry (char **str
)
2604 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2606 int length
= strlen (reloc_table
[i
].name
);
2608 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2609 && (*str
)[length
] == ':')
2611 *str
+= (length
+ 1);
2612 return &reloc_table
[i
];
2619 /* Mode argument to parse_shift and parser_shifter_operand. */
2620 enum parse_shift_mode
2622 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2624 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2626 SHIFTED_LSL
, /* bare "lsl #n" */
2627 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2628 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2631 /* Parse a <shift> operator on an AArch64 data processing instruction.
2632 Return TRUE on success; otherwise return FALSE. */
2634 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2636 const struct aarch64_name_value_pair
*shift_op
;
2637 enum aarch64_modifier_kind kind
;
2643 for (p
= *str
; ISALPHA (*p
); p
++)
2648 set_syntax_error (_("shift expression expected"));
2652 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2654 if (shift_op
== NULL
)
2656 set_syntax_error (_("shift operator expected"));
2660 kind
= aarch64_get_operand_modifier (shift_op
);
2662 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2664 set_syntax_error (_("invalid use of 'MSL'"));
2670 case SHIFTED_LOGIC_IMM
:
2671 if (aarch64_extend_operator_p (kind
) == TRUE
)
2673 set_syntax_error (_("extending shift is not permitted"));
2678 case SHIFTED_ARITH_IMM
:
2679 if (kind
== AARCH64_MOD_ROR
)
2681 set_syntax_error (_("'ROR' shift is not permitted"));
2687 if (kind
!= AARCH64_MOD_LSL
)
2689 set_syntax_error (_("only 'LSL' shift is permitted"));
2694 case SHIFTED_REG_OFFSET
:
2695 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2696 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2698 set_fatal_syntax_error
2699 (_("invalid shift for the register offset addressing mode"));
2704 case SHIFTED_LSL_MSL
:
2705 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2707 set_syntax_error (_("invalid shift operator"));
2716 /* Whitespace can appear here if the next thing is a bare digit. */
2717 skip_whitespace (p
);
2719 /* Parse shift amount. */
2721 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2722 exp
.X_op
= O_absent
;
2725 if (is_immediate_prefix (*p
))
2730 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2732 if (exp
.X_op
== O_absent
)
2734 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2736 set_syntax_error (_("missing shift amount"));
2739 operand
->shifter
.amount
= 0;
2741 else if (exp
.X_op
!= O_constant
)
2743 set_syntax_error (_("constant shift amount required"));
2746 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2748 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2753 operand
->shifter
.amount
= exp
.X_add_number
;
2754 operand
->shifter
.amount_present
= 1;
2757 operand
->shifter
.operator_present
= 1;
2758 operand
->shifter
.kind
= kind
;
2764 /* Parse a <shifter_operand> for a data processing instruction:
2767 #<immediate>, LSL #imm
2769 Validation of immediate operands is deferred to md_apply_fix.
2771 Return TRUE on success; otherwise return FALSE. */
2774 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2775 enum parse_shift_mode mode
)
2779 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2784 /* Accept an immediate expression. */
2785 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2788 /* Accept optional LSL for arithmetic immediate values. */
2789 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2790 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2793 /* Not accept any shifter for logical immediate values. */
2794 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2795 && parse_shift (&p
, operand
, mode
))
2797 set_syntax_error (_("unexpected shift operator"));
2805 /* Parse a <shifter_operand> for a data processing instruction:
2810 #<immediate>, LSL #imm
2812 where <shift> is handled by parse_shift above, and the last two
2813 cases are handled by the function above.
2815 Validation of immediate operands is deferred to md_apply_fix.
2817 Return TRUE on success; otherwise return FALSE. */
2820 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2821 enum parse_shift_mode mode
)
2824 int isreg32
, isregzero
;
2825 enum aarch64_operand_class opd_class
2826 = aarch64_get_operand_class (operand
->type
);
2829 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2831 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2833 set_syntax_error (_("unexpected register in the immediate operand"));
2837 if (!isregzero
&& reg
== REG_SP
)
2839 set_syntax_error (BAD_SP
);
2843 operand
->reg
.regno
= reg
;
2844 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2846 /* Accept optional shift operation on register. */
2847 if (! skip_past_comma (str
))
2850 if (! parse_shift (str
, operand
, mode
))
2855 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2858 (_("integer register expected in the extended/shifted operand "
2863 /* We have a shifted immediate variable. */
2864 return parse_shifter_operand_imm (str
, operand
, mode
);
2867 /* Return TRUE on success; return FALSE otherwise. */
2870 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
2871 enum parse_shift_mode mode
)
2875 /* Determine if we have the sequence of characters #: or just :
2876 coming next. If we do, then we check for a :rello: relocation
2877 modifier. If we don't, punt the whole lot to
2878 parse_shifter_operand. */
2880 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
2882 struct reloc_table_entry
*entry
;
2890 /* Try to parse a relocation. Anything else is an error. */
2891 if (!(entry
= find_reloc_table_entry (str
)))
2893 set_syntax_error (_("unknown relocation modifier"));
2897 if (entry
->add_type
== 0)
2900 (_("this relocation modifier is not allowed on this instruction"));
2904 /* Save str before we decompose it. */
2907 /* Next, we parse the expression. */
2908 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
2911 /* Record the relocation type (use the ADD variant here). */
2912 inst
.reloc
.type
= entry
->add_type
;
2913 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2915 /* If str is empty, we've reached the end, stop here. */
2919 /* Otherwise, we have a shifted reloc modifier, so rewind to
2920 recover the variable name and continue parsing for the shifter. */
2922 return parse_shifter_operand_imm (str
, operand
, mode
);
2925 return parse_shifter_operand (str
, operand
, mode
);
2928 /* Parse all forms of an address expression. Information is written
2929 to *OPERAND and/or inst.reloc.
2931 The A64 instruction set has the following addressing modes:
2934 [base] // in SIMD ld/st structure
2935 [base{,#0}] // in ld/st exclusive
2937 [base,Xm{,LSL #imm}]
2938 [base,Xm,SXTX {#imm}]
2939 [base,Wm,(S|U)XTW {#imm}]
2944 [base],Xm // in SIMD ld/st structure
2945 PC-relative (literal)
2949 (As a convenience, the notation "=immediate" is permitted in conjunction
2950 with the pc-relative literal load instructions to automatically place an
2951 immediate value or symbolic address in a nearby literal pool and generate
2952 a hidden label which references it.)
2954 Upon a successful parsing, the address structure in *OPERAND will be
2955 filled in the following way:
2957 .base_regno = <base>
2958 .offset.is_reg // 1 if the offset is a register
2960 .offset.regno = <Rm>
2962 For different addressing modes defined in the A64 ISA:
2965 .pcrel=0; .preind=1; .postind=0; .writeback=0
2967 .pcrel=0; .preind=1; .postind=0; .writeback=1
2969 .pcrel=0; .preind=0; .postind=1; .writeback=1
2970 PC-relative (literal)
2971 .pcrel=1; .preind=1; .postind=0; .writeback=0
2973 The shift/extension information, if any, will be stored in .shifter.
2975 It is the caller's responsibility to check for addressing modes not
2976 supported by the instruction, and to set inst.reloc.type. */
2979 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
2980 int accept_reg_post_index
)
2984 int isreg32
, isregzero
;
2985 expressionS
*exp
= &inst
.reloc
.exp
;
2987 if (! skip_past_char (&p
, '['))
2989 /* =immediate or label. */
2990 operand
->addr
.pcrel
= 1;
2991 operand
->addr
.preind
= 1;
2993 /* #:<reloc_op>:<symbol> */
2994 skip_past_char (&p
, '#');
2995 if (reloc
&& skip_past_char (&p
, ':'))
2997 bfd_reloc_code_real_type ty
;
2998 struct reloc_table_entry
*entry
;
3000 /* Try to parse a relocation modifier. Anything else is
3002 entry
= find_reloc_table_entry (&p
);
3005 set_syntax_error (_("unknown relocation modifier"));
3009 switch (operand
->type
)
3011 case AARCH64_OPND_ADDR_PCREL21
:
3013 ty
= entry
->adr_type
;
3017 ty
= entry
->ld_literal_type
;
3024 (_("this relocation modifier is not allowed on this "
3030 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3032 set_syntax_error (_("invalid relocation expression"));
3036 /* #:<reloc_op>:<expr> */
3037 /* Record the relocation type. */
3038 inst
.reloc
.type
= ty
;
3039 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3044 if (skip_past_char (&p
, '='))
3045 /* =immediate; need to generate the literal in the literal pool. */
3046 inst
.gen_lit_pool
= 1;
3048 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3050 set_syntax_error (_("invalid address"));
3061 /* Accept SP and reject ZR */
3062 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3063 if (reg
== PARSE_FAIL
|| isreg32
)
3065 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3068 operand
->addr
.base_regno
= reg
;
3071 if (skip_past_comma (&p
))
3074 operand
->addr
.preind
= 1;
3076 /* Reject SP and accept ZR */
3077 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3078 if (reg
!= PARSE_FAIL
)
3081 operand
->addr
.offset
.regno
= reg
;
3082 operand
->addr
.offset
.is_reg
= 1;
3083 /* Shifted index. */
3084 if (skip_past_comma (&p
))
3087 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3088 /* Use the diagnostics set in parse_shift, so not set new
3089 error message here. */
3093 [base,Xm{,LSL #imm}]
3094 [base,Xm,SXTX {#imm}]
3095 [base,Wm,(S|U)XTW {#imm}] */
3096 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3097 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3098 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3102 set_syntax_error (_("invalid use of 32-bit register offset"));
3108 set_syntax_error (_("invalid use of 64-bit register offset"));
3114 /* [Xn,#:<reloc_op>:<symbol> */
3115 skip_past_char (&p
, '#');
3116 if (reloc
&& skip_past_char (&p
, ':'))
3118 struct reloc_table_entry
*entry
;
3120 /* Try to parse a relocation modifier. Anything else is
3122 if (!(entry
= find_reloc_table_entry (&p
)))
3124 set_syntax_error (_("unknown relocation modifier"));
3128 if (entry
->ldst_type
== 0)
3131 (_("this relocation modifier is not allowed on this "
3136 /* [Xn,#:<reloc_op>: */
3137 /* We now have the group relocation table entry corresponding to
3138 the name in the assembler source. Next, we parse the
3140 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3142 set_syntax_error (_("invalid relocation expression"));
3146 /* [Xn,#:<reloc_op>:<expr> */
3147 /* Record the load/store relocation type. */
3148 inst
.reloc
.type
= entry
->ldst_type
;
3149 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3151 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3153 set_syntax_error (_("invalid expression in the address"));
3160 if (! skip_past_char (&p
, ']'))
3162 set_syntax_error (_("']' expected"));
3166 if (skip_past_char (&p
, '!'))
3168 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3170 set_syntax_error (_("register offset not allowed in pre-indexed "
3171 "addressing mode"));
3175 operand
->addr
.writeback
= 1;
3177 else if (skip_past_comma (&p
))
3180 operand
->addr
.postind
= 1;
3181 operand
->addr
.writeback
= 1;
3183 if (operand
->addr
.preind
)
3185 set_syntax_error (_("cannot combine pre- and post-indexing"));
3189 if (accept_reg_post_index
3190 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3191 &isregzero
)) != PARSE_FAIL
)
3196 set_syntax_error (_("invalid 32-bit register offset"));
3199 operand
->addr
.offset
.regno
= reg
;
3200 operand
->addr
.offset
.is_reg
= 1;
3202 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3205 set_syntax_error (_("invalid expression in the address"));
3210 /* If at this point neither .preind nor .postind is set, we have a
3211 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3212 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3214 if (operand
->addr
.writeback
)
3217 set_syntax_error (_("missing offset in the pre-indexed address"));
3220 operand
->addr
.preind
= 1;
3221 inst
.reloc
.exp
.X_op
= O_constant
;
3222 inst
.reloc
.exp
.X_add_number
= 0;
3229 /* Return TRUE on success; otherwise return FALSE. */
3231 parse_address (char **str
, aarch64_opnd_info
*operand
,
3232 int accept_reg_post_index
)
3234 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3237 /* Return TRUE on success; otherwise return FALSE. */
3239 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3241 return parse_address_main (str
, operand
, 1, 0);
3244 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3245 Return TRUE on success; otherwise return FALSE. */
3247 parse_half (char **str
, int *internal_fixup_p
)
3253 skip_past_char (&p
, '#');
3255 gas_assert (internal_fixup_p
);
3256 *internal_fixup_p
= 0;
3260 struct reloc_table_entry
*entry
;
3262 /* Try to parse a relocation. Anything else is an error. */
3264 if (!(entry
= find_reloc_table_entry (&p
)))
3266 set_syntax_error (_("unknown relocation modifier"));
3270 if (entry
->movw_type
== 0)
3273 (_("this relocation modifier is not allowed on this instruction"));
3277 inst
.reloc
.type
= entry
->movw_type
;
3280 *internal_fixup_p
= 1;
3282 /* Avoid parsing a register as a general symbol. */
3284 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3288 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3295 /* Parse an operand for an ADRP instruction:
3297 Return TRUE on success; otherwise return FALSE. */
3300 parse_adrp (char **str
)
3307 struct reloc_table_entry
*entry
;
3309 /* Try to parse a relocation. Anything else is an error. */
3311 if (!(entry
= find_reloc_table_entry (&p
)))
3313 set_syntax_error (_("unknown relocation modifier"));
3317 if (entry
->adrp_type
== 0)
3320 (_("this relocation modifier is not allowed on this instruction"));
3324 inst
.reloc
.type
= entry
->adrp_type
;
3327 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3329 inst
.reloc
.pc_rel
= 1;
3331 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3338 /* Miscellaneous. */
3340 /* Parse an option for a preload instruction. Returns the encoding for the
3341 option, or PARSE_FAIL. */
3344 parse_pldop (char **str
)
3347 const struct aarch64_name_value_pair
*o
;
3350 while (ISALNUM (*q
))
3353 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3361 /* Parse an option for a barrier instruction. Returns the encoding for the
3362 option, or PARSE_FAIL. */
3365 parse_barrier (char **str
)
3368 const asm_barrier_opt
*o
;
3371 while (ISALPHA (*q
))
3374 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3382 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3383 Returns the encoding for the option, or PARSE_FAIL.
3385 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3386 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3389 parse_sys_reg (char **str
, struct hash_control
*sys_regs
, int imple_defined_p
)
3393 const aarch64_sys_reg
*o
;
3397 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3399 *p
++ = TOLOWER (*q
);
3401 /* Assert that BUF be large enough. */
3402 gas_assert (p
- buf
== q
- *str
);
3404 o
= hash_find (sys_regs
, buf
);
3407 if (!imple_defined_p
)
3411 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3412 unsigned int op0
, op1
, cn
, cm
, op2
;
3414 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3417 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3419 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3424 if (aarch64_sys_reg_deprecated_p (o
))
3425 as_warn (_("system register name '%s' is deprecated and may be "
3426 "removed in a future release"), buf
);
3434 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3435 for the option, or NULL. */
3437 static const aarch64_sys_ins_reg
*
3438 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3442 const aarch64_sys_ins_reg
*o
;
3445 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3447 *p
++ = TOLOWER (*q
);
3450 o
= hash_find (sys_ins_regs
, buf
);
3458 #define po_char_or_fail(chr) do { \
3459 if (! skip_past_char (&str, chr)) \
3463 #define po_reg_or_fail(regtype) do { \
3464 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3465 if (val == PARSE_FAIL) \
3467 set_default_error (); \
3472 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3473 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3474 &isreg32, &isregzero); \
3475 if (val == PARSE_FAIL) \
3477 set_default_error (); \
3480 info->reg.regno = val; \
3482 info->qualifier = AARCH64_OPND_QLF_W; \
3484 info->qualifier = AARCH64_OPND_QLF_X; \
3487 #define po_imm_nc_or_fail() do { \
3488 if (! parse_constant_immediate (&str, &val)) \
3492 #define po_imm_or_fail(min, max) do { \
3493 if (! parse_constant_immediate (&str, &val)) \
3495 if (val < min || val > max) \
3497 set_fatal_syntax_error (_("immediate value out of range "\
3498 #min " to "#max)); \
3503 #define po_misc_or_fail(expr) do { \
3508 /* encode the 12-bit imm field of Add/sub immediate */
3509 static inline uint32_t
3510 encode_addsub_imm (uint32_t imm
)
3515 /* encode the shift amount field of Add/sub immediate */
3516 static inline uint32_t
3517 encode_addsub_imm_shift_amount (uint32_t cnt
)
3523 /* encode the imm field of Adr instruction */
3524 static inline uint32_t
3525 encode_adr_imm (uint32_t imm
)
3527 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3528 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3531 /* encode the immediate field of Move wide immediate */
3532 static inline uint32_t
3533 encode_movw_imm (uint32_t imm
)
3538 /* encode the 26-bit offset of unconditional branch */
3539 static inline uint32_t
3540 encode_branch_ofs_26 (uint32_t ofs
)
3542 return ofs
& ((1 << 26) - 1);
3545 /* encode the 19-bit offset of conditional branch and compare & branch */
3546 static inline uint32_t
3547 encode_cond_branch_ofs_19 (uint32_t ofs
)
3549 return (ofs
& ((1 << 19) - 1)) << 5;
3552 /* encode the 19-bit offset of ld literal */
3553 static inline uint32_t
3554 encode_ld_lit_ofs_19 (uint32_t ofs
)
3556 return (ofs
& ((1 << 19) - 1)) << 5;
3559 /* Encode the 14-bit offset of test & branch. */
3560 static inline uint32_t
3561 encode_tst_branch_ofs_14 (uint32_t ofs
)
3563 return (ofs
& ((1 << 14) - 1)) << 5;
3566 /* Encode the 16-bit imm field of svc/hvc/smc. */
3567 static inline uint32_t
3568 encode_svc_imm (uint32_t imm
)
3573 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3574 static inline uint32_t
3575 reencode_addsub_switch_add_sub (uint32_t opcode
)
3577 return opcode
^ (1 << 30);
3580 static inline uint32_t
3581 reencode_movzn_to_movz (uint32_t opcode
)
3583 return opcode
| (1 << 30);
3586 static inline uint32_t
3587 reencode_movzn_to_movn (uint32_t opcode
)
3589 return opcode
& ~(1 << 30);
3592 /* Overall per-instruction processing. */
3594 /* We need to be able to fix up arbitrary expressions in some statements.
3595 This is so that we can handle symbols that are an arbitrary distance from
3596 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3597 which returns part of an address in a form which will be valid for
3598 a data instruction. We do this by pushing the expression into a symbol
3599 in the expr_section, and creating a fix for that. */
3602 fix_new_aarch64 (fragS
* frag
,
3604 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3614 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3618 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3625 /* Diagnostics on operands errors. */
3627 /* By default, output verbose error message.
3628 Disable the verbose error message by -mno-verbose-error. */
3629 static int verbose_error_p
= 1;
3631 #ifdef DEBUG_AARCH64
3632 /* N.B. this is only for the purpose of debugging. */
3633 const char* operand_mismatch_kind_names
[] =
3636 "AARCH64_OPDE_RECOVERABLE",
3637 "AARCH64_OPDE_SYNTAX_ERROR",
3638 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3639 "AARCH64_OPDE_INVALID_VARIANT",
3640 "AARCH64_OPDE_OUT_OF_RANGE",
3641 "AARCH64_OPDE_UNALIGNED",
3642 "AARCH64_OPDE_REG_LIST",
3643 "AARCH64_OPDE_OTHER_ERROR",
3645 #endif /* DEBUG_AARCH64 */
3647 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3649 When multiple errors of different kinds are found in the same assembly
3650 line, only the error of the highest severity will be picked up for
3651 issuing the diagnostics. */
3653 static inline bfd_boolean
3654 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3655 enum aarch64_operand_error_kind rhs
)
3657 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3658 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3659 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3660 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3661 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3662 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3663 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3664 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3668 /* Helper routine to get the mnemonic name from the assembly instruction
3669 line; should only be called for the diagnosis purpose, as there is
3670 string copy operation involved, which may affect the runtime
3671 performance if used in elsewhere. */
3674 get_mnemonic_name (const char *str
)
3676 static char mnemonic
[32];
3679 /* Get the first 15 bytes and assume that the full name is included. */
3680 strncpy (mnemonic
, str
, 31);
3681 mnemonic
[31] = '\0';
3683 /* Scan up to the end of the mnemonic, which must end in white space,
3684 '.', or end of string. */
3685 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3690 /* Append '...' to the truncated long name. */
3691 if (ptr
- mnemonic
== 31)
3692 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3698 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3700 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3701 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3704 /* Data strutures storing one user error in the assembly code related to
3707 struct operand_error_record
3709 const aarch64_opcode
*opcode
;
3710 aarch64_operand_error detail
;
3711 struct operand_error_record
*next
;
3714 typedef struct operand_error_record operand_error_record
;
3716 struct operand_errors
3718 operand_error_record
*head
;
3719 operand_error_record
*tail
;
3722 typedef struct operand_errors operand_errors
;
3724 /* Top-level data structure reporting user errors for the current line of
3726 The way md_assemble works is that all opcodes sharing the same mnemonic
3727 name are iterated to find a match to the assembly line. In this data
3728 structure, each of the such opcodes will have one operand_error_record
3729 allocated and inserted. In other words, excessive errors related with
3730 a single opcode are disregarded. */
3731 operand_errors operand_error_report
;
3733 /* Free record nodes. */
3734 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3736 /* Initialize the data structure that stores the operand mismatch
3737 information on assembling one line of the assembly code. */
3739 init_operand_error_report (void)
3741 if (operand_error_report
.head
!= NULL
)
3743 gas_assert (operand_error_report
.tail
!= NULL
);
3744 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3745 free_opnd_error_record_nodes
= operand_error_report
.head
;
3746 operand_error_report
.head
= NULL
;
3747 operand_error_report
.tail
= NULL
;
3750 gas_assert (operand_error_report
.tail
== NULL
);
3753 /* Return TRUE if some operand error has been recorded during the
3754 parsing of the current assembly line using the opcode *OPCODE;
3755 otherwise return FALSE. */
3756 static inline bfd_boolean
3757 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3759 operand_error_record
*record
= operand_error_report
.head
;
3760 return record
&& record
->opcode
== opcode
;
3763 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3764 OPCODE field is initialized with OPCODE.
3765 N.B. only one record for each opcode, i.e. the maximum of one error is
3766 recorded for each instruction template. */
3769 add_operand_error_record (const operand_error_record
* new_record
)
3771 const aarch64_opcode
*opcode
= new_record
->opcode
;
3772 operand_error_record
* record
= operand_error_report
.head
;
3774 /* The record may have been created for this opcode. If not, we need
3776 if (! opcode_has_operand_error_p (opcode
))
3778 /* Get one empty record. */
3779 if (free_opnd_error_record_nodes
== NULL
)
3781 record
= xmalloc (sizeof (operand_error_record
));
3787 record
= free_opnd_error_record_nodes
;
3788 free_opnd_error_record_nodes
= record
->next
;
3790 record
->opcode
= opcode
;
3791 /* Insert at the head. */
3792 record
->next
= operand_error_report
.head
;
3793 operand_error_report
.head
= record
;
3794 if (operand_error_report
.tail
== NULL
)
3795 operand_error_report
.tail
= record
;
3797 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3798 && record
->detail
.index
<= new_record
->detail
.index
3799 && operand_error_higher_severity_p (record
->detail
.kind
,
3800 new_record
->detail
.kind
))
3802 /* In the case of multiple errors found on operands related with a
3803 single opcode, only record the error of the leftmost operand and
3804 only if the error is of higher severity. */
3805 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3806 " the existing error %s on operand %d",
3807 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3808 new_record
->detail
.index
,
3809 operand_mismatch_kind_names
[record
->detail
.kind
],
3810 record
->detail
.index
);
3814 record
->detail
= new_record
->detail
;
3818 record_operand_error_info (const aarch64_opcode
*opcode
,
3819 aarch64_operand_error
*error_info
)
3821 operand_error_record record
;
3822 record
.opcode
= opcode
;
3823 record
.detail
= *error_info
;
3824 add_operand_error_record (&record
);
3827 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3828 error message *ERROR, for operand IDX (count from 0). */
3831 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3832 enum aarch64_operand_error_kind kind
,
3835 aarch64_operand_error info
;
3836 memset(&info
, 0, sizeof (info
));
3840 record_operand_error_info (opcode
, &info
);
3844 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3845 enum aarch64_operand_error_kind kind
,
3846 const char* error
, const int *extra_data
)
3848 aarch64_operand_error info
;
3852 info
.data
[0] = extra_data
[0];
3853 info
.data
[1] = extra_data
[1];
3854 info
.data
[2] = extra_data
[2];
3855 record_operand_error_info (opcode
, &info
);
3859 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
3860 const char* error
, int lower_bound
,
3863 int data
[3] = {lower_bound
, upper_bound
, 0};
3864 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
3868 /* Remove the operand error record for *OPCODE. */
3869 static void ATTRIBUTE_UNUSED
3870 remove_operand_error_record (const aarch64_opcode
*opcode
)
3872 if (opcode_has_operand_error_p (opcode
))
3874 operand_error_record
* record
= operand_error_report
.head
;
3875 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
3876 operand_error_report
.head
= record
->next
;
3877 record
->next
= free_opnd_error_record_nodes
;
3878 free_opnd_error_record_nodes
= record
;
3879 if (operand_error_report
.head
== NULL
)
3881 gas_assert (operand_error_report
.tail
== record
);
3882 operand_error_report
.tail
= NULL
;
3887 /* Given the instruction in *INSTR, return the index of the best matched
3888 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3890 Return -1 if there is no qualifier sequence; return the first match
3891 if there is multiple matches found. */
3894 find_best_match (const aarch64_inst
*instr
,
3895 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
3897 int i
, num_opnds
, max_num_matched
, idx
;
3899 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3902 DEBUG_TRACE ("no operand");
3906 max_num_matched
= 0;
3909 /* For each pattern. */
3910 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
3913 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
3915 /* Most opcodes has much fewer patterns in the list. */
3916 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
3918 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
3919 if (i
!= 0 && idx
== -1)
3920 /* If nothing has been matched, return the 1st sequence. */
3925 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
3926 if (*qualifiers
== instr
->operands
[j
].qualifier
)
3929 if (num_matched
> max_num_matched
)
3931 max_num_matched
= num_matched
;
3936 DEBUG_TRACE ("return with %d", idx
);
3940 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3941 corresponding operands in *INSTR. */
3944 assign_qualifier_sequence (aarch64_inst
*instr
,
3945 const aarch64_opnd_qualifier_t
*qualifiers
)
3948 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3949 gas_assert (num_opnds
);
3950 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
3951 instr
->operands
[i
].qualifier
= *qualifiers
;
3954 /* Print operands for the diagnosis purpose. */
3957 print_operands (char *buf
, const aarch64_opcode
*opcode
,
3958 const aarch64_opnd_info
*opnds
)
3962 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
3964 const size_t size
= 128;
3967 /* We regard the opcode operand info more, however we also look into
3968 the inst->operands to support the disassembling of the optional
3970 The two operand code should be the same in all cases, apart from
3971 when the operand can be optional. */
3972 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
3973 || opnds
[i
].type
== AARCH64_OPND_NIL
)
3976 /* Generate the operand string in STR. */
3977 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
3981 strcat (buf
, i
== 0 ? " " : ",");
3983 /* Append the operand string. */
3988 /* Send to stderr a string as information. */
3991 output_info (const char *format
, ...)
3997 as_where (&file
, &line
);
4001 fprintf (stderr
, "%s:%u: ", file
, line
);
4003 fprintf (stderr
, "%s: ", file
);
4005 fprintf (stderr
, _("Info: "));
4006 va_start (args
, format
);
4007 vfprintf (stderr
, format
, args
);
4009 (void) putc ('\n', stderr
);
4012 /* Output one operand error record. */
4015 output_operand_error_record (const operand_error_record
*record
, char *str
)
4017 const aarch64_operand_error
*detail
= &record
->detail
;
4018 int idx
= detail
->index
;
4019 const aarch64_opcode
*opcode
= record
->opcode
;
4020 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4021 : AARCH64_OPND_NIL
);
4023 switch (detail
->kind
)
4025 case AARCH64_OPDE_NIL
:
4029 case AARCH64_OPDE_SYNTAX_ERROR
:
4030 case AARCH64_OPDE_RECOVERABLE
:
4031 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4032 case AARCH64_OPDE_OTHER_ERROR
:
4033 /* Use the prepared error message if there is, otherwise use the
4034 operand description string to describe the error. */
4035 if (detail
->error
!= NULL
)
4038 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4040 as_bad (_("%s at operand %d -- `%s'"),
4041 detail
->error
, idx
+ 1, str
);
4045 gas_assert (idx
>= 0);
4046 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4047 aarch64_get_operand_desc (opd_code
), str
);
4051 case AARCH64_OPDE_INVALID_VARIANT
:
4052 as_bad (_("operand mismatch -- `%s'"), str
);
4053 if (verbose_error_p
)
4055 /* We will try to correct the erroneous instruction and also provide
4056 more information e.g. all other valid variants.
4058 The string representation of the corrected instruction and other
4059 valid variants are generated by
4061 1) obtaining the intermediate representation of the erroneous
4063 2) manipulating the IR, e.g. replacing the operand qualifier;
4064 3) printing out the instruction by calling the printer functions
4065 shared with the disassembler.
4067 The limitation of this method is that the exact input assembly
4068 line cannot be accurately reproduced in some cases, for example an
4069 optional operand present in the actual assembly line will be
4070 omitted in the output; likewise for the optional syntax rules,
4071 e.g. the # before the immediate. Another limitation is that the
4072 assembly symbols and relocation operations in the assembly line
4073 currently cannot be printed out in the error report. Last but not
4074 least, when there is other error(s) co-exist with this error, the
4075 'corrected' instruction may be still incorrect, e.g. given
4076 'ldnp h0,h1,[x0,#6]!'
4077 this diagnosis will provide the version:
4078 'ldnp s0,s1,[x0,#6]!'
4079 which is still not right. */
4080 size_t len
= strlen (get_mnemonic_name (str
));
4083 const size_t size
= 2048;
4085 aarch64_inst
*inst_base
= &inst
.base
;
4086 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4089 reset_aarch64_instruction (&inst
);
4090 inst_base
->opcode
= opcode
;
4092 /* Reset the error report so that there is no side effect on the
4093 following operand parsing. */
4094 init_operand_error_report ();
4097 result
= parse_operands (str
+ len
, opcode
)
4098 && programmer_friendly_fixup (&inst
);
4099 gas_assert (result
);
4100 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4102 gas_assert (!result
);
4104 /* Find the most matched qualifier sequence. */
4105 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4106 gas_assert (qlf_idx
> -1);
4108 /* Assign the qualifiers. */
4109 assign_qualifier_sequence (inst_base
,
4110 opcode
->qualifiers_list
[qlf_idx
]);
4112 /* Print the hint. */
4113 output_info (_(" did you mean this?"));
4114 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4115 print_operands (buf
, opcode
, inst_base
->operands
);
4116 output_info (_(" %s"), buf
);
4118 /* Print out other variant(s) if there is any. */
4120 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4121 output_info (_(" other valid variant(s):"));
4123 /* For each pattern. */
4124 qualifiers_list
= opcode
->qualifiers_list
;
4125 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4127 /* Most opcodes has much fewer patterns in the list.
4128 First NIL qualifier indicates the end in the list. */
4129 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4134 /* Mnemonics name. */
4135 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4137 /* Assign the qualifiers. */
4138 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4140 /* Print instruction. */
4141 print_operands (buf
, opcode
, inst_base
->operands
);
4143 output_info (_(" %s"), buf
);
4149 case AARCH64_OPDE_OUT_OF_RANGE
:
4150 if (detail
->data
[0] != detail
->data
[1])
4151 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4152 detail
->error
? detail
->error
: _("immediate value"),
4153 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4155 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4156 detail
->error
? detail
->error
: _("immediate value"),
4157 detail
->data
[0], idx
+ 1, str
);
4160 case AARCH64_OPDE_REG_LIST
:
4161 if (detail
->data
[0] == 1)
4162 as_bad (_("invalid number of registers in the list; "
4163 "only 1 register is expected at operand %d -- `%s'"),
4166 as_bad (_("invalid number of registers in the list; "
4167 "%d registers are expected at operand %d -- `%s'"),
4168 detail
->data
[0], idx
+ 1, str
);
4171 case AARCH64_OPDE_UNALIGNED
:
4172 as_bad (_("immediate value should be a multiple of "
4173 "%d at operand %d -- `%s'"),
4174 detail
->data
[0], idx
+ 1, str
);
4183 /* Process and output the error message about the operand mismatching.
4185 When this function is called, the operand error information had
4186 been collected for an assembly line and there will be multiple
4187 errors in the case of mulitple instruction templates; output the
4188 error message that most closely describes the problem. */
4191 output_operand_error_report (char *str
)
4193 int largest_error_pos
;
4194 const char *msg
= NULL
;
4195 enum aarch64_operand_error_kind kind
;
4196 operand_error_record
*curr
;
4197 operand_error_record
*head
= operand_error_report
.head
;
4198 operand_error_record
*record
= NULL
;
4200 /* No error to report. */
4204 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4206 /* Only one error. */
4207 if (head
== operand_error_report
.tail
)
4209 DEBUG_TRACE ("single opcode entry with error kind: %s",
4210 operand_mismatch_kind_names
[head
->detail
.kind
]);
4211 output_operand_error_record (head
, str
);
4215 /* Find the error kind of the highest severity. */
4216 DEBUG_TRACE ("multiple opcode entres with error kind");
4217 kind
= AARCH64_OPDE_NIL
;
4218 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4220 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4221 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4222 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4223 kind
= curr
->detail
.kind
;
4225 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4227 /* Pick up one of errors of KIND to report. */
4228 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4229 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4231 if (curr
->detail
.kind
!= kind
)
4233 /* If there are multiple errors, pick up the one with the highest
4234 mismatching operand index. In the case of multiple errors with
4235 the equally highest operand index, pick up the first one or the
4236 first one with non-NULL error message. */
4237 if (curr
->detail
.index
> largest_error_pos
4238 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4239 && curr
->detail
.error
!= NULL
))
4241 largest_error_pos
= curr
->detail
.index
;
4243 msg
= record
->detail
.error
;
4247 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4248 DEBUG_TRACE ("Pick up error kind %s to report",
4249 operand_mismatch_kind_names
[record
->detail
.kind
]);
4252 output_operand_error_record (record
, str
);
4255 /* Write an AARCH64 instruction to buf - always little-endian. */
4257 put_aarch64_insn (char *buf
, uint32_t insn
)
4259 unsigned char *where
= (unsigned char *) buf
;
4261 where
[1] = insn
>> 8;
4262 where
[2] = insn
>> 16;
4263 where
[3] = insn
>> 24;
4267 get_aarch64_insn (char *buf
)
4269 unsigned char *where
= (unsigned char *) buf
;
4271 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4276 output_inst (struct aarch64_inst
*new_inst
)
4280 to
= frag_more (INSN_SIZE
);
4282 frag_now
->tc_frag_data
.recorded
= 1;
4284 put_aarch64_insn (to
, inst
.base
.value
);
4286 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4288 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4289 INSN_SIZE
, &inst
.reloc
.exp
,
4292 DEBUG_TRACE ("Prepared relocation fix up");
4293 /* Don't check the addend value against the instruction size,
4294 that's the job of our code in md_apply_fix(). */
4295 fixp
->fx_no_overflow
= 1;
4296 if (new_inst
!= NULL
)
4297 fixp
->tc_fix_data
.inst
= new_inst
;
4298 if (aarch64_gas_internal_fixup_p ())
4300 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4301 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4302 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4306 dwarf2_emit_insn (INSN_SIZE
);
4309 /* Link together opcodes of the same name. */
4313 aarch64_opcode
*opcode
;
4314 struct templates
*next
;
4317 typedef struct templates templates
;
4320 lookup_mnemonic (const char *start
, int len
)
4322 templates
*templ
= NULL
;
4324 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4328 /* Subroutine of md_assemble, responsible for looking up the primary
4329 opcode from the mnemonic the user wrote. STR points to the
4330 beginning of the mnemonic. */
4333 opcode_lookup (char **str
)
4336 const aarch64_cond
*cond
;
4340 /* Scan up to the end of the mnemonic, which must end in white space,
4341 '.', or end of string. */
4342 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4349 inst
.cond
= COND_ALWAYS
;
4351 /* Handle a possible condition. */
4354 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4357 inst
.cond
= cond
->value
;
4371 if (inst
.cond
== COND_ALWAYS
)
4373 /* Look for unaffixed mnemonic. */
4374 return lookup_mnemonic (base
, len
);
4378 /* append ".c" to mnemonic if conditional */
4379 memcpy (condname
, base
, len
);
4380 memcpy (condname
+ len
, ".c", 2);
4383 return lookup_mnemonic (base
, len
);
4389 /* Internal helper routine converting a vector neon_type_el structure
4390 *VECTYPE to a corresponding operand qualifier. */
4392 static inline aarch64_opnd_qualifier_t
4393 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4395 /* Element size in bytes indexed by neon_el_type. */
4396 const unsigned char ele_size
[5]
4399 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4400 goto vectype_conversion_fail
;
4402 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4404 if (vectype
->defined
& NTA_HASINDEX
)
4405 /* Vector element register. */
4406 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4409 /* Vector register. */
4410 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4412 if (reg_size
!= 16 && reg_size
!= 8)
4413 goto vectype_conversion_fail
;
4414 /* The conversion is calculated based on the relation of the order of
4415 qualifiers to the vector element size and vector register size. */
4416 offset
= (vectype
->type
== NT_q
)
4417 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4418 gas_assert (offset
<= 8);
4419 return AARCH64_OPND_QLF_V_8B
+ offset
;
4422 vectype_conversion_fail
:
4423 first_error (_("bad vector arrangement type"));
4424 return AARCH64_OPND_QLF_NIL
;
4427 /* Process an optional operand that is found omitted from the assembly line.
4428 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4429 instruction's opcode entry while IDX is the index of this omitted operand.
4433 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4434 int idx
, aarch64_opnd_info
*operand
)
4436 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4437 gas_assert (optional_operand_p (opcode
, idx
));
4438 gas_assert (!operand
->present
);
4442 case AARCH64_OPND_Rd
:
4443 case AARCH64_OPND_Rn
:
4444 case AARCH64_OPND_Rm
:
4445 case AARCH64_OPND_Rt
:
4446 case AARCH64_OPND_Rt2
:
4447 case AARCH64_OPND_Rs
:
4448 case AARCH64_OPND_Ra
:
4449 case AARCH64_OPND_Rt_SYS
:
4450 case AARCH64_OPND_Rd_SP
:
4451 case AARCH64_OPND_Rn_SP
:
4452 case AARCH64_OPND_Fd
:
4453 case AARCH64_OPND_Fn
:
4454 case AARCH64_OPND_Fm
:
4455 case AARCH64_OPND_Fa
:
4456 case AARCH64_OPND_Ft
:
4457 case AARCH64_OPND_Ft2
:
4458 case AARCH64_OPND_Sd
:
4459 case AARCH64_OPND_Sn
:
4460 case AARCH64_OPND_Sm
:
4461 case AARCH64_OPND_Vd
:
4462 case AARCH64_OPND_Vn
:
4463 case AARCH64_OPND_Vm
:
4464 case AARCH64_OPND_VdD1
:
4465 case AARCH64_OPND_VnD1
:
4466 operand
->reg
.regno
= default_value
;
4469 case AARCH64_OPND_Ed
:
4470 case AARCH64_OPND_En
:
4471 case AARCH64_OPND_Em
:
4472 operand
->reglane
.regno
= default_value
;
4475 case AARCH64_OPND_IDX
:
4476 case AARCH64_OPND_BIT_NUM
:
4477 case AARCH64_OPND_IMMR
:
4478 case AARCH64_OPND_IMMS
:
4479 case AARCH64_OPND_SHLL_IMM
:
4480 case AARCH64_OPND_IMM_VLSL
:
4481 case AARCH64_OPND_IMM_VLSR
:
4482 case AARCH64_OPND_CCMP_IMM
:
4483 case AARCH64_OPND_FBITS
:
4484 case AARCH64_OPND_UIMM4
:
4485 case AARCH64_OPND_UIMM3_OP1
:
4486 case AARCH64_OPND_UIMM3_OP2
:
4487 case AARCH64_OPND_IMM
:
4488 case AARCH64_OPND_WIDTH
:
4489 case AARCH64_OPND_UIMM7
:
4490 case AARCH64_OPND_NZCV
:
4491 operand
->imm
.value
= default_value
;
4494 case AARCH64_OPND_EXCEPTION
:
4495 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4498 case AARCH64_OPND_BARRIER_ISB
:
4499 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4506 /* Process the relocation type for move wide instructions.
4507 Return TRUE on success; otherwise return FALSE. */
4510 process_movw_reloc_info (void)
4515 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4517 if (inst
.base
.opcode
->op
== OP_MOVK
)
4518 switch (inst
.reloc
.type
)
4520 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4521 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4522 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4523 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4524 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4525 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4527 (_("the specified relocation type is not allowed for MOVK"));
4533 switch (inst
.reloc
.type
)
4535 case BFD_RELOC_AARCH64_MOVW_G0
:
4536 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4537 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4538 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4539 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4542 case BFD_RELOC_AARCH64_MOVW_G1
:
4543 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4544 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4545 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4546 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4549 case BFD_RELOC_AARCH64_MOVW_G2
:
4550 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4551 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4552 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4555 set_fatal_syntax_error
4556 (_("the specified relocation type is not allowed for 32-bit "
4562 case BFD_RELOC_AARCH64_MOVW_G3
:
4565 set_fatal_syntax_error
4566 (_("the specified relocation type is not allowed for 32-bit "
4573 /* More cases should be added when more MOVW-related relocation types
4574 are supported in GAS. */
4575 gas_assert (aarch64_gas_internal_fixup_p ());
4576 /* The shift amount should have already been set by the parser. */
4579 inst
.base
.operands
[1].shifter
.amount
= shift
;
4583 /* A primitive log caculator. */
4585 static inline unsigned int
4586 get_logsz (unsigned int size
)
4588 const unsigned char ls
[16] =
4589 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4595 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4596 return ls
[size
- 1];
4599 /* Determine and return the real reloc type code for an instruction
4600 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4602 static inline bfd_reloc_code_real_type
4603 ldst_lo12_determine_real_reloc_type (void)
4606 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4607 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4609 const bfd_reloc_code_real_type reloc_ldst_lo12
[5] = {
4610 BFD_RELOC_AARCH64_LDST8_LO12
, BFD_RELOC_AARCH64_LDST16_LO12
,
4611 BFD_RELOC_AARCH64_LDST32_LO12
, BFD_RELOC_AARCH64_LDST64_LO12
,
4612 BFD_RELOC_AARCH64_LDST128_LO12
4615 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
);
4616 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4618 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4620 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4622 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4624 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4625 gas_assert (logsz
>= 0 && logsz
<= 4);
4627 return reloc_ldst_lo12
[logsz
];
4630 /* Check whether a register list REGINFO is valid. The registers must be
4631 numbered in increasing order (modulo 32), in increments of one or two.
4633 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4636 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4639 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4641 uint32_t i
, nb_regs
, prev_regno
, incr
;
4643 nb_regs
= 1 + (reginfo
& 0x3);
4645 prev_regno
= reginfo
& 0x1f;
4646 incr
= accept_alternate
? 2 : 1;
4648 for (i
= 1; i
< nb_regs
; ++i
)
4650 uint32_t curr_regno
;
4652 curr_regno
= reginfo
& 0x1f;
4653 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4655 prev_regno
= curr_regno
;
4661 /* Generic instruction operand parser. This does no encoding and no
4662 semantic validation; it merely squirrels values away in the inst
4663 structure. Returns TRUE or FALSE depending on whether the
4664 specified grammar matched. */
4667 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4670 char *backtrack_pos
= 0;
4671 const enum aarch64_opnd
*operands
= opcode
->operands
;
4674 skip_whitespace (str
);
4676 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4679 int isreg32
, isregzero
;
4680 int comma_skipped_p
= 0;
4681 aarch64_reg_type rtype
;
4682 struct neon_type_el vectype
;
4683 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4685 DEBUG_TRACE ("parse operand %d", i
);
4687 /* Assign the operand code. */
4688 info
->type
= operands
[i
];
4690 if (optional_operand_p (opcode
, i
))
4692 /* Remember where we are in case we need to backtrack. */
4693 gas_assert (!backtrack_pos
);
4694 backtrack_pos
= str
;
4697 /* Expect comma between operands; the backtrack mechanizm will take
4698 care of cases of omitted optional operand. */
4699 if (i
> 0 && ! skip_past_char (&str
, ','))
4701 set_syntax_error (_("comma expected between operands"));
4705 comma_skipped_p
= 1;
4707 switch (operands
[i
])
4709 case AARCH64_OPND_Rd
:
4710 case AARCH64_OPND_Rn
:
4711 case AARCH64_OPND_Rm
:
4712 case AARCH64_OPND_Rt
:
4713 case AARCH64_OPND_Rt2
:
4714 case AARCH64_OPND_Rs
:
4715 case AARCH64_OPND_Ra
:
4716 case AARCH64_OPND_Rt_SYS
:
4717 case AARCH64_OPND_PAIRREG
:
4718 po_int_reg_or_fail (1, 0);
4721 case AARCH64_OPND_Rd_SP
:
4722 case AARCH64_OPND_Rn_SP
:
4723 po_int_reg_or_fail (0, 1);
4726 case AARCH64_OPND_Rm_EXT
:
4727 case AARCH64_OPND_Rm_SFT
:
4728 po_misc_or_fail (parse_shifter_operand
4729 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4731 : SHIFTED_LOGIC_IMM
)));
4732 if (!info
->shifter
.operator_present
)
4734 /* Default to LSL if not present. Libopcodes prefers shifter
4735 kind to be explicit. */
4736 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4737 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4738 /* For Rm_EXT, libopcodes will carry out further check on whether
4739 or not stack pointer is used in the instruction (Recall that
4740 "the extend operator is not optional unless at least one of
4741 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4745 case AARCH64_OPND_Fd
:
4746 case AARCH64_OPND_Fn
:
4747 case AARCH64_OPND_Fm
:
4748 case AARCH64_OPND_Fa
:
4749 case AARCH64_OPND_Ft
:
4750 case AARCH64_OPND_Ft2
:
4751 case AARCH64_OPND_Sd
:
4752 case AARCH64_OPND_Sn
:
4753 case AARCH64_OPND_Sm
:
4754 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4755 if (val
== PARSE_FAIL
)
4757 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4760 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4762 info
->reg
.regno
= val
;
4763 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4766 case AARCH64_OPND_Vd
:
4767 case AARCH64_OPND_Vn
:
4768 case AARCH64_OPND_Vm
:
4769 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4770 if (val
== PARSE_FAIL
)
4772 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4775 if (vectype
.defined
& NTA_HASINDEX
)
4778 info
->reg
.regno
= val
;
4779 info
->qualifier
= vectype_to_qualifier (&vectype
);
4780 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4784 case AARCH64_OPND_VdD1
:
4785 case AARCH64_OPND_VnD1
:
4786 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4787 if (val
== PARSE_FAIL
)
4789 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4792 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4794 set_fatal_syntax_error
4795 (_("the top half of a 128-bit FP/SIMD register is expected"));
4798 info
->reg
.regno
= val
;
4799 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4800 here; it is correct for the purpose of encoding/decoding since
4801 only the register number is explicitly encoded in the related
4802 instructions, although this appears a bit hacky. */
4803 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4806 case AARCH64_OPND_Ed
:
4807 case AARCH64_OPND_En
:
4808 case AARCH64_OPND_Em
:
4809 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4810 if (val
== PARSE_FAIL
)
4812 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4815 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
4818 info
->reglane
.regno
= val
;
4819 info
->reglane
.index
= vectype
.index
;
4820 info
->qualifier
= vectype_to_qualifier (&vectype
);
4821 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4825 case AARCH64_OPND_LVn
:
4826 case AARCH64_OPND_LVt
:
4827 case AARCH64_OPND_LVt_AL
:
4828 case AARCH64_OPND_LEt
:
4829 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
4831 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
4833 set_fatal_syntax_error (_("invalid register list"));
4836 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
4837 info
->reglist
.num_regs
= (val
& 0x3) + 1;
4838 if (operands
[i
] == AARCH64_OPND_LEt
)
4840 if (!(vectype
.defined
& NTA_HASINDEX
))
4842 info
->reglist
.has_index
= 1;
4843 info
->reglist
.index
= vectype
.index
;
4845 else if (!(vectype
.defined
& NTA_HASTYPE
))
4847 info
->qualifier
= vectype_to_qualifier (&vectype
);
4848 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4852 case AARCH64_OPND_Cn
:
4853 case AARCH64_OPND_Cm
:
4854 po_reg_or_fail (REG_TYPE_CN
);
4857 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
4860 inst
.base
.operands
[i
].reg
.regno
= val
;
4863 case AARCH64_OPND_SHLL_IMM
:
4864 case AARCH64_OPND_IMM_VLSR
:
4865 po_imm_or_fail (1, 64);
4866 info
->imm
.value
= val
;
4869 case AARCH64_OPND_CCMP_IMM
:
4870 case AARCH64_OPND_FBITS
:
4871 case AARCH64_OPND_UIMM4
:
4872 case AARCH64_OPND_UIMM3_OP1
:
4873 case AARCH64_OPND_UIMM3_OP2
:
4874 case AARCH64_OPND_IMM_VLSL
:
4875 case AARCH64_OPND_IMM
:
4876 case AARCH64_OPND_WIDTH
:
4877 po_imm_nc_or_fail ();
4878 info
->imm
.value
= val
;
4881 case AARCH64_OPND_UIMM7
:
4882 po_imm_or_fail (0, 127);
4883 info
->imm
.value
= val
;
4886 case AARCH64_OPND_IDX
:
4887 case AARCH64_OPND_BIT_NUM
:
4888 case AARCH64_OPND_IMMR
:
4889 case AARCH64_OPND_IMMS
:
4890 po_imm_or_fail (0, 63);
4891 info
->imm
.value
= val
;
4894 case AARCH64_OPND_IMM0
:
4895 po_imm_nc_or_fail ();
4898 set_fatal_syntax_error (_("immediate zero expected"));
4901 info
->imm
.value
= 0;
4904 case AARCH64_OPND_FPIMM0
:
4907 bfd_boolean res1
= FALSE
, res2
= FALSE
;
4908 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4909 it is probably not worth the effort to support it. */
4910 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
4911 && !(res2
= parse_constant_immediate (&str
, &val
)))
4913 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
4915 info
->imm
.value
= 0;
4916 info
->imm
.is_fp
= 1;
4919 set_fatal_syntax_error (_("immediate zero expected"));
4923 case AARCH64_OPND_IMM_MOV
:
4926 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
4927 reg_name_p (str
, REG_TYPE_VN
))
4930 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
4932 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4933 later. fix_mov_imm_insn will try to determine a machine
4934 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4935 message if the immediate cannot be moved by a single
4937 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
4938 inst
.base
.operands
[i
].skip
= 1;
4942 case AARCH64_OPND_SIMD_IMM
:
4943 case AARCH64_OPND_SIMD_IMM_SFT
:
4944 if (! parse_big_immediate (&str
, &val
))
4946 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4948 /* need_libopcodes_p */ 1,
4951 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4952 shift, we don't check it here; we leave the checking to
4953 the libopcodes (operand_general_constraint_met_p). By
4954 doing this, we achieve better diagnostics. */
4955 if (skip_past_comma (&str
)
4956 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
4958 if (!info
->shifter
.operator_present
4959 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
4961 /* Default to LSL if not present. Libopcodes prefers shifter
4962 kind to be explicit. */
4963 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4964 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4968 case AARCH64_OPND_FPIMM
:
4969 case AARCH64_OPND_SIMD_FPIMM
:
4973 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
4975 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
4979 set_fatal_syntax_error (_("invalid floating-point constant"));
4982 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
4983 inst
.base
.operands
[i
].imm
.is_fp
= 1;
4987 case AARCH64_OPND_LIMM
:
4988 po_misc_or_fail (parse_shifter_operand (&str
, info
,
4989 SHIFTED_LOGIC_IMM
));
4990 if (info
->shifter
.operator_present
)
4992 set_fatal_syntax_error
4993 (_("shift not allowed for bitmask immediate"));
4996 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4998 /* need_libopcodes_p */ 1,
5002 case AARCH64_OPND_AIMM
:
5003 if (opcode
->op
== OP_ADD
)
5004 /* ADD may have relocation types. */
5005 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5006 SHIFTED_ARITH_IMM
));
5008 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5009 SHIFTED_ARITH_IMM
));
5010 switch (inst
.reloc
.type
)
5012 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5013 info
->shifter
.amount
= 12;
5015 case BFD_RELOC_UNUSED
:
5016 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5017 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5018 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5019 inst
.reloc
.pc_rel
= 0;
5024 info
->imm
.value
= 0;
5025 if (!info
->shifter
.operator_present
)
5027 /* Default to LSL if not present. Libopcodes prefers shifter
5028 kind to be explicit. */
5029 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5030 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5034 case AARCH64_OPND_HALF
:
5036 /* #<imm16> or relocation. */
5037 int internal_fixup_p
;
5038 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5039 if (internal_fixup_p
)
5040 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5041 skip_whitespace (str
);
5042 if (skip_past_comma (&str
))
5044 /* {, LSL #<shift>} */
5045 if (! aarch64_gas_internal_fixup_p ())
5047 set_fatal_syntax_error (_("can't mix relocation modifier "
5048 "with explicit shift"));
5051 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5054 inst
.base
.operands
[i
].shifter
.amount
= 0;
5055 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5056 inst
.base
.operands
[i
].imm
.value
= 0;
5057 if (! process_movw_reloc_info ())
5062 case AARCH64_OPND_EXCEPTION
:
5063 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5064 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5066 /* need_libopcodes_p */ 0,
5070 case AARCH64_OPND_NZCV
:
5072 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5076 info
->imm
.value
= nzcv
->value
;
5079 po_imm_or_fail (0, 15);
5080 info
->imm
.value
= val
;
5084 case AARCH64_OPND_COND
:
5085 case AARCH64_OPND_COND1
:
5086 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5088 if (info
->cond
== NULL
)
5090 set_syntax_error (_("invalid condition"));
5093 else if (operands
[i
] == AARCH64_OPND_COND1
5094 && (info
->cond
->value
& 0xe) == 0xe)
5096 /* Not allow AL or NV. */
5097 set_default_error ();
5102 case AARCH64_OPND_ADDR_ADRP
:
5103 po_misc_or_fail (parse_adrp (&str
));
5104 /* Clear the value as operand needs to be relocated. */
5105 info
->imm
.value
= 0;
5108 case AARCH64_OPND_ADDR_PCREL14
:
5109 case AARCH64_OPND_ADDR_PCREL19
:
5110 case AARCH64_OPND_ADDR_PCREL21
:
5111 case AARCH64_OPND_ADDR_PCREL26
:
5112 po_misc_or_fail (parse_address_reloc (&str
, info
));
5113 if (!info
->addr
.pcrel
)
5115 set_syntax_error (_("invalid pc-relative address"));
5118 if (inst
.gen_lit_pool
5119 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5121 /* Only permit "=value" in the literal load instructions.
5122 The literal will be generated by programmer_friendly_fixup. */
5123 set_syntax_error (_("invalid use of \"=immediate\""));
5126 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5128 set_syntax_error (_("unrecognized relocation suffix"));
5131 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5133 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5134 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5138 info
->imm
.value
= 0;
5139 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5140 switch (opcode
->iclass
)
5144 /* e.g. CBZ or B.COND */
5145 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5146 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5150 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5151 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5155 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5157 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5158 : BFD_RELOC_AARCH64_JUMP26
;
5161 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5162 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5165 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5166 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5172 inst
.reloc
.pc_rel
= 1;
5176 case AARCH64_OPND_ADDR_SIMPLE
:
5177 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5178 /* [<Xn|SP>{, #<simm>}] */
5179 po_char_or_fail ('[');
5180 po_reg_or_fail (REG_TYPE_R64_SP
);
5181 /* Accept optional ", #0". */
5182 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5183 && skip_past_char (&str
, ','))
5185 skip_past_char (&str
, '#');
5186 if (! skip_past_char (&str
, '0'))
5188 set_fatal_syntax_error
5189 (_("the optional immediate offset can only be 0"));
5193 po_char_or_fail (']');
5194 info
->addr
.base_regno
= val
;
5197 case AARCH64_OPND_ADDR_REGOFF
:
5198 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5199 po_misc_or_fail (parse_address (&str
, info
, 0));
5200 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5201 || !info
->addr
.preind
|| info
->addr
.postind
5202 || info
->addr
.writeback
)
5204 set_syntax_error (_("invalid addressing mode"));
5207 if (!info
->shifter
.operator_present
)
5209 /* Default to LSL if not present. Libopcodes prefers shifter
5210 kind to be explicit. */
5211 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5212 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5214 /* Qualifier to be deduced by libopcodes. */
5217 case AARCH64_OPND_ADDR_SIMM7
:
5218 po_misc_or_fail (parse_address (&str
, info
, 0));
5219 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5220 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5222 set_syntax_error (_("invalid addressing mode"));
5225 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5227 /* need_libopcodes_p */ 1,
5231 case AARCH64_OPND_ADDR_SIMM9
:
5232 case AARCH64_OPND_ADDR_SIMM9_2
:
5233 po_misc_or_fail (parse_address_reloc (&str
, info
));
5234 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5235 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5236 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5237 && info
->addr
.writeback
))
5239 set_syntax_error (_("invalid addressing mode"));
5242 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5244 set_syntax_error (_("relocation not allowed"));
5247 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5249 /* need_libopcodes_p */ 1,
5253 case AARCH64_OPND_ADDR_UIMM12
:
5254 po_misc_or_fail (parse_address_reloc (&str
, info
));
5255 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5256 || !info
->addr
.preind
|| info
->addr
.writeback
)
5258 set_syntax_error (_("invalid addressing mode"));
5261 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5262 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5263 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
)
5264 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5265 /* Leave qualifier to be determined by libopcodes. */
5268 case AARCH64_OPND_SIMD_ADDR_POST
:
5269 /* [<Xn|SP>], <Xm|#<amount>> */
5270 po_misc_or_fail (parse_address (&str
, info
, 1));
5271 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5273 set_syntax_error (_("invalid addressing mode"));
5276 if (!info
->addr
.offset
.is_reg
)
5278 if (inst
.reloc
.exp
.X_op
== O_constant
)
5279 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5282 set_fatal_syntax_error
5283 (_("writeback value should be an immediate constant"));
5290 case AARCH64_OPND_SYSREG
:
5291 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1))
5294 set_syntax_error (_("unknown or missing system register name"));
5297 inst
.base
.operands
[i
].sysreg
= val
;
5300 case AARCH64_OPND_PSTATEFIELD
:
5301 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0))
5304 set_syntax_error (_("unknown or missing PSTATE field name"));
5307 inst
.base
.operands
[i
].pstatefield
= val
;
5310 case AARCH64_OPND_SYSREG_IC
:
5311 inst
.base
.operands
[i
].sysins_op
=
5312 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5314 case AARCH64_OPND_SYSREG_DC
:
5315 inst
.base
.operands
[i
].sysins_op
=
5316 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5318 case AARCH64_OPND_SYSREG_AT
:
5319 inst
.base
.operands
[i
].sysins_op
=
5320 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5322 case AARCH64_OPND_SYSREG_TLBI
:
5323 inst
.base
.operands
[i
].sysins_op
=
5324 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5326 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5328 set_fatal_syntax_error ( _("unknown or missing operation name"));
5333 case AARCH64_OPND_BARRIER
:
5334 case AARCH64_OPND_BARRIER_ISB
:
5335 val
= parse_barrier (&str
);
5336 if (val
!= PARSE_FAIL
5337 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5339 /* ISB only accepts options name 'sy'. */
5341 (_("the specified option is not accepted in ISB"));
5342 /* Turn off backtrack as this optional operand is present. */
5346 /* This is an extension to accept a 0..15 immediate. */
5347 if (val
== PARSE_FAIL
)
5348 po_imm_or_fail (0, 15);
5349 info
->barrier
= aarch64_barrier_options
+ val
;
5352 case AARCH64_OPND_PRFOP
:
5353 val
= parse_pldop (&str
);
5354 /* This is an extension to accept a 0..31 immediate. */
5355 if (val
== PARSE_FAIL
)
5356 po_imm_or_fail (0, 31);
5357 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5361 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5364 /* If we get here, this operand was successfully parsed. */
5365 inst
.base
.operands
[i
].present
= 1;
5369 /* The parse routine should already have set the error, but in case
5370 not, set a default one here. */
5372 set_default_error ();
5374 if (! backtrack_pos
)
5375 goto parse_operands_return
;
5378 /* We reach here because this operand is marked as optional, and
5379 either no operand was supplied or the operand was supplied but it
5380 was syntactically incorrect. In the latter case we report an
5381 error. In the former case we perform a few more checks before
5382 dropping through to the code to insert the default operand. */
5384 char *tmp
= backtrack_pos
;
5385 char endchar
= END_OF_INSN
;
5387 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5389 skip_past_char (&tmp
, ',');
5391 if (*tmp
!= endchar
)
5392 /* The user has supplied an operand in the wrong format. */
5393 goto parse_operands_return
;
5395 /* Make sure there is not a comma before the optional operand.
5396 For example the fifth operand of 'sys' is optional:
5398 sys #0,c0,c0,#0, <--- wrong
5399 sys #0,c0,c0,#0 <--- correct. */
5400 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5402 set_fatal_syntax_error
5403 (_("unexpected comma before the omitted optional operand"));
5404 goto parse_operands_return
;
5408 /* Reaching here means we are dealing with an optional operand that is
5409 omitted from the assembly line. */
5410 gas_assert (optional_operand_p (opcode
, i
));
5412 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5414 /* Try again, skipping the optional operand at backtrack_pos. */
5415 str
= backtrack_pos
;
5418 /* Clear any error record after the omitted optional operand has been
5419 successfully handled. */
5423 /* Check if we have parsed all the operands. */
5424 if (*str
!= '\0' && ! error_p ())
5426 /* Set I to the index of the last present operand; this is
5427 for the purpose of diagnostics. */
5428 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5430 set_fatal_syntax_error
5431 (_("unexpected characters following instruction"));
5434 parse_operands_return
:
5438 DEBUG_TRACE ("parsing FAIL: %s - %s",
5439 operand_mismatch_kind_names
[get_error_kind ()],
5440 get_error_message ());
5441 /* Record the operand error properly; this is useful when there
5442 are multiple instruction templates for a mnemonic name, so that
5443 later on, we can select the error that most closely describes
5445 record_operand_error (opcode
, i
, get_error_kind (),
5446 get_error_message ());
5451 DEBUG_TRACE ("parsing SUCCESS");
5456 /* It does some fix-up to provide some programmer friendly feature while
5457 keeping the libopcodes happy, i.e. libopcodes only accepts
5458 the preferred architectural syntax.
5459 Return FALSE if there is any failure; otherwise return TRUE. */
5462 programmer_friendly_fixup (aarch64_instruction
*instr
)
5464 aarch64_inst
*base
= &instr
->base
;
5465 const aarch64_opcode
*opcode
= base
->opcode
;
5466 enum aarch64_op op
= opcode
->op
;
5467 aarch64_opnd_info
*operands
= base
->operands
;
5469 DEBUG_TRACE ("enter");
5471 switch (opcode
->iclass
)
5474 /* TBNZ Xn|Wn, #uimm6, label
5475 Test and Branch Not Zero: conditionally jumps to label if bit number
5476 uimm6 in register Xn is not zero. The bit number implies the width of
5477 the register, which may be written and should be disassembled as Wn if
5478 uimm is less than 32. */
5479 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5481 if (operands
[1].imm
.value
>= 32)
5483 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5487 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5491 /* LDR Wt, label | =value
5492 As a convenience assemblers will typically permit the notation
5493 "=value" in conjunction with the pc-relative literal load instructions
5494 to automatically place an immediate value or symbolic address in a
5495 nearby literal pool and generate a hidden label which references it.
5496 ISREG has been set to 0 in the case of =value. */
5497 if (instr
->gen_lit_pool
5498 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5500 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5501 if (op
== OP_LDRSW_LIT
)
5503 if (instr
->reloc
.exp
.X_op
!= O_constant
5504 && instr
->reloc
.exp
.X_op
!= O_big
5505 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5507 record_operand_error (opcode
, 1,
5508 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5509 _("constant expression expected"));
5512 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5514 record_operand_error (opcode
, 1,
5515 AARCH64_OPDE_OTHER_ERROR
,
5516 _("literal pool insertion failed"));
5524 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5525 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5526 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5527 A programmer-friendly assembler should accept a destination Xd in
5528 place of Wd, however that is not the preferred form for disassembly.
5530 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5531 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5532 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5533 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5538 /* In the 64-bit form, the final register operand is written as Wm
5539 for all but the (possibly omitted) UXTX/LSL and SXTX
5541 As a programmer-friendly assembler, we accept e.g.
5542 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5543 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5544 int idx
= aarch64_operand_index (opcode
->operands
,
5545 AARCH64_OPND_Rm_EXT
);
5546 gas_assert (idx
== 1 || idx
== 2);
5547 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5548 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5549 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5550 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5551 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5552 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5560 DEBUG_TRACE ("exit with SUCCESS");
5564 /* Check for loads and stores that will cause unpredictable behavior. */
5567 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5569 aarch64_inst
*base
= &instr
->base
;
5570 const aarch64_opcode
*opcode
= base
->opcode
;
5571 const aarch64_opnd_info
*opnds
= base
->operands
;
5572 switch (opcode
->iclass
)
5578 /* Loading/storing the base register is unpredictable if writeback. */
5579 if ((aarch64_get_operand_class (opnds
[0].type
)
5580 == AARCH64_OPND_CLASS_INT_REG
)
5581 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5582 && opnds
[1].addr
.base_regno
!= REG_SP
5583 && opnds
[1].addr
.writeback
)
5584 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5587 case ldstnapair_offs
:
5588 case ldstpair_indexed
:
5589 /* Loading/storing the base register is unpredictable if writeback. */
5590 if ((aarch64_get_operand_class (opnds
[0].type
)
5591 == AARCH64_OPND_CLASS_INT_REG
)
5592 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5593 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5594 && opnds
[2].addr
.base_regno
!= REG_SP
5595 && opnds
[2].addr
.writeback
)
5596 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5597 /* Load operations must load different registers. */
5598 if ((opcode
->opcode
& (1 << 22))
5599 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5600 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5607 /* A wrapper function to interface with libopcodes on encoding and
5608 record the error message if there is any.
5610 Return TRUE on success; otherwise return FALSE. */
5613 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5616 aarch64_operand_error error_info
;
5617 error_info
.kind
= AARCH64_OPDE_NIL
;
5618 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5622 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5623 record_operand_error_info (opcode
, &error_info
);
5628 #ifdef DEBUG_AARCH64
5630 dump_opcode_operands (const aarch64_opcode
*opcode
)
5633 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5635 aarch64_verbose ("\t\t opnd%d: %s", i
,
5636 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5637 ? aarch64_get_operand_name (opcode
->operands
[i
])
5638 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5642 #endif /* DEBUG_AARCH64 */
5644 /* This is the guts of the machine-dependent assembler. STR points to a
5645 machine dependent instruction. This function is supposed to emit
5646 the frags/bytes it assembles to. */
5649 md_assemble (char *str
)
5652 templates
*template;
5653 aarch64_opcode
*opcode
;
5654 aarch64_inst
*inst_base
;
5655 unsigned saved_cond
;
5657 /* Align the previous label if needed. */
5658 if (last_label_seen
!= NULL
)
5660 symbol_set_frag (last_label_seen
, frag_now
);
5661 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5662 S_SET_SEGMENT (last_label_seen
, now_seg
);
5665 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5667 DEBUG_TRACE ("\n\n");
5668 DEBUG_TRACE ("==============================");
5669 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5671 template = opcode_lookup (&p
);
5674 /* It wasn't an instruction, but it might be a register alias of
5675 the form alias .req reg directive. */
5676 if (!create_register_alias (str
, p
))
5677 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5682 skip_whitespace (p
);
5685 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5686 get_mnemonic_name (str
), str
);
5690 init_operand_error_report ();
5692 /* Sections are assumed to start aligned. In executable section, there is no
5693 MAP_DATA symbol pending. So we only align the address during
5694 MAP_DATA --> MAP_INSN transition.
5695 For other sections, this is not guaranteed. */
5696 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
5697 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
5698 frag_align_code (2, 0);
5700 saved_cond
= inst
.cond
;
5701 reset_aarch64_instruction (&inst
);
5702 inst
.cond
= saved_cond
;
5704 /* Iterate through all opcode entries with the same mnemonic name. */
5707 opcode
= template->opcode
;
5709 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5710 #ifdef DEBUG_AARCH64
5712 dump_opcode_operands (opcode
);
5713 #endif /* DEBUG_AARCH64 */
5715 mapping_state (MAP_INSN
);
5717 inst_base
= &inst
.base
;
5718 inst_base
->opcode
= opcode
;
5720 /* Truly conditionally executed instructions, e.g. b.cond. */
5721 if (opcode
->flags
& F_COND
)
5723 gas_assert (inst
.cond
!= COND_ALWAYS
);
5724 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5725 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5727 else if (inst
.cond
!= COND_ALWAYS
)
5729 /* It shouldn't arrive here, where the assembly looks like a
5730 conditional instruction but the found opcode is unconditional. */
5735 if (parse_operands (p
, opcode
)
5736 && programmer_friendly_fixup (&inst
)
5737 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5739 /* Check that this instruction is supported for this CPU. */
5740 if (!opcode
->avariant
5741 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5743 as_bad (_("selected processor does not support `%s'"), str
);
5747 warn_unpredictable_ldst (&inst
, str
);
5749 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5750 || !inst
.reloc
.need_libopcodes_p
)
5754 /* If there is relocation generated for the instruction,
5755 store the instruction information for the future fix-up. */
5756 struct aarch64_inst
*copy
;
5757 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5758 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5760 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5766 template = template->next
;
5767 if (template != NULL
)
5769 reset_aarch64_instruction (&inst
);
5770 inst
.cond
= saved_cond
;
5773 while (template != NULL
);
5775 /* Issue the error messages if any. */
5776 output_operand_error_report (str
);
5779 /* Various frobbings of labels and their addresses. */
5782 aarch64_start_line_hook (void)
5784 last_label_seen
= NULL
;
5788 aarch64_frob_label (symbolS
* sym
)
5790 last_label_seen
= sym
;
5792 dwarf2_emit_label (sym
);
5796 aarch64_data_in_code (void)
5798 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5800 *input_line_pointer
= '/';
5801 input_line_pointer
+= 5;
5802 *input_line_pointer
= 0;
5810 aarch64_canonicalize_symbol_name (char *name
)
5814 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
5815 *(name
+ len
- 5) = 0;
5820 /* Table of all register names defined by default. The user can
5821 define additional names with .req. Note that all register names
5822 should appear in both upper and lowercase variants. Some registers
5823 also have mixed-case names. */
5825 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5826 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5827 #define REGSET31(p,t) \
5828 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5829 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5830 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5831 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5832 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5833 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5834 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5835 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5836 #define REGSET(p,t) \
5837 REGSET31(p,t), REGNUM(p,31,t)
5839 /* These go into aarch64_reg_hsh hash-table. */
5840 static const reg_entry reg_names
[] = {
5841 /* Integer registers. */
5842 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
5843 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
5845 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
5846 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
5848 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
5849 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
5851 /* Coprocessor register numbers. */
5852 REGSET (c
, CN
), REGSET (C
, CN
),
5854 /* Floating-point single precision registers. */
5855 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
5857 /* Floating-point double precision registers. */
5858 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
5860 /* Floating-point half precision registers. */
5861 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
5863 /* Floating-point byte precision registers. */
5864 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
5866 /* Floating-point quad precision registers. */
5867 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
5869 /* FP/SIMD registers. */
5870 REGSET (v
, VN
), REGSET (V
, VN
),
5885 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5886 static const asm_nzcv nzcv_names
[] = {
5887 {"nzcv", B (n
, z
, c
, v
)},
5888 {"nzcV", B (n
, z
, c
, V
)},
5889 {"nzCv", B (n
, z
, C
, v
)},
5890 {"nzCV", B (n
, z
, C
, V
)},
5891 {"nZcv", B (n
, Z
, c
, v
)},
5892 {"nZcV", B (n
, Z
, c
, V
)},
5893 {"nZCv", B (n
, Z
, C
, v
)},
5894 {"nZCV", B (n
, Z
, C
, V
)},
5895 {"Nzcv", B (N
, z
, c
, v
)},
5896 {"NzcV", B (N
, z
, c
, V
)},
5897 {"NzCv", B (N
, z
, C
, v
)},
5898 {"NzCV", B (N
, z
, C
, V
)},
5899 {"NZcv", B (N
, Z
, c
, v
)},
5900 {"NZcV", B (N
, Z
, c
, V
)},
5901 {"NZCv", B (N
, Z
, C
, v
)},
5902 {"NZCV", B (N
, Z
, C
, V
)}
5915 /* MD interface: bits in the object file. */
5917 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5918 for use in the a.out file, and stores them in the array pointed to by buf.
5919 This knows about the endian-ness of the target machine and does
5920 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5921 2 (short) and 4 (long) Floating numbers are put out as a series of
5922 LITTLENUMS (shorts, here at least). */
5925 md_number_to_chars (char *buf
, valueT val
, int n
)
5927 if (target_big_endian
)
5928 number_to_chars_bigendian (buf
, val
, n
);
5930 number_to_chars_littleendian (buf
, val
, n
);
5933 /* MD interface: Sections. */
5935 /* Estimate the size of a frag before relaxing. Assume everything fits in
5939 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
5945 /* Round up a section size to the appropriate boundary. */
5948 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5953 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5954 of an rs_align_code fragment.
5956 Here we fill the frag with the appropriate info for padding the
5957 output stream. The resulting frag will consist of a fixed (fr_fix)
5958 and of a repeating (fr_var) part.
5960 The fixed content is always emitted before the repeating content and
5961 these two parts are used as follows in constructing the output:
5962 - the fixed part will be used to align to a valid instruction word
5963 boundary, in case that we start at a misaligned address; as no
5964 executable instruction can live at the misaligned location, we
5965 simply fill with zeros;
5966 - the variable part will be used to cover the remaining padding and
5967 we fill using the AArch64 NOP instruction.
5969 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
5970 enough storage space for up to 3 bytes for padding the back to a valid
5971 instruction alignment and exactly 4 bytes to store the NOP pattern. */
5974 aarch64_handle_align (fragS
* fragP
)
5976 /* NOP = d503201f */
5977 /* AArch64 instructions are always little-endian. */
5978 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5980 int bytes
, fix
, noop_size
;
5983 if (fragP
->fr_type
!= rs_align_code
)
5986 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5987 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
5990 gas_assert (fragP
->tc_frag_data
.recorded
);
5993 noop_size
= sizeof (aarch64_noop
);
5995 fix
= bytes
& (noop_size
- 1);
5999 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6003 fragP
->fr_fix
+= fix
;
6007 memcpy (p
, aarch64_noop
, noop_size
);
6008 fragP
->fr_var
= noop_size
;
6011 /* Perform target specific initialisation of a frag.
6012 Note - despite the name this initialisation is not done when the frag
6013 is created, but only when its type is assigned. A frag can be created
6014 and used a long time before its type is set, so beware of assuming that
6015 this initialisationis performed first. */
6019 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6020 int max_chars ATTRIBUTE_UNUSED
)
6024 #else /* OBJ_ELF is defined. */
6026 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6028 /* Record a mapping symbol for alignment frags. We will delete this
6029 later if the alignment ends up empty. */
6030 if (!fragP
->tc_frag_data
.recorded
)
6031 fragP
->tc_frag_data
.recorded
= 1;
6033 switch (fragP
->fr_type
)
6038 mapping_state_2 (MAP_DATA
, max_chars
);
6041 mapping_state_2 (MAP_INSN
, max_chars
);
6048 /* Initialize the DWARF-2 unwind information for this procedure. */
6051 tc_aarch64_frame_initial_instructions (void)
6053 cfi_add_CFA_def_cfa (REG_SP
, 0);
6055 #endif /* OBJ_ELF */
6057 /* Convert REGNAME to a DWARF-2 register number. */
6060 tc_aarch64_regname_to_dw2regnum (char *regname
)
6062 const reg_entry
*reg
= parse_reg (®name
);
6068 case REG_TYPE_SP_32
:
6069 case REG_TYPE_SP_64
:
6079 return reg
->number
+ 64;
6087 /* Implement DWARF2_ADDR_SIZE. */
6090 aarch64_dwarf2_addr_size (void)
6092 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6096 return bfd_arch_bits_per_address (stdoutput
) / 8;
6099 /* MD interface: Symbol and relocation handling. */
6101 /* Return the address within the segment that a PC-relative fixup is
6102 relative to. For AArch64 PC-relative fixups applied to instructions
6103 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6106 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6108 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6110 /* If this is pc-relative and we are going to emit a relocation
6111 then we just want to put out any pipeline compensation that the linker
6112 will need. Otherwise we want to use the calculated base. */
6114 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6115 || aarch64_force_relocation (fixP
)))
6118 /* AArch64 should be consistent for all pc-relative relocations. */
6119 return base
+ AARCH64_PCREL_OFFSET
;
6122 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6123 Otherwise we have no need to default values of symbols. */
6126 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6129 if (name
[0] == '_' && name
[1] == 'G'
6130 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6134 if (symbol_find (name
))
6135 as_bad (_("GOT already in the symbol table"));
6137 GOT_symbol
= symbol_new (name
, undefined_section
,
6138 (valueT
) 0, &zero_address_frag
);
6148 /* Return non-zero if the indicated VALUE has overflowed the maximum
6149 range expressible by a unsigned number with the indicated number of
6153 unsigned_overflow (valueT value
, unsigned bits
)
6156 if (bits
>= sizeof (valueT
) * 8)
6158 lim
= (valueT
) 1 << bits
;
6159 return (value
>= lim
);
6163 /* Return non-zero if the indicated VALUE has overflowed the maximum
6164 range expressible by an signed number with the indicated number of
6168 signed_overflow (offsetT value
, unsigned bits
)
6171 if (bits
>= sizeof (offsetT
) * 8)
6173 lim
= (offsetT
) 1 << (bits
- 1);
6174 return (value
< -lim
|| value
>= lim
);
6177 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6178 unsigned immediate offset load/store instruction, try to encode it as
6179 an unscaled, 9-bit, signed immediate offset load/store instruction.
6180 Return TRUE if it is successful; otherwise return FALSE.
6182 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6183 in response to the standard LDR/STR mnemonics when the immediate offset is
6184 unambiguous, i.e. when it is negative or unaligned. */
6187 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6190 enum aarch64_op new_op
;
6191 const aarch64_opcode
*new_opcode
;
6193 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6195 switch (instr
->opcode
->op
)
6197 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6198 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6199 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6200 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6201 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6202 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6203 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6204 case OP_STR_POS
: new_op
= OP_STUR
; break;
6205 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6206 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6207 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6208 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6209 default: new_op
= OP_NIL
; break;
6212 if (new_op
== OP_NIL
)
6215 new_opcode
= aarch64_get_opcode (new_op
);
6216 gas_assert (new_opcode
!= NULL
);
6218 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6219 instr
->opcode
->op
, new_opcode
->op
);
6221 aarch64_replace_opcode (instr
, new_opcode
);
6223 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6224 qualifier matching may fail because the out-of-date qualifier will
6225 prevent the operand being updated with a new and correct qualifier. */
6226 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6227 AARCH64_OPND_ADDR_SIMM9
);
6228 gas_assert (idx
== 1);
6229 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6231 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6233 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6239 /* Called by fix_insn to fix a MOV immediate alias instruction.
6241 Operand for a generic move immediate instruction, which is an alias
6242 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6243 a 32-bit/64-bit immediate value into general register. An assembler error
6244 shall result if the immediate cannot be created by a single one of these
6245 instructions. If there is a choice, then to ensure reversability an
6246 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6249 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6251 const aarch64_opcode
*opcode
;
6253 /* Need to check if the destination is SP/ZR. The check has to be done
6254 before any aarch64_replace_opcode. */
6255 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6256 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6258 instr
->operands
[1].imm
.value
= value
;
6259 instr
->operands
[1].skip
= 0;
6263 /* Try the MOVZ alias. */
6264 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6265 aarch64_replace_opcode (instr
, opcode
);
6266 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6267 &instr
->value
, NULL
, NULL
))
6269 put_aarch64_insn (buf
, instr
->value
);
6272 /* Try the MOVK alias. */
6273 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6274 aarch64_replace_opcode (instr
, opcode
);
6275 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6276 &instr
->value
, NULL
, NULL
))
6278 put_aarch64_insn (buf
, instr
->value
);
6283 if (try_mov_bitmask_p
)
6285 /* Try the ORR alias. */
6286 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6287 aarch64_replace_opcode (instr
, opcode
);
6288 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6289 &instr
->value
, NULL
, NULL
))
6291 put_aarch64_insn (buf
, instr
->value
);
6296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6297 _("immediate cannot be moved by a single instruction"));
6300 /* An instruction operand which is immediate related may have symbol used
6301 in the assembly, e.g.
6304 .set u32, 0x00ffff00
6306 At the time when the assembly instruction is parsed, a referenced symbol,
6307 like 'u32' in the above example may not have been seen; a fixS is created
6308 in such a case and is handled here after symbols have been resolved.
6309 Instruction is fixed up with VALUE using the information in *FIXP plus
6310 extra information in FLAGS.
6312 This function is called by md_apply_fix to fix up instructions that need
6313 a fix-up described above but does not involve any linker-time relocation. */
6316 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6320 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6321 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6322 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6326 /* Now the instruction is about to be fixed-up, so the operand that
6327 was previously marked as 'ignored' needs to be unmarked in order
6328 to get the encoding done properly. */
6329 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6330 new_inst
->operands
[idx
].skip
= 0;
6333 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6337 case AARCH64_OPND_EXCEPTION
:
6338 if (unsigned_overflow (value
, 16))
6339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6340 _("immediate out of range"));
6341 insn
= get_aarch64_insn (buf
);
6342 insn
|= encode_svc_imm (value
);
6343 put_aarch64_insn (buf
, insn
);
6346 case AARCH64_OPND_AIMM
:
6347 /* ADD or SUB with immediate.
6348 NOTE this assumes we come here with a add/sub shifted reg encoding
6349 3 322|2222|2 2 2 21111 111111
6350 1 098|7654|3 2 1 09876 543210 98765 43210
6351 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6352 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6353 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6354 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6356 3 322|2222|2 2 221111111111
6357 1 098|7654|3 2 109876543210 98765 43210
6358 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6359 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6360 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6361 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6362 Fields sf Rn Rd are already set. */
6363 insn
= get_aarch64_insn (buf
);
6367 insn
= reencode_addsub_switch_add_sub (insn
);
6371 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6372 && unsigned_overflow (value
, 12))
6374 /* Try to shift the value by 12 to make it fit. */
6375 if (((value
>> 12) << 12) == value
6376 && ! unsigned_overflow (value
, 12 + 12))
6379 insn
|= encode_addsub_imm_shift_amount (1);
6383 if (unsigned_overflow (value
, 12))
6384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6385 _("immediate out of range"));
6387 insn
|= encode_addsub_imm (value
);
6389 put_aarch64_insn (buf
, insn
);
6392 case AARCH64_OPND_SIMD_IMM
:
6393 case AARCH64_OPND_SIMD_IMM_SFT
:
6394 case AARCH64_OPND_LIMM
:
6395 /* Bit mask immediate. */
6396 gas_assert (new_inst
!= NULL
);
6397 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6398 new_inst
->operands
[idx
].imm
.value
= value
;
6399 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6400 &new_inst
->value
, NULL
, NULL
))
6401 put_aarch64_insn (buf
, new_inst
->value
);
6403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6404 _("invalid immediate"));
6407 case AARCH64_OPND_HALF
:
6408 /* 16-bit unsigned immediate. */
6409 if (unsigned_overflow (value
, 16))
6410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6411 _("immediate out of range"));
6412 insn
= get_aarch64_insn (buf
);
6413 insn
|= encode_movw_imm (value
& 0xffff);
6414 put_aarch64_insn (buf
, insn
);
6417 case AARCH64_OPND_IMM_MOV
:
6418 /* Operand for a generic move immediate instruction, which is
6419 an alias instruction that generates a single MOVZ, MOVN or ORR
6420 instruction to loads a 32-bit/64-bit immediate value into general
6421 register. An assembler error shall result if the immediate cannot be
6422 created by a single one of these instructions. If there is a choice,
6423 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6424 and MOVZ or MOVN to ORR. */
6425 gas_assert (new_inst
!= NULL
);
6426 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6429 case AARCH64_OPND_ADDR_SIMM7
:
6430 case AARCH64_OPND_ADDR_SIMM9
:
6431 case AARCH64_OPND_ADDR_SIMM9_2
:
6432 case AARCH64_OPND_ADDR_UIMM12
:
6433 /* Immediate offset in an address. */
6434 insn
= get_aarch64_insn (buf
);
6436 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6437 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6438 || new_inst
->opcode
->operands
[2] == opnd
);
6440 /* Get the index of the address operand. */
6441 if (new_inst
->opcode
->operands
[1] == opnd
)
6442 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6445 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6448 /* Update the resolved offset value. */
6449 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6451 /* Encode/fix-up. */
6452 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6453 &new_inst
->value
, NULL
, NULL
))
6455 put_aarch64_insn (buf
, new_inst
->value
);
6458 else if (new_inst
->opcode
->iclass
== ldst_pos
6459 && try_to_encode_as_unscaled_ldst (new_inst
))
6461 put_aarch64_insn (buf
, new_inst
->value
);
6465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6466 _("immediate offset out of range"));
6471 as_fatal (_("unhandled operand code %d"), opnd
);
6475 /* Apply a fixup (fixP) to segment data, once it has been determined
6476 by our caller that we have all the info we need to fix it up.
6478 Parameter valP is the pointer to the value of the bits. */
6481 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6483 offsetT value
= *valP
;
6485 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6487 unsigned flags
= fixP
->fx_addnumber
;
6489 DEBUG_TRACE ("\n\n");
6490 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6491 DEBUG_TRACE ("Enter md_apply_fix");
6493 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6495 /* Note whether this will delete the relocation. */
6497 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6500 /* Process the relocations. */
6501 switch (fixP
->fx_r_type
)
6503 case BFD_RELOC_NONE
:
6504 /* This will need to go in the object file. */
6509 case BFD_RELOC_8_PCREL
:
6510 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6511 md_number_to_chars (buf
, value
, 1);
6515 case BFD_RELOC_16_PCREL
:
6516 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6517 md_number_to_chars (buf
, value
, 2);
6521 case BFD_RELOC_32_PCREL
:
6522 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6523 md_number_to_chars (buf
, value
, 4);
6527 case BFD_RELOC_64_PCREL
:
6528 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6529 md_number_to_chars (buf
, value
, 8);
6532 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6533 /* We claim that these fixups have been processed here, even if
6534 in fact we generate an error because we do not have a reloc
6535 for them, so tc_gen_reloc() will reject them. */
6537 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6540 _("undefined symbol %s used as an immediate value"),
6541 S_GET_NAME (fixP
->fx_addsy
));
6542 goto apply_fix_return
;
6544 fix_insn (fixP
, flags
, value
);
6547 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6548 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6552 _("pc-relative load offset not word aligned"));
6553 if (signed_overflow (value
, 21))
6554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6555 _("pc-relative load offset out of range"));
6556 insn
= get_aarch64_insn (buf
);
6557 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6558 put_aarch64_insn (buf
, insn
);
6562 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6563 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6565 if (signed_overflow (value
, 21))
6566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6567 _("pc-relative address offset out of range"));
6568 insn
= get_aarch64_insn (buf
);
6569 insn
|= encode_adr_imm (value
);
6570 put_aarch64_insn (buf
, insn
);
6574 case BFD_RELOC_AARCH64_BRANCH19
:
6575 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6579 _("conditional branch target not word aligned"));
6580 if (signed_overflow (value
, 21))
6581 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6582 _("conditional branch out of range"));
6583 insn
= get_aarch64_insn (buf
);
6584 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6585 put_aarch64_insn (buf
, insn
);
6589 case BFD_RELOC_AARCH64_TSTBR14
:
6590 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6594 _("conditional branch target not word aligned"));
6595 if (signed_overflow (value
, 16))
6596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6597 _("conditional branch out of range"));
6598 insn
= get_aarch64_insn (buf
);
6599 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6600 put_aarch64_insn (buf
, insn
);
6604 case BFD_RELOC_AARCH64_JUMP26
:
6605 case BFD_RELOC_AARCH64_CALL26
:
6606 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6610 _("branch target not word aligned"));
6611 if (signed_overflow (value
, 28))
6612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6613 _("branch out of range"));
6614 insn
= get_aarch64_insn (buf
);
6615 insn
|= encode_branch_ofs_26 (value
>> 2);
6616 put_aarch64_insn (buf
, insn
);
6620 case BFD_RELOC_AARCH64_MOVW_G0
:
6621 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6622 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6625 case BFD_RELOC_AARCH64_MOVW_G1
:
6626 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6627 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6630 case BFD_RELOC_AARCH64_MOVW_G2
:
6631 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6632 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6635 case BFD_RELOC_AARCH64_MOVW_G3
:
6638 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6640 insn
= get_aarch64_insn (buf
);
6644 /* REL signed addend must fit in 16 bits */
6645 if (signed_overflow (value
, 16))
6646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6647 _("offset out of range"));
6651 /* Check for overflow and scale. */
6652 switch (fixP
->fx_r_type
)
6654 case BFD_RELOC_AARCH64_MOVW_G0
:
6655 case BFD_RELOC_AARCH64_MOVW_G1
:
6656 case BFD_RELOC_AARCH64_MOVW_G2
:
6657 case BFD_RELOC_AARCH64_MOVW_G3
:
6658 if (unsigned_overflow (value
, scale
+ 16))
6659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6660 _("unsigned value out of range"));
6662 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6663 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6664 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6665 /* NOTE: We can only come here with movz or movn. */
6666 if (signed_overflow (value
, scale
+ 16))
6667 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6668 _("signed value out of range"));
6671 /* Force use of MOVN. */
6673 insn
= reencode_movzn_to_movn (insn
);
6677 /* Force use of MOVZ. */
6678 insn
= reencode_movzn_to_movz (insn
);
6682 /* Unchecked relocations. */
6688 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6689 insn
|= encode_movw_imm (value
& 0xffff);
6691 put_aarch64_insn (buf
, insn
);
6695 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6696 fixP
->fx_r_type
= (ilp32_p
6697 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6698 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
6699 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6700 /* Should always be exported to object file, see
6701 aarch64_force_relocation(). */
6702 gas_assert (!fixP
->fx_done
);
6703 gas_assert (seg
->use_rela_p
);
6706 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6707 fixP
->fx_r_type
= (ilp32_p
6708 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6709 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
6710 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6711 /* Should always be exported to object file, see
6712 aarch64_force_relocation(). */
6713 gas_assert (!fixP
->fx_done
);
6714 gas_assert (seg
->use_rela_p
);
6717 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6718 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6719 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6720 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6721 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6722 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6723 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6724 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6725 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6726 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6727 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6728 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6729 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6730 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6731 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6732 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6733 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6734 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6735 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6736 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6737 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6738 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6739 /* Should always be exported to object file, see
6740 aarch64_force_relocation(). */
6741 gas_assert (!fixP
->fx_done
);
6742 gas_assert (seg
->use_rela_p
);
6745 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6746 /* Should always be exported to object file, see
6747 aarch64_force_relocation(). */
6748 fixP
->fx_r_type
= (ilp32_p
6749 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6750 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
6751 gas_assert (!fixP
->fx_done
);
6752 gas_assert (seg
->use_rela_p
);
6755 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6756 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6757 case BFD_RELOC_AARCH64_ADD_LO12
:
6758 case BFD_RELOC_AARCH64_LDST8_LO12
:
6759 case BFD_RELOC_AARCH64_LDST16_LO12
:
6760 case BFD_RELOC_AARCH64_LDST32_LO12
:
6761 case BFD_RELOC_AARCH64_LDST64_LO12
:
6762 case BFD_RELOC_AARCH64_LDST128_LO12
:
6763 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6764 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6765 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6766 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6767 /* Should always be exported to object file, see
6768 aarch64_force_relocation(). */
6769 gas_assert (!fixP
->fx_done
);
6770 gas_assert (seg
->use_rela_p
);
6773 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6774 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6775 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6778 case BFD_RELOC_UNUSED
:
6779 /* An error will already have been reported. */
6783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6784 _("unexpected %s fixup"),
6785 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6790 /* Free the allocated the struct aarch64_inst.
6791 N.B. currently there are very limited number of fix-up types actually use
6792 this field, so the impact on the performance should be minimal . */
6793 if (fixP
->tc_fix_data
.inst
!= NULL
)
6794 free (fixP
->tc_fix_data
.inst
);
6799 /* Translate internal representation of relocation info to BFD target
6803 tc_gen_reloc (asection
* section
, fixS
* fixp
)
6806 bfd_reloc_code_real_type code
;
6808 reloc
= xmalloc (sizeof (arelent
));
6810 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
6811 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6812 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6816 if (section
->use_rela_p
)
6817 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
6819 fixp
->fx_offset
= reloc
->address
;
6821 reloc
->addend
= fixp
->fx_offset
;
6823 code
= fixp
->fx_r_type
;
6828 code
= BFD_RELOC_16_PCREL
;
6833 code
= BFD_RELOC_32_PCREL
;
6838 code
= BFD_RELOC_64_PCREL
;
6845 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6846 if (reloc
->howto
== NULL
)
6848 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6850 ("cannot represent %s relocation in this object file format"),
6851 bfd_get_reloc_code_name (code
));
6858 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6861 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
6863 bfd_reloc_code_real_type type
;
6867 FIXME: @@ Should look at CPU word size. */
6874 type
= BFD_RELOC_16
;
6877 type
= BFD_RELOC_32
;
6880 type
= BFD_RELOC_64
;
6883 as_bad (_("cannot do %u-byte relocation"), size
);
6884 type
= BFD_RELOC_UNUSED
;
6888 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6892 aarch64_force_relocation (struct fix
*fixp
)
6894 switch (fixp
->fx_r_type
)
6896 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6897 /* Perform these "immediate" internal relocations
6898 even if the symbol is extern or weak. */
6901 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6902 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6903 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6904 /* Pseudo relocs that need to be fixed up according to
6908 case BFD_RELOC_AARCH64_ADD_LO12
:
6909 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6910 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6911 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6912 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6913 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6914 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6915 case BFD_RELOC_AARCH64_LDST128_LO12
:
6916 case BFD_RELOC_AARCH64_LDST16_LO12
:
6917 case BFD_RELOC_AARCH64_LDST32_LO12
:
6918 case BFD_RELOC_AARCH64_LDST64_LO12
:
6919 case BFD_RELOC_AARCH64_LDST8_LO12
:
6920 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6921 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6922 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6923 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6924 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6925 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6926 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6927 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6928 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6929 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6930 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6931 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6932 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6933 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6934 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6935 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6936 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6937 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6938 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6939 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6940 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6941 /* Always leave these relocations for the linker. */
6948 return generic_force_reloc (fixp
);
6954 elf64_aarch64_target_format (void)
6956 if (target_big_endian
)
6957 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
6959 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
6963 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
6965 elf_frob_symbol (symp
, puntp
);
6969 /* MD interface: Finalization. */
6971 /* A good place to do this, although this was probably not intended
6972 for this kind of use. We need to dump the literal pool before
6973 references are made to a null symbol pointer. */
6976 aarch64_cleanup (void)
6980 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
6982 /* Put it at the end of the relevant section. */
6983 subseg_set (pool
->section
, pool
->sub_section
);
6989 /* Remove any excess mapping symbols generated for alignment frags in
6990 SEC. We may have created a mapping symbol before a zero byte
6991 alignment; remove it if there's a mapping symbol after the
6994 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
6995 void *dummy ATTRIBUTE_UNUSED
)
6997 segment_info_type
*seginfo
= seg_info (sec
);
7000 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7003 for (fragp
= seginfo
->frchainP
->frch_root
;
7004 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7006 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7007 fragS
*next
= fragp
->fr_next
;
7009 /* Variable-sized frags have been converted to fixed size by
7010 this point. But if this was variable-sized to start with,
7011 there will be a fixed-size frag after it. So don't handle
7013 if (sym
== NULL
|| next
== NULL
)
7016 if (S_GET_VALUE (sym
) < next
->fr_address
)
7017 /* Not at the end of this frag. */
7019 know (S_GET_VALUE (sym
) == next
->fr_address
);
7023 if (next
->tc_frag_data
.first_map
!= NULL
)
7025 /* Next frag starts with a mapping symbol. Discard this
7027 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7031 if (next
->fr_next
== NULL
)
7033 /* This mapping symbol is at the end of the section. Discard
7035 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7036 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7040 /* As long as we have empty frags without any mapping symbols,
7042 /* If the next frag is non-empty and does not start with a
7043 mapping symbol, then this mapping symbol is required. */
7044 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7047 next
= next
->fr_next
;
7049 while (next
!= NULL
);
7054 /* Adjust the symbol table. */
7057 aarch64_adjust_symtab (void)
7060 /* Remove any overlapping mapping symbols generated by alignment frags. */
7061 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7062 /* Now do generic ELF adjustments. */
7063 elf_adjust_symtab ();
7068 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7070 const char *hash_err
;
7072 hash_err
= hash_insert (table
, key
, value
);
7074 printf ("Internal Error: Can't hash %s\n", key
);
7078 fill_instruction_hash_table (void)
7080 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7082 while (opcode
->name
!= NULL
)
7084 templates
*templ
, *new_templ
;
7085 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7087 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7088 new_templ
->opcode
= opcode
;
7089 new_templ
->next
= NULL
;
7092 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7095 new_templ
->next
= templ
->next
;
7096 templ
->next
= new_templ
;
7103 convert_to_upper (char *dst
, const char *src
, size_t num
)
7106 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7107 *dst
= TOUPPER (*src
);
7111 /* Assume STR point to a lower-case string, allocate, convert and return
7112 the corresponding upper-case string. */
7113 static inline const char*
7114 get_upper_str (const char *str
)
7117 size_t len
= strlen (str
);
7118 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7120 convert_to_upper (ret
, str
, len
);
7124 /* MD interface: Initialization. */
7132 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7133 || (aarch64_cond_hsh
= hash_new ()) == NULL
7134 || (aarch64_shift_hsh
= hash_new ()) == NULL
7135 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7136 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7137 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7138 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7139 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7140 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7141 || (aarch64_reg_hsh
= hash_new ()) == NULL
7142 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7143 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7144 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
7145 as_fatal (_("virtual memory exhausted"));
7147 fill_instruction_hash_table ();
7149 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7150 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7151 (void *) (aarch64_sys_regs
+ i
));
7153 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7154 checked_hash_insert (aarch64_pstatefield_hsh
,
7155 aarch64_pstatefields
[i
].name
,
7156 (void *) (aarch64_pstatefields
+ i
));
7158 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
7159 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7160 aarch64_sys_regs_ic
[i
].template,
7161 (void *) (aarch64_sys_regs_ic
+ i
));
7163 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
7164 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7165 aarch64_sys_regs_dc
[i
].template,
7166 (void *) (aarch64_sys_regs_dc
+ i
));
7168 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
7169 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7170 aarch64_sys_regs_at
[i
].template,
7171 (void *) (aarch64_sys_regs_at
+ i
));
7173 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
7174 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7175 aarch64_sys_regs_tlbi
[i
].template,
7176 (void *) (aarch64_sys_regs_tlbi
+ i
));
7178 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7179 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7180 (void *) (reg_names
+ i
));
7182 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7183 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7184 (void *) (nzcv_names
+ i
));
7186 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7188 const char *name
= aarch64_operand_modifiers
[i
].name
;
7189 checked_hash_insert (aarch64_shift_hsh
, name
,
7190 (void *) (aarch64_operand_modifiers
+ i
));
7191 /* Also hash the name in the upper case. */
7192 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7193 (void *) (aarch64_operand_modifiers
+ i
));
7196 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7199 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7200 the same condition code. */
7201 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7203 const char *name
= aarch64_conds
[i
].names
[j
];
7206 checked_hash_insert (aarch64_cond_hsh
, name
,
7207 (void *) (aarch64_conds
+ i
));
7208 /* Also hash the name in the upper case. */
7209 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7210 (void *) (aarch64_conds
+ i
));
7214 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7216 const char *name
= aarch64_barrier_options
[i
].name
;
7217 /* Skip xx00 - the unallocated values of option. */
7220 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7221 (void *) (aarch64_barrier_options
+ i
));
7222 /* Also hash the name in the upper case. */
7223 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7224 (void *) (aarch64_barrier_options
+ i
));
7227 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7229 const char* name
= aarch64_prfops
[i
].name
;
7230 /* Skip the unallocated hint encodings. */
7233 checked_hash_insert (aarch64_pldop_hsh
, name
,
7234 (void *) (aarch64_prfops
+ i
));
7235 /* Also hash the name in the upper case. */
7236 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7237 (void *) (aarch64_prfops
+ i
));
7240 /* Set the cpu variant based on the command-line options. */
7242 mcpu_cpu_opt
= march_cpu_opt
;
7245 mcpu_cpu_opt
= &cpu_default
;
7247 cpu_variant
= *mcpu_cpu_opt
;
7249 /* Record the CPU type. */
7250 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7252 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7255 /* Command line processing. */
7257 const char *md_shortopts
= "m:";
7259 #ifdef AARCH64_BI_ENDIAN
7260 #define OPTION_EB (OPTION_MD_BASE + 0)
7261 #define OPTION_EL (OPTION_MD_BASE + 1)
7263 #if TARGET_BYTES_BIG_ENDIAN
7264 #define OPTION_EB (OPTION_MD_BASE + 0)
7266 #define OPTION_EL (OPTION_MD_BASE + 1)
7270 struct option md_longopts
[] = {
7272 {"EB", no_argument
, NULL
, OPTION_EB
},
7275 {"EL", no_argument
, NULL
, OPTION_EL
},
7277 {NULL
, no_argument
, NULL
, 0}
7280 size_t md_longopts_size
= sizeof (md_longopts
);
7282 struct aarch64_option_table
7284 char *option
; /* Option name to match. */
7285 char *help
; /* Help information. */
7286 int *var
; /* Variable to change. */
7287 int value
; /* What to change it to. */
7288 char *deprecated
; /* If non-null, print this message. */
7291 static struct aarch64_option_table aarch64_opts
[] = {
7292 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7293 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7295 #ifdef DEBUG_AARCH64
7296 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7297 #endif /* DEBUG_AARCH64 */
7298 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7300 {"mno-verbose-error", N_("do not output verbose error messages"),
7301 &verbose_error_p
, 0, NULL
},
7302 {NULL
, NULL
, NULL
, 0, NULL
}
7305 struct aarch64_cpu_option_table
7308 const aarch64_feature_set value
;
7309 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7311 const char *canonical_name
;
7314 /* This list should, at a minimum, contain all the cpu names
7315 recognized by GCC. */
7316 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7317 {"all", AARCH64_ANY
, NULL
},
7318 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7319 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7320 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7321 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7322 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7323 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7324 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7325 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7326 "Samsung Exynos M1"},
7327 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7328 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7330 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7331 in earlier releases and is superseded by 'xgene1' in all
7333 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7334 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7335 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7336 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7337 {"generic", AARCH64_ARCH_V8
, NULL
},
7339 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7342 struct aarch64_arch_option_table
7345 const aarch64_feature_set value
;
7348 /* This list should, at a minimum, contain all the architecture names
7349 recognized by GCC. */
7350 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7351 {"all", AARCH64_ANY
},
7352 {"armv8-a", AARCH64_ARCH_V8
},
7353 {NULL
, AARCH64_ARCH_NONE
}
7356 /* ISA extensions. */
7357 struct aarch64_option_cpu_value_table
7360 const aarch64_feature_set value
;
7363 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7364 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7365 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7366 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7367 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7368 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7369 {NULL
, AARCH64_ARCH_NONE
}
7372 struct aarch64_long_option_table
7374 char *option
; /* Substring to match. */
7375 char *help
; /* Help information. */
7376 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7377 char *deprecated
; /* If non-null, print this message. */
7381 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7382 bfd_boolean ext_only
)
7384 /* We insist on extensions being added before being removed. We achieve
7385 this by using the ADDING_VALUE variable to indicate whether we are
7386 adding an extension (1) or removing it (0) and only allowing it to
7387 change in the order -1 -> 1 -> 0. */
7388 int adding_value
= -1;
7389 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7391 /* Copy the feature set, so that we can modify it. */
7395 while (str
!= NULL
&& *str
!= 0)
7397 const struct aarch64_option_cpu_value_table
*opt
;
7405 as_bad (_("invalid architectural extension"));
7409 ext
= strchr (++str
, '+');
7415 optlen
= strlen (str
);
7417 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7419 if (adding_value
!= 0)
7424 else if (optlen
> 0)
7426 if (adding_value
== -1)
7428 else if (adding_value
!= 1)
7430 as_bad (_("must specify extensions to add before specifying "
7431 "those to remove"));
7438 as_bad (_("missing architectural extension"));
7442 gas_assert (adding_value
!= -1);
7444 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7445 if (strncmp (opt
->name
, str
, optlen
) == 0)
7447 /* Add or remove the extension. */
7449 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7451 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7455 if (opt
->name
== NULL
)
7457 as_bad (_("unknown architectural extension `%s'"), str
);
7468 aarch64_parse_cpu (char *str
)
7470 const struct aarch64_cpu_option_table
*opt
;
7471 char *ext
= strchr (str
, '+');
7477 optlen
= strlen (str
);
7481 as_bad (_("missing cpu name `%s'"), str
);
7485 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7486 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7488 mcpu_cpu_opt
= &opt
->value
;
7490 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7495 as_bad (_("unknown cpu `%s'"), str
);
7500 aarch64_parse_arch (char *str
)
7502 const struct aarch64_arch_option_table
*opt
;
7503 char *ext
= strchr (str
, '+');
7509 optlen
= strlen (str
);
7513 as_bad (_("missing architecture name `%s'"), str
);
7517 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7518 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7520 march_cpu_opt
= &opt
->value
;
7522 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7527 as_bad (_("unknown architecture `%s'\n"), str
);
7532 struct aarch64_option_abi_value_table
7535 enum aarch64_abi_type value
;
7538 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7539 {"ilp32", AARCH64_ABI_ILP32
},
7540 {"lp64", AARCH64_ABI_LP64
},
7545 aarch64_parse_abi (char *str
)
7547 const struct aarch64_option_abi_value_table
*opt
;
7548 size_t optlen
= strlen (str
);
7552 as_bad (_("missing abi name `%s'"), str
);
7556 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
7557 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7559 aarch64_abi
= opt
->value
;
7563 as_bad (_("unknown abi `%s'\n"), str
);
7567 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7569 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7570 aarch64_parse_abi
, NULL
},
7571 #endif /* OBJ_ELF */
7572 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7573 aarch64_parse_cpu
, NULL
},
7574 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7575 aarch64_parse_arch
, NULL
},
7576 {NULL
, NULL
, 0, NULL
}
7580 md_parse_option (int c
, char *arg
)
7582 struct aarch64_option_table
*opt
;
7583 struct aarch64_long_option_table
*lopt
;
7589 target_big_endian
= 1;
7595 target_big_endian
= 0;
7600 /* Listing option. Just ignore these, we don't support additional
7605 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7607 if (c
== opt
->option
[0]
7608 && ((arg
== NULL
&& opt
->option
[1] == 0)
7609 || streq (arg
, opt
->option
+ 1)))
7611 /* If the option is deprecated, tell the user. */
7612 if (opt
->deprecated
!= NULL
)
7613 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7614 arg
? arg
: "", _(opt
->deprecated
));
7616 if (opt
->var
!= NULL
)
7617 *opt
->var
= opt
->value
;
7623 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7625 /* These options are expected to have an argument. */
7626 if (c
== lopt
->option
[0]
7628 && strncmp (arg
, lopt
->option
+ 1,
7629 strlen (lopt
->option
+ 1)) == 0)
7631 /* If the option is deprecated, tell the user. */
7632 if (lopt
->deprecated
!= NULL
)
7633 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7634 _(lopt
->deprecated
));
7636 /* Call the sup-option parser. */
7637 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7648 md_show_usage (FILE * fp
)
7650 struct aarch64_option_table
*opt
;
7651 struct aarch64_long_option_table
*lopt
;
7653 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7655 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7656 if (opt
->help
!= NULL
)
7657 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7659 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7660 if (lopt
->help
!= NULL
)
7661 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7665 -EB assemble code for a big-endian cpu\n"));
7670 -EL assemble code for a little-endian cpu\n"));
7674 /* Parse a .cpu directive. */
7677 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7679 const struct aarch64_cpu_option_table
*opt
;
7685 name
= input_line_pointer
;
7686 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7687 input_line_pointer
++;
7688 saved_char
= *input_line_pointer
;
7689 *input_line_pointer
= 0;
7691 ext
= strchr (name
, '+');
7694 optlen
= ext
- name
;
7696 optlen
= strlen (name
);
7698 /* Skip the first "all" entry. */
7699 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7700 if (strlen (opt
->name
) == optlen
7701 && strncmp (name
, opt
->name
, optlen
) == 0)
7703 mcpu_cpu_opt
= &opt
->value
;
7705 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7708 cpu_variant
= *mcpu_cpu_opt
;
7710 *input_line_pointer
= saved_char
;
7711 demand_empty_rest_of_line ();
7714 as_bad (_("unknown cpu `%s'"), name
);
7715 *input_line_pointer
= saved_char
;
7716 ignore_rest_of_line ();
7720 /* Parse a .arch directive. */
7723 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7725 const struct aarch64_arch_option_table
*opt
;
7731 name
= input_line_pointer
;
7732 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7733 input_line_pointer
++;
7734 saved_char
= *input_line_pointer
;
7735 *input_line_pointer
= 0;
7737 ext
= strchr (name
, '+');
7740 optlen
= ext
- name
;
7742 optlen
= strlen (name
);
7744 /* Skip the first "all" entry. */
7745 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7746 if (strlen (opt
->name
) == optlen
7747 && strncmp (name
, opt
->name
, optlen
) == 0)
7749 mcpu_cpu_opt
= &opt
->value
;
7751 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7754 cpu_variant
= *mcpu_cpu_opt
;
7756 *input_line_pointer
= saved_char
;
7757 demand_empty_rest_of_line ();
7761 as_bad (_("unknown architecture `%s'\n"), name
);
7762 *input_line_pointer
= saved_char
;
7763 ignore_rest_of_line ();
7766 /* Parse a .arch_extension directive. */
7769 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
7772 char *ext
= input_line_pointer
;;
7774 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7775 input_line_pointer
++;
7776 saved_char
= *input_line_pointer
;
7777 *input_line_pointer
= 0;
7779 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
7782 cpu_variant
= *mcpu_cpu_opt
;
7784 *input_line_pointer
= saved_char
;
7785 demand_empty_rest_of_line ();
7788 /* Copy symbol information. */
7791 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
7793 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);