1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
410 /* Stuff needed to resolve the label ambiguity
419 static symbolS
*last_label_seen
;
421 /* Literal pool structure. Held on a per-section
422 and per-sub-section basis. */
424 #define MAX_LITERAL_POOL_SIZE 1024
425 typedef struct literal_expression
428 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
429 LITTLENUM_TYPE
* bignum
;
430 } literal_expression
;
432 typedef struct literal_pool
434 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
435 unsigned int next_free_entry
;
441 struct literal_pool
*next
;
444 /* Pointer to a linked list of literal pools. */
445 static literal_pool
*list_of_pools
= NULL
;
449 /* This array holds the chars that always start a comment. If the
450 pre-processor is disabled, these aren't very useful. */
451 const char comment_chars
[] = "";
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output. */
456 /* Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output. */
459 /* Also note that comments like this one will always work. */
460 const char line_comment_chars
[] = "#";
462 const char line_separator_chars
[] = ";";
464 /* Chars that can be used to separate mant
465 from exp in floating point numbers. */
466 const char EXP_CHARS
[] = "eE";
468 /* Chars that mean this number is a floating point constant. */
472 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
474 /* Prefix character that indicates the start of an immediate value. */
475 #define is_immediate_prefix(C) ((C) == '#')
477 /* Separator character handling. */
479 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
481 static inline bfd_boolean
482 skip_past_char (char **str
, char c
)
493 #define skip_past_comma(str) skip_past_char (str, ',')
495 /* Arithmetic expressions (possibly involving symbols). */
497 static bfd_boolean in_my_get_expression_p
= FALSE
;
499 /* Third argument to my_get_expression. */
500 #define GE_NO_PREFIX 0
501 #define GE_OPT_PREFIX 1
503 /* Return TRUE if the string pointed by *STR is successfully parsed
504 as an valid expression; *EP will be filled with the information of
505 such an expression. Otherwise return FALSE. */
508 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
513 int prefix_present_p
= 0;
520 if (is_immediate_prefix (**str
))
523 prefix_present_p
= 1;
530 memset (ep
, 0, sizeof (expressionS
));
532 save_in
= input_line_pointer
;
533 input_line_pointer
= *str
;
534 in_my_get_expression_p
= TRUE
;
535 seg
= expression (ep
);
536 in_my_get_expression_p
= FALSE
;
538 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
540 /* We found a bad expression in md_operand(). */
541 *str
= input_line_pointer
;
542 input_line_pointer
= save_in
;
543 if (prefix_present_p
&& ! error_p ())
544 set_fatal_syntax_error (_("bad expression"));
546 set_first_syntax_error (_("bad expression"));
551 if (seg
!= absolute_section
552 && seg
!= text_section
553 && seg
!= data_section
554 && seg
!= bss_section
&& seg
!= undefined_section
)
556 set_syntax_error (_("bad segment"));
557 *str
= input_line_pointer
;
558 input_line_pointer
= save_in
;
565 *str
= input_line_pointer
;
566 input_line_pointer
= save_in
;
570 /* Turn a string in input_line_pointer into a floating point constant
571 of type TYPE, and store the appropriate bytes in *LITP. The number
572 of LITTLENUMS emitted is stored in *SIZEP. An error message is
573 returned, or NULL on OK. */
576 md_atof (int type
, char *litP
, int *sizeP
)
578 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
581 /* We handle all bad expressions here, so that we can report the faulty
582 instruction in the error message. */
584 md_operand (expressionS
* exp
)
586 if (in_my_get_expression_p
)
587 exp
->X_op
= O_illegal
;
590 /* Immediate values. */
592 /* Errors may be set multiple times during parsing or bit encoding
593 (particularly in the Neon bits), but usually the earliest error which is set
594 will be the most meaningful. Avoid overwriting it with later (cascading)
595 errors by calling this function. */
598 first_error (const char *error
)
601 set_syntax_error (error
);
604 /* Similiar to first_error, but this function accepts formatted error
607 first_error_fmt (const char *format
, ...)
612 /* N.B. this single buffer will not cause error messages for different
613 instructions to pollute each other; this is because at the end of
614 processing of each assembly line, error message if any will be
615 collected by as_bad. */
616 static char buffer
[size
];
620 int ret ATTRIBUTE_UNUSED
;
621 va_start (args
, format
);
622 ret
= vsnprintf (buffer
, size
, format
, args
);
623 know (ret
<= size
- 1 && ret
>= 0);
625 set_syntax_error (buffer
);
629 /* Register parsing. */
631 /* Generic register parser which is called by other specialized
633 CCP points to what should be the beginning of a register name.
634 If it is indeed a valid register name, advance CCP over it and
635 return the reg_entry structure; otherwise return NULL.
636 It does not issue diagnostics. */
639 parse_reg (char **ccp
)
645 #ifdef REGISTER_PREFIX
646 if (*start
!= REGISTER_PREFIX
)
652 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
657 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
659 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
668 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
671 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
673 if (reg
->type
== type
)
678 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
679 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
680 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
681 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
682 case REG_TYPE_VN
: /* Vector register. */
683 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
684 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
685 == reg_type_masks
[reg
->type
]);
687 as_fatal ("unhandled type %d", type
);
692 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
693 Return the register number otherwise. *ISREG32 is set to one if the
694 register is 32-bit wide; *ISREGZERO is set to one if the register is
695 of type Z_32 or Z_64.
696 Note that this function does not issue any diagnostics. */
699 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
700 int *isreg32
, int *isregzero
)
703 const reg_entry
*reg
= parse_reg (&str
);
708 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
717 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
722 *isreg32
= reg
->type
== REG_TYPE_R_32
;
729 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
741 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
742 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
743 otherwise return FALSE.
745 Accept only one occurrence of:
746 8b 16b 4h 8h 2s 4s 1d 2d
749 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
753 unsigned element_size
;
754 enum neon_el_type type
;
764 width
= strtoul (ptr
, &ptr
, 10);
765 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
767 first_error_fmt (_("bad size %d in vector width specifier"), width
);
772 switch (TOLOWER (*ptr
))
800 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
802 first_error (_("missing element size"));
805 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
808 ("invalid element size %d and vector size combination %c"),
814 parsed_type
->type
= type
;
815 parsed_type
->width
= width
;
822 /* Parse a single type, e.g. ".8b", leading period included.
823 Only applicable to Vn registers.
825 Return TRUE on success; otherwise return FALSE. */
827 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
833 if (! parse_neon_type_for_operand (vectype
, &str
))
835 first_error (_("vector type expected"));
847 /* Parse a register of the type TYPE.
849 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
850 name or the parsed register is not of TYPE.
852 Otherwise return the register number, and optionally fill in the actual
853 type of the register in *RTYPE when multiple alternatives were given, and
854 return the register shape and element index information in *TYPEINFO.
856 IN_REG_LIST should be set with TRUE if the caller is parsing a register
860 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
861 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
864 const reg_entry
*reg
= parse_reg (&str
);
865 struct neon_type_el atype
;
866 struct neon_type_el parsetype
;
867 bfd_boolean is_typed_vecreg
= FALSE
;
870 atype
.type
= NT_invtype
;
878 set_default_error ();
882 if (! aarch64_check_reg_type (reg
, type
))
884 DEBUG_TRACE ("reg type check failed");
885 set_default_error ();
890 if (type
== REG_TYPE_VN
891 && parse_neon_operand_type (&parsetype
, &str
))
893 /* Register if of the form Vn.[bhsdq]. */
894 is_typed_vecreg
= TRUE
;
896 if (parsetype
.width
== 0)
897 /* Expect index. In the new scheme we cannot have
898 Vn.[bhsdq] represent a scalar. Therefore any
899 Vn.[bhsdq] should have an index following it.
900 Except in reglists ofcourse. */
901 atype
.defined
|= NTA_HASINDEX
;
903 atype
.defined
|= NTA_HASTYPE
;
905 atype
.type
= parsetype
.type
;
906 atype
.width
= parsetype
.width
;
909 if (skip_past_char (&str
, '['))
913 /* Reject Sn[index] syntax. */
914 if (!is_typed_vecreg
)
916 first_error (_("this type of register can't be indexed"));
920 if (in_reg_list
== TRUE
)
922 first_error (_("index not allowed inside register list"));
926 atype
.defined
|= NTA_HASINDEX
;
928 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
930 if (exp
.X_op
!= O_constant
)
932 first_error (_("constant expression required"));
936 if (! skip_past_char (&str
, ']'))
939 atype
.index
= exp
.X_add_number
;
941 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
943 /* Indexed vector register expected. */
944 first_error (_("indexed vector register expected"));
948 /* A vector reg Vn should be typed or indexed. */
949 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
951 first_error (_("invalid use of vector register"));
967 Return the register number on success; return PARSE_FAIL otherwise.
969 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
970 the register (e.g. NEON double or quad reg when either has been requested).
972 If this is a NEON vector register with additional type information, fill
973 in the struct pointed to by VECTYPE (if non-NULL).
975 This parser does not handle register list. */
978 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
979 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
981 struct neon_type_el atype
;
983 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
984 /*in_reg_list= */ FALSE
);
986 if (reg
== PARSE_FAIL
)
997 static inline bfd_boolean
998 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1002 && e1
.defined
== e2
.defined
1003 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1006 /* This function parses the NEON register list. On success, it returns
1007 the parsed register list information in the following encoded format:
1009 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1010 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1012 The information of the register shape and/or index is returned in
1015 It returns PARSE_FAIL if the register list is invalid.
1017 The list contains one to four registers.
1018 Each register can be one of:
1021 All <T> should be identical.
1022 All <index> should be identical.
1023 There are restrictions on <Vt> numbers which are checked later
1024 (by reg_list_valid_p). */
1027 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1031 struct neon_type_el typeinfo
, typeinfo_first
;
1036 bfd_boolean error
= FALSE
;
1037 bfd_boolean expect_index
= FALSE
;
1041 set_syntax_error (_("expecting {"));
1047 typeinfo_first
.defined
= 0;
1048 typeinfo_first
.type
= NT_invtype
;
1049 typeinfo_first
.width
= -1;
1050 typeinfo_first
.index
= 0;
1059 str
++; /* skip over '-' */
1062 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1063 /*in_reg_list= */ TRUE
);
1064 if (val
== PARSE_FAIL
)
1066 set_first_syntax_error (_("invalid vector register in list"));
1070 /* reject [bhsd]n */
1071 if (typeinfo
.defined
== 0)
1073 set_first_syntax_error (_("invalid scalar register in list"));
1078 if (typeinfo
.defined
& NTA_HASINDEX
)
1079 expect_index
= TRUE
;
1083 if (val
< val_range
)
1085 set_first_syntax_error
1086 (_("invalid range in vector register list"));
1095 typeinfo_first
= typeinfo
;
1096 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1098 set_first_syntax_error
1099 (_("type mismatch in vector register list"));
1104 for (i
= val_range
; i
<= val
; i
++)
1106 ret_val
|= i
<< (5 * nb_regs
);
1111 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1113 skip_whitespace (str
);
1116 set_first_syntax_error (_("end of vector register list not found"));
1121 skip_whitespace (str
);
1125 if (skip_past_char (&str
, '['))
1129 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1130 if (exp
.X_op
!= O_constant
)
1132 set_first_syntax_error (_("constant expression required."));
1135 if (! skip_past_char (&str
, ']'))
1138 typeinfo_first
.index
= exp
.X_add_number
;
1142 set_first_syntax_error (_("expected index"));
1149 set_first_syntax_error (_("too many registers in vector register list"));
1152 else if (nb_regs
== 0)
1154 set_first_syntax_error (_("empty vector register list"));
1160 *vectype
= typeinfo_first
;
1162 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1165 /* Directives: register aliases. */
1168 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1173 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1176 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1179 /* Only warn about a redefinition if it's not defined as the
1181 else if (new->number
!= number
|| new->type
!= type
)
1182 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1187 name
= xstrdup (str
);
1188 new = xmalloc (sizeof (reg_entry
));
1191 new->number
= number
;
1193 new->builtin
= FALSE
;
1195 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1201 /* Look for the .req directive. This is of the form:
1203 new_register_name .req existing_register_name
1205 If we find one, or if it looks sufficiently like one that we want to
1206 handle any error here, return TRUE. Otherwise return FALSE. */
1209 create_register_alias (char *newname
, char *p
)
1211 const reg_entry
*old
;
1212 char *oldname
, *nbuf
;
1215 /* The input scrubber ensures that whitespace after the mnemonic is
1216 collapsed to single spaces. */
1218 if (strncmp (oldname
, " .req ", 6) != 0)
1222 if (*oldname
== '\0')
1225 old
= hash_find (aarch64_reg_hsh
, oldname
);
1228 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1232 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1233 the desired alias name, and p points to its end. If not, then
1234 the desired alias name is in the global original_case_string. */
1235 #ifdef TC_CASE_SENSITIVE
1238 newname
= original_case_string
;
1239 nlen
= strlen (newname
);
1242 nbuf
= alloca (nlen
+ 1);
1243 memcpy (nbuf
, newname
, nlen
);
1246 /* Create aliases under the new name as stated; an all-lowercase
1247 version of the new name; and an all-uppercase version of the new
1249 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1256 /* If this attempt to create an additional alias fails, do not bother
1257 trying to create the all-lower case alias. We will fail and issue
1258 a second, duplicate error message. This situation arises when the
1259 programmer does something like:
1262 The second .req creates the "Foo" alias but then fails to create
1263 the artificial FOO alias because it has already been created by the
1265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1269 for (p
= nbuf
; *p
; p
++)
1272 if (strncmp (nbuf
, newname
, nlen
))
1273 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1279 /* Should never be called, as .req goes between the alias and the
1280 register name, not at the beginning of the line. */
1282 s_req (int a ATTRIBUTE_UNUSED
)
1284 as_bad (_("invalid syntax for .req directive"));
1287 /* The .unreq directive deletes an alias which was previously defined
1288 by .req. For example:
1294 s_unreq (int a ATTRIBUTE_UNUSED
)
1299 name
= input_line_pointer
;
1301 while (*input_line_pointer
!= 0
1302 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1303 ++input_line_pointer
;
1305 saved_char
= *input_line_pointer
;
1306 *input_line_pointer
= 0;
1309 as_bad (_("invalid syntax for .unreq directive"));
1312 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1315 as_bad (_("unknown register alias '%s'"), name
);
1316 else if (reg
->builtin
)
1317 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1324 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1325 free ((char *) reg
->name
);
1328 /* Also locate the all upper case and all lower case versions.
1329 Do not complain if we cannot find one or the other as it
1330 was probably deleted above. */
1332 nbuf
= strdup (name
);
1333 for (p
= nbuf
; *p
; p
++)
1335 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1338 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1339 free ((char *) reg
->name
);
1343 for (p
= nbuf
; *p
; p
++)
1345 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1348 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1349 free ((char *) reg
->name
);
1357 *input_line_pointer
= saved_char
;
1358 demand_empty_rest_of_line ();
1361 /* Directives: Instruction set selection. */
1364 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1365 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1366 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1367 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1369 /* Create a new mapping symbol for the transition to STATE. */
1372 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1375 const char *symname
;
1382 type
= BSF_NO_FLAGS
;
1386 type
= BSF_NO_FLAGS
;
1392 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1393 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1395 /* Save the mapping symbols for future reference. Also check that
1396 we do not place two mapping symbols at the same offset within a
1397 frag. We'll handle overlap between frags in
1398 check_mapping_symbols.
1400 If .fill or other data filling directive generates zero sized data,
1401 the mapping symbol for the following code will have the same value
1402 as the one generated for the data filling directive. In this case,
1403 we replace the old symbol with the new one at the same address. */
1406 if (frag
->tc_frag_data
.first_map
!= NULL
)
1408 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1409 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1412 frag
->tc_frag_data
.first_map
= symbolP
;
1414 if (frag
->tc_frag_data
.last_map
!= NULL
)
1416 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1417 S_GET_VALUE (symbolP
));
1418 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1419 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1422 frag
->tc_frag_data
.last_map
= symbolP
;
1425 /* We must sometimes convert a region marked as code to data during
1426 code alignment, if an odd number of bytes have to be padded. The
1427 code mapping symbol is pushed to an aligned address. */
1430 insert_data_mapping_symbol (enum mstate state
,
1431 valueT value
, fragS
* frag
, offsetT bytes
)
1433 /* If there was already a mapping symbol, remove it. */
1434 if (frag
->tc_frag_data
.last_map
!= NULL
1435 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1436 frag
->fr_address
+ value
)
1438 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1442 know (frag
->tc_frag_data
.first_map
== symp
);
1443 frag
->tc_frag_data
.first_map
= NULL
;
1445 frag
->tc_frag_data
.last_map
= NULL
;
1446 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1449 make_mapping_symbol (MAP_DATA
, value
, frag
);
1450 make_mapping_symbol (state
, value
+ bytes
, frag
);
1453 static void mapping_state_2 (enum mstate state
, int max_chars
);
1455 /* Set the mapping state to STATE. Only call this when about to
1456 emit some STATE bytes to the file. */
1459 mapping_state (enum mstate state
)
1461 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1463 if (state
== MAP_INSN
)
1464 /* AArch64 instructions require 4-byte alignment. When emitting
1465 instructions into any section, record the appropriate section
1467 record_alignment (now_seg
, 2);
1469 if (mapstate
== state
)
1470 /* The mapping symbol has already been emitted.
1471 There is nothing else to do. */
1474 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1475 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1476 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1477 evaluated later in the next else. */
1479 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1481 /* Only add the symbol if the offset is > 0:
1482 if we're at the first frag, check it's size > 0;
1483 if we're not at the first frag, then for sure
1484 the offset is > 0. */
1485 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1486 const int add_symbol
= (frag_now
!= frag_first
)
1487 || (frag_now_fix () > 0);
1490 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1494 mapping_state_2 (state
, 0);
1497 /* Same as mapping_state, but MAX_CHARS bytes have already been
1498 allocated. Put the mapping symbol that far back. */
1501 mapping_state_2 (enum mstate state
, int max_chars
)
1503 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1505 if (!SEG_NORMAL (now_seg
))
1508 if (mapstate
== state
)
1509 /* The mapping symbol has already been emitted.
1510 There is nothing else to do. */
1513 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1514 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1517 #define mapping_state(x) /* nothing */
1518 #define mapping_state_2(x, y) /* nothing */
1521 /* Directives: sectioning and alignment. */
1524 s_bss (int ignore ATTRIBUTE_UNUSED
)
1526 /* We don't support putting frags in the BSS segment, we fake it by
1527 marking in_bss, then looking at s_skip for clues. */
1528 subseg_set (bss_section
, 0);
1529 demand_empty_rest_of_line ();
1530 mapping_state (MAP_DATA
);
1534 s_even (int ignore ATTRIBUTE_UNUSED
)
1536 /* Never make frag if expect extra pass. */
1538 frag_align (1, 0, 0);
1540 record_alignment (now_seg
, 1);
1542 demand_empty_rest_of_line ();
1545 /* Directives: Literal pools. */
1547 static literal_pool
*
1548 find_literal_pool (int size
)
1552 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1554 if (pool
->section
== now_seg
1555 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1562 static literal_pool
*
1563 find_or_make_literal_pool (int size
)
1565 /* Next literal pool ID number. */
1566 static unsigned int latest_pool_num
= 1;
1569 pool
= find_literal_pool (size
);
1573 /* Create a new pool. */
1574 pool
= xmalloc (sizeof (*pool
));
1578 /* Currently we always put the literal pool in the current text
1579 section. If we were generating "small" model code where we
1580 knew that all code and initialised data was within 1MB then
1581 we could output literals to mergeable, read-only data
1584 pool
->next_free_entry
= 0;
1585 pool
->section
= now_seg
;
1586 pool
->sub_section
= now_subseg
;
1588 pool
->next
= list_of_pools
;
1589 pool
->symbol
= NULL
;
1591 /* Add it to the list. */
1592 list_of_pools
= pool
;
1595 /* New pools, and emptied pools, will have a NULL symbol. */
1596 if (pool
->symbol
== NULL
)
1598 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1599 (valueT
) 0, &zero_address_frag
);
1600 pool
->id
= latest_pool_num
++;
1607 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1608 Return TRUE on success, otherwise return FALSE. */
1610 add_to_lit_pool (expressionS
*exp
, int size
)
1615 pool
= find_or_make_literal_pool (size
);
1617 /* Check if this literal value is already in the pool. */
1618 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1620 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1622 if ((litexp
->X_op
== exp
->X_op
)
1623 && (exp
->X_op
== O_constant
)
1624 && (litexp
->X_add_number
== exp
->X_add_number
)
1625 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1628 if ((litexp
->X_op
== exp
->X_op
)
1629 && (exp
->X_op
== O_symbol
)
1630 && (litexp
->X_add_number
== exp
->X_add_number
)
1631 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1632 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1636 /* Do we need to create a new entry? */
1637 if (entry
== pool
->next_free_entry
)
1639 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1641 set_syntax_error (_("literal pool overflow"));
1645 pool
->literals
[entry
].exp
= *exp
;
1646 pool
->next_free_entry
+= 1;
1647 if (exp
->X_op
== O_big
)
1649 /* PR 16688: Bignums are held in a single global array. We must
1650 copy and preserve that value now, before it is overwritten. */
1651 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1652 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1653 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1656 pool
->literals
[entry
].bignum
= NULL
;
1659 exp
->X_op
= O_symbol
;
1660 exp
->X_add_number
= ((int) entry
) * size
;
1661 exp
->X_add_symbol
= pool
->symbol
;
1666 /* Can't use symbol_new here, so have to create a symbol and then at
1667 a later date assign it a value. Thats what these functions do. */
1670 symbol_locate (symbolS
* symbolP
,
1671 const char *name
,/* It is copied, the caller can modify. */
1672 segT segment
, /* Segment identifier (SEG_<something>). */
1673 valueT valu
, /* Symbol value. */
1674 fragS
* frag
) /* Associated fragment. */
1677 char *preserved_copy_of_name
;
1679 name_length
= strlen (name
) + 1; /* +1 for \0. */
1680 obstack_grow (¬es
, name
, name_length
);
1681 preserved_copy_of_name
= obstack_finish (¬es
);
1683 #ifdef tc_canonicalize_symbol_name
1684 preserved_copy_of_name
=
1685 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1688 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1690 S_SET_SEGMENT (symbolP
, segment
);
1691 S_SET_VALUE (symbolP
, valu
);
1692 symbol_clear_list_pointers (symbolP
);
1694 symbol_set_frag (symbolP
, frag
);
1696 /* Link to end of symbol chain. */
1698 extern int symbol_table_frozen
;
1700 if (symbol_table_frozen
)
1704 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1706 obj_symbol_new_hook (symbolP
);
1708 #ifdef tc_symbol_new_hook
1709 tc_symbol_new_hook (symbolP
);
1713 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1714 #endif /* DEBUG_SYMS */
1719 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1726 for (align
= 2; align
<= 4; align
++)
1728 int size
= 1 << align
;
1730 pool
= find_literal_pool (size
);
1731 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1734 mapping_state (MAP_DATA
);
1736 /* Align pool as you have word accesses.
1737 Only make a frag if we have to. */
1739 frag_align (align
, 0, 0);
1741 record_alignment (now_seg
, align
);
1743 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1745 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1746 (valueT
) frag_now_fix (), frag_now
);
1747 symbol_table_insert (pool
->symbol
);
1749 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1751 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1753 if (exp
->X_op
== O_big
)
1755 /* PR 16688: Restore the global bignum value. */
1756 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1757 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1758 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1761 /* First output the expression in the instruction to the pool. */
1762 emit_expr (exp
, size
); /* .word|.xword */
1764 if (exp
->X_op
== O_big
)
1766 free (pool
->literals
[entry
].bignum
);
1767 pool
->literals
[entry
].bignum
= NULL
;
1771 /* Mark the pool as empty. */
1772 pool
->next_free_entry
= 0;
1773 pool
->symbol
= NULL
;
1778 /* Forward declarations for functions below, in the MD interface
1780 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1781 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1783 /* Directives: Data. */
1784 /* N.B. the support for relocation suffix in this directive needs to be
1785 implemented properly. */
1788 s_aarch64_elf_cons (int nbytes
)
1792 #ifdef md_flush_pending_output
1793 md_flush_pending_output ();
1796 if (is_it_end_of_statement ())
1798 demand_empty_rest_of_line ();
1802 #ifdef md_cons_align
1803 md_cons_align (nbytes
);
1806 mapping_state (MAP_DATA
);
1809 struct reloc_table_entry
*reloc
;
1813 if (exp
.X_op
!= O_symbol
)
1814 emit_expr (&exp
, (unsigned int) nbytes
);
1817 skip_past_char (&input_line_pointer
, '#');
1818 if (skip_past_char (&input_line_pointer
, ':'))
1820 reloc
= find_reloc_table_entry (&input_line_pointer
);
1822 as_bad (_("unrecognized relocation suffix"));
1824 as_bad (_("unimplemented relocation suffix"));
1825 ignore_rest_of_line ();
1829 emit_expr (&exp
, (unsigned int) nbytes
);
1832 while (*input_line_pointer
++ == ',');
1834 /* Put terminator back into stream. */
1835 input_line_pointer
--;
1836 demand_empty_rest_of_line ();
1839 #endif /* OBJ_ELF */
1841 /* Output a 32-bit word, but mark as an instruction. */
1844 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1848 #ifdef md_flush_pending_output
1849 md_flush_pending_output ();
1852 if (is_it_end_of_statement ())
1854 demand_empty_rest_of_line ();
1858 /* Sections are assumed to start aligned. In executable section, there is no
1859 MAP_DATA symbol pending. So we only align the address during
1860 MAP_DATA --> MAP_INSN transition.
1861 For other sections, this is not guaranteed. */
1862 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1863 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1864 frag_align_code (2, 0);
1867 mapping_state (MAP_INSN
);
1873 if (exp
.X_op
!= O_constant
)
1875 as_bad (_("constant expression required"));
1876 ignore_rest_of_line ();
1880 if (target_big_endian
)
1882 unsigned int val
= exp
.X_add_number
;
1883 exp
.X_add_number
= SWAP_32 (val
);
1885 emit_expr (&exp
, 4);
1887 while (*input_line_pointer
++ == ',');
1889 /* Put terminator back into stream. */
1890 input_line_pointer
--;
1891 demand_empty_rest_of_line ();
1895 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1898 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1902 /* Since we're just labelling the code, there's no need to define a
1905 /* Make sure there is enough room in this frag for the following
1906 blr. This trick only works if the blr follows immediately after
1907 the .tlsdesc directive. */
1909 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1910 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1912 demand_empty_rest_of_line ();
1914 #endif /* OBJ_ELF */
1916 static void s_aarch64_arch (int);
1917 static void s_aarch64_cpu (int);
1918 static void s_aarch64_arch_extension (int);
1920 /* This table describes all the machine specific pseudo-ops the assembler
1921 has to support. The fields are:
1922 pseudo-op name without dot
1923 function to call to execute this pseudo-op
1924 Integer arg to pass to the function. */
1926 const pseudo_typeS md_pseudo_table
[] = {
1927 /* Never called because '.req' does not start a line. */
1929 {"unreq", s_unreq
, 0},
1931 {"even", s_even
, 0},
1932 {"ltorg", s_ltorg
, 0},
1933 {"pool", s_ltorg
, 0},
1934 {"cpu", s_aarch64_cpu
, 0},
1935 {"arch", s_aarch64_arch
, 0},
1936 {"arch_extension", s_aarch64_arch_extension
, 0},
1937 {"inst", s_aarch64_inst
, 0},
1939 {"tlsdesccall", s_tlsdesccall
, 0},
1940 {"word", s_aarch64_elf_cons
, 4},
1941 {"long", s_aarch64_elf_cons
, 4},
1942 {"xword", s_aarch64_elf_cons
, 8},
1943 {"dword", s_aarch64_elf_cons
, 8},
1949 /* Check whether STR points to a register name followed by a comma or the
1950 end of line; REG_TYPE indicates which register types are checked
1951 against. Return TRUE if STR is such a register name; otherwise return
1952 FALSE. The function does not intend to produce any diagnostics, but since
1953 the register parser aarch64_reg_parse, which is called by this function,
1954 does produce diagnostics, we call clear_error to clear any diagnostics
1955 that may be generated by aarch64_reg_parse.
1956 Also, the function returns FALSE directly if there is any user error
1957 present at the function entry. This prevents the existing diagnostics
1958 state from being spoiled.
1959 The function currently serves parse_constant_immediate and
1960 parse_big_immediate only. */
1962 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1966 /* Prevent the diagnostics state from being spoiled. */
1970 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1972 /* Clear the parsing error that may be set by the reg parser. */
1975 if (reg
== PARSE_FAIL
)
1978 skip_whitespace (str
);
1979 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1985 /* Parser functions used exclusively in instruction operands. */
1987 /* Parse an immediate expression which may not be constant.
1989 To prevent the expression parser from pushing a register name
1990 into the symbol table as an undefined symbol, firstly a check is
1991 done to find out whether STR is a valid register name followed
1992 by a comma or the end of line. Return FALSE if STR is such a
1996 parse_immediate_expression (char **str
, expressionS
*exp
)
1998 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2000 set_recoverable_error (_("immediate operand required"));
2004 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2006 if (exp
->X_op
== O_absent
)
2008 set_fatal_syntax_error (_("missing immediate expression"));
2015 /* Constant immediate-value read function for use in insn parsing.
2016 STR points to the beginning of the immediate (with the optional
2017 leading #); *VAL receives the value.
2019 Return TRUE on success; otherwise return FALSE. */
2022 parse_constant_immediate (char **str
, int64_t * val
)
2026 if (! parse_immediate_expression (str
, &exp
))
2029 if (exp
.X_op
!= O_constant
)
2031 set_syntax_error (_("constant expression required"));
2035 *val
= exp
.X_add_number
;
2040 encode_imm_float_bits (uint32_t imm
)
2042 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2043 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2046 /* Return TRUE if the single-precision floating-point value encoded in IMM
2047 can be expressed in the AArch64 8-bit signed floating-point format with
2048 3-bit exponent and normalized 4 bits of precision; in other words, the
2049 floating-point value must be expressable as
2050 (+/-) n / 16 * power (2, r)
2051 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2054 aarch64_imm_float_p (uint32_t imm
)
2056 /* If a single-precision floating-point value has the following bit
2057 pattern, it can be expressed in the AArch64 8-bit floating-point
2060 3 32222222 2221111111111
2061 1 09876543 21098765432109876543210
2062 n Eeeeeexx xxxx0000000000000000000
2064 where n, e and each x are either 0 or 1 independently, with
2069 /* Prepare the pattern for 'Eeeeee'. */
2070 if (((imm
>> 30) & 0x1) == 0)
2071 pattern
= 0x3e000000;
2073 pattern
= 0x40000000;
2075 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2076 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2079 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2081 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2082 8-bit signed floating-point format with 3-bit exponent and normalized 4
2083 bits of precision (i.e. can be used in an FMOV instruction); return the
2084 equivalent single-precision encoding in *FPWORD.
2086 Otherwise return FALSE. */
2089 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2091 /* If a double-precision floating-point value has the following bit
2092 pattern, it can be expressed in the AArch64 8-bit floating-point
2095 6 66655555555 554444444...21111111111
2096 3 21098765432 109876543...098765432109876543210
2097 n Eeeeeeeeexx xxxx00000...000000000000000000000
2099 where n, e and each x are either 0 or 1 independently, with
2103 uint32_t high32
= imm
>> 32;
2105 /* Lower 32 bits need to be 0s. */
2106 if ((imm
& 0xffffffff) != 0)
2109 /* Prepare the pattern for 'Eeeeeeeee'. */
2110 if (((high32
>> 30) & 0x1) == 0)
2111 pattern
= 0x3fc00000;
2113 pattern
= 0x40000000;
2115 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2116 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2118 /* Convert to the single-precision encoding.
2120 n Eeeeeeeeexx xxxx00000...000000000000000000000
2122 n Eeeeeexx xxxx0000000000000000000. */
2123 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2124 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2131 /* Parse a floating-point immediate. Return TRUE on success and return the
2132 value in *IMMED in the format of IEEE754 single-precision encoding.
2133 *CCP points to the start of the string; DP_P is TRUE when the immediate
2134 is expected to be in double-precision (N.B. this only matters when
2135 hexadecimal representation is involved).
2137 N.B. 0.0 is accepted by this function. */
2140 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2144 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2145 int found_fpchar
= 0;
2147 unsigned fpword
= 0;
2148 bfd_boolean hex_p
= FALSE
;
2150 skip_past_char (&str
, '#');
2153 skip_whitespace (fpnum
);
2155 if (strncmp (fpnum
, "0x", 2) == 0)
2157 /* Support the hexadecimal representation of the IEEE754 encoding.
2158 Double-precision is expected when DP_P is TRUE, otherwise the
2159 representation should be in single-precision. */
2160 if (! parse_constant_immediate (&str
, &val
))
2165 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2168 else if ((uint64_t) val
> 0xffffffff)
2177 /* We must not accidentally parse an integer as a floating-point number.
2178 Make sure that the value we parse is not an integer by checking for
2179 special characters '.' or 'e'. */
2180 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2181 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2195 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2198 /* Our FP word must be 32 bits (single-precision FP). */
2199 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2201 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2206 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2214 set_fatal_syntax_error (_("invalid floating-point constant"));
2218 /* Less-generic immediate-value read function with the possibility of loading
2219 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2222 To prevent the expression parser from pushing a register name into the
2223 symbol table as an undefined symbol, a check is firstly done to find
2224 out whether STR is a valid register name followed by a comma or the end
2225 of line. Return FALSE if STR is such a register. */
2228 parse_big_immediate (char **str
, int64_t *imm
)
2232 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2234 set_syntax_error (_("immediate operand required"));
2238 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2240 if (inst
.reloc
.exp
.X_op
== O_constant
)
2241 *imm
= inst
.reloc
.exp
.X_add_number
;
2248 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2249 if NEED_LIBOPCODES is non-zero, the fixup will need
2250 assistance from the libopcodes. */
2253 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2254 const aarch64_opnd_info
*operand
,
2255 int need_libopcodes_p
)
2257 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2258 reloc
->opnd
= operand
->type
;
2259 if (need_libopcodes_p
)
2260 reloc
->need_libopcodes_p
= 1;
2263 /* Return TRUE if the instruction needs to be fixed up later internally by
2264 the GAS; otherwise return FALSE. */
2266 static inline bfd_boolean
2267 aarch64_gas_internal_fixup_p (void)
2269 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2272 /* Assign the immediate value to the relavant field in *OPERAND if
2273 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2274 needs an internal fixup in a later stage.
2275 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2276 IMM.VALUE that may get assigned with the constant. */
2278 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2279 aarch64_opnd_info
*operand
,
2281 int need_libopcodes_p
,
2284 if (reloc
->exp
.X_op
== O_constant
)
2287 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2289 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2290 reloc
->type
= BFD_RELOC_UNUSED
;
2294 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2295 /* Tell libopcodes to ignore this operand or not. This is helpful
2296 when one of the operands needs to be fixed up later but we need
2297 libopcodes to check the other operands. */
2298 operand
->skip
= skip_p
;
2302 /* Relocation modifiers. Each entry in the table contains the textual
2303 name for the relocation which may be placed before a symbol used as
2304 a load/store offset, or add immediate. It must be surrounded by a
2305 leading and trailing colon, for example:
2307 ldr x0, [x1, #:rello:varsym]
2308 add x0, x1, #:rello:varsym */
2310 struct reloc_table_entry
2314 bfd_reloc_code_real_type adr_type
;
2315 bfd_reloc_code_real_type adrp_type
;
2316 bfd_reloc_code_real_type movw_type
;
2317 bfd_reloc_code_real_type add_type
;
2318 bfd_reloc_code_real_type ldst_type
;
2319 bfd_reloc_code_real_type ld_literal_type
;
2322 static struct reloc_table_entry reloc_table
[] = {
2323 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2328 BFD_RELOC_AARCH64_ADD_LO12
,
2329 BFD_RELOC_AARCH64_LDST_LO12
,
2332 /* Higher 21 bits of pc-relative page offset: ADRP */
2335 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2341 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2344 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2350 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2354 BFD_RELOC_AARCH64_MOVW_G0
,
2359 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2363 BFD_RELOC_AARCH64_MOVW_G0_S
,
2368 /* Less significant bits 0-15 of address/value: MOVK, no check */
2372 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2377 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2381 BFD_RELOC_AARCH64_MOVW_G1
,
2386 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2390 BFD_RELOC_AARCH64_MOVW_G1_S
,
2395 /* Less significant bits 16-31 of address/value: MOVK, no check */
2399 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2404 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2408 BFD_RELOC_AARCH64_MOVW_G2
,
2413 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2417 BFD_RELOC_AARCH64_MOVW_G2_S
,
2422 /* Less significant bits 32-47 of address/value: MOVK, no check */
2426 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2431 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2435 BFD_RELOC_AARCH64_MOVW_G3
,
2440 /* Get to the page containing GOT entry for a symbol. */
2443 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2447 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2449 /* 12 bit offset into the page containing GOT entry for that symbol. */
2455 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2458 /* 15 bit offset into the page containing GOT entry for that symbol. */
2464 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2467 /* Get to the page containing GOT TLS entry for a symbol */
2469 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2470 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2476 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2481 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2485 /* Get to the page containing GOT TLS entry for a symbol */
2487 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2488 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2492 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2494 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2499 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2500 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2503 /* Get to the page containing GOT TLS entry for a symbol.
2504 The same as GD, we allocate two consecutive GOT slots
2505 for module index and module offset, the only difference
2506 with GD is the module offset should be intialized to
2507 zero without any outstanding runtime relocation. */
2509 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2510 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2516 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2517 {"tlsldm_lo12_nc", 0,
2521 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2525 /* 12 bit offset into the module TLS base address. */
2530 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2531 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2534 /* Same as dtprel_lo12, no overflow check. */
2535 {"dtprel_lo12_nc", 0,
2539 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2540 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2543 /* bits[23:12] of offset to the module TLS base address. */
2548 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2552 /* bits[15:0] of offset to the module TLS base address. */
2556 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2561 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2565 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2570 /* bits[31:16] of offset to the module TLS base address. */
2574 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2579 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2583 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2588 /* bits[47:32] of offset to the module TLS base address. */
2592 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2597 /* Get to the page containing GOT TLS entry for a symbol */
2600 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2604 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2606 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2607 {"gottprel_lo12", 0,
2612 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2615 /* Get tp offset for a symbol. */
2620 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2624 /* Get tp offset for a symbol. */
2629 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2633 /* Get tp offset for a symbol. */
2638 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2642 /* Get tp offset for a symbol. */
2643 {"tprel_lo12_nc", 0,
2647 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2651 /* Most significant bits 32-47 of address/value: MOVZ. */
2655 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2660 /* Most significant bits 16-31 of address/value: MOVZ. */
2664 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2669 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2673 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2678 /* Most significant bits 0-15 of address/value: MOVZ. */
2682 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2687 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2691 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2696 /* 15bit offset from got entry to base address of GOT table. */
2702 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2705 /* 14bit offset from got entry to base address of GOT table. */
2711 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2715 /* Given the address of a pointer pointing to the textual name of a
2716 relocation as may appear in assembler source, attempt to find its
2717 details in reloc_table. The pointer will be updated to the character
2718 after the trailing colon. On failure, NULL will be returned;
2719 otherwise return the reloc_table_entry. */
2721 static struct reloc_table_entry
*
2722 find_reloc_table_entry (char **str
)
2725 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2727 int length
= strlen (reloc_table
[i
].name
);
2729 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2730 && (*str
)[length
] == ':')
2732 *str
+= (length
+ 1);
2733 return &reloc_table
[i
];
2740 /* Mode argument to parse_shift and parser_shifter_operand. */
2741 enum parse_shift_mode
2743 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2745 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2747 SHIFTED_LSL
, /* bare "lsl #n" */
2748 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2749 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2752 /* Parse a <shift> operator on an AArch64 data processing instruction.
2753 Return TRUE on success; otherwise return FALSE. */
2755 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2757 const struct aarch64_name_value_pair
*shift_op
;
2758 enum aarch64_modifier_kind kind
;
2764 for (p
= *str
; ISALPHA (*p
); p
++)
2769 set_syntax_error (_("shift expression expected"));
2773 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2775 if (shift_op
== NULL
)
2777 set_syntax_error (_("shift operator expected"));
2781 kind
= aarch64_get_operand_modifier (shift_op
);
2783 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2785 set_syntax_error (_("invalid use of 'MSL'"));
2791 case SHIFTED_LOGIC_IMM
:
2792 if (aarch64_extend_operator_p (kind
) == TRUE
)
2794 set_syntax_error (_("extending shift is not permitted"));
2799 case SHIFTED_ARITH_IMM
:
2800 if (kind
== AARCH64_MOD_ROR
)
2802 set_syntax_error (_("'ROR' shift is not permitted"));
2808 if (kind
!= AARCH64_MOD_LSL
)
2810 set_syntax_error (_("only 'LSL' shift is permitted"));
2815 case SHIFTED_REG_OFFSET
:
2816 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2817 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2819 set_fatal_syntax_error
2820 (_("invalid shift for the register offset addressing mode"));
2825 case SHIFTED_LSL_MSL
:
2826 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2828 set_syntax_error (_("invalid shift operator"));
2837 /* Whitespace can appear here if the next thing is a bare digit. */
2838 skip_whitespace (p
);
2840 /* Parse shift amount. */
2842 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2843 exp
.X_op
= O_absent
;
2846 if (is_immediate_prefix (*p
))
2851 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2853 if (exp
.X_op
== O_absent
)
2855 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2857 set_syntax_error (_("missing shift amount"));
2860 operand
->shifter
.amount
= 0;
2862 else if (exp
.X_op
!= O_constant
)
2864 set_syntax_error (_("constant shift amount required"));
2867 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2869 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2874 operand
->shifter
.amount
= exp
.X_add_number
;
2875 operand
->shifter
.amount_present
= 1;
2878 operand
->shifter
.operator_present
= 1;
2879 operand
->shifter
.kind
= kind
;
2885 /* Parse a <shifter_operand> for a data processing instruction:
2888 #<immediate>, LSL #imm
2890 Validation of immediate operands is deferred to md_apply_fix.
2892 Return TRUE on success; otherwise return FALSE. */
2895 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2896 enum parse_shift_mode mode
)
2900 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2905 /* Accept an immediate expression. */
2906 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2909 /* Accept optional LSL for arithmetic immediate values. */
2910 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2911 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2914 /* Not accept any shifter for logical immediate values. */
2915 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2916 && parse_shift (&p
, operand
, mode
))
2918 set_syntax_error (_("unexpected shift operator"));
2926 /* Parse a <shifter_operand> for a data processing instruction:
2931 #<immediate>, LSL #imm
2933 where <shift> is handled by parse_shift above, and the last two
2934 cases are handled by the function above.
2936 Validation of immediate operands is deferred to md_apply_fix.
2938 Return TRUE on success; otherwise return FALSE. */
2941 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2942 enum parse_shift_mode mode
)
2945 int isreg32
, isregzero
;
2946 enum aarch64_operand_class opd_class
2947 = aarch64_get_operand_class (operand
->type
);
2950 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2952 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2954 set_syntax_error (_("unexpected register in the immediate operand"));
2958 if (!isregzero
&& reg
== REG_SP
)
2960 set_syntax_error (BAD_SP
);
2964 operand
->reg
.regno
= reg
;
2965 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2967 /* Accept optional shift operation on register. */
2968 if (! skip_past_comma (str
))
2971 if (! parse_shift (str
, operand
, mode
))
2976 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2979 (_("integer register expected in the extended/shifted operand "
2984 /* We have a shifted immediate variable. */
2985 return parse_shifter_operand_imm (str
, operand
, mode
);
2988 /* Return TRUE on success; return FALSE otherwise. */
2991 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
2992 enum parse_shift_mode mode
)
2996 /* Determine if we have the sequence of characters #: or just :
2997 coming next. If we do, then we check for a :rello: relocation
2998 modifier. If we don't, punt the whole lot to
2999 parse_shifter_operand. */
3001 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3003 struct reloc_table_entry
*entry
;
3011 /* Try to parse a relocation. Anything else is an error. */
3012 if (!(entry
= find_reloc_table_entry (str
)))
3014 set_syntax_error (_("unknown relocation modifier"));
3018 if (entry
->add_type
== 0)
3021 (_("this relocation modifier is not allowed on this instruction"));
3025 /* Save str before we decompose it. */
3028 /* Next, we parse the expression. */
3029 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3032 /* Record the relocation type (use the ADD variant here). */
3033 inst
.reloc
.type
= entry
->add_type
;
3034 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3036 /* If str is empty, we've reached the end, stop here. */
3040 /* Otherwise, we have a shifted reloc modifier, so rewind to
3041 recover the variable name and continue parsing for the shifter. */
3043 return parse_shifter_operand_imm (str
, operand
, mode
);
3046 return parse_shifter_operand (str
, operand
, mode
);
3049 /* Parse all forms of an address expression. Information is written
3050 to *OPERAND and/or inst.reloc.
3052 The A64 instruction set has the following addressing modes:
3055 [base] // in SIMD ld/st structure
3056 [base{,#0}] // in ld/st exclusive
3058 [base,Xm{,LSL #imm}]
3059 [base,Xm,SXTX {#imm}]
3060 [base,Wm,(S|U)XTW {#imm}]
3065 [base],Xm // in SIMD ld/st structure
3066 PC-relative (literal)
3070 (As a convenience, the notation "=immediate" is permitted in conjunction
3071 with the pc-relative literal load instructions to automatically place an
3072 immediate value or symbolic address in a nearby literal pool and generate
3073 a hidden label which references it.)
3075 Upon a successful parsing, the address structure in *OPERAND will be
3076 filled in the following way:
3078 .base_regno = <base>
3079 .offset.is_reg // 1 if the offset is a register
3081 .offset.regno = <Rm>
3083 For different addressing modes defined in the A64 ISA:
3086 .pcrel=0; .preind=1; .postind=0; .writeback=0
3088 .pcrel=0; .preind=1; .postind=0; .writeback=1
3090 .pcrel=0; .preind=0; .postind=1; .writeback=1
3091 PC-relative (literal)
3092 .pcrel=1; .preind=1; .postind=0; .writeback=0
3094 The shift/extension information, if any, will be stored in .shifter.
3096 It is the caller's responsibility to check for addressing modes not
3097 supported by the instruction, and to set inst.reloc.type. */
3100 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3101 int accept_reg_post_index
)
3105 int isreg32
, isregzero
;
3106 expressionS
*exp
= &inst
.reloc
.exp
;
3108 if (! skip_past_char (&p
, '['))
3110 /* =immediate or label. */
3111 operand
->addr
.pcrel
= 1;
3112 operand
->addr
.preind
= 1;
3114 /* #:<reloc_op>:<symbol> */
3115 skip_past_char (&p
, '#');
3116 if (reloc
&& skip_past_char (&p
, ':'))
3118 bfd_reloc_code_real_type ty
;
3119 struct reloc_table_entry
*entry
;
3121 /* Try to parse a relocation modifier. Anything else is
3123 entry
= find_reloc_table_entry (&p
);
3126 set_syntax_error (_("unknown relocation modifier"));
3130 switch (operand
->type
)
3132 case AARCH64_OPND_ADDR_PCREL21
:
3134 ty
= entry
->adr_type
;
3138 ty
= entry
->ld_literal_type
;
3145 (_("this relocation modifier is not allowed on this "
3151 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3153 set_syntax_error (_("invalid relocation expression"));
3157 /* #:<reloc_op>:<expr> */
3158 /* Record the relocation type. */
3159 inst
.reloc
.type
= ty
;
3160 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3165 if (skip_past_char (&p
, '='))
3166 /* =immediate; need to generate the literal in the literal pool. */
3167 inst
.gen_lit_pool
= 1;
3169 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3171 set_syntax_error (_("invalid address"));
3182 /* Accept SP and reject ZR */
3183 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3184 if (reg
== PARSE_FAIL
|| isreg32
)
3186 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3189 operand
->addr
.base_regno
= reg
;
3192 if (skip_past_comma (&p
))
3195 operand
->addr
.preind
= 1;
3197 /* Reject SP and accept ZR */
3198 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3199 if (reg
!= PARSE_FAIL
)
3202 operand
->addr
.offset
.regno
= reg
;
3203 operand
->addr
.offset
.is_reg
= 1;
3204 /* Shifted index. */
3205 if (skip_past_comma (&p
))
3208 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3209 /* Use the diagnostics set in parse_shift, so not set new
3210 error message here. */
3214 [base,Xm{,LSL #imm}]
3215 [base,Xm,SXTX {#imm}]
3216 [base,Wm,(S|U)XTW {#imm}] */
3217 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3218 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3219 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3223 set_syntax_error (_("invalid use of 32-bit register offset"));
3229 set_syntax_error (_("invalid use of 64-bit register offset"));
3235 /* [Xn,#:<reloc_op>:<symbol> */
3236 skip_past_char (&p
, '#');
3237 if (reloc
&& skip_past_char (&p
, ':'))
3239 struct reloc_table_entry
*entry
;
3241 /* Try to parse a relocation modifier. Anything else is
3243 if (!(entry
= find_reloc_table_entry (&p
)))
3245 set_syntax_error (_("unknown relocation modifier"));
3249 if (entry
->ldst_type
== 0)
3252 (_("this relocation modifier is not allowed on this "
3257 /* [Xn,#:<reloc_op>: */
3258 /* We now have the group relocation table entry corresponding to
3259 the name in the assembler source. Next, we parse the
3261 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3263 set_syntax_error (_("invalid relocation expression"));
3267 /* [Xn,#:<reloc_op>:<expr> */
3268 /* Record the load/store relocation type. */
3269 inst
.reloc
.type
= entry
->ldst_type
;
3270 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3272 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3274 set_syntax_error (_("invalid expression in the address"));
3281 if (! skip_past_char (&p
, ']'))
3283 set_syntax_error (_("']' expected"));
3287 if (skip_past_char (&p
, '!'))
3289 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3291 set_syntax_error (_("register offset not allowed in pre-indexed "
3292 "addressing mode"));
3296 operand
->addr
.writeback
= 1;
3298 else if (skip_past_comma (&p
))
3301 operand
->addr
.postind
= 1;
3302 operand
->addr
.writeback
= 1;
3304 if (operand
->addr
.preind
)
3306 set_syntax_error (_("cannot combine pre- and post-indexing"));
3310 if (accept_reg_post_index
3311 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3312 &isregzero
)) != PARSE_FAIL
)
3317 set_syntax_error (_("invalid 32-bit register offset"));
3320 operand
->addr
.offset
.regno
= reg
;
3321 operand
->addr
.offset
.is_reg
= 1;
3323 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3326 set_syntax_error (_("invalid expression in the address"));
3331 /* If at this point neither .preind nor .postind is set, we have a
3332 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3333 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3335 if (operand
->addr
.writeback
)
3338 set_syntax_error (_("missing offset in the pre-indexed address"));
3341 operand
->addr
.preind
= 1;
3342 inst
.reloc
.exp
.X_op
= O_constant
;
3343 inst
.reloc
.exp
.X_add_number
= 0;
3350 /* Return TRUE on success; otherwise return FALSE. */
3352 parse_address (char **str
, aarch64_opnd_info
*operand
,
3353 int accept_reg_post_index
)
3355 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3358 /* Return TRUE on success; otherwise return FALSE. */
3360 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3362 return parse_address_main (str
, operand
, 1, 0);
3365 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3366 Return TRUE on success; otherwise return FALSE. */
3368 parse_half (char **str
, int *internal_fixup_p
)
3374 skip_past_char (&p
, '#');
3376 gas_assert (internal_fixup_p
);
3377 *internal_fixup_p
= 0;
3381 struct reloc_table_entry
*entry
;
3383 /* Try to parse a relocation. Anything else is an error. */
3385 if (!(entry
= find_reloc_table_entry (&p
)))
3387 set_syntax_error (_("unknown relocation modifier"));
3391 if (entry
->movw_type
== 0)
3394 (_("this relocation modifier is not allowed on this instruction"));
3398 inst
.reloc
.type
= entry
->movw_type
;
3401 *internal_fixup_p
= 1;
3403 /* Avoid parsing a register as a general symbol. */
3405 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3409 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3416 /* Parse an operand for an ADRP instruction:
3418 Return TRUE on success; otherwise return FALSE. */
3421 parse_adrp (char **str
)
3428 struct reloc_table_entry
*entry
;
3430 /* Try to parse a relocation. Anything else is an error. */
3432 if (!(entry
= find_reloc_table_entry (&p
)))
3434 set_syntax_error (_("unknown relocation modifier"));
3438 if (entry
->adrp_type
== 0)
3441 (_("this relocation modifier is not allowed on this instruction"));
3445 inst
.reloc
.type
= entry
->adrp_type
;
3448 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3450 inst
.reloc
.pc_rel
= 1;
3452 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3459 /* Miscellaneous. */
3461 /* Parse an option for a preload instruction. Returns the encoding for the
3462 option, or PARSE_FAIL. */
3465 parse_pldop (char **str
)
3468 const struct aarch64_name_value_pair
*o
;
3471 while (ISALNUM (*q
))
3474 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3482 /* Parse an option for a barrier instruction. Returns the encoding for the
3483 option, or PARSE_FAIL. */
3486 parse_barrier (char **str
)
3489 const asm_barrier_opt
*o
;
3492 while (ISALPHA (*q
))
3495 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3503 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3504 Returns the encoding for the option, or PARSE_FAIL.
3506 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3507 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3509 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3510 field, otherwise as a system register.
3514 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3515 int imple_defined_p
, int pstatefield_p
)
3519 const aarch64_sys_reg
*o
;
3523 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3525 *p
++ = TOLOWER (*q
);
3527 /* Assert that BUF be large enough. */
3528 gas_assert (p
- buf
== q
- *str
);
3530 o
= hash_find (sys_regs
, buf
);
3533 if (!imple_defined_p
)
3537 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3538 unsigned int op0
, op1
, cn
, cm
, op2
;
3540 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3543 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3545 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3550 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3551 as_bad (_("selected processor does not support PSTATE field "
3553 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3554 as_bad (_("selected processor does not support system register "
3556 if (aarch64_sys_reg_deprecated_p (o
))
3557 as_warn (_("system register name '%s' is deprecated and may be "
3558 "removed in a future release"), buf
);
3566 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3567 for the option, or NULL. */
3569 static const aarch64_sys_ins_reg
*
3570 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3574 const aarch64_sys_ins_reg
*o
;
3577 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3579 *p
++ = TOLOWER (*q
);
3582 o
= hash_find (sys_ins_regs
, buf
);
3590 #define po_char_or_fail(chr) do { \
3591 if (! skip_past_char (&str, chr)) \
3595 #define po_reg_or_fail(regtype) do { \
3596 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3597 if (val == PARSE_FAIL) \
3599 set_default_error (); \
3604 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3605 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3606 &isreg32, &isregzero); \
3607 if (val == PARSE_FAIL) \
3609 set_default_error (); \
3612 info->reg.regno = val; \
3614 info->qualifier = AARCH64_OPND_QLF_W; \
3616 info->qualifier = AARCH64_OPND_QLF_X; \
3619 #define po_imm_nc_or_fail() do { \
3620 if (! parse_constant_immediate (&str, &val)) \
3624 #define po_imm_or_fail(min, max) do { \
3625 if (! parse_constant_immediate (&str, &val)) \
3627 if (val < min || val > max) \
3629 set_fatal_syntax_error (_("immediate value out of range "\
3630 #min " to "#max)); \
3635 #define po_misc_or_fail(expr) do { \
3640 /* encode the 12-bit imm field of Add/sub immediate */
3641 static inline uint32_t
3642 encode_addsub_imm (uint32_t imm
)
3647 /* encode the shift amount field of Add/sub immediate */
3648 static inline uint32_t
3649 encode_addsub_imm_shift_amount (uint32_t cnt
)
3655 /* encode the imm field of Adr instruction */
3656 static inline uint32_t
3657 encode_adr_imm (uint32_t imm
)
3659 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3660 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3663 /* encode the immediate field of Move wide immediate */
3664 static inline uint32_t
3665 encode_movw_imm (uint32_t imm
)
3670 /* encode the 26-bit offset of unconditional branch */
3671 static inline uint32_t
3672 encode_branch_ofs_26 (uint32_t ofs
)
3674 return ofs
& ((1 << 26) - 1);
3677 /* encode the 19-bit offset of conditional branch and compare & branch */
3678 static inline uint32_t
3679 encode_cond_branch_ofs_19 (uint32_t ofs
)
3681 return (ofs
& ((1 << 19) - 1)) << 5;
3684 /* encode the 19-bit offset of ld literal */
3685 static inline uint32_t
3686 encode_ld_lit_ofs_19 (uint32_t ofs
)
3688 return (ofs
& ((1 << 19) - 1)) << 5;
3691 /* Encode the 14-bit offset of test & branch. */
3692 static inline uint32_t
3693 encode_tst_branch_ofs_14 (uint32_t ofs
)
3695 return (ofs
& ((1 << 14) - 1)) << 5;
3698 /* Encode the 16-bit imm field of svc/hvc/smc. */
3699 static inline uint32_t
3700 encode_svc_imm (uint32_t imm
)
3705 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3706 static inline uint32_t
3707 reencode_addsub_switch_add_sub (uint32_t opcode
)
3709 return opcode
^ (1 << 30);
3712 static inline uint32_t
3713 reencode_movzn_to_movz (uint32_t opcode
)
3715 return opcode
| (1 << 30);
3718 static inline uint32_t
3719 reencode_movzn_to_movn (uint32_t opcode
)
3721 return opcode
& ~(1 << 30);
3724 /* Overall per-instruction processing. */
3726 /* We need to be able to fix up arbitrary expressions in some statements.
3727 This is so that we can handle symbols that are an arbitrary distance from
3728 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3729 which returns part of an address in a form which will be valid for
3730 a data instruction. We do this by pushing the expression into a symbol
3731 in the expr_section, and creating a fix for that. */
3734 fix_new_aarch64 (fragS
* frag
,
3736 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3746 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3750 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3757 /* Diagnostics on operands errors. */
3759 /* By default, output verbose error message.
3760 Disable the verbose error message by -mno-verbose-error. */
3761 static int verbose_error_p
= 1;
3763 #ifdef DEBUG_AARCH64
3764 /* N.B. this is only for the purpose of debugging. */
3765 const char* operand_mismatch_kind_names
[] =
3768 "AARCH64_OPDE_RECOVERABLE",
3769 "AARCH64_OPDE_SYNTAX_ERROR",
3770 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3771 "AARCH64_OPDE_INVALID_VARIANT",
3772 "AARCH64_OPDE_OUT_OF_RANGE",
3773 "AARCH64_OPDE_UNALIGNED",
3774 "AARCH64_OPDE_REG_LIST",
3775 "AARCH64_OPDE_OTHER_ERROR",
3777 #endif /* DEBUG_AARCH64 */
3779 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3781 When multiple errors of different kinds are found in the same assembly
3782 line, only the error of the highest severity will be picked up for
3783 issuing the diagnostics. */
3785 static inline bfd_boolean
3786 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3787 enum aarch64_operand_error_kind rhs
)
3789 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3790 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3791 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3792 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3793 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3794 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3795 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3796 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3800 /* Helper routine to get the mnemonic name from the assembly instruction
3801 line; should only be called for the diagnosis purpose, as there is
3802 string copy operation involved, which may affect the runtime
3803 performance if used in elsewhere. */
3806 get_mnemonic_name (const char *str
)
3808 static char mnemonic
[32];
3811 /* Get the first 15 bytes and assume that the full name is included. */
3812 strncpy (mnemonic
, str
, 31);
3813 mnemonic
[31] = '\0';
3815 /* Scan up to the end of the mnemonic, which must end in white space,
3816 '.', or end of string. */
3817 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3822 /* Append '...' to the truncated long name. */
3823 if (ptr
- mnemonic
== 31)
3824 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3830 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3832 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3833 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3836 /* Data strutures storing one user error in the assembly code related to
3839 struct operand_error_record
3841 const aarch64_opcode
*opcode
;
3842 aarch64_operand_error detail
;
3843 struct operand_error_record
*next
;
3846 typedef struct operand_error_record operand_error_record
;
3848 struct operand_errors
3850 operand_error_record
*head
;
3851 operand_error_record
*tail
;
3854 typedef struct operand_errors operand_errors
;
3856 /* Top-level data structure reporting user errors for the current line of
3858 The way md_assemble works is that all opcodes sharing the same mnemonic
3859 name are iterated to find a match to the assembly line. In this data
3860 structure, each of the such opcodes will have one operand_error_record
3861 allocated and inserted. In other words, excessive errors related with
3862 a single opcode are disregarded. */
3863 operand_errors operand_error_report
;
3865 /* Free record nodes. */
3866 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3868 /* Initialize the data structure that stores the operand mismatch
3869 information on assembling one line of the assembly code. */
3871 init_operand_error_report (void)
3873 if (operand_error_report
.head
!= NULL
)
3875 gas_assert (operand_error_report
.tail
!= NULL
);
3876 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3877 free_opnd_error_record_nodes
= operand_error_report
.head
;
3878 operand_error_report
.head
= NULL
;
3879 operand_error_report
.tail
= NULL
;
3882 gas_assert (operand_error_report
.tail
== NULL
);
3885 /* Return TRUE if some operand error has been recorded during the
3886 parsing of the current assembly line using the opcode *OPCODE;
3887 otherwise return FALSE. */
3888 static inline bfd_boolean
3889 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3891 operand_error_record
*record
= operand_error_report
.head
;
3892 return record
&& record
->opcode
== opcode
;
3895 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3896 OPCODE field is initialized with OPCODE.
3897 N.B. only one record for each opcode, i.e. the maximum of one error is
3898 recorded for each instruction template. */
3901 add_operand_error_record (const operand_error_record
* new_record
)
3903 const aarch64_opcode
*opcode
= new_record
->opcode
;
3904 operand_error_record
* record
= operand_error_report
.head
;
3906 /* The record may have been created for this opcode. If not, we need
3908 if (! opcode_has_operand_error_p (opcode
))
3910 /* Get one empty record. */
3911 if (free_opnd_error_record_nodes
== NULL
)
3913 record
= xmalloc (sizeof (operand_error_record
));
3919 record
= free_opnd_error_record_nodes
;
3920 free_opnd_error_record_nodes
= record
->next
;
3922 record
->opcode
= opcode
;
3923 /* Insert at the head. */
3924 record
->next
= operand_error_report
.head
;
3925 operand_error_report
.head
= record
;
3926 if (operand_error_report
.tail
== NULL
)
3927 operand_error_report
.tail
= record
;
3929 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3930 && record
->detail
.index
<= new_record
->detail
.index
3931 && operand_error_higher_severity_p (record
->detail
.kind
,
3932 new_record
->detail
.kind
))
3934 /* In the case of multiple errors found on operands related with a
3935 single opcode, only record the error of the leftmost operand and
3936 only if the error is of higher severity. */
3937 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3938 " the existing error %s on operand %d",
3939 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3940 new_record
->detail
.index
,
3941 operand_mismatch_kind_names
[record
->detail
.kind
],
3942 record
->detail
.index
);
3946 record
->detail
= new_record
->detail
;
3950 record_operand_error_info (const aarch64_opcode
*opcode
,
3951 aarch64_operand_error
*error_info
)
3953 operand_error_record record
;
3954 record
.opcode
= opcode
;
3955 record
.detail
= *error_info
;
3956 add_operand_error_record (&record
);
3959 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3960 error message *ERROR, for operand IDX (count from 0). */
3963 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3964 enum aarch64_operand_error_kind kind
,
3967 aarch64_operand_error info
;
3968 memset(&info
, 0, sizeof (info
));
3972 record_operand_error_info (opcode
, &info
);
3976 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3977 enum aarch64_operand_error_kind kind
,
3978 const char* error
, const int *extra_data
)
3980 aarch64_operand_error info
;
3984 info
.data
[0] = extra_data
[0];
3985 info
.data
[1] = extra_data
[1];
3986 info
.data
[2] = extra_data
[2];
3987 record_operand_error_info (opcode
, &info
);
3991 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
3992 const char* error
, int lower_bound
,
3995 int data
[3] = {lower_bound
, upper_bound
, 0};
3996 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4000 /* Remove the operand error record for *OPCODE. */
4001 static void ATTRIBUTE_UNUSED
4002 remove_operand_error_record (const aarch64_opcode
*opcode
)
4004 if (opcode_has_operand_error_p (opcode
))
4006 operand_error_record
* record
= operand_error_report
.head
;
4007 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4008 operand_error_report
.head
= record
->next
;
4009 record
->next
= free_opnd_error_record_nodes
;
4010 free_opnd_error_record_nodes
= record
;
4011 if (operand_error_report
.head
== NULL
)
4013 gas_assert (operand_error_report
.tail
== record
);
4014 operand_error_report
.tail
= NULL
;
4019 /* Given the instruction in *INSTR, return the index of the best matched
4020 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4022 Return -1 if there is no qualifier sequence; return the first match
4023 if there is multiple matches found. */
4026 find_best_match (const aarch64_inst
*instr
,
4027 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4029 int i
, num_opnds
, max_num_matched
, idx
;
4031 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4034 DEBUG_TRACE ("no operand");
4038 max_num_matched
= 0;
4041 /* For each pattern. */
4042 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4045 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4047 /* Most opcodes has much fewer patterns in the list. */
4048 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4050 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4051 if (i
!= 0 && idx
== -1)
4052 /* If nothing has been matched, return the 1st sequence. */
4057 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4058 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4061 if (num_matched
> max_num_matched
)
4063 max_num_matched
= num_matched
;
4068 DEBUG_TRACE ("return with %d", idx
);
4072 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4073 corresponding operands in *INSTR. */
4076 assign_qualifier_sequence (aarch64_inst
*instr
,
4077 const aarch64_opnd_qualifier_t
*qualifiers
)
4080 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4081 gas_assert (num_opnds
);
4082 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4083 instr
->operands
[i
].qualifier
= *qualifiers
;
4086 /* Print operands for the diagnosis purpose. */
4089 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4090 const aarch64_opnd_info
*opnds
)
4094 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4096 const size_t size
= 128;
4099 /* We regard the opcode operand info more, however we also look into
4100 the inst->operands to support the disassembling of the optional
4102 The two operand code should be the same in all cases, apart from
4103 when the operand can be optional. */
4104 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4105 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4108 /* Generate the operand string in STR. */
4109 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
4113 strcat (buf
, i
== 0 ? " " : ",");
4115 /* Append the operand string. */
4120 /* Send to stderr a string as information. */
4123 output_info (const char *format
, ...)
4129 as_where (&file
, &line
);
4133 fprintf (stderr
, "%s:%u: ", file
, line
);
4135 fprintf (stderr
, "%s: ", file
);
4137 fprintf (stderr
, _("Info: "));
4138 va_start (args
, format
);
4139 vfprintf (stderr
, format
, args
);
4141 (void) putc ('\n', stderr
);
4144 /* Output one operand error record. */
4147 output_operand_error_record (const operand_error_record
*record
, char *str
)
4149 const aarch64_operand_error
*detail
= &record
->detail
;
4150 int idx
= detail
->index
;
4151 const aarch64_opcode
*opcode
= record
->opcode
;
4152 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4153 : AARCH64_OPND_NIL
);
4155 switch (detail
->kind
)
4157 case AARCH64_OPDE_NIL
:
4161 case AARCH64_OPDE_SYNTAX_ERROR
:
4162 case AARCH64_OPDE_RECOVERABLE
:
4163 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4164 case AARCH64_OPDE_OTHER_ERROR
:
4165 /* Use the prepared error message if there is, otherwise use the
4166 operand description string to describe the error. */
4167 if (detail
->error
!= NULL
)
4170 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4172 as_bad (_("%s at operand %d -- `%s'"),
4173 detail
->error
, idx
+ 1, str
);
4177 gas_assert (idx
>= 0);
4178 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4179 aarch64_get_operand_desc (opd_code
), str
);
4183 case AARCH64_OPDE_INVALID_VARIANT
:
4184 as_bad (_("operand mismatch -- `%s'"), str
);
4185 if (verbose_error_p
)
4187 /* We will try to correct the erroneous instruction and also provide
4188 more information e.g. all other valid variants.
4190 The string representation of the corrected instruction and other
4191 valid variants are generated by
4193 1) obtaining the intermediate representation of the erroneous
4195 2) manipulating the IR, e.g. replacing the operand qualifier;
4196 3) printing out the instruction by calling the printer functions
4197 shared with the disassembler.
4199 The limitation of this method is that the exact input assembly
4200 line cannot be accurately reproduced in some cases, for example an
4201 optional operand present in the actual assembly line will be
4202 omitted in the output; likewise for the optional syntax rules,
4203 e.g. the # before the immediate. Another limitation is that the
4204 assembly symbols and relocation operations in the assembly line
4205 currently cannot be printed out in the error report. Last but not
4206 least, when there is other error(s) co-exist with this error, the
4207 'corrected' instruction may be still incorrect, e.g. given
4208 'ldnp h0,h1,[x0,#6]!'
4209 this diagnosis will provide the version:
4210 'ldnp s0,s1,[x0,#6]!'
4211 which is still not right. */
4212 size_t len
= strlen (get_mnemonic_name (str
));
4215 const size_t size
= 2048;
4217 aarch64_inst
*inst_base
= &inst
.base
;
4218 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4221 reset_aarch64_instruction (&inst
);
4222 inst_base
->opcode
= opcode
;
4224 /* Reset the error report so that there is no side effect on the
4225 following operand parsing. */
4226 init_operand_error_report ();
4229 result
= parse_operands (str
+ len
, opcode
)
4230 && programmer_friendly_fixup (&inst
);
4231 gas_assert (result
);
4232 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4234 gas_assert (!result
);
4236 /* Find the most matched qualifier sequence. */
4237 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4238 gas_assert (qlf_idx
> -1);
4240 /* Assign the qualifiers. */
4241 assign_qualifier_sequence (inst_base
,
4242 opcode
->qualifiers_list
[qlf_idx
]);
4244 /* Print the hint. */
4245 output_info (_(" did you mean this?"));
4246 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4247 print_operands (buf
, opcode
, inst_base
->operands
);
4248 output_info (_(" %s"), buf
);
4250 /* Print out other variant(s) if there is any. */
4252 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4253 output_info (_(" other valid variant(s):"));
4255 /* For each pattern. */
4256 qualifiers_list
= opcode
->qualifiers_list
;
4257 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4259 /* Most opcodes has much fewer patterns in the list.
4260 First NIL qualifier indicates the end in the list. */
4261 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4266 /* Mnemonics name. */
4267 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4269 /* Assign the qualifiers. */
4270 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4272 /* Print instruction. */
4273 print_operands (buf
, opcode
, inst_base
->operands
);
4275 output_info (_(" %s"), buf
);
4281 case AARCH64_OPDE_OUT_OF_RANGE
:
4282 if (detail
->data
[0] != detail
->data
[1])
4283 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4284 detail
->error
? detail
->error
: _("immediate value"),
4285 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4287 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4288 detail
->error
? detail
->error
: _("immediate value"),
4289 detail
->data
[0], idx
+ 1, str
);
4292 case AARCH64_OPDE_REG_LIST
:
4293 if (detail
->data
[0] == 1)
4294 as_bad (_("invalid number of registers in the list; "
4295 "only 1 register is expected at operand %d -- `%s'"),
4298 as_bad (_("invalid number of registers in the list; "
4299 "%d registers are expected at operand %d -- `%s'"),
4300 detail
->data
[0], idx
+ 1, str
);
4303 case AARCH64_OPDE_UNALIGNED
:
4304 as_bad (_("immediate value should be a multiple of "
4305 "%d at operand %d -- `%s'"),
4306 detail
->data
[0], idx
+ 1, str
);
4315 /* Process and output the error message about the operand mismatching.
4317 When this function is called, the operand error information had
4318 been collected for an assembly line and there will be multiple
4319 errors in the case of mulitple instruction templates; output the
4320 error message that most closely describes the problem. */
4323 output_operand_error_report (char *str
)
4325 int largest_error_pos
;
4326 const char *msg
= NULL
;
4327 enum aarch64_operand_error_kind kind
;
4328 operand_error_record
*curr
;
4329 operand_error_record
*head
= operand_error_report
.head
;
4330 operand_error_record
*record
= NULL
;
4332 /* No error to report. */
4336 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4338 /* Only one error. */
4339 if (head
== operand_error_report
.tail
)
4341 DEBUG_TRACE ("single opcode entry with error kind: %s",
4342 operand_mismatch_kind_names
[head
->detail
.kind
]);
4343 output_operand_error_record (head
, str
);
4347 /* Find the error kind of the highest severity. */
4348 DEBUG_TRACE ("multiple opcode entres with error kind");
4349 kind
= AARCH64_OPDE_NIL
;
4350 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4352 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4353 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4354 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4355 kind
= curr
->detail
.kind
;
4357 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4359 /* Pick up one of errors of KIND to report. */
4360 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4361 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4363 if (curr
->detail
.kind
!= kind
)
4365 /* If there are multiple errors, pick up the one with the highest
4366 mismatching operand index. In the case of multiple errors with
4367 the equally highest operand index, pick up the first one or the
4368 first one with non-NULL error message. */
4369 if (curr
->detail
.index
> largest_error_pos
4370 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4371 && curr
->detail
.error
!= NULL
))
4373 largest_error_pos
= curr
->detail
.index
;
4375 msg
= record
->detail
.error
;
4379 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4380 DEBUG_TRACE ("Pick up error kind %s to report",
4381 operand_mismatch_kind_names
[record
->detail
.kind
]);
4384 output_operand_error_record (record
, str
);
4387 /* Write an AARCH64 instruction to buf - always little-endian. */
4389 put_aarch64_insn (char *buf
, uint32_t insn
)
4391 unsigned char *where
= (unsigned char *) buf
;
4393 where
[1] = insn
>> 8;
4394 where
[2] = insn
>> 16;
4395 where
[3] = insn
>> 24;
4399 get_aarch64_insn (char *buf
)
4401 unsigned char *where
= (unsigned char *) buf
;
4403 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4408 output_inst (struct aarch64_inst
*new_inst
)
4412 to
= frag_more (INSN_SIZE
);
4414 frag_now
->tc_frag_data
.recorded
= 1;
4416 put_aarch64_insn (to
, inst
.base
.value
);
4418 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4420 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4421 INSN_SIZE
, &inst
.reloc
.exp
,
4424 DEBUG_TRACE ("Prepared relocation fix up");
4425 /* Don't check the addend value against the instruction size,
4426 that's the job of our code in md_apply_fix(). */
4427 fixp
->fx_no_overflow
= 1;
4428 if (new_inst
!= NULL
)
4429 fixp
->tc_fix_data
.inst
= new_inst
;
4430 if (aarch64_gas_internal_fixup_p ())
4432 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4433 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4434 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4438 dwarf2_emit_insn (INSN_SIZE
);
4441 /* Link together opcodes of the same name. */
4445 aarch64_opcode
*opcode
;
4446 struct templates
*next
;
4449 typedef struct templates templates
;
4452 lookup_mnemonic (const char *start
, int len
)
4454 templates
*templ
= NULL
;
4456 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4460 /* Subroutine of md_assemble, responsible for looking up the primary
4461 opcode from the mnemonic the user wrote. STR points to the
4462 beginning of the mnemonic. */
4465 opcode_lookup (char **str
)
4468 const aarch64_cond
*cond
;
4472 /* Scan up to the end of the mnemonic, which must end in white space,
4473 '.', or end of string. */
4474 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4481 inst
.cond
= COND_ALWAYS
;
4483 /* Handle a possible condition. */
4486 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4489 inst
.cond
= cond
->value
;
4503 if (inst
.cond
== COND_ALWAYS
)
4505 /* Look for unaffixed mnemonic. */
4506 return lookup_mnemonic (base
, len
);
4510 /* append ".c" to mnemonic if conditional */
4511 memcpy (condname
, base
, len
);
4512 memcpy (condname
+ len
, ".c", 2);
4515 return lookup_mnemonic (base
, len
);
4521 /* Internal helper routine converting a vector neon_type_el structure
4522 *VECTYPE to a corresponding operand qualifier. */
4524 static inline aarch64_opnd_qualifier_t
4525 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4527 /* Element size in bytes indexed by neon_el_type. */
4528 const unsigned char ele_size
[5]
4531 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4532 goto vectype_conversion_fail
;
4534 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4536 if (vectype
->defined
& NTA_HASINDEX
)
4537 /* Vector element register. */
4538 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4541 /* Vector register. */
4542 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4544 if (reg_size
!= 16 && reg_size
!= 8)
4545 goto vectype_conversion_fail
;
4546 /* The conversion is calculated based on the relation of the order of
4547 qualifiers to the vector element size and vector register size. */
4548 offset
= (vectype
->type
== NT_q
)
4549 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4550 gas_assert (offset
<= 8);
4551 return AARCH64_OPND_QLF_V_8B
+ offset
;
4554 vectype_conversion_fail
:
4555 first_error (_("bad vector arrangement type"));
4556 return AARCH64_OPND_QLF_NIL
;
4559 /* Process an optional operand that is found omitted from the assembly line.
4560 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4561 instruction's opcode entry while IDX is the index of this omitted operand.
4565 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4566 int idx
, aarch64_opnd_info
*operand
)
4568 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4569 gas_assert (optional_operand_p (opcode
, idx
));
4570 gas_assert (!operand
->present
);
4574 case AARCH64_OPND_Rd
:
4575 case AARCH64_OPND_Rn
:
4576 case AARCH64_OPND_Rm
:
4577 case AARCH64_OPND_Rt
:
4578 case AARCH64_OPND_Rt2
:
4579 case AARCH64_OPND_Rs
:
4580 case AARCH64_OPND_Ra
:
4581 case AARCH64_OPND_Rt_SYS
:
4582 case AARCH64_OPND_Rd_SP
:
4583 case AARCH64_OPND_Rn_SP
:
4584 case AARCH64_OPND_Fd
:
4585 case AARCH64_OPND_Fn
:
4586 case AARCH64_OPND_Fm
:
4587 case AARCH64_OPND_Fa
:
4588 case AARCH64_OPND_Ft
:
4589 case AARCH64_OPND_Ft2
:
4590 case AARCH64_OPND_Sd
:
4591 case AARCH64_OPND_Sn
:
4592 case AARCH64_OPND_Sm
:
4593 case AARCH64_OPND_Vd
:
4594 case AARCH64_OPND_Vn
:
4595 case AARCH64_OPND_Vm
:
4596 case AARCH64_OPND_VdD1
:
4597 case AARCH64_OPND_VnD1
:
4598 operand
->reg
.regno
= default_value
;
4601 case AARCH64_OPND_Ed
:
4602 case AARCH64_OPND_En
:
4603 case AARCH64_OPND_Em
:
4604 operand
->reglane
.regno
= default_value
;
4607 case AARCH64_OPND_IDX
:
4608 case AARCH64_OPND_BIT_NUM
:
4609 case AARCH64_OPND_IMMR
:
4610 case AARCH64_OPND_IMMS
:
4611 case AARCH64_OPND_SHLL_IMM
:
4612 case AARCH64_OPND_IMM_VLSL
:
4613 case AARCH64_OPND_IMM_VLSR
:
4614 case AARCH64_OPND_CCMP_IMM
:
4615 case AARCH64_OPND_FBITS
:
4616 case AARCH64_OPND_UIMM4
:
4617 case AARCH64_OPND_UIMM3_OP1
:
4618 case AARCH64_OPND_UIMM3_OP2
:
4619 case AARCH64_OPND_IMM
:
4620 case AARCH64_OPND_WIDTH
:
4621 case AARCH64_OPND_UIMM7
:
4622 case AARCH64_OPND_NZCV
:
4623 operand
->imm
.value
= default_value
;
4626 case AARCH64_OPND_EXCEPTION
:
4627 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4630 case AARCH64_OPND_BARRIER_ISB
:
4631 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4638 /* Process the relocation type for move wide instructions.
4639 Return TRUE on success; otherwise return FALSE. */
4642 process_movw_reloc_info (void)
4647 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4649 if (inst
.base
.opcode
->op
== OP_MOVK
)
4650 switch (inst
.reloc
.type
)
4652 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4653 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4654 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4655 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4656 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4657 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4659 (_("the specified relocation type is not allowed for MOVK"));
4665 switch (inst
.reloc
.type
)
4667 case BFD_RELOC_AARCH64_MOVW_G0
:
4668 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4669 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4670 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4671 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4672 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4673 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4676 case BFD_RELOC_AARCH64_MOVW_G1
:
4677 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4678 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4679 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4680 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4681 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4682 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4685 case BFD_RELOC_AARCH64_MOVW_G2
:
4686 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4687 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4688 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4689 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4692 set_fatal_syntax_error
4693 (_("the specified relocation type is not allowed for 32-bit "
4699 case BFD_RELOC_AARCH64_MOVW_G3
:
4702 set_fatal_syntax_error
4703 (_("the specified relocation type is not allowed for 32-bit "
4710 /* More cases should be added when more MOVW-related relocation types
4711 are supported in GAS. */
4712 gas_assert (aarch64_gas_internal_fixup_p ());
4713 /* The shift amount should have already been set by the parser. */
4716 inst
.base
.operands
[1].shifter
.amount
= shift
;
4720 /* A primitive log caculator. */
4722 static inline unsigned int
4723 get_logsz (unsigned int size
)
4725 const unsigned char ls
[16] =
4726 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4732 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4733 return ls
[size
- 1];
4736 /* Determine and return the real reloc type code for an instruction
4737 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4739 static inline bfd_reloc_code_real_type
4740 ldst_lo12_determine_real_reloc_type (void)
4743 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4744 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4746 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4748 BFD_RELOC_AARCH64_LDST8_LO12
,
4749 BFD_RELOC_AARCH64_LDST16_LO12
,
4750 BFD_RELOC_AARCH64_LDST32_LO12
,
4751 BFD_RELOC_AARCH64_LDST64_LO12
,
4752 BFD_RELOC_AARCH64_LDST128_LO12
4755 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4756 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4757 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4758 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4759 BFD_RELOC_AARCH64_NONE
4762 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4763 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4764 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4765 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4766 BFD_RELOC_AARCH64_NONE
4770 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4771 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4773 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4774 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4776 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4778 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4780 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4782 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4783 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4784 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4785 gas_assert (logsz
<= 3);
4787 gas_assert (logsz
<= 4);
4789 /* In reloc.c, these pseudo relocation types should be defined in similar
4790 order as above reloc_ldst_lo12 array. Because the array index calcuation
4791 below relies on this. */
4792 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4795 /* Check whether a register list REGINFO is valid. The registers must be
4796 numbered in increasing order (modulo 32), in increments of one or two.
4798 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4801 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4804 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4806 uint32_t i
, nb_regs
, prev_regno
, incr
;
4808 nb_regs
= 1 + (reginfo
& 0x3);
4810 prev_regno
= reginfo
& 0x1f;
4811 incr
= accept_alternate
? 2 : 1;
4813 for (i
= 1; i
< nb_regs
; ++i
)
4815 uint32_t curr_regno
;
4817 curr_regno
= reginfo
& 0x1f;
4818 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4820 prev_regno
= curr_regno
;
4826 /* Generic instruction operand parser. This does no encoding and no
4827 semantic validation; it merely squirrels values away in the inst
4828 structure. Returns TRUE or FALSE depending on whether the
4829 specified grammar matched. */
4832 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4835 char *backtrack_pos
= 0;
4836 const enum aarch64_opnd
*operands
= opcode
->operands
;
4839 skip_whitespace (str
);
4841 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4844 int isreg32
, isregzero
;
4845 int comma_skipped_p
= 0;
4846 aarch64_reg_type rtype
;
4847 struct neon_type_el vectype
;
4848 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4850 DEBUG_TRACE ("parse operand %d", i
);
4852 /* Assign the operand code. */
4853 info
->type
= operands
[i
];
4855 if (optional_operand_p (opcode
, i
))
4857 /* Remember where we are in case we need to backtrack. */
4858 gas_assert (!backtrack_pos
);
4859 backtrack_pos
= str
;
4862 /* Expect comma between operands; the backtrack mechanizm will take
4863 care of cases of omitted optional operand. */
4864 if (i
> 0 && ! skip_past_char (&str
, ','))
4866 set_syntax_error (_("comma expected between operands"));
4870 comma_skipped_p
= 1;
4872 switch (operands
[i
])
4874 case AARCH64_OPND_Rd
:
4875 case AARCH64_OPND_Rn
:
4876 case AARCH64_OPND_Rm
:
4877 case AARCH64_OPND_Rt
:
4878 case AARCH64_OPND_Rt2
:
4879 case AARCH64_OPND_Rs
:
4880 case AARCH64_OPND_Ra
:
4881 case AARCH64_OPND_Rt_SYS
:
4882 case AARCH64_OPND_PAIRREG
:
4883 po_int_reg_or_fail (1, 0);
4886 case AARCH64_OPND_Rd_SP
:
4887 case AARCH64_OPND_Rn_SP
:
4888 po_int_reg_or_fail (0, 1);
4891 case AARCH64_OPND_Rm_EXT
:
4892 case AARCH64_OPND_Rm_SFT
:
4893 po_misc_or_fail (parse_shifter_operand
4894 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4896 : SHIFTED_LOGIC_IMM
)));
4897 if (!info
->shifter
.operator_present
)
4899 /* Default to LSL if not present. Libopcodes prefers shifter
4900 kind to be explicit. */
4901 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4902 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4903 /* For Rm_EXT, libopcodes will carry out further check on whether
4904 or not stack pointer is used in the instruction (Recall that
4905 "the extend operator is not optional unless at least one of
4906 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4910 case AARCH64_OPND_Fd
:
4911 case AARCH64_OPND_Fn
:
4912 case AARCH64_OPND_Fm
:
4913 case AARCH64_OPND_Fa
:
4914 case AARCH64_OPND_Ft
:
4915 case AARCH64_OPND_Ft2
:
4916 case AARCH64_OPND_Sd
:
4917 case AARCH64_OPND_Sn
:
4918 case AARCH64_OPND_Sm
:
4919 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4920 if (val
== PARSE_FAIL
)
4922 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4925 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4927 info
->reg
.regno
= val
;
4928 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4931 case AARCH64_OPND_Vd
:
4932 case AARCH64_OPND_Vn
:
4933 case AARCH64_OPND_Vm
:
4934 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4935 if (val
== PARSE_FAIL
)
4937 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4940 if (vectype
.defined
& NTA_HASINDEX
)
4943 info
->reg
.regno
= val
;
4944 info
->qualifier
= vectype_to_qualifier (&vectype
);
4945 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4949 case AARCH64_OPND_VdD1
:
4950 case AARCH64_OPND_VnD1
:
4951 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4952 if (val
== PARSE_FAIL
)
4954 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4957 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4959 set_fatal_syntax_error
4960 (_("the top half of a 128-bit FP/SIMD register is expected"));
4963 info
->reg
.regno
= val
;
4964 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4965 here; it is correct for the purpose of encoding/decoding since
4966 only the register number is explicitly encoded in the related
4967 instructions, although this appears a bit hacky. */
4968 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4971 case AARCH64_OPND_Ed
:
4972 case AARCH64_OPND_En
:
4973 case AARCH64_OPND_Em
:
4974 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4975 if (val
== PARSE_FAIL
)
4977 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4980 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
4983 info
->reglane
.regno
= val
;
4984 info
->reglane
.index
= vectype
.index
;
4985 info
->qualifier
= vectype_to_qualifier (&vectype
);
4986 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4990 case AARCH64_OPND_LVn
:
4991 case AARCH64_OPND_LVt
:
4992 case AARCH64_OPND_LVt_AL
:
4993 case AARCH64_OPND_LEt
:
4994 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
4996 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
4998 set_fatal_syntax_error (_("invalid register list"));
5001 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5002 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5003 if (operands
[i
] == AARCH64_OPND_LEt
)
5005 if (!(vectype
.defined
& NTA_HASINDEX
))
5007 info
->reglist
.has_index
= 1;
5008 info
->reglist
.index
= vectype
.index
;
5010 else if (!(vectype
.defined
& NTA_HASTYPE
))
5012 info
->qualifier
= vectype_to_qualifier (&vectype
);
5013 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5017 case AARCH64_OPND_Cn
:
5018 case AARCH64_OPND_Cm
:
5019 po_reg_or_fail (REG_TYPE_CN
);
5022 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5025 inst
.base
.operands
[i
].reg
.regno
= val
;
5028 case AARCH64_OPND_SHLL_IMM
:
5029 case AARCH64_OPND_IMM_VLSR
:
5030 po_imm_or_fail (1, 64);
5031 info
->imm
.value
= val
;
5034 case AARCH64_OPND_CCMP_IMM
:
5035 case AARCH64_OPND_FBITS
:
5036 case AARCH64_OPND_UIMM4
:
5037 case AARCH64_OPND_UIMM3_OP1
:
5038 case AARCH64_OPND_UIMM3_OP2
:
5039 case AARCH64_OPND_IMM_VLSL
:
5040 case AARCH64_OPND_IMM
:
5041 case AARCH64_OPND_WIDTH
:
5042 po_imm_nc_or_fail ();
5043 info
->imm
.value
= val
;
5046 case AARCH64_OPND_UIMM7
:
5047 po_imm_or_fail (0, 127);
5048 info
->imm
.value
= val
;
5051 case AARCH64_OPND_IDX
:
5052 case AARCH64_OPND_BIT_NUM
:
5053 case AARCH64_OPND_IMMR
:
5054 case AARCH64_OPND_IMMS
:
5055 po_imm_or_fail (0, 63);
5056 info
->imm
.value
= val
;
5059 case AARCH64_OPND_IMM0
:
5060 po_imm_nc_or_fail ();
5063 set_fatal_syntax_error (_("immediate zero expected"));
5066 info
->imm
.value
= 0;
5069 case AARCH64_OPND_FPIMM0
:
5072 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5073 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5074 it is probably not worth the effort to support it. */
5075 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
5076 && !(res2
= parse_constant_immediate (&str
, &val
)))
5078 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5080 info
->imm
.value
= 0;
5081 info
->imm
.is_fp
= 1;
5084 set_fatal_syntax_error (_("immediate zero expected"));
5088 case AARCH64_OPND_IMM_MOV
:
5091 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5092 reg_name_p (str
, REG_TYPE_VN
))
5095 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5097 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5098 later. fix_mov_imm_insn will try to determine a machine
5099 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5100 message if the immediate cannot be moved by a single
5102 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5103 inst
.base
.operands
[i
].skip
= 1;
5107 case AARCH64_OPND_SIMD_IMM
:
5108 case AARCH64_OPND_SIMD_IMM_SFT
:
5109 if (! parse_big_immediate (&str
, &val
))
5111 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5113 /* need_libopcodes_p */ 1,
5116 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5117 shift, we don't check it here; we leave the checking to
5118 the libopcodes (operand_general_constraint_met_p). By
5119 doing this, we achieve better diagnostics. */
5120 if (skip_past_comma (&str
)
5121 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5123 if (!info
->shifter
.operator_present
5124 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5126 /* Default to LSL if not present. Libopcodes prefers shifter
5127 kind to be explicit. */
5128 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5129 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5133 case AARCH64_OPND_FPIMM
:
5134 case AARCH64_OPND_SIMD_FPIMM
:
5138 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5140 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5144 set_fatal_syntax_error (_("invalid floating-point constant"));
5147 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5148 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5152 case AARCH64_OPND_LIMM
:
5153 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5154 SHIFTED_LOGIC_IMM
));
5155 if (info
->shifter
.operator_present
)
5157 set_fatal_syntax_error
5158 (_("shift not allowed for bitmask immediate"));
5161 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5163 /* need_libopcodes_p */ 1,
5167 case AARCH64_OPND_AIMM
:
5168 if (opcode
->op
== OP_ADD
)
5169 /* ADD may have relocation types. */
5170 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5171 SHIFTED_ARITH_IMM
));
5173 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5174 SHIFTED_ARITH_IMM
));
5175 switch (inst
.reloc
.type
)
5177 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5178 info
->shifter
.amount
= 12;
5180 case BFD_RELOC_UNUSED
:
5181 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5182 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5183 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5184 inst
.reloc
.pc_rel
= 0;
5189 info
->imm
.value
= 0;
5190 if (!info
->shifter
.operator_present
)
5192 /* Default to LSL if not present. Libopcodes prefers shifter
5193 kind to be explicit. */
5194 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5195 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5199 case AARCH64_OPND_HALF
:
5201 /* #<imm16> or relocation. */
5202 int internal_fixup_p
;
5203 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5204 if (internal_fixup_p
)
5205 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5206 skip_whitespace (str
);
5207 if (skip_past_comma (&str
))
5209 /* {, LSL #<shift>} */
5210 if (! aarch64_gas_internal_fixup_p ())
5212 set_fatal_syntax_error (_("can't mix relocation modifier "
5213 "with explicit shift"));
5216 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5219 inst
.base
.operands
[i
].shifter
.amount
= 0;
5220 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5221 inst
.base
.operands
[i
].imm
.value
= 0;
5222 if (! process_movw_reloc_info ())
5227 case AARCH64_OPND_EXCEPTION
:
5228 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5229 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5231 /* need_libopcodes_p */ 0,
5235 case AARCH64_OPND_NZCV
:
5237 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5241 info
->imm
.value
= nzcv
->value
;
5244 po_imm_or_fail (0, 15);
5245 info
->imm
.value
= val
;
5249 case AARCH64_OPND_COND
:
5250 case AARCH64_OPND_COND1
:
5251 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5253 if (info
->cond
== NULL
)
5255 set_syntax_error (_("invalid condition"));
5258 else if (operands
[i
] == AARCH64_OPND_COND1
5259 && (info
->cond
->value
& 0xe) == 0xe)
5261 /* Not allow AL or NV. */
5262 set_default_error ();
5267 case AARCH64_OPND_ADDR_ADRP
:
5268 po_misc_or_fail (parse_adrp (&str
));
5269 /* Clear the value as operand needs to be relocated. */
5270 info
->imm
.value
= 0;
5273 case AARCH64_OPND_ADDR_PCREL14
:
5274 case AARCH64_OPND_ADDR_PCREL19
:
5275 case AARCH64_OPND_ADDR_PCREL21
:
5276 case AARCH64_OPND_ADDR_PCREL26
:
5277 po_misc_or_fail (parse_address_reloc (&str
, info
));
5278 if (!info
->addr
.pcrel
)
5280 set_syntax_error (_("invalid pc-relative address"));
5283 if (inst
.gen_lit_pool
5284 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5286 /* Only permit "=value" in the literal load instructions.
5287 The literal will be generated by programmer_friendly_fixup. */
5288 set_syntax_error (_("invalid use of \"=immediate\""));
5291 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5293 set_syntax_error (_("unrecognized relocation suffix"));
5296 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5298 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5299 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5303 info
->imm
.value
= 0;
5304 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5305 switch (opcode
->iclass
)
5309 /* e.g. CBZ or B.COND */
5310 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5311 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5315 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5316 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5320 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5322 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5323 : BFD_RELOC_AARCH64_JUMP26
;
5326 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5327 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5330 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5331 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5337 inst
.reloc
.pc_rel
= 1;
5341 case AARCH64_OPND_ADDR_SIMPLE
:
5342 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5343 /* [<Xn|SP>{, #<simm>}] */
5344 po_char_or_fail ('[');
5345 po_reg_or_fail (REG_TYPE_R64_SP
);
5346 /* Accept optional ", #0". */
5347 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5348 && skip_past_char (&str
, ','))
5350 skip_past_char (&str
, '#');
5351 if (! skip_past_char (&str
, '0'))
5353 set_fatal_syntax_error
5354 (_("the optional immediate offset can only be 0"));
5358 po_char_or_fail (']');
5359 info
->addr
.base_regno
= val
;
5362 case AARCH64_OPND_ADDR_REGOFF
:
5363 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5364 po_misc_or_fail (parse_address (&str
, info
, 0));
5365 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5366 || !info
->addr
.preind
|| info
->addr
.postind
5367 || info
->addr
.writeback
)
5369 set_syntax_error (_("invalid addressing mode"));
5372 if (!info
->shifter
.operator_present
)
5374 /* Default to LSL if not present. Libopcodes prefers shifter
5375 kind to be explicit. */
5376 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5377 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5379 /* Qualifier to be deduced by libopcodes. */
5382 case AARCH64_OPND_ADDR_SIMM7
:
5383 po_misc_or_fail (parse_address (&str
, info
, 0));
5384 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5385 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5387 set_syntax_error (_("invalid addressing mode"));
5390 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5392 /* need_libopcodes_p */ 1,
5396 case AARCH64_OPND_ADDR_SIMM9
:
5397 case AARCH64_OPND_ADDR_SIMM9_2
:
5398 po_misc_or_fail (parse_address_reloc (&str
, info
));
5399 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5400 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5401 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5402 && info
->addr
.writeback
))
5404 set_syntax_error (_("invalid addressing mode"));
5407 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5409 set_syntax_error (_("relocation not allowed"));
5412 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5414 /* need_libopcodes_p */ 1,
5418 case AARCH64_OPND_ADDR_UIMM12
:
5419 po_misc_or_fail (parse_address_reloc (&str
, info
));
5420 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5421 || !info
->addr
.preind
|| info
->addr
.writeback
)
5423 set_syntax_error (_("invalid addressing mode"));
5426 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5427 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5428 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5430 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5432 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5433 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5434 /* Leave qualifier to be determined by libopcodes. */
5437 case AARCH64_OPND_SIMD_ADDR_POST
:
5438 /* [<Xn|SP>], <Xm|#<amount>> */
5439 po_misc_or_fail (parse_address (&str
, info
, 1));
5440 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5442 set_syntax_error (_("invalid addressing mode"));
5445 if (!info
->addr
.offset
.is_reg
)
5447 if (inst
.reloc
.exp
.X_op
== O_constant
)
5448 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5451 set_fatal_syntax_error
5452 (_("writeback value should be an immediate constant"));
5459 case AARCH64_OPND_SYSREG
:
5460 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5463 set_syntax_error (_("unknown or missing system register name"));
5466 inst
.base
.operands
[i
].sysreg
= val
;
5469 case AARCH64_OPND_PSTATEFIELD
:
5470 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5473 set_syntax_error (_("unknown or missing PSTATE field name"));
5476 inst
.base
.operands
[i
].pstatefield
= val
;
5479 case AARCH64_OPND_SYSREG_IC
:
5480 inst
.base
.operands
[i
].sysins_op
=
5481 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5483 case AARCH64_OPND_SYSREG_DC
:
5484 inst
.base
.operands
[i
].sysins_op
=
5485 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5487 case AARCH64_OPND_SYSREG_AT
:
5488 inst
.base
.operands
[i
].sysins_op
=
5489 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5491 case AARCH64_OPND_SYSREG_TLBI
:
5492 inst
.base
.operands
[i
].sysins_op
=
5493 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5495 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5497 set_fatal_syntax_error ( _("unknown or missing operation name"));
5502 case AARCH64_OPND_BARRIER
:
5503 case AARCH64_OPND_BARRIER_ISB
:
5504 val
= parse_barrier (&str
);
5505 if (val
!= PARSE_FAIL
5506 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5508 /* ISB only accepts options name 'sy'. */
5510 (_("the specified option is not accepted in ISB"));
5511 /* Turn off backtrack as this optional operand is present. */
5515 /* This is an extension to accept a 0..15 immediate. */
5516 if (val
== PARSE_FAIL
)
5517 po_imm_or_fail (0, 15);
5518 info
->barrier
= aarch64_barrier_options
+ val
;
5521 case AARCH64_OPND_PRFOP
:
5522 val
= parse_pldop (&str
);
5523 /* This is an extension to accept a 0..31 immediate. */
5524 if (val
== PARSE_FAIL
)
5525 po_imm_or_fail (0, 31);
5526 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5530 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5533 /* If we get here, this operand was successfully parsed. */
5534 inst
.base
.operands
[i
].present
= 1;
5538 /* The parse routine should already have set the error, but in case
5539 not, set a default one here. */
5541 set_default_error ();
5543 if (! backtrack_pos
)
5544 goto parse_operands_return
;
5547 /* We reach here because this operand is marked as optional, and
5548 either no operand was supplied or the operand was supplied but it
5549 was syntactically incorrect. In the latter case we report an
5550 error. In the former case we perform a few more checks before
5551 dropping through to the code to insert the default operand. */
5553 char *tmp
= backtrack_pos
;
5554 char endchar
= END_OF_INSN
;
5556 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5558 skip_past_char (&tmp
, ',');
5560 if (*tmp
!= endchar
)
5561 /* The user has supplied an operand in the wrong format. */
5562 goto parse_operands_return
;
5564 /* Make sure there is not a comma before the optional operand.
5565 For example the fifth operand of 'sys' is optional:
5567 sys #0,c0,c0,#0, <--- wrong
5568 sys #0,c0,c0,#0 <--- correct. */
5569 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5571 set_fatal_syntax_error
5572 (_("unexpected comma before the omitted optional operand"));
5573 goto parse_operands_return
;
5577 /* Reaching here means we are dealing with an optional operand that is
5578 omitted from the assembly line. */
5579 gas_assert (optional_operand_p (opcode
, i
));
5581 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5583 /* Try again, skipping the optional operand at backtrack_pos. */
5584 str
= backtrack_pos
;
5587 /* Clear any error record after the omitted optional operand has been
5588 successfully handled. */
5592 /* Check if we have parsed all the operands. */
5593 if (*str
!= '\0' && ! error_p ())
5595 /* Set I to the index of the last present operand; this is
5596 for the purpose of diagnostics. */
5597 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5599 set_fatal_syntax_error
5600 (_("unexpected characters following instruction"));
5603 parse_operands_return
:
5607 DEBUG_TRACE ("parsing FAIL: %s - %s",
5608 operand_mismatch_kind_names
[get_error_kind ()],
5609 get_error_message ());
5610 /* Record the operand error properly; this is useful when there
5611 are multiple instruction templates for a mnemonic name, so that
5612 later on, we can select the error that most closely describes
5614 record_operand_error (opcode
, i
, get_error_kind (),
5615 get_error_message ());
5620 DEBUG_TRACE ("parsing SUCCESS");
5625 /* It does some fix-up to provide some programmer friendly feature while
5626 keeping the libopcodes happy, i.e. libopcodes only accepts
5627 the preferred architectural syntax.
5628 Return FALSE if there is any failure; otherwise return TRUE. */
5631 programmer_friendly_fixup (aarch64_instruction
*instr
)
5633 aarch64_inst
*base
= &instr
->base
;
5634 const aarch64_opcode
*opcode
= base
->opcode
;
5635 enum aarch64_op op
= opcode
->op
;
5636 aarch64_opnd_info
*operands
= base
->operands
;
5638 DEBUG_TRACE ("enter");
5640 switch (opcode
->iclass
)
5643 /* TBNZ Xn|Wn, #uimm6, label
5644 Test and Branch Not Zero: conditionally jumps to label if bit number
5645 uimm6 in register Xn is not zero. The bit number implies the width of
5646 the register, which may be written and should be disassembled as Wn if
5647 uimm is less than 32. */
5648 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5650 if (operands
[1].imm
.value
>= 32)
5652 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5656 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5660 /* LDR Wt, label | =value
5661 As a convenience assemblers will typically permit the notation
5662 "=value" in conjunction with the pc-relative literal load instructions
5663 to automatically place an immediate value or symbolic address in a
5664 nearby literal pool and generate a hidden label which references it.
5665 ISREG has been set to 0 in the case of =value. */
5666 if (instr
->gen_lit_pool
5667 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5669 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5670 if (op
== OP_LDRSW_LIT
)
5672 if (instr
->reloc
.exp
.X_op
!= O_constant
5673 && instr
->reloc
.exp
.X_op
!= O_big
5674 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5676 record_operand_error (opcode
, 1,
5677 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5678 _("constant expression expected"));
5681 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5683 record_operand_error (opcode
, 1,
5684 AARCH64_OPDE_OTHER_ERROR
,
5685 _("literal pool insertion failed"));
5693 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5694 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5695 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5696 A programmer-friendly assembler should accept a destination Xd in
5697 place of Wd, however that is not the preferred form for disassembly.
5699 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5700 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5701 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5702 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5707 /* In the 64-bit form, the final register operand is written as Wm
5708 for all but the (possibly omitted) UXTX/LSL and SXTX
5710 As a programmer-friendly assembler, we accept e.g.
5711 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5712 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5713 int idx
= aarch64_operand_index (opcode
->operands
,
5714 AARCH64_OPND_Rm_EXT
);
5715 gas_assert (idx
== 1 || idx
== 2);
5716 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5717 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5718 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5719 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5720 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5721 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5729 DEBUG_TRACE ("exit with SUCCESS");
5733 /* Check for loads and stores that will cause unpredictable behavior. */
5736 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5738 aarch64_inst
*base
= &instr
->base
;
5739 const aarch64_opcode
*opcode
= base
->opcode
;
5740 const aarch64_opnd_info
*opnds
= base
->operands
;
5741 switch (opcode
->iclass
)
5747 /* Loading/storing the base register is unpredictable if writeback. */
5748 if ((aarch64_get_operand_class (opnds
[0].type
)
5749 == AARCH64_OPND_CLASS_INT_REG
)
5750 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5751 && opnds
[1].addr
.base_regno
!= REG_SP
5752 && opnds
[1].addr
.writeback
)
5753 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5756 case ldstnapair_offs
:
5757 case ldstpair_indexed
:
5758 /* Loading/storing the base register is unpredictable if writeback. */
5759 if ((aarch64_get_operand_class (opnds
[0].type
)
5760 == AARCH64_OPND_CLASS_INT_REG
)
5761 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5762 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5763 && opnds
[2].addr
.base_regno
!= REG_SP
5764 && opnds
[2].addr
.writeback
)
5765 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5766 /* Load operations must load different registers. */
5767 if ((opcode
->opcode
& (1 << 22))
5768 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5769 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5776 /* A wrapper function to interface with libopcodes on encoding and
5777 record the error message if there is any.
5779 Return TRUE on success; otherwise return FALSE. */
5782 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5785 aarch64_operand_error error_info
;
5786 error_info
.kind
= AARCH64_OPDE_NIL
;
5787 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5791 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5792 record_operand_error_info (opcode
, &error_info
);
5797 #ifdef DEBUG_AARCH64
5799 dump_opcode_operands (const aarch64_opcode
*opcode
)
5802 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5804 aarch64_verbose ("\t\t opnd%d: %s", i
,
5805 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5806 ? aarch64_get_operand_name (opcode
->operands
[i
])
5807 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5811 #endif /* DEBUG_AARCH64 */
5813 /* This is the guts of the machine-dependent assembler. STR points to a
5814 machine dependent instruction. This function is supposed to emit
5815 the frags/bytes it assembles to. */
5818 md_assemble (char *str
)
5821 templates
*template;
5822 aarch64_opcode
*opcode
;
5823 aarch64_inst
*inst_base
;
5824 unsigned saved_cond
;
5826 /* Align the previous label if needed. */
5827 if (last_label_seen
!= NULL
)
5829 symbol_set_frag (last_label_seen
, frag_now
);
5830 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5831 S_SET_SEGMENT (last_label_seen
, now_seg
);
5834 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5836 DEBUG_TRACE ("\n\n");
5837 DEBUG_TRACE ("==============================");
5838 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5840 template = opcode_lookup (&p
);
5843 /* It wasn't an instruction, but it might be a register alias of
5844 the form alias .req reg directive. */
5845 if (!create_register_alias (str
, p
))
5846 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5851 skip_whitespace (p
);
5854 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5855 get_mnemonic_name (str
), str
);
5859 init_operand_error_report ();
5861 /* Sections are assumed to start aligned. In executable section, there is no
5862 MAP_DATA symbol pending. So we only align the address during
5863 MAP_DATA --> MAP_INSN transition.
5864 For other sections, this is not guaranteed. */
5865 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
5866 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
5867 frag_align_code (2, 0);
5869 saved_cond
= inst
.cond
;
5870 reset_aarch64_instruction (&inst
);
5871 inst
.cond
= saved_cond
;
5873 /* Iterate through all opcode entries with the same mnemonic name. */
5876 opcode
= template->opcode
;
5878 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5879 #ifdef DEBUG_AARCH64
5881 dump_opcode_operands (opcode
);
5882 #endif /* DEBUG_AARCH64 */
5884 mapping_state (MAP_INSN
);
5886 inst_base
= &inst
.base
;
5887 inst_base
->opcode
= opcode
;
5889 /* Truly conditionally executed instructions, e.g. b.cond. */
5890 if (opcode
->flags
& F_COND
)
5892 gas_assert (inst
.cond
!= COND_ALWAYS
);
5893 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5894 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5896 else if (inst
.cond
!= COND_ALWAYS
)
5898 /* It shouldn't arrive here, where the assembly looks like a
5899 conditional instruction but the found opcode is unconditional. */
5904 if (parse_operands (p
, opcode
)
5905 && programmer_friendly_fixup (&inst
)
5906 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5908 /* Check that this instruction is supported for this CPU. */
5909 if (!opcode
->avariant
5910 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5912 as_bad (_("selected processor does not support `%s'"), str
);
5916 warn_unpredictable_ldst (&inst
, str
);
5918 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5919 || !inst
.reloc
.need_libopcodes_p
)
5923 /* If there is relocation generated for the instruction,
5924 store the instruction information for the future fix-up. */
5925 struct aarch64_inst
*copy
;
5926 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5927 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5929 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5935 template = template->next
;
5936 if (template != NULL
)
5938 reset_aarch64_instruction (&inst
);
5939 inst
.cond
= saved_cond
;
5942 while (template != NULL
);
5944 /* Issue the error messages if any. */
5945 output_operand_error_report (str
);
5948 /* Various frobbings of labels and their addresses. */
5951 aarch64_start_line_hook (void)
5953 last_label_seen
= NULL
;
5957 aarch64_frob_label (symbolS
* sym
)
5959 last_label_seen
= sym
;
5961 dwarf2_emit_label (sym
);
5965 aarch64_data_in_code (void)
5967 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5969 *input_line_pointer
= '/';
5970 input_line_pointer
+= 5;
5971 *input_line_pointer
= 0;
5979 aarch64_canonicalize_symbol_name (char *name
)
5983 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
5984 *(name
+ len
- 5) = 0;
5989 /* Table of all register names defined by default. The user can
5990 define additional names with .req. Note that all register names
5991 should appear in both upper and lowercase variants. Some registers
5992 also have mixed-case names. */
5994 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5995 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5996 #define REGSET31(p,t) \
5997 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5998 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5999 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6000 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6001 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6002 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6003 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6004 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6005 #define REGSET(p,t) \
6006 REGSET31(p,t), REGNUM(p,31,t)
6008 /* These go into aarch64_reg_hsh hash-table. */
6009 static const reg_entry reg_names
[] = {
6010 /* Integer registers. */
6011 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6012 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6014 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6015 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6017 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6018 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6020 /* Coprocessor register numbers. */
6021 REGSET (c
, CN
), REGSET (C
, CN
),
6023 /* Floating-point single precision registers. */
6024 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6026 /* Floating-point double precision registers. */
6027 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6029 /* Floating-point half precision registers. */
6030 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6032 /* Floating-point byte precision registers. */
6033 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6035 /* Floating-point quad precision registers. */
6036 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6038 /* FP/SIMD registers. */
6039 REGSET (v
, VN
), REGSET (V
, VN
),
6054 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6055 static const asm_nzcv nzcv_names
[] = {
6056 {"nzcv", B (n
, z
, c
, v
)},
6057 {"nzcV", B (n
, z
, c
, V
)},
6058 {"nzCv", B (n
, z
, C
, v
)},
6059 {"nzCV", B (n
, z
, C
, V
)},
6060 {"nZcv", B (n
, Z
, c
, v
)},
6061 {"nZcV", B (n
, Z
, c
, V
)},
6062 {"nZCv", B (n
, Z
, C
, v
)},
6063 {"nZCV", B (n
, Z
, C
, V
)},
6064 {"Nzcv", B (N
, z
, c
, v
)},
6065 {"NzcV", B (N
, z
, c
, V
)},
6066 {"NzCv", B (N
, z
, C
, v
)},
6067 {"NzCV", B (N
, z
, C
, V
)},
6068 {"NZcv", B (N
, Z
, c
, v
)},
6069 {"NZcV", B (N
, Z
, c
, V
)},
6070 {"NZCv", B (N
, Z
, C
, v
)},
6071 {"NZCV", B (N
, Z
, C
, V
)}
6084 /* MD interface: bits in the object file. */
6086 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6087 for use in the a.out file, and stores them in the array pointed to by buf.
6088 This knows about the endian-ness of the target machine and does
6089 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6090 2 (short) and 4 (long) Floating numbers are put out as a series of
6091 LITTLENUMS (shorts, here at least). */
6094 md_number_to_chars (char *buf
, valueT val
, int n
)
6096 if (target_big_endian
)
6097 number_to_chars_bigendian (buf
, val
, n
);
6099 number_to_chars_littleendian (buf
, val
, n
);
6102 /* MD interface: Sections. */
6104 /* Estimate the size of a frag before relaxing. Assume everything fits in
6108 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6114 /* Round up a section size to the appropriate boundary. */
6117 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6122 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6123 of an rs_align_code fragment.
6125 Here we fill the frag with the appropriate info for padding the
6126 output stream. The resulting frag will consist of a fixed (fr_fix)
6127 and of a repeating (fr_var) part.
6129 The fixed content is always emitted before the repeating content and
6130 these two parts are used as follows in constructing the output:
6131 - the fixed part will be used to align to a valid instruction word
6132 boundary, in case that we start at a misaligned address; as no
6133 executable instruction can live at the misaligned location, we
6134 simply fill with zeros;
6135 - the variable part will be used to cover the remaining padding and
6136 we fill using the AArch64 NOP instruction.
6138 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6139 enough storage space for up to 3 bytes for padding the back to a valid
6140 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6143 aarch64_handle_align (fragS
* fragP
)
6145 /* NOP = d503201f */
6146 /* AArch64 instructions are always little-endian. */
6147 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6149 int bytes
, fix
, noop_size
;
6152 if (fragP
->fr_type
!= rs_align_code
)
6155 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6156 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6159 gas_assert (fragP
->tc_frag_data
.recorded
);
6162 noop_size
= sizeof (aarch64_noop
);
6164 fix
= bytes
& (noop_size
- 1);
6168 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6172 fragP
->fr_fix
+= fix
;
6176 memcpy (p
, aarch64_noop
, noop_size
);
6177 fragP
->fr_var
= noop_size
;
6180 /* Perform target specific initialisation of a frag.
6181 Note - despite the name this initialisation is not done when the frag
6182 is created, but only when its type is assigned. A frag can be created
6183 and used a long time before its type is set, so beware of assuming that
6184 this initialisationis performed first. */
6188 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6189 int max_chars ATTRIBUTE_UNUSED
)
6193 #else /* OBJ_ELF is defined. */
6195 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6197 /* Record a mapping symbol for alignment frags. We will delete this
6198 later if the alignment ends up empty. */
6199 if (!fragP
->tc_frag_data
.recorded
)
6200 fragP
->tc_frag_data
.recorded
= 1;
6202 switch (fragP
->fr_type
)
6207 mapping_state_2 (MAP_DATA
, max_chars
);
6210 mapping_state_2 (MAP_INSN
, max_chars
);
6217 /* Initialize the DWARF-2 unwind information for this procedure. */
6220 tc_aarch64_frame_initial_instructions (void)
6222 cfi_add_CFA_def_cfa (REG_SP
, 0);
6224 #endif /* OBJ_ELF */
6226 /* Convert REGNAME to a DWARF-2 register number. */
6229 tc_aarch64_regname_to_dw2regnum (char *regname
)
6231 const reg_entry
*reg
= parse_reg (®name
);
6237 case REG_TYPE_SP_32
:
6238 case REG_TYPE_SP_64
:
6248 return reg
->number
+ 64;
6256 /* Implement DWARF2_ADDR_SIZE. */
6259 aarch64_dwarf2_addr_size (void)
6261 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6265 return bfd_arch_bits_per_address (stdoutput
) / 8;
6268 /* MD interface: Symbol and relocation handling. */
6270 /* Return the address within the segment that a PC-relative fixup is
6271 relative to. For AArch64 PC-relative fixups applied to instructions
6272 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6275 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6277 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6279 /* If this is pc-relative and we are going to emit a relocation
6280 then we just want to put out any pipeline compensation that the linker
6281 will need. Otherwise we want to use the calculated base. */
6283 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6284 || aarch64_force_relocation (fixP
)))
6287 /* AArch64 should be consistent for all pc-relative relocations. */
6288 return base
+ AARCH64_PCREL_OFFSET
;
6291 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6292 Otherwise we have no need to default values of symbols. */
6295 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6298 if (name
[0] == '_' && name
[1] == 'G'
6299 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6303 if (symbol_find (name
))
6304 as_bad (_("GOT already in the symbol table"));
6306 GOT_symbol
= symbol_new (name
, undefined_section
,
6307 (valueT
) 0, &zero_address_frag
);
6317 /* Return non-zero if the indicated VALUE has overflowed the maximum
6318 range expressible by a unsigned number with the indicated number of
6322 unsigned_overflow (valueT value
, unsigned bits
)
6325 if (bits
>= sizeof (valueT
) * 8)
6327 lim
= (valueT
) 1 << bits
;
6328 return (value
>= lim
);
6332 /* Return non-zero if the indicated VALUE has overflowed the maximum
6333 range expressible by an signed number with the indicated number of
6337 signed_overflow (offsetT value
, unsigned bits
)
6340 if (bits
>= sizeof (offsetT
) * 8)
6342 lim
= (offsetT
) 1 << (bits
- 1);
6343 return (value
< -lim
|| value
>= lim
);
6346 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6347 unsigned immediate offset load/store instruction, try to encode it as
6348 an unscaled, 9-bit, signed immediate offset load/store instruction.
6349 Return TRUE if it is successful; otherwise return FALSE.
6351 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6352 in response to the standard LDR/STR mnemonics when the immediate offset is
6353 unambiguous, i.e. when it is negative or unaligned. */
6356 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6359 enum aarch64_op new_op
;
6360 const aarch64_opcode
*new_opcode
;
6362 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6364 switch (instr
->opcode
->op
)
6366 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6367 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6368 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6369 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6370 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6371 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6372 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6373 case OP_STR_POS
: new_op
= OP_STUR
; break;
6374 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6375 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6376 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6377 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6378 default: new_op
= OP_NIL
; break;
6381 if (new_op
== OP_NIL
)
6384 new_opcode
= aarch64_get_opcode (new_op
);
6385 gas_assert (new_opcode
!= NULL
);
6387 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6388 instr
->opcode
->op
, new_opcode
->op
);
6390 aarch64_replace_opcode (instr
, new_opcode
);
6392 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6393 qualifier matching may fail because the out-of-date qualifier will
6394 prevent the operand being updated with a new and correct qualifier. */
6395 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6396 AARCH64_OPND_ADDR_SIMM9
);
6397 gas_assert (idx
== 1);
6398 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6400 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6402 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6408 /* Called by fix_insn to fix a MOV immediate alias instruction.
6410 Operand for a generic move immediate instruction, which is an alias
6411 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6412 a 32-bit/64-bit immediate value into general register. An assembler error
6413 shall result if the immediate cannot be created by a single one of these
6414 instructions. If there is a choice, then to ensure reversability an
6415 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6418 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6420 const aarch64_opcode
*opcode
;
6422 /* Need to check if the destination is SP/ZR. The check has to be done
6423 before any aarch64_replace_opcode. */
6424 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6425 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6427 instr
->operands
[1].imm
.value
= value
;
6428 instr
->operands
[1].skip
= 0;
6432 /* Try the MOVZ alias. */
6433 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6434 aarch64_replace_opcode (instr
, opcode
);
6435 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6436 &instr
->value
, NULL
, NULL
))
6438 put_aarch64_insn (buf
, instr
->value
);
6441 /* Try the MOVK alias. */
6442 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6443 aarch64_replace_opcode (instr
, opcode
);
6444 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6445 &instr
->value
, NULL
, NULL
))
6447 put_aarch64_insn (buf
, instr
->value
);
6452 if (try_mov_bitmask_p
)
6454 /* Try the ORR alias. */
6455 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6456 aarch64_replace_opcode (instr
, opcode
);
6457 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6458 &instr
->value
, NULL
, NULL
))
6460 put_aarch64_insn (buf
, instr
->value
);
6465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6466 _("immediate cannot be moved by a single instruction"));
6469 /* An instruction operand which is immediate related may have symbol used
6470 in the assembly, e.g.
6473 .set u32, 0x00ffff00
6475 At the time when the assembly instruction is parsed, a referenced symbol,
6476 like 'u32' in the above example may not have been seen; a fixS is created
6477 in such a case and is handled here after symbols have been resolved.
6478 Instruction is fixed up with VALUE using the information in *FIXP plus
6479 extra information in FLAGS.
6481 This function is called by md_apply_fix to fix up instructions that need
6482 a fix-up described above but does not involve any linker-time relocation. */
6485 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6489 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6490 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6491 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6495 /* Now the instruction is about to be fixed-up, so the operand that
6496 was previously marked as 'ignored' needs to be unmarked in order
6497 to get the encoding done properly. */
6498 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6499 new_inst
->operands
[idx
].skip
= 0;
6502 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6506 case AARCH64_OPND_EXCEPTION
:
6507 if (unsigned_overflow (value
, 16))
6508 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6509 _("immediate out of range"));
6510 insn
= get_aarch64_insn (buf
);
6511 insn
|= encode_svc_imm (value
);
6512 put_aarch64_insn (buf
, insn
);
6515 case AARCH64_OPND_AIMM
:
6516 /* ADD or SUB with immediate.
6517 NOTE this assumes we come here with a add/sub shifted reg encoding
6518 3 322|2222|2 2 2 21111 111111
6519 1 098|7654|3 2 1 09876 543210 98765 43210
6520 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6521 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6522 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6523 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6525 3 322|2222|2 2 221111111111
6526 1 098|7654|3 2 109876543210 98765 43210
6527 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6528 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6529 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6530 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6531 Fields sf Rn Rd are already set. */
6532 insn
= get_aarch64_insn (buf
);
6536 insn
= reencode_addsub_switch_add_sub (insn
);
6540 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6541 && unsigned_overflow (value
, 12))
6543 /* Try to shift the value by 12 to make it fit. */
6544 if (((value
>> 12) << 12) == value
6545 && ! unsigned_overflow (value
, 12 + 12))
6548 insn
|= encode_addsub_imm_shift_amount (1);
6552 if (unsigned_overflow (value
, 12))
6553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6554 _("immediate out of range"));
6556 insn
|= encode_addsub_imm (value
);
6558 put_aarch64_insn (buf
, insn
);
6561 case AARCH64_OPND_SIMD_IMM
:
6562 case AARCH64_OPND_SIMD_IMM_SFT
:
6563 case AARCH64_OPND_LIMM
:
6564 /* Bit mask immediate. */
6565 gas_assert (new_inst
!= NULL
);
6566 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6567 new_inst
->operands
[idx
].imm
.value
= value
;
6568 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6569 &new_inst
->value
, NULL
, NULL
))
6570 put_aarch64_insn (buf
, new_inst
->value
);
6572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6573 _("invalid immediate"));
6576 case AARCH64_OPND_HALF
:
6577 /* 16-bit unsigned immediate. */
6578 if (unsigned_overflow (value
, 16))
6579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6580 _("immediate out of range"));
6581 insn
= get_aarch64_insn (buf
);
6582 insn
|= encode_movw_imm (value
& 0xffff);
6583 put_aarch64_insn (buf
, insn
);
6586 case AARCH64_OPND_IMM_MOV
:
6587 /* Operand for a generic move immediate instruction, which is
6588 an alias instruction that generates a single MOVZ, MOVN or ORR
6589 instruction to loads a 32-bit/64-bit immediate value into general
6590 register. An assembler error shall result if the immediate cannot be
6591 created by a single one of these instructions. If there is a choice,
6592 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6593 and MOVZ or MOVN to ORR. */
6594 gas_assert (new_inst
!= NULL
);
6595 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6598 case AARCH64_OPND_ADDR_SIMM7
:
6599 case AARCH64_OPND_ADDR_SIMM9
:
6600 case AARCH64_OPND_ADDR_SIMM9_2
:
6601 case AARCH64_OPND_ADDR_UIMM12
:
6602 /* Immediate offset in an address. */
6603 insn
= get_aarch64_insn (buf
);
6605 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6606 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6607 || new_inst
->opcode
->operands
[2] == opnd
);
6609 /* Get the index of the address operand. */
6610 if (new_inst
->opcode
->operands
[1] == opnd
)
6611 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6614 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6617 /* Update the resolved offset value. */
6618 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6620 /* Encode/fix-up. */
6621 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6622 &new_inst
->value
, NULL
, NULL
))
6624 put_aarch64_insn (buf
, new_inst
->value
);
6627 else if (new_inst
->opcode
->iclass
== ldst_pos
6628 && try_to_encode_as_unscaled_ldst (new_inst
))
6630 put_aarch64_insn (buf
, new_inst
->value
);
6634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6635 _("immediate offset out of range"));
6640 as_fatal (_("unhandled operand code %d"), opnd
);
6644 /* Apply a fixup (fixP) to segment data, once it has been determined
6645 by our caller that we have all the info we need to fix it up.
6647 Parameter valP is the pointer to the value of the bits. */
6650 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6652 offsetT value
= *valP
;
6654 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6656 unsigned flags
= fixP
->fx_addnumber
;
6658 DEBUG_TRACE ("\n\n");
6659 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6660 DEBUG_TRACE ("Enter md_apply_fix");
6662 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6664 /* Note whether this will delete the relocation. */
6666 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6669 /* Process the relocations. */
6670 switch (fixP
->fx_r_type
)
6672 case BFD_RELOC_NONE
:
6673 /* This will need to go in the object file. */
6678 case BFD_RELOC_8_PCREL
:
6679 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6680 md_number_to_chars (buf
, value
, 1);
6684 case BFD_RELOC_16_PCREL
:
6685 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6686 md_number_to_chars (buf
, value
, 2);
6690 case BFD_RELOC_32_PCREL
:
6691 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6692 md_number_to_chars (buf
, value
, 4);
6696 case BFD_RELOC_64_PCREL
:
6697 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6698 md_number_to_chars (buf
, value
, 8);
6701 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6702 /* We claim that these fixups have been processed here, even if
6703 in fact we generate an error because we do not have a reloc
6704 for them, so tc_gen_reloc() will reject them. */
6706 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6709 _("undefined symbol %s used as an immediate value"),
6710 S_GET_NAME (fixP
->fx_addsy
));
6711 goto apply_fix_return
;
6713 fix_insn (fixP
, flags
, value
);
6716 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6717 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6721 _("pc-relative load offset not word aligned"));
6722 if (signed_overflow (value
, 21))
6723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6724 _("pc-relative load offset out of range"));
6725 insn
= get_aarch64_insn (buf
);
6726 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6727 put_aarch64_insn (buf
, insn
);
6731 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6732 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6734 if (signed_overflow (value
, 21))
6735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6736 _("pc-relative address offset out of range"));
6737 insn
= get_aarch64_insn (buf
);
6738 insn
|= encode_adr_imm (value
);
6739 put_aarch64_insn (buf
, insn
);
6743 case BFD_RELOC_AARCH64_BRANCH19
:
6744 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6748 _("conditional branch target not word aligned"));
6749 if (signed_overflow (value
, 21))
6750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6751 _("conditional branch out of range"));
6752 insn
= get_aarch64_insn (buf
);
6753 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6754 put_aarch64_insn (buf
, insn
);
6758 case BFD_RELOC_AARCH64_TSTBR14
:
6759 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6763 _("conditional branch target not word aligned"));
6764 if (signed_overflow (value
, 16))
6765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6766 _("conditional branch out of range"));
6767 insn
= get_aarch64_insn (buf
);
6768 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6769 put_aarch64_insn (buf
, insn
);
6773 case BFD_RELOC_AARCH64_CALL26
:
6774 case BFD_RELOC_AARCH64_JUMP26
:
6775 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6779 _("branch target not word aligned"));
6780 if (signed_overflow (value
, 28))
6781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6782 _("branch out of range"));
6783 insn
= get_aarch64_insn (buf
);
6784 insn
|= encode_branch_ofs_26 (value
>> 2);
6785 put_aarch64_insn (buf
, insn
);
6789 case BFD_RELOC_AARCH64_MOVW_G0
:
6790 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6791 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6794 case BFD_RELOC_AARCH64_MOVW_G1
:
6795 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6796 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6799 case BFD_RELOC_AARCH64_MOVW_G2
:
6800 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6801 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6804 case BFD_RELOC_AARCH64_MOVW_G3
:
6807 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6809 insn
= get_aarch64_insn (buf
);
6813 /* REL signed addend must fit in 16 bits */
6814 if (signed_overflow (value
, 16))
6815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6816 _("offset out of range"));
6820 /* Check for overflow and scale. */
6821 switch (fixP
->fx_r_type
)
6823 case BFD_RELOC_AARCH64_MOVW_G0
:
6824 case BFD_RELOC_AARCH64_MOVW_G1
:
6825 case BFD_RELOC_AARCH64_MOVW_G2
:
6826 case BFD_RELOC_AARCH64_MOVW_G3
:
6827 if (unsigned_overflow (value
, scale
+ 16))
6828 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6829 _("unsigned value out of range"));
6831 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6832 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6833 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6834 /* NOTE: We can only come here with movz or movn. */
6835 if (signed_overflow (value
, scale
+ 16))
6836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6837 _("signed value out of range"));
6840 /* Force use of MOVN. */
6842 insn
= reencode_movzn_to_movn (insn
);
6846 /* Force use of MOVZ. */
6847 insn
= reencode_movzn_to_movz (insn
);
6851 /* Unchecked relocations. */
6857 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6858 insn
|= encode_movw_imm (value
& 0xffff);
6860 put_aarch64_insn (buf
, insn
);
6864 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6865 fixP
->fx_r_type
= (ilp32_p
6866 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6867 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
6868 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6869 /* Should always be exported to object file, see
6870 aarch64_force_relocation(). */
6871 gas_assert (!fixP
->fx_done
);
6872 gas_assert (seg
->use_rela_p
);
6875 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6876 fixP
->fx_r_type
= (ilp32_p
6877 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6878 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
6879 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6880 /* Should always be exported to object file, see
6881 aarch64_force_relocation(). */
6882 gas_assert (!fixP
->fx_done
);
6883 gas_assert (seg
->use_rela_p
);
6886 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6887 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6888 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6889 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6890 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6891 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6892 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6893 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6894 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6895 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6896 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6897 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6898 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6899 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
6900 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
6901 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
6902 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
6903 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
6904 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
6905 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
6906 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
6907 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
6908 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
6909 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
6910 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
6911 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
6912 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
6913 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6914 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6915 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6916 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6917 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6918 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6919 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6920 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6921 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6922 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6923 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6924 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6925 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6926 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6927 /* Should always be exported to object file, see
6928 aarch64_force_relocation(). */
6929 gas_assert (!fixP
->fx_done
);
6930 gas_assert (seg
->use_rela_p
);
6933 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6934 /* Should always be exported to object file, see
6935 aarch64_force_relocation(). */
6936 fixP
->fx_r_type
= (ilp32_p
6937 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6938 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
6939 gas_assert (!fixP
->fx_done
);
6940 gas_assert (seg
->use_rela_p
);
6943 case BFD_RELOC_AARCH64_ADD_LO12
:
6944 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6945 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6946 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6947 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6948 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6949 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
6950 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
6951 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
6952 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6953 case BFD_RELOC_AARCH64_LDST128_LO12
:
6954 case BFD_RELOC_AARCH64_LDST16_LO12
:
6955 case BFD_RELOC_AARCH64_LDST32_LO12
:
6956 case BFD_RELOC_AARCH64_LDST64_LO12
:
6957 case BFD_RELOC_AARCH64_LDST8_LO12
:
6958 /* Should always be exported to object file, see
6959 aarch64_force_relocation(). */
6960 gas_assert (!fixP
->fx_done
);
6961 gas_assert (seg
->use_rela_p
);
6964 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6965 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6966 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6969 case BFD_RELOC_UNUSED
:
6970 /* An error will already have been reported. */
6974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6975 _("unexpected %s fixup"),
6976 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6981 /* Free the allocated the struct aarch64_inst.
6982 N.B. currently there are very limited number of fix-up types actually use
6983 this field, so the impact on the performance should be minimal . */
6984 if (fixP
->tc_fix_data
.inst
!= NULL
)
6985 free (fixP
->tc_fix_data
.inst
);
6990 /* Translate internal representation of relocation info to BFD target
6994 tc_gen_reloc (asection
* section
, fixS
* fixp
)
6997 bfd_reloc_code_real_type code
;
6999 reloc
= xmalloc (sizeof (arelent
));
7001 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
7002 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7003 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7007 if (section
->use_rela_p
)
7008 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7010 fixp
->fx_offset
= reloc
->address
;
7012 reloc
->addend
= fixp
->fx_offset
;
7014 code
= fixp
->fx_r_type
;
7019 code
= BFD_RELOC_16_PCREL
;
7024 code
= BFD_RELOC_32_PCREL
;
7029 code
= BFD_RELOC_64_PCREL
;
7036 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7037 if (reloc
->howto
== NULL
)
7039 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7041 ("cannot represent %s relocation in this object file format"),
7042 bfd_get_reloc_code_name (code
));
7049 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7052 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7054 bfd_reloc_code_real_type type
;
7058 FIXME: @@ Should look at CPU word size. */
7065 type
= BFD_RELOC_16
;
7068 type
= BFD_RELOC_32
;
7071 type
= BFD_RELOC_64
;
7074 as_bad (_("cannot do %u-byte relocation"), size
);
7075 type
= BFD_RELOC_UNUSED
;
7079 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7083 aarch64_force_relocation (struct fix
*fixp
)
7085 switch (fixp
->fx_r_type
)
7087 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7088 /* Perform these "immediate" internal relocations
7089 even if the symbol is extern or weak. */
7092 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7093 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7094 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7095 /* Pseudo relocs that need to be fixed up according to
7099 case BFD_RELOC_AARCH64_ADD_LO12
:
7100 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7101 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7102 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7103 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7104 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7105 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7106 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7107 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7108 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7109 case BFD_RELOC_AARCH64_LDST128_LO12
:
7110 case BFD_RELOC_AARCH64_LDST16_LO12
:
7111 case BFD_RELOC_AARCH64_LDST32_LO12
:
7112 case BFD_RELOC_AARCH64_LDST64_LO12
:
7113 case BFD_RELOC_AARCH64_LDST8_LO12
:
7114 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7115 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7116 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7117 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7118 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7119 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7120 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7121 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7122 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7123 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7124 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7125 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7126 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7127 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7128 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7129 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7130 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7131 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7132 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7133 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7134 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7135 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7136 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7137 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7138 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7139 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7140 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7141 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7142 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7143 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7144 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7145 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7146 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7147 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7148 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7149 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7150 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7151 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7152 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7153 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7154 /* Always leave these relocations for the linker. */
7161 return generic_force_reloc (fixp
);
7167 elf64_aarch64_target_format (void)
7169 if (target_big_endian
)
7170 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7172 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7176 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7178 elf_frob_symbol (symp
, puntp
);
7182 /* MD interface: Finalization. */
7184 /* A good place to do this, although this was probably not intended
7185 for this kind of use. We need to dump the literal pool before
7186 references are made to a null symbol pointer. */
7189 aarch64_cleanup (void)
7193 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7195 /* Put it at the end of the relevant section. */
7196 subseg_set (pool
->section
, pool
->sub_section
);
7202 /* Remove any excess mapping symbols generated for alignment frags in
7203 SEC. We may have created a mapping symbol before a zero byte
7204 alignment; remove it if there's a mapping symbol after the
7207 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7208 void *dummy ATTRIBUTE_UNUSED
)
7210 segment_info_type
*seginfo
= seg_info (sec
);
7213 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7216 for (fragp
= seginfo
->frchainP
->frch_root
;
7217 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7219 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7220 fragS
*next
= fragp
->fr_next
;
7222 /* Variable-sized frags have been converted to fixed size by
7223 this point. But if this was variable-sized to start with,
7224 there will be a fixed-size frag after it. So don't handle
7226 if (sym
== NULL
|| next
== NULL
)
7229 if (S_GET_VALUE (sym
) < next
->fr_address
)
7230 /* Not at the end of this frag. */
7232 know (S_GET_VALUE (sym
) == next
->fr_address
);
7236 if (next
->tc_frag_data
.first_map
!= NULL
)
7238 /* Next frag starts with a mapping symbol. Discard this
7240 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7244 if (next
->fr_next
== NULL
)
7246 /* This mapping symbol is at the end of the section. Discard
7248 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7249 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7253 /* As long as we have empty frags without any mapping symbols,
7255 /* If the next frag is non-empty and does not start with a
7256 mapping symbol, then this mapping symbol is required. */
7257 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7260 next
= next
->fr_next
;
7262 while (next
!= NULL
);
7267 /* Adjust the symbol table. */
7270 aarch64_adjust_symtab (void)
7273 /* Remove any overlapping mapping symbols generated by alignment frags. */
7274 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7275 /* Now do generic ELF adjustments. */
7276 elf_adjust_symtab ();
7281 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7283 const char *hash_err
;
7285 hash_err
= hash_insert (table
, key
, value
);
7287 printf ("Internal Error: Can't hash %s\n", key
);
7291 fill_instruction_hash_table (void)
7293 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7295 while (opcode
->name
!= NULL
)
7297 templates
*templ
, *new_templ
;
7298 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7300 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7301 new_templ
->opcode
= opcode
;
7302 new_templ
->next
= NULL
;
7305 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7308 new_templ
->next
= templ
->next
;
7309 templ
->next
= new_templ
;
7316 convert_to_upper (char *dst
, const char *src
, size_t num
)
7319 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7320 *dst
= TOUPPER (*src
);
7324 /* Assume STR point to a lower-case string, allocate, convert and return
7325 the corresponding upper-case string. */
7326 static inline const char*
7327 get_upper_str (const char *str
)
7330 size_t len
= strlen (str
);
7331 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7333 convert_to_upper (ret
, str
, len
);
7337 /* MD interface: Initialization. */
7345 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7346 || (aarch64_cond_hsh
= hash_new ()) == NULL
7347 || (aarch64_shift_hsh
= hash_new ()) == NULL
7348 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7349 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7350 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7351 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7352 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7353 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7354 || (aarch64_reg_hsh
= hash_new ()) == NULL
7355 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7356 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7357 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
7358 as_fatal (_("virtual memory exhausted"));
7360 fill_instruction_hash_table ();
7362 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7363 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7364 (void *) (aarch64_sys_regs
+ i
));
7366 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7367 checked_hash_insert (aarch64_pstatefield_hsh
,
7368 aarch64_pstatefields
[i
].name
,
7369 (void *) (aarch64_pstatefields
+ i
));
7371 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
7372 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7373 aarch64_sys_regs_ic
[i
].template,
7374 (void *) (aarch64_sys_regs_ic
+ i
));
7376 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
7377 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7378 aarch64_sys_regs_dc
[i
].template,
7379 (void *) (aarch64_sys_regs_dc
+ i
));
7381 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
7382 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7383 aarch64_sys_regs_at
[i
].template,
7384 (void *) (aarch64_sys_regs_at
+ i
));
7386 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
7387 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7388 aarch64_sys_regs_tlbi
[i
].template,
7389 (void *) (aarch64_sys_regs_tlbi
+ i
));
7391 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7392 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7393 (void *) (reg_names
+ i
));
7395 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7396 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7397 (void *) (nzcv_names
+ i
));
7399 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7401 const char *name
= aarch64_operand_modifiers
[i
].name
;
7402 checked_hash_insert (aarch64_shift_hsh
, name
,
7403 (void *) (aarch64_operand_modifiers
+ i
));
7404 /* Also hash the name in the upper case. */
7405 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7406 (void *) (aarch64_operand_modifiers
+ i
));
7409 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7412 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7413 the same condition code. */
7414 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7416 const char *name
= aarch64_conds
[i
].names
[j
];
7419 checked_hash_insert (aarch64_cond_hsh
, name
,
7420 (void *) (aarch64_conds
+ i
));
7421 /* Also hash the name in the upper case. */
7422 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7423 (void *) (aarch64_conds
+ i
));
7427 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7429 const char *name
= aarch64_barrier_options
[i
].name
;
7430 /* Skip xx00 - the unallocated values of option. */
7433 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7434 (void *) (aarch64_barrier_options
+ i
));
7435 /* Also hash the name in the upper case. */
7436 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7437 (void *) (aarch64_barrier_options
+ i
));
7440 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7442 const char* name
= aarch64_prfops
[i
].name
;
7443 /* Skip the unallocated hint encodings. */
7446 checked_hash_insert (aarch64_pldop_hsh
, name
,
7447 (void *) (aarch64_prfops
+ i
));
7448 /* Also hash the name in the upper case. */
7449 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7450 (void *) (aarch64_prfops
+ i
));
7453 /* Set the cpu variant based on the command-line options. */
7455 mcpu_cpu_opt
= march_cpu_opt
;
7458 mcpu_cpu_opt
= &cpu_default
;
7460 cpu_variant
= *mcpu_cpu_opt
;
7462 /* Record the CPU type. */
7463 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7465 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7468 /* Command line processing. */
7470 const char *md_shortopts
= "m:";
7472 #ifdef AARCH64_BI_ENDIAN
7473 #define OPTION_EB (OPTION_MD_BASE + 0)
7474 #define OPTION_EL (OPTION_MD_BASE + 1)
7476 #if TARGET_BYTES_BIG_ENDIAN
7477 #define OPTION_EB (OPTION_MD_BASE + 0)
7479 #define OPTION_EL (OPTION_MD_BASE + 1)
7483 struct option md_longopts
[] = {
7485 {"EB", no_argument
, NULL
, OPTION_EB
},
7488 {"EL", no_argument
, NULL
, OPTION_EL
},
7490 {NULL
, no_argument
, NULL
, 0}
7493 size_t md_longopts_size
= sizeof (md_longopts
);
7495 struct aarch64_option_table
7497 char *option
; /* Option name to match. */
7498 char *help
; /* Help information. */
7499 int *var
; /* Variable to change. */
7500 int value
; /* What to change it to. */
7501 char *deprecated
; /* If non-null, print this message. */
7504 static struct aarch64_option_table aarch64_opts
[] = {
7505 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7506 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7508 #ifdef DEBUG_AARCH64
7509 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7510 #endif /* DEBUG_AARCH64 */
7511 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7513 {"mno-verbose-error", N_("do not output verbose error messages"),
7514 &verbose_error_p
, 0, NULL
},
7515 {NULL
, NULL
, NULL
, 0, NULL
}
7518 struct aarch64_cpu_option_table
7521 const aarch64_feature_set value
;
7522 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7524 const char *canonical_name
;
7527 /* This list should, at a minimum, contain all the cpu names
7528 recognized by GCC. */
7529 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7530 {"all", AARCH64_ANY
, NULL
},
7531 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7532 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7533 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7534 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7535 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7536 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7537 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7538 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7539 "Samsung Exynos M1"},
7540 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7541 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7543 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7544 in earlier releases and is superseded by 'xgene1' in all
7546 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7547 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7548 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7549 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7550 {"generic", AARCH64_ARCH_V8
, NULL
},
7552 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7555 struct aarch64_arch_option_table
7558 const aarch64_feature_set value
;
7561 /* This list should, at a minimum, contain all the architecture names
7562 recognized by GCC. */
7563 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7564 {"all", AARCH64_ANY
},
7565 {"armv8-a", AARCH64_ARCH_V8
},
7566 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7567 {NULL
, AARCH64_ARCH_NONE
}
7570 /* ISA extensions. */
7571 struct aarch64_option_cpu_value_table
7574 const aarch64_feature_set value
;
7577 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7578 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7579 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7580 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7581 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7582 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7583 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0)},
7584 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0)},
7585 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7586 | AARCH64_FEATURE_RDMA
, 0)},
7587 {NULL
, AARCH64_ARCH_NONE
}
7590 struct aarch64_long_option_table
7592 char *option
; /* Substring to match. */
7593 char *help
; /* Help information. */
7594 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7595 char *deprecated
; /* If non-null, print this message. */
7599 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7600 bfd_boolean ext_only
)
7602 /* We insist on extensions being added before being removed. We achieve
7603 this by using the ADDING_VALUE variable to indicate whether we are
7604 adding an extension (1) or removing it (0) and only allowing it to
7605 change in the order -1 -> 1 -> 0. */
7606 int adding_value
= -1;
7607 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7609 /* Copy the feature set, so that we can modify it. */
7613 while (str
!= NULL
&& *str
!= 0)
7615 const struct aarch64_option_cpu_value_table
*opt
;
7623 as_bad (_("invalid architectural extension"));
7627 ext
= strchr (++str
, '+');
7633 optlen
= strlen (str
);
7635 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7637 if (adding_value
!= 0)
7642 else if (optlen
> 0)
7644 if (adding_value
== -1)
7646 else if (adding_value
!= 1)
7648 as_bad (_("must specify extensions to add before specifying "
7649 "those to remove"));
7656 as_bad (_("missing architectural extension"));
7660 gas_assert (adding_value
!= -1);
7662 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7663 if (strncmp (opt
->name
, str
, optlen
) == 0)
7665 /* Add or remove the extension. */
7667 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7669 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7673 if (opt
->name
== NULL
)
7675 as_bad (_("unknown architectural extension `%s'"), str
);
7686 aarch64_parse_cpu (char *str
)
7688 const struct aarch64_cpu_option_table
*opt
;
7689 char *ext
= strchr (str
, '+');
7695 optlen
= strlen (str
);
7699 as_bad (_("missing cpu name `%s'"), str
);
7703 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7704 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7706 mcpu_cpu_opt
= &opt
->value
;
7708 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7713 as_bad (_("unknown cpu `%s'"), str
);
7718 aarch64_parse_arch (char *str
)
7720 const struct aarch64_arch_option_table
*opt
;
7721 char *ext
= strchr (str
, '+');
7727 optlen
= strlen (str
);
7731 as_bad (_("missing architecture name `%s'"), str
);
7735 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7736 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7738 march_cpu_opt
= &opt
->value
;
7740 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7745 as_bad (_("unknown architecture `%s'\n"), str
);
7750 struct aarch64_option_abi_value_table
7753 enum aarch64_abi_type value
;
7756 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7757 {"ilp32", AARCH64_ABI_ILP32
},
7758 {"lp64", AARCH64_ABI_LP64
},
7763 aarch64_parse_abi (char *str
)
7765 const struct aarch64_option_abi_value_table
*opt
;
7766 size_t optlen
= strlen (str
);
7770 as_bad (_("missing abi name `%s'"), str
);
7774 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
7775 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7777 aarch64_abi
= opt
->value
;
7781 as_bad (_("unknown abi `%s'\n"), str
);
7785 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7787 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7788 aarch64_parse_abi
, NULL
},
7789 #endif /* OBJ_ELF */
7790 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7791 aarch64_parse_cpu
, NULL
},
7792 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7793 aarch64_parse_arch
, NULL
},
7794 {NULL
, NULL
, 0, NULL
}
7798 md_parse_option (int c
, char *arg
)
7800 struct aarch64_option_table
*opt
;
7801 struct aarch64_long_option_table
*lopt
;
7807 target_big_endian
= 1;
7813 target_big_endian
= 0;
7818 /* Listing option. Just ignore these, we don't support additional
7823 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7825 if (c
== opt
->option
[0]
7826 && ((arg
== NULL
&& opt
->option
[1] == 0)
7827 || streq (arg
, opt
->option
+ 1)))
7829 /* If the option is deprecated, tell the user. */
7830 if (opt
->deprecated
!= NULL
)
7831 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7832 arg
? arg
: "", _(opt
->deprecated
));
7834 if (opt
->var
!= NULL
)
7835 *opt
->var
= opt
->value
;
7841 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7843 /* These options are expected to have an argument. */
7844 if (c
== lopt
->option
[0]
7846 && strncmp (arg
, lopt
->option
+ 1,
7847 strlen (lopt
->option
+ 1)) == 0)
7849 /* If the option is deprecated, tell the user. */
7850 if (lopt
->deprecated
!= NULL
)
7851 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7852 _(lopt
->deprecated
));
7854 /* Call the sup-option parser. */
7855 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7866 md_show_usage (FILE * fp
)
7868 struct aarch64_option_table
*opt
;
7869 struct aarch64_long_option_table
*lopt
;
7871 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7873 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7874 if (opt
->help
!= NULL
)
7875 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7877 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7878 if (lopt
->help
!= NULL
)
7879 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7883 -EB assemble code for a big-endian cpu\n"));
7888 -EL assemble code for a little-endian cpu\n"));
7892 /* Parse a .cpu directive. */
7895 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7897 const struct aarch64_cpu_option_table
*opt
;
7903 name
= input_line_pointer
;
7904 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7905 input_line_pointer
++;
7906 saved_char
= *input_line_pointer
;
7907 *input_line_pointer
= 0;
7909 ext
= strchr (name
, '+');
7912 optlen
= ext
- name
;
7914 optlen
= strlen (name
);
7916 /* Skip the first "all" entry. */
7917 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7918 if (strlen (opt
->name
) == optlen
7919 && strncmp (name
, opt
->name
, optlen
) == 0)
7921 mcpu_cpu_opt
= &opt
->value
;
7923 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7926 cpu_variant
= *mcpu_cpu_opt
;
7928 *input_line_pointer
= saved_char
;
7929 demand_empty_rest_of_line ();
7932 as_bad (_("unknown cpu `%s'"), name
);
7933 *input_line_pointer
= saved_char
;
7934 ignore_rest_of_line ();
7938 /* Parse a .arch directive. */
7941 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7943 const struct aarch64_arch_option_table
*opt
;
7949 name
= input_line_pointer
;
7950 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7951 input_line_pointer
++;
7952 saved_char
= *input_line_pointer
;
7953 *input_line_pointer
= 0;
7955 ext
= strchr (name
, '+');
7958 optlen
= ext
- name
;
7960 optlen
= strlen (name
);
7962 /* Skip the first "all" entry. */
7963 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7964 if (strlen (opt
->name
) == optlen
7965 && strncmp (name
, opt
->name
, optlen
) == 0)
7967 mcpu_cpu_opt
= &opt
->value
;
7969 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7972 cpu_variant
= *mcpu_cpu_opt
;
7974 *input_line_pointer
= saved_char
;
7975 demand_empty_rest_of_line ();
7979 as_bad (_("unknown architecture `%s'\n"), name
);
7980 *input_line_pointer
= saved_char
;
7981 ignore_rest_of_line ();
7984 /* Parse a .arch_extension directive. */
7987 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
7990 char *ext
= input_line_pointer
;;
7992 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7993 input_line_pointer
++;
7994 saved_char
= *input_line_pointer
;
7995 *input_line_pointer
= 0;
7997 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8000 cpu_variant
= *mcpu_cpu_opt
;
8002 *input_line_pointer
= saved_char
;
8003 demand_empty_rest_of_line ();
8006 /* Copy symbol information. */
8009 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8011 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);