1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
410 /* Stuff needed to resolve the label ambiguity
419 static symbolS
*last_label_seen
;
421 /* Literal pool structure. Held on a per-section
422 and per-sub-section basis. */
424 #define MAX_LITERAL_POOL_SIZE 1024
425 typedef struct literal_expression
428 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
429 LITTLENUM_TYPE
* bignum
;
430 } literal_expression
;
432 typedef struct literal_pool
434 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
435 unsigned int next_free_entry
;
441 struct literal_pool
*next
;
444 /* Pointer to a linked list of literal pools. */
445 static literal_pool
*list_of_pools
= NULL
;
449 /* This array holds the chars that always start a comment. If the
450 pre-processor is disabled, these aren't very useful. */
451 const char comment_chars
[] = "";
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output. */
456 /* Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output. */
459 /* Also note that comments like this one will always work. */
460 const char line_comment_chars
[] = "#";
462 const char line_separator_chars
[] = ";";
464 /* Chars that can be used to separate mant
465 from exp in floating point numbers. */
466 const char EXP_CHARS
[] = "eE";
468 /* Chars that mean this number is a floating point constant. */
472 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
474 /* Prefix character that indicates the start of an immediate value. */
475 #define is_immediate_prefix(C) ((C) == '#')
477 /* Separator character handling. */
479 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
481 static inline bfd_boolean
482 skip_past_char (char **str
, char c
)
493 #define skip_past_comma(str) skip_past_char (str, ',')
495 /* Arithmetic expressions (possibly involving symbols). */
497 static bfd_boolean in_my_get_expression_p
= FALSE
;
499 /* Third argument to my_get_expression. */
500 #define GE_NO_PREFIX 0
501 #define GE_OPT_PREFIX 1
503 /* Return TRUE if the string pointed by *STR is successfully parsed
504 as an valid expression; *EP will be filled with the information of
505 such an expression. Otherwise return FALSE. */
508 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
513 int prefix_present_p
= 0;
520 if (is_immediate_prefix (**str
))
523 prefix_present_p
= 1;
530 memset (ep
, 0, sizeof (expressionS
));
532 save_in
= input_line_pointer
;
533 input_line_pointer
= *str
;
534 in_my_get_expression_p
= TRUE
;
535 seg
= expression (ep
);
536 in_my_get_expression_p
= FALSE
;
538 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
540 /* We found a bad expression in md_operand(). */
541 *str
= input_line_pointer
;
542 input_line_pointer
= save_in
;
543 if (prefix_present_p
&& ! error_p ())
544 set_fatal_syntax_error (_("bad expression"));
546 set_first_syntax_error (_("bad expression"));
551 if (seg
!= absolute_section
552 && seg
!= text_section
553 && seg
!= data_section
554 && seg
!= bss_section
&& seg
!= undefined_section
)
556 set_syntax_error (_("bad segment"));
557 *str
= input_line_pointer
;
558 input_line_pointer
= save_in
;
565 *str
= input_line_pointer
;
566 input_line_pointer
= save_in
;
570 /* Turn a string in input_line_pointer into a floating point constant
571 of type TYPE, and store the appropriate bytes in *LITP. The number
572 of LITTLENUMS emitted is stored in *SIZEP. An error message is
573 returned, or NULL on OK. */
576 md_atof (int type
, char *litP
, int *sizeP
)
578 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
581 /* We handle all bad expressions here, so that we can report the faulty
582 instruction in the error message. */
584 md_operand (expressionS
* exp
)
586 if (in_my_get_expression_p
)
587 exp
->X_op
= O_illegal
;
590 /* Immediate values. */
592 /* Errors may be set multiple times during parsing or bit encoding
593 (particularly in the Neon bits), but usually the earliest error which is set
594 will be the most meaningful. Avoid overwriting it with later (cascading)
595 errors by calling this function. */
598 first_error (const char *error
)
601 set_syntax_error (error
);
604 /* Similiar to first_error, but this function accepts formatted error
607 first_error_fmt (const char *format
, ...)
612 /* N.B. this single buffer will not cause error messages for different
613 instructions to pollute each other; this is because at the end of
614 processing of each assembly line, error message if any will be
615 collected by as_bad. */
616 static char buffer
[size
];
620 int ret ATTRIBUTE_UNUSED
;
621 va_start (args
, format
);
622 ret
= vsnprintf (buffer
, size
, format
, args
);
623 know (ret
<= size
- 1 && ret
>= 0);
625 set_syntax_error (buffer
);
629 /* Register parsing. */
631 /* Generic register parser which is called by other specialized
633 CCP points to what should be the beginning of a register name.
634 If it is indeed a valid register name, advance CCP over it and
635 return the reg_entry structure; otherwise return NULL.
636 It does not issue diagnostics. */
639 parse_reg (char **ccp
)
645 #ifdef REGISTER_PREFIX
646 if (*start
!= REGISTER_PREFIX
)
652 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
657 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
659 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
668 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
671 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
673 if (reg
->type
== type
)
678 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
679 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
680 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
681 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
682 case REG_TYPE_VN
: /* Vector register. */
683 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
684 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
685 == reg_type_masks
[reg
->type
]);
687 as_fatal ("unhandled type %d", type
);
692 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
693 Return the register number otherwise. *ISREG32 is set to one if the
694 register is 32-bit wide; *ISREGZERO is set to one if the register is
695 of type Z_32 or Z_64.
696 Note that this function does not issue any diagnostics. */
699 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
700 int *isreg32
, int *isregzero
)
703 const reg_entry
*reg
= parse_reg (&str
);
708 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
717 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
722 *isreg32
= reg
->type
== REG_TYPE_R_32
;
729 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
741 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
742 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
743 otherwise return FALSE.
745 Accept only one occurrence of:
746 8b 16b 4h 8h 2s 4s 1d 2d
749 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
753 unsigned element_size
;
754 enum neon_el_type type
;
764 width
= strtoul (ptr
, &ptr
, 10);
765 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
767 first_error_fmt (_("bad size %d in vector width specifier"), width
);
772 switch (TOLOWER (*ptr
))
800 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
802 first_error (_("missing element size"));
805 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
808 ("invalid element size %d and vector size combination %c"),
814 parsed_type
->type
= type
;
815 parsed_type
->width
= width
;
822 /* Parse a single type, e.g. ".8b", leading period included.
823 Only applicable to Vn registers.
825 Return TRUE on success; otherwise return FALSE. */
827 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
833 if (! parse_neon_type_for_operand (vectype
, &str
))
835 first_error (_("vector type expected"));
847 /* Parse a register of the type TYPE.
849 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
850 name or the parsed register is not of TYPE.
852 Otherwise return the register number, and optionally fill in the actual
853 type of the register in *RTYPE when multiple alternatives were given, and
854 return the register shape and element index information in *TYPEINFO.
856 IN_REG_LIST should be set with TRUE if the caller is parsing a register
860 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
861 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
864 const reg_entry
*reg
= parse_reg (&str
);
865 struct neon_type_el atype
;
866 struct neon_type_el parsetype
;
867 bfd_boolean is_typed_vecreg
= FALSE
;
870 atype
.type
= NT_invtype
;
878 set_default_error ();
882 if (! aarch64_check_reg_type (reg
, type
))
884 DEBUG_TRACE ("reg type check failed");
885 set_default_error ();
890 if (type
== REG_TYPE_VN
891 && parse_neon_operand_type (&parsetype
, &str
))
893 /* Register if of the form Vn.[bhsdq]. */
894 is_typed_vecreg
= TRUE
;
896 if (parsetype
.width
== 0)
897 /* Expect index. In the new scheme we cannot have
898 Vn.[bhsdq] represent a scalar. Therefore any
899 Vn.[bhsdq] should have an index following it.
900 Except in reglists ofcourse. */
901 atype
.defined
|= NTA_HASINDEX
;
903 atype
.defined
|= NTA_HASTYPE
;
905 atype
.type
= parsetype
.type
;
906 atype
.width
= parsetype
.width
;
909 if (skip_past_char (&str
, '['))
913 /* Reject Sn[index] syntax. */
914 if (!is_typed_vecreg
)
916 first_error (_("this type of register can't be indexed"));
920 if (in_reg_list
== TRUE
)
922 first_error (_("index not allowed inside register list"));
926 atype
.defined
|= NTA_HASINDEX
;
928 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
930 if (exp
.X_op
!= O_constant
)
932 first_error (_("constant expression required"));
936 if (! skip_past_char (&str
, ']'))
939 atype
.index
= exp
.X_add_number
;
941 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
943 /* Indexed vector register expected. */
944 first_error (_("indexed vector register expected"));
948 /* A vector reg Vn should be typed or indexed. */
949 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
951 first_error (_("invalid use of vector register"));
967 Return the register number on success; return PARSE_FAIL otherwise.
969 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
970 the register (e.g. NEON double or quad reg when either has been requested).
972 If this is a NEON vector register with additional type information, fill
973 in the struct pointed to by VECTYPE (if non-NULL).
975 This parser does not handle register list. */
978 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
979 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
981 struct neon_type_el atype
;
983 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
984 /*in_reg_list= */ FALSE
);
986 if (reg
== PARSE_FAIL
)
997 static inline bfd_boolean
998 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1002 && e1
.defined
== e2
.defined
1003 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1006 /* This function parses the NEON register list. On success, it returns
1007 the parsed register list information in the following encoded format:
1009 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1010 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1012 The information of the register shape and/or index is returned in
1015 It returns PARSE_FAIL if the register list is invalid.
1017 The list contains one to four registers.
1018 Each register can be one of:
1021 All <T> should be identical.
1022 All <index> should be identical.
1023 There are restrictions on <Vt> numbers which are checked later
1024 (by reg_list_valid_p). */
1027 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1031 struct neon_type_el typeinfo
, typeinfo_first
;
1036 bfd_boolean error
= FALSE
;
1037 bfd_boolean expect_index
= FALSE
;
1041 set_syntax_error (_("expecting {"));
1047 typeinfo_first
.defined
= 0;
1048 typeinfo_first
.type
= NT_invtype
;
1049 typeinfo_first
.width
= -1;
1050 typeinfo_first
.index
= 0;
1059 str
++; /* skip over '-' */
1062 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1063 /*in_reg_list= */ TRUE
);
1064 if (val
== PARSE_FAIL
)
1066 set_first_syntax_error (_("invalid vector register in list"));
1070 /* reject [bhsd]n */
1071 if (typeinfo
.defined
== 0)
1073 set_first_syntax_error (_("invalid scalar register in list"));
1078 if (typeinfo
.defined
& NTA_HASINDEX
)
1079 expect_index
= TRUE
;
1083 if (val
< val_range
)
1085 set_first_syntax_error
1086 (_("invalid range in vector register list"));
1095 typeinfo_first
= typeinfo
;
1096 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1098 set_first_syntax_error
1099 (_("type mismatch in vector register list"));
1104 for (i
= val_range
; i
<= val
; i
++)
1106 ret_val
|= i
<< (5 * nb_regs
);
1111 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1113 skip_whitespace (str
);
1116 set_first_syntax_error (_("end of vector register list not found"));
1121 skip_whitespace (str
);
1125 if (skip_past_char (&str
, '['))
1129 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1130 if (exp
.X_op
!= O_constant
)
1132 set_first_syntax_error (_("constant expression required."));
1135 if (! skip_past_char (&str
, ']'))
1138 typeinfo_first
.index
= exp
.X_add_number
;
1142 set_first_syntax_error (_("expected index"));
1149 set_first_syntax_error (_("too many registers in vector register list"));
1152 else if (nb_regs
== 0)
1154 set_first_syntax_error (_("empty vector register list"));
1160 *vectype
= typeinfo_first
;
1162 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1165 /* Directives: register aliases. */
1168 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1173 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1176 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1179 /* Only warn about a redefinition if it's not defined as the
1181 else if (new->number
!= number
|| new->type
!= type
)
1182 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1187 name
= xstrdup (str
);
1188 new = xmalloc (sizeof (reg_entry
));
1191 new->number
= number
;
1193 new->builtin
= FALSE
;
1195 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1201 /* Look for the .req directive. This is of the form:
1203 new_register_name .req existing_register_name
1205 If we find one, or if it looks sufficiently like one that we want to
1206 handle any error here, return TRUE. Otherwise return FALSE. */
1209 create_register_alias (char *newname
, char *p
)
1211 const reg_entry
*old
;
1212 char *oldname
, *nbuf
;
1215 /* The input scrubber ensures that whitespace after the mnemonic is
1216 collapsed to single spaces. */
1218 if (strncmp (oldname
, " .req ", 6) != 0)
1222 if (*oldname
== '\0')
1225 old
= hash_find (aarch64_reg_hsh
, oldname
);
1228 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1232 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1233 the desired alias name, and p points to its end. If not, then
1234 the desired alias name is in the global original_case_string. */
1235 #ifdef TC_CASE_SENSITIVE
1238 newname
= original_case_string
;
1239 nlen
= strlen (newname
);
1242 nbuf
= alloca (nlen
+ 1);
1243 memcpy (nbuf
, newname
, nlen
);
1246 /* Create aliases under the new name as stated; an all-lowercase
1247 version of the new name; and an all-uppercase version of the new
1249 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1256 /* If this attempt to create an additional alias fails, do not bother
1257 trying to create the all-lower case alias. We will fail and issue
1258 a second, duplicate error message. This situation arises when the
1259 programmer does something like:
1262 The second .req creates the "Foo" alias but then fails to create
1263 the artificial FOO alias because it has already been created by the
1265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1269 for (p
= nbuf
; *p
; p
++)
1272 if (strncmp (nbuf
, newname
, nlen
))
1273 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1279 /* Should never be called, as .req goes between the alias and the
1280 register name, not at the beginning of the line. */
1282 s_req (int a ATTRIBUTE_UNUSED
)
1284 as_bad (_("invalid syntax for .req directive"));
1287 /* The .unreq directive deletes an alias which was previously defined
1288 by .req. For example:
1294 s_unreq (int a ATTRIBUTE_UNUSED
)
1299 name
= input_line_pointer
;
1301 while (*input_line_pointer
!= 0
1302 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1303 ++input_line_pointer
;
1305 saved_char
= *input_line_pointer
;
1306 *input_line_pointer
= 0;
1309 as_bad (_("invalid syntax for .unreq directive"));
1312 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1315 as_bad (_("unknown register alias '%s'"), name
);
1316 else if (reg
->builtin
)
1317 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1324 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1325 free ((char *) reg
->name
);
1328 /* Also locate the all upper case and all lower case versions.
1329 Do not complain if we cannot find one or the other as it
1330 was probably deleted above. */
1332 nbuf
= strdup (name
);
1333 for (p
= nbuf
; *p
; p
++)
1335 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1338 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1339 free ((char *) reg
->name
);
1343 for (p
= nbuf
; *p
; p
++)
1345 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1348 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1349 free ((char *) reg
->name
);
1357 *input_line_pointer
= saved_char
;
1358 demand_empty_rest_of_line ();
1361 /* Directives: Instruction set selection. */
1364 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1365 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1366 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1367 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1369 /* Create a new mapping symbol for the transition to STATE. */
1372 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1375 const char *symname
;
1382 type
= BSF_NO_FLAGS
;
1386 type
= BSF_NO_FLAGS
;
1392 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1393 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1395 /* Save the mapping symbols for future reference. Also check that
1396 we do not place two mapping symbols at the same offset within a
1397 frag. We'll handle overlap between frags in
1398 check_mapping_symbols.
1400 If .fill or other data filling directive generates zero sized data,
1401 the mapping symbol for the following code will have the same value
1402 as the one generated for the data filling directive. In this case,
1403 we replace the old symbol with the new one at the same address. */
1406 if (frag
->tc_frag_data
.first_map
!= NULL
)
1408 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1409 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1412 frag
->tc_frag_data
.first_map
= symbolP
;
1414 if (frag
->tc_frag_data
.last_map
!= NULL
)
1416 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1417 S_GET_VALUE (symbolP
));
1418 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1419 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1422 frag
->tc_frag_data
.last_map
= symbolP
;
1425 /* We must sometimes convert a region marked as code to data during
1426 code alignment, if an odd number of bytes have to be padded. The
1427 code mapping symbol is pushed to an aligned address. */
1430 insert_data_mapping_symbol (enum mstate state
,
1431 valueT value
, fragS
* frag
, offsetT bytes
)
1433 /* If there was already a mapping symbol, remove it. */
1434 if (frag
->tc_frag_data
.last_map
!= NULL
1435 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1436 frag
->fr_address
+ value
)
1438 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1442 know (frag
->tc_frag_data
.first_map
== symp
);
1443 frag
->tc_frag_data
.first_map
= NULL
;
1445 frag
->tc_frag_data
.last_map
= NULL
;
1446 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1449 make_mapping_symbol (MAP_DATA
, value
, frag
);
1450 make_mapping_symbol (state
, value
+ bytes
, frag
);
1453 static void mapping_state_2 (enum mstate state
, int max_chars
);
1455 /* Set the mapping state to STATE. Only call this when about to
1456 emit some STATE bytes to the file. */
1459 mapping_state (enum mstate state
)
1461 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1463 if (state
== MAP_INSN
)
1464 /* AArch64 instructions require 4-byte alignment. When emitting
1465 instructions into any section, record the appropriate section
1467 record_alignment (now_seg
, 2);
1469 if (mapstate
== state
)
1470 /* The mapping symbol has already been emitted.
1471 There is nothing else to do. */
1474 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1475 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1476 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1477 evaluated later in the next else. */
1479 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1481 /* Only add the symbol if the offset is > 0:
1482 if we're at the first frag, check it's size > 0;
1483 if we're not at the first frag, then for sure
1484 the offset is > 0. */
1485 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1486 const int add_symbol
= (frag_now
!= frag_first
)
1487 || (frag_now_fix () > 0);
1490 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1494 mapping_state_2 (state
, 0);
1497 /* Same as mapping_state, but MAX_CHARS bytes have already been
1498 allocated. Put the mapping symbol that far back. */
1501 mapping_state_2 (enum mstate state
, int max_chars
)
1503 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1505 if (!SEG_NORMAL (now_seg
))
1508 if (mapstate
== state
)
1509 /* The mapping symbol has already been emitted.
1510 There is nothing else to do. */
1513 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1514 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1517 #define mapping_state(x) /* nothing */
1518 #define mapping_state_2(x, y) /* nothing */
1521 /* Directives: sectioning and alignment. */
1524 s_bss (int ignore ATTRIBUTE_UNUSED
)
1526 /* We don't support putting frags in the BSS segment, we fake it by
1527 marking in_bss, then looking at s_skip for clues. */
1528 subseg_set (bss_section
, 0);
1529 demand_empty_rest_of_line ();
1530 mapping_state (MAP_DATA
);
1534 s_even (int ignore ATTRIBUTE_UNUSED
)
1536 /* Never make frag if expect extra pass. */
1538 frag_align (1, 0, 0);
1540 record_alignment (now_seg
, 1);
1542 demand_empty_rest_of_line ();
1545 /* Directives: Literal pools. */
1547 static literal_pool
*
1548 find_literal_pool (int size
)
1552 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1554 if (pool
->section
== now_seg
1555 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1562 static literal_pool
*
1563 find_or_make_literal_pool (int size
)
1565 /* Next literal pool ID number. */
1566 static unsigned int latest_pool_num
= 1;
1569 pool
= find_literal_pool (size
);
1573 /* Create a new pool. */
1574 pool
= xmalloc (sizeof (*pool
));
1578 /* Currently we always put the literal pool in the current text
1579 section. If we were generating "small" model code where we
1580 knew that all code and initialised data was within 1MB then
1581 we could output literals to mergeable, read-only data
1584 pool
->next_free_entry
= 0;
1585 pool
->section
= now_seg
;
1586 pool
->sub_section
= now_subseg
;
1588 pool
->next
= list_of_pools
;
1589 pool
->symbol
= NULL
;
1591 /* Add it to the list. */
1592 list_of_pools
= pool
;
1595 /* New pools, and emptied pools, will have a NULL symbol. */
1596 if (pool
->symbol
== NULL
)
1598 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1599 (valueT
) 0, &zero_address_frag
);
1600 pool
->id
= latest_pool_num
++;
1607 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1608 Return TRUE on success, otherwise return FALSE. */
1610 add_to_lit_pool (expressionS
*exp
, int size
)
1615 pool
= find_or_make_literal_pool (size
);
1617 /* Check if this literal value is already in the pool. */
1618 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1620 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1622 if ((litexp
->X_op
== exp
->X_op
)
1623 && (exp
->X_op
== O_constant
)
1624 && (litexp
->X_add_number
== exp
->X_add_number
)
1625 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1628 if ((litexp
->X_op
== exp
->X_op
)
1629 && (exp
->X_op
== O_symbol
)
1630 && (litexp
->X_add_number
== exp
->X_add_number
)
1631 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1632 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1636 /* Do we need to create a new entry? */
1637 if (entry
== pool
->next_free_entry
)
1639 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1641 set_syntax_error (_("literal pool overflow"));
1645 pool
->literals
[entry
].exp
= *exp
;
1646 pool
->next_free_entry
+= 1;
1647 if (exp
->X_op
== O_big
)
1649 /* PR 16688: Bignums are held in a single global array. We must
1650 copy and preserve that value now, before it is overwritten. */
1651 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1652 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1653 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1656 pool
->literals
[entry
].bignum
= NULL
;
1659 exp
->X_op
= O_symbol
;
1660 exp
->X_add_number
= ((int) entry
) * size
;
1661 exp
->X_add_symbol
= pool
->symbol
;
1666 /* Can't use symbol_new here, so have to create a symbol and then at
1667 a later date assign it a value. Thats what these functions do. */
1670 symbol_locate (symbolS
* symbolP
,
1671 const char *name
,/* It is copied, the caller can modify. */
1672 segT segment
, /* Segment identifier (SEG_<something>). */
1673 valueT valu
, /* Symbol value. */
1674 fragS
* frag
) /* Associated fragment. */
1677 char *preserved_copy_of_name
;
1679 name_length
= strlen (name
) + 1; /* +1 for \0. */
1680 obstack_grow (¬es
, name
, name_length
);
1681 preserved_copy_of_name
= obstack_finish (¬es
);
1683 #ifdef tc_canonicalize_symbol_name
1684 preserved_copy_of_name
=
1685 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1688 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1690 S_SET_SEGMENT (symbolP
, segment
);
1691 S_SET_VALUE (symbolP
, valu
);
1692 symbol_clear_list_pointers (symbolP
);
1694 symbol_set_frag (symbolP
, frag
);
1696 /* Link to end of symbol chain. */
1698 extern int symbol_table_frozen
;
1700 if (symbol_table_frozen
)
1704 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1706 obj_symbol_new_hook (symbolP
);
1708 #ifdef tc_symbol_new_hook
1709 tc_symbol_new_hook (symbolP
);
1713 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1714 #endif /* DEBUG_SYMS */
1719 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1726 for (align
= 2; align
<= 4; align
++)
1728 int size
= 1 << align
;
1730 pool
= find_literal_pool (size
);
1731 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1734 mapping_state (MAP_DATA
);
1736 /* Align pool as you have word accesses.
1737 Only make a frag if we have to. */
1739 frag_align (align
, 0, 0);
1741 record_alignment (now_seg
, align
);
1743 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1745 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1746 (valueT
) frag_now_fix (), frag_now
);
1747 symbol_table_insert (pool
->symbol
);
1749 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1751 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1753 if (exp
->X_op
== O_big
)
1755 /* PR 16688: Restore the global bignum value. */
1756 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1757 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1758 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1761 /* First output the expression in the instruction to the pool. */
1762 emit_expr (exp
, size
); /* .word|.xword */
1764 if (exp
->X_op
== O_big
)
1766 free (pool
->literals
[entry
].bignum
);
1767 pool
->literals
[entry
].bignum
= NULL
;
1771 /* Mark the pool as empty. */
1772 pool
->next_free_entry
= 0;
1773 pool
->symbol
= NULL
;
1778 /* Forward declarations for functions below, in the MD interface
1780 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1781 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1783 /* Directives: Data. */
1784 /* N.B. the support for relocation suffix in this directive needs to be
1785 implemented properly. */
1788 s_aarch64_elf_cons (int nbytes
)
1792 #ifdef md_flush_pending_output
1793 md_flush_pending_output ();
1796 if (is_it_end_of_statement ())
1798 demand_empty_rest_of_line ();
1802 #ifdef md_cons_align
1803 md_cons_align (nbytes
);
1806 mapping_state (MAP_DATA
);
1809 struct reloc_table_entry
*reloc
;
1813 if (exp
.X_op
!= O_symbol
)
1814 emit_expr (&exp
, (unsigned int) nbytes
);
1817 skip_past_char (&input_line_pointer
, '#');
1818 if (skip_past_char (&input_line_pointer
, ':'))
1820 reloc
= find_reloc_table_entry (&input_line_pointer
);
1822 as_bad (_("unrecognized relocation suffix"));
1824 as_bad (_("unimplemented relocation suffix"));
1825 ignore_rest_of_line ();
1829 emit_expr (&exp
, (unsigned int) nbytes
);
1832 while (*input_line_pointer
++ == ',');
1834 /* Put terminator back into stream. */
1835 input_line_pointer
--;
1836 demand_empty_rest_of_line ();
1839 #endif /* OBJ_ELF */
1841 /* Output a 32-bit word, but mark as an instruction. */
1844 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1848 #ifdef md_flush_pending_output
1849 md_flush_pending_output ();
1852 if (is_it_end_of_statement ())
1854 demand_empty_rest_of_line ();
1858 /* Sections are assumed to start aligned. In executable section, there is no
1859 MAP_DATA symbol pending. So we only align the address during
1860 MAP_DATA --> MAP_INSN transition.
1861 For other sections, this is not guaranteed. */
1862 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1863 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1864 frag_align_code (2, 0);
1867 mapping_state (MAP_INSN
);
1873 if (exp
.X_op
!= O_constant
)
1875 as_bad (_("constant expression required"));
1876 ignore_rest_of_line ();
1880 if (target_big_endian
)
1882 unsigned int val
= exp
.X_add_number
;
1883 exp
.X_add_number
= SWAP_32 (val
);
1885 emit_expr (&exp
, 4);
1887 while (*input_line_pointer
++ == ',');
1889 /* Put terminator back into stream. */
1890 input_line_pointer
--;
1891 demand_empty_rest_of_line ();
1895 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1898 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1902 /* Since we're just labelling the code, there's no need to define a
1905 /* Make sure there is enough room in this frag for the following
1906 blr. This trick only works if the blr follows immediately after
1907 the .tlsdesc directive. */
1909 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1910 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1912 demand_empty_rest_of_line ();
1914 #endif /* OBJ_ELF */
1916 static void s_aarch64_arch (int);
1917 static void s_aarch64_cpu (int);
1918 static void s_aarch64_arch_extension (int);
1920 /* This table describes all the machine specific pseudo-ops the assembler
1921 has to support. The fields are:
1922 pseudo-op name without dot
1923 function to call to execute this pseudo-op
1924 Integer arg to pass to the function. */
1926 const pseudo_typeS md_pseudo_table
[] = {
1927 /* Never called because '.req' does not start a line. */
1929 {"unreq", s_unreq
, 0},
1931 {"even", s_even
, 0},
1932 {"ltorg", s_ltorg
, 0},
1933 {"pool", s_ltorg
, 0},
1934 {"cpu", s_aarch64_cpu
, 0},
1935 {"arch", s_aarch64_arch
, 0},
1936 {"arch_extension", s_aarch64_arch_extension
, 0},
1937 {"inst", s_aarch64_inst
, 0},
1939 {"tlsdesccall", s_tlsdesccall
, 0},
1940 {"word", s_aarch64_elf_cons
, 4},
1941 {"long", s_aarch64_elf_cons
, 4},
1942 {"xword", s_aarch64_elf_cons
, 8},
1943 {"dword", s_aarch64_elf_cons
, 8},
1949 /* Check whether STR points to a register name followed by a comma or the
1950 end of line; REG_TYPE indicates which register types are checked
1951 against. Return TRUE if STR is such a register name; otherwise return
1952 FALSE. The function does not intend to produce any diagnostics, but since
1953 the register parser aarch64_reg_parse, which is called by this function,
1954 does produce diagnostics, we call clear_error to clear any diagnostics
1955 that may be generated by aarch64_reg_parse.
1956 Also, the function returns FALSE directly if there is any user error
1957 present at the function entry. This prevents the existing diagnostics
1958 state from being spoiled.
1959 The function currently serves parse_constant_immediate and
1960 parse_big_immediate only. */
1962 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1966 /* Prevent the diagnostics state from being spoiled. */
1970 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1972 /* Clear the parsing error that may be set by the reg parser. */
1975 if (reg
== PARSE_FAIL
)
1978 skip_whitespace (str
);
1979 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1985 /* Parser functions used exclusively in instruction operands. */
1987 /* Parse an immediate expression which may not be constant.
1989 To prevent the expression parser from pushing a register name
1990 into the symbol table as an undefined symbol, firstly a check is
1991 done to find out whether STR is a valid register name followed
1992 by a comma or the end of line. Return FALSE if STR is such a
1996 parse_immediate_expression (char **str
, expressionS
*exp
)
1998 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2000 set_recoverable_error (_("immediate operand required"));
2004 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2006 if (exp
->X_op
== O_absent
)
2008 set_fatal_syntax_error (_("missing immediate expression"));
2015 /* Constant immediate-value read function for use in insn parsing.
2016 STR points to the beginning of the immediate (with the optional
2017 leading #); *VAL receives the value.
2019 Return TRUE on success; otherwise return FALSE. */
2022 parse_constant_immediate (char **str
, int64_t * val
)
2026 if (! parse_immediate_expression (str
, &exp
))
2029 if (exp
.X_op
!= O_constant
)
2031 set_syntax_error (_("constant expression required"));
2035 *val
= exp
.X_add_number
;
2040 encode_imm_float_bits (uint32_t imm
)
2042 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2043 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2046 /* Return TRUE if the single-precision floating-point value encoded in IMM
2047 can be expressed in the AArch64 8-bit signed floating-point format with
2048 3-bit exponent and normalized 4 bits of precision; in other words, the
2049 floating-point value must be expressable as
2050 (+/-) n / 16 * power (2, r)
2051 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2054 aarch64_imm_float_p (uint32_t imm
)
2056 /* If a single-precision floating-point value has the following bit
2057 pattern, it can be expressed in the AArch64 8-bit floating-point
2060 3 32222222 2221111111111
2061 1 09876543 21098765432109876543210
2062 n Eeeeeexx xxxx0000000000000000000
2064 where n, e and each x are either 0 or 1 independently, with
2069 /* Prepare the pattern for 'Eeeeee'. */
2070 if (((imm
>> 30) & 0x1) == 0)
2071 pattern
= 0x3e000000;
2073 pattern
= 0x40000000;
2075 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2076 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2079 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2081 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2082 8-bit signed floating-point format with 3-bit exponent and normalized 4
2083 bits of precision (i.e. can be used in an FMOV instruction); return the
2084 equivalent single-precision encoding in *FPWORD.
2086 Otherwise return FALSE. */
2089 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2091 /* If a double-precision floating-point value has the following bit
2092 pattern, it can be expressed in the AArch64 8-bit floating-point
2095 6 66655555555 554444444...21111111111
2096 3 21098765432 109876543...098765432109876543210
2097 n Eeeeeeeeexx xxxx00000...000000000000000000000
2099 where n, e and each x are either 0 or 1 independently, with
2103 uint32_t high32
= imm
>> 32;
2105 /* Lower 32 bits need to be 0s. */
2106 if ((imm
& 0xffffffff) != 0)
2109 /* Prepare the pattern for 'Eeeeeeeee'. */
2110 if (((high32
>> 30) & 0x1) == 0)
2111 pattern
= 0x3fc00000;
2113 pattern
= 0x40000000;
2115 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2116 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2118 /* Convert to the single-precision encoding.
2120 n Eeeeeeeeexx xxxx00000...000000000000000000000
2122 n Eeeeeexx xxxx0000000000000000000. */
2123 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2124 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2131 /* Parse a floating-point immediate. Return TRUE on success and return the
2132 value in *IMMED in the format of IEEE754 single-precision encoding.
2133 *CCP points to the start of the string; DP_P is TRUE when the immediate
2134 is expected to be in double-precision (N.B. this only matters when
2135 hexadecimal representation is involved).
2137 N.B. 0.0 is accepted by this function. */
2140 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2144 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2145 int found_fpchar
= 0;
2147 unsigned fpword
= 0;
2148 bfd_boolean hex_p
= FALSE
;
2150 skip_past_char (&str
, '#');
2153 skip_whitespace (fpnum
);
2155 if (strncmp (fpnum
, "0x", 2) == 0)
2157 /* Support the hexadecimal representation of the IEEE754 encoding.
2158 Double-precision is expected when DP_P is TRUE, otherwise the
2159 representation should be in single-precision. */
2160 if (! parse_constant_immediate (&str
, &val
))
2165 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2168 else if ((uint64_t) val
> 0xffffffff)
2177 /* We must not accidentally parse an integer as a floating-point number.
2178 Make sure that the value we parse is not an integer by checking for
2179 special characters '.' or 'e'. */
2180 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2181 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2195 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2198 /* Our FP word must be 32 bits (single-precision FP). */
2199 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2201 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2206 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2214 set_fatal_syntax_error (_("invalid floating-point constant"));
2218 /* Less-generic immediate-value read function with the possibility of loading
2219 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2222 To prevent the expression parser from pushing a register name into the
2223 symbol table as an undefined symbol, a check is firstly done to find
2224 out whether STR is a valid register name followed by a comma or the end
2225 of line. Return FALSE if STR is such a register. */
2228 parse_big_immediate (char **str
, int64_t *imm
)
2232 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2234 set_syntax_error (_("immediate operand required"));
2238 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2240 if (inst
.reloc
.exp
.X_op
== O_constant
)
2241 *imm
= inst
.reloc
.exp
.X_add_number
;
2248 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2249 if NEED_LIBOPCODES is non-zero, the fixup will need
2250 assistance from the libopcodes. */
2253 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2254 const aarch64_opnd_info
*operand
,
2255 int need_libopcodes_p
)
2257 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2258 reloc
->opnd
= operand
->type
;
2259 if (need_libopcodes_p
)
2260 reloc
->need_libopcodes_p
= 1;
2263 /* Return TRUE if the instruction needs to be fixed up later internally by
2264 the GAS; otherwise return FALSE. */
2266 static inline bfd_boolean
2267 aarch64_gas_internal_fixup_p (void)
2269 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2272 /* Assign the immediate value to the relavant field in *OPERAND if
2273 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2274 needs an internal fixup in a later stage.
2275 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2276 IMM.VALUE that may get assigned with the constant. */
2278 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2279 aarch64_opnd_info
*operand
,
2281 int need_libopcodes_p
,
2284 if (reloc
->exp
.X_op
== O_constant
)
2287 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2289 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2290 reloc
->type
= BFD_RELOC_UNUSED
;
2294 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2295 /* Tell libopcodes to ignore this operand or not. This is helpful
2296 when one of the operands needs to be fixed up later but we need
2297 libopcodes to check the other operands. */
2298 operand
->skip
= skip_p
;
2302 /* Relocation modifiers. Each entry in the table contains the textual
2303 name for the relocation which may be placed before a symbol used as
2304 a load/store offset, or add immediate. It must be surrounded by a
2305 leading and trailing colon, for example:
2307 ldr x0, [x1, #:rello:varsym]
2308 add x0, x1, #:rello:varsym */
2310 struct reloc_table_entry
2314 bfd_reloc_code_real_type adr_type
;
2315 bfd_reloc_code_real_type adrp_type
;
2316 bfd_reloc_code_real_type movw_type
;
2317 bfd_reloc_code_real_type add_type
;
2318 bfd_reloc_code_real_type ldst_type
;
2319 bfd_reloc_code_real_type ld_literal_type
;
2322 static struct reloc_table_entry reloc_table
[] = {
2323 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2328 BFD_RELOC_AARCH64_ADD_LO12
,
2329 BFD_RELOC_AARCH64_LDST_LO12
,
2332 /* Higher 21 bits of pc-relative page offset: ADRP */
2335 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2341 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2344 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2350 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2354 BFD_RELOC_AARCH64_MOVW_G0
,
2359 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2363 BFD_RELOC_AARCH64_MOVW_G0_S
,
2368 /* Less significant bits 0-15 of address/value: MOVK, no check */
2372 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2377 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2381 BFD_RELOC_AARCH64_MOVW_G1
,
2386 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2390 BFD_RELOC_AARCH64_MOVW_G1_S
,
2395 /* Less significant bits 16-31 of address/value: MOVK, no check */
2399 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2404 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2408 BFD_RELOC_AARCH64_MOVW_G2
,
2413 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2417 BFD_RELOC_AARCH64_MOVW_G2_S
,
2422 /* Less significant bits 32-47 of address/value: MOVK, no check */
2426 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2431 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2435 BFD_RELOC_AARCH64_MOVW_G3
,
2440 /* Get to the page containing GOT entry for a symbol. */
2443 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2447 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2449 /* 12 bit offset into the page containing GOT entry for that symbol. */
2455 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2458 /* 15 bit offset into the page containing GOT entry for that symbol. */
2464 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2467 /* Get to the page containing GOT TLS entry for a symbol */
2469 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2470 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2476 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2481 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2485 /* Get to the page containing GOT TLS entry for a symbol */
2487 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2488 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2492 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2494 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2499 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2500 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2503 /* Get to the page containing GOT TLS entry for a symbol */
2506 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2510 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2512 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2513 {"gottprel_lo12", 0,
2518 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2521 /* Get tp offset for a symbol. */
2526 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2530 /* Get tp offset for a symbol. */
2535 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2539 /* Get tp offset for a symbol. */
2544 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2548 /* Get tp offset for a symbol. */
2549 {"tprel_lo12_nc", 0,
2553 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2557 /* Most significant bits 32-47 of address/value: MOVZ. */
2561 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2566 /* Most significant bits 16-31 of address/value: MOVZ. */
2570 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2575 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2579 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2584 /* Most significant bits 0-15 of address/value: MOVZ. */
2588 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2593 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2597 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2602 /* 15bit offset from got entry to base address of GOT table. */
2608 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2611 /* 14bit offset from got entry to base address of GOT table. */
2617 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2621 /* Given the address of a pointer pointing to the textual name of a
2622 relocation as may appear in assembler source, attempt to find its
2623 details in reloc_table. The pointer will be updated to the character
2624 after the trailing colon. On failure, NULL will be returned;
2625 otherwise return the reloc_table_entry. */
2627 static struct reloc_table_entry
*
2628 find_reloc_table_entry (char **str
)
2631 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2633 int length
= strlen (reloc_table
[i
].name
);
2635 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2636 && (*str
)[length
] == ':')
2638 *str
+= (length
+ 1);
2639 return &reloc_table
[i
];
2646 /* Mode argument to parse_shift and parser_shifter_operand. */
2647 enum parse_shift_mode
2649 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2651 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2653 SHIFTED_LSL
, /* bare "lsl #n" */
2654 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2655 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2658 /* Parse a <shift> operator on an AArch64 data processing instruction.
2659 Return TRUE on success; otherwise return FALSE. */
2661 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2663 const struct aarch64_name_value_pair
*shift_op
;
2664 enum aarch64_modifier_kind kind
;
2670 for (p
= *str
; ISALPHA (*p
); p
++)
2675 set_syntax_error (_("shift expression expected"));
2679 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2681 if (shift_op
== NULL
)
2683 set_syntax_error (_("shift operator expected"));
2687 kind
= aarch64_get_operand_modifier (shift_op
);
2689 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2691 set_syntax_error (_("invalid use of 'MSL'"));
2697 case SHIFTED_LOGIC_IMM
:
2698 if (aarch64_extend_operator_p (kind
) == TRUE
)
2700 set_syntax_error (_("extending shift is not permitted"));
2705 case SHIFTED_ARITH_IMM
:
2706 if (kind
== AARCH64_MOD_ROR
)
2708 set_syntax_error (_("'ROR' shift is not permitted"));
2714 if (kind
!= AARCH64_MOD_LSL
)
2716 set_syntax_error (_("only 'LSL' shift is permitted"));
2721 case SHIFTED_REG_OFFSET
:
2722 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2723 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2725 set_fatal_syntax_error
2726 (_("invalid shift for the register offset addressing mode"));
2731 case SHIFTED_LSL_MSL
:
2732 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2734 set_syntax_error (_("invalid shift operator"));
2743 /* Whitespace can appear here if the next thing is a bare digit. */
2744 skip_whitespace (p
);
2746 /* Parse shift amount. */
2748 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2749 exp
.X_op
= O_absent
;
2752 if (is_immediate_prefix (*p
))
2757 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2759 if (exp
.X_op
== O_absent
)
2761 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2763 set_syntax_error (_("missing shift amount"));
2766 operand
->shifter
.amount
= 0;
2768 else if (exp
.X_op
!= O_constant
)
2770 set_syntax_error (_("constant shift amount required"));
2773 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2775 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2780 operand
->shifter
.amount
= exp
.X_add_number
;
2781 operand
->shifter
.amount_present
= 1;
2784 operand
->shifter
.operator_present
= 1;
2785 operand
->shifter
.kind
= kind
;
2791 /* Parse a <shifter_operand> for a data processing instruction:
2794 #<immediate>, LSL #imm
2796 Validation of immediate operands is deferred to md_apply_fix.
2798 Return TRUE on success; otherwise return FALSE. */
2801 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2802 enum parse_shift_mode mode
)
2806 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2811 /* Accept an immediate expression. */
2812 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2815 /* Accept optional LSL for arithmetic immediate values. */
2816 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2817 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2820 /* Not accept any shifter for logical immediate values. */
2821 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2822 && parse_shift (&p
, operand
, mode
))
2824 set_syntax_error (_("unexpected shift operator"));
2832 /* Parse a <shifter_operand> for a data processing instruction:
2837 #<immediate>, LSL #imm
2839 where <shift> is handled by parse_shift above, and the last two
2840 cases are handled by the function above.
2842 Validation of immediate operands is deferred to md_apply_fix.
2844 Return TRUE on success; otherwise return FALSE. */
2847 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2848 enum parse_shift_mode mode
)
2851 int isreg32
, isregzero
;
2852 enum aarch64_operand_class opd_class
2853 = aarch64_get_operand_class (operand
->type
);
2856 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2858 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2860 set_syntax_error (_("unexpected register in the immediate operand"));
2864 if (!isregzero
&& reg
== REG_SP
)
2866 set_syntax_error (BAD_SP
);
2870 operand
->reg
.regno
= reg
;
2871 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2873 /* Accept optional shift operation on register. */
2874 if (! skip_past_comma (str
))
2877 if (! parse_shift (str
, operand
, mode
))
2882 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2885 (_("integer register expected in the extended/shifted operand "
2890 /* We have a shifted immediate variable. */
2891 return parse_shifter_operand_imm (str
, operand
, mode
);
2894 /* Return TRUE on success; return FALSE otherwise. */
2897 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
2898 enum parse_shift_mode mode
)
2902 /* Determine if we have the sequence of characters #: or just :
2903 coming next. If we do, then we check for a :rello: relocation
2904 modifier. If we don't, punt the whole lot to
2905 parse_shifter_operand. */
2907 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
2909 struct reloc_table_entry
*entry
;
2917 /* Try to parse a relocation. Anything else is an error. */
2918 if (!(entry
= find_reloc_table_entry (str
)))
2920 set_syntax_error (_("unknown relocation modifier"));
2924 if (entry
->add_type
== 0)
2927 (_("this relocation modifier is not allowed on this instruction"));
2931 /* Save str before we decompose it. */
2934 /* Next, we parse the expression. */
2935 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
2938 /* Record the relocation type (use the ADD variant here). */
2939 inst
.reloc
.type
= entry
->add_type
;
2940 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2942 /* If str is empty, we've reached the end, stop here. */
2946 /* Otherwise, we have a shifted reloc modifier, so rewind to
2947 recover the variable name and continue parsing for the shifter. */
2949 return parse_shifter_operand_imm (str
, operand
, mode
);
2952 return parse_shifter_operand (str
, operand
, mode
);
2955 /* Parse all forms of an address expression. Information is written
2956 to *OPERAND and/or inst.reloc.
2958 The A64 instruction set has the following addressing modes:
2961 [base] // in SIMD ld/st structure
2962 [base{,#0}] // in ld/st exclusive
2964 [base,Xm{,LSL #imm}]
2965 [base,Xm,SXTX {#imm}]
2966 [base,Wm,(S|U)XTW {#imm}]
2971 [base],Xm // in SIMD ld/st structure
2972 PC-relative (literal)
2976 (As a convenience, the notation "=immediate" is permitted in conjunction
2977 with the pc-relative literal load instructions to automatically place an
2978 immediate value or symbolic address in a nearby literal pool and generate
2979 a hidden label which references it.)
2981 Upon a successful parsing, the address structure in *OPERAND will be
2982 filled in the following way:
2984 .base_regno = <base>
2985 .offset.is_reg // 1 if the offset is a register
2987 .offset.regno = <Rm>
2989 For different addressing modes defined in the A64 ISA:
2992 .pcrel=0; .preind=1; .postind=0; .writeback=0
2994 .pcrel=0; .preind=1; .postind=0; .writeback=1
2996 .pcrel=0; .preind=0; .postind=1; .writeback=1
2997 PC-relative (literal)
2998 .pcrel=1; .preind=1; .postind=0; .writeback=0
3000 The shift/extension information, if any, will be stored in .shifter.
3002 It is the caller's responsibility to check for addressing modes not
3003 supported by the instruction, and to set inst.reloc.type. */
3006 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3007 int accept_reg_post_index
)
3011 int isreg32
, isregzero
;
3012 expressionS
*exp
= &inst
.reloc
.exp
;
3014 if (! skip_past_char (&p
, '['))
3016 /* =immediate or label. */
3017 operand
->addr
.pcrel
= 1;
3018 operand
->addr
.preind
= 1;
3020 /* #:<reloc_op>:<symbol> */
3021 skip_past_char (&p
, '#');
3022 if (reloc
&& skip_past_char (&p
, ':'))
3024 bfd_reloc_code_real_type ty
;
3025 struct reloc_table_entry
*entry
;
3027 /* Try to parse a relocation modifier. Anything else is
3029 entry
= find_reloc_table_entry (&p
);
3032 set_syntax_error (_("unknown relocation modifier"));
3036 switch (operand
->type
)
3038 case AARCH64_OPND_ADDR_PCREL21
:
3040 ty
= entry
->adr_type
;
3044 ty
= entry
->ld_literal_type
;
3051 (_("this relocation modifier is not allowed on this "
3057 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3059 set_syntax_error (_("invalid relocation expression"));
3063 /* #:<reloc_op>:<expr> */
3064 /* Record the relocation type. */
3065 inst
.reloc
.type
= ty
;
3066 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3071 if (skip_past_char (&p
, '='))
3072 /* =immediate; need to generate the literal in the literal pool. */
3073 inst
.gen_lit_pool
= 1;
3075 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3077 set_syntax_error (_("invalid address"));
3088 /* Accept SP and reject ZR */
3089 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3090 if (reg
== PARSE_FAIL
|| isreg32
)
3092 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3095 operand
->addr
.base_regno
= reg
;
3098 if (skip_past_comma (&p
))
3101 operand
->addr
.preind
= 1;
3103 /* Reject SP and accept ZR */
3104 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3105 if (reg
!= PARSE_FAIL
)
3108 operand
->addr
.offset
.regno
= reg
;
3109 operand
->addr
.offset
.is_reg
= 1;
3110 /* Shifted index. */
3111 if (skip_past_comma (&p
))
3114 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3115 /* Use the diagnostics set in parse_shift, so not set new
3116 error message here. */
3120 [base,Xm{,LSL #imm}]
3121 [base,Xm,SXTX {#imm}]
3122 [base,Wm,(S|U)XTW {#imm}] */
3123 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3124 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3125 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3129 set_syntax_error (_("invalid use of 32-bit register offset"));
3135 set_syntax_error (_("invalid use of 64-bit register offset"));
3141 /* [Xn,#:<reloc_op>:<symbol> */
3142 skip_past_char (&p
, '#');
3143 if (reloc
&& skip_past_char (&p
, ':'))
3145 struct reloc_table_entry
*entry
;
3147 /* Try to parse a relocation modifier. Anything else is
3149 if (!(entry
= find_reloc_table_entry (&p
)))
3151 set_syntax_error (_("unknown relocation modifier"));
3155 if (entry
->ldst_type
== 0)
3158 (_("this relocation modifier is not allowed on this "
3163 /* [Xn,#:<reloc_op>: */
3164 /* We now have the group relocation table entry corresponding to
3165 the name in the assembler source. Next, we parse the
3167 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3169 set_syntax_error (_("invalid relocation expression"));
3173 /* [Xn,#:<reloc_op>:<expr> */
3174 /* Record the load/store relocation type. */
3175 inst
.reloc
.type
= entry
->ldst_type
;
3176 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3178 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3180 set_syntax_error (_("invalid expression in the address"));
3187 if (! skip_past_char (&p
, ']'))
3189 set_syntax_error (_("']' expected"));
3193 if (skip_past_char (&p
, '!'))
3195 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3197 set_syntax_error (_("register offset not allowed in pre-indexed "
3198 "addressing mode"));
3202 operand
->addr
.writeback
= 1;
3204 else if (skip_past_comma (&p
))
3207 operand
->addr
.postind
= 1;
3208 operand
->addr
.writeback
= 1;
3210 if (operand
->addr
.preind
)
3212 set_syntax_error (_("cannot combine pre- and post-indexing"));
3216 if (accept_reg_post_index
3217 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3218 &isregzero
)) != PARSE_FAIL
)
3223 set_syntax_error (_("invalid 32-bit register offset"));
3226 operand
->addr
.offset
.regno
= reg
;
3227 operand
->addr
.offset
.is_reg
= 1;
3229 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3232 set_syntax_error (_("invalid expression in the address"));
3237 /* If at this point neither .preind nor .postind is set, we have a
3238 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3239 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3241 if (operand
->addr
.writeback
)
3244 set_syntax_error (_("missing offset in the pre-indexed address"));
3247 operand
->addr
.preind
= 1;
3248 inst
.reloc
.exp
.X_op
= O_constant
;
3249 inst
.reloc
.exp
.X_add_number
= 0;
3256 /* Return TRUE on success; otherwise return FALSE. */
3258 parse_address (char **str
, aarch64_opnd_info
*operand
,
3259 int accept_reg_post_index
)
3261 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3264 /* Return TRUE on success; otherwise return FALSE. */
3266 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3268 return parse_address_main (str
, operand
, 1, 0);
3271 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3272 Return TRUE on success; otherwise return FALSE. */
3274 parse_half (char **str
, int *internal_fixup_p
)
3280 skip_past_char (&p
, '#');
3282 gas_assert (internal_fixup_p
);
3283 *internal_fixup_p
= 0;
3287 struct reloc_table_entry
*entry
;
3289 /* Try to parse a relocation. Anything else is an error. */
3291 if (!(entry
= find_reloc_table_entry (&p
)))
3293 set_syntax_error (_("unknown relocation modifier"));
3297 if (entry
->movw_type
== 0)
3300 (_("this relocation modifier is not allowed on this instruction"));
3304 inst
.reloc
.type
= entry
->movw_type
;
3307 *internal_fixup_p
= 1;
3309 /* Avoid parsing a register as a general symbol. */
3311 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3315 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3322 /* Parse an operand for an ADRP instruction:
3324 Return TRUE on success; otherwise return FALSE. */
3327 parse_adrp (char **str
)
3334 struct reloc_table_entry
*entry
;
3336 /* Try to parse a relocation. Anything else is an error. */
3338 if (!(entry
= find_reloc_table_entry (&p
)))
3340 set_syntax_error (_("unknown relocation modifier"));
3344 if (entry
->adrp_type
== 0)
3347 (_("this relocation modifier is not allowed on this instruction"));
3351 inst
.reloc
.type
= entry
->adrp_type
;
3354 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3356 inst
.reloc
.pc_rel
= 1;
3358 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3365 /* Miscellaneous. */
3367 /* Parse an option for a preload instruction. Returns the encoding for the
3368 option, or PARSE_FAIL. */
3371 parse_pldop (char **str
)
3374 const struct aarch64_name_value_pair
*o
;
3377 while (ISALNUM (*q
))
3380 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3388 /* Parse an option for a barrier instruction. Returns the encoding for the
3389 option, or PARSE_FAIL. */
3392 parse_barrier (char **str
)
3395 const asm_barrier_opt
*o
;
3398 while (ISALPHA (*q
))
3401 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3409 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3410 Returns the encoding for the option, or PARSE_FAIL.
3412 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3413 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3415 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3416 field, otherwise as a system register.
3420 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3421 int imple_defined_p
, int pstatefield_p
)
3425 const aarch64_sys_reg
*o
;
3429 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3431 *p
++ = TOLOWER (*q
);
3433 /* Assert that BUF be large enough. */
3434 gas_assert (p
- buf
== q
- *str
);
3436 o
= hash_find (sys_regs
, buf
);
3439 if (!imple_defined_p
)
3443 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3444 unsigned int op0
, op1
, cn
, cm
, op2
;
3446 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3449 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3451 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3456 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3457 as_bad (_("selected processor does not support PSTATE field "
3459 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3460 as_bad (_("selected processor does not support system register "
3462 if (aarch64_sys_reg_deprecated_p (o
))
3463 as_warn (_("system register name '%s' is deprecated and may be "
3464 "removed in a future release"), buf
);
3472 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3473 for the option, or NULL. */
3475 static const aarch64_sys_ins_reg
*
3476 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3480 const aarch64_sys_ins_reg
*o
;
3483 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3485 *p
++ = TOLOWER (*q
);
3488 o
= hash_find (sys_ins_regs
, buf
);
3496 #define po_char_or_fail(chr) do { \
3497 if (! skip_past_char (&str, chr)) \
3501 #define po_reg_or_fail(regtype) do { \
3502 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3503 if (val == PARSE_FAIL) \
3505 set_default_error (); \
3510 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3511 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3512 &isreg32, &isregzero); \
3513 if (val == PARSE_FAIL) \
3515 set_default_error (); \
3518 info->reg.regno = val; \
3520 info->qualifier = AARCH64_OPND_QLF_W; \
3522 info->qualifier = AARCH64_OPND_QLF_X; \
3525 #define po_imm_nc_or_fail() do { \
3526 if (! parse_constant_immediate (&str, &val)) \
3530 #define po_imm_or_fail(min, max) do { \
3531 if (! parse_constant_immediate (&str, &val)) \
3533 if (val < min || val > max) \
3535 set_fatal_syntax_error (_("immediate value out of range "\
3536 #min " to "#max)); \
3541 #define po_misc_or_fail(expr) do { \
3546 /* encode the 12-bit imm field of Add/sub immediate */
3547 static inline uint32_t
3548 encode_addsub_imm (uint32_t imm
)
3553 /* encode the shift amount field of Add/sub immediate */
3554 static inline uint32_t
3555 encode_addsub_imm_shift_amount (uint32_t cnt
)
3561 /* encode the imm field of Adr instruction */
3562 static inline uint32_t
3563 encode_adr_imm (uint32_t imm
)
3565 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3566 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3569 /* encode the immediate field of Move wide immediate */
3570 static inline uint32_t
3571 encode_movw_imm (uint32_t imm
)
3576 /* encode the 26-bit offset of unconditional branch */
3577 static inline uint32_t
3578 encode_branch_ofs_26 (uint32_t ofs
)
3580 return ofs
& ((1 << 26) - 1);
3583 /* encode the 19-bit offset of conditional branch and compare & branch */
3584 static inline uint32_t
3585 encode_cond_branch_ofs_19 (uint32_t ofs
)
3587 return (ofs
& ((1 << 19) - 1)) << 5;
3590 /* encode the 19-bit offset of ld literal */
3591 static inline uint32_t
3592 encode_ld_lit_ofs_19 (uint32_t ofs
)
3594 return (ofs
& ((1 << 19) - 1)) << 5;
3597 /* Encode the 14-bit offset of test & branch. */
3598 static inline uint32_t
3599 encode_tst_branch_ofs_14 (uint32_t ofs
)
3601 return (ofs
& ((1 << 14) - 1)) << 5;
3604 /* Encode the 16-bit imm field of svc/hvc/smc. */
3605 static inline uint32_t
3606 encode_svc_imm (uint32_t imm
)
3611 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3612 static inline uint32_t
3613 reencode_addsub_switch_add_sub (uint32_t opcode
)
3615 return opcode
^ (1 << 30);
3618 static inline uint32_t
3619 reencode_movzn_to_movz (uint32_t opcode
)
3621 return opcode
| (1 << 30);
3624 static inline uint32_t
3625 reencode_movzn_to_movn (uint32_t opcode
)
3627 return opcode
& ~(1 << 30);
3630 /* Overall per-instruction processing. */
3632 /* We need to be able to fix up arbitrary expressions in some statements.
3633 This is so that we can handle symbols that are an arbitrary distance from
3634 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3635 which returns part of an address in a form which will be valid for
3636 a data instruction. We do this by pushing the expression into a symbol
3637 in the expr_section, and creating a fix for that. */
3640 fix_new_aarch64 (fragS
* frag
,
3642 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3652 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3656 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3663 /* Diagnostics on operands errors. */
3665 /* By default, output verbose error message.
3666 Disable the verbose error message by -mno-verbose-error. */
3667 static int verbose_error_p
= 1;
3669 #ifdef DEBUG_AARCH64
3670 /* N.B. this is only for the purpose of debugging. */
3671 const char* operand_mismatch_kind_names
[] =
3674 "AARCH64_OPDE_RECOVERABLE",
3675 "AARCH64_OPDE_SYNTAX_ERROR",
3676 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3677 "AARCH64_OPDE_INVALID_VARIANT",
3678 "AARCH64_OPDE_OUT_OF_RANGE",
3679 "AARCH64_OPDE_UNALIGNED",
3680 "AARCH64_OPDE_REG_LIST",
3681 "AARCH64_OPDE_OTHER_ERROR",
3683 #endif /* DEBUG_AARCH64 */
3685 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3687 When multiple errors of different kinds are found in the same assembly
3688 line, only the error of the highest severity will be picked up for
3689 issuing the diagnostics. */
3691 static inline bfd_boolean
3692 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3693 enum aarch64_operand_error_kind rhs
)
3695 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3696 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3697 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3698 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3699 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3700 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3701 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3702 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3706 /* Helper routine to get the mnemonic name from the assembly instruction
3707 line; should only be called for the diagnosis purpose, as there is
3708 string copy operation involved, which may affect the runtime
3709 performance if used in elsewhere. */
3712 get_mnemonic_name (const char *str
)
3714 static char mnemonic
[32];
3717 /* Get the first 15 bytes and assume that the full name is included. */
3718 strncpy (mnemonic
, str
, 31);
3719 mnemonic
[31] = '\0';
3721 /* Scan up to the end of the mnemonic, which must end in white space,
3722 '.', or end of string. */
3723 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3728 /* Append '...' to the truncated long name. */
3729 if (ptr
- mnemonic
== 31)
3730 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3736 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3738 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3739 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3742 /* Data strutures storing one user error in the assembly code related to
3745 struct operand_error_record
3747 const aarch64_opcode
*opcode
;
3748 aarch64_operand_error detail
;
3749 struct operand_error_record
*next
;
3752 typedef struct operand_error_record operand_error_record
;
3754 struct operand_errors
3756 operand_error_record
*head
;
3757 operand_error_record
*tail
;
3760 typedef struct operand_errors operand_errors
;
3762 /* Top-level data structure reporting user errors for the current line of
3764 The way md_assemble works is that all opcodes sharing the same mnemonic
3765 name are iterated to find a match to the assembly line. In this data
3766 structure, each of the such opcodes will have one operand_error_record
3767 allocated and inserted. In other words, excessive errors related with
3768 a single opcode are disregarded. */
3769 operand_errors operand_error_report
;
3771 /* Free record nodes. */
3772 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3774 /* Initialize the data structure that stores the operand mismatch
3775 information on assembling one line of the assembly code. */
3777 init_operand_error_report (void)
3779 if (operand_error_report
.head
!= NULL
)
3781 gas_assert (operand_error_report
.tail
!= NULL
);
3782 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3783 free_opnd_error_record_nodes
= operand_error_report
.head
;
3784 operand_error_report
.head
= NULL
;
3785 operand_error_report
.tail
= NULL
;
3788 gas_assert (operand_error_report
.tail
== NULL
);
3791 /* Return TRUE if some operand error has been recorded during the
3792 parsing of the current assembly line using the opcode *OPCODE;
3793 otherwise return FALSE. */
3794 static inline bfd_boolean
3795 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3797 operand_error_record
*record
= operand_error_report
.head
;
3798 return record
&& record
->opcode
== opcode
;
3801 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3802 OPCODE field is initialized with OPCODE.
3803 N.B. only one record for each opcode, i.e. the maximum of one error is
3804 recorded for each instruction template. */
3807 add_operand_error_record (const operand_error_record
* new_record
)
3809 const aarch64_opcode
*opcode
= new_record
->opcode
;
3810 operand_error_record
* record
= operand_error_report
.head
;
3812 /* The record may have been created for this opcode. If not, we need
3814 if (! opcode_has_operand_error_p (opcode
))
3816 /* Get one empty record. */
3817 if (free_opnd_error_record_nodes
== NULL
)
3819 record
= xmalloc (sizeof (operand_error_record
));
3825 record
= free_opnd_error_record_nodes
;
3826 free_opnd_error_record_nodes
= record
->next
;
3828 record
->opcode
= opcode
;
3829 /* Insert at the head. */
3830 record
->next
= operand_error_report
.head
;
3831 operand_error_report
.head
= record
;
3832 if (operand_error_report
.tail
== NULL
)
3833 operand_error_report
.tail
= record
;
3835 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3836 && record
->detail
.index
<= new_record
->detail
.index
3837 && operand_error_higher_severity_p (record
->detail
.kind
,
3838 new_record
->detail
.kind
))
3840 /* In the case of multiple errors found on operands related with a
3841 single opcode, only record the error of the leftmost operand and
3842 only if the error is of higher severity. */
3843 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3844 " the existing error %s on operand %d",
3845 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3846 new_record
->detail
.index
,
3847 operand_mismatch_kind_names
[record
->detail
.kind
],
3848 record
->detail
.index
);
3852 record
->detail
= new_record
->detail
;
3856 record_operand_error_info (const aarch64_opcode
*opcode
,
3857 aarch64_operand_error
*error_info
)
3859 operand_error_record record
;
3860 record
.opcode
= opcode
;
3861 record
.detail
= *error_info
;
3862 add_operand_error_record (&record
);
3865 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3866 error message *ERROR, for operand IDX (count from 0). */
3869 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3870 enum aarch64_operand_error_kind kind
,
3873 aarch64_operand_error info
;
3874 memset(&info
, 0, sizeof (info
));
3878 record_operand_error_info (opcode
, &info
);
3882 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3883 enum aarch64_operand_error_kind kind
,
3884 const char* error
, const int *extra_data
)
3886 aarch64_operand_error info
;
3890 info
.data
[0] = extra_data
[0];
3891 info
.data
[1] = extra_data
[1];
3892 info
.data
[2] = extra_data
[2];
3893 record_operand_error_info (opcode
, &info
);
3897 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
3898 const char* error
, int lower_bound
,
3901 int data
[3] = {lower_bound
, upper_bound
, 0};
3902 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
3906 /* Remove the operand error record for *OPCODE. */
3907 static void ATTRIBUTE_UNUSED
3908 remove_operand_error_record (const aarch64_opcode
*opcode
)
3910 if (opcode_has_operand_error_p (opcode
))
3912 operand_error_record
* record
= operand_error_report
.head
;
3913 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
3914 operand_error_report
.head
= record
->next
;
3915 record
->next
= free_opnd_error_record_nodes
;
3916 free_opnd_error_record_nodes
= record
;
3917 if (operand_error_report
.head
== NULL
)
3919 gas_assert (operand_error_report
.tail
== record
);
3920 operand_error_report
.tail
= NULL
;
3925 /* Given the instruction in *INSTR, return the index of the best matched
3926 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3928 Return -1 if there is no qualifier sequence; return the first match
3929 if there is multiple matches found. */
3932 find_best_match (const aarch64_inst
*instr
,
3933 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
3935 int i
, num_opnds
, max_num_matched
, idx
;
3937 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3940 DEBUG_TRACE ("no operand");
3944 max_num_matched
= 0;
3947 /* For each pattern. */
3948 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
3951 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
3953 /* Most opcodes has much fewer patterns in the list. */
3954 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
3956 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
3957 if (i
!= 0 && idx
== -1)
3958 /* If nothing has been matched, return the 1st sequence. */
3963 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
3964 if (*qualifiers
== instr
->operands
[j
].qualifier
)
3967 if (num_matched
> max_num_matched
)
3969 max_num_matched
= num_matched
;
3974 DEBUG_TRACE ("return with %d", idx
);
3978 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3979 corresponding operands in *INSTR. */
3982 assign_qualifier_sequence (aarch64_inst
*instr
,
3983 const aarch64_opnd_qualifier_t
*qualifiers
)
3986 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3987 gas_assert (num_opnds
);
3988 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
3989 instr
->operands
[i
].qualifier
= *qualifiers
;
3992 /* Print operands for the diagnosis purpose. */
3995 print_operands (char *buf
, const aarch64_opcode
*opcode
,
3996 const aarch64_opnd_info
*opnds
)
4000 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4002 const size_t size
= 128;
4005 /* We regard the opcode operand info more, however we also look into
4006 the inst->operands to support the disassembling of the optional
4008 The two operand code should be the same in all cases, apart from
4009 when the operand can be optional. */
4010 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4011 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4014 /* Generate the operand string in STR. */
4015 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
4019 strcat (buf
, i
== 0 ? " " : ",");
4021 /* Append the operand string. */
4026 /* Send to stderr a string as information. */
4029 output_info (const char *format
, ...)
4035 as_where (&file
, &line
);
4039 fprintf (stderr
, "%s:%u: ", file
, line
);
4041 fprintf (stderr
, "%s: ", file
);
4043 fprintf (stderr
, _("Info: "));
4044 va_start (args
, format
);
4045 vfprintf (stderr
, format
, args
);
4047 (void) putc ('\n', stderr
);
4050 /* Output one operand error record. */
4053 output_operand_error_record (const operand_error_record
*record
, char *str
)
4055 const aarch64_operand_error
*detail
= &record
->detail
;
4056 int idx
= detail
->index
;
4057 const aarch64_opcode
*opcode
= record
->opcode
;
4058 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4059 : AARCH64_OPND_NIL
);
4061 switch (detail
->kind
)
4063 case AARCH64_OPDE_NIL
:
4067 case AARCH64_OPDE_SYNTAX_ERROR
:
4068 case AARCH64_OPDE_RECOVERABLE
:
4069 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4070 case AARCH64_OPDE_OTHER_ERROR
:
4071 /* Use the prepared error message if there is, otherwise use the
4072 operand description string to describe the error. */
4073 if (detail
->error
!= NULL
)
4076 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4078 as_bad (_("%s at operand %d -- `%s'"),
4079 detail
->error
, idx
+ 1, str
);
4083 gas_assert (idx
>= 0);
4084 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4085 aarch64_get_operand_desc (opd_code
), str
);
4089 case AARCH64_OPDE_INVALID_VARIANT
:
4090 as_bad (_("operand mismatch -- `%s'"), str
);
4091 if (verbose_error_p
)
4093 /* We will try to correct the erroneous instruction and also provide
4094 more information e.g. all other valid variants.
4096 The string representation of the corrected instruction and other
4097 valid variants are generated by
4099 1) obtaining the intermediate representation of the erroneous
4101 2) manipulating the IR, e.g. replacing the operand qualifier;
4102 3) printing out the instruction by calling the printer functions
4103 shared with the disassembler.
4105 The limitation of this method is that the exact input assembly
4106 line cannot be accurately reproduced in some cases, for example an
4107 optional operand present in the actual assembly line will be
4108 omitted in the output; likewise for the optional syntax rules,
4109 e.g. the # before the immediate. Another limitation is that the
4110 assembly symbols and relocation operations in the assembly line
4111 currently cannot be printed out in the error report. Last but not
4112 least, when there is other error(s) co-exist with this error, the
4113 'corrected' instruction may be still incorrect, e.g. given
4114 'ldnp h0,h1,[x0,#6]!'
4115 this diagnosis will provide the version:
4116 'ldnp s0,s1,[x0,#6]!'
4117 which is still not right. */
4118 size_t len
= strlen (get_mnemonic_name (str
));
4121 const size_t size
= 2048;
4123 aarch64_inst
*inst_base
= &inst
.base
;
4124 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4127 reset_aarch64_instruction (&inst
);
4128 inst_base
->opcode
= opcode
;
4130 /* Reset the error report so that there is no side effect on the
4131 following operand parsing. */
4132 init_operand_error_report ();
4135 result
= parse_operands (str
+ len
, opcode
)
4136 && programmer_friendly_fixup (&inst
);
4137 gas_assert (result
);
4138 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4140 gas_assert (!result
);
4142 /* Find the most matched qualifier sequence. */
4143 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4144 gas_assert (qlf_idx
> -1);
4146 /* Assign the qualifiers. */
4147 assign_qualifier_sequence (inst_base
,
4148 opcode
->qualifiers_list
[qlf_idx
]);
4150 /* Print the hint. */
4151 output_info (_(" did you mean this?"));
4152 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4153 print_operands (buf
, opcode
, inst_base
->operands
);
4154 output_info (_(" %s"), buf
);
4156 /* Print out other variant(s) if there is any. */
4158 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4159 output_info (_(" other valid variant(s):"));
4161 /* For each pattern. */
4162 qualifiers_list
= opcode
->qualifiers_list
;
4163 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4165 /* Most opcodes has much fewer patterns in the list.
4166 First NIL qualifier indicates the end in the list. */
4167 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4172 /* Mnemonics name. */
4173 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4175 /* Assign the qualifiers. */
4176 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4178 /* Print instruction. */
4179 print_operands (buf
, opcode
, inst_base
->operands
);
4181 output_info (_(" %s"), buf
);
4187 case AARCH64_OPDE_OUT_OF_RANGE
:
4188 if (detail
->data
[0] != detail
->data
[1])
4189 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4190 detail
->error
? detail
->error
: _("immediate value"),
4191 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4193 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4194 detail
->error
? detail
->error
: _("immediate value"),
4195 detail
->data
[0], idx
+ 1, str
);
4198 case AARCH64_OPDE_REG_LIST
:
4199 if (detail
->data
[0] == 1)
4200 as_bad (_("invalid number of registers in the list; "
4201 "only 1 register is expected at operand %d -- `%s'"),
4204 as_bad (_("invalid number of registers in the list; "
4205 "%d registers are expected at operand %d -- `%s'"),
4206 detail
->data
[0], idx
+ 1, str
);
4209 case AARCH64_OPDE_UNALIGNED
:
4210 as_bad (_("immediate value should be a multiple of "
4211 "%d at operand %d -- `%s'"),
4212 detail
->data
[0], idx
+ 1, str
);
4221 /* Process and output the error message about the operand mismatching.
4223 When this function is called, the operand error information had
4224 been collected for an assembly line and there will be multiple
4225 errors in the case of mulitple instruction templates; output the
4226 error message that most closely describes the problem. */
4229 output_operand_error_report (char *str
)
4231 int largest_error_pos
;
4232 const char *msg
= NULL
;
4233 enum aarch64_operand_error_kind kind
;
4234 operand_error_record
*curr
;
4235 operand_error_record
*head
= operand_error_report
.head
;
4236 operand_error_record
*record
= NULL
;
4238 /* No error to report. */
4242 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4244 /* Only one error. */
4245 if (head
== operand_error_report
.tail
)
4247 DEBUG_TRACE ("single opcode entry with error kind: %s",
4248 operand_mismatch_kind_names
[head
->detail
.kind
]);
4249 output_operand_error_record (head
, str
);
4253 /* Find the error kind of the highest severity. */
4254 DEBUG_TRACE ("multiple opcode entres with error kind");
4255 kind
= AARCH64_OPDE_NIL
;
4256 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4258 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4259 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4260 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4261 kind
= curr
->detail
.kind
;
4263 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4265 /* Pick up one of errors of KIND to report. */
4266 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4267 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4269 if (curr
->detail
.kind
!= kind
)
4271 /* If there are multiple errors, pick up the one with the highest
4272 mismatching operand index. In the case of multiple errors with
4273 the equally highest operand index, pick up the first one or the
4274 first one with non-NULL error message. */
4275 if (curr
->detail
.index
> largest_error_pos
4276 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4277 && curr
->detail
.error
!= NULL
))
4279 largest_error_pos
= curr
->detail
.index
;
4281 msg
= record
->detail
.error
;
4285 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4286 DEBUG_TRACE ("Pick up error kind %s to report",
4287 operand_mismatch_kind_names
[record
->detail
.kind
]);
4290 output_operand_error_record (record
, str
);
4293 /* Write an AARCH64 instruction to buf - always little-endian. */
4295 put_aarch64_insn (char *buf
, uint32_t insn
)
4297 unsigned char *where
= (unsigned char *) buf
;
4299 where
[1] = insn
>> 8;
4300 where
[2] = insn
>> 16;
4301 where
[3] = insn
>> 24;
4305 get_aarch64_insn (char *buf
)
4307 unsigned char *where
= (unsigned char *) buf
;
4309 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4314 output_inst (struct aarch64_inst
*new_inst
)
4318 to
= frag_more (INSN_SIZE
);
4320 frag_now
->tc_frag_data
.recorded
= 1;
4322 put_aarch64_insn (to
, inst
.base
.value
);
4324 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4326 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4327 INSN_SIZE
, &inst
.reloc
.exp
,
4330 DEBUG_TRACE ("Prepared relocation fix up");
4331 /* Don't check the addend value against the instruction size,
4332 that's the job of our code in md_apply_fix(). */
4333 fixp
->fx_no_overflow
= 1;
4334 if (new_inst
!= NULL
)
4335 fixp
->tc_fix_data
.inst
= new_inst
;
4336 if (aarch64_gas_internal_fixup_p ())
4338 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4339 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4340 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4344 dwarf2_emit_insn (INSN_SIZE
);
4347 /* Link together opcodes of the same name. */
4351 aarch64_opcode
*opcode
;
4352 struct templates
*next
;
4355 typedef struct templates templates
;
4358 lookup_mnemonic (const char *start
, int len
)
4360 templates
*templ
= NULL
;
4362 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4366 /* Subroutine of md_assemble, responsible for looking up the primary
4367 opcode from the mnemonic the user wrote. STR points to the
4368 beginning of the mnemonic. */
4371 opcode_lookup (char **str
)
4374 const aarch64_cond
*cond
;
4378 /* Scan up to the end of the mnemonic, which must end in white space,
4379 '.', or end of string. */
4380 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4387 inst
.cond
= COND_ALWAYS
;
4389 /* Handle a possible condition. */
4392 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4395 inst
.cond
= cond
->value
;
4409 if (inst
.cond
== COND_ALWAYS
)
4411 /* Look for unaffixed mnemonic. */
4412 return lookup_mnemonic (base
, len
);
4416 /* append ".c" to mnemonic if conditional */
4417 memcpy (condname
, base
, len
);
4418 memcpy (condname
+ len
, ".c", 2);
4421 return lookup_mnemonic (base
, len
);
4427 /* Internal helper routine converting a vector neon_type_el structure
4428 *VECTYPE to a corresponding operand qualifier. */
4430 static inline aarch64_opnd_qualifier_t
4431 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4433 /* Element size in bytes indexed by neon_el_type. */
4434 const unsigned char ele_size
[5]
4437 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4438 goto vectype_conversion_fail
;
4440 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4442 if (vectype
->defined
& NTA_HASINDEX
)
4443 /* Vector element register. */
4444 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4447 /* Vector register. */
4448 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4450 if (reg_size
!= 16 && reg_size
!= 8)
4451 goto vectype_conversion_fail
;
4452 /* The conversion is calculated based on the relation of the order of
4453 qualifiers to the vector element size and vector register size. */
4454 offset
= (vectype
->type
== NT_q
)
4455 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4456 gas_assert (offset
<= 8);
4457 return AARCH64_OPND_QLF_V_8B
+ offset
;
4460 vectype_conversion_fail
:
4461 first_error (_("bad vector arrangement type"));
4462 return AARCH64_OPND_QLF_NIL
;
4465 /* Process an optional operand that is found omitted from the assembly line.
4466 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4467 instruction's opcode entry while IDX is the index of this omitted operand.
4471 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4472 int idx
, aarch64_opnd_info
*operand
)
4474 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4475 gas_assert (optional_operand_p (opcode
, idx
));
4476 gas_assert (!operand
->present
);
4480 case AARCH64_OPND_Rd
:
4481 case AARCH64_OPND_Rn
:
4482 case AARCH64_OPND_Rm
:
4483 case AARCH64_OPND_Rt
:
4484 case AARCH64_OPND_Rt2
:
4485 case AARCH64_OPND_Rs
:
4486 case AARCH64_OPND_Ra
:
4487 case AARCH64_OPND_Rt_SYS
:
4488 case AARCH64_OPND_Rd_SP
:
4489 case AARCH64_OPND_Rn_SP
:
4490 case AARCH64_OPND_Fd
:
4491 case AARCH64_OPND_Fn
:
4492 case AARCH64_OPND_Fm
:
4493 case AARCH64_OPND_Fa
:
4494 case AARCH64_OPND_Ft
:
4495 case AARCH64_OPND_Ft2
:
4496 case AARCH64_OPND_Sd
:
4497 case AARCH64_OPND_Sn
:
4498 case AARCH64_OPND_Sm
:
4499 case AARCH64_OPND_Vd
:
4500 case AARCH64_OPND_Vn
:
4501 case AARCH64_OPND_Vm
:
4502 case AARCH64_OPND_VdD1
:
4503 case AARCH64_OPND_VnD1
:
4504 operand
->reg
.regno
= default_value
;
4507 case AARCH64_OPND_Ed
:
4508 case AARCH64_OPND_En
:
4509 case AARCH64_OPND_Em
:
4510 operand
->reglane
.regno
= default_value
;
4513 case AARCH64_OPND_IDX
:
4514 case AARCH64_OPND_BIT_NUM
:
4515 case AARCH64_OPND_IMMR
:
4516 case AARCH64_OPND_IMMS
:
4517 case AARCH64_OPND_SHLL_IMM
:
4518 case AARCH64_OPND_IMM_VLSL
:
4519 case AARCH64_OPND_IMM_VLSR
:
4520 case AARCH64_OPND_CCMP_IMM
:
4521 case AARCH64_OPND_FBITS
:
4522 case AARCH64_OPND_UIMM4
:
4523 case AARCH64_OPND_UIMM3_OP1
:
4524 case AARCH64_OPND_UIMM3_OP2
:
4525 case AARCH64_OPND_IMM
:
4526 case AARCH64_OPND_WIDTH
:
4527 case AARCH64_OPND_UIMM7
:
4528 case AARCH64_OPND_NZCV
:
4529 operand
->imm
.value
= default_value
;
4532 case AARCH64_OPND_EXCEPTION
:
4533 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4536 case AARCH64_OPND_BARRIER_ISB
:
4537 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4544 /* Process the relocation type for move wide instructions.
4545 Return TRUE on success; otherwise return FALSE. */
4548 process_movw_reloc_info (void)
4553 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4555 if (inst
.base
.opcode
->op
== OP_MOVK
)
4556 switch (inst
.reloc
.type
)
4558 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4559 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4560 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4561 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4562 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4563 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4565 (_("the specified relocation type is not allowed for MOVK"));
4571 switch (inst
.reloc
.type
)
4573 case BFD_RELOC_AARCH64_MOVW_G0
:
4574 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4575 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4576 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4577 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4580 case BFD_RELOC_AARCH64_MOVW_G1
:
4581 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4582 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4583 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4584 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4587 case BFD_RELOC_AARCH64_MOVW_G2
:
4588 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4589 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4590 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4593 set_fatal_syntax_error
4594 (_("the specified relocation type is not allowed for 32-bit "
4600 case BFD_RELOC_AARCH64_MOVW_G3
:
4603 set_fatal_syntax_error
4604 (_("the specified relocation type is not allowed for 32-bit "
4611 /* More cases should be added when more MOVW-related relocation types
4612 are supported in GAS. */
4613 gas_assert (aarch64_gas_internal_fixup_p ());
4614 /* The shift amount should have already been set by the parser. */
4617 inst
.base
.operands
[1].shifter
.amount
= shift
;
4621 /* A primitive log caculator. */
4623 static inline unsigned int
4624 get_logsz (unsigned int size
)
4626 const unsigned char ls
[16] =
4627 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4633 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4634 return ls
[size
- 1];
4637 /* Determine and return the real reloc type code for an instruction
4638 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4640 static inline bfd_reloc_code_real_type
4641 ldst_lo12_determine_real_reloc_type (void)
4644 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4645 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4647 const bfd_reloc_code_real_type reloc_ldst_lo12
[5] = {
4648 BFD_RELOC_AARCH64_LDST8_LO12
, BFD_RELOC_AARCH64_LDST16_LO12
,
4649 BFD_RELOC_AARCH64_LDST32_LO12
, BFD_RELOC_AARCH64_LDST64_LO12
,
4650 BFD_RELOC_AARCH64_LDST128_LO12
4653 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
);
4654 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4656 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4658 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4660 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4662 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4663 gas_assert (logsz
>= 0 && logsz
<= 4);
4665 return reloc_ldst_lo12
[logsz
];
4668 /* Check whether a register list REGINFO is valid. The registers must be
4669 numbered in increasing order (modulo 32), in increments of one or two.
4671 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4674 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4677 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4679 uint32_t i
, nb_regs
, prev_regno
, incr
;
4681 nb_regs
= 1 + (reginfo
& 0x3);
4683 prev_regno
= reginfo
& 0x1f;
4684 incr
= accept_alternate
? 2 : 1;
4686 for (i
= 1; i
< nb_regs
; ++i
)
4688 uint32_t curr_regno
;
4690 curr_regno
= reginfo
& 0x1f;
4691 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4693 prev_regno
= curr_regno
;
4699 /* Generic instruction operand parser. This does no encoding and no
4700 semantic validation; it merely squirrels values away in the inst
4701 structure. Returns TRUE or FALSE depending on whether the
4702 specified grammar matched. */
4705 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4708 char *backtrack_pos
= 0;
4709 const enum aarch64_opnd
*operands
= opcode
->operands
;
4712 skip_whitespace (str
);
4714 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4717 int isreg32
, isregzero
;
4718 int comma_skipped_p
= 0;
4719 aarch64_reg_type rtype
;
4720 struct neon_type_el vectype
;
4721 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4723 DEBUG_TRACE ("parse operand %d", i
);
4725 /* Assign the operand code. */
4726 info
->type
= operands
[i
];
4728 if (optional_operand_p (opcode
, i
))
4730 /* Remember where we are in case we need to backtrack. */
4731 gas_assert (!backtrack_pos
);
4732 backtrack_pos
= str
;
4735 /* Expect comma between operands; the backtrack mechanizm will take
4736 care of cases of omitted optional operand. */
4737 if (i
> 0 && ! skip_past_char (&str
, ','))
4739 set_syntax_error (_("comma expected between operands"));
4743 comma_skipped_p
= 1;
4745 switch (operands
[i
])
4747 case AARCH64_OPND_Rd
:
4748 case AARCH64_OPND_Rn
:
4749 case AARCH64_OPND_Rm
:
4750 case AARCH64_OPND_Rt
:
4751 case AARCH64_OPND_Rt2
:
4752 case AARCH64_OPND_Rs
:
4753 case AARCH64_OPND_Ra
:
4754 case AARCH64_OPND_Rt_SYS
:
4755 case AARCH64_OPND_PAIRREG
:
4756 po_int_reg_or_fail (1, 0);
4759 case AARCH64_OPND_Rd_SP
:
4760 case AARCH64_OPND_Rn_SP
:
4761 po_int_reg_or_fail (0, 1);
4764 case AARCH64_OPND_Rm_EXT
:
4765 case AARCH64_OPND_Rm_SFT
:
4766 po_misc_or_fail (parse_shifter_operand
4767 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4769 : SHIFTED_LOGIC_IMM
)));
4770 if (!info
->shifter
.operator_present
)
4772 /* Default to LSL if not present. Libopcodes prefers shifter
4773 kind to be explicit. */
4774 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4775 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4776 /* For Rm_EXT, libopcodes will carry out further check on whether
4777 or not stack pointer is used in the instruction (Recall that
4778 "the extend operator is not optional unless at least one of
4779 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4783 case AARCH64_OPND_Fd
:
4784 case AARCH64_OPND_Fn
:
4785 case AARCH64_OPND_Fm
:
4786 case AARCH64_OPND_Fa
:
4787 case AARCH64_OPND_Ft
:
4788 case AARCH64_OPND_Ft2
:
4789 case AARCH64_OPND_Sd
:
4790 case AARCH64_OPND_Sn
:
4791 case AARCH64_OPND_Sm
:
4792 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4793 if (val
== PARSE_FAIL
)
4795 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4798 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4800 info
->reg
.regno
= val
;
4801 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4804 case AARCH64_OPND_Vd
:
4805 case AARCH64_OPND_Vn
:
4806 case AARCH64_OPND_Vm
:
4807 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4808 if (val
== PARSE_FAIL
)
4810 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4813 if (vectype
.defined
& NTA_HASINDEX
)
4816 info
->reg
.regno
= val
;
4817 info
->qualifier
= vectype_to_qualifier (&vectype
);
4818 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4822 case AARCH64_OPND_VdD1
:
4823 case AARCH64_OPND_VnD1
:
4824 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4825 if (val
== PARSE_FAIL
)
4827 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4830 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4832 set_fatal_syntax_error
4833 (_("the top half of a 128-bit FP/SIMD register is expected"));
4836 info
->reg
.regno
= val
;
4837 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4838 here; it is correct for the purpose of encoding/decoding since
4839 only the register number is explicitly encoded in the related
4840 instructions, although this appears a bit hacky. */
4841 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4844 case AARCH64_OPND_Ed
:
4845 case AARCH64_OPND_En
:
4846 case AARCH64_OPND_Em
:
4847 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4848 if (val
== PARSE_FAIL
)
4850 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4853 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
4856 info
->reglane
.regno
= val
;
4857 info
->reglane
.index
= vectype
.index
;
4858 info
->qualifier
= vectype_to_qualifier (&vectype
);
4859 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4863 case AARCH64_OPND_LVn
:
4864 case AARCH64_OPND_LVt
:
4865 case AARCH64_OPND_LVt_AL
:
4866 case AARCH64_OPND_LEt
:
4867 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
4869 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
4871 set_fatal_syntax_error (_("invalid register list"));
4874 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
4875 info
->reglist
.num_regs
= (val
& 0x3) + 1;
4876 if (operands
[i
] == AARCH64_OPND_LEt
)
4878 if (!(vectype
.defined
& NTA_HASINDEX
))
4880 info
->reglist
.has_index
= 1;
4881 info
->reglist
.index
= vectype
.index
;
4883 else if (!(vectype
.defined
& NTA_HASTYPE
))
4885 info
->qualifier
= vectype_to_qualifier (&vectype
);
4886 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4890 case AARCH64_OPND_Cn
:
4891 case AARCH64_OPND_Cm
:
4892 po_reg_or_fail (REG_TYPE_CN
);
4895 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
4898 inst
.base
.operands
[i
].reg
.regno
= val
;
4901 case AARCH64_OPND_SHLL_IMM
:
4902 case AARCH64_OPND_IMM_VLSR
:
4903 po_imm_or_fail (1, 64);
4904 info
->imm
.value
= val
;
4907 case AARCH64_OPND_CCMP_IMM
:
4908 case AARCH64_OPND_FBITS
:
4909 case AARCH64_OPND_UIMM4
:
4910 case AARCH64_OPND_UIMM3_OP1
:
4911 case AARCH64_OPND_UIMM3_OP2
:
4912 case AARCH64_OPND_IMM_VLSL
:
4913 case AARCH64_OPND_IMM
:
4914 case AARCH64_OPND_WIDTH
:
4915 po_imm_nc_or_fail ();
4916 info
->imm
.value
= val
;
4919 case AARCH64_OPND_UIMM7
:
4920 po_imm_or_fail (0, 127);
4921 info
->imm
.value
= val
;
4924 case AARCH64_OPND_IDX
:
4925 case AARCH64_OPND_BIT_NUM
:
4926 case AARCH64_OPND_IMMR
:
4927 case AARCH64_OPND_IMMS
:
4928 po_imm_or_fail (0, 63);
4929 info
->imm
.value
= val
;
4932 case AARCH64_OPND_IMM0
:
4933 po_imm_nc_or_fail ();
4936 set_fatal_syntax_error (_("immediate zero expected"));
4939 info
->imm
.value
= 0;
4942 case AARCH64_OPND_FPIMM0
:
4945 bfd_boolean res1
= FALSE
, res2
= FALSE
;
4946 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4947 it is probably not worth the effort to support it. */
4948 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
4949 && !(res2
= parse_constant_immediate (&str
, &val
)))
4951 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
4953 info
->imm
.value
= 0;
4954 info
->imm
.is_fp
= 1;
4957 set_fatal_syntax_error (_("immediate zero expected"));
4961 case AARCH64_OPND_IMM_MOV
:
4964 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
4965 reg_name_p (str
, REG_TYPE_VN
))
4968 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
4970 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4971 later. fix_mov_imm_insn will try to determine a machine
4972 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4973 message if the immediate cannot be moved by a single
4975 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
4976 inst
.base
.operands
[i
].skip
= 1;
4980 case AARCH64_OPND_SIMD_IMM
:
4981 case AARCH64_OPND_SIMD_IMM_SFT
:
4982 if (! parse_big_immediate (&str
, &val
))
4984 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4986 /* need_libopcodes_p */ 1,
4989 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4990 shift, we don't check it here; we leave the checking to
4991 the libopcodes (operand_general_constraint_met_p). By
4992 doing this, we achieve better diagnostics. */
4993 if (skip_past_comma (&str
)
4994 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
4996 if (!info
->shifter
.operator_present
4997 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
4999 /* Default to LSL if not present. Libopcodes prefers shifter
5000 kind to be explicit. */
5001 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5002 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5006 case AARCH64_OPND_FPIMM
:
5007 case AARCH64_OPND_SIMD_FPIMM
:
5011 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5013 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5017 set_fatal_syntax_error (_("invalid floating-point constant"));
5020 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5021 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5025 case AARCH64_OPND_LIMM
:
5026 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5027 SHIFTED_LOGIC_IMM
));
5028 if (info
->shifter
.operator_present
)
5030 set_fatal_syntax_error
5031 (_("shift not allowed for bitmask immediate"));
5034 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5036 /* need_libopcodes_p */ 1,
5040 case AARCH64_OPND_AIMM
:
5041 if (opcode
->op
== OP_ADD
)
5042 /* ADD may have relocation types. */
5043 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5044 SHIFTED_ARITH_IMM
));
5046 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5047 SHIFTED_ARITH_IMM
));
5048 switch (inst
.reloc
.type
)
5050 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5051 info
->shifter
.amount
= 12;
5053 case BFD_RELOC_UNUSED
:
5054 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5055 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5056 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5057 inst
.reloc
.pc_rel
= 0;
5062 info
->imm
.value
= 0;
5063 if (!info
->shifter
.operator_present
)
5065 /* Default to LSL if not present. Libopcodes prefers shifter
5066 kind to be explicit. */
5067 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5068 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5072 case AARCH64_OPND_HALF
:
5074 /* #<imm16> or relocation. */
5075 int internal_fixup_p
;
5076 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5077 if (internal_fixup_p
)
5078 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5079 skip_whitespace (str
);
5080 if (skip_past_comma (&str
))
5082 /* {, LSL #<shift>} */
5083 if (! aarch64_gas_internal_fixup_p ())
5085 set_fatal_syntax_error (_("can't mix relocation modifier "
5086 "with explicit shift"));
5089 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5092 inst
.base
.operands
[i
].shifter
.amount
= 0;
5093 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5094 inst
.base
.operands
[i
].imm
.value
= 0;
5095 if (! process_movw_reloc_info ())
5100 case AARCH64_OPND_EXCEPTION
:
5101 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5102 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5104 /* need_libopcodes_p */ 0,
5108 case AARCH64_OPND_NZCV
:
5110 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5114 info
->imm
.value
= nzcv
->value
;
5117 po_imm_or_fail (0, 15);
5118 info
->imm
.value
= val
;
5122 case AARCH64_OPND_COND
:
5123 case AARCH64_OPND_COND1
:
5124 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5126 if (info
->cond
== NULL
)
5128 set_syntax_error (_("invalid condition"));
5131 else if (operands
[i
] == AARCH64_OPND_COND1
5132 && (info
->cond
->value
& 0xe) == 0xe)
5134 /* Not allow AL or NV. */
5135 set_default_error ();
5140 case AARCH64_OPND_ADDR_ADRP
:
5141 po_misc_or_fail (parse_adrp (&str
));
5142 /* Clear the value as operand needs to be relocated. */
5143 info
->imm
.value
= 0;
5146 case AARCH64_OPND_ADDR_PCREL14
:
5147 case AARCH64_OPND_ADDR_PCREL19
:
5148 case AARCH64_OPND_ADDR_PCREL21
:
5149 case AARCH64_OPND_ADDR_PCREL26
:
5150 po_misc_or_fail (parse_address_reloc (&str
, info
));
5151 if (!info
->addr
.pcrel
)
5153 set_syntax_error (_("invalid pc-relative address"));
5156 if (inst
.gen_lit_pool
5157 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5159 /* Only permit "=value" in the literal load instructions.
5160 The literal will be generated by programmer_friendly_fixup. */
5161 set_syntax_error (_("invalid use of \"=immediate\""));
5164 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5166 set_syntax_error (_("unrecognized relocation suffix"));
5169 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5171 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5172 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5176 info
->imm
.value
= 0;
5177 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5178 switch (opcode
->iclass
)
5182 /* e.g. CBZ or B.COND */
5183 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5184 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5188 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5189 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5193 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5195 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5196 : BFD_RELOC_AARCH64_JUMP26
;
5199 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5200 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5203 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5204 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5210 inst
.reloc
.pc_rel
= 1;
5214 case AARCH64_OPND_ADDR_SIMPLE
:
5215 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5216 /* [<Xn|SP>{, #<simm>}] */
5217 po_char_or_fail ('[');
5218 po_reg_or_fail (REG_TYPE_R64_SP
);
5219 /* Accept optional ", #0". */
5220 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5221 && skip_past_char (&str
, ','))
5223 skip_past_char (&str
, '#');
5224 if (! skip_past_char (&str
, '0'))
5226 set_fatal_syntax_error
5227 (_("the optional immediate offset can only be 0"));
5231 po_char_or_fail (']');
5232 info
->addr
.base_regno
= val
;
5235 case AARCH64_OPND_ADDR_REGOFF
:
5236 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5237 po_misc_or_fail (parse_address (&str
, info
, 0));
5238 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5239 || !info
->addr
.preind
|| info
->addr
.postind
5240 || info
->addr
.writeback
)
5242 set_syntax_error (_("invalid addressing mode"));
5245 if (!info
->shifter
.operator_present
)
5247 /* Default to LSL if not present. Libopcodes prefers shifter
5248 kind to be explicit. */
5249 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5250 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5252 /* Qualifier to be deduced by libopcodes. */
5255 case AARCH64_OPND_ADDR_SIMM7
:
5256 po_misc_or_fail (parse_address (&str
, info
, 0));
5257 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5258 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5260 set_syntax_error (_("invalid addressing mode"));
5263 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5265 /* need_libopcodes_p */ 1,
5269 case AARCH64_OPND_ADDR_SIMM9
:
5270 case AARCH64_OPND_ADDR_SIMM9_2
:
5271 po_misc_or_fail (parse_address_reloc (&str
, info
));
5272 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5273 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5274 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5275 && info
->addr
.writeback
))
5277 set_syntax_error (_("invalid addressing mode"));
5280 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5282 set_syntax_error (_("relocation not allowed"));
5285 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5287 /* need_libopcodes_p */ 1,
5291 case AARCH64_OPND_ADDR_UIMM12
:
5292 po_misc_or_fail (parse_address_reloc (&str
, info
));
5293 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5294 || !info
->addr
.preind
|| info
->addr
.writeback
)
5296 set_syntax_error (_("invalid addressing mode"));
5299 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5300 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5301 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
)
5302 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5303 /* Leave qualifier to be determined by libopcodes. */
5306 case AARCH64_OPND_SIMD_ADDR_POST
:
5307 /* [<Xn|SP>], <Xm|#<amount>> */
5308 po_misc_or_fail (parse_address (&str
, info
, 1));
5309 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5311 set_syntax_error (_("invalid addressing mode"));
5314 if (!info
->addr
.offset
.is_reg
)
5316 if (inst
.reloc
.exp
.X_op
== O_constant
)
5317 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5320 set_fatal_syntax_error
5321 (_("writeback value should be an immediate constant"));
5328 case AARCH64_OPND_SYSREG
:
5329 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5332 set_syntax_error (_("unknown or missing system register name"));
5335 inst
.base
.operands
[i
].sysreg
= val
;
5338 case AARCH64_OPND_PSTATEFIELD
:
5339 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5342 set_syntax_error (_("unknown or missing PSTATE field name"));
5345 inst
.base
.operands
[i
].pstatefield
= val
;
5348 case AARCH64_OPND_SYSREG_IC
:
5349 inst
.base
.operands
[i
].sysins_op
=
5350 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5352 case AARCH64_OPND_SYSREG_DC
:
5353 inst
.base
.operands
[i
].sysins_op
=
5354 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5356 case AARCH64_OPND_SYSREG_AT
:
5357 inst
.base
.operands
[i
].sysins_op
=
5358 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5360 case AARCH64_OPND_SYSREG_TLBI
:
5361 inst
.base
.operands
[i
].sysins_op
=
5362 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5364 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5366 set_fatal_syntax_error ( _("unknown or missing operation name"));
5371 case AARCH64_OPND_BARRIER
:
5372 case AARCH64_OPND_BARRIER_ISB
:
5373 val
= parse_barrier (&str
);
5374 if (val
!= PARSE_FAIL
5375 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5377 /* ISB only accepts options name 'sy'. */
5379 (_("the specified option is not accepted in ISB"));
5380 /* Turn off backtrack as this optional operand is present. */
5384 /* This is an extension to accept a 0..15 immediate. */
5385 if (val
== PARSE_FAIL
)
5386 po_imm_or_fail (0, 15);
5387 info
->barrier
= aarch64_barrier_options
+ val
;
5390 case AARCH64_OPND_PRFOP
:
5391 val
= parse_pldop (&str
);
5392 /* This is an extension to accept a 0..31 immediate. */
5393 if (val
== PARSE_FAIL
)
5394 po_imm_or_fail (0, 31);
5395 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5399 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5402 /* If we get here, this operand was successfully parsed. */
5403 inst
.base
.operands
[i
].present
= 1;
5407 /* The parse routine should already have set the error, but in case
5408 not, set a default one here. */
5410 set_default_error ();
5412 if (! backtrack_pos
)
5413 goto parse_operands_return
;
5416 /* We reach here because this operand is marked as optional, and
5417 either no operand was supplied or the operand was supplied but it
5418 was syntactically incorrect. In the latter case we report an
5419 error. In the former case we perform a few more checks before
5420 dropping through to the code to insert the default operand. */
5422 char *tmp
= backtrack_pos
;
5423 char endchar
= END_OF_INSN
;
5425 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5427 skip_past_char (&tmp
, ',');
5429 if (*tmp
!= endchar
)
5430 /* The user has supplied an operand in the wrong format. */
5431 goto parse_operands_return
;
5433 /* Make sure there is not a comma before the optional operand.
5434 For example the fifth operand of 'sys' is optional:
5436 sys #0,c0,c0,#0, <--- wrong
5437 sys #0,c0,c0,#0 <--- correct. */
5438 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5440 set_fatal_syntax_error
5441 (_("unexpected comma before the omitted optional operand"));
5442 goto parse_operands_return
;
5446 /* Reaching here means we are dealing with an optional operand that is
5447 omitted from the assembly line. */
5448 gas_assert (optional_operand_p (opcode
, i
));
5450 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5452 /* Try again, skipping the optional operand at backtrack_pos. */
5453 str
= backtrack_pos
;
5456 /* Clear any error record after the omitted optional operand has been
5457 successfully handled. */
5461 /* Check if we have parsed all the operands. */
5462 if (*str
!= '\0' && ! error_p ())
5464 /* Set I to the index of the last present operand; this is
5465 for the purpose of diagnostics. */
5466 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5468 set_fatal_syntax_error
5469 (_("unexpected characters following instruction"));
5472 parse_operands_return
:
5476 DEBUG_TRACE ("parsing FAIL: %s - %s",
5477 operand_mismatch_kind_names
[get_error_kind ()],
5478 get_error_message ());
5479 /* Record the operand error properly; this is useful when there
5480 are multiple instruction templates for a mnemonic name, so that
5481 later on, we can select the error that most closely describes
5483 record_operand_error (opcode
, i
, get_error_kind (),
5484 get_error_message ());
5489 DEBUG_TRACE ("parsing SUCCESS");
5494 /* It does some fix-up to provide some programmer friendly feature while
5495 keeping the libopcodes happy, i.e. libopcodes only accepts
5496 the preferred architectural syntax.
5497 Return FALSE if there is any failure; otherwise return TRUE. */
5500 programmer_friendly_fixup (aarch64_instruction
*instr
)
5502 aarch64_inst
*base
= &instr
->base
;
5503 const aarch64_opcode
*opcode
= base
->opcode
;
5504 enum aarch64_op op
= opcode
->op
;
5505 aarch64_opnd_info
*operands
= base
->operands
;
5507 DEBUG_TRACE ("enter");
5509 switch (opcode
->iclass
)
5512 /* TBNZ Xn|Wn, #uimm6, label
5513 Test and Branch Not Zero: conditionally jumps to label if bit number
5514 uimm6 in register Xn is not zero. The bit number implies the width of
5515 the register, which may be written and should be disassembled as Wn if
5516 uimm is less than 32. */
5517 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5519 if (operands
[1].imm
.value
>= 32)
5521 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5525 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5529 /* LDR Wt, label | =value
5530 As a convenience assemblers will typically permit the notation
5531 "=value" in conjunction with the pc-relative literal load instructions
5532 to automatically place an immediate value or symbolic address in a
5533 nearby literal pool and generate a hidden label which references it.
5534 ISREG has been set to 0 in the case of =value. */
5535 if (instr
->gen_lit_pool
5536 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5538 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5539 if (op
== OP_LDRSW_LIT
)
5541 if (instr
->reloc
.exp
.X_op
!= O_constant
5542 && instr
->reloc
.exp
.X_op
!= O_big
5543 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5545 record_operand_error (opcode
, 1,
5546 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5547 _("constant expression expected"));
5550 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5552 record_operand_error (opcode
, 1,
5553 AARCH64_OPDE_OTHER_ERROR
,
5554 _("literal pool insertion failed"));
5562 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5563 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5564 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5565 A programmer-friendly assembler should accept a destination Xd in
5566 place of Wd, however that is not the preferred form for disassembly.
5568 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5569 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5570 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5571 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5576 /* In the 64-bit form, the final register operand is written as Wm
5577 for all but the (possibly omitted) UXTX/LSL and SXTX
5579 As a programmer-friendly assembler, we accept e.g.
5580 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5581 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5582 int idx
= aarch64_operand_index (opcode
->operands
,
5583 AARCH64_OPND_Rm_EXT
);
5584 gas_assert (idx
== 1 || idx
== 2);
5585 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5586 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5587 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5588 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5589 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5590 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5598 DEBUG_TRACE ("exit with SUCCESS");
5602 /* Check for loads and stores that will cause unpredictable behavior. */
5605 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5607 aarch64_inst
*base
= &instr
->base
;
5608 const aarch64_opcode
*opcode
= base
->opcode
;
5609 const aarch64_opnd_info
*opnds
= base
->operands
;
5610 switch (opcode
->iclass
)
5616 /* Loading/storing the base register is unpredictable if writeback. */
5617 if ((aarch64_get_operand_class (opnds
[0].type
)
5618 == AARCH64_OPND_CLASS_INT_REG
)
5619 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5620 && opnds
[1].addr
.base_regno
!= REG_SP
5621 && opnds
[1].addr
.writeback
)
5622 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5625 case ldstnapair_offs
:
5626 case ldstpair_indexed
:
5627 /* Loading/storing the base register is unpredictable if writeback. */
5628 if ((aarch64_get_operand_class (opnds
[0].type
)
5629 == AARCH64_OPND_CLASS_INT_REG
)
5630 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5631 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5632 && opnds
[2].addr
.base_regno
!= REG_SP
5633 && opnds
[2].addr
.writeback
)
5634 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5635 /* Load operations must load different registers. */
5636 if ((opcode
->opcode
& (1 << 22))
5637 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5638 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5645 /* A wrapper function to interface with libopcodes on encoding and
5646 record the error message if there is any.
5648 Return TRUE on success; otherwise return FALSE. */
5651 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5654 aarch64_operand_error error_info
;
5655 error_info
.kind
= AARCH64_OPDE_NIL
;
5656 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5660 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5661 record_operand_error_info (opcode
, &error_info
);
5666 #ifdef DEBUG_AARCH64
5668 dump_opcode_operands (const aarch64_opcode
*opcode
)
5671 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5673 aarch64_verbose ("\t\t opnd%d: %s", i
,
5674 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5675 ? aarch64_get_operand_name (opcode
->operands
[i
])
5676 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5680 #endif /* DEBUG_AARCH64 */
5682 /* This is the guts of the machine-dependent assembler. STR points to a
5683 machine dependent instruction. This function is supposed to emit
5684 the frags/bytes it assembles to. */
5687 md_assemble (char *str
)
5690 templates
*template;
5691 aarch64_opcode
*opcode
;
5692 aarch64_inst
*inst_base
;
5693 unsigned saved_cond
;
5695 /* Align the previous label if needed. */
5696 if (last_label_seen
!= NULL
)
5698 symbol_set_frag (last_label_seen
, frag_now
);
5699 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5700 S_SET_SEGMENT (last_label_seen
, now_seg
);
5703 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5705 DEBUG_TRACE ("\n\n");
5706 DEBUG_TRACE ("==============================");
5707 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5709 template = opcode_lookup (&p
);
5712 /* It wasn't an instruction, but it might be a register alias of
5713 the form alias .req reg directive. */
5714 if (!create_register_alias (str
, p
))
5715 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5720 skip_whitespace (p
);
5723 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5724 get_mnemonic_name (str
), str
);
5728 init_operand_error_report ();
5730 /* Sections are assumed to start aligned. In executable section, there is no
5731 MAP_DATA symbol pending. So we only align the address during
5732 MAP_DATA --> MAP_INSN transition.
5733 For other sections, this is not guaranteed. */
5734 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
5735 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
5736 frag_align_code (2, 0);
5738 saved_cond
= inst
.cond
;
5739 reset_aarch64_instruction (&inst
);
5740 inst
.cond
= saved_cond
;
5742 /* Iterate through all opcode entries with the same mnemonic name. */
5745 opcode
= template->opcode
;
5747 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5748 #ifdef DEBUG_AARCH64
5750 dump_opcode_operands (opcode
);
5751 #endif /* DEBUG_AARCH64 */
5753 mapping_state (MAP_INSN
);
5755 inst_base
= &inst
.base
;
5756 inst_base
->opcode
= opcode
;
5758 /* Truly conditionally executed instructions, e.g. b.cond. */
5759 if (opcode
->flags
& F_COND
)
5761 gas_assert (inst
.cond
!= COND_ALWAYS
);
5762 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5763 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5765 else if (inst
.cond
!= COND_ALWAYS
)
5767 /* It shouldn't arrive here, where the assembly looks like a
5768 conditional instruction but the found opcode is unconditional. */
5773 if (parse_operands (p
, opcode
)
5774 && programmer_friendly_fixup (&inst
)
5775 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5777 /* Check that this instruction is supported for this CPU. */
5778 if (!opcode
->avariant
5779 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5781 as_bad (_("selected processor does not support `%s'"), str
);
5785 warn_unpredictable_ldst (&inst
, str
);
5787 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5788 || !inst
.reloc
.need_libopcodes_p
)
5792 /* If there is relocation generated for the instruction,
5793 store the instruction information for the future fix-up. */
5794 struct aarch64_inst
*copy
;
5795 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5796 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5798 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5804 template = template->next
;
5805 if (template != NULL
)
5807 reset_aarch64_instruction (&inst
);
5808 inst
.cond
= saved_cond
;
5811 while (template != NULL
);
5813 /* Issue the error messages if any. */
5814 output_operand_error_report (str
);
5817 /* Various frobbings of labels and their addresses. */
5820 aarch64_start_line_hook (void)
5822 last_label_seen
= NULL
;
5826 aarch64_frob_label (symbolS
* sym
)
5828 last_label_seen
= sym
;
5830 dwarf2_emit_label (sym
);
5834 aarch64_data_in_code (void)
5836 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5838 *input_line_pointer
= '/';
5839 input_line_pointer
+= 5;
5840 *input_line_pointer
= 0;
5848 aarch64_canonicalize_symbol_name (char *name
)
5852 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
5853 *(name
+ len
- 5) = 0;
5858 /* Table of all register names defined by default. The user can
5859 define additional names with .req. Note that all register names
5860 should appear in both upper and lowercase variants. Some registers
5861 also have mixed-case names. */
5863 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5864 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5865 #define REGSET31(p,t) \
5866 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5867 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5868 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5869 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5870 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5871 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5872 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5873 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5874 #define REGSET(p,t) \
5875 REGSET31(p,t), REGNUM(p,31,t)
5877 /* These go into aarch64_reg_hsh hash-table. */
5878 static const reg_entry reg_names
[] = {
5879 /* Integer registers. */
5880 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
5881 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
5883 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
5884 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
5886 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
5887 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
5889 /* Coprocessor register numbers. */
5890 REGSET (c
, CN
), REGSET (C
, CN
),
5892 /* Floating-point single precision registers. */
5893 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
5895 /* Floating-point double precision registers. */
5896 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
5898 /* Floating-point half precision registers. */
5899 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
5901 /* Floating-point byte precision registers. */
5902 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
5904 /* Floating-point quad precision registers. */
5905 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
5907 /* FP/SIMD registers. */
5908 REGSET (v
, VN
), REGSET (V
, VN
),
5923 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5924 static const asm_nzcv nzcv_names
[] = {
5925 {"nzcv", B (n
, z
, c
, v
)},
5926 {"nzcV", B (n
, z
, c
, V
)},
5927 {"nzCv", B (n
, z
, C
, v
)},
5928 {"nzCV", B (n
, z
, C
, V
)},
5929 {"nZcv", B (n
, Z
, c
, v
)},
5930 {"nZcV", B (n
, Z
, c
, V
)},
5931 {"nZCv", B (n
, Z
, C
, v
)},
5932 {"nZCV", B (n
, Z
, C
, V
)},
5933 {"Nzcv", B (N
, z
, c
, v
)},
5934 {"NzcV", B (N
, z
, c
, V
)},
5935 {"NzCv", B (N
, z
, C
, v
)},
5936 {"NzCV", B (N
, z
, C
, V
)},
5937 {"NZcv", B (N
, Z
, c
, v
)},
5938 {"NZcV", B (N
, Z
, c
, V
)},
5939 {"NZCv", B (N
, Z
, C
, v
)},
5940 {"NZCV", B (N
, Z
, C
, V
)}
5953 /* MD interface: bits in the object file. */
5955 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5956 for use in the a.out file, and stores them in the array pointed to by buf.
5957 This knows about the endian-ness of the target machine and does
5958 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5959 2 (short) and 4 (long) Floating numbers are put out as a series of
5960 LITTLENUMS (shorts, here at least). */
5963 md_number_to_chars (char *buf
, valueT val
, int n
)
5965 if (target_big_endian
)
5966 number_to_chars_bigendian (buf
, val
, n
);
5968 number_to_chars_littleendian (buf
, val
, n
);
5971 /* MD interface: Sections. */
5973 /* Estimate the size of a frag before relaxing. Assume everything fits in
5977 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
5983 /* Round up a section size to the appropriate boundary. */
5986 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5991 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5992 of an rs_align_code fragment.
5994 Here we fill the frag with the appropriate info for padding the
5995 output stream. The resulting frag will consist of a fixed (fr_fix)
5996 and of a repeating (fr_var) part.
5998 The fixed content is always emitted before the repeating content and
5999 these two parts are used as follows in constructing the output:
6000 - the fixed part will be used to align to a valid instruction word
6001 boundary, in case that we start at a misaligned address; as no
6002 executable instruction can live at the misaligned location, we
6003 simply fill with zeros;
6004 - the variable part will be used to cover the remaining padding and
6005 we fill using the AArch64 NOP instruction.
6007 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6008 enough storage space for up to 3 bytes for padding the back to a valid
6009 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6012 aarch64_handle_align (fragS
* fragP
)
6014 /* NOP = d503201f */
6015 /* AArch64 instructions are always little-endian. */
6016 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6018 int bytes
, fix
, noop_size
;
6021 if (fragP
->fr_type
!= rs_align_code
)
6024 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6025 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6028 gas_assert (fragP
->tc_frag_data
.recorded
);
6031 noop_size
= sizeof (aarch64_noop
);
6033 fix
= bytes
& (noop_size
- 1);
6037 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6041 fragP
->fr_fix
+= fix
;
6045 memcpy (p
, aarch64_noop
, noop_size
);
6046 fragP
->fr_var
= noop_size
;
6049 /* Perform target specific initialisation of a frag.
6050 Note - despite the name this initialisation is not done when the frag
6051 is created, but only when its type is assigned. A frag can be created
6052 and used a long time before its type is set, so beware of assuming that
6053 this initialisationis performed first. */
6057 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6058 int max_chars ATTRIBUTE_UNUSED
)
6062 #else /* OBJ_ELF is defined. */
6064 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6066 /* Record a mapping symbol for alignment frags. We will delete this
6067 later if the alignment ends up empty. */
6068 if (!fragP
->tc_frag_data
.recorded
)
6069 fragP
->tc_frag_data
.recorded
= 1;
6071 switch (fragP
->fr_type
)
6076 mapping_state_2 (MAP_DATA
, max_chars
);
6079 mapping_state_2 (MAP_INSN
, max_chars
);
6086 /* Initialize the DWARF-2 unwind information for this procedure. */
6089 tc_aarch64_frame_initial_instructions (void)
6091 cfi_add_CFA_def_cfa (REG_SP
, 0);
6093 #endif /* OBJ_ELF */
6095 /* Convert REGNAME to a DWARF-2 register number. */
6098 tc_aarch64_regname_to_dw2regnum (char *regname
)
6100 const reg_entry
*reg
= parse_reg (®name
);
6106 case REG_TYPE_SP_32
:
6107 case REG_TYPE_SP_64
:
6117 return reg
->number
+ 64;
6125 /* Implement DWARF2_ADDR_SIZE. */
6128 aarch64_dwarf2_addr_size (void)
6130 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6134 return bfd_arch_bits_per_address (stdoutput
) / 8;
6137 /* MD interface: Symbol and relocation handling. */
6139 /* Return the address within the segment that a PC-relative fixup is
6140 relative to. For AArch64 PC-relative fixups applied to instructions
6141 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6144 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6146 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6148 /* If this is pc-relative and we are going to emit a relocation
6149 then we just want to put out any pipeline compensation that the linker
6150 will need. Otherwise we want to use the calculated base. */
6152 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6153 || aarch64_force_relocation (fixP
)))
6156 /* AArch64 should be consistent for all pc-relative relocations. */
6157 return base
+ AARCH64_PCREL_OFFSET
;
6160 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6161 Otherwise we have no need to default values of symbols. */
6164 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6167 if (name
[0] == '_' && name
[1] == 'G'
6168 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6172 if (symbol_find (name
))
6173 as_bad (_("GOT already in the symbol table"));
6175 GOT_symbol
= symbol_new (name
, undefined_section
,
6176 (valueT
) 0, &zero_address_frag
);
6186 /* Return non-zero if the indicated VALUE has overflowed the maximum
6187 range expressible by a unsigned number with the indicated number of
6191 unsigned_overflow (valueT value
, unsigned bits
)
6194 if (bits
>= sizeof (valueT
) * 8)
6196 lim
= (valueT
) 1 << bits
;
6197 return (value
>= lim
);
6201 /* Return non-zero if the indicated VALUE has overflowed the maximum
6202 range expressible by an signed number with the indicated number of
6206 signed_overflow (offsetT value
, unsigned bits
)
6209 if (bits
>= sizeof (offsetT
) * 8)
6211 lim
= (offsetT
) 1 << (bits
- 1);
6212 return (value
< -lim
|| value
>= lim
);
6215 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6216 unsigned immediate offset load/store instruction, try to encode it as
6217 an unscaled, 9-bit, signed immediate offset load/store instruction.
6218 Return TRUE if it is successful; otherwise return FALSE.
6220 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6221 in response to the standard LDR/STR mnemonics when the immediate offset is
6222 unambiguous, i.e. when it is negative or unaligned. */
6225 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6228 enum aarch64_op new_op
;
6229 const aarch64_opcode
*new_opcode
;
6231 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6233 switch (instr
->opcode
->op
)
6235 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6236 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6237 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6238 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6239 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6240 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6241 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6242 case OP_STR_POS
: new_op
= OP_STUR
; break;
6243 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6244 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6245 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6246 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6247 default: new_op
= OP_NIL
; break;
6250 if (new_op
== OP_NIL
)
6253 new_opcode
= aarch64_get_opcode (new_op
);
6254 gas_assert (new_opcode
!= NULL
);
6256 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6257 instr
->opcode
->op
, new_opcode
->op
);
6259 aarch64_replace_opcode (instr
, new_opcode
);
6261 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6262 qualifier matching may fail because the out-of-date qualifier will
6263 prevent the operand being updated with a new and correct qualifier. */
6264 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6265 AARCH64_OPND_ADDR_SIMM9
);
6266 gas_assert (idx
== 1);
6267 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6269 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6271 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6277 /* Called by fix_insn to fix a MOV immediate alias instruction.
6279 Operand for a generic move immediate instruction, which is an alias
6280 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6281 a 32-bit/64-bit immediate value into general register. An assembler error
6282 shall result if the immediate cannot be created by a single one of these
6283 instructions. If there is a choice, then to ensure reversability an
6284 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6287 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6289 const aarch64_opcode
*opcode
;
6291 /* Need to check if the destination is SP/ZR. The check has to be done
6292 before any aarch64_replace_opcode. */
6293 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6294 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6296 instr
->operands
[1].imm
.value
= value
;
6297 instr
->operands
[1].skip
= 0;
6301 /* Try the MOVZ alias. */
6302 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6303 aarch64_replace_opcode (instr
, opcode
);
6304 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6305 &instr
->value
, NULL
, NULL
))
6307 put_aarch64_insn (buf
, instr
->value
);
6310 /* Try the MOVK alias. */
6311 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6312 aarch64_replace_opcode (instr
, opcode
);
6313 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6314 &instr
->value
, NULL
, NULL
))
6316 put_aarch64_insn (buf
, instr
->value
);
6321 if (try_mov_bitmask_p
)
6323 /* Try the ORR alias. */
6324 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6325 aarch64_replace_opcode (instr
, opcode
);
6326 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6327 &instr
->value
, NULL
, NULL
))
6329 put_aarch64_insn (buf
, instr
->value
);
6334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6335 _("immediate cannot be moved by a single instruction"));
6338 /* An instruction operand which is immediate related may have symbol used
6339 in the assembly, e.g.
6342 .set u32, 0x00ffff00
6344 At the time when the assembly instruction is parsed, a referenced symbol,
6345 like 'u32' in the above example may not have been seen; a fixS is created
6346 in such a case and is handled here after symbols have been resolved.
6347 Instruction is fixed up with VALUE using the information in *FIXP plus
6348 extra information in FLAGS.
6350 This function is called by md_apply_fix to fix up instructions that need
6351 a fix-up described above but does not involve any linker-time relocation. */
6354 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6358 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6359 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6360 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6364 /* Now the instruction is about to be fixed-up, so the operand that
6365 was previously marked as 'ignored' needs to be unmarked in order
6366 to get the encoding done properly. */
6367 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6368 new_inst
->operands
[idx
].skip
= 0;
6371 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6375 case AARCH64_OPND_EXCEPTION
:
6376 if (unsigned_overflow (value
, 16))
6377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6378 _("immediate out of range"));
6379 insn
= get_aarch64_insn (buf
);
6380 insn
|= encode_svc_imm (value
);
6381 put_aarch64_insn (buf
, insn
);
6384 case AARCH64_OPND_AIMM
:
6385 /* ADD or SUB with immediate.
6386 NOTE this assumes we come here with a add/sub shifted reg encoding
6387 3 322|2222|2 2 2 21111 111111
6388 1 098|7654|3 2 1 09876 543210 98765 43210
6389 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6390 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6391 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6392 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6394 3 322|2222|2 2 221111111111
6395 1 098|7654|3 2 109876543210 98765 43210
6396 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6397 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6398 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6399 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6400 Fields sf Rn Rd are already set. */
6401 insn
= get_aarch64_insn (buf
);
6405 insn
= reencode_addsub_switch_add_sub (insn
);
6409 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6410 && unsigned_overflow (value
, 12))
6412 /* Try to shift the value by 12 to make it fit. */
6413 if (((value
>> 12) << 12) == value
6414 && ! unsigned_overflow (value
, 12 + 12))
6417 insn
|= encode_addsub_imm_shift_amount (1);
6421 if (unsigned_overflow (value
, 12))
6422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6423 _("immediate out of range"));
6425 insn
|= encode_addsub_imm (value
);
6427 put_aarch64_insn (buf
, insn
);
6430 case AARCH64_OPND_SIMD_IMM
:
6431 case AARCH64_OPND_SIMD_IMM_SFT
:
6432 case AARCH64_OPND_LIMM
:
6433 /* Bit mask immediate. */
6434 gas_assert (new_inst
!= NULL
);
6435 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6436 new_inst
->operands
[idx
].imm
.value
= value
;
6437 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6438 &new_inst
->value
, NULL
, NULL
))
6439 put_aarch64_insn (buf
, new_inst
->value
);
6441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6442 _("invalid immediate"));
6445 case AARCH64_OPND_HALF
:
6446 /* 16-bit unsigned immediate. */
6447 if (unsigned_overflow (value
, 16))
6448 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6449 _("immediate out of range"));
6450 insn
= get_aarch64_insn (buf
);
6451 insn
|= encode_movw_imm (value
& 0xffff);
6452 put_aarch64_insn (buf
, insn
);
6455 case AARCH64_OPND_IMM_MOV
:
6456 /* Operand for a generic move immediate instruction, which is
6457 an alias instruction that generates a single MOVZ, MOVN or ORR
6458 instruction to loads a 32-bit/64-bit immediate value into general
6459 register. An assembler error shall result if the immediate cannot be
6460 created by a single one of these instructions. If there is a choice,
6461 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6462 and MOVZ or MOVN to ORR. */
6463 gas_assert (new_inst
!= NULL
);
6464 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6467 case AARCH64_OPND_ADDR_SIMM7
:
6468 case AARCH64_OPND_ADDR_SIMM9
:
6469 case AARCH64_OPND_ADDR_SIMM9_2
:
6470 case AARCH64_OPND_ADDR_UIMM12
:
6471 /* Immediate offset in an address. */
6472 insn
= get_aarch64_insn (buf
);
6474 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6475 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6476 || new_inst
->opcode
->operands
[2] == opnd
);
6478 /* Get the index of the address operand. */
6479 if (new_inst
->opcode
->operands
[1] == opnd
)
6480 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6483 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6486 /* Update the resolved offset value. */
6487 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6489 /* Encode/fix-up. */
6490 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6491 &new_inst
->value
, NULL
, NULL
))
6493 put_aarch64_insn (buf
, new_inst
->value
);
6496 else if (new_inst
->opcode
->iclass
== ldst_pos
6497 && try_to_encode_as_unscaled_ldst (new_inst
))
6499 put_aarch64_insn (buf
, new_inst
->value
);
6503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6504 _("immediate offset out of range"));
6509 as_fatal (_("unhandled operand code %d"), opnd
);
6513 /* Apply a fixup (fixP) to segment data, once it has been determined
6514 by our caller that we have all the info we need to fix it up.
6516 Parameter valP is the pointer to the value of the bits. */
6519 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6521 offsetT value
= *valP
;
6523 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6525 unsigned flags
= fixP
->fx_addnumber
;
6527 DEBUG_TRACE ("\n\n");
6528 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6529 DEBUG_TRACE ("Enter md_apply_fix");
6531 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6533 /* Note whether this will delete the relocation. */
6535 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6538 /* Process the relocations. */
6539 switch (fixP
->fx_r_type
)
6541 case BFD_RELOC_NONE
:
6542 /* This will need to go in the object file. */
6547 case BFD_RELOC_8_PCREL
:
6548 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6549 md_number_to_chars (buf
, value
, 1);
6553 case BFD_RELOC_16_PCREL
:
6554 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6555 md_number_to_chars (buf
, value
, 2);
6559 case BFD_RELOC_32_PCREL
:
6560 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6561 md_number_to_chars (buf
, value
, 4);
6565 case BFD_RELOC_64_PCREL
:
6566 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6567 md_number_to_chars (buf
, value
, 8);
6570 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6571 /* We claim that these fixups have been processed here, even if
6572 in fact we generate an error because we do not have a reloc
6573 for them, so tc_gen_reloc() will reject them. */
6575 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6578 _("undefined symbol %s used as an immediate value"),
6579 S_GET_NAME (fixP
->fx_addsy
));
6580 goto apply_fix_return
;
6582 fix_insn (fixP
, flags
, value
);
6585 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6586 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6590 _("pc-relative load offset not word aligned"));
6591 if (signed_overflow (value
, 21))
6592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6593 _("pc-relative load offset out of range"));
6594 insn
= get_aarch64_insn (buf
);
6595 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6596 put_aarch64_insn (buf
, insn
);
6600 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6601 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6603 if (signed_overflow (value
, 21))
6604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6605 _("pc-relative address offset out of range"));
6606 insn
= get_aarch64_insn (buf
);
6607 insn
|= encode_adr_imm (value
);
6608 put_aarch64_insn (buf
, insn
);
6612 case BFD_RELOC_AARCH64_BRANCH19
:
6613 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6616 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6617 _("conditional branch target not word aligned"));
6618 if (signed_overflow (value
, 21))
6619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6620 _("conditional branch out of range"));
6621 insn
= get_aarch64_insn (buf
);
6622 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6623 put_aarch64_insn (buf
, insn
);
6627 case BFD_RELOC_AARCH64_TSTBR14
:
6628 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6632 _("conditional branch target not word aligned"));
6633 if (signed_overflow (value
, 16))
6634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6635 _("conditional branch out of range"));
6636 insn
= get_aarch64_insn (buf
);
6637 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6638 put_aarch64_insn (buf
, insn
);
6642 case BFD_RELOC_AARCH64_CALL26
:
6643 case BFD_RELOC_AARCH64_JUMP26
:
6644 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6648 _("branch target not word aligned"));
6649 if (signed_overflow (value
, 28))
6650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6651 _("branch out of range"));
6652 insn
= get_aarch64_insn (buf
);
6653 insn
|= encode_branch_ofs_26 (value
>> 2);
6654 put_aarch64_insn (buf
, insn
);
6658 case BFD_RELOC_AARCH64_MOVW_G0
:
6659 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6660 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6663 case BFD_RELOC_AARCH64_MOVW_G1
:
6664 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6665 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6668 case BFD_RELOC_AARCH64_MOVW_G2
:
6669 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6670 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6673 case BFD_RELOC_AARCH64_MOVW_G3
:
6676 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6678 insn
= get_aarch64_insn (buf
);
6682 /* REL signed addend must fit in 16 bits */
6683 if (signed_overflow (value
, 16))
6684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6685 _("offset out of range"));
6689 /* Check for overflow and scale. */
6690 switch (fixP
->fx_r_type
)
6692 case BFD_RELOC_AARCH64_MOVW_G0
:
6693 case BFD_RELOC_AARCH64_MOVW_G1
:
6694 case BFD_RELOC_AARCH64_MOVW_G2
:
6695 case BFD_RELOC_AARCH64_MOVW_G3
:
6696 if (unsigned_overflow (value
, scale
+ 16))
6697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6698 _("unsigned value out of range"));
6700 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6701 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6702 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6703 /* NOTE: We can only come here with movz or movn. */
6704 if (signed_overflow (value
, scale
+ 16))
6705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6706 _("signed value out of range"));
6709 /* Force use of MOVN. */
6711 insn
= reencode_movzn_to_movn (insn
);
6715 /* Force use of MOVZ. */
6716 insn
= reencode_movzn_to_movz (insn
);
6720 /* Unchecked relocations. */
6726 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6727 insn
|= encode_movw_imm (value
& 0xffff);
6729 put_aarch64_insn (buf
, insn
);
6733 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6734 fixP
->fx_r_type
= (ilp32_p
6735 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6736 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
6737 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6738 /* Should always be exported to object file, see
6739 aarch64_force_relocation(). */
6740 gas_assert (!fixP
->fx_done
);
6741 gas_assert (seg
->use_rela_p
);
6744 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6745 fixP
->fx_r_type
= (ilp32_p
6746 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6747 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
6748 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6749 /* Should always be exported to object file, see
6750 aarch64_force_relocation(). */
6751 gas_assert (!fixP
->fx_done
);
6752 gas_assert (seg
->use_rela_p
);
6755 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6756 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6757 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6758 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6759 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6760 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6761 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6762 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6763 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6764 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6765 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6766 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6767 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6768 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6769 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6770 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6771 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6772 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6773 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6774 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6775 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6776 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6777 /* Should always be exported to object file, see
6778 aarch64_force_relocation(). */
6779 gas_assert (!fixP
->fx_done
);
6780 gas_assert (seg
->use_rela_p
);
6783 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6784 /* Should always be exported to object file, see
6785 aarch64_force_relocation(). */
6786 fixP
->fx_r_type
= (ilp32_p
6787 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6788 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
6789 gas_assert (!fixP
->fx_done
);
6790 gas_assert (seg
->use_rela_p
);
6793 case BFD_RELOC_AARCH64_ADD_LO12
:
6794 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6795 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6796 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6797 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6798 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6799 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
6800 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
6801 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
6802 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6803 case BFD_RELOC_AARCH64_LDST128_LO12
:
6804 case BFD_RELOC_AARCH64_LDST16_LO12
:
6805 case BFD_RELOC_AARCH64_LDST32_LO12
:
6806 case BFD_RELOC_AARCH64_LDST64_LO12
:
6807 case BFD_RELOC_AARCH64_LDST8_LO12
:
6808 /* Should always be exported to object file, see
6809 aarch64_force_relocation(). */
6810 gas_assert (!fixP
->fx_done
);
6811 gas_assert (seg
->use_rela_p
);
6814 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6815 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6816 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6819 case BFD_RELOC_UNUSED
:
6820 /* An error will already have been reported. */
6824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6825 _("unexpected %s fixup"),
6826 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6831 /* Free the allocated the struct aarch64_inst.
6832 N.B. currently there are very limited number of fix-up types actually use
6833 this field, so the impact on the performance should be minimal . */
6834 if (fixP
->tc_fix_data
.inst
!= NULL
)
6835 free (fixP
->tc_fix_data
.inst
);
6840 /* Translate internal representation of relocation info to BFD target
6844 tc_gen_reloc (asection
* section
, fixS
* fixp
)
6847 bfd_reloc_code_real_type code
;
6849 reloc
= xmalloc (sizeof (arelent
));
6851 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
6852 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6853 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6857 if (section
->use_rela_p
)
6858 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
6860 fixp
->fx_offset
= reloc
->address
;
6862 reloc
->addend
= fixp
->fx_offset
;
6864 code
= fixp
->fx_r_type
;
6869 code
= BFD_RELOC_16_PCREL
;
6874 code
= BFD_RELOC_32_PCREL
;
6879 code
= BFD_RELOC_64_PCREL
;
6886 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6887 if (reloc
->howto
== NULL
)
6889 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6891 ("cannot represent %s relocation in this object file format"),
6892 bfd_get_reloc_code_name (code
));
6899 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6902 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
6904 bfd_reloc_code_real_type type
;
6908 FIXME: @@ Should look at CPU word size. */
6915 type
= BFD_RELOC_16
;
6918 type
= BFD_RELOC_32
;
6921 type
= BFD_RELOC_64
;
6924 as_bad (_("cannot do %u-byte relocation"), size
);
6925 type
= BFD_RELOC_UNUSED
;
6929 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6933 aarch64_force_relocation (struct fix
*fixp
)
6935 switch (fixp
->fx_r_type
)
6937 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6938 /* Perform these "immediate" internal relocations
6939 even if the symbol is extern or weak. */
6942 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6943 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6944 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6945 /* Pseudo relocs that need to be fixed up according to
6949 case BFD_RELOC_AARCH64_ADD_LO12
:
6950 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6951 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6952 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6953 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6954 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6955 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
6956 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
6957 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
6958 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6959 case BFD_RELOC_AARCH64_LDST128_LO12
:
6960 case BFD_RELOC_AARCH64_LDST16_LO12
:
6961 case BFD_RELOC_AARCH64_LDST32_LO12
:
6962 case BFD_RELOC_AARCH64_LDST64_LO12
:
6963 case BFD_RELOC_AARCH64_LDST8_LO12
:
6964 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6965 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6966 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6967 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6968 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6969 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6970 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6971 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6972 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6973 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6974 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6975 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6976 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6977 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6978 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6979 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6980 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6981 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6982 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6983 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6984 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6985 /* Always leave these relocations for the linker. */
6992 return generic_force_reloc (fixp
);
6998 elf64_aarch64_target_format (void)
7000 if (target_big_endian
)
7001 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7003 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7007 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7009 elf_frob_symbol (symp
, puntp
);
7013 /* MD interface: Finalization. */
7015 /* A good place to do this, although this was probably not intended
7016 for this kind of use. We need to dump the literal pool before
7017 references are made to a null symbol pointer. */
7020 aarch64_cleanup (void)
7024 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7026 /* Put it at the end of the relevant section. */
7027 subseg_set (pool
->section
, pool
->sub_section
);
7033 /* Remove any excess mapping symbols generated for alignment frags in
7034 SEC. We may have created a mapping symbol before a zero byte
7035 alignment; remove it if there's a mapping symbol after the
7038 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7039 void *dummy ATTRIBUTE_UNUSED
)
7041 segment_info_type
*seginfo
= seg_info (sec
);
7044 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7047 for (fragp
= seginfo
->frchainP
->frch_root
;
7048 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7050 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7051 fragS
*next
= fragp
->fr_next
;
7053 /* Variable-sized frags have been converted to fixed size by
7054 this point. But if this was variable-sized to start with,
7055 there will be a fixed-size frag after it. So don't handle
7057 if (sym
== NULL
|| next
== NULL
)
7060 if (S_GET_VALUE (sym
) < next
->fr_address
)
7061 /* Not at the end of this frag. */
7063 know (S_GET_VALUE (sym
) == next
->fr_address
);
7067 if (next
->tc_frag_data
.first_map
!= NULL
)
7069 /* Next frag starts with a mapping symbol. Discard this
7071 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7075 if (next
->fr_next
== NULL
)
7077 /* This mapping symbol is at the end of the section. Discard
7079 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7080 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7084 /* As long as we have empty frags without any mapping symbols,
7086 /* If the next frag is non-empty and does not start with a
7087 mapping symbol, then this mapping symbol is required. */
7088 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7091 next
= next
->fr_next
;
7093 while (next
!= NULL
);
7098 /* Adjust the symbol table. */
7101 aarch64_adjust_symtab (void)
7104 /* Remove any overlapping mapping symbols generated by alignment frags. */
7105 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7106 /* Now do generic ELF adjustments. */
7107 elf_adjust_symtab ();
7112 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7114 const char *hash_err
;
7116 hash_err
= hash_insert (table
, key
, value
);
7118 printf ("Internal Error: Can't hash %s\n", key
);
7122 fill_instruction_hash_table (void)
7124 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7126 while (opcode
->name
!= NULL
)
7128 templates
*templ
, *new_templ
;
7129 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7131 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7132 new_templ
->opcode
= opcode
;
7133 new_templ
->next
= NULL
;
7136 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7139 new_templ
->next
= templ
->next
;
7140 templ
->next
= new_templ
;
7147 convert_to_upper (char *dst
, const char *src
, size_t num
)
7150 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7151 *dst
= TOUPPER (*src
);
7155 /* Assume STR point to a lower-case string, allocate, convert and return
7156 the corresponding upper-case string. */
7157 static inline const char*
7158 get_upper_str (const char *str
)
7161 size_t len
= strlen (str
);
7162 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7164 convert_to_upper (ret
, str
, len
);
7168 /* MD interface: Initialization. */
7176 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7177 || (aarch64_cond_hsh
= hash_new ()) == NULL
7178 || (aarch64_shift_hsh
= hash_new ()) == NULL
7179 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7180 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7181 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7182 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7183 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7184 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7185 || (aarch64_reg_hsh
= hash_new ()) == NULL
7186 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7187 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7188 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
7189 as_fatal (_("virtual memory exhausted"));
7191 fill_instruction_hash_table ();
7193 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7194 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7195 (void *) (aarch64_sys_regs
+ i
));
7197 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7198 checked_hash_insert (aarch64_pstatefield_hsh
,
7199 aarch64_pstatefields
[i
].name
,
7200 (void *) (aarch64_pstatefields
+ i
));
7202 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
7203 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7204 aarch64_sys_regs_ic
[i
].template,
7205 (void *) (aarch64_sys_regs_ic
+ i
));
7207 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
7208 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7209 aarch64_sys_regs_dc
[i
].template,
7210 (void *) (aarch64_sys_regs_dc
+ i
));
7212 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
7213 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7214 aarch64_sys_regs_at
[i
].template,
7215 (void *) (aarch64_sys_regs_at
+ i
));
7217 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
7218 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7219 aarch64_sys_regs_tlbi
[i
].template,
7220 (void *) (aarch64_sys_regs_tlbi
+ i
));
7222 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7223 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7224 (void *) (reg_names
+ i
));
7226 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7227 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7228 (void *) (nzcv_names
+ i
));
7230 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7232 const char *name
= aarch64_operand_modifiers
[i
].name
;
7233 checked_hash_insert (aarch64_shift_hsh
, name
,
7234 (void *) (aarch64_operand_modifiers
+ i
));
7235 /* Also hash the name in the upper case. */
7236 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7237 (void *) (aarch64_operand_modifiers
+ i
));
7240 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7243 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7244 the same condition code. */
7245 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7247 const char *name
= aarch64_conds
[i
].names
[j
];
7250 checked_hash_insert (aarch64_cond_hsh
, name
,
7251 (void *) (aarch64_conds
+ i
));
7252 /* Also hash the name in the upper case. */
7253 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7254 (void *) (aarch64_conds
+ i
));
7258 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7260 const char *name
= aarch64_barrier_options
[i
].name
;
7261 /* Skip xx00 - the unallocated values of option. */
7264 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7265 (void *) (aarch64_barrier_options
+ i
));
7266 /* Also hash the name in the upper case. */
7267 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7268 (void *) (aarch64_barrier_options
+ i
));
7271 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7273 const char* name
= aarch64_prfops
[i
].name
;
7274 /* Skip the unallocated hint encodings. */
7277 checked_hash_insert (aarch64_pldop_hsh
, name
,
7278 (void *) (aarch64_prfops
+ i
));
7279 /* Also hash the name in the upper case. */
7280 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7281 (void *) (aarch64_prfops
+ i
));
7284 /* Set the cpu variant based on the command-line options. */
7286 mcpu_cpu_opt
= march_cpu_opt
;
7289 mcpu_cpu_opt
= &cpu_default
;
7291 cpu_variant
= *mcpu_cpu_opt
;
7293 /* Record the CPU type. */
7294 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7296 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7299 /* Command line processing. */
7301 const char *md_shortopts
= "m:";
7303 #ifdef AARCH64_BI_ENDIAN
7304 #define OPTION_EB (OPTION_MD_BASE + 0)
7305 #define OPTION_EL (OPTION_MD_BASE + 1)
7307 #if TARGET_BYTES_BIG_ENDIAN
7308 #define OPTION_EB (OPTION_MD_BASE + 0)
7310 #define OPTION_EL (OPTION_MD_BASE + 1)
7314 struct option md_longopts
[] = {
7316 {"EB", no_argument
, NULL
, OPTION_EB
},
7319 {"EL", no_argument
, NULL
, OPTION_EL
},
7321 {NULL
, no_argument
, NULL
, 0}
7324 size_t md_longopts_size
= sizeof (md_longopts
);
7326 struct aarch64_option_table
7328 char *option
; /* Option name to match. */
7329 char *help
; /* Help information. */
7330 int *var
; /* Variable to change. */
7331 int value
; /* What to change it to. */
7332 char *deprecated
; /* If non-null, print this message. */
7335 static struct aarch64_option_table aarch64_opts
[] = {
7336 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7337 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7339 #ifdef DEBUG_AARCH64
7340 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7341 #endif /* DEBUG_AARCH64 */
7342 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7344 {"mno-verbose-error", N_("do not output verbose error messages"),
7345 &verbose_error_p
, 0, NULL
},
7346 {NULL
, NULL
, NULL
, 0, NULL
}
7349 struct aarch64_cpu_option_table
7352 const aarch64_feature_set value
;
7353 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7355 const char *canonical_name
;
7358 /* This list should, at a minimum, contain all the cpu names
7359 recognized by GCC. */
7360 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7361 {"all", AARCH64_ANY
, NULL
},
7362 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7363 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7364 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7365 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7366 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7367 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7368 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7369 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7370 "Samsung Exynos M1"},
7371 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7372 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7374 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7375 in earlier releases and is superseded by 'xgene1' in all
7377 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7378 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7379 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7380 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7381 {"generic", AARCH64_ARCH_V8
, NULL
},
7383 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7386 struct aarch64_arch_option_table
7389 const aarch64_feature_set value
;
7392 /* This list should, at a minimum, contain all the architecture names
7393 recognized by GCC. */
7394 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7395 {"all", AARCH64_ANY
},
7396 {"armv8-a", AARCH64_ARCH_V8
},
7397 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7398 {NULL
, AARCH64_ARCH_NONE
}
7401 /* ISA extensions. */
7402 struct aarch64_option_cpu_value_table
7405 const aarch64_feature_set value
;
7408 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7409 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7410 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7411 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7412 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7413 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7414 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0)},
7415 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0)},
7416 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7417 | AARCH64_FEATURE_RDMA
, 0)},
7418 {NULL
, AARCH64_ARCH_NONE
}
7421 struct aarch64_long_option_table
7423 char *option
; /* Substring to match. */
7424 char *help
; /* Help information. */
7425 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7426 char *deprecated
; /* If non-null, print this message. */
7430 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7431 bfd_boolean ext_only
)
7433 /* We insist on extensions being added before being removed. We achieve
7434 this by using the ADDING_VALUE variable to indicate whether we are
7435 adding an extension (1) or removing it (0) and only allowing it to
7436 change in the order -1 -> 1 -> 0. */
7437 int adding_value
= -1;
7438 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7440 /* Copy the feature set, so that we can modify it. */
7444 while (str
!= NULL
&& *str
!= 0)
7446 const struct aarch64_option_cpu_value_table
*opt
;
7454 as_bad (_("invalid architectural extension"));
7458 ext
= strchr (++str
, '+');
7464 optlen
= strlen (str
);
7466 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7468 if (adding_value
!= 0)
7473 else if (optlen
> 0)
7475 if (adding_value
== -1)
7477 else if (adding_value
!= 1)
7479 as_bad (_("must specify extensions to add before specifying "
7480 "those to remove"));
7487 as_bad (_("missing architectural extension"));
7491 gas_assert (adding_value
!= -1);
7493 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7494 if (strncmp (opt
->name
, str
, optlen
) == 0)
7496 /* Add or remove the extension. */
7498 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7500 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7504 if (opt
->name
== NULL
)
7506 as_bad (_("unknown architectural extension `%s'"), str
);
7517 aarch64_parse_cpu (char *str
)
7519 const struct aarch64_cpu_option_table
*opt
;
7520 char *ext
= strchr (str
, '+');
7526 optlen
= strlen (str
);
7530 as_bad (_("missing cpu name `%s'"), str
);
7534 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7535 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7537 mcpu_cpu_opt
= &opt
->value
;
7539 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7544 as_bad (_("unknown cpu `%s'"), str
);
7549 aarch64_parse_arch (char *str
)
7551 const struct aarch64_arch_option_table
*opt
;
7552 char *ext
= strchr (str
, '+');
7558 optlen
= strlen (str
);
7562 as_bad (_("missing architecture name `%s'"), str
);
7566 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7567 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7569 march_cpu_opt
= &opt
->value
;
7571 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7576 as_bad (_("unknown architecture `%s'\n"), str
);
7581 struct aarch64_option_abi_value_table
7584 enum aarch64_abi_type value
;
7587 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7588 {"ilp32", AARCH64_ABI_ILP32
},
7589 {"lp64", AARCH64_ABI_LP64
},
7594 aarch64_parse_abi (char *str
)
7596 const struct aarch64_option_abi_value_table
*opt
;
7597 size_t optlen
= strlen (str
);
7601 as_bad (_("missing abi name `%s'"), str
);
7605 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
7606 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7608 aarch64_abi
= opt
->value
;
7612 as_bad (_("unknown abi `%s'\n"), str
);
7616 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7618 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7619 aarch64_parse_abi
, NULL
},
7620 #endif /* OBJ_ELF */
7621 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7622 aarch64_parse_cpu
, NULL
},
7623 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7624 aarch64_parse_arch
, NULL
},
7625 {NULL
, NULL
, 0, NULL
}
7629 md_parse_option (int c
, char *arg
)
7631 struct aarch64_option_table
*opt
;
7632 struct aarch64_long_option_table
*lopt
;
7638 target_big_endian
= 1;
7644 target_big_endian
= 0;
7649 /* Listing option. Just ignore these, we don't support additional
7654 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7656 if (c
== opt
->option
[0]
7657 && ((arg
== NULL
&& opt
->option
[1] == 0)
7658 || streq (arg
, opt
->option
+ 1)))
7660 /* If the option is deprecated, tell the user. */
7661 if (opt
->deprecated
!= NULL
)
7662 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7663 arg
? arg
: "", _(opt
->deprecated
));
7665 if (opt
->var
!= NULL
)
7666 *opt
->var
= opt
->value
;
7672 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7674 /* These options are expected to have an argument. */
7675 if (c
== lopt
->option
[0]
7677 && strncmp (arg
, lopt
->option
+ 1,
7678 strlen (lopt
->option
+ 1)) == 0)
7680 /* If the option is deprecated, tell the user. */
7681 if (lopt
->deprecated
!= NULL
)
7682 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7683 _(lopt
->deprecated
));
7685 /* Call the sup-option parser. */
7686 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7697 md_show_usage (FILE * fp
)
7699 struct aarch64_option_table
*opt
;
7700 struct aarch64_long_option_table
*lopt
;
7702 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7704 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7705 if (opt
->help
!= NULL
)
7706 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7708 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7709 if (lopt
->help
!= NULL
)
7710 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7714 -EB assemble code for a big-endian cpu\n"));
7719 -EL assemble code for a little-endian cpu\n"));
7723 /* Parse a .cpu directive. */
7726 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7728 const struct aarch64_cpu_option_table
*opt
;
7734 name
= input_line_pointer
;
7735 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7736 input_line_pointer
++;
7737 saved_char
= *input_line_pointer
;
7738 *input_line_pointer
= 0;
7740 ext
= strchr (name
, '+');
7743 optlen
= ext
- name
;
7745 optlen
= strlen (name
);
7747 /* Skip the first "all" entry. */
7748 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7749 if (strlen (opt
->name
) == optlen
7750 && strncmp (name
, opt
->name
, optlen
) == 0)
7752 mcpu_cpu_opt
= &opt
->value
;
7754 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7757 cpu_variant
= *mcpu_cpu_opt
;
7759 *input_line_pointer
= saved_char
;
7760 demand_empty_rest_of_line ();
7763 as_bad (_("unknown cpu `%s'"), name
);
7764 *input_line_pointer
= saved_char
;
7765 ignore_rest_of_line ();
7769 /* Parse a .arch directive. */
7772 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7774 const struct aarch64_arch_option_table
*opt
;
7780 name
= input_line_pointer
;
7781 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7782 input_line_pointer
++;
7783 saved_char
= *input_line_pointer
;
7784 *input_line_pointer
= 0;
7786 ext
= strchr (name
, '+');
7789 optlen
= ext
- name
;
7791 optlen
= strlen (name
);
7793 /* Skip the first "all" entry. */
7794 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7795 if (strlen (opt
->name
) == optlen
7796 && strncmp (name
, opt
->name
, optlen
) == 0)
7798 mcpu_cpu_opt
= &opt
->value
;
7800 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7803 cpu_variant
= *mcpu_cpu_opt
;
7805 *input_line_pointer
= saved_char
;
7806 demand_empty_rest_of_line ();
7810 as_bad (_("unknown architecture `%s'\n"), name
);
7811 *input_line_pointer
= saved_char
;
7812 ignore_rest_of_line ();
7815 /* Parse a .arch_extension directive. */
7818 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
7821 char *ext
= input_line_pointer
;;
7823 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7824 input_line_pointer
++;
7825 saved_char
= *input_line_pointer
;
7826 *input_line_pointer
= 0;
7828 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
7831 cpu_variant
= *mcpu_cpu_opt
;
7833 *input_line_pointer
= saved_char
;
7834 demand_empty_rest_of_line ();
7837 /* Copy symbol information. */
7840 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
7842 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);