1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the license, or
12 (at your option) any later version.
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "bfd_stdint.h"
28 #include "safe-ctype.h"
33 #include "elf/aarch64.h"
34 #include "dw2gencfi.h"
37 #include "dwarf2dbg.h"
39 /* Types of processor to assemble for. */
41 #define CPU_DEFAULT AARCH64_ARCH_V8
44 #define streq(a, b) (strcmp (a, b) == 0)
46 static aarch64_feature_set cpu_variant
;
48 /* Variables that we set while parsing command-line options. Once all
49 options have been read we re-process these values to set the real
51 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
52 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
54 /* Constants for known architecture features. */
55 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
57 static const aarch64_feature_set aarch64_arch_any
= AARCH64_ANY
;
58 static const aarch64_feature_set aarch64_arch_none
= AARCH64_ARCH_NONE
;
61 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
62 static symbolS
*GOT_symbol
;
75 /* Bits for DEFINED field in neon_type_el. */
77 #define NTA_HASINDEX 2
81 enum neon_el_type type
;
82 unsigned char defined
;
87 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
91 bfd_reloc_code_real_type type
;
94 enum aarch64_opnd opnd
;
96 unsigned need_libopcodes_p
: 1;
99 struct aarch64_instruction
101 /* libopcodes structure for instruction intermediate representation. */
103 /* Record assembly errors found during the parsing. */
106 enum aarch64_operand_error_kind kind
;
109 /* The condition that appears in the assembly line. */
111 /* Relocation information (including the GAS internal fixup). */
113 /* Need to generate an immediate in the literal pool. */
114 unsigned gen_lit_pool
: 1;
117 typedef struct aarch64_instruction aarch64_instruction
;
119 static aarch64_instruction inst
;
121 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
122 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
124 /* Diagnostics inline function utilites.
126 These are lightweight utlities which should only be called by parse_operands
127 and other parsers. GAS processes each assembly line by parsing it against
128 instruction template(s), in the case of multiple templates (for the same
129 mnemonic name), those templates are tried one by one until one succeeds or
130 all fail. An assembly line may fail a few templates before being
131 successfully parsed; an error saved here in most cases is not a user error
132 but an error indicating the current template is not the right template.
133 Therefore it is very important that errors can be saved at a low cost during
134 the parsing; we don't want to slow down the whole parsing by recording
135 non-user errors in detail.
137 Remember that the objective is to help GAS pick up the most approapriate
138 error message in the case of multiple templates, e.g. FMOV which has 8
144 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
145 inst
.parsing_error
.error
= NULL
;
148 static inline bfd_boolean
151 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
154 static inline const char *
155 get_error_message (void)
157 return inst
.parsing_error
.error
;
161 set_error_message (const char *error
)
163 inst
.parsing_error
.error
= error
;
166 static inline enum aarch64_operand_error_kind
167 get_error_kind (void)
169 return inst
.parsing_error
.kind
;
173 set_error_kind (enum aarch64_operand_error_kind kind
)
175 inst
.parsing_error
.kind
= kind
;
179 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
181 inst
.parsing_error
.kind
= kind
;
182 inst
.parsing_error
.error
= error
;
186 set_recoverable_error (const char *error
)
188 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
191 /* Use the DESC field of the corresponding aarch64_operand entry to compose
192 the error message. */
194 set_default_error (void)
196 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
200 set_syntax_error (const char *error
)
202 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
206 set_first_syntax_error (const char *error
)
209 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
213 set_fatal_syntax_error (const char *error
)
215 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
218 /* Number of littlenums required to hold an extended precision number. */
219 #define MAX_LITTLENUMS 6
221 /* Return value for certain parsers when the parsing fails; those parsers
222 return the information of the parsed result, e.g. register number, on
224 #define PARSE_FAIL -1
226 /* This is an invalid condition code that means no conditional field is
228 #define COND_ALWAYS 0x10
232 const char *template;
238 const char *template;
245 bfd_reloc_code_real_type reloc
;
248 /* Structure for a hash table entry for a register. */
252 unsigned char number
;
254 unsigned char builtin
;
257 /* Macros to define the register types and masks for the purpose
260 #undef AARCH64_REG_TYPES
261 #define AARCH64_REG_TYPES \
262 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
263 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
264 BASIC_REG_TYPE(SP_32) /* wsp */ \
265 BASIC_REG_TYPE(SP_64) /* sp */ \
266 BASIC_REG_TYPE(Z_32) /* wzr */ \
267 BASIC_REG_TYPE(Z_64) /* xzr */ \
268 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
269 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
270 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
271 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
272 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
273 BASIC_REG_TYPE(CN) /* c[0-7] */ \
274 BASIC_REG_TYPE(VN) /* v[0-31] */ \
275 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
276 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
277 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
278 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
279 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
280 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
281 /* Typecheck: any [BHSDQ]P FP. */ \
282 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
283 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
284 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
285 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
286 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
287 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
288 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
289 /* Any integer register; used for error messages only. */ \
290 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
291 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
292 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
293 /* Pseudo type to mark the end of the enumerator sequence. */ \
296 #undef BASIC_REG_TYPE
297 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
298 #undef MULTI_REG_TYPE
299 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
301 /* Register type enumerators. */
304 /* A list of REG_TYPE_*. */
308 #undef BASIC_REG_TYPE
309 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
311 #define REG_TYPE(T) (1 << REG_TYPE_##T)
312 #undef MULTI_REG_TYPE
313 #define MULTI_REG_TYPE(T,V) V,
315 /* Values indexed by aarch64_reg_type to assist the type checking. */
316 static const unsigned reg_type_masks
[] =
321 #undef BASIC_REG_TYPE
323 #undef MULTI_REG_TYPE
324 #undef AARCH64_REG_TYPES
326 /* Diagnostics used when we don't get a register of the expected type.
327 Note: this has to synchronized with aarch64_reg_type definitions
330 get_reg_expected_msg (aarch64_reg_type reg_type
)
337 msg
= N_("integer 32-bit register expected");
340 msg
= N_("integer 64-bit register expected");
343 msg
= N_("integer register expected");
345 case REG_TYPE_R_Z_SP
:
346 msg
= N_("integer, zero or SP register expected");
349 msg
= N_("8-bit SIMD scalar register expected");
352 msg
= N_("16-bit SIMD scalar or floating-point half precision "
353 "register expected");
356 msg
= N_("32-bit SIMD scalar or floating-point single precision "
357 "register expected");
360 msg
= N_("64-bit SIMD scalar or floating-point double precision "
361 "register expected");
364 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
365 "register expected");
368 msg
= N_("C0 - C15 expected");
370 case REG_TYPE_R_Z_BHSDQ_V
:
371 msg
= N_("register expected");
373 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
374 msg
= N_("SIMD scalar or floating-point register expected");
376 case REG_TYPE_VN
: /* any V reg */
377 msg
= N_("vector register expected");
380 as_fatal (_("invalid register type %d"), reg_type
);
385 /* Some well known registers that we refer to directly elsewhere. */
388 /* Instructions take 4 bytes in the object file. */
391 /* Define some common error messages. */
392 #define BAD_SP _("SP not allowed here")
394 static struct hash_control
*aarch64_ops_hsh
;
395 static struct hash_control
*aarch64_cond_hsh
;
396 static struct hash_control
*aarch64_shift_hsh
;
397 static struct hash_control
*aarch64_sys_regs_hsh
;
398 static struct hash_control
*aarch64_pstatefield_hsh
;
399 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
400 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
401 static struct hash_control
*aarch64_sys_regs_at_hsh
;
402 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
403 static struct hash_control
*aarch64_reg_hsh
;
404 static struct hash_control
*aarch64_barrier_opt_hsh
;
405 static struct hash_control
*aarch64_nzcv_hsh
;
406 static struct hash_control
*aarch64_pldop_hsh
;
408 /* Stuff needed to resolve the label ambiguity
417 static symbolS
*last_label_seen
;
419 /* Literal pool structure. Held on a per-section
420 and per-sub-section basis. */
422 #define MAX_LITERAL_POOL_SIZE 1024
423 typedef struct literal_pool
425 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
426 unsigned int next_free_entry
;
432 struct literal_pool
*next
;
435 /* Pointer to a linked list of literal pools. */
436 static literal_pool
*list_of_pools
= NULL
;
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. */
442 const char comment_chars
[] = "";
444 /* This array holds the chars that only start a comment at the beginning of
445 a line. If the line seems to have the form '# 123 filename'
446 .line and .file directives will appear in the pre-processed output. */
447 /* Note that input_file.c hand checks for '#' at the beginning of the
448 first line of the input file. This is because the compiler outputs
449 #NO_APP at the beginning of its output. */
450 /* Also note that comments like this one will always work. */
451 const char line_comment_chars
[] = "#";
453 const char line_separator_chars
[] = ";";
455 /* Chars that can be used to separate mant
456 from exp in floating point numbers. */
457 const char EXP_CHARS
[] = "eE";
459 /* Chars that mean this number is a floating point constant. */
463 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
465 /* Prefix character that indicates the start of an immediate value. */
466 #define is_immediate_prefix(C) ((C) == '#')
468 /* Separator character handling. */
470 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
472 static inline bfd_boolean
473 skip_past_char (char **str
, char c
)
484 #define skip_past_comma(str) skip_past_char (str, ',')
486 /* Arithmetic expressions (possibly involving symbols). */
488 static bfd_boolean in_my_get_expression_p
= FALSE
;
490 /* Third argument to my_get_expression. */
491 #define GE_NO_PREFIX 0
492 #define GE_OPT_PREFIX 1
494 /* Return TRUE if the string pointed by *STR is successfully parsed
495 as an valid expression; *EP will be filled with the information of
496 such an expression. Otherwise return FALSE. */
499 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
504 int prefix_present_p
= 0;
511 if (is_immediate_prefix (**str
))
514 prefix_present_p
= 1;
521 memset (ep
, 0, sizeof (expressionS
));
523 save_in
= input_line_pointer
;
524 input_line_pointer
= *str
;
525 in_my_get_expression_p
= TRUE
;
526 seg
= expression (ep
);
527 in_my_get_expression_p
= FALSE
;
529 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
531 /* We found a bad expression in md_operand(). */
532 *str
= input_line_pointer
;
533 input_line_pointer
= save_in
;
534 if (prefix_present_p
&& ! error_p ())
535 set_fatal_syntax_error (_("bad expression"));
537 set_first_syntax_error (_("bad expression"));
542 if (seg
!= absolute_section
543 && seg
!= text_section
544 && seg
!= data_section
545 && seg
!= bss_section
&& seg
!= undefined_section
)
547 set_syntax_error (_("bad segment"));
548 *str
= input_line_pointer
;
549 input_line_pointer
= save_in
;
556 *str
= input_line_pointer
;
557 input_line_pointer
= save_in
;
561 /* Turn a string in input_line_pointer into a floating point constant
562 of type TYPE, and store the appropriate bytes in *LITP. The number
563 of LITTLENUMS emitted is stored in *SIZEP. An error message is
564 returned, or NULL on OK. */
567 md_atof (int type
, char *litP
, int *sizeP
)
569 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
572 /* We handle all bad expressions here, so that we can report the faulty
573 instruction in the error message. */
575 md_operand (expressionS
* exp
)
577 if (in_my_get_expression_p
)
578 exp
->X_op
= O_illegal
;
581 /* Immediate values. */
583 /* Errors may be set multiple times during parsing or bit encoding
584 (particularly in the Neon bits), but usually the earliest error which is set
585 will be the most meaningful. Avoid overwriting it with later (cascading)
586 errors by calling this function. */
589 first_error (const char *error
)
592 set_syntax_error (error
);
595 /* Similiar to first_error, but this function accepts formatted error
598 first_error_fmt (const char *format
, ...)
603 /* N.B. this single buffer will not cause error messages for different
604 instructions to pollute each other; this is because at the end of
605 processing of each assembly line, error message if any will be
606 collected by as_bad. */
607 static char buffer
[size
];
611 int ret ATTRIBUTE_UNUSED
;
612 va_start (args
, format
);
613 ret
= vsnprintf (buffer
, size
, format
, args
);
614 know (ret
<= size
- 1 && ret
>= 0);
616 set_syntax_error (buffer
);
620 /* Register parsing. */
622 /* Generic register parser which is called by other specialized
624 CCP points to what should be the beginning of a register name.
625 If it is indeed a valid register name, advance CCP over it and
626 return the reg_entry structure; otherwise return NULL.
627 It does not issue diagnostics. */
630 parse_reg (char **ccp
)
636 #ifdef REGISTER_PREFIX
637 if (*start
!= REGISTER_PREFIX
)
643 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
648 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
650 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
659 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
662 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
664 if (reg
->type
== type
)
669 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
670 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
671 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
672 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
673 case REG_TYPE_VN
: /* Vector register. */
674 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
675 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
676 == reg_type_masks
[reg
->type
]);
678 as_fatal ("unhandled type %d", type
);
683 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
684 Return the register number otherwise. *ISREG32 is set to one if the
685 register is 32-bit wide; *ISREGZERO is set to one if the register is
686 of type Z_32 or Z_64.
687 Note that this function does not issue any diagnostics. */
690 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
691 int *isreg32
, int *isregzero
)
694 const reg_entry
*reg
= parse_reg (&str
);
699 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
708 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
713 *isreg32
= reg
->type
== REG_TYPE_R_32
;
720 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
732 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
733 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
734 otherwise return FALSE.
736 Accept only one occurrence of:
737 8b 16b 4h 8h 2s 4s 1d 2d
740 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
744 unsigned element_size
;
745 enum neon_el_type type
;
755 width
= strtoul (ptr
, &ptr
, 10);
756 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
758 first_error_fmt (_("bad size %d in vector width specifier"), width
);
763 switch (TOLOWER (*ptr
))
791 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
793 first_error (_("missing element size"));
796 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
799 ("invalid element size %d and vector size combination %c"),
805 parsed_type
->type
= type
;
806 parsed_type
->width
= width
;
813 /* Parse a single type, e.g. ".8b", leading period included.
814 Only applicable to Vn registers.
816 Return TRUE on success; otherwise return FALSE. */
818 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
824 if (! parse_neon_type_for_operand (vectype
, &str
))
826 first_error (_("vector type expected"));
838 /* Parse a register of the type TYPE.
840 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
841 name or the parsed register is not of TYPE.
843 Otherwise return the register number, and optionally fill in the actual
844 type of the register in *RTYPE when multiple alternatives were given, and
845 return the register shape and element index information in *TYPEINFO.
847 IN_REG_LIST should be set with TRUE if the caller is parsing a register
851 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
852 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
855 const reg_entry
*reg
= parse_reg (&str
);
856 struct neon_type_el atype
;
857 struct neon_type_el parsetype
;
858 bfd_boolean is_typed_vecreg
= FALSE
;
861 atype
.type
= NT_invtype
;
869 set_default_error ();
873 if (! aarch64_check_reg_type (reg
, type
))
875 DEBUG_TRACE ("reg type check failed");
876 set_default_error ();
881 if (type
== REG_TYPE_VN
882 && parse_neon_operand_type (&parsetype
, &str
))
884 /* Register if of the form Vn.[bhsdq]. */
885 is_typed_vecreg
= TRUE
;
887 if (parsetype
.width
== 0)
888 /* Expect index. In the new scheme we cannot have
889 Vn.[bhsdq] represent a scalar. Therefore any
890 Vn.[bhsdq] should have an index following it.
891 Except in reglists ofcourse. */
892 atype
.defined
|= NTA_HASINDEX
;
894 atype
.defined
|= NTA_HASTYPE
;
896 atype
.type
= parsetype
.type
;
897 atype
.width
= parsetype
.width
;
900 if (skip_past_char (&str
, '['))
904 /* Reject Sn[index] syntax. */
905 if (!is_typed_vecreg
)
907 first_error (_("this type of register can't be indexed"));
911 if (in_reg_list
== TRUE
)
913 first_error (_("index not allowed inside register list"));
917 atype
.defined
|= NTA_HASINDEX
;
919 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
921 if (exp
.X_op
!= O_constant
)
923 first_error (_("constant expression required"));
927 if (! skip_past_char (&str
, ']'))
930 atype
.index
= exp
.X_add_number
;
932 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
934 /* Indexed vector register expected. */
935 first_error (_("indexed vector register expected"));
939 /* A vector reg Vn should be typed or indexed. */
940 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
942 first_error (_("invalid use of vector register"));
958 Return the register number on success; return PARSE_FAIL otherwise.
960 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
961 the register (e.g. NEON double or quad reg when either has been requested).
963 If this is a NEON vector register with additional type information, fill
964 in the struct pointed to by VECTYPE (if non-NULL).
966 This parser does not handle register list. */
969 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
970 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
972 struct neon_type_el atype
;
974 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
975 /*in_reg_list= */ FALSE
);
977 if (reg
== PARSE_FAIL
)
988 static inline bfd_boolean
989 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
993 && e1
.defined
== e2
.defined
994 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
997 /* This function parses the NEON register list. On success, it returns
998 the parsed register list information in the following encoded format:
1000 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1001 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1003 The information of the register shape and/or index is returned in
1006 It returns PARSE_FAIL if the register list is invalid.
1008 The list contains one to four registers.
1009 Each register can be one of:
1012 All <T> should be identical.
1013 All <index> should be identical.
1014 There are restrictions on <Vt> numbers which are checked later
1015 (by reg_list_valid_p). */
1018 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1022 struct neon_type_el typeinfo
, typeinfo_first
;
1027 bfd_boolean error
= FALSE
;
1028 bfd_boolean expect_index
= FALSE
;
1032 set_syntax_error (_("expecting {"));
1038 typeinfo_first
.defined
= 0;
1039 typeinfo_first
.type
= NT_invtype
;
1040 typeinfo_first
.width
= -1;
1041 typeinfo_first
.index
= 0;
1050 str
++; /* skip over '-' */
1053 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1054 /*in_reg_list= */ TRUE
);
1055 if (val
== PARSE_FAIL
)
1057 set_first_syntax_error (_("invalid vector register in list"));
1061 /* reject [bhsd]n */
1062 if (typeinfo
.defined
== 0)
1064 set_first_syntax_error (_("invalid scalar register in list"));
1069 if (typeinfo
.defined
& NTA_HASINDEX
)
1070 expect_index
= TRUE
;
1074 if (val
< val_range
)
1076 set_first_syntax_error
1077 (_("invalid range in vector register list"));
1086 typeinfo_first
= typeinfo
;
1087 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1089 set_first_syntax_error
1090 (_("type mismatch in vector register list"));
1095 for (i
= val_range
; i
<= val
; i
++)
1097 ret_val
|= i
<< (5 * nb_regs
);
1102 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1104 skip_whitespace (str
);
1107 set_first_syntax_error (_("end of vector register list not found"));
1112 skip_whitespace (str
);
1116 if (skip_past_char (&str
, '['))
1120 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1121 if (exp
.X_op
!= O_constant
)
1123 set_first_syntax_error (_("constant expression required."));
1126 if (! skip_past_char (&str
, ']'))
1129 typeinfo_first
.index
= exp
.X_add_number
;
1133 set_first_syntax_error (_("expected index"));
1140 set_first_syntax_error (_("too many registers in vector register list"));
1143 else if (nb_regs
== 0)
1145 set_first_syntax_error (_("empty vector register list"));
1151 *vectype
= typeinfo_first
;
1153 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1156 /* Directives: register aliases. */
1159 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1164 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1167 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1170 /* Only warn about a redefinition if it's not defined as the
1172 else if (new->number
!= number
|| new->type
!= type
)
1173 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1178 name
= xstrdup (str
);
1179 new = xmalloc (sizeof (reg_entry
));
1182 new->number
= number
;
1184 new->builtin
= FALSE
;
1186 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1192 /* Look for the .req directive. This is of the form:
1194 new_register_name .req existing_register_name
1196 If we find one, or if it looks sufficiently like one that we want to
1197 handle any error here, return TRUE. Otherwise return FALSE. */
1200 create_register_alias (char *newname
, char *p
)
1202 const reg_entry
*old
;
1203 char *oldname
, *nbuf
;
1206 /* The input scrubber ensures that whitespace after the mnemonic is
1207 collapsed to single spaces. */
1209 if (strncmp (oldname
, " .req ", 6) != 0)
1213 if (*oldname
== '\0')
1216 old
= hash_find (aarch64_reg_hsh
, oldname
);
1219 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1223 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1224 the desired alias name, and p points to its end. If not, then
1225 the desired alias name is in the global original_case_string. */
1226 #ifdef TC_CASE_SENSITIVE
1229 newname
= original_case_string
;
1230 nlen
= strlen (newname
);
1233 nbuf
= alloca (nlen
+ 1);
1234 memcpy (nbuf
, newname
, nlen
);
1237 /* Create aliases under the new name as stated; an all-lowercase
1238 version of the new name; and an all-uppercase version of the new
1240 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1242 for (p
= nbuf
; *p
; p
++)
1245 if (strncmp (nbuf
, newname
, nlen
))
1247 /* If this attempt to create an additional alias fails, do not bother
1248 trying to create the all-lower case alias. We will fail and issue
1249 a second, duplicate error message. This situation arises when the
1250 programmer does something like:
1253 The second .req creates the "Foo" alias but then fails to create
1254 the artificial FOO alias because it has already been created by the
1256 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1260 for (p
= nbuf
; *p
; p
++)
1263 if (strncmp (nbuf
, newname
, nlen
))
1264 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1270 /* Should never be called, as .req goes between the alias and the
1271 register name, not at the beginning of the line. */
1273 s_req (int a ATTRIBUTE_UNUSED
)
1275 as_bad (_("invalid syntax for .req directive"));
1278 /* The .unreq directive deletes an alias which was previously defined
1279 by .req. For example:
1285 s_unreq (int a ATTRIBUTE_UNUSED
)
1290 name
= input_line_pointer
;
1292 while (*input_line_pointer
!= 0
1293 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1294 ++input_line_pointer
;
1296 saved_char
= *input_line_pointer
;
1297 *input_line_pointer
= 0;
1300 as_bad (_("invalid syntax for .unreq directive"));
1303 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1306 as_bad (_("unknown register alias '%s'"), name
);
1307 else if (reg
->builtin
)
1308 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1315 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1316 free ((char *) reg
->name
);
1319 /* Also locate the all upper case and all lower case versions.
1320 Do not complain if we cannot find one or the other as it
1321 was probably deleted above. */
1323 nbuf
= strdup (name
);
1324 for (p
= nbuf
; *p
; p
++)
1326 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1329 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1330 free ((char *) reg
->name
);
1334 for (p
= nbuf
; *p
; p
++)
1336 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1339 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1340 free ((char *) reg
->name
);
1348 *input_line_pointer
= saved_char
;
1349 demand_empty_rest_of_line ();
1352 /* Directives: Instruction set selection. */
1355 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1356 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1357 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1358 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1360 /* Create a new mapping symbol for the transition to STATE. */
1363 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1366 const char *symname
;
1373 type
= BSF_NO_FLAGS
;
1377 type
= BSF_NO_FLAGS
;
1383 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1384 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1386 /* Save the mapping symbols for future reference. Also check that
1387 we do not place two mapping symbols at the same offset within a
1388 frag. We'll handle overlap between frags in
1389 check_mapping_symbols.
1391 If .fill or other data filling directive generates zero sized data,
1392 the mapping symbol for the following code will have the same value
1393 as the one generated for the data filling directive. In this case,
1394 we replace the old symbol with the new one at the same address. */
1397 if (frag
->tc_frag_data
.first_map
!= NULL
)
1399 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1400 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1403 frag
->tc_frag_data
.first_map
= symbolP
;
1405 if (frag
->tc_frag_data
.last_map
!= NULL
)
1407 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1408 S_GET_VALUE (symbolP
));
1409 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1410 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1413 frag
->tc_frag_data
.last_map
= symbolP
;
1416 /* We must sometimes convert a region marked as code to data during
1417 code alignment, if an odd number of bytes have to be padded. The
1418 code mapping symbol is pushed to an aligned address. */
1421 insert_data_mapping_symbol (enum mstate state
,
1422 valueT value
, fragS
* frag
, offsetT bytes
)
1424 /* If there was already a mapping symbol, remove it. */
1425 if (frag
->tc_frag_data
.last_map
!= NULL
1426 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1427 frag
->fr_address
+ value
)
1429 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1433 know (frag
->tc_frag_data
.first_map
== symp
);
1434 frag
->tc_frag_data
.first_map
= NULL
;
1436 frag
->tc_frag_data
.last_map
= NULL
;
1437 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1440 make_mapping_symbol (MAP_DATA
, value
, frag
);
1441 make_mapping_symbol (state
, value
+ bytes
, frag
);
1444 static void mapping_state_2 (enum mstate state
, int max_chars
);
1446 /* Set the mapping state to STATE. Only call this when about to
1447 emit some STATE bytes to the file. */
1450 mapping_state (enum mstate state
)
1452 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1454 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1456 if (mapstate
== state
)
1457 /* The mapping symbol has already been emitted.
1458 There is nothing else to do. */
1460 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
1461 /* This case will be evaluated later in the next else. */
1463 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1465 /* Only add the symbol if the offset is > 0:
1466 if we're at the first frag, check it's size > 0;
1467 if we're not at the first frag, then for sure
1468 the offset is > 0. */
1469 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1470 const int add_symbol
= (frag_now
!= frag_first
)
1471 || (frag_now_fix () > 0);
1474 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1477 mapping_state_2 (state
, 0);
1481 /* Same as mapping_state, but MAX_CHARS bytes have already been
1482 allocated. Put the mapping symbol that far back. */
1485 mapping_state_2 (enum mstate state
, int max_chars
)
1487 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1489 if (!SEG_NORMAL (now_seg
))
1492 if (mapstate
== state
)
1493 /* The mapping symbol has already been emitted.
1494 There is nothing else to do. */
1497 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1498 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1501 #define mapping_state(x) /* nothing */
1502 #define mapping_state_2(x, y) /* nothing */
1505 /* Directives: sectioning and alignment. */
1508 s_bss (int ignore ATTRIBUTE_UNUSED
)
1510 /* We don't support putting frags in the BSS segment, we fake it by
1511 marking in_bss, then looking at s_skip for clues. */
1512 subseg_set (bss_section
, 0);
1513 demand_empty_rest_of_line ();
1514 mapping_state (MAP_DATA
);
1518 s_even (int ignore ATTRIBUTE_UNUSED
)
1520 /* Never make frag if expect extra pass. */
1522 frag_align (1, 0, 0);
1524 record_alignment (now_seg
, 1);
1526 demand_empty_rest_of_line ();
1529 /* Directives: Literal pools. */
1531 static literal_pool
*
1532 find_literal_pool (int size
)
1536 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1538 if (pool
->section
== now_seg
1539 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1546 static literal_pool
*
1547 find_or_make_literal_pool (int size
)
1549 /* Next literal pool ID number. */
1550 static unsigned int latest_pool_num
= 1;
1553 pool
= find_literal_pool (size
);
1557 /* Create a new pool. */
1558 pool
= xmalloc (sizeof (*pool
));
1562 /* Currently we always put the literal pool in the current text
1563 section. If we were generating "small" model code where we
1564 knew that all code and initialised data was within 1MB then
1565 we could output literals to mergeable, read-only data
1568 pool
->next_free_entry
= 0;
1569 pool
->section
= now_seg
;
1570 pool
->sub_section
= now_subseg
;
1572 pool
->next
= list_of_pools
;
1573 pool
->symbol
= NULL
;
1575 /* Add it to the list. */
1576 list_of_pools
= pool
;
1579 /* New pools, and emptied pools, will have a NULL symbol. */
1580 if (pool
->symbol
== NULL
)
1582 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1583 (valueT
) 0, &zero_address_frag
);
1584 pool
->id
= latest_pool_num
++;
1591 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1592 Return TRUE on success, otherwise return FALSE. */
1594 add_to_lit_pool (expressionS
*exp
, int size
)
1599 pool
= find_or_make_literal_pool (size
);
1601 /* Check if this literal value is already in the pool. */
1602 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1604 if ((pool
->literals
[entry
].X_op
== exp
->X_op
)
1605 && (exp
->X_op
== O_constant
)
1606 && (pool
->literals
[entry
].X_add_number
== exp
->X_add_number
)
1607 && (pool
->literals
[entry
].X_unsigned
== exp
->X_unsigned
))
1610 if ((pool
->literals
[entry
].X_op
== exp
->X_op
)
1611 && (exp
->X_op
== O_symbol
)
1612 && (pool
->literals
[entry
].X_add_number
== exp
->X_add_number
)
1613 && (pool
->literals
[entry
].X_add_symbol
== exp
->X_add_symbol
)
1614 && (pool
->literals
[entry
].X_op_symbol
== exp
->X_op_symbol
))
1618 /* Do we need to create a new entry? */
1619 if (entry
== pool
->next_free_entry
)
1621 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1623 set_syntax_error (_("literal pool overflow"));
1627 pool
->literals
[entry
] = *exp
;
1628 pool
->next_free_entry
+= 1;
1631 exp
->X_op
= O_symbol
;
1632 exp
->X_add_number
= ((int) entry
) * size
;
1633 exp
->X_add_symbol
= pool
->symbol
;
1638 /* Can't use symbol_new here, so have to create a symbol and then at
1639 a later date assign it a value. Thats what these functions do. */
1642 symbol_locate (symbolS
* symbolP
,
1643 const char *name
,/* It is copied, the caller can modify. */
1644 segT segment
, /* Segment identifier (SEG_<something>). */
1645 valueT valu
, /* Symbol value. */
1646 fragS
* frag
) /* Associated fragment. */
1648 unsigned int name_length
;
1649 char *preserved_copy_of_name
;
1651 name_length
= strlen (name
) + 1; /* +1 for \0. */
1652 obstack_grow (¬es
, name
, name_length
);
1653 preserved_copy_of_name
= obstack_finish (¬es
);
1655 #ifdef tc_canonicalize_symbol_name
1656 preserved_copy_of_name
=
1657 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1660 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1662 S_SET_SEGMENT (symbolP
, segment
);
1663 S_SET_VALUE (symbolP
, valu
);
1664 symbol_clear_list_pointers (symbolP
);
1666 symbol_set_frag (symbolP
, frag
);
1668 /* Link to end of symbol chain. */
1670 extern int symbol_table_frozen
;
1672 if (symbol_table_frozen
)
1676 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1678 obj_symbol_new_hook (symbolP
);
1680 #ifdef tc_symbol_new_hook
1681 tc_symbol_new_hook (symbolP
);
1685 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1686 #endif /* DEBUG_SYMS */
1691 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1698 for (align
= 2; align
<= 4; align
++)
1700 int size
= 1 << align
;
1702 pool
= find_literal_pool (size
);
1703 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1706 mapping_state (MAP_DATA
);
1708 /* Align pool as you have word accesses.
1709 Only make a frag if we have to. */
1711 frag_align (align
, 0, 0);
1713 record_alignment (now_seg
, align
);
1715 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1717 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1718 (valueT
) frag_now_fix (), frag_now
);
1719 symbol_table_insert (pool
->symbol
);
1721 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1722 /* First output the expression in the instruction to the pool. */
1723 emit_expr (&(pool
->literals
[entry
]), size
); /* .word|.xword */
1725 /* Mark the pool as empty. */
1726 pool
->next_free_entry
= 0;
1727 pool
->symbol
= NULL
;
1732 /* Forward declarations for functions below, in the MD interface
1734 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1735 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1737 /* Directives: Data. */
1738 /* N.B. the support for relocation suffix in this directive needs to be
1739 implemented properly. */
1742 s_aarch64_elf_cons (int nbytes
)
1746 #ifdef md_flush_pending_output
1747 md_flush_pending_output ();
1750 if (is_it_end_of_statement ())
1752 demand_empty_rest_of_line ();
1756 #ifdef md_cons_align
1757 md_cons_align (nbytes
);
1760 mapping_state (MAP_DATA
);
1763 struct reloc_table_entry
*reloc
;
1767 if (exp
.X_op
!= O_symbol
)
1768 emit_expr (&exp
, (unsigned int) nbytes
);
1771 skip_past_char (&input_line_pointer
, '#');
1772 if (skip_past_char (&input_line_pointer
, ':'))
1774 reloc
= find_reloc_table_entry (&input_line_pointer
);
1776 as_bad (_("unrecognized relocation suffix"));
1778 as_bad (_("unimplemented relocation suffix"));
1779 ignore_rest_of_line ();
1783 emit_expr (&exp
, (unsigned int) nbytes
);
1786 while (*input_line_pointer
++ == ',');
1788 /* Put terminator back into stream. */
1789 input_line_pointer
--;
1790 demand_empty_rest_of_line ();
1793 #endif /* OBJ_ELF */
1795 /* Output a 32-bit word, but mark as an instruction. */
1798 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1802 #ifdef md_flush_pending_output
1803 md_flush_pending_output ();
1806 if (is_it_end_of_statement ())
1808 demand_empty_rest_of_line ();
1813 frag_align_code (2, 0);
1815 mapping_state (MAP_INSN
);
1821 if (exp
.X_op
!= O_constant
)
1823 as_bad (_("constant expression required"));
1824 ignore_rest_of_line ();
1828 if (target_big_endian
)
1830 unsigned int val
= exp
.X_add_number
;
1831 exp
.X_add_number
= SWAP_32 (val
);
1833 emit_expr (&exp
, 4);
1835 while (*input_line_pointer
++ == ',');
1837 /* Put terminator back into stream. */
1838 input_line_pointer
--;
1839 demand_empty_rest_of_line ();
1843 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1846 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1850 /* Since we're just labelling the code, there's no need to define a
1853 /* Make sure there is enough room in this frag for the following
1854 blr. This trick only works if the blr follows immediately after
1855 the .tlsdesc directive. */
1857 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1858 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1860 demand_empty_rest_of_line ();
1862 #endif /* OBJ_ELF */
1864 static void s_aarch64_arch (int);
1865 static void s_aarch64_cpu (int);
1867 /* This table describes all the machine specific pseudo-ops the assembler
1868 has to support. The fields are:
1869 pseudo-op name without dot
1870 function to call to execute this pseudo-op
1871 Integer arg to pass to the function. */
1873 const pseudo_typeS md_pseudo_table
[] = {
1874 /* Never called because '.req' does not start a line. */
1876 {"unreq", s_unreq
, 0},
1878 {"even", s_even
, 0},
1879 {"ltorg", s_ltorg
, 0},
1880 {"pool", s_ltorg
, 0},
1881 {"cpu", s_aarch64_cpu
, 0},
1882 {"arch", s_aarch64_arch
, 0},
1883 {"inst", s_aarch64_inst
, 0},
1885 {"tlsdesccall", s_tlsdesccall
, 0},
1886 {"word", s_aarch64_elf_cons
, 4},
1887 {"long", s_aarch64_elf_cons
, 4},
1888 {"xword", s_aarch64_elf_cons
, 8},
1889 {"dword", s_aarch64_elf_cons
, 8},
1895 /* Check whether STR points to a register name followed by a comma or the
1896 end of line; REG_TYPE indicates which register types are checked
1897 against. Return TRUE if STR is such a register name; otherwise return
1898 FALSE. The function does not intend to produce any diagnostics, but since
1899 the register parser aarch64_reg_parse, which is called by this function,
1900 does produce diagnostics, we call clear_error to clear any diagnostics
1901 that may be generated by aarch64_reg_parse.
1902 Also, the function returns FALSE directly if there is any user error
1903 present at the function entry. This prevents the existing diagnostics
1904 state from being spoiled.
1905 The function currently serves parse_constant_immediate and
1906 parse_big_immediate only. */
1908 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1912 /* Prevent the diagnostics state from being spoiled. */
1916 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1918 /* Clear the parsing error that may be set by the reg parser. */
1921 if (reg
== PARSE_FAIL
)
1924 skip_whitespace (str
);
1925 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1931 /* Parser functions used exclusively in instruction operands. */
1933 /* Parse an immediate expression which may not be constant.
1935 To prevent the expression parser from pushing a register name
1936 into the symbol table as an undefined symbol, firstly a check is
1937 done to find out whether STR is a valid register name followed
1938 by a comma or the end of line. Return FALSE if STR is such a
1942 parse_immediate_expression (char **str
, expressionS
*exp
)
1944 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
1946 set_recoverable_error (_("immediate operand required"));
1950 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
1952 if (exp
->X_op
== O_absent
)
1954 set_fatal_syntax_error (_("missing immediate expression"));
1961 /* Constant immediate-value read function for use in insn parsing.
1962 STR points to the beginning of the immediate (with the optional
1963 leading #); *VAL receives the value.
1965 Return TRUE on success; otherwise return FALSE. */
1968 parse_constant_immediate (char **str
, int64_t * val
)
1972 if (! parse_immediate_expression (str
, &exp
))
1975 if (exp
.X_op
!= O_constant
)
1977 set_syntax_error (_("constant expression required"));
1981 *val
= exp
.X_add_number
;
1986 encode_imm_float_bits (uint32_t imm
)
1988 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
1989 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
1992 /* Return TRUE if the single-precision floating-point value encoded in IMM
1993 can be expressed in the AArch64 8-bit signed floating-point format with
1994 3-bit exponent and normalized 4 bits of precision; in other words, the
1995 floating-point value must be expressable as
1996 (+/-) n / 16 * power (2, r)
1997 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2000 aarch64_imm_float_p (uint32_t imm
)
2002 /* If a single-precision floating-point value has the following bit
2003 pattern, it can be expressed in the AArch64 8-bit floating-point
2006 3 32222222 2221111111111
2007 1 09876543 21098765432109876543210
2008 n Eeeeeexx xxxx0000000000000000000
2010 where n, e and each x are either 0 or 1 independently, with
2015 /* Prepare the pattern for 'Eeeeee'. */
2016 if (((imm
>> 30) & 0x1) == 0)
2017 pattern
= 0x3e000000;
2019 pattern
= 0x40000000;
2021 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2022 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2025 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2027 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2028 8-bit signed floating-point format with 3-bit exponent and normalized 4
2029 bits of precision (i.e. can be used in an FMOV instruction); return the
2030 equivalent single-precision encoding in *FPWORD.
2032 Otherwise return FALSE. */
2035 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2037 /* If a double-precision floating-point value has the following bit
2038 pattern, it can be expressed in the AArch64 8-bit floating-point
2041 6 66655555555 554444444...21111111111
2042 3 21098765432 109876543...098765432109876543210
2043 n Eeeeeeeeexx xxxx00000...000000000000000000000
2045 where n, e and each x are either 0 or 1 independently, with
2049 uint32_t high32
= imm
>> 32;
2051 /* Lower 32 bits need to be 0s. */
2052 if ((imm
& 0xffffffff) != 0)
2055 /* Prepare the pattern for 'Eeeeeeeee'. */
2056 if (((high32
>> 30) & 0x1) == 0)
2057 pattern
= 0x3fc00000;
2059 pattern
= 0x40000000;
2061 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2062 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2064 /* Convert to the single-precision encoding.
2066 n Eeeeeeeeexx xxxx00000...000000000000000000000
2068 n Eeeeeexx xxxx0000000000000000000. */
2069 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2070 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2077 /* Parse a floating-point immediate. Return TRUE on success and return the
2078 value in *IMMED in the format of IEEE754 single-precision encoding.
2079 *CCP points to the start of the string; DP_P is TRUE when the immediate
2080 is expected to be in double-precision (N.B. this only matters when
2081 hexadecimal representation is involved).
2083 N.B. 0.0 is accepted by this function. */
2086 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2090 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2091 int found_fpchar
= 0;
2093 unsigned fpword
= 0;
2094 bfd_boolean hex_p
= FALSE
;
2096 skip_past_char (&str
, '#');
2099 skip_whitespace (fpnum
);
2101 if (strncmp (fpnum
, "0x", 2) == 0)
2103 /* Support the hexadecimal representation of the IEEE754 encoding.
2104 Double-precision is expected when DP_P is TRUE, otherwise the
2105 representation should be in single-precision. */
2106 if (! parse_constant_immediate (&str
, &val
))
2111 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2114 else if ((uint64_t) val
> 0xffffffff)
2123 /* We must not accidentally parse an integer as a floating-point number.
2124 Make sure that the value we parse is not an integer by checking for
2125 special characters '.' or 'e'. */
2126 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2127 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2141 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2144 /* Our FP word must be 32 bits (single-precision FP). */
2145 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2147 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2152 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2160 set_fatal_syntax_error (_("invalid floating-point constant"));
2164 /* Less-generic immediate-value read function with the possibility of loading
2165 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2168 To prevent the expression parser from pushing a register name into the
2169 symbol table as an undefined symbol, a check is firstly done to find
2170 out whether STR is a valid register name followed by a comma or the end
2171 of line. Return FALSE if STR is such a register. */
2174 parse_big_immediate (char **str
, int64_t *imm
)
2178 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2180 set_syntax_error (_("immediate operand required"));
2184 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2186 if (inst
.reloc
.exp
.X_op
== O_constant
)
2187 *imm
= inst
.reloc
.exp
.X_add_number
;
2194 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2195 if NEED_LIBOPCODES is non-zero, the fixup will need
2196 assistance from the libopcodes. */
2199 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2200 const aarch64_opnd_info
*operand
,
2201 int need_libopcodes_p
)
2203 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2204 reloc
->opnd
= operand
->type
;
2205 if (need_libopcodes_p
)
2206 reloc
->need_libopcodes_p
= 1;
2209 /* Return TRUE if the instruction needs to be fixed up later internally by
2210 the GAS; otherwise return FALSE. */
2212 static inline bfd_boolean
2213 aarch64_gas_internal_fixup_p (void)
2215 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2218 /* Assign the immediate value to the relavant field in *OPERAND if
2219 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2220 needs an internal fixup in a later stage.
2221 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2222 IMM.VALUE that may get assigned with the constant. */
2224 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2225 aarch64_opnd_info
*operand
,
2227 int need_libopcodes_p
,
2230 if (reloc
->exp
.X_op
== O_constant
)
2233 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2235 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2236 reloc
->type
= BFD_RELOC_UNUSED
;
2240 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2241 /* Tell libopcodes to ignore this operand or not. This is helpful
2242 when one of the operands needs to be fixed up later but we need
2243 libopcodes to check the other operands. */
2244 operand
->skip
= skip_p
;
2248 /* Relocation modifiers. Each entry in the table contains the textual
2249 name for the relocation which may be placed before a symbol used as
2250 a load/store offset, or add immediate. It must be surrounded by a
2251 leading and trailing colon, for example:
2253 ldr x0, [x1, #:rello:varsym]
2254 add x0, x1, #:rello:varsym */
2256 struct reloc_table_entry
2260 bfd_reloc_code_real_type adrp_type
;
2261 bfd_reloc_code_real_type movw_type
;
2262 bfd_reloc_code_real_type add_type
;
2263 bfd_reloc_code_real_type ldst_type
;
2266 static struct reloc_table_entry reloc_table
[] = {
2267 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2271 BFD_RELOC_AARCH64_ADD_LO12
,
2272 BFD_RELOC_AARCH64_LDST_LO12
},
2274 /* Higher 21 bits of pc-relative page offset: ADRP */
2276 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2281 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2283 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2288 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2291 BFD_RELOC_AARCH64_MOVW_G0
,
2295 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2298 BFD_RELOC_AARCH64_MOVW_G0_S
,
2302 /* Less significant bits 0-15 of address/value: MOVK, no check */
2305 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2309 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2312 BFD_RELOC_AARCH64_MOVW_G1
,
2316 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2319 BFD_RELOC_AARCH64_MOVW_G1_S
,
2323 /* Less significant bits 16-31 of address/value: MOVK, no check */
2326 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2330 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2333 BFD_RELOC_AARCH64_MOVW_G2
,
2337 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2340 BFD_RELOC_AARCH64_MOVW_G2_S
,
2344 /* Less significant bits 32-47 of address/value: MOVK, no check */
2347 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2351 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2354 BFD_RELOC_AARCH64_MOVW_G3
,
2357 /* Get to the GOT entry for a symbol. */
2362 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2363 /* Get to the page containing GOT entry for a symbol. */
2365 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2369 /* 12 bit offset into the page containing GOT entry for that symbol. */
2374 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
},
2376 /* Get to the page containing GOT TLS entry for a symbol */
2378 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2383 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2387 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2390 /* Get to the page containing GOT TLS entry for a symbol */
2392 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
,
2397 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2401 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2402 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
},
2404 /* Get to the page containing GOT TLS entry for a symbol */
2406 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2411 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2412 {"gottprel_lo12", 0,
2416 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
},
2418 /* Get tp offset for a symbol. */
2422 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2425 /* Get tp offset for a symbol. */
2429 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2432 /* Get tp offset for a symbol. */
2436 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2439 /* Get tp offset for a symbol. */
2440 {"tprel_lo12_nc", 0,
2443 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2446 /* Most significant bits 32-47 of address/value: MOVZ. */
2449 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2453 /* Most significant bits 16-31 of address/value: MOVZ. */
2456 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2460 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2463 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2467 /* Most significant bits 0-15 of address/value: MOVZ. */
2470 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2474 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2477 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2482 /* Given the address of a pointer pointing to the textual name of a
2483 relocation as may appear in assembler source, attempt to find its
2484 details in reloc_table. The pointer will be updated to the character
2485 after the trailing colon. On failure, NULL will be returned;
2486 otherwise return the reloc_table_entry. */
2488 static struct reloc_table_entry
*
2489 find_reloc_table_entry (char **str
)
2492 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2494 int length
= strlen (reloc_table
[i
].name
);
2496 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2497 && (*str
)[length
] == ':')
2499 *str
+= (length
+ 1);
2500 return &reloc_table
[i
];
2507 /* Mode argument to parse_shift and parser_shifter_operand. */
2508 enum parse_shift_mode
2510 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2512 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2514 SHIFTED_LSL
, /* bare "lsl #n" */
2515 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2516 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2519 /* Parse a <shift> operator on an AArch64 data processing instruction.
2520 Return TRUE on success; otherwise return FALSE. */
2522 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2524 const struct aarch64_name_value_pair
*shift_op
;
2525 enum aarch64_modifier_kind kind
;
2531 for (p
= *str
; ISALPHA (*p
); p
++)
2536 set_syntax_error (_("shift expression expected"));
2540 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2542 if (shift_op
== NULL
)
2544 set_syntax_error (_("shift operator expected"));
2548 kind
= aarch64_get_operand_modifier (shift_op
);
2550 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2552 set_syntax_error (_("invalid use of 'MSL'"));
2558 case SHIFTED_LOGIC_IMM
:
2559 if (aarch64_extend_operator_p (kind
) == TRUE
)
2561 set_syntax_error (_("extending shift is not permitted"));
2566 case SHIFTED_ARITH_IMM
:
2567 if (kind
== AARCH64_MOD_ROR
)
2569 set_syntax_error (_("'ROR' shift is not permitted"));
2575 if (kind
!= AARCH64_MOD_LSL
)
2577 set_syntax_error (_("only 'LSL' shift is permitted"));
2582 case SHIFTED_REG_OFFSET
:
2583 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2584 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2586 set_fatal_syntax_error
2587 (_("invalid shift for the register offset addressing mode"));
2592 case SHIFTED_LSL_MSL
:
2593 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2595 set_syntax_error (_("invalid shift operator"));
2604 /* Whitespace can appear here if the next thing is a bare digit. */
2605 skip_whitespace (p
);
2607 /* Parse shift amount. */
2609 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2610 exp
.X_op
= O_absent
;
2613 if (is_immediate_prefix (*p
))
2618 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2620 if (exp
.X_op
== O_absent
)
2622 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2624 set_syntax_error (_("missing shift amount"));
2627 operand
->shifter
.amount
= 0;
2629 else if (exp
.X_op
!= O_constant
)
2631 set_syntax_error (_("constant shift amount required"));
2634 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2636 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2641 operand
->shifter
.amount
= exp
.X_add_number
;
2642 operand
->shifter
.amount_present
= 1;
2645 operand
->shifter
.operator_present
= 1;
2646 operand
->shifter
.kind
= kind
;
2652 /* Parse a <shifter_operand> for a data processing instruction:
2655 #<immediate>, LSL #imm
2657 Validation of immediate operands is deferred to md_apply_fix.
2659 Return TRUE on success; otherwise return FALSE. */
2662 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2663 enum parse_shift_mode mode
)
2667 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2672 /* Accept an immediate expression. */
2673 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2676 /* Accept optional LSL for arithmetic immediate values. */
2677 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2678 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2681 /* Not accept any shifter for logical immediate values. */
2682 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2683 && parse_shift (&p
, operand
, mode
))
2685 set_syntax_error (_("unexpected shift operator"));
2693 /* Parse a <shifter_operand> for a data processing instruction:
2698 #<immediate>, LSL #imm
2700 where <shift> is handled by parse_shift above, and the last two
2701 cases are handled by the function above.
2703 Validation of immediate operands is deferred to md_apply_fix.
2705 Return TRUE on success; otherwise return FALSE. */
2708 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2709 enum parse_shift_mode mode
)
2712 int isreg32
, isregzero
;
2713 enum aarch64_operand_class opd_class
2714 = aarch64_get_operand_class (operand
->type
);
2717 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2719 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2721 set_syntax_error (_("unexpected register in the immediate operand"));
2725 if (!isregzero
&& reg
== REG_SP
)
2727 set_syntax_error (BAD_SP
);
2731 operand
->reg
.regno
= reg
;
2732 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2734 /* Accept optional shift operation on register. */
2735 if (! skip_past_comma (str
))
2738 if (! parse_shift (str
, operand
, mode
))
2743 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2746 (_("integer register expected in the extended/shifted operand "
2751 /* We have a shifted immediate variable. */
2752 return parse_shifter_operand_imm (str
, operand
, mode
);
2755 /* Return TRUE on success; return FALSE otherwise. */
2758 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
2759 enum parse_shift_mode mode
)
2763 /* Determine if we have the sequence of characters #: or just :
2764 coming next. If we do, then we check for a :rello: relocation
2765 modifier. If we don't, punt the whole lot to
2766 parse_shifter_operand. */
2768 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
2770 struct reloc_table_entry
*entry
;
2778 /* Try to parse a relocation. Anything else is an error. */
2779 if (!(entry
= find_reloc_table_entry (str
)))
2781 set_syntax_error (_("unknown relocation modifier"));
2785 if (entry
->add_type
== 0)
2788 (_("this relocation modifier is not allowed on this instruction"));
2792 /* Save str before we decompose it. */
2795 /* Next, we parse the expression. */
2796 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
2799 /* Record the relocation type (use the ADD variant here). */
2800 inst
.reloc
.type
= entry
->add_type
;
2801 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2803 /* If str is empty, we've reached the end, stop here. */
2807 /* Otherwise, we have a shifted reloc modifier, so rewind to
2808 recover the variable name and continue parsing for the shifter. */
2810 return parse_shifter_operand_imm (str
, operand
, mode
);
2813 return parse_shifter_operand (str
, operand
, mode
);
2816 /* Parse all forms of an address expression. Information is written
2817 to *OPERAND and/or inst.reloc.
2819 The A64 instruction set has the following addressing modes:
2822 [base] // in SIMD ld/st structure
2823 [base{,#0}] // in ld/st exclusive
2825 [base,Xm{,LSL #imm}]
2826 [base,Xm,SXTX {#imm}]
2827 [base,Wm,(S|U)XTW {#imm}]
2832 [base],Xm // in SIMD ld/st structure
2833 PC-relative (literal)
2837 (As a convenience, the notation "=immediate" is permitted in conjunction
2838 with the pc-relative literal load instructions to automatically place an
2839 immediate value or symbolic address in a nearby literal pool and generate
2840 a hidden label which references it.)
2842 Upon a successful parsing, the address structure in *OPERAND will be
2843 filled in the following way:
2845 .base_regno = <base>
2846 .offset.is_reg // 1 if the offset is a register
2848 .offset.regno = <Rm>
2850 For different addressing modes defined in the A64 ISA:
2853 .pcrel=0; .preind=1; .postind=0; .writeback=0
2855 .pcrel=0; .preind=1; .postind=0; .writeback=1
2857 .pcrel=0; .preind=0; .postind=1; .writeback=1
2858 PC-relative (literal)
2859 .pcrel=1; .preind=1; .postind=0; .writeback=0
2861 The shift/extension information, if any, will be stored in .shifter.
2863 It is the caller's responsibility to check for addressing modes not
2864 supported by the instruction, and to set inst.reloc.type. */
2867 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
2868 int accept_reg_post_index
)
2872 int isreg32
, isregzero
;
2873 expressionS
*exp
= &inst
.reloc
.exp
;
2875 if (! skip_past_char (&p
, '['))
2877 /* =immediate or label. */
2878 operand
->addr
.pcrel
= 1;
2879 operand
->addr
.preind
= 1;
2881 /* #:<reloc_op>:<symbol> */
2882 skip_past_char (&p
, '#');
2883 if (reloc
&& skip_past_char (&p
, ':'))
2885 struct reloc_table_entry
*entry
;
2887 /* Try to parse a relocation modifier. Anything else is
2889 entry
= find_reloc_table_entry (&p
);
2892 set_syntax_error (_("unknown relocation modifier"));
2896 if (entry
->ldst_type
== 0)
2899 (_("this relocation modifier is not allowed on this "
2905 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
2907 set_syntax_error (_("invalid relocation expression"));
2911 /* #:<reloc_op>:<expr> */
2912 /* Record the load/store relocation type. */
2913 inst
.reloc
.type
= entry
->ldst_type
;
2914 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2919 if (skip_past_char (&p
, '='))
2920 /* =immediate; need to generate the literal in the literal pool. */
2921 inst
.gen_lit_pool
= 1;
2923 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
2925 set_syntax_error (_("invalid address"));
2936 /* Accept SP and reject ZR */
2937 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
2938 if (reg
== PARSE_FAIL
|| isreg32
)
2940 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
2943 operand
->addr
.base_regno
= reg
;
2946 if (skip_past_comma (&p
))
2949 operand
->addr
.preind
= 1;
2951 /* Reject SP and accept ZR */
2952 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
2953 if (reg
!= PARSE_FAIL
)
2956 operand
->addr
.offset
.regno
= reg
;
2957 operand
->addr
.offset
.is_reg
= 1;
2958 /* Shifted index. */
2959 if (skip_past_comma (&p
))
2962 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
2963 /* Use the diagnostics set in parse_shift, so not set new
2964 error message here. */
2968 [base,Xm{,LSL #imm}]
2969 [base,Xm,SXTX {#imm}]
2970 [base,Wm,(S|U)XTW {#imm}] */
2971 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
2972 || operand
->shifter
.kind
== AARCH64_MOD_LSL
2973 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
2977 set_syntax_error (_("invalid use of 32-bit register offset"));
2983 set_syntax_error (_("invalid use of 64-bit register offset"));
2989 /* [Xn,#:<reloc_op>:<symbol> */
2990 skip_past_char (&p
, '#');
2991 if (reloc
&& skip_past_char (&p
, ':'))
2993 struct reloc_table_entry
*entry
;
2995 /* Try to parse a relocation modifier. Anything else is
2997 if (!(entry
= find_reloc_table_entry (&p
)))
2999 set_syntax_error (_("unknown relocation modifier"));
3003 if (entry
->ldst_type
== 0)
3006 (_("this relocation modifier is not allowed on this "
3011 /* [Xn,#:<reloc_op>: */
3012 /* We now have the group relocation table entry corresponding to
3013 the name in the assembler source. Next, we parse the
3015 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3017 set_syntax_error (_("invalid relocation expression"));
3021 /* [Xn,#:<reloc_op>:<expr> */
3022 /* Record the load/store relocation type. */
3023 inst
.reloc
.type
= entry
->ldst_type
;
3024 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3026 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3028 set_syntax_error (_("invalid expression in the address"));
3035 if (! skip_past_char (&p
, ']'))
3037 set_syntax_error (_("']' expected"));
3041 if (skip_past_char (&p
, '!'))
3043 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3045 set_syntax_error (_("register offset not allowed in pre-indexed "
3046 "addressing mode"));
3050 operand
->addr
.writeback
= 1;
3052 else if (skip_past_comma (&p
))
3055 operand
->addr
.postind
= 1;
3056 operand
->addr
.writeback
= 1;
3058 if (operand
->addr
.preind
)
3060 set_syntax_error (_("cannot combine pre- and post-indexing"));
3064 if (accept_reg_post_index
3065 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3066 &isregzero
)) != PARSE_FAIL
)
3071 set_syntax_error (_("invalid 32-bit register offset"));
3074 operand
->addr
.offset
.regno
= reg
;
3075 operand
->addr
.offset
.is_reg
= 1;
3077 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3080 set_syntax_error (_("invalid expression in the address"));
3085 /* If at this point neither .preind nor .postind is set, we have a
3086 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3087 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3089 if (operand
->addr
.writeback
)
3092 set_syntax_error (_("missing offset in the pre-indexed address"));
3095 operand
->addr
.preind
= 1;
3096 inst
.reloc
.exp
.X_op
= O_constant
;
3097 inst
.reloc
.exp
.X_add_number
= 0;
3104 /* Return TRUE on success; otherwise return FALSE. */
3106 parse_address (char **str
, aarch64_opnd_info
*operand
,
3107 int accept_reg_post_index
)
3109 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3112 /* Return TRUE on success; otherwise return FALSE. */
3114 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3116 return parse_address_main (str
, operand
, 1, 0);
3119 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3120 Return TRUE on success; otherwise return FALSE. */
3122 parse_half (char **str
, int *internal_fixup_p
)
3128 skip_past_char (&p
, '#');
3130 gas_assert (internal_fixup_p
);
3131 *internal_fixup_p
= 0;
3135 struct reloc_table_entry
*entry
;
3137 /* Try to parse a relocation. Anything else is an error. */
3139 if (!(entry
= find_reloc_table_entry (&p
)))
3141 set_syntax_error (_("unknown relocation modifier"));
3145 if (entry
->movw_type
== 0)
3148 (_("this relocation modifier is not allowed on this instruction"));
3152 inst
.reloc
.type
= entry
->movw_type
;
3155 *internal_fixup_p
= 1;
3157 /* Avoid parsing a register as a general symbol. */
3159 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3163 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3170 /* Parse an operand for an ADRP instruction:
3172 Return TRUE on success; otherwise return FALSE. */
3175 parse_adrp (char **str
)
3182 struct reloc_table_entry
*entry
;
3184 /* Try to parse a relocation. Anything else is an error. */
3186 if (!(entry
= find_reloc_table_entry (&p
)))
3188 set_syntax_error (_("unknown relocation modifier"));
3192 if (entry
->adrp_type
== 0)
3195 (_("this relocation modifier is not allowed on this instruction"));
3199 inst
.reloc
.type
= entry
->adrp_type
;
3202 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3204 inst
.reloc
.pc_rel
= 1;
3206 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3213 /* Miscellaneous. */
3215 /* Parse an option for a preload instruction. Returns the encoding for the
3216 option, or PARSE_FAIL. */
3219 parse_pldop (char **str
)
3222 const struct aarch64_name_value_pair
*o
;
3225 while (ISALNUM (*q
))
3228 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3236 /* Parse an option for a barrier instruction. Returns the encoding for the
3237 option, or PARSE_FAIL. */
3240 parse_barrier (char **str
)
3243 const asm_barrier_opt
*o
;
3246 while (ISALPHA (*q
))
3249 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3257 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3258 Returns the encoding for the option, or PARSE_FAIL.
3260 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3261 implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
3264 parse_sys_reg (char **str
, struct hash_control
*sys_regs
, int imple_defined_p
)
3268 const struct aarch64_name_value_pair
*o
;
3272 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3274 *p
++ = TOLOWER (*q
);
3276 /* Assert that BUF be large enough. */
3277 gas_assert (p
- buf
== q
- *str
);
3279 o
= hash_find (sys_regs
, buf
);
3282 if (!imple_defined_p
)
3286 /* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
3288 unsigned int op0
, op1
, cn
, cm
, op2
;
3289 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
) != 5)
3291 /* The architecture specifies the encoding space for implementation
3292 defined registers as:
3294 11 xxx 1x11 xxxx xxx
3295 For convenience GAS accepts a wider encoding space, as follows:
3297 11 xxx xxxx xxxx xxx */
3298 if (op0
!= 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3300 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3310 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3311 for the option, or NULL. */
3313 static const aarch64_sys_ins_reg
*
3314 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3318 const aarch64_sys_ins_reg
*o
;
3321 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3323 *p
++ = TOLOWER (*q
);
3326 o
= hash_find (sys_ins_regs
, buf
);
3334 #define po_char_or_fail(chr) do { \
3335 if (! skip_past_char (&str, chr)) \
3339 #define po_reg_or_fail(regtype) do { \
3340 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3341 if (val == PARSE_FAIL) \
3343 set_default_error (); \
3348 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3349 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3350 &isreg32, &isregzero); \
3351 if (val == PARSE_FAIL) \
3353 set_default_error (); \
3356 info->reg.regno = val; \
3358 info->qualifier = AARCH64_OPND_QLF_W; \
3360 info->qualifier = AARCH64_OPND_QLF_X; \
3363 #define po_imm_nc_or_fail() do { \
3364 if (! parse_constant_immediate (&str, &val)) \
3368 #define po_imm_or_fail(min, max) do { \
3369 if (! parse_constant_immediate (&str, &val)) \
3371 if (val < min || val > max) \
3373 set_fatal_syntax_error (_("immediate value out of range "\
3374 #min " to "#max)); \
3379 #define po_misc_or_fail(expr) do { \
3384 /* encode the 12-bit imm field of Add/sub immediate */
3385 static inline uint32_t
3386 encode_addsub_imm (uint32_t imm
)
3391 /* encode the shift amount field of Add/sub immediate */
3392 static inline uint32_t
3393 encode_addsub_imm_shift_amount (uint32_t cnt
)
3399 /* encode the imm field of Adr instruction */
3400 static inline uint32_t
3401 encode_adr_imm (uint32_t imm
)
3403 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3404 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3407 /* encode the immediate field of Move wide immediate */
3408 static inline uint32_t
3409 encode_movw_imm (uint32_t imm
)
3414 /* encode the 26-bit offset of unconditional branch */
3415 static inline uint32_t
3416 encode_branch_ofs_26 (uint32_t ofs
)
3418 return ofs
& ((1 << 26) - 1);
3421 /* encode the 19-bit offset of conditional branch and compare & branch */
3422 static inline uint32_t
3423 encode_cond_branch_ofs_19 (uint32_t ofs
)
3425 return (ofs
& ((1 << 19) - 1)) << 5;
3428 /* encode the 19-bit offset of ld literal */
3429 static inline uint32_t
3430 encode_ld_lit_ofs_19 (uint32_t ofs
)
3432 return (ofs
& ((1 << 19) - 1)) << 5;
3435 /* Encode the 14-bit offset of test & branch. */
3436 static inline uint32_t
3437 encode_tst_branch_ofs_14 (uint32_t ofs
)
3439 return (ofs
& ((1 << 14) - 1)) << 5;
3442 /* Encode the 16-bit imm field of svc/hvc/smc. */
3443 static inline uint32_t
3444 encode_svc_imm (uint32_t imm
)
3449 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3450 static inline uint32_t
3451 reencode_addsub_switch_add_sub (uint32_t opcode
)
3453 return opcode
^ (1 << 30);
3456 static inline uint32_t
3457 reencode_movzn_to_movz (uint32_t opcode
)
3459 return opcode
| (1 << 30);
3462 static inline uint32_t
3463 reencode_movzn_to_movn (uint32_t opcode
)
3465 return opcode
& ~(1 << 30);
3468 /* Overall per-instruction processing. */
3470 /* We need to be able to fix up arbitrary expressions in some statements.
3471 This is so that we can handle symbols that are an arbitrary distance from
3472 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3473 which returns part of an address in a form which will be valid for
3474 a data instruction. We do this by pushing the expression into a symbol
3475 in the expr_section, and creating a fix for that. */
3478 fix_new_aarch64 (fragS
* frag
,
3480 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3490 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3494 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3501 /* Diagnostics on operands errors. */
3503 /* By default, output one-line error message only.
3504 Enable the verbose error message by -merror-verbose. */
3505 static int verbose_error_p
= 0;
3507 #ifdef DEBUG_AARCH64
3508 /* N.B. this is only for the purpose of debugging. */
3509 const char* operand_mismatch_kind_names
[] =
3512 "AARCH64_OPDE_RECOVERABLE",
3513 "AARCH64_OPDE_SYNTAX_ERROR",
3514 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3515 "AARCH64_OPDE_INVALID_VARIANT",
3516 "AARCH64_OPDE_OUT_OF_RANGE",
3517 "AARCH64_OPDE_UNALIGNED",
3518 "AARCH64_OPDE_REG_LIST",
3519 "AARCH64_OPDE_OTHER_ERROR",
3521 #endif /* DEBUG_AARCH64 */
3523 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3525 When multiple errors of different kinds are found in the same assembly
3526 line, only the error of the highest severity will be picked up for
3527 issuing the diagnostics. */
3529 static inline bfd_boolean
3530 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3531 enum aarch64_operand_error_kind rhs
)
3533 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3534 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3535 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3536 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3537 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3538 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3539 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3540 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3544 /* Helper routine to get the mnemonic name from the assembly instruction
3545 line; should only be called for the diagnosis purpose, as there is
3546 string copy operation involved, which may affect the runtime
3547 performance if used in elsewhere. */
3550 get_mnemonic_name (const char *str
)
3552 static char mnemonic
[32];
3555 /* Get the first 15 bytes and assume that the full name is included. */
3556 strncpy (mnemonic
, str
, 31);
3557 mnemonic
[31] = '\0';
3559 /* Scan up to the end of the mnemonic, which must end in white space,
3560 '.', or end of string. */
3561 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3566 /* Append '...' to the truncated long name. */
3567 if (ptr
- mnemonic
== 31)
3568 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3574 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3576 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3577 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3580 /* Data strutures storing one user error in the assembly code related to
3583 struct operand_error_record
3585 const aarch64_opcode
*opcode
;
3586 aarch64_operand_error detail
;
3587 struct operand_error_record
*next
;
3590 typedef struct operand_error_record operand_error_record
;
3592 struct operand_errors
3594 operand_error_record
*head
;
3595 operand_error_record
*tail
;
3598 typedef struct operand_errors operand_errors
;
3600 /* Top-level data structure reporting user errors for the current line of
3602 The way md_assemble works is that all opcodes sharing the same mnemonic
3603 name are iterated to find a match to the assembly line. In this data
3604 structure, each of the such opcodes will have one operand_error_record
3605 allocated and inserted. In other words, excessive errors related with
3606 a single opcode are disregarded. */
3607 operand_errors operand_error_report
;
3609 /* Free record nodes. */
3610 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3612 /* Initialize the data structure that stores the operand mismatch
3613 information on assembling one line of the assembly code. */
3615 init_operand_error_report (void)
3617 if (operand_error_report
.head
!= NULL
)
3619 gas_assert (operand_error_report
.tail
!= NULL
);
3620 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3621 free_opnd_error_record_nodes
= operand_error_report
.head
;
3622 operand_error_report
.head
= NULL
;
3623 operand_error_report
.tail
= NULL
;
3626 gas_assert (operand_error_report
.tail
== NULL
);
3629 /* Return TRUE if some operand error has been recorded during the
3630 parsing of the current assembly line using the opcode *OPCODE;
3631 otherwise return FALSE. */
3632 static inline bfd_boolean
3633 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3635 operand_error_record
*record
= operand_error_report
.head
;
3636 return record
&& record
->opcode
== opcode
;
3639 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3640 OPCODE field is initialized with OPCODE.
3641 N.B. only one record for each opcode, i.e. the maximum of one error is
3642 recorded for each instruction template. */
3645 add_operand_error_record (const operand_error_record
* new_record
)
3647 const aarch64_opcode
*opcode
= new_record
->opcode
;
3648 operand_error_record
* record
= operand_error_report
.head
;
3650 /* The record may have been created for this opcode. If not, we need
3652 if (! opcode_has_operand_error_p (opcode
))
3654 /* Get one empty record. */
3655 if (free_opnd_error_record_nodes
== NULL
)
3657 record
= xmalloc (sizeof (operand_error_record
));
3663 record
= free_opnd_error_record_nodes
;
3664 free_opnd_error_record_nodes
= record
->next
;
3666 record
->opcode
= opcode
;
3667 /* Insert at the head. */
3668 record
->next
= operand_error_report
.head
;
3669 operand_error_report
.head
= record
;
3670 if (operand_error_report
.tail
== NULL
)
3671 operand_error_report
.tail
= record
;
3673 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3674 && record
->detail
.index
<= new_record
->detail
.index
3675 && operand_error_higher_severity_p (record
->detail
.kind
,
3676 new_record
->detail
.kind
))
3678 /* In the case of multiple errors found on operands related with a
3679 single opcode, only record the error of the leftmost operand and
3680 only if the error is of higher severity. */
3681 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3682 " the existing error %s on operand %d",
3683 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3684 new_record
->detail
.index
,
3685 operand_mismatch_kind_names
[record
->detail
.kind
],
3686 record
->detail
.index
);
3690 record
->detail
= new_record
->detail
;
3694 record_operand_error_info (const aarch64_opcode
*opcode
,
3695 aarch64_operand_error
*error_info
)
3697 operand_error_record record
;
3698 record
.opcode
= opcode
;
3699 record
.detail
= *error_info
;
3700 add_operand_error_record (&record
);
3703 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3704 error message *ERROR, for operand IDX (count from 0). */
3707 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3708 enum aarch64_operand_error_kind kind
,
3711 aarch64_operand_error info
;
3712 memset(&info
, 0, sizeof (info
));
3716 record_operand_error_info (opcode
, &info
);
3720 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3721 enum aarch64_operand_error_kind kind
,
3722 const char* error
, const int *extra_data
)
3724 aarch64_operand_error info
;
3728 info
.data
[0] = extra_data
[0];
3729 info
.data
[1] = extra_data
[1];
3730 info
.data
[2] = extra_data
[2];
3731 record_operand_error_info (opcode
, &info
);
3735 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
3736 const char* error
, int lower_bound
,
3739 int data
[3] = {lower_bound
, upper_bound
, 0};
3740 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
3744 /* Remove the operand error record for *OPCODE. */
3745 static void ATTRIBUTE_UNUSED
3746 remove_operand_error_record (const aarch64_opcode
*opcode
)
3748 if (opcode_has_operand_error_p (opcode
))
3750 operand_error_record
* record
= operand_error_report
.head
;
3751 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
3752 operand_error_report
.head
= record
->next
;
3753 record
->next
= free_opnd_error_record_nodes
;
3754 free_opnd_error_record_nodes
= record
;
3755 if (operand_error_report
.head
== NULL
)
3757 gas_assert (operand_error_report
.tail
== record
);
3758 operand_error_report
.tail
= NULL
;
3763 /* Given the instruction in *INSTR, return the index of the best matched
3764 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3766 Return -1 if there is no qualifier sequence; return the first match
3767 if there is multiple matches found. */
3770 find_best_match (const aarch64_inst
*instr
,
3771 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
3773 int i
, num_opnds
, max_num_matched
, idx
;
3775 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3778 DEBUG_TRACE ("no operand");
3782 max_num_matched
= 0;
3785 /* For each pattern. */
3786 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
3789 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
3791 /* Most opcodes has much fewer patterns in the list. */
3792 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
3794 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
3795 if (i
!= 0 && idx
== -1)
3796 /* If nothing has been matched, return the 1st sequence. */
3801 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
3802 if (*qualifiers
== instr
->operands
[j
].qualifier
)
3805 if (num_matched
> max_num_matched
)
3807 max_num_matched
= num_matched
;
3812 DEBUG_TRACE ("return with %d", idx
);
3816 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3817 corresponding operands in *INSTR. */
3820 assign_qualifier_sequence (aarch64_inst
*instr
,
3821 const aarch64_opnd_qualifier_t
*qualifiers
)
3824 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3825 gas_assert (num_opnds
);
3826 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
3827 instr
->operands
[i
].qualifier
= *qualifiers
;
3830 /* Print operands for the diagnosis purpose. */
3833 print_operands (char *buf
, const aarch64_opcode
*opcode
,
3834 const aarch64_opnd_info
*opnds
)
3838 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
3840 const size_t size
= 128;
3843 /* We regard the opcode operand info more, however we also look into
3844 the inst->operands to support the disassembling of the optional
3846 The two operand code should be the same in all cases, apart from
3847 when the operand can be optional. */
3848 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
3849 || opnds
[i
].type
== AARCH64_OPND_NIL
)
3852 /* Generate the operand string in STR. */
3853 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
3857 strcat (buf
, i
== 0 ? " " : ",");
3859 /* Append the operand string. */
3864 /* Send to stderr a string as information. */
3867 output_info (const char *format
, ...)
3873 as_where (&file
, &line
);
3877 fprintf (stderr
, "%s:%u: ", file
, line
);
3879 fprintf (stderr
, "%s: ", file
);
3881 fprintf (stderr
, _("Info: "));
3882 va_start (args
, format
);
3883 vfprintf (stderr
, format
, args
);
3885 (void) putc ('\n', stderr
);
3888 /* Output one operand error record. */
3891 output_operand_error_record (const operand_error_record
*record
, char *str
)
3893 int idx
= record
->detail
.index
;
3894 const aarch64_opcode
*opcode
= record
->opcode
;
3895 enum aarch64_opnd opd_code
= (idx
!= -1 ? opcode
->operands
[idx
]
3896 : AARCH64_OPND_NIL
);
3897 const aarch64_operand_error
*detail
= &record
->detail
;
3899 switch (detail
->kind
)
3901 case AARCH64_OPDE_NIL
:
3905 case AARCH64_OPDE_SYNTAX_ERROR
:
3906 case AARCH64_OPDE_RECOVERABLE
:
3907 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
3908 case AARCH64_OPDE_OTHER_ERROR
:
3909 gas_assert (idx
>= 0);
3910 /* Use the prepared error message if there is, otherwise use the
3911 operand description string to describe the error. */
3912 if (detail
->error
!= NULL
)
3914 if (detail
->index
== -1)
3915 as_bad (_("%s -- `%s'"), detail
->error
, str
);
3917 as_bad (_("%s at operand %d -- `%s'"),
3918 detail
->error
, detail
->index
+ 1, str
);
3921 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
3922 aarch64_get_operand_desc (opd_code
), str
);
3925 case AARCH64_OPDE_INVALID_VARIANT
:
3926 as_bad (_("operand mismatch -- `%s'"), str
);
3927 if (verbose_error_p
)
3929 /* We will try to correct the erroneous instruction and also provide
3930 more information e.g. all other valid variants.
3932 The string representation of the corrected instruction and other
3933 valid variants are generated by
3935 1) obtaining the intermediate representation of the erroneous
3937 2) manipulating the IR, e.g. replacing the operand qualifier;
3938 3) printing out the instruction by calling the printer functions
3939 shared with the disassembler.
3941 The limitation of this method is that the exact input assembly
3942 line cannot be accurately reproduced in some cases, for example an
3943 optional operand present in the actual assembly line will be
3944 omitted in the output; likewise for the optional syntax rules,
3945 e.g. the # before the immediate. Another limitation is that the
3946 assembly symbols and relocation operations in the assembly line
3947 currently cannot be printed out in the error report. Last but not
3948 least, when there is other error(s) co-exist with this error, the
3949 'corrected' instruction may be still incorrect, e.g. given
3950 'ldnp h0,h1,[x0,#6]!'
3951 this diagnosis will provide the version:
3952 'ldnp s0,s1,[x0,#6]!'
3953 which is still not right. */
3954 size_t len
= strlen (get_mnemonic_name (str
));
3957 const size_t size
= 2048;
3959 aarch64_inst
*inst_base
= &inst
.base
;
3960 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
3963 reset_aarch64_instruction (&inst
);
3964 inst_base
->opcode
= opcode
;
3966 /* Reset the error report so that there is no side effect on the
3967 following operand parsing. */
3968 init_operand_error_report ();
3971 result
= parse_operands (str
+ len
, opcode
)
3972 && programmer_friendly_fixup (&inst
);
3973 gas_assert (result
);
3974 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
3976 gas_assert (!result
);
3978 /* Find the most matched qualifier sequence. */
3979 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
3980 gas_assert (qlf_idx
> -1);
3982 /* Assign the qualifiers. */
3983 assign_qualifier_sequence (inst_base
,
3984 opcode
->qualifiers_list
[qlf_idx
]);
3986 /* Print the hint. */
3987 output_info (_(" did you mean this?"));
3988 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
3989 print_operands (buf
, opcode
, inst_base
->operands
);
3990 output_info (_(" %s"), buf
);
3992 /* Print out other variant(s) if there is any. */
3994 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
3995 output_info (_(" other valid variant(s):"));
3997 /* For each pattern. */
3998 qualifiers_list
= opcode
->qualifiers_list
;
3999 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4001 /* Most opcodes has much fewer patterns in the list.
4002 First NIL qualifier indicates the end in the list. */
4003 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4008 /* Mnemonics name. */
4009 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4011 /* Assign the qualifiers. */
4012 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4014 /* Print instruction. */
4015 print_operands (buf
, opcode
, inst_base
->operands
);
4017 output_info (_(" %s"), buf
);
4023 case AARCH64_OPDE_OUT_OF_RANGE
:
4024 if (detail
->data
[0] != detail
->data
[1])
4025 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4026 detail
->error
? detail
->error
: _("immediate value"),
4027 detail
->data
[0], detail
->data
[1], detail
->index
+ 1, str
);
4029 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4030 detail
->error
? detail
->error
: _("immediate value"),
4031 detail
->data
[0], detail
->index
+ 1, str
);
4034 case AARCH64_OPDE_REG_LIST
:
4035 if (detail
->data
[0] == 1)
4036 as_bad (_("invalid number of registers in the list; "
4037 "only 1 register is expected at operand %d -- `%s'"),
4038 detail
->index
+ 1, str
);
4040 as_bad (_("invalid number of registers in the list; "
4041 "%d registers are expected at operand %d -- `%s'"),
4042 detail
->data
[0], detail
->index
+ 1, str
);
4045 case AARCH64_OPDE_UNALIGNED
:
4046 as_bad (_("immediate value should be a multiple of "
4047 "%d at operand %d -- `%s'"),
4048 detail
->data
[0], detail
->index
+ 1, str
);
4057 /* Process and output the error message about the operand mismatching.
4059 When this function is called, the operand error information had
4060 been collected for an assembly line and there will be multiple
4061 errors in the case of mulitple instruction templates; output the
4062 error message that most closely describes the problem. */
4065 output_operand_error_report (char *str
)
4067 int largest_error_pos
;
4068 const char *msg
= NULL
;
4069 enum aarch64_operand_error_kind kind
;
4070 operand_error_record
*curr
;
4071 operand_error_record
*head
= operand_error_report
.head
;
4072 operand_error_record
*record
= NULL
;
4074 /* No error to report. */
4078 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4080 /* Only one error. */
4081 if (head
== operand_error_report
.tail
)
4083 DEBUG_TRACE ("single opcode entry with error kind: %s",
4084 operand_mismatch_kind_names
[head
->detail
.kind
]);
4085 output_operand_error_record (head
, str
);
4089 /* Find the error kind of the highest severity. */
4090 DEBUG_TRACE ("multiple opcode entres with error kind");
4091 kind
= AARCH64_OPDE_NIL
;
4092 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4094 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4095 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4096 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4097 kind
= curr
->detail
.kind
;
4099 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4101 /* Pick up one of errors of KIND to report. */
4102 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4103 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4105 if (curr
->detail
.kind
!= kind
)
4107 /* If there are multiple errors, pick up the one with the highest
4108 mismatching operand index. In the case of multiple errors with
4109 the equally highest operand index, pick up the first one or the
4110 first one with non-NULL error message. */
4111 if (curr
->detail
.index
> largest_error_pos
4112 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4113 && curr
->detail
.error
!= NULL
))
4115 largest_error_pos
= curr
->detail
.index
;
4117 msg
= record
->detail
.error
;
4121 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4122 DEBUG_TRACE ("Pick up error kind %s to report",
4123 operand_mismatch_kind_names
[record
->detail
.kind
]);
4126 output_operand_error_record (record
, str
);
4129 /* Write an AARCH64 instruction to buf - always little-endian. */
4131 put_aarch64_insn (char *buf
, uint32_t insn
)
4133 unsigned char *where
= (unsigned char *) buf
;
4135 where
[1] = insn
>> 8;
4136 where
[2] = insn
>> 16;
4137 where
[3] = insn
>> 24;
4141 get_aarch64_insn (char *buf
)
4143 unsigned char *where
= (unsigned char *) buf
;
4145 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4150 output_inst (struct aarch64_inst
*new_inst
)
4154 to
= frag_more (INSN_SIZE
);
4156 frag_now
->tc_frag_data
.recorded
= 1;
4158 put_aarch64_insn (to
, inst
.base
.value
);
4160 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4162 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4163 INSN_SIZE
, &inst
.reloc
.exp
,
4166 DEBUG_TRACE ("Prepared relocation fix up");
4167 /* Don't check the addend value against the instruction size,
4168 that's the job of our code in md_apply_fix(). */
4169 fixp
->fx_no_overflow
= 1;
4170 if (new_inst
!= NULL
)
4171 fixp
->tc_fix_data
.inst
= new_inst
;
4172 if (aarch64_gas_internal_fixup_p ())
4174 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4175 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4176 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4180 dwarf2_emit_insn (INSN_SIZE
);
4183 /* Link together opcodes of the same name. */
4187 aarch64_opcode
*opcode
;
4188 struct templates
*next
;
4191 typedef struct templates templates
;
4194 lookup_mnemonic (const char *start
, int len
)
4196 templates
*templ
= NULL
;
4198 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4202 /* Subroutine of md_assemble, responsible for looking up the primary
4203 opcode from the mnemonic the user wrote. STR points to the
4204 beginning of the mnemonic. */
4207 opcode_lookup (char **str
)
4210 const aarch64_cond
*cond
;
4214 /* Scan up to the end of the mnemonic, which must end in white space,
4215 '.', or end of string. */
4216 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4223 inst
.cond
= COND_ALWAYS
;
4225 /* Handle a possible condition. */
4228 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4231 inst
.cond
= cond
->value
;
4245 if (inst
.cond
== COND_ALWAYS
)
4247 /* Look for unaffixed mnemonic. */
4248 return lookup_mnemonic (base
, len
);
4252 /* append ".c" to mnemonic if conditional */
4253 memcpy (condname
, base
, len
);
4254 memcpy (condname
+ len
, ".c", 2);
4257 return lookup_mnemonic (base
, len
);
4263 /* Internal helper routine converting a vector neon_type_el structure
4264 *VECTYPE to a corresponding operand qualifier. */
4266 static inline aarch64_opnd_qualifier_t
4267 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4269 /* Element size in bytes indexed by neon_el_type. */
4270 const unsigned char ele_size
[5]
4273 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4274 goto vectype_conversion_fail
;
4276 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4278 if (vectype
->defined
& NTA_HASINDEX
)
4279 /* Vector element register. */
4280 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4283 /* Vector register. */
4284 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4286 if (reg_size
!= 16 && reg_size
!= 8)
4287 goto vectype_conversion_fail
;
4288 /* The conversion is calculated based on the relation of the order of
4289 qualifiers to the vector element size and vector register size. */
4290 offset
= (vectype
->type
== NT_q
)
4291 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4292 gas_assert (offset
<= 8);
4293 return AARCH64_OPND_QLF_V_8B
+ offset
;
4296 vectype_conversion_fail
:
4297 first_error (_("bad vector arrangement type"));
4298 return AARCH64_OPND_QLF_NIL
;
4301 /* Process an optional operand that is found omitted from the assembly line.
4302 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4303 instruction's opcode entry while IDX is the index of this omitted operand.
4307 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4308 int idx
, aarch64_opnd_info
*operand
)
4310 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4311 gas_assert (optional_operand_p (opcode
, idx
));
4312 gas_assert (!operand
->present
);
4316 case AARCH64_OPND_Rd
:
4317 case AARCH64_OPND_Rn
:
4318 case AARCH64_OPND_Rm
:
4319 case AARCH64_OPND_Rt
:
4320 case AARCH64_OPND_Rt2
:
4321 case AARCH64_OPND_Rs
:
4322 case AARCH64_OPND_Ra
:
4323 case AARCH64_OPND_Rt_SYS
:
4324 case AARCH64_OPND_Rd_SP
:
4325 case AARCH64_OPND_Rn_SP
:
4326 case AARCH64_OPND_Fd
:
4327 case AARCH64_OPND_Fn
:
4328 case AARCH64_OPND_Fm
:
4329 case AARCH64_OPND_Fa
:
4330 case AARCH64_OPND_Ft
:
4331 case AARCH64_OPND_Ft2
:
4332 case AARCH64_OPND_Sd
:
4333 case AARCH64_OPND_Sn
:
4334 case AARCH64_OPND_Sm
:
4335 case AARCH64_OPND_Vd
:
4336 case AARCH64_OPND_Vn
:
4337 case AARCH64_OPND_Vm
:
4338 case AARCH64_OPND_VdD1
:
4339 case AARCH64_OPND_VnD1
:
4340 operand
->reg
.regno
= default_value
;
4343 case AARCH64_OPND_Ed
:
4344 case AARCH64_OPND_En
:
4345 case AARCH64_OPND_Em
:
4346 operand
->reglane
.regno
= default_value
;
4349 case AARCH64_OPND_IDX
:
4350 case AARCH64_OPND_BIT_NUM
:
4351 case AARCH64_OPND_IMMR
:
4352 case AARCH64_OPND_IMMS
:
4353 case AARCH64_OPND_SHLL_IMM
:
4354 case AARCH64_OPND_IMM_VLSL
:
4355 case AARCH64_OPND_IMM_VLSR
:
4356 case AARCH64_OPND_CCMP_IMM
:
4357 case AARCH64_OPND_FBITS
:
4358 case AARCH64_OPND_UIMM4
:
4359 case AARCH64_OPND_UIMM3_OP1
:
4360 case AARCH64_OPND_UIMM3_OP2
:
4361 case AARCH64_OPND_IMM
:
4362 case AARCH64_OPND_WIDTH
:
4363 case AARCH64_OPND_UIMM7
:
4364 case AARCH64_OPND_NZCV
:
4365 operand
->imm
.value
= default_value
;
4368 case AARCH64_OPND_EXCEPTION
:
4369 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4372 case AARCH64_OPND_BARRIER_ISB
:
4373 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4380 /* Process the relocation type for move wide instructions.
4381 Return TRUE on success; otherwise return FALSE. */
4384 process_movw_reloc_info (void)
4389 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4391 if (inst
.base
.opcode
->op
== OP_MOVK
)
4392 switch (inst
.reloc
.type
)
4394 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4395 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4396 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4397 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4398 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4399 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4400 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4401 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4403 (_("the specified relocation type is not allowed for MOVK"));
4409 switch (inst
.reloc
.type
)
4411 case BFD_RELOC_AARCH64_MOVW_G0
:
4412 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4413 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4414 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4415 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4418 case BFD_RELOC_AARCH64_MOVW_G1
:
4419 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4420 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4421 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4422 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4425 case BFD_RELOC_AARCH64_MOVW_G2
:
4426 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4427 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4428 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4431 set_fatal_syntax_error
4432 (_("the specified relocation type is not allowed for 32-bit "
4438 case BFD_RELOC_AARCH64_MOVW_G3
:
4441 set_fatal_syntax_error
4442 (_("the specified relocation type is not allowed for 32-bit "
4449 /* More cases should be added when more MOVW-related relocation types
4450 are supported in GAS. */
4451 gas_assert (aarch64_gas_internal_fixup_p ());
4452 /* The shift amount should have already been set by the parser. */
4455 inst
.base
.operands
[1].shifter
.amount
= shift
;
4459 /* A primitive log caculator. */
4461 static inline unsigned int
4462 get_logsz (unsigned int size
)
4464 const unsigned char ls
[16] =
4465 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4471 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4472 return ls
[size
- 1];
4475 /* Determine and return the real reloc type code for an instruction
4476 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4478 static inline bfd_reloc_code_real_type
4479 ldst_lo12_determine_real_reloc_type (void)
4482 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4483 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4485 const bfd_reloc_code_real_type reloc_ldst_lo12
[5] = {
4486 BFD_RELOC_AARCH64_LDST8_LO12
, BFD_RELOC_AARCH64_LDST16_LO12
,
4487 BFD_RELOC_AARCH64_LDST32_LO12
, BFD_RELOC_AARCH64_LDST64_LO12
,
4488 BFD_RELOC_AARCH64_LDST128_LO12
4491 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
);
4492 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4494 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4496 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4498 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4500 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4501 gas_assert (logsz
>= 0 && logsz
<= 4);
4503 return reloc_ldst_lo12
[logsz
];
4506 /* Check whether a register list REGINFO is valid. The registers must be
4507 numbered in increasing order (modulo 32), in increments of one or two.
4509 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4512 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4515 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4517 uint32_t i
, nb_regs
, prev_regno
, incr
;
4519 nb_regs
= 1 + (reginfo
& 0x3);
4521 prev_regno
= reginfo
& 0x1f;
4522 incr
= accept_alternate
? 2 : 1;
4524 for (i
= 1; i
< nb_regs
; ++i
)
4526 uint32_t curr_regno
;
4528 curr_regno
= reginfo
& 0x1f;
4529 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4531 prev_regno
= curr_regno
;
4537 /* Generic instruction operand parser. This does no encoding and no
4538 semantic validation; it merely squirrels values away in the inst
4539 structure. Returns TRUE or FALSE depending on whether the
4540 specified grammar matched. */
4543 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4546 char *backtrack_pos
= 0;
4547 const enum aarch64_opnd
*operands
= opcode
->operands
;
4550 skip_whitespace (str
);
4552 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4555 int isreg32
, isregzero
;
4556 int comma_skipped_p
= 0;
4557 aarch64_reg_type rtype
;
4558 struct neon_type_el vectype
;
4559 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4561 DEBUG_TRACE ("parse operand %d", i
);
4563 /* Assign the operand code. */
4564 info
->type
= operands
[i
];
4566 if (optional_operand_p (opcode
, i
))
4568 /* Remember where we are in case we need to backtrack. */
4569 gas_assert (!backtrack_pos
);
4570 backtrack_pos
= str
;
4573 /* Expect comma between operands; the backtrack mechanizm will take
4574 care of cases of omitted optional operand. */
4575 if (i
> 0 && ! skip_past_char (&str
, ','))
4577 set_syntax_error (_("comma expected between operands"));
4581 comma_skipped_p
= 1;
4583 switch (operands
[i
])
4585 case AARCH64_OPND_Rd
:
4586 case AARCH64_OPND_Rn
:
4587 case AARCH64_OPND_Rm
:
4588 case AARCH64_OPND_Rt
:
4589 case AARCH64_OPND_Rt2
:
4590 case AARCH64_OPND_Rs
:
4591 case AARCH64_OPND_Ra
:
4592 case AARCH64_OPND_Rt_SYS
:
4593 po_int_reg_or_fail (1, 0);
4596 case AARCH64_OPND_Rd_SP
:
4597 case AARCH64_OPND_Rn_SP
:
4598 po_int_reg_or_fail (0, 1);
4601 case AARCH64_OPND_Rm_EXT
:
4602 case AARCH64_OPND_Rm_SFT
:
4603 po_misc_or_fail (parse_shifter_operand
4604 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4606 : SHIFTED_LOGIC_IMM
)));
4607 if (!info
->shifter
.operator_present
)
4609 /* Default to LSL if not present. Libopcodes prefers shifter
4610 kind to be explicit. */
4611 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4612 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4613 /* For Rm_EXT, libopcodes will carry out further check on whether
4614 or not stack pointer is used in the instruction (Recall that
4615 "the extend operator is not optional unless at least one of
4616 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4620 case AARCH64_OPND_Fd
:
4621 case AARCH64_OPND_Fn
:
4622 case AARCH64_OPND_Fm
:
4623 case AARCH64_OPND_Fa
:
4624 case AARCH64_OPND_Ft
:
4625 case AARCH64_OPND_Ft2
:
4626 case AARCH64_OPND_Sd
:
4627 case AARCH64_OPND_Sn
:
4628 case AARCH64_OPND_Sm
:
4629 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4630 if (val
== PARSE_FAIL
)
4632 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4635 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4637 info
->reg
.regno
= val
;
4638 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4641 case AARCH64_OPND_Vd
:
4642 case AARCH64_OPND_Vn
:
4643 case AARCH64_OPND_Vm
:
4644 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4645 if (val
== PARSE_FAIL
)
4647 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4650 if (vectype
.defined
& NTA_HASINDEX
)
4653 info
->reg
.regno
= val
;
4654 info
->qualifier
= vectype_to_qualifier (&vectype
);
4655 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4659 case AARCH64_OPND_VdD1
:
4660 case AARCH64_OPND_VnD1
:
4661 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4662 if (val
== PARSE_FAIL
)
4664 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4667 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4669 set_fatal_syntax_error
4670 (_("the top half of a 128-bit FP/SIMD register is expected"));
4673 info
->reg
.regno
= val
;
4674 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4675 here; it is correct for the purpose of encoding/decoding since
4676 only the register number is explicitly encoded in the related
4677 instructions, although this appears a bit hacky. */
4678 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4681 case AARCH64_OPND_Ed
:
4682 case AARCH64_OPND_En
:
4683 case AARCH64_OPND_Em
:
4684 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4685 if (val
== PARSE_FAIL
)
4687 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4690 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
4693 info
->reglane
.regno
= val
;
4694 info
->reglane
.index
= vectype
.index
;
4695 info
->qualifier
= vectype_to_qualifier (&vectype
);
4696 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4700 case AARCH64_OPND_LVn
:
4701 case AARCH64_OPND_LVt
:
4702 case AARCH64_OPND_LVt_AL
:
4703 case AARCH64_OPND_LEt
:
4704 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
4706 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
4708 set_fatal_syntax_error (_("invalid register list"));
4711 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
4712 info
->reglist
.num_regs
= (val
& 0x3) + 1;
4713 if (operands
[i
] == AARCH64_OPND_LEt
)
4715 if (!(vectype
.defined
& NTA_HASINDEX
))
4717 info
->reglist
.has_index
= 1;
4718 info
->reglist
.index
= vectype
.index
;
4720 else if (!(vectype
.defined
& NTA_HASTYPE
))
4722 info
->qualifier
= vectype_to_qualifier (&vectype
);
4723 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4727 case AARCH64_OPND_Cn
:
4728 case AARCH64_OPND_Cm
:
4729 po_reg_or_fail (REG_TYPE_CN
);
4732 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
4735 inst
.base
.operands
[i
].reg
.regno
= val
;
4738 case AARCH64_OPND_SHLL_IMM
:
4739 case AARCH64_OPND_IMM_VLSR
:
4740 po_imm_or_fail (1, 64);
4741 info
->imm
.value
= val
;
4744 case AARCH64_OPND_CCMP_IMM
:
4745 case AARCH64_OPND_FBITS
:
4746 case AARCH64_OPND_UIMM4
:
4747 case AARCH64_OPND_UIMM3_OP1
:
4748 case AARCH64_OPND_UIMM3_OP2
:
4749 case AARCH64_OPND_IMM_VLSL
:
4750 case AARCH64_OPND_IMM
:
4751 case AARCH64_OPND_WIDTH
:
4752 po_imm_nc_or_fail ();
4753 info
->imm
.value
= val
;
4756 case AARCH64_OPND_UIMM7
:
4757 po_imm_or_fail (0, 127);
4758 info
->imm
.value
= val
;
4761 case AARCH64_OPND_IDX
:
4762 case AARCH64_OPND_BIT_NUM
:
4763 case AARCH64_OPND_IMMR
:
4764 case AARCH64_OPND_IMMS
:
4765 po_imm_or_fail (0, 63);
4766 info
->imm
.value
= val
;
4769 case AARCH64_OPND_IMM0
:
4770 po_imm_nc_or_fail ();
4773 set_fatal_syntax_error (_("immediate zero expected"));
4776 info
->imm
.value
= 0;
4779 case AARCH64_OPND_FPIMM0
:
4782 bfd_boolean res1
= FALSE
, res2
= FALSE
;
4783 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4784 it is probably not worth the effort to support it. */
4785 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
4786 && !(res2
= parse_constant_immediate (&str
, &val
)))
4788 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
4790 info
->imm
.value
= 0;
4791 info
->imm
.is_fp
= 1;
4794 set_fatal_syntax_error (_("immediate zero expected"));
4798 case AARCH64_OPND_IMM_MOV
:
4801 if (reg_name_p (str
, REG_TYPE_R_Z_SP
))
4804 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
4806 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4807 later. fix_mov_imm_insn will try to determine a machine
4808 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4809 message if the immediate cannot be moved by a single
4811 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
4812 inst
.base
.operands
[i
].skip
= 1;
4816 case AARCH64_OPND_SIMD_IMM
:
4817 case AARCH64_OPND_SIMD_IMM_SFT
:
4818 if (! parse_big_immediate (&str
, &val
))
4820 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4822 /* need_libopcodes_p */ 1,
4825 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4826 shift, we don't check it here; we leave the checking to
4827 the libopcodes (operand_general_constraint_met_p). By
4828 doing this, we achieve better diagnostics. */
4829 if (skip_past_comma (&str
)
4830 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
4832 if (!info
->shifter
.operator_present
4833 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
4835 /* Default to LSL if not present. Libopcodes prefers shifter
4836 kind to be explicit. */
4837 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4838 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4842 case AARCH64_OPND_FPIMM
:
4843 case AARCH64_OPND_SIMD_FPIMM
:
4847 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
4849 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
4853 set_fatal_syntax_error (_("invalid floating-point constant"));
4856 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
4857 inst
.base
.operands
[i
].imm
.is_fp
= 1;
4861 case AARCH64_OPND_LIMM
:
4862 po_misc_or_fail (parse_shifter_operand (&str
, info
,
4863 SHIFTED_LOGIC_IMM
));
4864 if (info
->shifter
.operator_present
)
4866 set_fatal_syntax_error
4867 (_("shift not allowed for bitmask immediate"));
4870 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4872 /* need_libopcodes_p */ 1,
4876 case AARCH64_OPND_AIMM
:
4877 if (opcode
->op
== OP_ADD
)
4878 /* ADD may have relocation types. */
4879 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
4880 SHIFTED_ARITH_IMM
));
4882 po_misc_or_fail (parse_shifter_operand (&str
, info
,
4883 SHIFTED_ARITH_IMM
));
4884 switch (inst
.reloc
.type
)
4886 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
4887 info
->shifter
.amount
= 12;
4889 case BFD_RELOC_UNUSED
:
4890 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
4891 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
4892 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
4893 inst
.reloc
.pc_rel
= 0;
4898 info
->imm
.value
= 0;
4899 if (!info
->shifter
.operator_present
)
4901 /* Default to LSL if not present. Libopcodes prefers shifter
4902 kind to be explicit. */
4903 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4904 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4908 case AARCH64_OPND_HALF
:
4910 /* #<imm16> or relocation. */
4911 int internal_fixup_p
;
4912 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
4913 if (internal_fixup_p
)
4914 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
4915 skip_whitespace (str
);
4916 if (skip_past_comma (&str
))
4918 /* {, LSL #<shift>} */
4919 if (! aarch64_gas_internal_fixup_p ())
4921 set_fatal_syntax_error (_("can't mix relocation modifier "
4922 "with explicit shift"));
4925 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
4928 inst
.base
.operands
[i
].shifter
.amount
= 0;
4929 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
4930 inst
.base
.operands
[i
].imm
.value
= 0;
4931 if (! process_movw_reloc_info ())
4936 case AARCH64_OPND_EXCEPTION
:
4937 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
4938 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4940 /* need_libopcodes_p */ 0,
4944 case AARCH64_OPND_NZCV
:
4946 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
4950 info
->imm
.value
= nzcv
->value
;
4953 po_imm_or_fail (0, 15);
4954 info
->imm
.value
= val
;
4958 case AARCH64_OPND_COND
:
4959 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
4961 if (info
->cond
== NULL
)
4963 set_syntax_error (_("invalid condition"));
4968 case AARCH64_OPND_ADDR_ADRP
:
4969 po_misc_or_fail (parse_adrp (&str
));
4970 /* Clear the value as operand needs to be relocated. */
4971 info
->imm
.value
= 0;
4974 case AARCH64_OPND_ADDR_PCREL14
:
4975 case AARCH64_OPND_ADDR_PCREL19
:
4976 case AARCH64_OPND_ADDR_PCREL21
:
4977 case AARCH64_OPND_ADDR_PCREL26
:
4978 po_misc_or_fail (parse_address_reloc (&str
, info
));
4979 if (!info
->addr
.pcrel
)
4981 set_syntax_error (_("invalid pc-relative address"));
4984 if (inst
.gen_lit_pool
4985 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
4987 /* Only permit "=value" in the literal load instructions.
4988 The literal will be generated by programmer_friendly_fixup. */
4989 set_syntax_error (_("invalid use of \"=immediate\""));
4992 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
4994 set_syntax_error (_("unrecognized relocation suffix"));
4997 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
4999 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5000 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5004 info
->imm
.value
= 0;
5005 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5006 switch (opcode
->iclass
)
5010 /* e.g. CBZ or B.COND */
5011 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5012 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5016 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5017 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5021 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5023 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5024 : BFD_RELOC_AARCH64_JUMP26
;
5027 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5028 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5031 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5032 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5038 inst
.reloc
.pc_rel
= 1;
5042 case AARCH64_OPND_ADDR_SIMPLE
:
5043 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5044 /* [<Xn|SP>{, #<simm>}] */
5045 po_char_or_fail ('[');
5046 po_reg_or_fail (REG_TYPE_R64_SP
);
5047 /* Accept optional ", #0". */
5048 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5049 && skip_past_char (&str
, ','))
5051 skip_past_char (&str
, '#');
5052 if (! skip_past_char (&str
, '0'))
5054 set_fatal_syntax_error
5055 (_("the optional immediate offset can only be 0"));
5059 po_char_or_fail (']');
5060 info
->addr
.base_regno
= val
;
5063 case AARCH64_OPND_ADDR_REGOFF
:
5064 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5065 po_misc_or_fail (parse_address (&str
, info
, 0));
5066 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5067 || !info
->addr
.preind
|| info
->addr
.postind
5068 || info
->addr
.writeback
)
5070 set_syntax_error (_("invalid addressing mode"));
5073 if (!info
->shifter
.operator_present
)
5075 /* Default to LSL if not present. Libopcodes prefers shifter
5076 kind to be explicit. */
5077 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5078 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5080 /* Qualifier to be deduced by libopcodes. */
5083 case AARCH64_OPND_ADDR_SIMM7
:
5084 po_misc_or_fail (parse_address (&str
, info
, 0));
5085 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5086 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5088 set_syntax_error (_("invalid addressing mode"));
5091 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5093 /* need_libopcodes_p */ 1,
5097 case AARCH64_OPND_ADDR_SIMM9
:
5098 case AARCH64_OPND_ADDR_SIMM9_2
:
5099 po_misc_or_fail (parse_address_reloc (&str
, info
));
5100 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5101 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5102 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5103 && info
->addr
.writeback
))
5105 set_syntax_error (_("invalid addressing mode"));
5108 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5110 set_syntax_error (_("relocation not allowed"));
5113 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5115 /* need_libopcodes_p */ 1,
5119 case AARCH64_OPND_ADDR_UIMM12
:
5120 po_misc_or_fail (parse_address_reloc (&str
, info
));
5121 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5122 || !info
->addr
.preind
|| info
->addr
.writeback
)
5124 set_syntax_error (_("invalid addressing mode"));
5127 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5128 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5129 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
)
5130 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5131 /* Leave qualifier to be determined by libopcodes. */
5134 case AARCH64_OPND_SIMD_ADDR_POST
:
5135 /* [<Xn|SP>], <Xm|#<amount>> */
5136 po_misc_or_fail (parse_address (&str
, info
, 1));
5137 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5139 set_syntax_error (_("invalid addressing mode"));
5142 if (!info
->addr
.offset
.is_reg
)
5144 if (inst
.reloc
.exp
.X_op
== O_constant
)
5145 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5148 set_fatal_syntax_error
5149 (_("writeback value should be an immediate constant"));
5156 case AARCH64_OPND_SYSREG
:
5157 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1))
5160 set_syntax_error (_("unknown or missing system register name"));
5163 inst
.base
.operands
[i
].sysreg
= val
;
5166 case AARCH64_OPND_PSTATEFIELD
:
5167 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0))
5170 set_syntax_error (_("unknown or missing PSTATE field name"));
5173 inst
.base
.operands
[i
].pstatefield
= val
;
5176 case AARCH64_OPND_SYSREG_IC
:
5177 inst
.base
.operands
[i
].sysins_op
=
5178 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5180 case AARCH64_OPND_SYSREG_DC
:
5181 inst
.base
.operands
[i
].sysins_op
=
5182 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5184 case AARCH64_OPND_SYSREG_AT
:
5185 inst
.base
.operands
[i
].sysins_op
=
5186 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5188 case AARCH64_OPND_SYSREG_TLBI
:
5189 inst
.base
.operands
[i
].sysins_op
=
5190 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5192 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5194 set_fatal_syntax_error ( _("unknown or missing operation name"));
5199 case AARCH64_OPND_BARRIER
:
5200 case AARCH64_OPND_BARRIER_ISB
:
5201 val
= parse_barrier (&str
);
5202 if (val
!= PARSE_FAIL
5203 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5205 /* ISB only accepts options name 'sy'. */
5207 (_("the specified option is not accepted in ISB"));
5208 /* Turn off backtrack as this optional operand is present. */
5212 /* This is an extension to accept a 0..15 immediate. */
5213 if (val
== PARSE_FAIL
)
5214 po_imm_or_fail (0, 15);
5215 info
->barrier
= aarch64_barrier_options
+ val
;
5218 case AARCH64_OPND_PRFOP
:
5219 val
= parse_pldop (&str
);
5220 /* This is an extension to accept a 0..31 immediate. */
5221 if (val
== PARSE_FAIL
)
5222 po_imm_or_fail (0, 31);
5223 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5227 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5230 /* If we get here, this operand was successfully parsed. */
5231 inst
.base
.operands
[i
].present
= 1;
5235 /* The parse routine should already have set the error, but in case
5236 not, set a default one here. */
5238 set_default_error ();
5240 if (! backtrack_pos
)
5241 goto parse_operands_return
;
5243 /* Reaching here means we are dealing with an optional operand that is
5244 omitted from the assembly line. */
5245 gas_assert (optional_operand_p (opcode
, i
));
5247 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5249 /* Try again, skipping the optional operand at backtrack_pos. */
5250 str
= backtrack_pos
;
5253 /* If this is the last operand that is optional and omitted, but without
5254 the presence of a comma. */
5255 if (i
&& comma_skipped_p
&& i
== aarch64_num_of_operands (opcode
) - 1)
5257 set_fatal_syntax_error
5258 (_("unexpected comma before the omitted optional operand"));
5259 goto parse_operands_return
;
5262 /* Clear any error record after the omitted optional operand has been
5263 successfully handled. */
5267 /* Check if we have parsed all the operands. */
5268 if (*str
!= '\0' && ! error_p ())
5270 /* Set I to the index of the last present operand; this is
5271 for the purpose of diagnostics. */
5272 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5274 set_fatal_syntax_error
5275 (_("unexpected characters following instruction"));
5278 parse_operands_return
:
5282 DEBUG_TRACE ("parsing FAIL: %s - %s",
5283 operand_mismatch_kind_names
[get_error_kind ()],
5284 get_error_message ());
5285 /* Record the operand error properly; this is useful when there
5286 are multiple instruction templates for a mnemonic name, so that
5287 later on, we can select the error that most closely describes
5289 record_operand_error (opcode
, i
, get_error_kind (),
5290 get_error_message ());
5295 DEBUG_TRACE ("parsing SUCCESS");
5300 /* It does some fix-up to provide some programmer friendly feature while
5301 keeping the libopcodes happy, i.e. libopcodes only accepts
5302 the preferred architectural syntax.
5303 Return FALSE if there is any failure; otherwise return TRUE. */
5306 programmer_friendly_fixup (aarch64_instruction
*instr
)
5308 aarch64_inst
*base
= &instr
->base
;
5309 const aarch64_opcode
*opcode
= base
->opcode
;
5310 enum aarch64_op op
= opcode
->op
;
5311 aarch64_opnd_info
*operands
= base
->operands
;
5313 DEBUG_TRACE ("enter");
5315 switch (opcode
->iclass
)
5318 /* TBNZ Xn|Wn, #uimm6, label
5319 Test and Branch Not Zero: conditionally jumps to label if bit number
5320 uimm6 in register Xn is not zero. The bit number implies the width of
5321 the register, which may be written and should be disassembled as Wn if
5322 uimm is less than 32. */
5323 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5325 if (operands
[1].imm
.value
>= 32)
5327 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5331 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5335 /* LDR Wt, label | =value
5336 As a convenience assemblers will typically permit the notation
5337 "=value" in conjunction with the pc-relative literal load instructions
5338 to automatically place an immediate value or symbolic address in a
5339 nearby literal pool and generate a hidden label which references it.
5340 ISREG has been set to 0 in the case of =value. */
5341 if (instr
->gen_lit_pool
5342 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5344 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5345 if (op
== OP_LDRSW_LIT
)
5347 if (instr
->reloc
.exp
.X_op
!= O_constant
5348 && instr
->reloc
.exp
.X_op
!= O_big
5349 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5351 record_operand_error (opcode
, 1,
5352 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5353 _("constant expression expected"));
5356 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5358 record_operand_error (opcode
, 1,
5359 AARCH64_OPDE_OTHER_ERROR
,
5360 _("literal pool insertion failed"));
5368 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5369 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5370 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5371 A programmer-friendly assembler should accept a destination Xd in
5372 place of Wd, however that is not the preferred form for disassembly.
5374 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5375 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5376 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5377 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5382 /* In the 64-bit form, the final register operand is written as Wm
5383 for all but the (possibly omitted) UXTX/LSL and SXTX
5385 As a programmer-friendly assembler, we accept e.g.
5386 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5387 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5388 int idx
= aarch64_operand_index (opcode
->operands
,
5389 AARCH64_OPND_Rm_EXT
);
5390 gas_assert (idx
== 1 || idx
== 2);
5391 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5392 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5393 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5394 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5395 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5396 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5404 DEBUG_TRACE ("exit with SUCCESS");
5408 /* A wrapper function to interface with libopcodes on encoding and
5409 record the error message if there is any.
5411 Return TRUE on success; otherwise return FALSE. */
5414 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5417 aarch64_operand_error error_info
;
5418 error_info
.kind
= AARCH64_OPDE_NIL
;
5419 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5423 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5424 record_operand_error_info (opcode
, &error_info
);
5429 #ifdef DEBUG_AARCH64
5431 dump_opcode_operands (const aarch64_opcode
*opcode
)
5434 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5436 aarch64_verbose ("\t\t opnd%d: %s", i
,
5437 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5438 ? aarch64_get_operand_name (opcode
->operands
[i
])
5439 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5443 #endif /* DEBUG_AARCH64 */
5445 /* This is the guts of the machine-dependent assembler. STR points to a
5446 machine dependent instruction. This function is supposed to emit
5447 the frags/bytes it assembles to. */
5450 md_assemble (char *str
)
5453 templates
*template;
5454 aarch64_opcode
*opcode
;
5455 aarch64_inst
*inst_base
;
5456 unsigned saved_cond
;
5458 /* Align the previous label if needed. */
5459 if (last_label_seen
!= NULL
)
5461 symbol_set_frag (last_label_seen
, frag_now
);
5462 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5463 S_SET_SEGMENT (last_label_seen
, now_seg
);
5466 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5468 DEBUG_TRACE ("\n\n");
5469 DEBUG_TRACE ("==============================");
5470 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5472 template = opcode_lookup (&p
);
5475 /* It wasn't an instruction, but it might be a register alias of
5476 the form alias .req reg directive. */
5477 if (!create_register_alias (str
, p
))
5478 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5483 skip_whitespace (p
);
5486 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5487 get_mnemonic_name (str
), str
);
5491 init_operand_error_report ();
5493 saved_cond
= inst
.cond
;
5494 reset_aarch64_instruction (&inst
);
5495 inst
.cond
= saved_cond
;
5497 /* Iterate through all opcode entries with the same mnemonic name. */
5500 opcode
= template->opcode
;
5502 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5503 #ifdef DEBUG_AARCH64
5505 dump_opcode_operands (opcode
);
5506 #endif /* DEBUG_AARCH64 */
5508 /* Check that this instruction is supported for this CPU. */
5509 if (!opcode
->avariant
5510 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5512 as_bad (_("selected processor does not support `%s'"), str
);
5516 mapping_state (MAP_INSN
);
5518 inst_base
= &inst
.base
;
5519 inst_base
->opcode
= opcode
;
5521 /* Truly conditionally executed instructions, e.g. b.cond. */
5522 if (opcode
->flags
& F_COND
)
5524 gas_assert (inst
.cond
!= COND_ALWAYS
);
5525 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5526 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5528 else if (inst
.cond
!= COND_ALWAYS
)
5530 /* It shouldn't arrive here, where the assembly looks like a
5531 conditional instruction but the found opcode is unconditional. */
5536 if (parse_operands (p
, opcode
)
5537 && programmer_friendly_fixup (&inst
)
5538 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5540 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5541 || !inst
.reloc
.need_libopcodes_p
)
5545 /* If there is relocation generated for the instruction,
5546 store the instruction information for the future fix-up. */
5547 struct aarch64_inst
*copy
;
5548 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5549 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5551 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5557 template = template->next
;
5558 if (template != NULL
)
5560 reset_aarch64_instruction (&inst
);
5561 inst
.cond
= saved_cond
;
5564 while (template != NULL
);
5566 /* Issue the error messages if any. */
5567 output_operand_error_report (str
);
5570 /* Various frobbings of labels and their addresses. */
5573 aarch64_start_line_hook (void)
5575 last_label_seen
= NULL
;
5579 aarch64_frob_label (symbolS
* sym
)
5581 last_label_seen
= sym
;
5583 dwarf2_emit_label (sym
);
5587 aarch64_data_in_code (void)
5589 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5591 *input_line_pointer
= '/';
5592 input_line_pointer
+= 5;
5593 *input_line_pointer
= 0;
5601 aarch64_canonicalize_symbol_name (char *name
)
5605 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
5606 *(name
+ len
- 5) = 0;
5611 /* Table of all register names defined by default. The user can
5612 define additional names with .req. Note that all register names
5613 should appear in both upper and lowercase variants. Some registers
5614 also have mixed-case names. */
5616 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5617 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5618 #define REGSET31(p,t) \
5619 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5620 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5621 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5622 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5623 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5624 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5625 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5626 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5627 #define REGSET(p,t) \
5628 REGSET31(p,t), REGNUM(p,31,t)
5630 /* These go into aarch64_reg_hsh hash-table. */
5631 static const reg_entry reg_names
[] = {
5632 /* Integer registers. */
5633 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
5634 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
5636 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
5637 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
5639 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
5640 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
5642 /* Coprocessor register numbers. */
5643 REGSET (c
, CN
), REGSET (C
, CN
),
5645 /* Floating-point single precision registers. */
5646 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
5648 /* Floating-point double precision registers. */
5649 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
5651 /* Floating-point half precision registers. */
5652 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
5654 /* Floating-point byte precision registers. */
5655 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
5657 /* Floating-point quad precision registers. */
5658 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
5660 /* FP/SIMD registers. */
5661 REGSET (v
, VN
), REGSET (V
, VN
),
5676 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5677 static const asm_nzcv nzcv_names
[] = {
5678 {"nzcv", B (n
, z
, c
, v
)},
5679 {"nzcV", B (n
, z
, c
, V
)},
5680 {"nzCv", B (n
, z
, C
, v
)},
5681 {"nzCV", B (n
, z
, C
, V
)},
5682 {"nZcv", B (n
, Z
, c
, v
)},
5683 {"nZcV", B (n
, Z
, c
, V
)},
5684 {"nZCv", B (n
, Z
, C
, v
)},
5685 {"nZCV", B (n
, Z
, C
, V
)},
5686 {"Nzcv", B (N
, z
, c
, v
)},
5687 {"NzcV", B (N
, z
, c
, V
)},
5688 {"NzCv", B (N
, z
, C
, v
)},
5689 {"NzCV", B (N
, z
, C
, V
)},
5690 {"NZcv", B (N
, Z
, c
, v
)},
5691 {"NZcV", B (N
, Z
, c
, V
)},
5692 {"NZCv", B (N
, Z
, C
, v
)},
5693 {"NZCV", B (N
, Z
, C
, V
)}
5706 /* MD interface: bits in the object file. */
5708 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5709 for use in the a.out file, and stores them in the array pointed to by buf.
5710 This knows about the endian-ness of the target machine and does
5711 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5712 2 (short) and 4 (long) Floating numbers are put out as a series of
5713 LITTLENUMS (shorts, here at least). */
5716 md_number_to_chars (char *buf
, valueT val
, int n
)
5718 if (target_big_endian
)
5719 number_to_chars_bigendian (buf
, val
, n
);
5721 number_to_chars_littleendian (buf
, val
, n
);
5724 /* MD interface: Sections. */
5726 /* Estimate the size of a frag before relaxing. Assume everything fits in
5730 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
5736 /* Round up a section size to the appropriate boundary. */
5739 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5744 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5745 of an rs_align_code fragment. */
5748 aarch64_handle_align (fragS
* fragP
)
5750 /* NOP = d503201f */
5751 /* AArch64 instructions are always little-endian. */
5752 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5754 int bytes
, fix
, noop_size
;
5758 if (fragP
->fr_type
!= rs_align_code
)
5761 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5762 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
5765 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
5766 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
5769 gas_assert (fragP
->tc_frag_data
.recorded
);
5772 noop
= aarch64_noop
;
5773 noop_size
= sizeof (aarch64_noop
);
5774 fragP
->fr_var
= noop_size
;
5776 if (bytes
& (noop_size
- 1))
5778 fix
= bytes
& (noop_size
- 1);
5780 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
5787 while (bytes
>= noop_size
)
5789 memcpy (p
, noop
, noop_size
);
5795 fragP
->fr_fix
+= fix
;
5798 /* Called from md_do_align. Used to create an alignment
5799 frag in a code section. */
5802 aarch64_frag_align_code (int n
, int max
)
5806 /* We assume that there will never be a requirement
5807 to support alignments greater than x bytes. */
5808 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
5810 ("alignments greater than %d bytes not supported in .text sections"),
5811 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
5813 p
= frag_var (rs_align_code
,
5814 MAX_MEM_FOR_RS_ALIGN_CODE
,
5816 (relax_substateT
) max
,
5817 (symbolS
*) NULL
, (offsetT
) n
, (char *) NULL
);
5821 /* Perform target specific initialisation of a frag.
5822 Note - despite the name this initialisation is not done when the frag
5823 is created, but only when its type is assigned. A frag can be created
5824 and used a long time before its type is set, so beware of assuming that
5825 this initialisationis performed first. */
5829 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
5830 int max_chars ATTRIBUTE_UNUSED
)
5834 #else /* OBJ_ELF is defined. */
5836 aarch64_init_frag (fragS
* fragP
, int max_chars
)
5838 /* Record a mapping symbol for alignment frags. We will delete this
5839 later if the alignment ends up empty. */
5840 if (!fragP
->tc_frag_data
.recorded
)
5842 fragP
->tc_frag_data
.recorded
= 1;
5843 switch (fragP
->fr_type
)
5848 mapping_state_2 (MAP_DATA
, max_chars
);
5851 mapping_state_2 (MAP_INSN
, max_chars
);
5859 /* Initialize the DWARF-2 unwind information for this procedure. */
5862 tc_aarch64_frame_initial_instructions (void)
5864 cfi_add_CFA_def_cfa (REG_SP
, 0);
5866 #endif /* OBJ_ELF */
5868 /* Convert REGNAME to a DWARF-2 register number. */
5871 tc_aarch64_regname_to_dw2regnum (char *regname
)
5873 const reg_entry
*reg
= parse_reg (®name
);
5879 case REG_TYPE_SP_32
:
5880 case REG_TYPE_SP_64
:
5895 /* MD interface: Symbol and relocation handling. */
5897 /* Return the address within the segment that a PC-relative fixup is
5898 relative to. For AArch64 PC-relative fixups applied to instructions
5899 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
5902 md_pcrel_from_section (fixS
* fixP
, segT seg
)
5904 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5906 /* If this is pc-relative and we are going to emit a relocation
5907 then we just want to put out any pipeline compensation that the linker
5908 will need. Otherwise we want to use the calculated base. */
5910 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
5911 || aarch64_force_relocation (fixP
)))
5914 /* AArch64 should be consistent for all pc-relative relocations. */
5915 return base
+ AARCH64_PCREL_OFFSET
;
5918 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5919 Otherwise we have no need to default values of symbols. */
5922 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5925 if (name
[0] == '_' && name
[1] == 'G'
5926 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
5930 if (symbol_find (name
))
5931 as_bad (_("GOT already in the symbol table"));
5933 GOT_symbol
= symbol_new (name
, undefined_section
,
5934 (valueT
) 0, &zero_address_frag
);
5944 /* Return non-zero if the indicated VALUE has overflowed the maximum
5945 range expressible by a unsigned number with the indicated number of
5949 unsigned_overflow (valueT value
, unsigned bits
)
5952 if (bits
>= sizeof (valueT
) * 8)
5954 lim
= (valueT
) 1 << bits
;
5955 return (value
>= lim
);
5959 /* Return non-zero if the indicated VALUE has overflowed the maximum
5960 range expressible by an signed number with the indicated number of
5964 signed_overflow (offsetT value
, unsigned bits
)
5967 if (bits
>= sizeof (offsetT
) * 8)
5969 lim
= (offsetT
) 1 << (bits
- 1);
5970 return (value
< -lim
|| value
>= lim
);
5973 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
5974 unsigned immediate offset load/store instruction, try to encode it as
5975 an unscaled, 9-bit, signed immediate offset load/store instruction.
5976 Return TRUE if it is successful; otherwise return FALSE.
5978 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
5979 in response to the standard LDR/STR mnemonics when the immediate offset is
5980 unambiguous, i.e. when it is negative or unaligned. */
5983 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
5986 enum aarch64_op new_op
;
5987 const aarch64_opcode
*new_opcode
;
5989 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
5991 switch (instr
->opcode
->op
)
5993 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
5994 case OP_STRB_POS
: new_op
= OP_STURB
; break;
5995 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
5996 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
5997 case OP_STRH_POS
: new_op
= OP_STURH
; break;
5998 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
5999 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6000 case OP_STR_POS
: new_op
= OP_STUR
; break;
6001 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6002 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6003 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6004 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6005 default: new_op
= OP_NIL
; break;
6008 if (new_op
== OP_NIL
)
6011 new_opcode
= aarch64_get_opcode (new_op
);
6012 gas_assert (new_opcode
!= NULL
);
6014 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6015 instr
->opcode
->op
, new_opcode
->op
);
6017 aarch64_replace_opcode (instr
, new_opcode
);
6019 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6020 qualifier matching may fail because the out-of-date qualifier will
6021 prevent the operand being updated with a new and correct qualifier. */
6022 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6023 AARCH64_OPND_ADDR_SIMM9
);
6024 gas_assert (idx
== 1);
6025 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6027 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6029 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6035 /* Called by fix_insn to fix a MOV immediate alias instruction.
6037 Operand for a generic move immediate instruction, which is an alias
6038 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6039 a 32-bit/64-bit immediate value into general register. An assembler error
6040 shall result if the immediate cannot be created by a single one of these
6041 instructions. If there is a choice, then to ensure reversability an
6042 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6045 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6047 const aarch64_opcode
*opcode
;
6049 /* Need to check if the destination is SP/ZR. The check has to be done
6050 before any aarch64_replace_opcode. */
6051 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6052 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6054 instr
->operands
[1].imm
.value
= value
;
6055 instr
->operands
[1].skip
= 0;
6059 /* Try the MOVZ alias. */
6060 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6061 aarch64_replace_opcode (instr
, opcode
);
6062 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6063 &instr
->value
, NULL
, NULL
))
6065 put_aarch64_insn (buf
, instr
->value
);
6068 /* Try the MOVK alias. */
6069 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6070 aarch64_replace_opcode (instr
, opcode
);
6071 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6072 &instr
->value
, NULL
, NULL
))
6074 put_aarch64_insn (buf
, instr
->value
);
6079 if (try_mov_bitmask_p
)
6081 /* Try the ORR alias. */
6082 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6083 aarch64_replace_opcode (instr
, opcode
);
6084 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6085 &instr
->value
, NULL
, NULL
))
6087 put_aarch64_insn (buf
, instr
->value
);
6092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6093 _("immediate cannot be moved by a single instruction"));
6096 /* An instruction operand which is immediate related may have symbol used
6097 in the assembly, e.g.
6100 .set u32, 0x00ffff00
6102 At the time when the assembly instruction is parsed, a referenced symbol,
6103 like 'u32' in the above example may not have been seen; a fixS is created
6104 in such a case and is handled here after symbols have been resolved.
6105 Instruction is fixed up with VALUE using the information in *FIXP plus
6106 extra information in FLAGS.
6108 This function is called by md_apply_fix to fix up instructions that need
6109 a fix-up described above but does not involve any linker-time relocation. */
6112 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6116 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6117 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6118 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6122 /* Now the instruction is about to be fixed-up, so the operand that
6123 was previously marked as 'ignored' needs to be unmarked in order
6124 to get the encoding done properly. */
6125 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6126 new_inst
->operands
[idx
].skip
= 0;
6129 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6133 case AARCH64_OPND_EXCEPTION
:
6134 if (unsigned_overflow (value
, 16))
6135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6136 _("immediate out of range"));
6137 insn
= get_aarch64_insn (buf
);
6138 insn
|= encode_svc_imm (value
);
6139 put_aarch64_insn (buf
, insn
);
6142 case AARCH64_OPND_AIMM
:
6143 /* ADD or SUB with immediate.
6144 NOTE this assumes we come here with a add/sub shifted reg encoding
6145 3 322|2222|2 2 2 21111 111111
6146 1 098|7654|3 2 1 09876 543210 98765 43210
6147 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6148 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6149 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6150 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6152 3 322|2222|2 2 221111111111
6153 1 098|7654|3 2 109876543210 98765 43210
6154 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6155 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6156 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6157 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6158 Fields sf Rn Rd are already set. */
6159 insn
= get_aarch64_insn (buf
);
6163 insn
= reencode_addsub_switch_add_sub (insn
);
6167 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6168 && unsigned_overflow (value
, 12))
6170 /* Try to shift the value by 12 to make it fit. */
6171 if (((value
>> 12) << 12) == value
6172 && ! unsigned_overflow (value
, 12 + 12))
6175 insn
|= encode_addsub_imm_shift_amount (1);
6179 if (unsigned_overflow (value
, 12))
6180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6181 _("immediate out of range"));
6183 insn
|= encode_addsub_imm (value
);
6185 put_aarch64_insn (buf
, insn
);
6188 case AARCH64_OPND_SIMD_IMM
:
6189 case AARCH64_OPND_SIMD_IMM_SFT
:
6190 case AARCH64_OPND_LIMM
:
6191 /* Bit mask immediate. */
6192 gas_assert (new_inst
!= NULL
);
6193 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6194 new_inst
->operands
[idx
].imm
.value
= value
;
6195 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6196 &new_inst
->value
, NULL
, NULL
))
6197 put_aarch64_insn (buf
, new_inst
->value
);
6199 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6200 _("invalid immediate"));
6203 case AARCH64_OPND_HALF
:
6204 /* 16-bit unsigned immediate. */
6205 if (unsigned_overflow (value
, 16))
6206 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6207 _("immediate out of range"));
6208 insn
= get_aarch64_insn (buf
);
6209 insn
|= encode_movw_imm (value
& 0xffff);
6210 put_aarch64_insn (buf
, insn
);
6213 case AARCH64_OPND_IMM_MOV
:
6214 /* Operand for a generic move immediate instruction, which is
6215 an alias instruction that generates a single MOVZ, MOVN or ORR
6216 instruction to loads a 32-bit/64-bit immediate value into general
6217 register. An assembler error shall result if the immediate cannot be
6218 created by a single one of these instructions. If there is a choice,
6219 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6220 and MOVZ or MOVN to ORR. */
6221 gas_assert (new_inst
!= NULL
);
6222 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6225 case AARCH64_OPND_ADDR_SIMM7
:
6226 case AARCH64_OPND_ADDR_SIMM9
:
6227 case AARCH64_OPND_ADDR_SIMM9_2
:
6228 case AARCH64_OPND_ADDR_UIMM12
:
6229 /* Immediate offset in an address. */
6230 insn
= get_aarch64_insn (buf
);
6232 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6233 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6234 || new_inst
->opcode
->operands
[2] == opnd
);
6236 /* Get the index of the address operand. */
6237 if (new_inst
->opcode
->operands
[1] == opnd
)
6238 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6241 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6244 /* Update the resolved offset value. */
6245 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6247 /* Encode/fix-up. */
6248 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6249 &new_inst
->value
, NULL
, NULL
))
6251 put_aarch64_insn (buf
, new_inst
->value
);
6254 else if (new_inst
->opcode
->iclass
== ldst_pos
6255 && try_to_encode_as_unscaled_ldst (new_inst
))
6257 put_aarch64_insn (buf
, new_inst
->value
);
6261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6262 _("immediate offset out of range"));
6267 as_fatal (_("unhandled operand code %d"), opnd
);
6271 /* Apply a fixup (fixP) to segment data, once it has been determined
6272 by our caller that we have all the info we need to fix it up.
6274 Parameter valP is the pointer to the value of the bits. */
6277 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6279 offsetT value
= *valP
;
6281 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6283 unsigned flags
= fixP
->fx_addnumber
;
6285 DEBUG_TRACE ("\n\n");
6286 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6287 DEBUG_TRACE ("Enter md_apply_fix");
6289 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6291 /* Note whether this will delete the relocation. */
6293 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6296 /* Process the relocations. */
6297 switch (fixP
->fx_r_type
)
6299 case BFD_RELOC_NONE
:
6300 /* This will need to go in the object file. */
6305 case BFD_RELOC_8_PCREL
:
6306 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6307 md_number_to_chars (buf
, value
, 1);
6311 case BFD_RELOC_16_PCREL
:
6312 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6313 md_number_to_chars (buf
, value
, 2);
6317 case BFD_RELOC_32_PCREL
:
6318 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6319 md_number_to_chars (buf
, value
, 4);
6323 case BFD_RELOC_64_PCREL
:
6324 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6325 md_number_to_chars (buf
, value
, 8);
6328 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6329 /* We claim that these fixups have been processed here, even if
6330 in fact we generate an error because we do not have a reloc
6331 for them, so tc_gen_reloc() will reject them. */
6333 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6335 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6336 _("undefined symbol %s used as an immediate value"),
6337 S_GET_NAME (fixP
->fx_addsy
));
6338 goto apply_fix_return
;
6340 fix_insn (fixP
, flags
, value
);
6343 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6344 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6348 _("pc-relative load offset not word aligned"));
6349 if (signed_overflow (value
, 21))
6350 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6351 _("pc-relative load offset out of range"));
6352 insn
= get_aarch64_insn (buf
);
6353 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6354 put_aarch64_insn (buf
, insn
);
6358 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6359 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6361 if (signed_overflow (value
, 21))
6362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6363 _("pc-relative address offset out of range"));
6364 insn
= get_aarch64_insn (buf
);
6365 insn
|= encode_adr_imm (value
);
6366 put_aarch64_insn (buf
, insn
);
6370 case BFD_RELOC_AARCH64_BRANCH19
:
6371 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6374 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6375 _("conditional branch target not word aligned"));
6376 if (signed_overflow (value
, 21))
6377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6378 _("conditional branch out of range"));
6379 insn
= get_aarch64_insn (buf
);
6380 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6381 put_aarch64_insn (buf
, insn
);
6385 case BFD_RELOC_AARCH64_TSTBR14
:
6386 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6390 _("conditional branch target not word aligned"));
6391 if (signed_overflow (value
, 16))
6392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6393 _("conditional branch out of range"));
6394 insn
= get_aarch64_insn (buf
);
6395 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6396 put_aarch64_insn (buf
, insn
);
6400 case BFD_RELOC_AARCH64_JUMP26
:
6401 case BFD_RELOC_AARCH64_CALL26
:
6402 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6406 _("branch target not word aligned"));
6407 if (signed_overflow (value
, 28))
6408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6409 _("branch out of range"));
6410 insn
= get_aarch64_insn (buf
);
6411 insn
|= encode_branch_ofs_26 (value
>> 2);
6412 put_aarch64_insn (buf
, insn
);
6416 case BFD_RELOC_AARCH64_MOVW_G0
:
6417 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6418 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6421 case BFD_RELOC_AARCH64_MOVW_G1
:
6422 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6423 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6426 case BFD_RELOC_AARCH64_MOVW_G2
:
6427 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6428 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6431 case BFD_RELOC_AARCH64_MOVW_G3
:
6434 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6436 insn
= get_aarch64_insn (buf
);
6440 /* REL signed addend must fit in 16 bits */
6441 if (signed_overflow (value
, 16))
6442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6443 _("offset out of range"));
6447 /* Check for overflow and scale. */
6448 switch (fixP
->fx_r_type
)
6450 case BFD_RELOC_AARCH64_MOVW_G0
:
6451 case BFD_RELOC_AARCH64_MOVW_G1
:
6452 case BFD_RELOC_AARCH64_MOVW_G2
:
6453 case BFD_RELOC_AARCH64_MOVW_G3
:
6454 if (unsigned_overflow (value
, scale
+ 16))
6455 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6456 _("unsigned value out of range"));
6458 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6459 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6460 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6461 /* NOTE: We can only come here with movz or movn. */
6462 if (signed_overflow (value
, scale
+ 16))
6463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6464 _("signed value out of range"));
6467 /* Force use of MOVN. */
6469 insn
= reencode_movzn_to_movn (insn
);
6473 /* Force use of MOVZ. */
6474 insn
= reencode_movzn_to_movz (insn
);
6478 /* Unchecked relocations. */
6484 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6485 insn
|= encode_movw_imm (value
& 0xffff);
6487 put_aarch64_insn (buf
, insn
);
6491 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6492 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6493 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6494 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6495 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6496 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6497 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6498 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6499 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6500 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6501 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6502 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6503 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
:
6504 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6505 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6506 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6507 /* Should always be exported to object file, see
6508 aarch64_force_relocation(). */
6509 gas_assert (!fixP
->fx_done
);
6510 gas_assert (seg
->use_rela_p
);
6513 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6514 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6515 case BFD_RELOC_AARCH64_ADD_LO12
:
6516 case BFD_RELOC_AARCH64_LDST8_LO12
:
6517 case BFD_RELOC_AARCH64_LDST16_LO12
:
6518 case BFD_RELOC_AARCH64_LDST32_LO12
:
6519 case BFD_RELOC_AARCH64_LDST64_LO12
:
6520 case BFD_RELOC_AARCH64_LDST128_LO12
:
6521 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6522 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6523 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6524 /* Should always be exported to object file, see
6525 aarch64_force_relocation(). */
6526 gas_assert (!fixP
->fx_done
);
6527 gas_assert (seg
->use_rela_p
);
6530 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6531 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6532 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6537 _("unexpected %s fixup"),
6538 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6543 /* Free the allocated the struct aarch64_inst.
6544 N.B. currently there are very limited number of fix-up types actually use
6545 this field, so the impact on the performance should be minimal . */
6546 if (fixP
->tc_fix_data
.inst
!= NULL
)
6547 free (fixP
->tc_fix_data
.inst
);
6552 /* Translate internal representation of relocation info to BFD target
6556 tc_gen_reloc (asection
* section
, fixS
* fixp
)
6559 bfd_reloc_code_real_type code
;
6561 reloc
= xmalloc (sizeof (arelent
));
6563 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
6564 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6565 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6569 if (section
->use_rela_p
)
6570 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
6572 fixp
->fx_offset
= reloc
->address
;
6574 reloc
->addend
= fixp
->fx_offset
;
6576 code
= fixp
->fx_r_type
;
6581 code
= BFD_RELOC_16_PCREL
;
6586 code
= BFD_RELOC_32_PCREL
;
6591 code
= BFD_RELOC_64_PCREL
;
6598 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6599 if (reloc
->howto
== NULL
)
6601 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6603 ("cannot represent %s relocation in this object file format"),
6604 bfd_get_reloc_code_name (code
));
6611 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6614 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
6616 bfd_reloc_code_real_type type
;
6620 FIXME: @@ Should look at CPU word size. */
6627 type
= BFD_RELOC_16
;
6630 type
= BFD_RELOC_32
;
6633 type
= BFD_RELOC_64
;
6636 as_bad (_("cannot do %u-byte relocation"), size
);
6637 type
= BFD_RELOC_UNUSED
;
6641 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6645 aarch64_force_relocation (struct fix
*fixp
)
6647 switch (fixp
->fx_r_type
)
6649 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6650 /* Perform these "immediate" internal relocations
6651 even if the symbol is extern or weak. */
6654 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6655 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6656 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6657 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6658 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6659 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6660 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6661 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6662 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6663 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6664 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6665 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6666 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
:
6667 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6668 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6669 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6670 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6671 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6672 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6673 case BFD_RELOC_AARCH64_ADD_LO12
:
6674 case BFD_RELOC_AARCH64_LDST8_LO12
:
6675 case BFD_RELOC_AARCH64_LDST16_LO12
:
6676 case BFD_RELOC_AARCH64_LDST32_LO12
:
6677 case BFD_RELOC_AARCH64_LDST64_LO12
:
6678 case BFD_RELOC_AARCH64_LDST128_LO12
:
6679 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6680 /* Always leave these relocations for the linker. */
6687 return generic_force_reloc (fixp
);
6693 elf64_aarch64_target_format (void)
6695 if (target_big_endian
)
6696 return "elf64-bigaarch64";
6698 return "elf64-littleaarch64";
6702 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
6704 elf_frob_symbol (symp
, puntp
);
6708 /* MD interface: Finalization. */
6710 /* A good place to do this, although this was probably not intended
6711 for this kind of use. We need to dump the literal pool before
6712 references are made to a null symbol pointer. */
6715 aarch64_cleanup (void)
6719 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
6721 /* Put it at the end of the relevant section. */
6722 subseg_set (pool
->section
, pool
->sub_section
);
6728 /* Remove any excess mapping symbols generated for alignment frags in
6729 SEC. We may have created a mapping symbol before a zero byte
6730 alignment; remove it if there's a mapping symbol after the
6733 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
6734 void *dummy ATTRIBUTE_UNUSED
)
6736 segment_info_type
*seginfo
= seg_info (sec
);
6739 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
6742 for (fragp
= seginfo
->frchainP
->frch_root
;
6743 fragp
!= NULL
; fragp
= fragp
->fr_next
)
6745 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
6746 fragS
*next
= fragp
->fr_next
;
6748 /* Variable-sized frags have been converted to fixed size by
6749 this point. But if this was variable-sized to start with,
6750 there will be a fixed-size frag after it. So don't handle
6752 if (sym
== NULL
|| next
== NULL
)
6755 if (S_GET_VALUE (sym
) < next
->fr_address
)
6756 /* Not at the end of this frag. */
6758 know (S_GET_VALUE (sym
) == next
->fr_address
);
6762 if (next
->tc_frag_data
.first_map
!= NULL
)
6764 /* Next frag starts with a mapping symbol. Discard this
6766 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
6770 if (next
->fr_next
== NULL
)
6772 /* This mapping symbol is at the end of the section. Discard
6774 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
6775 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
6779 /* As long as we have empty frags without any mapping symbols,
6781 /* If the next frag is non-empty and does not start with a
6782 mapping symbol, then this mapping symbol is required. */
6783 if (next
->fr_address
!= next
->fr_next
->fr_address
)
6786 next
= next
->fr_next
;
6788 while (next
!= NULL
);
6793 /* Adjust the symbol table. */
6796 aarch64_adjust_symtab (void)
6799 /* Remove any overlapping mapping symbols generated by alignment frags. */
6800 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
6801 /* Now do generic ELF adjustments. */
6802 elf_adjust_symtab ();
6807 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
6809 const char *hash_err
;
6811 hash_err
= hash_insert (table
, key
, value
);
6813 printf ("Internal Error: Can't hash %s\n", key
);
6817 fill_instruction_hash_table (void)
6819 aarch64_opcode
*opcode
= aarch64_opcode_table
;
6821 while (opcode
->name
!= NULL
)
6823 templates
*templ
, *new_templ
;
6824 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
6826 new_templ
= (templates
*) xmalloc (sizeof (templates
));
6827 new_templ
->opcode
= opcode
;
6828 new_templ
->next
= NULL
;
6831 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
6834 new_templ
->next
= templ
->next
;
6835 templ
->next
= new_templ
;
6842 convert_to_upper (char *dst
, const char *src
, size_t num
)
6845 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
6846 *dst
= TOUPPER (*src
);
6850 /* Assume STR point to a lower-case string, allocate, convert and return
6851 the corresponding upper-case string. */
6852 static inline const char*
6853 get_upper_str (const char *str
)
6856 size_t len
= strlen (str
);
6857 if ((ret
= xmalloc (len
+ 1)) == NULL
)
6859 convert_to_upper (ret
, str
, len
);
6863 /* MD interface: Initialization. */
6871 if ((aarch64_ops_hsh
= hash_new ()) == NULL
6872 || (aarch64_cond_hsh
= hash_new ()) == NULL
6873 || (aarch64_shift_hsh
= hash_new ()) == NULL
6874 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
6875 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
6876 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
6877 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
6878 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
6879 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
6880 || (aarch64_reg_hsh
= hash_new ()) == NULL
6881 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
6882 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
6883 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
6884 as_fatal (_("virtual memory exhausted"));
6886 fill_instruction_hash_table ();
6888 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
6889 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
6890 (void *) (aarch64_sys_regs
+ i
));
6892 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
6893 checked_hash_insert (aarch64_pstatefield_hsh
,
6894 aarch64_pstatefields
[i
].name
,
6895 (void *) (aarch64_pstatefields
+ i
));
6897 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
6898 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
6899 aarch64_sys_regs_ic
[i
].template,
6900 (void *) (aarch64_sys_regs_ic
+ i
));
6902 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
6903 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
6904 aarch64_sys_regs_dc
[i
].template,
6905 (void *) (aarch64_sys_regs_dc
+ i
));
6907 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
6908 checked_hash_insert (aarch64_sys_regs_at_hsh
,
6909 aarch64_sys_regs_at
[i
].template,
6910 (void *) (aarch64_sys_regs_at
+ i
));
6912 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
6913 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
6914 aarch64_sys_regs_tlbi
[i
].template,
6915 (void *) (aarch64_sys_regs_tlbi
+ i
));
6917 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
6918 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
6919 (void *) (reg_names
+ i
));
6921 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
6922 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
6923 (void *) (nzcv_names
+ i
));
6925 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
6927 const char *name
= aarch64_operand_modifiers
[i
].name
;
6928 checked_hash_insert (aarch64_shift_hsh
, name
,
6929 (void *) (aarch64_operand_modifiers
+ i
));
6930 /* Also hash the name in the upper case. */
6931 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
6932 (void *) (aarch64_operand_modifiers
+ i
));
6935 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
6938 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
6939 the same condition code. */
6940 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
6942 const char *name
= aarch64_conds
[i
].names
[j
];
6945 checked_hash_insert (aarch64_cond_hsh
, name
,
6946 (void *) (aarch64_conds
+ i
));
6947 /* Also hash the name in the upper case. */
6948 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
6949 (void *) (aarch64_conds
+ i
));
6953 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
6955 const char *name
= aarch64_barrier_options
[i
].name
;
6956 /* Skip xx00 - the unallocated values of option. */
6959 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
6960 (void *) (aarch64_barrier_options
+ i
));
6961 /* Also hash the name in the upper case. */
6962 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
6963 (void *) (aarch64_barrier_options
+ i
));
6966 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
6968 const char* name
= aarch64_prfops
[i
].name
;
6969 /* Skip the unallocated hint encodings. */
6972 checked_hash_insert (aarch64_pldop_hsh
, name
,
6973 (void *) (aarch64_prfops
+ i
));
6974 /* Also hash the name in the upper case. */
6975 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
6976 (void *) (aarch64_prfops
+ i
));
6979 /* Set the cpu variant based on the command-line options. */
6981 mcpu_cpu_opt
= march_cpu_opt
;
6984 mcpu_cpu_opt
= &cpu_default
;
6986 cpu_variant
= *mcpu_cpu_opt
;
6988 /* Record the CPU type. */
6989 mach
= bfd_mach_aarch64
;
6991 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
6994 /* Command line processing. */
6996 const char *md_shortopts
= "m:";
6998 #ifdef AARCH64_BI_ENDIAN
6999 #define OPTION_EB (OPTION_MD_BASE + 0)
7000 #define OPTION_EL (OPTION_MD_BASE + 1)
7002 #if TARGET_BYTES_BIG_ENDIAN
7003 #define OPTION_EB (OPTION_MD_BASE + 0)
7005 #define OPTION_EL (OPTION_MD_BASE + 1)
7009 struct option md_longopts
[] = {
7011 {"EB", no_argument
, NULL
, OPTION_EB
},
7014 {"EL", no_argument
, NULL
, OPTION_EL
},
7016 {NULL
, no_argument
, NULL
, 0}
7019 size_t md_longopts_size
= sizeof (md_longopts
);
7021 struct aarch64_option_table
7023 char *option
; /* Option name to match. */
7024 char *help
; /* Help information. */
7025 int *var
; /* Variable to change. */
7026 int value
; /* What to change it to. */
7027 char *deprecated
; /* If non-null, print this message. */
7030 static struct aarch64_option_table aarch64_opts
[] = {
7031 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7032 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7034 #ifdef DEBUG_AARCH64
7035 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7036 #endif /* DEBUG_AARCH64 */
7037 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7039 {NULL
, NULL
, NULL
, 0, NULL
}
7042 struct aarch64_cpu_option_table
7045 const aarch64_feature_set value
;
7046 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7048 const char *canonical_name
;
7051 /* This list should, at a minimum, contain all the cpu names
7052 recognized by GCC. */
7053 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7054 {"all", AARCH64_ANY
, NULL
},
7055 {"cortex-a53", AARCH64_ARCH_V8
, "Cortex-A53"},
7056 {"cortex-a57", AARCH64_ARCH_V8
, "Cortex-A57"},
7057 {"generic", AARCH64_ARCH_V8
, NULL
},
7059 /* These two are example CPUs supported in GCC, once we have real
7060 CPUs they will be removed. */
7061 {"example-1", AARCH64_ARCH_V8
, NULL
},
7062 {"example-2", AARCH64_ARCH_V8
, NULL
},
7064 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7067 struct aarch64_arch_option_table
7070 const aarch64_feature_set value
;
7073 /* This list should, at a minimum, contain all the architecture names
7074 recognized by GCC. */
7075 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7076 {"all", AARCH64_ANY
},
7077 {"armv8-a", AARCH64_ARCH_V8
},
7078 {NULL
, AARCH64_ARCH_NONE
}
7081 /* ISA extensions. */
7082 struct aarch64_option_cpu_value_table
7085 const aarch64_feature_set value
;
7088 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7089 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7090 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7091 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7092 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7093 {NULL
, AARCH64_ARCH_NONE
}
7096 struct aarch64_long_option_table
7098 char *option
; /* Substring to match. */
7099 char *help
; /* Help information. */
7100 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7101 char *deprecated
; /* If non-null, print this message. */
7105 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
)
7107 /* We insist on extensions being added before being removed. We achieve
7108 this by using the ADDING_VALUE variable to indicate whether we are
7109 adding an extension (1) or removing it (0) and only allowing it to
7110 change in the order -1 -> 1 -> 0. */
7111 int adding_value
= -1;
7112 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7114 /* Copy the feature set, so that we can modify it. */
7118 while (str
!= NULL
&& *str
!= 0)
7120 const struct aarch64_option_cpu_value_table
*opt
;
7126 as_bad (_("invalid architectural extension"));
7131 ext
= strchr (str
, '+');
7136 optlen
= strlen (str
);
7138 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7140 if (adding_value
!= 0)
7145 else if (optlen
> 0)
7147 if (adding_value
== -1)
7149 else if (adding_value
!= 1)
7151 as_bad (_("must specify extensions to add before specifying "
7152 "those to remove"));
7159 as_bad (_("missing architectural extension"));
7163 gas_assert (adding_value
!= -1);
7165 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7166 if (strncmp (opt
->name
, str
, optlen
) == 0)
7168 /* Add or remove the extension. */
7170 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7172 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7176 if (opt
->name
== NULL
)
7178 as_bad (_("unknown architectural extension `%s'"), str
);
7189 aarch64_parse_cpu (char *str
)
7191 const struct aarch64_cpu_option_table
*opt
;
7192 char *ext
= strchr (str
, '+');
7198 optlen
= strlen (str
);
7202 as_bad (_("missing cpu name `%s'"), str
);
7206 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7207 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7209 mcpu_cpu_opt
= &opt
->value
;
7211 return aarch64_parse_features (ext
, &mcpu_cpu_opt
);
7216 as_bad (_("unknown cpu `%s'"), str
);
7221 aarch64_parse_arch (char *str
)
7223 const struct aarch64_arch_option_table
*opt
;
7224 char *ext
= strchr (str
, '+');
7230 optlen
= strlen (str
);
7234 as_bad (_("missing architecture name `%s'"), str
);
7238 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7239 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7241 march_cpu_opt
= &opt
->value
;
7243 return aarch64_parse_features (ext
, &march_cpu_opt
);
7248 as_bad (_("unknown architecture `%s'\n"), str
);
7252 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7253 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7254 aarch64_parse_cpu
, NULL
},
7255 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7256 aarch64_parse_arch
, NULL
},
7257 {NULL
, NULL
, 0, NULL
}
7261 md_parse_option (int c
, char *arg
)
7263 struct aarch64_option_table
*opt
;
7264 struct aarch64_long_option_table
*lopt
;
7270 target_big_endian
= 1;
7276 target_big_endian
= 0;
7281 /* Listing option. Just ignore these, we don't support additional
7286 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7288 if (c
== opt
->option
[0]
7289 && ((arg
== NULL
&& opt
->option
[1] == 0)
7290 || streq (arg
, opt
->option
+ 1)))
7292 /* If the option is deprecated, tell the user. */
7293 if (opt
->deprecated
!= NULL
)
7294 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7295 arg
? arg
: "", _(opt
->deprecated
));
7297 if (opt
->var
!= NULL
)
7298 *opt
->var
= opt
->value
;
7304 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7306 /* These options are expected to have an argument. */
7307 if (c
== lopt
->option
[0]
7309 && strncmp (arg
, lopt
->option
+ 1,
7310 strlen (lopt
->option
+ 1)) == 0)
7312 /* If the option is deprecated, tell the user. */
7313 if (lopt
->deprecated
!= NULL
)
7314 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7315 _(lopt
->deprecated
));
7317 /* Call the sup-option parser. */
7318 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7329 md_show_usage (FILE * fp
)
7331 struct aarch64_option_table
*opt
;
7332 struct aarch64_long_option_table
*lopt
;
7334 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7336 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7337 if (opt
->help
!= NULL
)
7338 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7340 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7341 if (lopt
->help
!= NULL
)
7342 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7346 -EB assemble code for a big-endian cpu\n"));
7351 -EL assemble code for a little-endian cpu\n"));
7355 /* Parse a .cpu directive. */
7358 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7360 const struct aarch64_cpu_option_table
*opt
;
7366 name
= input_line_pointer
;
7367 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7368 input_line_pointer
++;
7369 saved_char
= *input_line_pointer
;
7370 *input_line_pointer
= 0;
7372 ext
= strchr (name
, '+');
7375 optlen
= ext
- name
;
7377 optlen
= strlen (name
);
7379 /* Skip the first "all" entry. */
7380 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7381 if (strlen (opt
->name
) == optlen
7382 && strncmp (name
, opt
->name
, optlen
) == 0)
7384 mcpu_cpu_opt
= &opt
->value
;
7386 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
))
7389 cpu_variant
= *mcpu_cpu_opt
;
7391 *input_line_pointer
= saved_char
;
7392 demand_empty_rest_of_line ();
7395 as_bad (_("unknown cpu `%s'"), name
);
7396 *input_line_pointer
= saved_char
;
7397 ignore_rest_of_line ();
7401 /* Parse a .arch directive. */
7404 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7406 const struct aarch64_arch_option_table
*opt
;
7412 name
= input_line_pointer
;
7413 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7414 input_line_pointer
++;
7415 saved_char
= *input_line_pointer
;
7416 *input_line_pointer
= 0;
7418 ext
= strchr (name
, '+');
7421 optlen
= ext
- name
;
7423 optlen
= strlen (name
);
7425 /* Skip the first "all" entry. */
7426 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7427 if (strlen (opt
->name
) == optlen
7428 && strncmp (name
, opt
->name
, optlen
) == 0)
7430 mcpu_cpu_opt
= &opt
->value
;
7432 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
))
7435 cpu_variant
= *mcpu_cpu_opt
;
7437 *input_line_pointer
= saved_char
;
7438 demand_empty_rest_of_line ();
7442 as_bad (_("unknown architecture `%s'\n"), name
);
7443 *input_line_pointer
= saved_char
;
7444 ignore_rest_of_line ();
7447 /* Copy symbol information. */
7450 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
7452 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);