1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
258 const char *template;
265 bfd_reloc_code_real_type reloc
;
268 /* Macros to define the register types and masks for the purpose
271 #undef AARCH64_REG_TYPES
272 #define AARCH64_REG_TYPES \
273 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
274 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
275 BASIC_REG_TYPE(SP_32) /* wsp */ \
276 BASIC_REG_TYPE(SP_64) /* sp */ \
277 BASIC_REG_TYPE(Z_32) /* wzr */ \
278 BASIC_REG_TYPE(Z_64) /* xzr */ \
279 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
280 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
281 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
282 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
283 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
284 BASIC_REG_TYPE(VN) /* v[0-31] */ \
285 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
286 BASIC_REG_TYPE(PN) /* p[0-15] */ \
287 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
288 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
292 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
293 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Typecheck: same, plus SVE registers. */ \
296 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
299 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
300 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
301 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
302 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
306 /* Typecheck: any [BHSDQ]P FP. */ \
307 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
308 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
309 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
310 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
312 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
313 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
314 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
315 be used for SVE instructions, since Zn and Pn are valid symbols \
316 in other contexts. */ \
317 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
320 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
321 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
322 | REG_TYPE(ZN) | REG_TYPE(PN)) \
323 /* Any integer register; used for error messages only. */ \
324 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
325 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
326 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
327 /* Pseudo type to mark the end of the enumerator sequence. */ \
330 #undef BASIC_REG_TYPE
331 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
332 #undef MULTI_REG_TYPE
333 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
335 /* Register type enumerators. */
336 typedef enum aarch64_reg_type_
338 /* A list of REG_TYPE_*. */
342 #undef BASIC_REG_TYPE
343 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
345 #define REG_TYPE(T) (1 << REG_TYPE_##T)
346 #undef MULTI_REG_TYPE
347 #define MULTI_REG_TYPE(T,V) V,
349 /* Structure for a hash table entry for a register. */
353 unsigned char number
;
354 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
355 unsigned char builtin
;
358 /* Values indexed by aarch64_reg_type to assist the type checking. */
359 static const unsigned reg_type_masks
[] =
364 #undef BASIC_REG_TYPE
366 #undef MULTI_REG_TYPE
367 #undef AARCH64_REG_TYPES
369 /* Diagnostics used when we don't get a register of the expected type.
370 Note: this has to synchronized with aarch64_reg_type definitions
373 get_reg_expected_msg (aarch64_reg_type reg_type
)
380 msg
= N_("integer 32-bit register expected");
383 msg
= N_("integer 64-bit register expected");
386 msg
= N_("integer register expected");
388 case REG_TYPE_R64_SP
:
389 msg
= N_("64-bit integer or SP register expected");
391 case REG_TYPE_SVE_BASE
:
392 msg
= N_("base register expected");
395 msg
= N_("integer or zero register expected");
397 case REG_TYPE_SVE_OFFSET
:
398 msg
= N_("offset register expected");
401 msg
= N_("integer or SP register expected");
403 case REG_TYPE_R_Z_SP
:
404 msg
= N_("integer, zero or SP register expected");
407 msg
= N_("8-bit SIMD scalar register expected");
410 msg
= N_("16-bit SIMD scalar or floating-point half precision "
411 "register expected");
414 msg
= N_("32-bit SIMD scalar or floating-point single precision "
415 "register expected");
418 msg
= N_("64-bit SIMD scalar or floating-point double precision "
419 "register expected");
422 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
423 "register expected");
425 case REG_TYPE_R_Z_BHSDQ_V
:
426 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
427 msg
= N_("register expected");
429 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
430 msg
= N_("SIMD scalar or floating-point register expected");
432 case REG_TYPE_VN
: /* any V reg */
433 msg
= N_("vector register expected");
436 msg
= N_("SVE vector register expected");
439 msg
= N_("SVE predicate register expected");
442 as_fatal (_("invalid register type %d"), reg_type
);
447 /* Some well known registers that we refer to directly elsewhere. */
451 /* Instructions take 4 bytes in the object file. */
454 static htab_t aarch64_ops_hsh
;
455 static htab_t aarch64_cond_hsh
;
456 static htab_t aarch64_shift_hsh
;
457 static htab_t aarch64_sys_regs_hsh
;
458 static htab_t aarch64_pstatefield_hsh
;
459 static htab_t aarch64_sys_regs_ic_hsh
;
460 static htab_t aarch64_sys_regs_dc_hsh
;
461 static htab_t aarch64_sys_regs_at_hsh
;
462 static htab_t aarch64_sys_regs_tlbi_hsh
;
463 static htab_t aarch64_sys_regs_sr_hsh
;
464 static htab_t aarch64_reg_hsh
;
465 static htab_t aarch64_barrier_opt_hsh
;
466 static htab_t aarch64_nzcv_hsh
;
467 static htab_t aarch64_pldop_hsh
;
468 static htab_t aarch64_hint_opt_hsh
;
470 /* Stuff needed to resolve the label ambiguity
479 static symbolS
*last_label_seen
;
481 /* Literal pool structure. Held on a per-section
482 and per-sub-section basis. */
484 #define MAX_LITERAL_POOL_SIZE 1024
485 typedef struct literal_expression
488 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
489 LITTLENUM_TYPE
* bignum
;
490 } literal_expression
;
492 typedef struct literal_pool
494 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
495 unsigned int next_free_entry
;
501 struct literal_pool
*next
;
504 /* Pointer to a linked list of literal pools. */
505 static literal_pool
*list_of_pools
= NULL
;
509 /* This array holds the chars that always start a comment. If the
510 pre-processor is disabled, these aren't very useful. */
511 const char comment_chars
[] = "";
513 /* This array holds the chars that only start a comment at the beginning of
514 a line. If the line seems to have the form '# 123 filename'
515 .line and .file directives will appear in the pre-processed output. */
516 /* Note that input_file.c hand checks for '#' at the beginning of the
517 first line of the input file. This is because the compiler outputs
518 #NO_APP at the beginning of its output. */
519 /* Also note that comments like this one will always work. */
520 const char line_comment_chars
[] = "#";
522 const char line_separator_chars
[] = ";";
524 /* Chars that can be used to separate mant
525 from exp in floating point numbers. */
526 const char EXP_CHARS
[] = "eE";
528 /* Chars that mean this number is a floating point constant. */
532 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
534 /* Prefix character that indicates the start of an immediate value. */
535 #define is_immediate_prefix(C) ((C) == '#')
537 /* Separator character handling. */
539 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
541 static inline bfd_boolean
542 skip_past_char (char **str
, char c
)
553 #define skip_past_comma(str) skip_past_char (str, ',')
555 /* Arithmetic expressions (possibly involving symbols). */
557 static bfd_boolean in_my_get_expression_p
= FALSE
;
559 /* Third argument to my_get_expression. */
560 #define GE_NO_PREFIX 0
561 #define GE_OPT_PREFIX 1
563 /* Return TRUE if the string pointed by *STR is successfully parsed
564 as an valid expression; *EP will be filled with the information of
565 such an expression. Otherwise return FALSE. */
568 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
573 int prefix_present_p
= 0;
580 if (is_immediate_prefix (**str
))
583 prefix_present_p
= 1;
590 memset (ep
, 0, sizeof (expressionS
));
592 save_in
= input_line_pointer
;
593 input_line_pointer
= *str
;
594 in_my_get_expression_p
= TRUE
;
595 seg
= expression (ep
);
596 in_my_get_expression_p
= FALSE
;
598 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
600 /* We found a bad expression in md_operand(). */
601 *str
= input_line_pointer
;
602 input_line_pointer
= save_in
;
603 if (prefix_present_p
&& ! error_p ())
604 set_fatal_syntax_error (_("bad expression"));
606 set_first_syntax_error (_("bad expression"));
611 if (seg
!= absolute_section
612 && seg
!= text_section
613 && seg
!= data_section
614 && seg
!= bss_section
&& seg
!= undefined_section
)
616 set_syntax_error (_("bad segment"));
617 *str
= input_line_pointer
;
618 input_line_pointer
= save_in
;
625 *str
= input_line_pointer
;
626 input_line_pointer
= save_in
;
630 /* Turn a string in input_line_pointer into a floating point constant
631 of type TYPE, and store the appropriate bytes in *LITP. The number
632 of LITTLENUMS emitted is stored in *SIZEP. An error message is
633 returned, or NULL on OK. */
636 md_atof (int type
, char *litP
, int *sizeP
)
638 /* If this is a bfloat16 type, then parse it slightly differently -
639 as it does not follow the IEEE standard exactly. */
643 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
644 FLONUM_TYPE generic_float
;
646 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
649 input_line_pointer
= t
;
651 return _("invalid floating point number");
653 switch (generic_float
.sign
)
666 /* bfloat16 has two types of NaN - quiet and signalling.
667 Quiet NaN has bit[6] == 1 && faction != 0, whereas
668 signalling Nan's have bit[0] == 0 && fraction != 0.
669 Chose this specific encoding as it is the same form
670 as used by other IEEE 754 encodings in GAS. */
681 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
686 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
689 /* We handle all bad expressions here, so that we can report the faulty
690 instruction in the error message. */
692 md_operand (expressionS
* exp
)
694 if (in_my_get_expression_p
)
695 exp
->X_op
= O_illegal
;
698 /* Immediate values. */
700 /* Errors may be set multiple times during parsing or bit encoding
701 (particularly in the Neon bits), but usually the earliest error which is set
702 will be the most meaningful. Avoid overwriting it with later (cascading)
703 errors by calling this function. */
706 first_error (const char *error
)
709 set_syntax_error (error
);
712 /* Similar to first_error, but this function accepts formatted error
715 first_error_fmt (const char *format
, ...)
720 /* N.B. this single buffer will not cause error messages for different
721 instructions to pollute each other; this is because at the end of
722 processing of each assembly line, error message if any will be
723 collected by as_bad. */
724 static char buffer
[size
];
728 int ret ATTRIBUTE_UNUSED
;
729 va_start (args
, format
);
730 ret
= vsnprintf (buffer
, size
, format
, args
);
731 know (ret
<= size
- 1 && ret
>= 0);
733 set_syntax_error (buffer
);
737 /* Register parsing. */
739 /* Generic register parser which is called by other specialized
741 CCP points to what should be the beginning of a register name.
742 If it is indeed a valid register name, advance CCP over it and
743 return the reg_entry structure; otherwise return NULL.
744 It does not issue diagnostics. */
747 parse_reg (char **ccp
)
753 #ifdef REGISTER_PREFIX
754 if (*start
!= REGISTER_PREFIX
)
760 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
765 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
767 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
776 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
779 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
781 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
784 /* Try to parse a base or offset register. Allow SVE base and offset
785 registers if REG_TYPE includes SVE registers. Return the register
786 entry on success, setting *QUALIFIER to the register qualifier.
787 Return null otherwise.
789 Note that this function does not issue any diagnostics. */
791 static const reg_entry
*
792 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
793 aarch64_opnd_qualifier_t
*qualifier
)
796 const reg_entry
*reg
= parse_reg (&str
);
806 *qualifier
= AARCH64_OPND_QLF_W
;
812 *qualifier
= AARCH64_OPND_QLF_X
;
816 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
819 switch (TOLOWER (str
[1]))
822 *qualifier
= AARCH64_OPND_QLF_S_S
;
825 *qualifier
= AARCH64_OPND_QLF_S_D
;
842 /* Try to parse a base or offset register. Return the register entry
843 on success, setting *QUALIFIER to the register qualifier. Return null
846 Note that this function does not issue any diagnostics. */
848 static const reg_entry
*
849 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
851 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
854 /* Parse the qualifier of a vector register or vector element of type
855 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
856 succeeds; otherwise return FALSE.
858 Accept only one occurrence of:
859 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
862 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
863 struct vector_type_el
*parsed_type
, char **str
)
867 unsigned element_size
;
868 enum vector_el_type type
;
871 gas_assert (*ptr
== '.');
874 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
879 width
= strtoul (ptr
, &ptr
, 10);
880 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
882 first_error_fmt (_("bad size %d in vector width specifier"), width
);
887 switch (TOLOWER (*ptr
))
906 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
915 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
917 first_error (_("missing element size"));
920 if (width
!= 0 && width
* element_size
!= 64
921 && width
* element_size
!= 128
922 && !(width
== 2 && element_size
== 16)
923 && !(width
== 4 && element_size
== 8))
926 ("invalid element size %d and vector size combination %c"),
932 parsed_type
->type
= type
;
933 parsed_type
->width
= width
;
940 /* *STR contains an SVE zero/merge predication suffix. Parse it into
941 *PARSED_TYPE and point *STR at the end of the suffix. */
944 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
949 gas_assert (*ptr
== '/');
951 switch (TOLOWER (*ptr
))
954 parsed_type
->type
= NT_zero
;
957 parsed_type
->type
= NT_merge
;
960 if (*ptr
!= '\0' && *ptr
!= ',')
961 first_error_fmt (_("unexpected character `%c' in predication type"),
964 first_error (_("missing predication type"));
967 parsed_type
->width
= 0;
972 /* Parse a register of the type TYPE.
974 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
975 name or the parsed register is not of TYPE.
977 Otherwise return the register number, and optionally fill in the actual
978 type of the register in *RTYPE when multiple alternatives were given, and
979 return the register shape and element index information in *TYPEINFO.
981 IN_REG_LIST should be set with TRUE if the caller is parsing a register
985 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
986 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
989 const reg_entry
*reg
= parse_reg (&str
);
990 struct vector_type_el atype
;
991 struct vector_type_el parsetype
;
992 bfd_boolean is_typed_vecreg
= FALSE
;
995 atype
.type
= NT_invtype
;
1003 set_default_error ();
1007 if (! aarch64_check_reg_type (reg
, type
))
1009 DEBUG_TRACE ("reg type check failed");
1010 set_default_error ();
1015 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1016 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
1020 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1025 if (!parse_predication_for_operand (&parsetype
, &str
))
1029 /* Register if of the form Vn.[bhsdq]. */
1030 is_typed_vecreg
= TRUE
;
1032 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1034 /* The width is always variable; we don't allow an integer width
1036 gas_assert (parsetype
.width
== 0);
1037 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1039 else if (parsetype
.width
== 0)
1040 /* Expect index. In the new scheme we cannot have
1041 Vn.[bhsdq] represent a scalar. Therefore any
1042 Vn.[bhsdq] should have an index following it.
1043 Except in reglists of course. */
1044 atype
.defined
|= NTA_HASINDEX
;
1046 atype
.defined
|= NTA_HASTYPE
;
1048 atype
.type
= parsetype
.type
;
1049 atype
.width
= parsetype
.width
;
1052 if (skip_past_char (&str
, '['))
1056 /* Reject Sn[index] syntax. */
1057 if (!is_typed_vecreg
)
1059 first_error (_("this type of register can't be indexed"));
1065 first_error (_("index not allowed inside register list"));
1069 atype
.defined
|= NTA_HASINDEX
;
1071 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1073 if (exp
.X_op
!= O_constant
)
1075 first_error (_("constant expression required"));
1079 if (! skip_past_char (&str
, ']'))
1082 atype
.index
= exp
.X_add_number
;
1084 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1086 /* Indexed vector register expected. */
1087 first_error (_("indexed vector register expected"));
1091 /* A vector reg Vn should be typed or indexed. */
1092 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1094 first_error (_("invalid use of vector register"));
1110 Return the register number on success; return PARSE_FAIL otherwise.
1112 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1113 the register (e.g. NEON double or quad reg when either has been requested).
1115 If this is a NEON vector register with additional type information, fill
1116 in the struct pointed to by VECTYPE (if non-NULL).
1118 This parser does not handle register list. */
1121 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1122 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1124 struct vector_type_el atype
;
1126 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1127 /*in_reg_list= */ FALSE
);
1129 if (reg
== PARSE_FAIL
)
1140 static inline bfd_boolean
1141 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1145 && e1
.defined
== e2
.defined
1146 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1149 /* This function parses a list of vector registers of type TYPE.
1150 On success, it returns the parsed register list information in the
1151 following encoded format:
1153 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1154 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1156 The information of the register shape and/or index is returned in
1159 It returns PARSE_FAIL if the register list is invalid.
1161 The list contains one to four registers.
1162 Each register can be one of:
1165 All <T> should be identical.
1166 All <index> should be identical.
1167 There are restrictions on <Vt> numbers which are checked later
1168 (by reg_list_valid_p). */
1171 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1172 struct vector_type_el
*vectype
)
1176 struct vector_type_el typeinfo
, typeinfo_first
;
1181 bfd_boolean error
= FALSE
;
1182 bfd_boolean expect_index
= FALSE
;
1186 set_syntax_error (_("expecting {"));
1192 typeinfo_first
.defined
= 0;
1193 typeinfo_first
.type
= NT_invtype
;
1194 typeinfo_first
.width
= -1;
1195 typeinfo_first
.index
= 0;
1204 str
++; /* skip over '-' */
1207 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1208 /*in_reg_list= */ TRUE
);
1209 if (val
== PARSE_FAIL
)
1211 set_first_syntax_error (_("invalid vector register in list"));
1215 /* reject [bhsd]n */
1216 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1218 set_first_syntax_error (_("invalid scalar register in list"));
1223 if (typeinfo
.defined
& NTA_HASINDEX
)
1224 expect_index
= TRUE
;
1228 if (val
< val_range
)
1230 set_first_syntax_error
1231 (_("invalid range in vector register list"));
1240 typeinfo_first
= typeinfo
;
1241 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1243 set_first_syntax_error
1244 (_("type mismatch in vector register list"));
1249 for (i
= val_range
; i
<= val
; i
++)
1251 ret_val
|= i
<< (5 * nb_regs
);
1256 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1258 skip_whitespace (str
);
1261 set_first_syntax_error (_("end of vector register list not found"));
1266 skip_whitespace (str
);
1270 if (skip_past_char (&str
, '['))
1274 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1275 if (exp
.X_op
!= O_constant
)
1277 set_first_syntax_error (_("constant expression required."));
1280 if (! skip_past_char (&str
, ']'))
1283 typeinfo_first
.index
= exp
.X_add_number
;
1287 set_first_syntax_error (_("expected index"));
1294 set_first_syntax_error (_("too many registers in vector register list"));
1297 else if (nb_regs
== 0)
1299 set_first_syntax_error (_("empty vector register list"));
1305 *vectype
= typeinfo_first
;
1307 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1310 /* Directives: register aliases. */
1313 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1318 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1321 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1324 /* Only warn about a redefinition if it's not defined as the
1326 else if (new->number
!= number
|| new->type
!= type
)
1327 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1332 name
= xstrdup (str
);
1333 new = XNEW (reg_entry
);
1336 new->number
= number
;
1338 new->builtin
= FALSE
;
1340 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1345 /* Look for the .req directive. This is of the form:
1347 new_register_name .req existing_register_name
1349 If we find one, or if it looks sufficiently like one that we want to
1350 handle any error here, return TRUE. Otherwise return FALSE. */
1353 create_register_alias (char *newname
, char *p
)
1355 const reg_entry
*old
;
1356 char *oldname
, *nbuf
;
1359 /* The input scrubber ensures that whitespace after the mnemonic is
1360 collapsed to single spaces. */
1362 if (strncmp (oldname
, " .req ", 6) != 0)
1366 if (*oldname
== '\0')
1369 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1372 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1376 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1377 the desired alias name, and p points to its end. If not, then
1378 the desired alias name is in the global original_case_string. */
1379 #ifdef TC_CASE_SENSITIVE
1382 newname
= original_case_string
;
1383 nlen
= strlen (newname
);
1386 nbuf
= xmemdup0 (newname
, nlen
);
1388 /* Create aliases under the new name as stated; an all-lowercase
1389 version of the new name; and an all-uppercase version of the new
1391 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1393 for (p
= nbuf
; *p
; p
++)
1396 if (strncmp (nbuf
, newname
, nlen
))
1398 /* If this attempt to create an additional alias fails, do not bother
1399 trying to create the all-lower case alias. We will fail and issue
1400 a second, duplicate error message. This situation arises when the
1401 programmer does something like:
1404 The second .req creates the "Foo" alias but then fails to create
1405 the artificial FOO alias because it has already been created by the
1407 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1414 for (p
= nbuf
; *p
; p
++)
1417 if (strncmp (nbuf
, newname
, nlen
))
1418 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1425 /* Should never be called, as .req goes between the alias and the
1426 register name, not at the beginning of the line. */
1428 s_req (int a ATTRIBUTE_UNUSED
)
1430 as_bad (_("invalid syntax for .req directive"));
1433 /* The .unreq directive deletes an alias which was previously defined
1434 by .req. For example:
1440 s_unreq (int a ATTRIBUTE_UNUSED
)
1445 name
= input_line_pointer
;
1447 while (*input_line_pointer
!= 0
1448 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1449 ++input_line_pointer
;
1451 saved_char
= *input_line_pointer
;
1452 *input_line_pointer
= 0;
1455 as_bad (_("invalid syntax for .unreq directive"));
1458 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1461 as_bad (_("unknown register alias '%s'"), name
);
1462 else if (reg
->builtin
)
1463 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1470 str_hash_delete (aarch64_reg_hsh
, name
);
1471 free ((char *) reg
->name
);
1474 /* Also locate the all upper case and all lower case versions.
1475 Do not complain if we cannot find one or the other as it
1476 was probably deleted above. */
1478 nbuf
= strdup (name
);
1479 for (p
= nbuf
; *p
; p
++)
1481 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1484 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1485 free ((char *) reg
->name
);
1489 for (p
= nbuf
; *p
; p
++)
1491 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1494 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1495 free ((char *) reg
->name
);
1503 *input_line_pointer
= saved_char
;
1504 demand_empty_rest_of_line ();
1507 /* Directives: Instruction set selection. */
1510 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1511 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1512 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1513 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1515 /* Create a new mapping symbol for the transition to STATE. */
1518 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1521 const char *symname
;
1528 type
= BSF_NO_FLAGS
;
1532 type
= BSF_NO_FLAGS
;
1538 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1539 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1541 /* Save the mapping symbols for future reference. Also check that
1542 we do not place two mapping symbols at the same offset within a
1543 frag. We'll handle overlap between frags in
1544 check_mapping_symbols.
1546 If .fill or other data filling directive generates zero sized data,
1547 the mapping symbol for the following code will have the same value
1548 as the one generated for the data filling directive. In this case,
1549 we replace the old symbol with the new one at the same address. */
1552 if (frag
->tc_frag_data
.first_map
!= NULL
)
1554 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1555 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1558 frag
->tc_frag_data
.first_map
= symbolP
;
1560 if (frag
->tc_frag_data
.last_map
!= NULL
)
1562 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1563 S_GET_VALUE (symbolP
));
1564 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1565 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1568 frag
->tc_frag_data
.last_map
= symbolP
;
1571 /* We must sometimes convert a region marked as code to data during
1572 code alignment, if an odd number of bytes have to be padded. The
1573 code mapping symbol is pushed to an aligned address. */
1576 insert_data_mapping_symbol (enum mstate state
,
1577 valueT value
, fragS
* frag
, offsetT bytes
)
1579 /* If there was already a mapping symbol, remove it. */
1580 if (frag
->tc_frag_data
.last_map
!= NULL
1581 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1582 frag
->fr_address
+ value
)
1584 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1588 know (frag
->tc_frag_data
.first_map
== symp
);
1589 frag
->tc_frag_data
.first_map
= NULL
;
1591 frag
->tc_frag_data
.last_map
= NULL
;
1592 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1595 make_mapping_symbol (MAP_DATA
, value
, frag
);
1596 make_mapping_symbol (state
, value
+ bytes
, frag
);
1599 static void mapping_state_2 (enum mstate state
, int max_chars
);
1601 /* Set the mapping state to STATE. Only call this when about to
1602 emit some STATE bytes to the file. */
1605 mapping_state (enum mstate state
)
1607 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1609 if (state
== MAP_INSN
)
1610 /* AArch64 instructions require 4-byte alignment. When emitting
1611 instructions into any section, record the appropriate section
1613 record_alignment (now_seg
, 2);
1615 if (mapstate
== state
)
1616 /* The mapping symbol has already been emitted.
1617 There is nothing else to do. */
1620 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1621 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1622 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1623 evaluated later in the next else. */
1625 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1627 /* Only add the symbol if the offset is > 0:
1628 if we're at the first frag, check it's size > 0;
1629 if we're not at the first frag, then for sure
1630 the offset is > 0. */
1631 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1632 const int add_symbol
= (frag_now
!= frag_first
)
1633 || (frag_now_fix () > 0);
1636 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1640 mapping_state_2 (state
, 0);
1643 /* Same as mapping_state, but MAX_CHARS bytes have already been
1644 allocated. Put the mapping symbol that far back. */
1647 mapping_state_2 (enum mstate state
, int max_chars
)
1649 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1651 if (!SEG_NORMAL (now_seg
))
1654 if (mapstate
== state
)
1655 /* The mapping symbol has already been emitted.
1656 There is nothing else to do. */
1659 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1660 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1663 #define mapping_state(x) /* nothing */
1664 #define mapping_state_2(x, y) /* nothing */
1667 /* Directives: sectioning and alignment. */
1670 s_bss (int ignore ATTRIBUTE_UNUSED
)
1672 /* We don't support putting frags in the BSS segment, we fake it by
1673 marking in_bss, then looking at s_skip for clues. */
1674 subseg_set (bss_section
, 0);
1675 demand_empty_rest_of_line ();
1676 mapping_state (MAP_DATA
);
1680 s_even (int ignore ATTRIBUTE_UNUSED
)
1682 /* Never make frag if expect extra pass. */
1684 frag_align (1, 0, 0);
1686 record_alignment (now_seg
, 1);
1688 demand_empty_rest_of_line ();
1691 /* Directives: Literal pools. */
1693 static literal_pool
*
1694 find_literal_pool (int size
)
1698 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1700 if (pool
->section
== now_seg
1701 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1708 static literal_pool
*
1709 find_or_make_literal_pool (int size
)
1711 /* Next literal pool ID number. */
1712 static unsigned int latest_pool_num
= 1;
1715 pool
= find_literal_pool (size
);
1719 /* Create a new pool. */
1720 pool
= XNEW (literal_pool
);
1724 /* Currently we always put the literal pool in the current text
1725 section. If we were generating "small" model code where we
1726 knew that all code and initialised data was within 1MB then
1727 we could output literals to mergeable, read-only data
1730 pool
->next_free_entry
= 0;
1731 pool
->section
= now_seg
;
1732 pool
->sub_section
= now_subseg
;
1734 pool
->next
= list_of_pools
;
1735 pool
->symbol
= NULL
;
1737 /* Add it to the list. */
1738 list_of_pools
= pool
;
1741 /* New pools, and emptied pools, will have a NULL symbol. */
1742 if (pool
->symbol
== NULL
)
1744 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1745 &zero_address_frag
, 0);
1746 pool
->id
= latest_pool_num
++;
1753 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1754 Return TRUE on success, otherwise return FALSE. */
1756 add_to_lit_pool (expressionS
*exp
, int size
)
1761 pool
= find_or_make_literal_pool (size
);
1763 /* Check if this literal value is already in the pool. */
1764 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1766 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1768 if ((litexp
->X_op
== exp
->X_op
)
1769 && (exp
->X_op
== O_constant
)
1770 && (litexp
->X_add_number
== exp
->X_add_number
)
1771 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1774 if ((litexp
->X_op
== exp
->X_op
)
1775 && (exp
->X_op
== O_symbol
)
1776 && (litexp
->X_add_number
== exp
->X_add_number
)
1777 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1778 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1782 /* Do we need to create a new entry? */
1783 if (entry
== pool
->next_free_entry
)
1785 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1787 set_syntax_error (_("literal pool overflow"));
1791 pool
->literals
[entry
].exp
= *exp
;
1792 pool
->next_free_entry
+= 1;
1793 if (exp
->X_op
== O_big
)
1795 /* PR 16688: Bignums are held in a single global array. We must
1796 copy and preserve that value now, before it is overwritten. */
1797 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1799 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1800 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1803 pool
->literals
[entry
].bignum
= NULL
;
1806 exp
->X_op
= O_symbol
;
1807 exp
->X_add_number
= ((int) entry
) * size
;
1808 exp
->X_add_symbol
= pool
->symbol
;
1813 /* Can't use symbol_new here, so have to create a symbol and then at
1814 a later date assign it a value. That's what these functions do. */
1817 symbol_locate (symbolS
* symbolP
,
1818 const char *name
,/* It is copied, the caller can modify. */
1819 segT segment
, /* Segment identifier (SEG_<something>). */
1820 valueT valu
, /* Symbol value. */
1821 fragS
* frag
) /* Associated fragment. */
1824 char *preserved_copy_of_name
;
1826 name_length
= strlen (name
) + 1; /* +1 for \0. */
1827 obstack_grow (¬es
, name
, name_length
);
1828 preserved_copy_of_name
= obstack_finish (¬es
);
1830 #ifdef tc_canonicalize_symbol_name
1831 preserved_copy_of_name
=
1832 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1835 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1837 S_SET_SEGMENT (symbolP
, segment
);
1838 S_SET_VALUE (symbolP
, valu
);
1839 symbol_clear_list_pointers (symbolP
);
1841 symbol_set_frag (symbolP
, frag
);
1843 /* Link to end of symbol chain. */
1845 extern int symbol_table_frozen
;
1847 if (symbol_table_frozen
)
1851 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1853 obj_symbol_new_hook (symbolP
);
1855 #ifdef tc_symbol_new_hook
1856 tc_symbol_new_hook (symbolP
);
1860 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1861 #endif /* DEBUG_SYMS */
1866 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1873 for (align
= 2; align
<= 4; align
++)
1875 int size
= 1 << align
;
1877 pool
= find_literal_pool (size
);
1878 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1881 /* Align pool as you have word accesses.
1882 Only make a frag if we have to. */
1884 frag_align (align
, 0, 0);
1886 mapping_state (MAP_DATA
);
1888 record_alignment (now_seg
, align
);
1890 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1892 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1893 (valueT
) frag_now_fix (), frag_now
);
1894 symbol_table_insert (pool
->symbol
);
1896 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1898 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1900 if (exp
->X_op
== O_big
)
1902 /* PR 16688: Restore the global bignum value. */
1903 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1904 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1905 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1908 /* First output the expression in the instruction to the pool. */
1909 emit_expr (exp
, size
); /* .word|.xword */
1911 if (exp
->X_op
== O_big
)
1913 free (pool
->literals
[entry
].bignum
);
1914 pool
->literals
[entry
].bignum
= NULL
;
1918 /* Mark the pool as empty. */
1919 pool
->next_free_entry
= 0;
1920 pool
->symbol
= NULL
;
1925 /* Forward declarations for functions below, in the MD interface
1927 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1928 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1930 /* Directives: Data. */
1931 /* N.B. the support for relocation suffix in this directive needs to be
1932 implemented properly. */
1935 s_aarch64_elf_cons (int nbytes
)
1939 #ifdef md_flush_pending_output
1940 md_flush_pending_output ();
1943 if (is_it_end_of_statement ())
1945 demand_empty_rest_of_line ();
1949 #ifdef md_cons_align
1950 md_cons_align (nbytes
);
1953 mapping_state (MAP_DATA
);
1956 struct reloc_table_entry
*reloc
;
1960 if (exp
.X_op
!= O_symbol
)
1961 emit_expr (&exp
, (unsigned int) nbytes
);
1964 skip_past_char (&input_line_pointer
, '#');
1965 if (skip_past_char (&input_line_pointer
, ':'))
1967 reloc
= find_reloc_table_entry (&input_line_pointer
);
1969 as_bad (_("unrecognized relocation suffix"));
1971 as_bad (_("unimplemented relocation suffix"));
1972 ignore_rest_of_line ();
1976 emit_expr (&exp
, (unsigned int) nbytes
);
1979 while (*input_line_pointer
++ == ',');
1981 /* Put terminator back into stream. */
1982 input_line_pointer
--;
1983 demand_empty_rest_of_line ();
1986 /* Mark symbol that it follows a variant PCS convention. */
1989 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1995 elf_symbol_type
*elfsym
;
1997 c
= get_symbol_name (&name
);
1999 as_bad (_("Missing symbol name in directive"));
2000 sym
= symbol_find_or_make (name
);
2001 restore_line_pointer (c
);
2002 demand_empty_rest_of_line ();
2003 bfdsym
= symbol_get_bfdsym (sym
);
2004 elfsym
= elf_symbol_from (bfdsym
);
2005 gas_assert (elfsym
);
2006 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2008 #endif /* OBJ_ELF */
2010 /* Output a 32-bit word, but mark as an instruction. */
2013 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2017 #ifdef md_flush_pending_output
2018 md_flush_pending_output ();
2021 if (is_it_end_of_statement ())
2023 demand_empty_rest_of_line ();
2027 /* Sections are assumed to start aligned. In executable section, there is no
2028 MAP_DATA symbol pending. So we only align the address during
2029 MAP_DATA --> MAP_INSN transition.
2030 For other sections, this is not guaranteed. */
2031 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2032 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2033 frag_align_code (2, 0);
2036 mapping_state (MAP_INSN
);
2042 if (exp
.X_op
!= O_constant
)
2044 as_bad (_("constant expression required"));
2045 ignore_rest_of_line ();
2049 if (target_big_endian
)
2051 unsigned int val
= exp
.X_add_number
;
2052 exp
.X_add_number
= SWAP_32 (val
);
2054 emit_expr (&exp
, 4);
2056 while (*input_line_pointer
++ == ',');
2058 /* Put terminator back into stream. */
2059 input_line_pointer
--;
2060 demand_empty_rest_of_line ();
2064 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2066 demand_empty_rest_of_line ();
2067 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2068 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2072 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2075 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2081 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2082 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2084 demand_empty_rest_of_line ();
2087 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2090 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2094 /* Since we're just labelling the code, there's no need to define a
2097 /* Make sure there is enough room in this frag for the following
2098 blr. This trick only works if the blr follows immediately after
2099 the .tlsdesc directive. */
2101 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2102 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2104 demand_empty_rest_of_line ();
2107 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2110 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2116 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2117 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2119 demand_empty_rest_of_line ();
2121 #endif /* OBJ_ELF */
2123 static void s_aarch64_arch (int);
2124 static void s_aarch64_cpu (int);
2125 static void s_aarch64_arch_extension (int);
2127 /* This table describes all the machine specific pseudo-ops the assembler
2128 has to support. The fields are:
2129 pseudo-op name without dot
2130 function to call to execute this pseudo-op
2131 Integer arg to pass to the function. */
2133 const pseudo_typeS md_pseudo_table
[] = {
2134 /* Never called because '.req' does not start a line. */
2136 {"unreq", s_unreq
, 0},
2138 {"even", s_even
, 0},
2139 {"ltorg", s_ltorg
, 0},
2140 {"pool", s_ltorg
, 0},
2141 {"cpu", s_aarch64_cpu
, 0},
2142 {"arch", s_aarch64_arch
, 0},
2143 {"arch_extension", s_aarch64_arch_extension
, 0},
2144 {"inst", s_aarch64_inst
, 0},
2145 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2147 {"tlsdescadd", s_tlsdescadd
, 0},
2148 {"tlsdesccall", s_tlsdesccall
, 0},
2149 {"tlsdescldr", s_tlsdescldr
, 0},
2150 {"word", s_aarch64_elf_cons
, 4},
2151 {"long", s_aarch64_elf_cons
, 4},
2152 {"xword", s_aarch64_elf_cons
, 8},
2153 {"dword", s_aarch64_elf_cons
, 8},
2154 {"variant_pcs", s_variant_pcs
, 0},
2156 {"float16", float_cons
, 'h'},
2157 {"bfloat16", float_cons
, 'b'},
2162 /* Check whether STR points to a register name followed by a comma or the
2163 end of line; REG_TYPE indicates which register types are checked
2164 against. Return TRUE if STR is such a register name; otherwise return
2165 FALSE. The function does not intend to produce any diagnostics, but since
2166 the register parser aarch64_reg_parse, which is called by this function,
2167 does produce diagnostics, we call clear_error to clear any diagnostics
2168 that may be generated by aarch64_reg_parse.
2169 Also, the function returns FALSE directly if there is any user error
2170 present at the function entry. This prevents the existing diagnostics
2171 state from being spoiled.
2172 The function currently serves parse_constant_immediate and
2173 parse_big_immediate only. */
2175 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2179 /* Prevent the diagnostics state from being spoiled. */
2183 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2185 /* Clear the parsing error that may be set by the reg parser. */
2188 if (reg
== PARSE_FAIL
)
2191 skip_whitespace (str
);
2192 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2198 /* Parser functions used exclusively in instruction operands. */
2200 /* Parse an immediate expression which may not be constant.
2202 To prevent the expression parser from pushing a register name
2203 into the symbol table as an undefined symbol, firstly a check is
2204 done to find out whether STR is a register of type REG_TYPE followed
2205 by a comma or the end of line. Return FALSE if STR is such a string. */
2208 parse_immediate_expression (char **str
, expressionS
*exp
,
2209 aarch64_reg_type reg_type
)
2211 if (reg_name_p (*str
, reg_type
))
2213 set_recoverable_error (_("immediate operand required"));
2217 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2219 if (exp
->X_op
== O_absent
)
2221 set_fatal_syntax_error (_("missing immediate expression"));
2228 /* Constant immediate-value read function for use in insn parsing.
2229 STR points to the beginning of the immediate (with the optional
2230 leading #); *VAL receives the value. REG_TYPE says which register
2231 names should be treated as registers rather than as symbolic immediates.
2233 Return TRUE on success; otherwise return FALSE. */
2236 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2240 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2243 if (exp
.X_op
!= O_constant
)
2245 set_syntax_error (_("constant expression required"));
2249 *val
= exp
.X_add_number
;
2254 encode_imm_float_bits (uint32_t imm
)
2256 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2257 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2260 /* Return TRUE if the single-precision floating-point value encoded in IMM
2261 can be expressed in the AArch64 8-bit signed floating-point format with
2262 3-bit exponent and normalized 4 bits of precision; in other words, the
2263 floating-point value must be expressable as
2264 (+/-) n / 16 * power (2, r)
2265 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2268 aarch64_imm_float_p (uint32_t imm
)
2270 /* If a single-precision floating-point value has the following bit
2271 pattern, it can be expressed in the AArch64 8-bit floating-point
2274 3 32222222 2221111111111
2275 1 09876543 21098765432109876543210
2276 n Eeeeeexx xxxx0000000000000000000
2278 where n, e and each x are either 0 or 1 independently, with
2283 /* Prepare the pattern for 'Eeeeee'. */
2284 if (((imm
>> 30) & 0x1) == 0)
2285 pattern
= 0x3e000000;
2287 pattern
= 0x40000000;
2289 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2290 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2293 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2294 as an IEEE float without any loss of precision. Store the value in
2298 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2300 /* If a double-precision floating-point value has the following bit
2301 pattern, it can be expressed in a float:
2303 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2304 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2305 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2307 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2308 if Eeee_eeee != 1111_1111
2310 where n, e, s and S are either 0 or 1 independently and where ~ is the
2314 uint32_t high32
= imm
>> 32;
2315 uint32_t low32
= imm
;
2317 /* Lower 29 bits need to be 0s. */
2318 if ((imm
& 0x1fffffff) != 0)
2321 /* Prepare the pattern for 'Eeeeeeeee'. */
2322 if (((high32
>> 30) & 0x1) == 0)
2323 pattern
= 0x38000000;
2325 pattern
= 0x40000000;
2328 if ((high32
& 0x78000000) != pattern
)
2331 /* Check Eeee_eeee != 1111_1111. */
2332 if ((high32
& 0x7ff00000) == 0x47f00000)
2335 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2336 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2337 | (low32
>> 29)); /* 3 S bits. */
2341 /* Return true if we should treat OPERAND as a double-precision
2342 floating-point operand rather than a single-precision one. */
2344 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2346 /* Check for unsuffixed SVE registers, which are allowed
2347 for LDR and STR but not in instructions that require an
2348 immediate. We get better error messages if we arbitrarily
2349 pick one size, parse the immediate normally, and then
2350 report the match failure in the normal way. */
2351 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2352 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2355 /* Parse a floating-point immediate. Return TRUE on success and return the
2356 value in *IMMED in the format of IEEE754 single-precision encoding.
2357 *CCP points to the start of the string; DP_P is TRUE when the immediate
2358 is expected to be in double-precision (N.B. this only matters when
2359 hexadecimal representation is involved). REG_TYPE says which register
2360 names should be treated as registers rather than as symbolic immediates.
2362 This routine accepts any IEEE float; it is up to the callers to reject
2366 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2367 aarch64_reg_type reg_type
)
2371 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2373 unsigned fpword
= 0;
2374 bfd_boolean hex_p
= FALSE
;
2376 skip_past_char (&str
, '#');
2379 skip_whitespace (fpnum
);
2381 if (strncmp (fpnum
, "0x", 2) == 0)
2383 /* Support the hexadecimal representation of the IEEE754 encoding.
2384 Double-precision is expected when DP_P is TRUE, otherwise the
2385 representation should be in single-precision. */
2386 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2391 if (!can_convert_double_to_float (val
, &fpword
))
2394 else if ((uint64_t) val
> 0xffffffff)
2401 else if (reg_name_p (str
, reg_type
))
2403 set_recoverable_error (_("immediate operand required"));
2411 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2414 /* Our FP word must be 32 bits (single-precision FP). */
2415 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2417 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2427 set_fatal_syntax_error (_("invalid floating-point constant"));
2431 /* Less-generic immediate-value read function with the possibility of loading
2432 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2435 To prevent the expression parser from pushing a register name into the
2436 symbol table as an undefined symbol, a check is firstly done to find
2437 out whether STR is a register of type REG_TYPE followed by a comma or
2438 the end of line. Return FALSE if STR is such a register. */
2441 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2445 if (reg_name_p (ptr
, reg_type
))
2447 set_syntax_error (_("immediate operand required"));
2451 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2453 if (inst
.reloc
.exp
.X_op
== O_constant
)
2454 *imm
= inst
.reloc
.exp
.X_add_number
;
2461 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2462 if NEED_LIBOPCODES is non-zero, the fixup will need
2463 assistance from the libopcodes. */
2466 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2467 const aarch64_opnd_info
*operand
,
2468 int need_libopcodes_p
)
2470 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2471 reloc
->opnd
= operand
->type
;
2472 if (need_libopcodes_p
)
2473 reloc
->need_libopcodes_p
= 1;
2476 /* Return TRUE if the instruction needs to be fixed up later internally by
2477 the GAS; otherwise return FALSE. */
2479 static inline bfd_boolean
2480 aarch64_gas_internal_fixup_p (void)
2482 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2485 /* Assign the immediate value to the relevant field in *OPERAND if
2486 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2487 needs an internal fixup in a later stage.
2488 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2489 IMM.VALUE that may get assigned with the constant. */
2491 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2492 aarch64_opnd_info
*operand
,
2494 int need_libopcodes_p
,
2497 if (reloc
->exp
.X_op
== O_constant
)
2500 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2502 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2503 reloc
->type
= BFD_RELOC_UNUSED
;
2507 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2508 /* Tell libopcodes to ignore this operand or not. This is helpful
2509 when one of the operands needs to be fixed up later but we need
2510 libopcodes to check the other operands. */
2511 operand
->skip
= skip_p
;
2515 /* Relocation modifiers. Each entry in the table contains the textual
2516 name for the relocation which may be placed before a symbol used as
2517 a load/store offset, or add immediate. It must be surrounded by a
2518 leading and trailing colon, for example:
2520 ldr x0, [x1, #:rello:varsym]
2521 add x0, x1, #:rello:varsym */
2523 struct reloc_table_entry
2527 bfd_reloc_code_real_type adr_type
;
2528 bfd_reloc_code_real_type adrp_type
;
2529 bfd_reloc_code_real_type movw_type
;
2530 bfd_reloc_code_real_type add_type
;
2531 bfd_reloc_code_real_type ldst_type
;
2532 bfd_reloc_code_real_type ld_literal_type
;
2535 static struct reloc_table_entry reloc_table
[] = {
2536 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2541 BFD_RELOC_AARCH64_ADD_LO12
,
2542 BFD_RELOC_AARCH64_LDST_LO12
,
2545 /* Higher 21 bits of pc-relative page offset: ADRP */
2548 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2554 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2557 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2563 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2567 BFD_RELOC_AARCH64_MOVW_G0
,
2572 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2576 BFD_RELOC_AARCH64_MOVW_G0_S
,
2581 /* Less significant bits 0-15 of address/value: MOVK, no check */
2585 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2590 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2594 BFD_RELOC_AARCH64_MOVW_G1
,
2599 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2603 BFD_RELOC_AARCH64_MOVW_G1_S
,
2608 /* Less significant bits 16-31 of address/value: MOVK, no check */
2612 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2617 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2621 BFD_RELOC_AARCH64_MOVW_G2
,
2626 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2630 BFD_RELOC_AARCH64_MOVW_G2_S
,
2635 /* Less significant bits 32-47 of address/value: MOVK, no check */
2639 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2644 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2648 BFD_RELOC_AARCH64_MOVW_G3
,
2653 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2657 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2662 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2666 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2671 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2675 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2680 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2684 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2689 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2693 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2698 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2702 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2707 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2711 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2716 /* Get to the page containing GOT entry for a symbol. */
2719 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2723 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2725 /* 12 bit offset into the page containing GOT entry for that symbol. */
2731 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2734 /* 0-15 bits of address/value: MOVk, no check. */
2738 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2743 /* Most significant bits 16-31 of address/value: MOVZ. */
2747 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2752 /* 15 bit offset into the page containing GOT entry for that symbol. */
2758 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2761 /* Get to the page containing GOT TLS entry for a symbol */
2762 {"gottprel_g0_nc", 0,
2765 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2770 /* Get to the page containing GOT TLS entry for a symbol */
2774 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2779 /* Get to the page containing GOT TLS entry for a symbol */
2781 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2782 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2788 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2793 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2797 /* Lower 16 bits address/value: MOVk. */
2801 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2806 /* Most significant bits 16-31 of address/value: MOVZ. */
2810 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2815 /* Get to the page containing GOT TLS entry for a symbol */
2817 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2818 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2822 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2824 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2829 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2830 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2833 /* Get to the page containing GOT TLS entry for a symbol.
2834 The same as GD, we allocate two consecutive GOT slots
2835 for module index and module offset, the only difference
2836 with GD is the module offset should be initialized to
2837 zero without any outstanding runtime relocation. */
2839 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2840 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2846 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2847 {"tlsldm_lo12_nc", 0,
2851 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2855 /* 12 bit offset into the module TLS base address. */
2860 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2861 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2864 /* Same as dtprel_lo12, no overflow check. */
2865 {"dtprel_lo12_nc", 0,
2869 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2870 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2873 /* bits[23:12] of offset to the module TLS base address. */
2878 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2882 /* bits[15:0] of offset to the module TLS base address. */
2886 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2891 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2895 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2900 /* bits[31:16] of offset to the module TLS base address. */
2904 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2909 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2913 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2918 /* bits[47:32] of offset to the module TLS base address. */
2922 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2927 /* Lower 16 bit offset into GOT entry for a symbol */
2928 {"tlsdesc_off_g0_nc", 0,
2931 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2936 /* Higher 16 bit offset into GOT entry for a symbol */
2937 {"tlsdesc_off_g1", 0,
2940 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2945 /* Get to the page containing GOT TLS entry for a symbol */
2948 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2952 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2954 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2955 {"gottprel_lo12", 0,
2960 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2963 /* Get tp offset for a symbol. */
2968 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2972 /* Get tp offset for a symbol. */
2977 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2978 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2981 /* Get tp offset for a symbol. */
2986 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2990 /* Get tp offset for a symbol. */
2991 {"tprel_lo12_nc", 0,
2995 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2996 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2999 /* Most significant bits 32-47 of address/value: MOVZ. */
3003 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3008 /* Most significant bits 16-31 of address/value: MOVZ. */
3012 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3017 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3021 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3026 /* Most significant bits 0-15 of address/value: MOVZ. */
3030 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3035 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3039 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3044 /* 15bit offset from got entry to base address of GOT table. */
3050 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3053 /* 14bit offset from got entry to base address of GOT table. */
3059 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3063 /* Given the address of a pointer pointing to the textual name of a
3064 relocation as may appear in assembler source, attempt to find its
3065 details in reloc_table. The pointer will be updated to the character
3066 after the trailing colon. On failure, NULL will be returned;
3067 otherwise return the reloc_table_entry. */
3069 static struct reloc_table_entry
*
3070 find_reloc_table_entry (char **str
)
3073 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3075 int length
= strlen (reloc_table
[i
].name
);
3077 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3078 && (*str
)[length
] == ':')
3080 *str
+= (length
+ 1);
3081 return &reloc_table
[i
];
3088 /* Mode argument to parse_shift and parser_shifter_operand. */
3089 enum parse_shift_mode
3091 SHIFTED_NONE
, /* no shifter allowed */
3092 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3094 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3096 SHIFTED_LSL
, /* bare "lsl #n" */
3097 SHIFTED_MUL
, /* bare "mul #n" */
3098 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3099 SHIFTED_MUL_VL
, /* "mul vl" */
3100 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3103 /* Parse a <shift> operator on an AArch64 data processing instruction.
3104 Return TRUE on success; otherwise return FALSE. */
3106 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3108 const struct aarch64_name_value_pair
*shift_op
;
3109 enum aarch64_modifier_kind kind
;
3115 for (p
= *str
; ISALPHA (*p
); p
++)
3120 set_syntax_error (_("shift expression expected"));
3124 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3126 if (shift_op
== NULL
)
3128 set_syntax_error (_("shift operator expected"));
3132 kind
= aarch64_get_operand_modifier (shift_op
);
3134 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3136 set_syntax_error (_("invalid use of 'MSL'"));
3140 if (kind
== AARCH64_MOD_MUL
3141 && mode
!= SHIFTED_MUL
3142 && mode
!= SHIFTED_MUL_VL
)
3144 set_syntax_error (_("invalid use of 'MUL'"));
3150 case SHIFTED_LOGIC_IMM
:
3151 if (aarch64_extend_operator_p (kind
))
3153 set_syntax_error (_("extending shift is not permitted"));
3158 case SHIFTED_ARITH_IMM
:
3159 if (kind
== AARCH64_MOD_ROR
)
3161 set_syntax_error (_("'ROR' shift is not permitted"));
3167 if (kind
!= AARCH64_MOD_LSL
)
3169 set_syntax_error (_("only 'LSL' shift is permitted"));
3175 if (kind
!= AARCH64_MOD_MUL
)
3177 set_syntax_error (_("only 'MUL' is permitted"));
3182 case SHIFTED_MUL_VL
:
3183 /* "MUL VL" consists of two separate tokens. Require the first
3184 token to be "MUL" and look for a following "VL". */
3185 if (kind
== AARCH64_MOD_MUL
)
3187 skip_whitespace (p
);
3188 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3191 kind
= AARCH64_MOD_MUL_VL
;
3195 set_syntax_error (_("only 'MUL VL' is permitted"));
3198 case SHIFTED_REG_OFFSET
:
3199 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3200 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3202 set_fatal_syntax_error
3203 (_("invalid shift for the register offset addressing mode"));
3208 case SHIFTED_LSL_MSL
:
3209 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3211 set_syntax_error (_("invalid shift operator"));
3220 /* Whitespace can appear here if the next thing is a bare digit. */
3221 skip_whitespace (p
);
3223 /* Parse shift amount. */
3225 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3226 exp
.X_op
= O_absent
;
3229 if (is_immediate_prefix (*p
))
3234 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3236 if (kind
== AARCH64_MOD_MUL_VL
)
3237 /* For consistency, give MUL VL the same shift amount as an implicit
3239 operand
->shifter
.amount
= 1;
3240 else if (exp
.X_op
== O_absent
)
3242 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3244 set_syntax_error (_("missing shift amount"));
3247 operand
->shifter
.amount
= 0;
3249 else if (exp
.X_op
!= O_constant
)
3251 set_syntax_error (_("constant shift amount required"));
3254 /* For parsing purposes, MUL #n has no inherent range. The range
3255 depends on the operand and will be checked by operand-specific
3257 else if (kind
!= AARCH64_MOD_MUL
3258 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3260 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3265 operand
->shifter
.amount
= exp
.X_add_number
;
3266 operand
->shifter
.amount_present
= 1;
3269 operand
->shifter
.operator_present
= 1;
3270 operand
->shifter
.kind
= kind
;
3276 /* Parse a <shifter_operand> for a data processing instruction:
3279 #<immediate>, LSL #imm
3281 Validation of immediate operands is deferred to md_apply_fix.
3283 Return TRUE on success; otherwise return FALSE. */
3286 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3287 enum parse_shift_mode mode
)
3291 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3296 /* Accept an immediate expression. */
3297 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3300 /* Accept optional LSL for arithmetic immediate values. */
3301 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3302 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3305 /* Not accept any shifter for logical immediate values. */
3306 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3307 && parse_shift (&p
, operand
, mode
))
3309 set_syntax_error (_("unexpected shift operator"));
3317 /* Parse a <shifter_operand> for a data processing instruction:
3322 #<immediate>, LSL #imm
3324 where <shift> is handled by parse_shift above, and the last two
3325 cases are handled by the function above.
3327 Validation of immediate operands is deferred to md_apply_fix.
3329 Return TRUE on success; otherwise return FALSE. */
3332 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3333 enum parse_shift_mode mode
)
3335 const reg_entry
*reg
;
3336 aarch64_opnd_qualifier_t qualifier
;
3337 enum aarch64_operand_class opd_class
3338 = aarch64_get_operand_class (operand
->type
);
3340 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3343 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3345 set_syntax_error (_("unexpected register in the immediate operand"));
3349 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3351 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3355 operand
->reg
.regno
= reg
->number
;
3356 operand
->qualifier
= qualifier
;
3358 /* Accept optional shift operation on register. */
3359 if (! skip_past_comma (str
))
3362 if (! parse_shift (str
, operand
, mode
))
3367 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3370 (_("integer register expected in the extended/shifted operand "
3375 /* We have a shifted immediate variable. */
3376 return parse_shifter_operand_imm (str
, operand
, mode
);
3379 /* Return TRUE on success; return FALSE otherwise. */
3382 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3383 enum parse_shift_mode mode
)
3387 /* Determine if we have the sequence of characters #: or just :
3388 coming next. If we do, then we check for a :rello: relocation
3389 modifier. If we don't, punt the whole lot to
3390 parse_shifter_operand. */
3392 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3394 struct reloc_table_entry
*entry
;
3402 /* Try to parse a relocation. Anything else is an error. */
3403 if (!(entry
= find_reloc_table_entry (str
)))
3405 set_syntax_error (_("unknown relocation modifier"));
3409 if (entry
->add_type
== 0)
3412 (_("this relocation modifier is not allowed on this instruction"));
3416 /* Save str before we decompose it. */
3419 /* Next, we parse the expression. */
3420 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3423 /* Record the relocation type (use the ADD variant here). */
3424 inst
.reloc
.type
= entry
->add_type
;
3425 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3427 /* If str is empty, we've reached the end, stop here. */
3431 /* Otherwise, we have a shifted reloc modifier, so rewind to
3432 recover the variable name and continue parsing for the shifter. */
3434 return parse_shifter_operand_imm (str
, operand
, mode
);
3437 return parse_shifter_operand (str
, operand
, mode
);
3440 /* Parse all forms of an address expression. Information is written
3441 to *OPERAND and/or inst.reloc.
3443 The A64 instruction set has the following addressing modes:
3446 [base] // in SIMD ld/st structure
3447 [base{,#0}] // in ld/st exclusive
3449 [base,Xm{,LSL #imm}]
3450 [base,Xm,SXTX {#imm}]
3451 [base,Wm,(S|U)XTW {#imm}]
3453 [base]! // in ldraa/ldrab exclusive
3457 [base],Xm // in SIMD ld/st structure
3458 PC-relative (literal)
3462 [base,Zm.D{,LSL #imm}]
3463 [base,Zm.S,(S|U)XTW {#imm}]
3464 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3468 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3469 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3470 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3472 (As a convenience, the notation "=immediate" is permitted in conjunction
3473 with the pc-relative literal load instructions to automatically place an
3474 immediate value or symbolic address in a nearby literal pool and generate
3475 a hidden label which references it.)
3477 Upon a successful parsing, the address structure in *OPERAND will be
3478 filled in the following way:
3480 .base_regno = <base>
3481 .offset.is_reg // 1 if the offset is a register
3483 .offset.regno = <Rm>
3485 For different addressing modes defined in the A64 ISA:
3488 .pcrel=0; .preind=1; .postind=0; .writeback=0
3490 .pcrel=0; .preind=1; .postind=0; .writeback=1
3492 .pcrel=0; .preind=0; .postind=1; .writeback=1
3493 PC-relative (literal)
3494 .pcrel=1; .preind=1; .postind=0; .writeback=0
3496 The shift/extension information, if any, will be stored in .shifter.
3497 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3498 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3499 corresponding register.
3501 BASE_TYPE says which types of base register should be accepted and
3502 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3503 is the type of shifter that is allowed for immediate offsets,
3504 or SHIFTED_NONE if none.
3506 In all other respects, it is the caller's responsibility to check
3507 for addressing modes not supported by the instruction, and to set
3511 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3512 aarch64_opnd_qualifier_t
*base_qualifier
,
3513 aarch64_opnd_qualifier_t
*offset_qualifier
,
3514 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3515 enum parse_shift_mode imm_shift_mode
)
3518 const reg_entry
*reg
;
3519 expressionS
*exp
= &inst
.reloc
.exp
;
3521 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3522 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3523 if (! skip_past_char (&p
, '['))
3525 /* =immediate or label. */
3526 operand
->addr
.pcrel
= 1;
3527 operand
->addr
.preind
= 1;
3529 /* #:<reloc_op>:<symbol> */
3530 skip_past_char (&p
, '#');
3531 if (skip_past_char (&p
, ':'))
3533 bfd_reloc_code_real_type ty
;
3534 struct reloc_table_entry
*entry
;
3536 /* Try to parse a relocation modifier. Anything else is
3538 entry
= find_reloc_table_entry (&p
);
3541 set_syntax_error (_("unknown relocation modifier"));
3545 switch (operand
->type
)
3547 case AARCH64_OPND_ADDR_PCREL21
:
3549 ty
= entry
->adr_type
;
3553 ty
= entry
->ld_literal_type
;
3560 (_("this relocation modifier is not allowed on this "
3566 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3568 set_syntax_error (_("invalid relocation expression"));
3572 /* #:<reloc_op>:<expr> */
3573 /* Record the relocation type. */
3574 inst
.reloc
.type
= ty
;
3575 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3580 if (skip_past_char (&p
, '='))
3581 /* =immediate; need to generate the literal in the literal pool. */
3582 inst
.gen_lit_pool
= 1;
3584 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3586 set_syntax_error (_("invalid address"));
3597 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3598 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3600 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3603 operand
->addr
.base_regno
= reg
->number
;
3606 if (skip_past_comma (&p
))
3609 operand
->addr
.preind
= 1;
3611 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3614 if (!aarch64_check_reg_type (reg
, offset_type
))
3616 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3621 operand
->addr
.offset
.regno
= reg
->number
;
3622 operand
->addr
.offset
.is_reg
= 1;
3623 /* Shifted index. */
3624 if (skip_past_comma (&p
))
3627 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3628 /* Use the diagnostics set in parse_shift, so not set new
3629 error message here. */
3633 [base,Xm] # For vector plus scalar SVE2 indexing.
3634 [base,Xm{,LSL #imm}]
3635 [base,Xm,SXTX {#imm}]
3636 [base,Wm,(S|U)XTW {#imm}] */
3637 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3638 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3639 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3641 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3643 set_syntax_error (_("invalid use of 32-bit register offset"));
3646 if (aarch64_get_qualifier_esize (*base_qualifier
)
3647 != aarch64_get_qualifier_esize (*offset_qualifier
)
3648 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3649 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3650 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3652 set_syntax_error (_("offset has different size from base"));
3656 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3658 set_syntax_error (_("invalid use of 64-bit register offset"));
3664 /* [Xn,#:<reloc_op>:<symbol> */
3665 skip_past_char (&p
, '#');
3666 if (skip_past_char (&p
, ':'))
3668 struct reloc_table_entry
*entry
;
3670 /* Try to parse a relocation modifier. Anything else is
3672 if (!(entry
= find_reloc_table_entry (&p
)))
3674 set_syntax_error (_("unknown relocation modifier"));
3678 if (entry
->ldst_type
== 0)
3681 (_("this relocation modifier is not allowed on this "
3686 /* [Xn,#:<reloc_op>: */
3687 /* We now have the group relocation table entry corresponding to
3688 the name in the assembler source. Next, we parse the
3690 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3692 set_syntax_error (_("invalid relocation expression"));
3696 /* [Xn,#:<reloc_op>:<expr> */
3697 /* Record the load/store relocation type. */
3698 inst
.reloc
.type
= entry
->ldst_type
;
3699 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3703 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3705 set_syntax_error (_("invalid expression in the address"));
3709 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3710 /* [Xn,<expr>,<shifter> */
3711 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3717 if (! skip_past_char (&p
, ']'))
3719 set_syntax_error (_("']' expected"));
3723 if (skip_past_char (&p
, '!'))
3725 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3727 set_syntax_error (_("register offset not allowed in pre-indexed "
3728 "addressing mode"));
3732 operand
->addr
.writeback
= 1;
3734 else if (skip_past_comma (&p
))
3737 operand
->addr
.postind
= 1;
3738 operand
->addr
.writeback
= 1;
3740 if (operand
->addr
.preind
)
3742 set_syntax_error (_("cannot combine pre- and post-indexing"));
3746 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3750 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3752 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3756 operand
->addr
.offset
.regno
= reg
->number
;
3757 operand
->addr
.offset
.is_reg
= 1;
3759 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3762 set_syntax_error (_("invalid expression in the address"));
3767 /* If at this point neither .preind nor .postind is set, we have a
3768 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3769 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3770 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3772 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3774 if (operand
->addr
.writeback
)
3776 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3778 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3779 operand
->addr
.offset
.is_reg
= 0;
3780 operand
->addr
.offset
.imm
= 0;
3781 operand
->addr
.preind
= 1;
3786 set_syntax_error (_("missing offset in the pre-indexed address"));
3792 operand
->addr
.preind
= 1;
3793 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3795 operand
->addr
.offset
.is_reg
= 1;
3796 operand
->addr
.offset
.regno
= REG_ZR
;
3797 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3801 inst
.reloc
.exp
.X_op
= O_constant
;
3802 inst
.reloc
.exp
.X_add_number
= 0;
3811 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3814 parse_address (char **str
, aarch64_opnd_info
*operand
)
3816 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3817 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3818 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3821 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3822 The arguments have the same meaning as for parse_address_main.
3823 Return TRUE on success. */
3825 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3826 aarch64_opnd_qualifier_t
*base_qualifier
,
3827 aarch64_opnd_qualifier_t
*offset_qualifier
)
3829 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3830 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3834 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3835 Return TRUE on success; otherwise return FALSE. */
3837 parse_half (char **str
, int *internal_fixup_p
)
3841 skip_past_char (&p
, '#');
3843 gas_assert (internal_fixup_p
);
3844 *internal_fixup_p
= 0;
3848 struct reloc_table_entry
*entry
;
3850 /* Try to parse a relocation. Anything else is an error. */
3852 if (!(entry
= find_reloc_table_entry (&p
)))
3854 set_syntax_error (_("unknown relocation modifier"));
3858 if (entry
->movw_type
== 0)
3861 (_("this relocation modifier is not allowed on this instruction"));
3865 inst
.reloc
.type
= entry
->movw_type
;
3868 *internal_fixup_p
= 1;
3870 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3877 /* Parse an operand for an ADRP instruction:
3879 Return TRUE on success; otherwise return FALSE. */
3882 parse_adrp (char **str
)
3889 struct reloc_table_entry
*entry
;
3891 /* Try to parse a relocation. Anything else is an error. */
3893 if (!(entry
= find_reloc_table_entry (&p
)))
3895 set_syntax_error (_("unknown relocation modifier"));
3899 if (entry
->adrp_type
== 0)
3902 (_("this relocation modifier is not allowed on this instruction"));
3906 inst
.reloc
.type
= entry
->adrp_type
;
3909 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3911 inst
.reloc
.pc_rel
= 1;
3913 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3920 /* Miscellaneous. */
3922 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3923 of SIZE tokens in which index I gives the token for field value I,
3924 or is null if field value I is invalid. REG_TYPE says which register
3925 names should be treated as registers rather than as symbolic immediates.
3927 Return true on success, moving *STR past the operand and storing the
3928 field value in *VAL. */
3931 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3932 size_t size
, aarch64_reg_type reg_type
)
3938 /* Match C-like tokens. */
3940 while (ISALNUM (*q
))
3943 for (i
= 0; i
< size
; ++i
)
3945 && strncasecmp (array
[i
], p
, q
- p
) == 0
3946 && array
[i
][q
- p
] == 0)
3953 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3956 if (exp
.X_op
== O_constant
3957 && (uint64_t) exp
.X_add_number
< size
)
3959 *val
= exp
.X_add_number
;
3964 /* Use the default error for this operand. */
3968 /* Parse an option for a preload instruction. Returns the encoding for the
3969 option, or PARSE_FAIL. */
3972 parse_pldop (char **str
)
3975 const struct aarch64_name_value_pair
*o
;
3978 while (ISALNUM (*q
))
3981 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3989 /* Parse an option for a barrier instruction. Returns the encoding for the
3990 option, or PARSE_FAIL. */
3993 parse_barrier (char **str
)
3996 const asm_barrier_opt
*o
;
3999 while (ISALPHA (*q
))
4002 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4010 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4011 return 0 if successful. Otherwise return PARSE_FAIL. */
4014 parse_barrier_psb (char **str
,
4015 const struct aarch64_name_value_pair
** hint_opt
)
4018 const struct aarch64_name_value_pair
*o
;
4021 while (ISALPHA (*q
))
4024 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4027 set_fatal_syntax_error
4028 ( _("unknown or missing option to PSB/TSB"));
4032 if (o
->value
!= 0x11)
4034 /* PSB only accepts option name 'CSYNC'. */
4036 (_("the specified option is not accepted for PSB/TSB"));
4045 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4046 return 0 if successful. Otherwise return PARSE_FAIL. */
4049 parse_bti_operand (char **str
,
4050 const struct aarch64_name_value_pair
** hint_opt
)
4053 const struct aarch64_name_value_pair
*o
;
4056 while (ISALPHA (*q
))
4059 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4062 set_fatal_syntax_error
4063 ( _("unknown option to BTI"));
4069 /* Valid BTI operands. */
4077 (_("unknown option to BTI"));
4086 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4087 Returns the encoding for the option, or PARSE_FAIL.
4089 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4090 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4092 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4093 field, otherwise as a system register.
4097 parse_sys_reg (char **str
, htab_t sys_regs
,
4098 int imple_defined_p
, int pstatefield_p
,
4102 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4103 const aarch64_sys_reg
*o
;
4107 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4108 if (p
< buf
+ (sizeof (buf
) - 1))
4109 *p
++ = TOLOWER (*q
);
4112 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4113 valid system register. This is enforced by construction of the hash
4115 if (p
- buf
!= q
- *str
)
4118 o
= str_hash_find (sys_regs
, buf
);
4121 if (!imple_defined_p
)
4125 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4126 unsigned int op0
, op1
, cn
, cm
, op2
;
4128 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4131 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4133 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4140 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4141 as_bad (_("selected processor does not support PSTATE field "
4144 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4145 o
->value
, o
->flags
, o
->features
))
4146 as_bad (_("selected processor does not support system register "
4148 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4149 as_warn (_("system register name '%s' is deprecated and may be "
4150 "removed in a future release"), buf
);
4160 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4161 for the option, or NULL. */
4163 static const aarch64_sys_ins_reg
*
4164 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4167 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4168 const aarch64_sys_ins_reg
*o
;
4171 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4172 if (p
< buf
+ (sizeof (buf
) - 1))
4173 *p
++ = TOLOWER (*q
);
4176 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4177 valid system register. This is enforced by construction of the hash
4179 if (p
- buf
!= q
- *str
)
4182 o
= str_hash_find (sys_ins_regs
, buf
);
4186 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4187 o
->name
, o
->value
, o
->flags
, 0))
4188 as_bad (_("selected processor does not support system register "
4190 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4191 as_warn (_("system register name '%s' is deprecated and may be "
4192 "removed in a future release"), buf
);
4198 #define po_char_or_fail(chr) do { \
4199 if (! skip_past_char (&str, chr)) \
4203 #define po_reg_or_fail(regtype) do { \
4204 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4205 if (val == PARSE_FAIL) \
4207 set_default_error (); \
4212 #define po_int_reg_or_fail(reg_type) do { \
4213 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4214 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4216 set_default_error (); \
4219 info->reg.regno = reg->number; \
4220 info->qualifier = qualifier; \
4223 #define po_imm_nc_or_fail() do { \
4224 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4228 #define po_imm_or_fail(min, max) do { \
4229 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4231 if (val < min || val > max) \
4233 set_fatal_syntax_error (_("immediate value out of range "\
4234 #min " to "#max)); \
4239 #define po_enum_or_fail(array) do { \
4240 if (!parse_enum_string (&str, &val, array, \
4241 ARRAY_SIZE (array), imm_reg_type)) \
4245 #define po_misc_or_fail(expr) do { \
4250 /* encode the 12-bit imm field of Add/sub immediate */
4251 static inline uint32_t
4252 encode_addsub_imm (uint32_t imm
)
4257 /* encode the shift amount field of Add/sub immediate */
4258 static inline uint32_t
4259 encode_addsub_imm_shift_amount (uint32_t cnt
)
4265 /* encode the imm field of Adr instruction */
4266 static inline uint32_t
4267 encode_adr_imm (uint32_t imm
)
4269 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4270 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4273 /* encode the immediate field of Move wide immediate */
4274 static inline uint32_t
4275 encode_movw_imm (uint32_t imm
)
4280 /* encode the 26-bit offset of unconditional branch */
4281 static inline uint32_t
4282 encode_branch_ofs_26 (uint32_t ofs
)
4284 return ofs
& ((1 << 26) - 1);
4287 /* encode the 19-bit offset of conditional branch and compare & branch */
4288 static inline uint32_t
4289 encode_cond_branch_ofs_19 (uint32_t ofs
)
4291 return (ofs
& ((1 << 19) - 1)) << 5;
4294 /* encode the 19-bit offset of ld literal */
4295 static inline uint32_t
4296 encode_ld_lit_ofs_19 (uint32_t ofs
)
4298 return (ofs
& ((1 << 19) - 1)) << 5;
4301 /* Encode the 14-bit offset of test & branch. */
4302 static inline uint32_t
4303 encode_tst_branch_ofs_14 (uint32_t ofs
)
4305 return (ofs
& ((1 << 14) - 1)) << 5;
4308 /* Encode the 16-bit imm field of svc/hvc/smc. */
4309 static inline uint32_t
4310 encode_svc_imm (uint32_t imm
)
4315 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4316 static inline uint32_t
4317 reencode_addsub_switch_add_sub (uint32_t opcode
)
4319 return opcode
^ (1 << 30);
4322 static inline uint32_t
4323 reencode_movzn_to_movz (uint32_t opcode
)
4325 return opcode
| (1 << 30);
4328 static inline uint32_t
4329 reencode_movzn_to_movn (uint32_t opcode
)
4331 return opcode
& ~(1 << 30);
4334 /* Overall per-instruction processing. */
4336 /* We need to be able to fix up arbitrary expressions in some statements.
4337 This is so that we can handle symbols that are an arbitrary distance from
4338 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4339 which returns part of an address in a form which will be valid for
4340 a data instruction. We do this by pushing the expression into a symbol
4341 in the expr_section, and creating a fix for that. */
4344 fix_new_aarch64 (fragS
* frag
,
4359 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4363 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4370 /* Diagnostics on operands errors. */
4372 /* By default, output verbose error message.
4373 Disable the verbose error message by -mno-verbose-error. */
4374 static int verbose_error_p
= 1;
4376 #ifdef DEBUG_AARCH64
4377 /* N.B. this is only for the purpose of debugging. */
4378 const char* operand_mismatch_kind_names
[] =
4381 "AARCH64_OPDE_RECOVERABLE",
4382 "AARCH64_OPDE_SYNTAX_ERROR",
4383 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4384 "AARCH64_OPDE_INVALID_VARIANT",
4385 "AARCH64_OPDE_OUT_OF_RANGE",
4386 "AARCH64_OPDE_UNALIGNED",
4387 "AARCH64_OPDE_REG_LIST",
4388 "AARCH64_OPDE_OTHER_ERROR",
4390 #endif /* DEBUG_AARCH64 */
4392 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4394 When multiple errors of different kinds are found in the same assembly
4395 line, only the error of the highest severity will be picked up for
4396 issuing the diagnostics. */
4398 static inline bfd_boolean
4399 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4400 enum aarch64_operand_error_kind rhs
)
4402 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4403 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4404 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4405 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4406 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4407 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4408 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4409 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4413 /* Helper routine to get the mnemonic name from the assembly instruction
4414 line; should only be called for the diagnosis purpose, as there is
4415 string copy operation involved, which may affect the runtime
4416 performance if used in elsewhere. */
4419 get_mnemonic_name (const char *str
)
4421 static char mnemonic
[32];
4424 /* Get the first 15 bytes and assume that the full name is included. */
4425 strncpy (mnemonic
, str
, 31);
4426 mnemonic
[31] = '\0';
4428 /* Scan up to the end of the mnemonic, which must end in white space,
4429 '.', or end of string. */
4430 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4435 /* Append '...' to the truncated long name. */
4436 if (ptr
- mnemonic
== 31)
4437 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4443 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4445 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4446 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4449 /* Data structures storing one user error in the assembly code related to
4452 struct operand_error_record
4454 const aarch64_opcode
*opcode
;
4455 aarch64_operand_error detail
;
4456 struct operand_error_record
*next
;
4459 typedef struct operand_error_record operand_error_record
;
4461 struct operand_errors
4463 operand_error_record
*head
;
4464 operand_error_record
*tail
;
4467 typedef struct operand_errors operand_errors
;
4469 /* Top-level data structure reporting user errors for the current line of
4471 The way md_assemble works is that all opcodes sharing the same mnemonic
4472 name are iterated to find a match to the assembly line. In this data
4473 structure, each of the such opcodes will have one operand_error_record
4474 allocated and inserted. In other words, excessive errors related with
4475 a single opcode are disregarded. */
4476 operand_errors operand_error_report
;
4478 /* Free record nodes. */
4479 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4481 /* Initialize the data structure that stores the operand mismatch
4482 information on assembling one line of the assembly code. */
4484 init_operand_error_report (void)
4486 if (operand_error_report
.head
!= NULL
)
4488 gas_assert (operand_error_report
.tail
!= NULL
);
4489 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4490 free_opnd_error_record_nodes
= operand_error_report
.head
;
4491 operand_error_report
.head
= NULL
;
4492 operand_error_report
.tail
= NULL
;
4495 gas_assert (operand_error_report
.tail
== NULL
);
4498 /* Return TRUE if some operand error has been recorded during the
4499 parsing of the current assembly line using the opcode *OPCODE;
4500 otherwise return FALSE. */
4501 static inline bfd_boolean
4502 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4504 operand_error_record
*record
= operand_error_report
.head
;
4505 return record
&& record
->opcode
== opcode
;
4508 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4509 OPCODE field is initialized with OPCODE.
4510 N.B. only one record for each opcode, i.e. the maximum of one error is
4511 recorded for each instruction template. */
4514 add_operand_error_record (const operand_error_record
* new_record
)
4516 const aarch64_opcode
*opcode
= new_record
->opcode
;
4517 operand_error_record
* record
= operand_error_report
.head
;
4519 /* The record may have been created for this opcode. If not, we need
4521 if (! opcode_has_operand_error_p (opcode
))
4523 /* Get one empty record. */
4524 if (free_opnd_error_record_nodes
== NULL
)
4526 record
= XNEW (operand_error_record
);
4530 record
= free_opnd_error_record_nodes
;
4531 free_opnd_error_record_nodes
= record
->next
;
4533 record
->opcode
= opcode
;
4534 /* Insert at the head. */
4535 record
->next
= operand_error_report
.head
;
4536 operand_error_report
.head
= record
;
4537 if (operand_error_report
.tail
== NULL
)
4538 operand_error_report
.tail
= record
;
4540 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4541 && record
->detail
.index
<= new_record
->detail
.index
4542 && operand_error_higher_severity_p (record
->detail
.kind
,
4543 new_record
->detail
.kind
))
4545 /* In the case of multiple errors found on operands related with a
4546 single opcode, only record the error of the leftmost operand and
4547 only if the error is of higher severity. */
4548 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4549 " the existing error %s on operand %d",
4550 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4551 new_record
->detail
.index
,
4552 operand_mismatch_kind_names
[record
->detail
.kind
],
4553 record
->detail
.index
);
4557 record
->detail
= new_record
->detail
;
4561 record_operand_error_info (const aarch64_opcode
*opcode
,
4562 aarch64_operand_error
*error_info
)
4564 operand_error_record record
;
4565 record
.opcode
= opcode
;
4566 record
.detail
= *error_info
;
4567 add_operand_error_record (&record
);
4570 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4571 error message *ERROR, for operand IDX (count from 0). */
4574 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4575 enum aarch64_operand_error_kind kind
,
4578 aarch64_operand_error info
;
4579 memset(&info
, 0, sizeof (info
));
4583 info
.non_fatal
= FALSE
;
4584 record_operand_error_info (opcode
, &info
);
4588 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4589 enum aarch64_operand_error_kind kind
,
4590 const char* error
, const int *extra_data
)
4592 aarch64_operand_error info
;
4596 info
.data
[0] = extra_data
[0];
4597 info
.data
[1] = extra_data
[1];
4598 info
.data
[2] = extra_data
[2];
4599 info
.non_fatal
= FALSE
;
4600 record_operand_error_info (opcode
, &info
);
4604 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4605 const char* error
, int lower_bound
,
4608 int data
[3] = {lower_bound
, upper_bound
, 0};
4609 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4613 /* Remove the operand error record for *OPCODE. */
4614 static void ATTRIBUTE_UNUSED
4615 remove_operand_error_record (const aarch64_opcode
*opcode
)
4617 if (opcode_has_operand_error_p (opcode
))
4619 operand_error_record
* record
= operand_error_report
.head
;
4620 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4621 operand_error_report
.head
= record
->next
;
4622 record
->next
= free_opnd_error_record_nodes
;
4623 free_opnd_error_record_nodes
= record
;
4624 if (operand_error_report
.head
== NULL
)
4626 gas_assert (operand_error_report
.tail
== record
);
4627 operand_error_report
.tail
= NULL
;
4632 /* Given the instruction in *INSTR, return the index of the best matched
4633 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4635 Return -1 if there is no qualifier sequence; return the first match
4636 if there is multiple matches found. */
4639 find_best_match (const aarch64_inst
*instr
,
4640 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4642 int i
, num_opnds
, max_num_matched
, idx
;
4644 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4647 DEBUG_TRACE ("no operand");
4651 max_num_matched
= 0;
4654 /* For each pattern. */
4655 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4658 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4660 /* Most opcodes has much fewer patterns in the list. */
4661 if (empty_qualifier_sequence_p (qualifiers
))
4663 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4667 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4668 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4671 if (num_matched
> max_num_matched
)
4673 max_num_matched
= num_matched
;
4678 DEBUG_TRACE ("return with %d", idx
);
4682 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4683 corresponding operands in *INSTR. */
4686 assign_qualifier_sequence (aarch64_inst
*instr
,
4687 const aarch64_opnd_qualifier_t
*qualifiers
)
4690 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4691 gas_assert (num_opnds
);
4692 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4693 instr
->operands
[i
].qualifier
= *qualifiers
;
4696 /* Print operands for the diagnosis purpose. */
4699 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4700 const aarch64_opnd_info
*opnds
)
4704 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4708 /* We regard the opcode operand info more, however we also look into
4709 the inst->operands to support the disassembling of the optional
4711 The two operand code should be the same in all cases, apart from
4712 when the operand can be optional. */
4713 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4714 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4717 /* Generate the operand string in STR. */
4718 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4723 strcat (buf
, i
== 0 ? " " : ", ");
4725 /* Append the operand string. */
4730 /* Send to stderr a string as information. */
4733 output_info (const char *format
, ...)
4739 file
= as_where (&line
);
4743 fprintf (stderr
, "%s:%u: ", file
, line
);
4745 fprintf (stderr
, "%s: ", file
);
4747 fprintf (stderr
, _("Info: "));
4748 va_start (args
, format
);
4749 vfprintf (stderr
, format
, args
);
4751 (void) putc ('\n', stderr
);
4754 /* Output one operand error record. */
4757 output_operand_error_record (const operand_error_record
*record
, char *str
)
4759 const aarch64_operand_error
*detail
= &record
->detail
;
4760 int idx
= detail
->index
;
4761 const aarch64_opcode
*opcode
= record
->opcode
;
4762 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4763 : AARCH64_OPND_NIL
);
4765 typedef void (*handler_t
)(const char *format
, ...);
4766 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4768 switch (detail
->kind
)
4770 case AARCH64_OPDE_NIL
:
4773 case AARCH64_OPDE_SYNTAX_ERROR
:
4774 case AARCH64_OPDE_RECOVERABLE
:
4775 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4776 case AARCH64_OPDE_OTHER_ERROR
:
4777 /* Use the prepared error message if there is, otherwise use the
4778 operand description string to describe the error. */
4779 if (detail
->error
!= NULL
)
4782 handler (_("%s -- `%s'"), detail
->error
, str
);
4784 handler (_("%s at operand %d -- `%s'"),
4785 detail
->error
, idx
+ 1, str
);
4789 gas_assert (idx
>= 0);
4790 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4791 aarch64_get_operand_desc (opd_code
), str
);
4795 case AARCH64_OPDE_INVALID_VARIANT
:
4796 handler (_("operand mismatch -- `%s'"), str
);
4797 if (verbose_error_p
)
4799 /* We will try to correct the erroneous instruction and also provide
4800 more information e.g. all other valid variants.
4802 The string representation of the corrected instruction and other
4803 valid variants are generated by
4805 1) obtaining the intermediate representation of the erroneous
4807 2) manipulating the IR, e.g. replacing the operand qualifier;
4808 3) printing out the instruction by calling the printer functions
4809 shared with the disassembler.
4811 The limitation of this method is that the exact input assembly
4812 line cannot be accurately reproduced in some cases, for example an
4813 optional operand present in the actual assembly line will be
4814 omitted in the output; likewise for the optional syntax rules,
4815 e.g. the # before the immediate. Another limitation is that the
4816 assembly symbols and relocation operations in the assembly line
4817 currently cannot be printed out in the error report. Last but not
4818 least, when there is other error(s) co-exist with this error, the
4819 'corrected' instruction may be still incorrect, e.g. given
4820 'ldnp h0,h1,[x0,#6]!'
4821 this diagnosis will provide the version:
4822 'ldnp s0,s1,[x0,#6]!'
4823 which is still not right. */
4824 size_t len
= strlen (get_mnemonic_name (str
));
4828 aarch64_inst
*inst_base
= &inst
.base
;
4829 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4832 reset_aarch64_instruction (&inst
);
4833 inst_base
->opcode
= opcode
;
4835 /* Reset the error report so that there is no side effect on the
4836 following operand parsing. */
4837 init_operand_error_report ();
4840 result
= parse_operands (str
+ len
, opcode
)
4841 && programmer_friendly_fixup (&inst
);
4842 gas_assert (result
);
4843 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4844 NULL
, NULL
, insn_sequence
);
4845 gas_assert (!result
);
4847 /* Find the most matched qualifier sequence. */
4848 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4849 gas_assert (qlf_idx
> -1);
4851 /* Assign the qualifiers. */
4852 assign_qualifier_sequence (inst_base
,
4853 opcode
->qualifiers_list
[qlf_idx
]);
4855 /* Print the hint. */
4856 output_info (_(" did you mean this?"));
4857 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4858 print_operands (buf
, opcode
, inst_base
->operands
);
4859 output_info (_(" %s"), buf
);
4861 /* Print out other variant(s) if there is any. */
4863 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4864 output_info (_(" other valid variant(s):"));
4866 /* For each pattern. */
4867 qualifiers_list
= opcode
->qualifiers_list
;
4868 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4870 /* Most opcodes has much fewer patterns in the list.
4871 First NIL qualifier indicates the end in the list. */
4872 if (empty_qualifier_sequence_p (*qualifiers_list
))
4877 /* Mnemonics name. */
4878 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4880 /* Assign the qualifiers. */
4881 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4883 /* Print instruction. */
4884 print_operands (buf
, opcode
, inst_base
->operands
);
4886 output_info (_(" %s"), buf
);
4892 case AARCH64_OPDE_UNTIED_OPERAND
:
4893 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4894 detail
->index
+ 1, str
);
4897 case AARCH64_OPDE_OUT_OF_RANGE
:
4898 if (detail
->data
[0] != detail
->data
[1])
4899 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4900 detail
->error
? detail
->error
: _("immediate value"),
4901 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4903 handler (_("%s must be %d at operand %d -- `%s'"),
4904 detail
->error
? detail
->error
: _("immediate value"),
4905 detail
->data
[0], idx
+ 1, str
);
4908 case AARCH64_OPDE_REG_LIST
:
4909 if (detail
->data
[0] == 1)
4910 handler (_("invalid number of registers in the list; "
4911 "only 1 register is expected at operand %d -- `%s'"),
4914 handler (_("invalid number of registers in the list; "
4915 "%d registers are expected at operand %d -- `%s'"),
4916 detail
->data
[0], idx
+ 1, str
);
4919 case AARCH64_OPDE_UNALIGNED
:
4920 handler (_("immediate value must be a multiple of "
4921 "%d at operand %d -- `%s'"),
4922 detail
->data
[0], idx
+ 1, str
);
4931 /* Process and output the error message about the operand mismatching.
4933 When this function is called, the operand error information had
4934 been collected for an assembly line and there will be multiple
4935 errors in the case of multiple instruction templates; output the
4936 error message that most closely describes the problem.
4938 The errors to be printed can be filtered on printing all errors
4939 or only non-fatal errors. This distinction has to be made because
4940 the error buffer may already be filled with fatal errors we don't want to
4941 print due to the different instruction templates. */
4944 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4946 int largest_error_pos
;
4947 const char *msg
= NULL
;
4948 enum aarch64_operand_error_kind kind
;
4949 operand_error_record
*curr
;
4950 operand_error_record
*head
= operand_error_report
.head
;
4951 operand_error_record
*record
= NULL
;
4953 /* No error to report. */
4957 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4959 /* Only one error. */
4960 if (head
== operand_error_report
.tail
)
4962 /* If the only error is a non-fatal one and we don't want to print it,
4964 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4966 DEBUG_TRACE ("single opcode entry with error kind: %s",
4967 operand_mismatch_kind_names
[head
->detail
.kind
]);
4968 output_operand_error_record (head
, str
);
4973 /* Find the error kind of the highest severity. */
4974 DEBUG_TRACE ("multiple opcode entries with error kind");
4975 kind
= AARCH64_OPDE_NIL
;
4976 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4978 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4979 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4980 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4981 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4982 kind
= curr
->detail
.kind
;
4985 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4987 /* Pick up one of errors of KIND to report. */
4988 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4989 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4991 /* If we don't want to print non-fatal errors then don't consider them
4993 if (curr
->detail
.kind
!= kind
4994 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4996 /* If there are multiple errors, pick up the one with the highest
4997 mismatching operand index. In the case of multiple errors with
4998 the equally highest operand index, pick up the first one or the
4999 first one with non-NULL error message. */
5000 if (curr
->detail
.index
> largest_error_pos
5001 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5002 && curr
->detail
.error
!= NULL
))
5004 largest_error_pos
= curr
->detail
.index
;
5006 msg
= record
->detail
.error
;
5010 /* The way errors are collected in the back-end is a bit non-intuitive. But
5011 essentially, because each operand template is tried recursively you may
5012 always have errors collected from the previous tried OPND. These are
5013 usually skipped if there is one successful match. However now with the
5014 non-fatal errors we have to ignore those previously collected hard errors
5015 when we're only interested in printing the non-fatal ones. This condition
5016 prevents us from printing errors that are not appropriate, since we did
5017 match a condition, but it also has warnings that it wants to print. */
5018 if (non_fatal_only
&& !record
)
5021 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5022 DEBUG_TRACE ("Pick up error kind %s to report",
5023 operand_mismatch_kind_names
[record
->detail
.kind
]);
5026 output_operand_error_record (record
, str
);
5029 /* Write an AARCH64 instruction to buf - always little-endian. */
5031 put_aarch64_insn (char *buf
, uint32_t insn
)
5033 unsigned char *where
= (unsigned char *) buf
;
5035 where
[1] = insn
>> 8;
5036 where
[2] = insn
>> 16;
5037 where
[3] = insn
>> 24;
5041 get_aarch64_insn (char *buf
)
5043 unsigned char *where
= (unsigned char *) buf
;
5045 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5046 | ((uint32_t) where
[3] << 24)));
5051 output_inst (struct aarch64_inst
*new_inst
)
5055 to
= frag_more (INSN_SIZE
);
5057 frag_now
->tc_frag_data
.recorded
= 1;
5059 put_aarch64_insn (to
, inst
.base
.value
);
5061 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5063 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5064 INSN_SIZE
, &inst
.reloc
.exp
,
5067 DEBUG_TRACE ("Prepared relocation fix up");
5068 /* Don't check the addend value against the instruction size,
5069 that's the job of our code in md_apply_fix(). */
5070 fixp
->fx_no_overflow
= 1;
5071 if (new_inst
!= NULL
)
5072 fixp
->tc_fix_data
.inst
= new_inst
;
5073 if (aarch64_gas_internal_fixup_p ())
5075 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5076 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5077 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5081 dwarf2_emit_insn (INSN_SIZE
);
5084 /* Link together opcodes of the same name. */
5088 aarch64_opcode
*opcode
;
5089 struct templates
*next
;
5092 typedef struct templates templates
;
5095 lookup_mnemonic (const char *start
, int len
)
5097 templates
*templ
= NULL
;
5099 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5103 /* Subroutine of md_assemble, responsible for looking up the primary
5104 opcode from the mnemonic the user wrote. STR points to the
5105 beginning of the mnemonic. */
5108 opcode_lookup (char **str
)
5110 char *end
, *base
, *dot
;
5111 const aarch64_cond
*cond
;
5115 /* Scan up to the end of the mnemonic, which must end in white space,
5116 '.', or end of string. */
5118 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5119 if (*end
== '.' && !dot
)
5122 if (end
== base
|| dot
== base
)
5125 inst
.cond
= COND_ALWAYS
;
5127 /* Handle a possible condition. */
5130 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5133 inst
.cond
= cond
->value
;
5149 if (inst
.cond
== COND_ALWAYS
)
5151 /* Look for unaffixed mnemonic. */
5152 return lookup_mnemonic (base
, len
);
5156 /* append ".c" to mnemonic if conditional */
5157 memcpy (condname
, base
, len
);
5158 memcpy (condname
+ len
, ".c", 2);
5161 return lookup_mnemonic (base
, len
);
5167 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5168 to a corresponding operand qualifier. */
5170 static inline aarch64_opnd_qualifier_t
5171 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5173 /* Element size in bytes indexed by vector_el_type. */
5174 const unsigned char ele_size
[5]
5176 const unsigned int ele_base
[5] =
5178 AARCH64_OPND_QLF_V_4B
,
5179 AARCH64_OPND_QLF_V_2H
,
5180 AARCH64_OPND_QLF_V_2S
,
5181 AARCH64_OPND_QLF_V_1D
,
5182 AARCH64_OPND_QLF_V_1Q
5185 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5186 goto vectype_conversion_fail
;
5188 if (vectype
->type
== NT_zero
)
5189 return AARCH64_OPND_QLF_P_Z
;
5190 if (vectype
->type
== NT_merge
)
5191 return AARCH64_OPND_QLF_P_M
;
5193 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5195 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5197 /* Special case S_4B. */
5198 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5199 return AARCH64_OPND_QLF_S_4B
;
5201 /* Special case S_2H. */
5202 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5203 return AARCH64_OPND_QLF_S_2H
;
5205 /* Vector element register. */
5206 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5210 /* Vector register. */
5211 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5214 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5215 goto vectype_conversion_fail
;
5217 /* The conversion is by calculating the offset from the base operand
5218 qualifier for the vector type. The operand qualifiers are regular
5219 enough that the offset can established by shifting the vector width by
5220 a vector-type dependent amount. */
5222 if (vectype
->type
== NT_b
)
5224 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5226 else if (vectype
->type
>= NT_d
)
5231 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5232 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5233 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5237 vectype_conversion_fail
:
5238 first_error (_("bad vector arrangement type"));
5239 return AARCH64_OPND_QLF_NIL
;
5242 /* Process an optional operand that is found omitted from the assembly line.
5243 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5244 instruction's opcode entry while IDX is the index of this omitted operand.
5248 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5249 int idx
, aarch64_opnd_info
*operand
)
5251 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5252 gas_assert (optional_operand_p (opcode
, idx
));
5253 gas_assert (!operand
->present
);
5257 case AARCH64_OPND_Rd
:
5258 case AARCH64_OPND_Rn
:
5259 case AARCH64_OPND_Rm
:
5260 case AARCH64_OPND_Rt
:
5261 case AARCH64_OPND_Rt2
:
5262 case AARCH64_OPND_Rt_SP
:
5263 case AARCH64_OPND_Rs
:
5264 case AARCH64_OPND_Ra
:
5265 case AARCH64_OPND_Rt_SYS
:
5266 case AARCH64_OPND_Rd_SP
:
5267 case AARCH64_OPND_Rn_SP
:
5268 case AARCH64_OPND_Rm_SP
:
5269 case AARCH64_OPND_Fd
:
5270 case AARCH64_OPND_Fn
:
5271 case AARCH64_OPND_Fm
:
5272 case AARCH64_OPND_Fa
:
5273 case AARCH64_OPND_Ft
:
5274 case AARCH64_OPND_Ft2
:
5275 case AARCH64_OPND_Sd
:
5276 case AARCH64_OPND_Sn
:
5277 case AARCH64_OPND_Sm
:
5278 case AARCH64_OPND_Va
:
5279 case AARCH64_OPND_Vd
:
5280 case AARCH64_OPND_Vn
:
5281 case AARCH64_OPND_Vm
:
5282 case AARCH64_OPND_VdD1
:
5283 case AARCH64_OPND_VnD1
:
5284 operand
->reg
.regno
= default_value
;
5287 case AARCH64_OPND_Ed
:
5288 case AARCH64_OPND_En
:
5289 case AARCH64_OPND_Em
:
5290 case AARCH64_OPND_Em16
:
5291 case AARCH64_OPND_SM3_IMM2
:
5292 operand
->reglane
.regno
= default_value
;
5295 case AARCH64_OPND_IDX
:
5296 case AARCH64_OPND_BIT_NUM
:
5297 case AARCH64_OPND_IMMR
:
5298 case AARCH64_OPND_IMMS
:
5299 case AARCH64_OPND_SHLL_IMM
:
5300 case AARCH64_OPND_IMM_VLSL
:
5301 case AARCH64_OPND_IMM_VLSR
:
5302 case AARCH64_OPND_CCMP_IMM
:
5303 case AARCH64_OPND_FBITS
:
5304 case AARCH64_OPND_UIMM4
:
5305 case AARCH64_OPND_UIMM3_OP1
:
5306 case AARCH64_OPND_UIMM3_OP2
:
5307 case AARCH64_OPND_IMM
:
5308 case AARCH64_OPND_IMM_2
:
5309 case AARCH64_OPND_WIDTH
:
5310 case AARCH64_OPND_UIMM7
:
5311 case AARCH64_OPND_NZCV
:
5312 case AARCH64_OPND_SVE_PATTERN
:
5313 case AARCH64_OPND_SVE_PRFOP
:
5314 operand
->imm
.value
= default_value
;
5317 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5318 operand
->imm
.value
= default_value
;
5319 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5320 operand
->shifter
.amount
= 1;
5323 case AARCH64_OPND_EXCEPTION
:
5324 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5327 case AARCH64_OPND_BARRIER_ISB
:
5328 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5331 case AARCH64_OPND_BTI_TARGET
:
5332 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5340 /* Process the relocation type for move wide instructions.
5341 Return TRUE on success; otherwise return FALSE. */
5344 process_movw_reloc_info (void)
5349 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5351 if (inst
.base
.opcode
->op
== OP_MOVK
)
5352 switch (inst
.reloc
.type
)
5354 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5355 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5356 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5357 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5358 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5359 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5360 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5361 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5362 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5363 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5364 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5366 (_("the specified relocation type is not allowed for MOVK"));
5372 switch (inst
.reloc
.type
)
5374 case BFD_RELOC_AARCH64_MOVW_G0
:
5375 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5376 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5377 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5378 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5379 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5380 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5381 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5382 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5383 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5384 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5385 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5386 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5389 case BFD_RELOC_AARCH64_MOVW_G1
:
5390 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5391 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5392 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5393 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5394 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5395 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5396 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5397 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5398 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5399 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5400 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5401 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5404 case BFD_RELOC_AARCH64_MOVW_G2
:
5405 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5406 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5407 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5408 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5409 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5410 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5413 set_fatal_syntax_error
5414 (_("the specified relocation type is not allowed for 32-bit "
5420 case BFD_RELOC_AARCH64_MOVW_G3
:
5421 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5424 set_fatal_syntax_error
5425 (_("the specified relocation type is not allowed for 32-bit "
5432 /* More cases should be added when more MOVW-related relocation types
5433 are supported in GAS. */
5434 gas_assert (aarch64_gas_internal_fixup_p ());
5435 /* The shift amount should have already been set by the parser. */
5438 inst
.base
.operands
[1].shifter
.amount
= shift
;
5442 /* A primitive log calculator. */
5444 static inline unsigned int
5445 get_logsz (unsigned int size
)
5447 const unsigned char ls
[16] =
5448 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5454 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5455 return ls
[size
- 1];
5458 /* Determine and return the real reloc type code for an instruction
5459 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5461 static inline bfd_reloc_code_real_type
5462 ldst_lo12_determine_real_reloc_type (void)
5465 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5466 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5468 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5470 BFD_RELOC_AARCH64_LDST8_LO12
,
5471 BFD_RELOC_AARCH64_LDST16_LO12
,
5472 BFD_RELOC_AARCH64_LDST32_LO12
,
5473 BFD_RELOC_AARCH64_LDST64_LO12
,
5474 BFD_RELOC_AARCH64_LDST128_LO12
5477 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5478 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5479 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5480 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5481 BFD_RELOC_AARCH64_NONE
5484 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5485 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5486 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5487 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5488 BFD_RELOC_AARCH64_NONE
5491 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5492 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5493 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5494 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5495 BFD_RELOC_AARCH64_NONE
5498 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5499 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5500 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5501 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5502 BFD_RELOC_AARCH64_NONE
5506 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5507 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5509 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5511 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5513 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5514 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5516 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5518 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5520 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5522 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5523 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5524 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5525 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5526 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5527 gas_assert (logsz
<= 3);
5529 gas_assert (logsz
<= 4);
5531 /* In reloc.c, these pseudo relocation types should be defined in similar
5532 order as above reloc_ldst_lo12 array. Because the array index calculation
5533 below relies on this. */
5534 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5537 /* Check whether a register list REGINFO is valid. The registers must be
5538 numbered in increasing order (modulo 32), in increments of one or two.
5540 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5543 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5546 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5548 uint32_t i
, nb_regs
, prev_regno
, incr
;
5550 nb_regs
= 1 + (reginfo
& 0x3);
5552 prev_regno
= reginfo
& 0x1f;
5553 incr
= accept_alternate
? 2 : 1;
5555 for (i
= 1; i
< nb_regs
; ++i
)
5557 uint32_t curr_regno
;
5559 curr_regno
= reginfo
& 0x1f;
5560 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5562 prev_regno
= curr_regno
;
5568 /* Generic instruction operand parser. This does no encoding and no
5569 semantic validation; it merely squirrels values away in the inst
5570 structure. Returns TRUE or FALSE depending on whether the
5571 specified grammar matched. */
5574 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5577 char *backtrack_pos
= 0;
5578 const enum aarch64_opnd
*operands
= opcode
->operands
;
5579 aarch64_reg_type imm_reg_type
;
5582 skip_whitespace (str
);
5584 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5585 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5587 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5589 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5592 const reg_entry
*reg
;
5593 int comma_skipped_p
= 0;
5594 aarch64_reg_type rtype
;
5595 struct vector_type_el vectype
;
5596 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5597 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5598 aarch64_reg_type reg_type
;
5600 DEBUG_TRACE ("parse operand %d", i
);
5602 /* Assign the operand code. */
5603 info
->type
= operands
[i
];
5605 if (optional_operand_p (opcode
, i
))
5607 /* Remember where we are in case we need to backtrack. */
5608 gas_assert (!backtrack_pos
);
5609 backtrack_pos
= str
;
5612 /* Expect comma between operands; the backtrack mechanism will take
5613 care of cases of omitted optional operand. */
5614 if (i
> 0 && ! skip_past_char (&str
, ','))
5616 set_syntax_error (_("comma expected between operands"));
5620 comma_skipped_p
= 1;
5622 switch (operands
[i
])
5624 case AARCH64_OPND_Rd
:
5625 case AARCH64_OPND_Rn
:
5626 case AARCH64_OPND_Rm
:
5627 case AARCH64_OPND_Rt
:
5628 case AARCH64_OPND_Rt2
:
5629 case AARCH64_OPND_Rs
:
5630 case AARCH64_OPND_Ra
:
5631 case AARCH64_OPND_Rt_SYS
:
5632 case AARCH64_OPND_PAIRREG
:
5633 case AARCH64_OPND_SVE_Rm
:
5634 po_int_reg_or_fail (REG_TYPE_R_Z
);
5637 case AARCH64_OPND_Rd_SP
:
5638 case AARCH64_OPND_Rn_SP
:
5639 case AARCH64_OPND_Rt_SP
:
5640 case AARCH64_OPND_SVE_Rn_SP
:
5641 case AARCH64_OPND_Rm_SP
:
5642 po_int_reg_or_fail (REG_TYPE_R_SP
);
5645 case AARCH64_OPND_Rm_EXT
:
5646 case AARCH64_OPND_Rm_SFT
:
5647 po_misc_or_fail (parse_shifter_operand
5648 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5650 : SHIFTED_LOGIC_IMM
)));
5651 if (!info
->shifter
.operator_present
)
5653 /* Default to LSL if not present. Libopcodes prefers shifter
5654 kind to be explicit. */
5655 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5656 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5657 /* For Rm_EXT, libopcodes will carry out further check on whether
5658 or not stack pointer is used in the instruction (Recall that
5659 "the extend operator is not optional unless at least one of
5660 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5664 case AARCH64_OPND_Fd
:
5665 case AARCH64_OPND_Fn
:
5666 case AARCH64_OPND_Fm
:
5667 case AARCH64_OPND_Fa
:
5668 case AARCH64_OPND_Ft
:
5669 case AARCH64_OPND_Ft2
:
5670 case AARCH64_OPND_Sd
:
5671 case AARCH64_OPND_Sn
:
5672 case AARCH64_OPND_Sm
:
5673 case AARCH64_OPND_SVE_VZn
:
5674 case AARCH64_OPND_SVE_Vd
:
5675 case AARCH64_OPND_SVE_Vm
:
5676 case AARCH64_OPND_SVE_Vn
:
5677 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5678 if (val
== PARSE_FAIL
)
5680 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5683 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5685 info
->reg
.regno
= val
;
5686 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5689 case AARCH64_OPND_SVE_Pd
:
5690 case AARCH64_OPND_SVE_Pg3
:
5691 case AARCH64_OPND_SVE_Pg4_5
:
5692 case AARCH64_OPND_SVE_Pg4_10
:
5693 case AARCH64_OPND_SVE_Pg4_16
:
5694 case AARCH64_OPND_SVE_Pm
:
5695 case AARCH64_OPND_SVE_Pn
:
5696 case AARCH64_OPND_SVE_Pt
:
5697 reg_type
= REG_TYPE_PN
;
5700 case AARCH64_OPND_SVE_Za_5
:
5701 case AARCH64_OPND_SVE_Za_16
:
5702 case AARCH64_OPND_SVE_Zd
:
5703 case AARCH64_OPND_SVE_Zm_5
:
5704 case AARCH64_OPND_SVE_Zm_16
:
5705 case AARCH64_OPND_SVE_Zn
:
5706 case AARCH64_OPND_SVE_Zt
:
5707 reg_type
= REG_TYPE_ZN
;
5710 case AARCH64_OPND_Va
:
5711 case AARCH64_OPND_Vd
:
5712 case AARCH64_OPND_Vn
:
5713 case AARCH64_OPND_Vm
:
5714 reg_type
= REG_TYPE_VN
;
5716 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5717 if (val
== PARSE_FAIL
)
5719 first_error (_(get_reg_expected_msg (reg_type
)));
5722 if (vectype
.defined
& NTA_HASINDEX
)
5725 info
->reg
.regno
= val
;
5726 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5727 && vectype
.type
== NT_invtype
)
5728 /* Unqualified Pn and Zn registers are allowed in certain
5729 contexts. Rely on F_STRICT qualifier checking to catch
5731 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5734 info
->qualifier
= vectype_to_qualifier (&vectype
);
5735 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5740 case AARCH64_OPND_VdD1
:
5741 case AARCH64_OPND_VnD1
:
5742 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5743 if (val
== PARSE_FAIL
)
5745 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5748 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5750 set_fatal_syntax_error
5751 (_("the top half of a 128-bit FP/SIMD register is expected"));
5754 info
->reg
.regno
= val
;
5755 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5756 here; it is correct for the purpose of encoding/decoding since
5757 only the register number is explicitly encoded in the related
5758 instructions, although this appears a bit hacky. */
5759 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5762 case AARCH64_OPND_SVE_Zm3_INDEX
:
5763 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5764 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5765 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5766 case AARCH64_OPND_SVE_Zm4_INDEX
:
5767 case AARCH64_OPND_SVE_Zn_INDEX
:
5768 reg_type
= REG_TYPE_ZN
;
5769 goto vector_reg_index
;
5771 case AARCH64_OPND_Ed
:
5772 case AARCH64_OPND_En
:
5773 case AARCH64_OPND_Em
:
5774 case AARCH64_OPND_Em16
:
5775 case AARCH64_OPND_SM3_IMM2
:
5776 reg_type
= REG_TYPE_VN
;
5778 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5779 if (val
== PARSE_FAIL
)
5781 first_error (_(get_reg_expected_msg (reg_type
)));
5784 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5787 info
->reglane
.regno
= val
;
5788 info
->reglane
.index
= vectype
.index
;
5789 info
->qualifier
= vectype_to_qualifier (&vectype
);
5790 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5794 case AARCH64_OPND_SVE_ZnxN
:
5795 case AARCH64_OPND_SVE_ZtxN
:
5796 reg_type
= REG_TYPE_ZN
;
5797 goto vector_reg_list
;
5799 case AARCH64_OPND_LVn
:
5800 case AARCH64_OPND_LVt
:
5801 case AARCH64_OPND_LVt_AL
:
5802 case AARCH64_OPND_LEt
:
5803 reg_type
= REG_TYPE_VN
;
5805 if (reg_type
== REG_TYPE_ZN
5806 && get_opcode_dependent_value (opcode
) == 1
5809 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5810 if (val
== PARSE_FAIL
)
5812 first_error (_(get_reg_expected_msg (reg_type
)));
5815 info
->reglist
.first_regno
= val
;
5816 info
->reglist
.num_regs
= 1;
5820 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5821 if (val
== PARSE_FAIL
)
5824 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5826 set_fatal_syntax_error (_("invalid register list"));
5830 if (vectype
.width
!= 0 && *str
!= ',')
5832 set_fatal_syntax_error
5833 (_("expected element type rather than vector type"));
5837 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5838 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5840 if (operands
[i
] == AARCH64_OPND_LEt
)
5842 if (!(vectype
.defined
& NTA_HASINDEX
))
5844 info
->reglist
.has_index
= 1;
5845 info
->reglist
.index
= vectype
.index
;
5849 if (vectype
.defined
& NTA_HASINDEX
)
5851 if (!(vectype
.defined
& NTA_HASTYPE
))
5853 if (reg_type
== REG_TYPE_ZN
)
5854 set_fatal_syntax_error (_("missing type suffix"));
5858 info
->qualifier
= vectype_to_qualifier (&vectype
);
5859 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5863 case AARCH64_OPND_CRn
:
5864 case AARCH64_OPND_CRm
:
5866 char prefix
= *(str
++);
5867 if (prefix
!= 'c' && prefix
!= 'C')
5870 po_imm_nc_or_fail ();
5873 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5876 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5877 info
->imm
.value
= val
;
5881 case AARCH64_OPND_SHLL_IMM
:
5882 case AARCH64_OPND_IMM_VLSR
:
5883 po_imm_or_fail (1, 64);
5884 info
->imm
.value
= val
;
5887 case AARCH64_OPND_CCMP_IMM
:
5888 case AARCH64_OPND_SIMM5
:
5889 case AARCH64_OPND_FBITS
:
5890 case AARCH64_OPND_TME_UIMM16
:
5891 case AARCH64_OPND_UIMM4
:
5892 case AARCH64_OPND_UIMM4_ADDG
:
5893 case AARCH64_OPND_UIMM10
:
5894 case AARCH64_OPND_UIMM3_OP1
:
5895 case AARCH64_OPND_UIMM3_OP2
:
5896 case AARCH64_OPND_IMM_VLSL
:
5897 case AARCH64_OPND_IMM
:
5898 case AARCH64_OPND_IMM_2
:
5899 case AARCH64_OPND_WIDTH
:
5900 case AARCH64_OPND_SVE_INV_LIMM
:
5901 case AARCH64_OPND_SVE_LIMM
:
5902 case AARCH64_OPND_SVE_LIMM_MOV
:
5903 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5904 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5905 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
5906 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5907 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5908 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
5909 case AARCH64_OPND_SVE_SIMM5
:
5910 case AARCH64_OPND_SVE_SIMM5B
:
5911 case AARCH64_OPND_SVE_SIMM6
:
5912 case AARCH64_OPND_SVE_SIMM8
:
5913 case AARCH64_OPND_SVE_UIMM3
:
5914 case AARCH64_OPND_SVE_UIMM7
:
5915 case AARCH64_OPND_SVE_UIMM8
:
5916 case AARCH64_OPND_SVE_UIMM8_53
:
5917 case AARCH64_OPND_IMM_ROT1
:
5918 case AARCH64_OPND_IMM_ROT2
:
5919 case AARCH64_OPND_IMM_ROT3
:
5920 case AARCH64_OPND_SVE_IMM_ROT1
:
5921 case AARCH64_OPND_SVE_IMM_ROT2
:
5922 case AARCH64_OPND_SVE_IMM_ROT3
:
5923 po_imm_nc_or_fail ();
5924 info
->imm
.value
= val
;
5927 case AARCH64_OPND_SVE_AIMM
:
5928 case AARCH64_OPND_SVE_ASIMM
:
5929 po_imm_nc_or_fail ();
5930 info
->imm
.value
= val
;
5931 skip_whitespace (str
);
5932 if (skip_past_comma (&str
))
5933 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5935 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5938 case AARCH64_OPND_SVE_PATTERN
:
5939 po_enum_or_fail (aarch64_sve_pattern_array
);
5940 info
->imm
.value
= val
;
5943 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5944 po_enum_or_fail (aarch64_sve_pattern_array
);
5945 info
->imm
.value
= val
;
5946 if (skip_past_comma (&str
)
5947 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5949 if (!info
->shifter
.operator_present
)
5951 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5952 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5953 info
->shifter
.amount
= 1;
5957 case AARCH64_OPND_SVE_PRFOP
:
5958 po_enum_or_fail (aarch64_sve_prfop_array
);
5959 info
->imm
.value
= val
;
5962 case AARCH64_OPND_UIMM7
:
5963 po_imm_or_fail (0, 127);
5964 info
->imm
.value
= val
;
5967 case AARCH64_OPND_IDX
:
5968 case AARCH64_OPND_MASK
:
5969 case AARCH64_OPND_BIT_NUM
:
5970 case AARCH64_OPND_IMMR
:
5971 case AARCH64_OPND_IMMS
:
5972 po_imm_or_fail (0, 63);
5973 info
->imm
.value
= val
;
5976 case AARCH64_OPND_IMM0
:
5977 po_imm_nc_or_fail ();
5980 set_fatal_syntax_error (_("immediate zero expected"));
5983 info
->imm
.value
= 0;
5986 case AARCH64_OPND_FPIMM0
:
5989 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5990 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5991 it is probably not worth the effort to support it. */
5992 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5995 || !(res2
= parse_constant_immediate (&str
, &val
,
5998 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6000 info
->imm
.value
= 0;
6001 info
->imm
.is_fp
= 1;
6004 set_fatal_syntax_error (_("immediate zero expected"));
6008 case AARCH64_OPND_IMM_MOV
:
6011 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6012 reg_name_p (str
, REG_TYPE_VN
))
6015 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6017 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6018 later. fix_mov_imm_insn will try to determine a machine
6019 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6020 message if the immediate cannot be moved by a single
6022 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6023 inst
.base
.operands
[i
].skip
= 1;
6027 case AARCH64_OPND_SIMD_IMM
:
6028 case AARCH64_OPND_SIMD_IMM_SFT
:
6029 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6031 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6033 /* need_libopcodes_p */ 1,
6036 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6037 shift, we don't check it here; we leave the checking to
6038 the libopcodes (operand_general_constraint_met_p). By
6039 doing this, we achieve better diagnostics. */
6040 if (skip_past_comma (&str
)
6041 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6043 if (!info
->shifter
.operator_present
6044 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6046 /* Default to LSL if not present. Libopcodes prefers shifter
6047 kind to be explicit. */
6048 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6049 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6053 case AARCH64_OPND_FPIMM
:
6054 case AARCH64_OPND_SIMD_FPIMM
:
6055 case AARCH64_OPND_SVE_FPIMM8
:
6060 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6061 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6062 || !aarch64_imm_float_p (qfloat
))
6065 set_fatal_syntax_error (_("invalid floating-point"
6069 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6070 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6074 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6075 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6076 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6081 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6082 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6085 set_fatal_syntax_error (_("invalid floating-point"
6089 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6090 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6094 case AARCH64_OPND_LIMM
:
6095 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6096 SHIFTED_LOGIC_IMM
));
6097 if (info
->shifter
.operator_present
)
6099 set_fatal_syntax_error
6100 (_("shift not allowed for bitmask immediate"));
6103 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6105 /* need_libopcodes_p */ 1,
6109 case AARCH64_OPND_AIMM
:
6110 if (opcode
->op
== OP_ADD
)
6111 /* ADD may have relocation types. */
6112 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6113 SHIFTED_ARITH_IMM
));
6115 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6116 SHIFTED_ARITH_IMM
));
6117 switch (inst
.reloc
.type
)
6119 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6120 info
->shifter
.amount
= 12;
6122 case BFD_RELOC_UNUSED
:
6123 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6124 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6125 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6126 inst
.reloc
.pc_rel
= 0;
6131 info
->imm
.value
= 0;
6132 if (!info
->shifter
.operator_present
)
6134 /* Default to LSL if not present. Libopcodes prefers shifter
6135 kind to be explicit. */
6136 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6137 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6141 case AARCH64_OPND_HALF
:
6143 /* #<imm16> or relocation. */
6144 int internal_fixup_p
;
6145 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6146 if (internal_fixup_p
)
6147 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6148 skip_whitespace (str
);
6149 if (skip_past_comma (&str
))
6151 /* {, LSL #<shift>} */
6152 if (! aarch64_gas_internal_fixup_p ())
6154 set_fatal_syntax_error (_("can't mix relocation modifier "
6155 "with explicit shift"));
6158 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6161 inst
.base
.operands
[i
].shifter
.amount
= 0;
6162 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6163 inst
.base
.operands
[i
].imm
.value
= 0;
6164 if (! process_movw_reloc_info ())
6169 case AARCH64_OPND_EXCEPTION
:
6170 case AARCH64_OPND_UNDEFINED
:
6171 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6173 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6175 /* need_libopcodes_p */ 0,
6179 case AARCH64_OPND_NZCV
:
6181 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6185 info
->imm
.value
= nzcv
->value
;
6188 po_imm_or_fail (0, 15);
6189 info
->imm
.value
= val
;
6193 case AARCH64_OPND_COND
:
6194 case AARCH64_OPND_COND1
:
6199 while (ISALPHA (*str
));
6200 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6201 if (info
->cond
== NULL
)
6203 set_syntax_error (_("invalid condition"));
6206 else if (operands
[i
] == AARCH64_OPND_COND1
6207 && (info
->cond
->value
& 0xe) == 0xe)
6209 /* Do not allow AL or NV. */
6210 set_default_error ();
6216 case AARCH64_OPND_ADDR_ADRP
:
6217 po_misc_or_fail (parse_adrp (&str
));
6218 /* Clear the value as operand needs to be relocated. */
6219 info
->imm
.value
= 0;
6222 case AARCH64_OPND_ADDR_PCREL14
:
6223 case AARCH64_OPND_ADDR_PCREL19
:
6224 case AARCH64_OPND_ADDR_PCREL21
:
6225 case AARCH64_OPND_ADDR_PCREL26
:
6226 po_misc_or_fail (parse_address (&str
, info
));
6227 if (!info
->addr
.pcrel
)
6229 set_syntax_error (_("invalid pc-relative address"));
6232 if (inst
.gen_lit_pool
6233 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6235 /* Only permit "=value" in the literal load instructions.
6236 The literal will be generated by programmer_friendly_fixup. */
6237 set_syntax_error (_("invalid use of \"=immediate\""));
6240 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6242 set_syntax_error (_("unrecognized relocation suffix"));
6245 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6247 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6248 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6252 info
->imm
.value
= 0;
6253 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6254 switch (opcode
->iclass
)
6258 /* e.g. CBZ or B.COND */
6259 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6260 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6264 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6265 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6269 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6271 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6272 : BFD_RELOC_AARCH64_JUMP26
;
6275 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6276 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6279 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6280 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6286 inst
.reloc
.pc_rel
= 1;
6290 case AARCH64_OPND_ADDR_SIMPLE
:
6291 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6293 /* [<Xn|SP>{, #<simm>}] */
6295 /* First use the normal address-parsing routines, to get
6296 the usual syntax errors. */
6297 po_misc_or_fail (parse_address (&str
, info
));
6298 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6299 || !info
->addr
.preind
|| info
->addr
.postind
6300 || info
->addr
.writeback
)
6302 set_syntax_error (_("invalid addressing mode"));
6306 /* Then retry, matching the specific syntax of these addresses. */
6308 po_char_or_fail ('[');
6309 po_reg_or_fail (REG_TYPE_R64_SP
);
6310 /* Accept optional ", #0". */
6311 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6312 && skip_past_char (&str
, ','))
6314 skip_past_char (&str
, '#');
6315 if (! skip_past_char (&str
, '0'))
6317 set_fatal_syntax_error
6318 (_("the optional immediate offset can only be 0"));
6322 po_char_or_fail (']');
6326 case AARCH64_OPND_ADDR_REGOFF
:
6327 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6328 po_misc_or_fail (parse_address (&str
, info
));
6330 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6331 || !info
->addr
.preind
|| info
->addr
.postind
6332 || info
->addr
.writeback
)
6334 set_syntax_error (_("invalid addressing mode"));
6337 if (!info
->shifter
.operator_present
)
6339 /* Default to LSL if not present. Libopcodes prefers shifter
6340 kind to be explicit. */
6341 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6342 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6344 /* Qualifier to be deduced by libopcodes. */
6347 case AARCH64_OPND_ADDR_SIMM7
:
6348 po_misc_or_fail (parse_address (&str
, info
));
6349 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6350 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6352 set_syntax_error (_("invalid addressing mode"));
6355 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6357 set_syntax_error (_("relocation not allowed"));
6360 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6362 /* need_libopcodes_p */ 1,
6366 case AARCH64_OPND_ADDR_SIMM9
:
6367 case AARCH64_OPND_ADDR_SIMM9_2
:
6368 case AARCH64_OPND_ADDR_SIMM11
:
6369 case AARCH64_OPND_ADDR_SIMM13
:
6370 po_misc_or_fail (parse_address (&str
, info
));
6371 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6372 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6373 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6374 && info
->addr
.writeback
))
6376 set_syntax_error (_("invalid addressing mode"));
6379 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6381 set_syntax_error (_("relocation not allowed"));
6384 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6386 /* need_libopcodes_p */ 1,
6390 case AARCH64_OPND_ADDR_SIMM10
:
6391 case AARCH64_OPND_ADDR_OFFSET
:
6392 po_misc_or_fail (parse_address (&str
, info
));
6393 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6394 || !info
->addr
.preind
|| info
->addr
.postind
)
6396 set_syntax_error (_("invalid addressing mode"));
6399 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6401 set_syntax_error (_("relocation not allowed"));
6404 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6406 /* need_libopcodes_p */ 1,
6410 case AARCH64_OPND_ADDR_UIMM12
:
6411 po_misc_or_fail (parse_address (&str
, info
));
6412 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6413 || !info
->addr
.preind
|| info
->addr
.writeback
)
6415 set_syntax_error (_("invalid addressing mode"));
6418 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6419 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6420 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6422 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6424 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6426 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6428 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6429 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6430 /* Leave qualifier to be determined by libopcodes. */
6433 case AARCH64_OPND_SIMD_ADDR_POST
:
6434 /* [<Xn|SP>], <Xm|#<amount>> */
6435 po_misc_or_fail (parse_address (&str
, info
));
6436 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6438 set_syntax_error (_("invalid addressing mode"));
6441 if (!info
->addr
.offset
.is_reg
)
6443 if (inst
.reloc
.exp
.X_op
== O_constant
)
6444 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6447 set_fatal_syntax_error
6448 (_("writeback value must be an immediate constant"));
6455 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6456 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
6457 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6458 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6459 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6460 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6461 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6462 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6463 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6464 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6465 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6466 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6467 /* [X<n>{, #imm, MUL VL}]
6469 but recognizing SVE registers. */
6470 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6471 &offset_qualifier
));
6472 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6474 set_syntax_error (_("invalid addressing mode"));
6478 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6479 || !info
->addr
.preind
|| info
->addr
.writeback
)
6481 set_syntax_error (_("invalid addressing mode"));
6484 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6485 || inst
.reloc
.exp
.X_op
!= O_constant
)
6487 /* Make sure this has priority over
6488 "invalid addressing mode". */
6489 set_fatal_syntax_error (_("constant offset required"));
6492 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6495 case AARCH64_OPND_SVE_ADDR_R
:
6496 /* [<Xn|SP>{, <R><m>}]
6497 but recognizing SVE registers. */
6498 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6499 &offset_qualifier
));
6500 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6502 offset_qualifier
= AARCH64_OPND_QLF_X
;
6503 info
->addr
.offset
.is_reg
= 1;
6504 info
->addr
.offset
.regno
= 31;
6506 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6507 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6509 set_syntax_error (_("invalid addressing mode"));
6514 case AARCH64_OPND_SVE_ADDR_RR
:
6515 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6516 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6517 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6518 case AARCH64_OPND_SVE_ADDR_RX
:
6519 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6520 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6521 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6522 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6523 but recognizing SVE registers. */
6524 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6525 &offset_qualifier
));
6526 if (base_qualifier
!= AARCH64_OPND_QLF_X
6527 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6529 set_syntax_error (_("invalid addressing mode"));
6534 case AARCH64_OPND_SVE_ADDR_RZ
:
6535 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6536 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6537 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6538 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6539 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6540 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6541 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6542 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6543 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6544 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6545 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6546 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6547 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6548 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6549 &offset_qualifier
));
6550 if (base_qualifier
!= AARCH64_OPND_QLF_X
6551 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6552 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6554 set_syntax_error (_("invalid addressing mode"));
6557 info
->qualifier
= offset_qualifier
;
6560 case AARCH64_OPND_SVE_ADDR_ZX
:
6561 /* [Zn.<T>{, <Xm>}]. */
6562 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6563 &offset_qualifier
));
6565 base_qualifier either S_S or S_D
6566 offset_qualifier must be X
6568 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6569 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6570 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6572 set_syntax_error (_("invalid addressing mode"));
6575 info
->qualifier
= base_qualifier
;
6576 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6577 || !info
->addr
.preind
|| info
->addr
.writeback
6578 || info
->shifter
.operator_present
!= 0)
6580 set_syntax_error (_("invalid addressing mode"));
6583 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6587 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6588 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6589 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6590 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6591 /* [Z<n>.<T>{, #imm}] */
6592 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6593 &offset_qualifier
));
6594 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6595 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6597 set_syntax_error (_("invalid addressing mode"));
6600 info
->qualifier
= base_qualifier
;
6603 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6604 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6605 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6606 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6607 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6611 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6613 here since we get better error messages by leaving it to
6614 the qualifier checking routines. */
6615 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6616 &offset_qualifier
));
6617 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6618 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6619 || offset_qualifier
!= base_qualifier
)
6621 set_syntax_error (_("invalid addressing mode"));
6624 info
->qualifier
= base_qualifier
;
6627 case AARCH64_OPND_SYSREG
:
6629 uint32_t sysreg_flags
;
6630 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6631 &sysreg_flags
)) == PARSE_FAIL
)
6633 set_syntax_error (_("unknown or missing system register name"));
6636 inst
.base
.operands
[i
].sysreg
.value
= val
;
6637 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6641 case AARCH64_OPND_PSTATEFIELD
:
6642 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6645 set_syntax_error (_("unknown or missing PSTATE field name"));
6648 inst
.base
.operands
[i
].pstatefield
= val
;
6651 case AARCH64_OPND_SYSREG_IC
:
6652 inst
.base
.operands
[i
].sysins_op
=
6653 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6656 case AARCH64_OPND_SYSREG_DC
:
6657 inst
.base
.operands
[i
].sysins_op
=
6658 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6661 case AARCH64_OPND_SYSREG_AT
:
6662 inst
.base
.operands
[i
].sysins_op
=
6663 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6666 case AARCH64_OPND_SYSREG_SR
:
6667 inst
.base
.operands
[i
].sysins_op
=
6668 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6671 case AARCH64_OPND_SYSREG_TLBI
:
6672 inst
.base
.operands
[i
].sysins_op
=
6673 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6675 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6677 set_fatal_syntax_error ( _("unknown or missing operation name"));
6682 case AARCH64_OPND_BARRIER
:
6683 case AARCH64_OPND_BARRIER_ISB
:
6684 val
= parse_barrier (&str
);
6685 if (val
!= PARSE_FAIL
6686 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6688 /* ISB only accepts options name 'sy'. */
6690 (_("the specified option is not accepted in ISB"));
6691 /* Turn off backtrack as this optional operand is present. */
6695 /* This is an extension to accept a 0..15 immediate. */
6696 if (val
== PARSE_FAIL
)
6697 po_imm_or_fail (0, 15);
6698 info
->barrier
= aarch64_barrier_options
+ val
;
6701 case AARCH64_OPND_PRFOP
:
6702 val
= parse_pldop (&str
);
6703 /* This is an extension to accept a 0..31 immediate. */
6704 if (val
== PARSE_FAIL
)
6705 po_imm_or_fail (0, 31);
6706 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6709 case AARCH64_OPND_BARRIER_PSB
:
6710 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6711 if (val
== PARSE_FAIL
)
6715 case AARCH64_OPND_BTI_TARGET
:
6716 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6717 if (val
== PARSE_FAIL
)
6722 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6725 /* If we get here, this operand was successfully parsed. */
6726 inst
.base
.operands
[i
].present
= 1;
6730 /* The parse routine should already have set the error, but in case
6731 not, set a default one here. */
6733 set_default_error ();
6735 if (! backtrack_pos
)
6736 goto parse_operands_return
;
6739 /* We reach here because this operand is marked as optional, and
6740 either no operand was supplied or the operand was supplied but it
6741 was syntactically incorrect. In the latter case we report an
6742 error. In the former case we perform a few more checks before
6743 dropping through to the code to insert the default operand. */
6745 char *tmp
= backtrack_pos
;
6746 char endchar
= END_OF_INSN
;
6748 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6750 skip_past_char (&tmp
, ',');
6752 if (*tmp
!= endchar
)
6753 /* The user has supplied an operand in the wrong format. */
6754 goto parse_operands_return
;
6756 /* Make sure there is not a comma before the optional operand.
6757 For example the fifth operand of 'sys' is optional:
6759 sys #0,c0,c0,#0, <--- wrong
6760 sys #0,c0,c0,#0 <--- correct. */
6761 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6763 set_fatal_syntax_error
6764 (_("unexpected comma before the omitted optional operand"));
6765 goto parse_operands_return
;
6769 /* Reaching here means we are dealing with an optional operand that is
6770 omitted from the assembly line. */
6771 gas_assert (optional_operand_p (opcode
, i
));
6773 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6775 /* Try again, skipping the optional operand at backtrack_pos. */
6776 str
= backtrack_pos
;
6779 /* Clear any error record after the omitted optional operand has been
6780 successfully handled. */
6784 /* Check if we have parsed all the operands. */
6785 if (*str
!= '\0' && ! error_p ())
6787 /* Set I to the index of the last present operand; this is
6788 for the purpose of diagnostics. */
6789 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6791 set_fatal_syntax_error
6792 (_("unexpected characters following instruction"));
6795 parse_operands_return
:
6799 DEBUG_TRACE ("parsing FAIL: %s - %s",
6800 operand_mismatch_kind_names
[get_error_kind ()],
6801 get_error_message ());
6802 /* Record the operand error properly; this is useful when there
6803 are multiple instruction templates for a mnemonic name, so that
6804 later on, we can select the error that most closely describes
6806 record_operand_error (opcode
, i
, get_error_kind (),
6807 get_error_message ());
6812 DEBUG_TRACE ("parsing SUCCESS");
6817 /* It does some fix-up to provide some programmer friendly feature while
6818 keeping the libopcodes happy, i.e. libopcodes only accepts
6819 the preferred architectural syntax.
6820 Return FALSE if there is any failure; otherwise return TRUE. */
6823 programmer_friendly_fixup (aarch64_instruction
*instr
)
6825 aarch64_inst
*base
= &instr
->base
;
6826 const aarch64_opcode
*opcode
= base
->opcode
;
6827 enum aarch64_op op
= opcode
->op
;
6828 aarch64_opnd_info
*operands
= base
->operands
;
6830 DEBUG_TRACE ("enter");
6832 switch (opcode
->iclass
)
6835 /* TBNZ Xn|Wn, #uimm6, label
6836 Test and Branch Not Zero: conditionally jumps to label if bit number
6837 uimm6 in register Xn is not zero. The bit number implies the width of
6838 the register, which may be written and should be disassembled as Wn if
6839 uimm is less than 32. */
6840 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6842 if (operands
[1].imm
.value
>= 32)
6844 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6848 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6852 /* LDR Wt, label | =value
6853 As a convenience assemblers will typically permit the notation
6854 "=value" in conjunction with the pc-relative literal load instructions
6855 to automatically place an immediate value or symbolic address in a
6856 nearby literal pool and generate a hidden label which references it.
6857 ISREG has been set to 0 in the case of =value. */
6858 if (instr
->gen_lit_pool
6859 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6861 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6862 if (op
== OP_LDRSW_LIT
)
6864 if (instr
->reloc
.exp
.X_op
!= O_constant
6865 && instr
->reloc
.exp
.X_op
!= O_big
6866 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6868 record_operand_error (opcode
, 1,
6869 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6870 _("constant expression expected"));
6873 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6875 record_operand_error (opcode
, 1,
6876 AARCH64_OPDE_OTHER_ERROR
,
6877 _("literal pool insertion failed"));
6885 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6886 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6887 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6888 A programmer-friendly assembler should accept a destination Xd in
6889 place of Wd, however that is not the preferred form for disassembly.
6891 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6892 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6893 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6894 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6899 /* In the 64-bit form, the final register operand is written as Wm
6900 for all but the (possibly omitted) UXTX/LSL and SXTX
6902 As a programmer-friendly assembler, we accept e.g.
6903 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6904 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6905 int idx
= aarch64_operand_index (opcode
->operands
,
6906 AARCH64_OPND_Rm_EXT
);
6907 gas_assert (idx
== 1 || idx
== 2);
6908 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6909 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6910 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6911 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6912 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6913 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6921 DEBUG_TRACE ("exit with SUCCESS");
6925 /* Check for loads and stores that will cause unpredictable behavior. */
6928 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6930 aarch64_inst
*base
= &instr
->base
;
6931 const aarch64_opcode
*opcode
= base
->opcode
;
6932 const aarch64_opnd_info
*opnds
= base
->operands
;
6933 switch (opcode
->iclass
)
6940 /* Loading/storing the base register is unpredictable if writeback. */
6941 if ((aarch64_get_operand_class (opnds
[0].type
)
6942 == AARCH64_OPND_CLASS_INT_REG
)
6943 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6944 && opnds
[1].addr
.base_regno
!= REG_SP
6945 /* Exempt STG/STZG/ST2G/STZ2G. */
6946 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
6947 && opnds
[1].addr
.writeback
)
6948 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6952 case ldstnapair_offs
:
6953 case ldstpair_indexed
:
6954 /* Loading/storing the base register is unpredictable if writeback. */
6955 if ((aarch64_get_operand_class (opnds
[0].type
)
6956 == AARCH64_OPND_CLASS_INT_REG
)
6957 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6958 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6959 && opnds
[2].addr
.base_regno
!= REG_SP
6961 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
6962 && opnds
[2].addr
.writeback
)
6963 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6964 /* Load operations must load different registers. */
6965 if ((opcode
->opcode
& (1 << 22))
6966 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6967 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6971 /* It is unpredictable if the destination and status registers are the
6973 if ((aarch64_get_operand_class (opnds
[0].type
)
6974 == AARCH64_OPND_CLASS_INT_REG
)
6975 && (aarch64_get_operand_class (opnds
[1].type
)
6976 == AARCH64_OPND_CLASS_INT_REG
)
6977 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6978 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6979 as_warn (_("unpredictable: identical transfer and status registers"
6991 force_automatic_sequence_close (void)
6993 if (now_instr_sequence
.instr
)
6995 as_warn (_("previous `%s' sequence has not been closed"),
6996 now_instr_sequence
.instr
->opcode
->name
);
6997 init_insn_sequence (NULL
, &now_instr_sequence
);
7001 /* A wrapper function to interface with libopcodes on encoding and
7002 record the error message if there is any.
7004 Return TRUE on success; otherwise return FALSE. */
7007 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7010 aarch64_operand_error error_info
;
7011 memset (&error_info
, '\0', sizeof (error_info
));
7012 error_info
.kind
= AARCH64_OPDE_NIL
;
7013 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7014 && !error_info
.non_fatal
)
7017 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7018 record_operand_error_info (opcode
, &error_info
);
7019 return error_info
.non_fatal
;
7022 #ifdef DEBUG_AARCH64
7024 dump_opcode_operands (const aarch64_opcode
*opcode
)
7027 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7029 aarch64_verbose ("\t\t opnd%d: %s", i
,
7030 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7031 ? aarch64_get_operand_name (opcode
->operands
[i
])
7032 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7036 #endif /* DEBUG_AARCH64 */
7038 /* This is the guts of the machine-dependent assembler. STR points to a
7039 machine dependent instruction. This function is supposed to emit
7040 the frags/bytes it assembles to. */
7043 md_assemble (char *str
)
7046 templates
*template;
7047 aarch64_opcode
*opcode
;
7048 aarch64_inst
*inst_base
;
7049 unsigned saved_cond
;
7051 /* Align the previous label if needed. */
7052 if (last_label_seen
!= NULL
)
7054 symbol_set_frag (last_label_seen
, frag_now
);
7055 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7056 S_SET_SEGMENT (last_label_seen
, now_seg
);
7059 /* Update the current insn_sequence from the segment. */
7060 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7062 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7064 DEBUG_TRACE ("\n\n");
7065 DEBUG_TRACE ("==============================");
7066 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7068 template = opcode_lookup (&p
);
7071 /* It wasn't an instruction, but it might be a register alias of
7072 the form alias .req reg directive. */
7073 if (!create_register_alias (str
, p
))
7074 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7079 skip_whitespace (p
);
7082 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7083 get_mnemonic_name (str
), str
);
7087 init_operand_error_report ();
7089 /* Sections are assumed to start aligned. In executable section, there is no
7090 MAP_DATA symbol pending. So we only align the address during
7091 MAP_DATA --> MAP_INSN transition.
7092 For other sections, this is not guaranteed. */
7093 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7094 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7095 frag_align_code (2, 0);
7097 saved_cond
= inst
.cond
;
7098 reset_aarch64_instruction (&inst
);
7099 inst
.cond
= saved_cond
;
7101 /* Iterate through all opcode entries with the same mnemonic name. */
7104 opcode
= template->opcode
;
7106 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7107 #ifdef DEBUG_AARCH64
7109 dump_opcode_operands (opcode
);
7110 #endif /* DEBUG_AARCH64 */
7112 mapping_state (MAP_INSN
);
7114 inst_base
= &inst
.base
;
7115 inst_base
->opcode
= opcode
;
7117 /* Truly conditionally executed instructions, e.g. b.cond. */
7118 if (opcode
->flags
& F_COND
)
7120 gas_assert (inst
.cond
!= COND_ALWAYS
);
7121 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7122 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7124 else if (inst
.cond
!= COND_ALWAYS
)
7126 /* It shouldn't arrive here, where the assembly looks like a
7127 conditional instruction but the found opcode is unconditional. */
7132 if (parse_operands (p
, opcode
)
7133 && programmer_friendly_fixup (&inst
)
7134 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7136 /* Check that this instruction is supported for this CPU. */
7137 if (!opcode
->avariant
7138 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7140 as_bad (_("selected processor does not support `%s'"), str
);
7144 warn_unpredictable_ldst (&inst
, str
);
7146 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7147 || !inst
.reloc
.need_libopcodes_p
)
7151 /* If there is relocation generated for the instruction,
7152 store the instruction information for the future fix-up. */
7153 struct aarch64_inst
*copy
;
7154 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7155 copy
= XNEW (struct aarch64_inst
);
7156 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7160 /* Issue non-fatal messages if any. */
7161 output_operand_error_report (str
, TRUE
);
7165 template = template->next
;
7166 if (template != NULL
)
7168 reset_aarch64_instruction (&inst
);
7169 inst
.cond
= saved_cond
;
7172 while (template != NULL
);
7174 /* Issue the error messages if any. */
7175 output_operand_error_report (str
, FALSE
);
7178 /* Various frobbings of labels and their addresses. */
7181 aarch64_start_line_hook (void)
7183 last_label_seen
= NULL
;
7187 aarch64_frob_label (symbolS
* sym
)
7189 last_label_seen
= sym
;
7191 dwarf2_emit_label (sym
);
7195 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7197 /* Check to see if we have a block to close. */
7198 force_automatic_sequence_close ();
7202 aarch64_data_in_code (void)
7204 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7206 *input_line_pointer
= '/';
7207 input_line_pointer
+= 5;
7208 *input_line_pointer
= 0;
7216 aarch64_canonicalize_symbol_name (char *name
)
7220 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7221 *(name
+ len
- 5) = 0;
7226 /* Table of all register names defined by default. The user can
7227 define additional names with .req. Note that all register names
7228 should appear in both upper and lowercase variants. Some registers
7229 also have mixed-case names. */
7231 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7232 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7233 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7234 #define REGSET16(p,t) \
7235 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7236 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7237 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7238 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7239 #define REGSET31(p,t) \
7241 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7242 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7243 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7244 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7245 #define REGSET(p,t) \
7246 REGSET31(p,t), REGNUM(p,31,t)
7248 /* These go into aarch64_reg_hsh hash-table. */
7249 static const reg_entry reg_names
[] = {
7250 /* Integer registers. */
7251 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7252 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7254 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7255 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7256 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7257 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7258 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7259 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7261 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7262 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7264 /* Floating-point single precision registers. */
7265 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7267 /* Floating-point double precision registers. */
7268 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7270 /* Floating-point half precision registers. */
7271 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7273 /* Floating-point byte precision registers. */
7274 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7276 /* Floating-point quad precision registers. */
7277 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7279 /* FP/SIMD registers. */
7280 REGSET (v
, VN
), REGSET (V
, VN
),
7282 /* SVE vector registers. */
7283 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7285 /* SVE predicate registers. */
7286 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7304 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7305 static const asm_nzcv nzcv_names
[] = {
7306 {"nzcv", B (n
, z
, c
, v
)},
7307 {"nzcV", B (n
, z
, c
, V
)},
7308 {"nzCv", B (n
, z
, C
, v
)},
7309 {"nzCV", B (n
, z
, C
, V
)},
7310 {"nZcv", B (n
, Z
, c
, v
)},
7311 {"nZcV", B (n
, Z
, c
, V
)},
7312 {"nZCv", B (n
, Z
, C
, v
)},
7313 {"nZCV", B (n
, Z
, C
, V
)},
7314 {"Nzcv", B (N
, z
, c
, v
)},
7315 {"NzcV", B (N
, z
, c
, V
)},
7316 {"NzCv", B (N
, z
, C
, v
)},
7317 {"NzCV", B (N
, z
, C
, V
)},
7318 {"NZcv", B (N
, Z
, c
, v
)},
7319 {"NZcV", B (N
, Z
, c
, V
)},
7320 {"NZCv", B (N
, Z
, C
, v
)},
7321 {"NZCV", B (N
, Z
, C
, V
)}
7334 /* MD interface: bits in the object file. */
7336 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7337 for use in the a.out file, and stores them in the array pointed to by buf.
7338 This knows about the endian-ness of the target machine and does
7339 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7340 2 (short) and 4 (long) Floating numbers are put out as a series of
7341 LITTLENUMS (shorts, here at least). */
7344 md_number_to_chars (char *buf
, valueT val
, int n
)
7346 if (target_big_endian
)
7347 number_to_chars_bigendian (buf
, val
, n
);
7349 number_to_chars_littleendian (buf
, val
, n
);
7352 /* MD interface: Sections. */
7354 /* Estimate the size of a frag before relaxing. Assume everything fits in
7358 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7364 /* Round up a section size to the appropriate boundary. */
7367 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7372 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7373 of an rs_align_code fragment.
7375 Here we fill the frag with the appropriate info for padding the
7376 output stream. The resulting frag will consist of a fixed (fr_fix)
7377 and of a repeating (fr_var) part.
7379 The fixed content is always emitted before the repeating content and
7380 these two parts are used as follows in constructing the output:
7381 - the fixed part will be used to align to a valid instruction word
7382 boundary, in case that we start at a misaligned address; as no
7383 executable instruction can live at the misaligned location, we
7384 simply fill with zeros;
7385 - the variable part will be used to cover the remaining padding and
7386 we fill using the AArch64 NOP instruction.
7388 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7389 enough storage space for up to 3 bytes for padding the back to a valid
7390 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7393 aarch64_handle_align (fragS
* fragP
)
7395 /* NOP = d503201f */
7396 /* AArch64 instructions are always little-endian. */
7397 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7399 int bytes
, fix
, noop_size
;
7402 if (fragP
->fr_type
!= rs_align_code
)
7405 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7406 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7409 gas_assert (fragP
->tc_frag_data
.recorded
);
7412 noop_size
= sizeof (aarch64_noop
);
7414 fix
= bytes
& (noop_size
- 1);
7418 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7422 fragP
->fr_fix
+= fix
;
7426 memcpy (p
, aarch64_noop
, noop_size
);
7427 fragP
->fr_var
= noop_size
;
7430 /* Perform target specific initialisation of a frag.
7431 Note - despite the name this initialisation is not done when the frag
7432 is created, but only when its type is assigned. A frag can be created
7433 and used a long time before its type is set, so beware of assuming that
7434 this initialisation is performed first. */
7438 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7439 int max_chars ATTRIBUTE_UNUSED
)
7443 #else /* OBJ_ELF is defined. */
7445 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7447 /* Record a mapping symbol for alignment frags. We will delete this
7448 later if the alignment ends up empty. */
7449 if (!fragP
->tc_frag_data
.recorded
)
7450 fragP
->tc_frag_data
.recorded
= 1;
7452 /* PR 21809: Do not set a mapping state for debug sections
7453 - it just confuses other tools. */
7454 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7457 switch (fragP
->fr_type
)
7461 mapping_state_2 (MAP_DATA
, max_chars
);
7464 /* PR 20364: We can get alignment frags in code sections,
7465 so do not just assume that we should use the MAP_DATA state. */
7466 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7469 mapping_state_2 (MAP_INSN
, max_chars
);
7476 /* Initialize the DWARF-2 unwind information for this procedure. */
7479 tc_aarch64_frame_initial_instructions (void)
7481 cfi_add_CFA_def_cfa (REG_SP
, 0);
7483 #endif /* OBJ_ELF */
7485 /* Convert REGNAME to a DWARF-2 register number. */
7488 tc_aarch64_regname_to_dw2regnum (char *regname
)
7490 const reg_entry
*reg
= parse_reg (®name
);
7496 case REG_TYPE_SP_32
:
7497 case REG_TYPE_SP_64
:
7507 return reg
->number
+ 64;
7515 /* Implement DWARF2_ADDR_SIZE. */
7518 aarch64_dwarf2_addr_size (void)
7520 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7524 return bfd_arch_bits_per_address (stdoutput
) / 8;
7527 /* MD interface: Symbol and relocation handling. */
7529 /* Return the address within the segment that a PC-relative fixup is
7530 relative to. For AArch64 PC-relative fixups applied to instructions
7531 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7534 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7536 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7538 /* If this is pc-relative and we are going to emit a relocation
7539 then we just want to put out any pipeline compensation that the linker
7540 will need. Otherwise we want to use the calculated base. */
7542 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7543 || aarch64_force_relocation (fixP
)))
7546 /* AArch64 should be consistent for all pc-relative relocations. */
7547 return base
+ AARCH64_PCREL_OFFSET
;
7550 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7551 Otherwise we have no need to default values of symbols. */
7554 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7557 if (name
[0] == '_' && name
[1] == 'G'
7558 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7562 if (symbol_find (name
))
7563 as_bad (_("GOT already in the symbol table"));
7565 GOT_symbol
= symbol_new (name
, undefined_section
,
7566 &zero_address_frag
, 0);
7576 /* Return non-zero if the indicated VALUE has overflowed the maximum
7577 range expressible by a unsigned number with the indicated number of
7581 unsigned_overflow (valueT value
, unsigned bits
)
7584 if (bits
>= sizeof (valueT
) * 8)
7586 lim
= (valueT
) 1 << bits
;
7587 return (value
>= lim
);
7591 /* Return non-zero if the indicated VALUE has overflowed the maximum
7592 range expressible by an signed number with the indicated number of
7596 signed_overflow (offsetT value
, unsigned bits
)
7599 if (bits
>= sizeof (offsetT
) * 8)
7601 lim
= (offsetT
) 1 << (bits
- 1);
7602 return (value
< -lim
|| value
>= lim
);
7605 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7606 unsigned immediate offset load/store instruction, try to encode it as
7607 an unscaled, 9-bit, signed immediate offset load/store instruction.
7608 Return TRUE if it is successful; otherwise return FALSE.
7610 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7611 in response to the standard LDR/STR mnemonics when the immediate offset is
7612 unambiguous, i.e. when it is negative or unaligned. */
7615 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7618 enum aarch64_op new_op
;
7619 const aarch64_opcode
*new_opcode
;
7621 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7623 switch (instr
->opcode
->op
)
7625 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7626 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7627 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7628 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7629 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7630 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7631 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7632 case OP_STR_POS
: new_op
= OP_STUR
; break;
7633 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7634 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7635 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7636 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7637 default: new_op
= OP_NIL
; break;
7640 if (new_op
== OP_NIL
)
7643 new_opcode
= aarch64_get_opcode (new_op
);
7644 gas_assert (new_opcode
!= NULL
);
7646 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7647 instr
->opcode
->op
, new_opcode
->op
);
7649 aarch64_replace_opcode (instr
, new_opcode
);
7651 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7652 qualifier matching may fail because the out-of-date qualifier will
7653 prevent the operand being updated with a new and correct qualifier. */
7654 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7655 AARCH64_OPND_ADDR_SIMM9
);
7656 gas_assert (idx
== 1);
7657 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7659 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7661 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7668 /* Called by fix_insn to fix a MOV immediate alias instruction.
7670 Operand for a generic move immediate instruction, which is an alias
7671 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7672 a 32-bit/64-bit immediate value into general register. An assembler error
7673 shall result if the immediate cannot be created by a single one of these
7674 instructions. If there is a choice, then to ensure reversability an
7675 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7678 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7680 const aarch64_opcode
*opcode
;
7682 /* Need to check if the destination is SP/ZR. The check has to be done
7683 before any aarch64_replace_opcode. */
7684 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7685 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7687 instr
->operands
[1].imm
.value
= value
;
7688 instr
->operands
[1].skip
= 0;
7692 /* Try the MOVZ alias. */
7693 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7694 aarch64_replace_opcode (instr
, opcode
);
7695 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7696 &instr
->value
, NULL
, NULL
, insn_sequence
))
7698 put_aarch64_insn (buf
, instr
->value
);
7701 /* Try the MOVK alias. */
7702 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7703 aarch64_replace_opcode (instr
, opcode
);
7704 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7705 &instr
->value
, NULL
, NULL
, insn_sequence
))
7707 put_aarch64_insn (buf
, instr
->value
);
7712 if (try_mov_bitmask_p
)
7714 /* Try the ORR alias. */
7715 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7716 aarch64_replace_opcode (instr
, opcode
);
7717 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7718 &instr
->value
, NULL
, NULL
, insn_sequence
))
7720 put_aarch64_insn (buf
, instr
->value
);
7725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7726 _("immediate cannot be moved by a single instruction"));
7729 /* An instruction operand which is immediate related may have symbol used
7730 in the assembly, e.g.
7733 .set u32, 0x00ffff00
7735 At the time when the assembly instruction is parsed, a referenced symbol,
7736 like 'u32' in the above example may not have been seen; a fixS is created
7737 in such a case and is handled here after symbols have been resolved.
7738 Instruction is fixed up with VALUE using the information in *FIXP plus
7739 extra information in FLAGS.
7741 This function is called by md_apply_fix to fix up instructions that need
7742 a fix-up described above but does not involve any linker-time relocation. */
7745 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7749 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7750 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7751 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7755 /* Now the instruction is about to be fixed-up, so the operand that
7756 was previously marked as 'ignored' needs to be unmarked in order
7757 to get the encoding done properly. */
7758 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7759 new_inst
->operands
[idx
].skip
= 0;
7762 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7766 case AARCH64_OPND_EXCEPTION
:
7767 case AARCH64_OPND_UNDEFINED
:
7768 if (unsigned_overflow (value
, 16))
7769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7770 _("immediate out of range"));
7771 insn
= get_aarch64_insn (buf
);
7772 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
7773 put_aarch64_insn (buf
, insn
);
7776 case AARCH64_OPND_AIMM
:
7777 /* ADD or SUB with immediate.
7778 NOTE this assumes we come here with a add/sub shifted reg encoding
7779 3 322|2222|2 2 2 21111 111111
7780 1 098|7654|3 2 1 09876 543210 98765 43210
7781 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7782 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7783 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7784 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7786 3 322|2222|2 2 221111111111
7787 1 098|7654|3 2 109876543210 98765 43210
7788 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7789 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7790 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7791 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7792 Fields sf Rn Rd are already set. */
7793 insn
= get_aarch64_insn (buf
);
7797 insn
= reencode_addsub_switch_add_sub (insn
);
7801 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7802 && unsigned_overflow (value
, 12))
7804 /* Try to shift the value by 12 to make it fit. */
7805 if (((value
>> 12) << 12) == value
7806 && ! unsigned_overflow (value
, 12 + 12))
7809 insn
|= encode_addsub_imm_shift_amount (1);
7813 if (unsigned_overflow (value
, 12))
7814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7815 _("immediate out of range"));
7817 insn
|= encode_addsub_imm (value
);
7819 put_aarch64_insn (buf
, insn
);
7822 case AARCH64_OPND_SIMD_IMM
:
7823 case AARCH64_OPND_SIMD_IMM_SFT
:
7824 case AARCH64_OPND_LIMM
:
7825 /* Bit mask immediate. */
7826 gas_assert (new_inst
!= NULL
);
7827 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7828 new_inst
->operands
[idx
].imm
.value
= value
;
7829 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7830 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7831 put_aarch64_insn (buf
, new_inst
->value
);
7833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7834 _("invalid immediate"));
7837 case AARCH64_OPND_HALF
:
7838 /* 16-bit unsigned immediate. */
7839 if (unsigned_overflow (value
, 16))
7840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7841 _("immediate out of range"));
7842 insn
= get_aarch64_insn (buf
);
7843 insn
|= encode_movw_imm (value
& 0xffff);
7844 put_aarch64_insn (buf
, insn
);
7847 case AARCH64_OPND_IMM_MOV
:
7848 /* Operand for a generic move immediate instruction, which is
7849 an alias instruction that generates a single MOVZ, MOVN or ORR
7850 instruction to loads a 32-bit/64-bit immediate value into general
7851 register. An assembler error shall result if the immediate cannot be
7852 created by a single one of these instructions. If there is a choice,
7853 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7854 and MOVZ or MOVN to ORR. */
7855 gas_assert (new_inst
!= NULL
);
7856 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7859 case AARCH64_OPND_ADDR_SIMM7
:
7860 case AARCH64_OPND_ADDR_SIMM9
:
7861 case AARCH64_OPND_ADDR_SIMM9_2
:
7862 case AARCH64_OPND_ADDR_SIMM10
:
7863 case AARCH64_OPND_ADDR_UIMM12
:
7864 case AARCH64_OPND_ADDR_SIMM11
:
7865 case AARCH64_OPND_ADDR_SIMM13
:
7866 /* Immediate offset in an address. */
7867 insn
= get_aarch64_insn (buf
);
7869 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7870 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7871 || new_inst
->opcode
->operands
[2] == opnd
);
7873 /* Get the index of the address operand. */
7874 if (new_inst
->opcode
->operands
[1] == opnd
)
7875 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7878 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7881 /* Update the resolved offset value. */
7882 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7884 /* Encode/fix-up. */
7885 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7886 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7888 put_aarch64_insn (buf
, new_inst
->value
);
7891 else if (new_inst
->opcode
->iclass
== ldst_pos
7892 && try_to_encode_as_unscaled_ldst (new_inst
))
7894 put_aarch64_insn (buf
, new_inst
->value
);
7898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7899 _("immediate offset out of range"));
7904 as_fatal (_("unhandled operand code %d"), opnd
);
7908 /* Apply a fixup (fixP) to segment data, once it has been determined
7909 by our caller that we have all the info we need to fix it up.
7911 Parameter valP is the pointer to the value of the bits. */
7914 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7916 offsetT value
= *valP
;
7918 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7920 unsigned flags
= fixP
->fx_addnumber
;
7922 DEBUG_TRACE ("\n\n");
7923 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7924 DEBUG_TRACE ("Enter md_apply_fix");
7926 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7928 /* Note whether this will delete the relocation. */
7930 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7933 /* Process the relocations. */
7934 switch (fixP
->fx_r_type
)
7936 case BFD_RELOC_NONE
:
7937 /* This will need to go in the object file. */
7942 case BFD_RELOC_8_PCREL
:
7943 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7944 md_number_to_chars (buf
, value
, 1);
7948 case BFD_RELOC_16_PCREL
:
7949 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7950 md_number_to_chars (buf
, value
, 2);
7954 case BFD_RELOC_32_PCREL
:
7955 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7956 md_number_to_chars (buf
, value
, 4);
7960 case BFD_RELOC_64_PCREL
:
7961 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7962 md_number_to_chars (buf
, value
, 8);
7965 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7966 /* We claim that these fixups have been processed here, even if
7967 in fact we generate an error because we do not have a reloc
7968 for them, so tc_gen_reloc() will reject them. */
7970 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7973 _("undefined symbol %s used as an immediate value"),
7974 S_GET_NAME (fixP
->fx_addsy
));
7975 goto apply_fix_return
;
7977 fix_insn (fixP
, flags
, value
);
7980 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7981 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7985 _("pc-relative load offset not word aligned"));
7986 if (signed_overflow (value
, 21))
7987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7988 _("pc-relative load offset out of range"));
7989 insn
= get_aarch64_insn (buf
);
7990 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7991 put_aarch64_insn (buf
, insn
);
7995 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7996 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7998 if (signed_overflow (value
, 21))
7999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8000 _("pc-relative address offset out of range"));
8001 insn
= get_aarch64_insn (buf
);
8002 insn
|= encode_adr_imm (value
);
8003 put_aarch64_insn (buf
, insn
);
8007 case BFD_RELOC_AARCH64_BRANCH19
:
8008 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8012 _("conditional branch target not word aligned"));
8013 if (signed_overflow (value
, 21))
8014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8015 _("conditional branch out of range"));
8016 insn
= get_aarch64_insn (buf
);
8017 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8018 put_aarch64_insn (buf
, insn
);
8022 case BFD_RELOC_AARCH64_TSTBR14
:
8023 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8027 _("conditional branch target not word aligned"));
8028 if (signed_overflow (value
, 16))
8029 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8030 _("conditional branch out of range"));
8031 insn
= get_aarch64_insn (buf
);
8032 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8033 put_aarch64_insn (buf
, insn
);
8037 case BFD_RELOC_AARCH64_CALL26
:
8038 case BFD_RELOC_AARCH64_JUMP26
:
8039 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8043 _("branch target not word aligned"));
8044 if (signed_overflow (value
, 28))
8045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8046 _("branch out of range"));
8047 insn
= get_aarch64_insn (buf
);
8048 insn
|= encode_branch_ofs_26 (value
>> 2);
8049 put_aarch64_insn (buf
, insn
);
8053 case BFD_RELOC_AARCH64_MOVW_G0
:
8054 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8055 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8056 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8057 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8058 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8061 case BFD_RELOC_AARCH64_MOVW_G1
:
8062 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8063 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8064 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8065 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8066 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8069 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8071 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8072 /* Should always be exported to object file, see
8073 aarch64_force_relocation(). */
8074 gas_assert (!fixP
->fx_done
);
8075 gas_assert (seg
->use_rela_p
);
8077 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8079 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8080 /* Should always be exported to object file, see
8081 aarch64_force_relocation(). */
8082 gas_assert (!fixP
->fx_done
);
8083 gas_assert (seg
->use_rela_p
);
8085 case BFD_RELOC_AARCH64_MOVW_G2
:
8086 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8087 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8088 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8089 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8092 case BFD_RELOC_AARCH64_MOVW_G3
:
8093 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8096 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8098 insn
= get_aarch64_insn (buf
);
8102 /* REL signed addend must fit in 16 bits */
8103 if (signed_overflow (value
, 16))
8104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8105 _("offset out of range"));
8109 /* Check for overflow and scale. */
8110 switch (fixP
->fx_r_type
)
8112 case BFD_RELOC_AARCH64_MOVW_G0
:
8113 case BFD_RELOC_AARCH64_MOVW_G1
:
8114 case BFD_RELOC_AARCH64_MOVW_G2
:
8115 case BFD_RELOC_AARCH64_MOVW_G3
:
8116 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8117 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8118 if (unsigned_overflow (value
, scale
+ 16))
8119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8120 _("unsigned value out of range"));
8122 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8123 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8124 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8125 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8126 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8127 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8128 /* NOTE: We can only come here with movz or movn. */
8129 if (signed_overflow (value
, scale
+ 16))
8130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8131 _("signed value out of range"));
8134 /* Force use of MOVN. */
8136 insn
= reencode_movzn_to_movn (insn
);
8140 /* Force use of MOVZ. */
8141 insn
= reencode_movzn_to_movz (insn
);
8145 /* Unchecked relocations. */
8151 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8152 insn
|= encode_movw_imm (value
& 0xffff);
8154 put_aarch64_insn (buf
, insn
);
8158 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8159 fixP
->fx_r_type
= (ilp32_p
8160 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8161 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8162 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8163 /* Should always be exported to object file, see
8164 aarch64_force_relocation(). */
8165 gas_assert (!fixP
->fx_done
);
8166 gas_assert (seg
->use_rela_p
);
8169 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8170 fixP
->fx_r_type
= (ilp32_p
8171 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8172 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8173 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8174 /* Should always be exported to object file, see
8175 aarch64_force_relocation(). */
8176 gas_assert (!fixP
->fx_done
);
8177 gas_assert (seg
->use_rela_p
);
8180 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8181 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8182 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8183 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8184 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8185 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8186 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8187 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8188 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8189 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8190 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8191 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8192 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8193 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8194 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8195 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8196 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8197 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8198 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8199 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8200 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8201 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8202 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8203 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8204 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8205 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8206 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8207 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8208 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8209 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8210 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8211 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8212 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8213 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8214 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8215 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8216 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8217 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8218 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8219 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8220 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8221 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8222 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8223 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8224 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8225 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8226 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8227 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8228 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8229 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8230 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8231 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8232 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8233 /* Should always be exported to object file, see
8234 aarch64_force_relocation(). */
8235 gas_assert (!fixP
->fx_done
);
8236 gas_assert (seg
->use_rela_p
);
8239 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8240 /* Should always be exported to object file, see
8241 aarch64_force_relocation(). */
8242 fixP
->fx_r_type
= (ilp32_p
8243 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8244 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8245 gas_assert (!fixP
->fx_done
);
8246 gas_assert (seg
->use_rela_p
);
8249 case BFD_RELOC_AARCH64_ADD_LO12
:
8250 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8251 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8252 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8253 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8254 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8255 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8256 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8257 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8258 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8259 case BFD_RELOC_AARCH64_LDST128_LO12
:
8260 case BFD_RELOC_AARCH64_LDST16_LO12
:
8261 case BFD_RELOC_AARCH64_LDST32_LO12
:
8262 case BFD_RELOC_AARCH64_LDST64_LO12
:
8263 case BFD_RELOC_AARCH64_LDST8_LO12
:
8264 /* Should always be exported to object file, see
8265 aarch64_force_relocation(). */
8266 gas_assert (!fixP
->fx_done
);
8267 gas_assert (seg
->use_rela_p
);
8270 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8271 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8272 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8275 case BFD_RELOC_UNUSED
:
8276 /* An error will already have been reported. */
8280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8281 _("unexpected %s fixup"),
8282 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8287 /* Free the allocated the struct aarch64_inst.
8288 N.B. currently there are very limited number of fix-up types actually use
8289 this field, so the impact on the performance should be minimal . */
8290 free (fixP
->tc_fix_data
.inst
);
8295 /* Translate internal representation of relocation info to BFD target
8299 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8302 bfd_reloc_code_real_type code
;
8304 reloc
= XNEW (arelent
);
8306 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8307 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8308 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8312 if (section
->use_rela_p
)
8313 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8315 fixp
->fx_offset
= reloc
->address
;
8317 reloc
->addend
= fixp
->fx_offset
;
8319 code
= fixp
->fx_r_type
;
8324 code
= BFD_RELOC_16_PCREL
;
8329 code
= BFD_RELOC_32_PCREL
;
8334 code
= BFD_RELOC_64_PCREL
;
8341 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8342 if (reloc
->howto
== NULL
)
8344 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8346 ("cannot represent %s relocation in this object file format"),
8347 bfd_get_reloc_code_name (code
));
8354 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8357 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8359 bfd_reloc_code_real_type type
;
8363 FIXME: @@ Should look at CPU word size. */
8370 type
= BFD_RELOC_16
;
8373 type
= BFD_RELOC_32
;
8376 type
= BFD_RELOC_64
;
8379 as_bad (_("cannot do %u-byte relocation"), size
);
8380 type
= BFD_RELOC_UNUSED
;
8384 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8388 aarch64_force_relocation (struct fix
*fixp
)
8390 switch (fixp
->fx_r_type
)
8392 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8393 /* Perform these "immediate" internal relocations
8394 even if the symbol is extern or weak. */
8397 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8398 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8399 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8400 /* Pseudo relocs that need to be fixed up according to
8404 case BFD_RELOC_AARCH64_ADD_LO12
:
8405 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8406 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8407 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8408 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8409 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8410 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8411 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8412 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8413 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8414 case BFD_RELOC_AARCH64_LDST128_LO12
:
8415 case BFD_RELOC_AARCH64_LDST16_LO12
:
8416 case BFD_RELOC_AARCH64_LDST32_LO12
:
8417 case BFD_RELOC_AARCH64_LDST64_LO12
:
8418 case BFD_RELOC_AARCH64_LDST8_LO12
:
8419 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8420 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8421 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8422 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8423 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8424 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8425 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8426 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8427 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8428 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8429 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8430 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8431 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8432 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8433 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8434 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8435 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8436 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8437 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8438 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8439 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8440 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8441 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8442 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8443 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8444 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8445 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8446 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8447 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8448 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8449 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8450 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8451 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8452 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8453 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8454 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8455 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8456 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8457 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8458 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8459 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8460 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8461 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8462 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8463 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8464 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8465 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8466 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8467 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8468 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8469 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8470 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8471 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8472 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8473 /* Always leave these relocations for the linker. */
8480 return generic_force_reloc (fixp
);
8485 /* Implement md_after_parse_args. This is the earliest time we need to decide
8486 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8489 aarch64_after_parse_args (void)
8491 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8494 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8495 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8496 aarch64_abi
= AARCH64_ABI_ILP32
;
8498 aarch64_abi
= AARCH64_ABI_LP64
;
8502 elf64_aarch64_target_format (void)
8505 /* FIXME: What to do for ilp32_p ? */
8506 if (target_big_endian
)
8507 return "elf64-bigaarch64-cloudabi";
8509 return "elf64-littleaarch64-cloudabi";
8511 if (target_big_endian
)
8512 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8514 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8519 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8521 elf_frob_symbol (symp
, puntp
);
8525 /* MD interface: Finalization. */
8527 /* A good place to do this, although this was probably not intended
8528 for this kind of use. We need to dump the literal pool before
8529 references are made to a null symbol pointer. */
8532 aarch64_cleanup (void)
8536 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8538 /* Put it at the end of the relevant section. */
8539 subseg_set (pool
->section
, pool
->sub_section
);
8545 /* Remove any excess mapping symbols generated for alignment frags in
8546 SEC. We may have created a mapping symbol before a zero byte
8547 alignment; remove it if there's a mapping symbol after the
8550 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8551 void *dummy ATTRIBUTE_UNUSED
)
8553 segment_info_type
*seginfo
= seg_info (sec
);
8556 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8559 for (fragp
= seginfo
->frchainP
->frch_root
;
8560 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8562 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8563 fragS
*next
= fragp
->fr_next
;
8565 /* Variable-sized frags have been converted to fixed size by
8566 this point. But if this was variable-sized to start with,
8567 there will be a fixed-size frag after it. So don't handle
8569 if (sym
== NULL
|| next
== NULL
)
8572 if (S_GET_VALUE (sym
) < next
->fr_address
)
8573 /* Not at the end of this frag. */
8575 know (S_GET_VALUE (sym
) == next
->fr_address
);
8579 if (next
->tc_frag_data
.first_map
!= NULL
)
8581 /* Next frag starts with a mapping symbol. Discard this
8583 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8587 if (next
->fr_next
== NULL
)
8589 /* This mapping symbol is at the end of the section. Discard
8591 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8592 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8596 /* As long as we have empty frags without any mapping symbols,
8598 /* If the next frag is non-empty and does not start with a
8599 mapping symbol, then this mapping symbol is required. */
8600 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8603 next
= next
->fr_next
;
8605 while (next
!= NULL
);
8610 /* Adjust the symbol table. */
8613 aarch64_adjust_symtab (void)
8616 /* Remove any overlapping mapping symbols generated by alignment frags. */
8617 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8618 /* Now do generic ELF adjustments. */
8619 elf_adjust_symtab ();
8624 checked_hash_insert (htab_t table
, const char *key
, void *value
)
8626 str_hash_insert (table
, key
, value
, 0);
8630 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
8632 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
8633 checked_hash_insert (table
, key
, value
);
8637 fill_instruction_hash_table (void)
8639 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8641 while (opcode
->name
!= NULL
)
8643 templates
*templ
, *new_templ
;
8644 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
8646 new_templ
= XNEW (templates
);
8647 new_templ
->opcode
= opcode
;
8648 new_templ
->next
= NULL
;
8651 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8654 new_templ
->next
= templ
->next
;
8655 templ
->next
= new_templ
;
8662 convert_to_upper (char *dst
, const char *src
, size_t num
)
8665 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8666 *dst
= TOUPPER (*src
);
8670 /* Assume STR point to a lower-case string, allocate, convert and return
8671 the corresponding upper-case string. */
8672 static inline const char*
8673 get_upper_str (const char *str
)
8676 size_t len
= strlen (str
);
8677 ret
= XNEWVEC (char, len
+ 1);
8678 convert_to_upper (ret
, str
, len
);
8682 /* MD interface: Initialization. */
8690 aarch64_ops_hsh
= str_htab_create ();
8691 aarch64_cond_hsh
= str_htab_create ();
8692 aarch64_shift_hsh
= str_htab_create ();
8693 aarch64_sys_regs_hsh
= str_htab_create ();
8694 aarch64_pstatefield_hsh
= str_htab_create ();
8695 aarch64_sys_regs_ic_hsh
= str_htab_create ();
8696 aarch64_sys_regs_dc_hsh
= str_htab_create ();
8697 aarch64_sys_regs_at_hsh
= str_htab_create ();
8698 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
8699 aarch64_sys_regs_sr_hsh
= str_htab_create ();
8700 aarch64_reg_hsh
= str_htab_create ();
8701 aarch64_barrier_opt_hsh
= str_htab_create ();
8702 aarch64_nzcv_hsh
= str_htab_create ();
8703 aarch64_pldop_hsh
= str_htab_create ();
8704 aarch64_hint_opt_hsh
= str_htab_create ();
8706 fill_instruction_hash_table ();
8708 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8709 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8710 (void *) (aarch64_sys_regs
+ i
));
8712 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8713 sysreg_hash_insert (aarch64_pstatefield_hsh
,
8714 aarch64_pstatefields
[i
].name
,
8715 (void *) (aarch64_pstatefields
+ i
));
8717 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8718 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
8719 aarch64_sys_regs_ic
[i
].name
,
8720 (void *) (aarch64_sys_regs_ic
+ i
));
8722 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8723 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
8724 aarch64_sys_regs_dc
[i
].name
,
8725 (void *) (aarch64_sys_regs_dc
+ i
));
8727 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8728 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
8729 aarch64_sys_regs_at
[i
].name
,
8730 (void *) (aarch64_sys_regs_at
+ i
));
8732 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8733 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8734 aarch64_sys_regs_tlbi
[i
].name
,
8735 (void *) (aarch64_sys_regs_tlbi
+ i
));
8737 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8738 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
8739 aarch64_sys_regs_sr
[i
].name
,
8740 (void *) (aarch64_sys_regs_sr
+ i
));
8742 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8743 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8744 (void *) (reg_names
+ i
));
8746 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8747 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8748 (void *) (nzcv_names
+ i
));
8750 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8752 const char *name
= aarch64_operand_modifiers
[i
].name
;
8753 checked_hash_insert (aarch64_shift_hsh
, name
,
8754 (void *) (aarch64_operand_modifiers
+ i
));
8755 /* Also hash the name in the upper case. */
8756 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8757 (void *) (aarch64_operand_modifiers
+ i
));
8760 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8763 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8764 the same condition code. */
8765 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8767 const char *name
= aarch64_conds
[i
].names
[j
];
8770 checked_hash_insert (aarch64_cond_hsh
, name
,
8771 (void *) (aarch64_conds
+ i
));
8772 /* Also hash the name in the upper case. */
8773 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8774 (void *) (aarch64_conds
+ i
));
8778 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8780 const char *name
= aarch64_barrier_options
[i
].name
;
8781 /* Skip xx00 - the unallocated values of option. */
8784 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8785 (void *) (aarch64_barrier_options
+ i
));
8786 /* Also hash the name in the upper case. */
8787 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8788 (void *) (aarch64_barrier_options
+ i
));
8791 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8793 const char* name
= aarch64_prfops
[i
].name
;
8794 /* Skip the unallocated hint encodings. */
8797 checked_hash_insert (aarch64_pldop_hsh
, name
,
8798 (void *) (aarch64_prfops
+ i
));
8799 /* Also hash the name in the upper case. */
8800 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8801 (void *) (aarch64_prfops
+ i
));
8804 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8806 const char* name
= aarch64_hint_options
[i
].name
;
8807 const char* upper_name
= get_upper_str(name
);
8809 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8810 (void *) (aarch64_hint_options
+ i
));
8812 /* Also hash the name in the upper case if not the same. */
8813 if (strcmp (name
, upper_name
) != 0)
8814 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
8815 (void *) (aarch64_hint_options
+ i
));
8818 /* Set the cpu variant based on the command-line options. */
8820 mcpu_cpu_opt
= march_cpu_opt
;
8823 mcpu_cpu_opt
= &cpu_default
;
8825 cpu_variant
= *mcpu_cpu_opt
;
8827 /* Record the CPU type. */
8828 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8830 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8833 /* Command line processing. */
8835 const char *md_shortopts
= "m:";
8837 #ifdef AARCH64_BI_ENDIAN
8838 #define OPTION_EB (OPTION_MD_BASE + 0)
8839 #define OPTION_EL (OPTION_MD_BASE + 1)
8841 #if TARGET_BYTES_BIG_ENDIAN
8842 #define OPTION_EB (OPTION_MD_BASE + 0)
8844 #define OPTION_EL (OPTION_MD_BASE + 1)
8848 struct option md_longopts
[] = {
8850 {"EB", no_argument
, NULL
, OPTION_EB
},
8853 {"EL", no_argument
, NULL
, OPTION_EL
},
8855 {NULL
, no_argument
, NULL
, 0}
8858 size_t md_longopts_size
= sizeof (md_longopts
);
8860 struct aarch64_option_table
8862 const char *option
; /* Option name to match. */
8863 const char *help
; /* Help information. */
8864 int *var
; /* Variable to change. */
8865 int value
; /* What to change it to. */
8866 char *deprecated
; /* If non-null, print this message. */
8869 static struct aarch64_option_table aarch64_opts
[] = {
8870 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8871 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8873 #ifdef DEBUG_AARCH64
8874 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8875 #endif /* DEBUG_AARCH64 */
8876 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8878 {"mno-verbose-error", N_("do not output verbose error messages"),
8879 &verbose_error_p
, 0, NULL
},
8880 {NULL
, NULL
, NULL
, 0, NULL
}
8883 struct aarch64_cpu_option_table
8886 const aarch64_feature_set value
;
8887 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8889 const char *canonical_name
;
8892 /* This list should, at a minimum, contain all the cpu names
8893 recognized by GCC. */
8894 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8895 {"all", AARCH64_ANY
, NULL
},
8896 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8897 AARCH64_FEATURE_CRC
), "Cortex-A34"},
8898 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8899 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8900 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8901 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8902 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8903 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8904 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8905 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8906 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8907 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8908 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8909 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8911 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8912 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8914 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8915 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8917 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8918 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8919 | AARCH64_FEATURE_DOTPROD
8920 | AARCH64_FEATURE_SSBS
),
8922 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8923 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8924 | AARCH64_FEATURE_DOTPROD
8925 | AARCH64_FEATURE_SSBS
),
8927 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8928 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8929 | AARCH64_FEATURE_DOTPROD
8930 | AARCH64_FEATURE_SSBS
),
8932 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8933 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8934 | AARCH64_FEATURE_DOTPROD
8935 | AARCH64_FEATURE_SSBS
),
8937 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8938 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8939 | AARCH64_FEATURE_DOTPROD
8940 | AARCH64_FEATURE_PROFILE
),
8942 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8943 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8944 "Samsung Exynos M1"},
8945 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8946 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8947 | AARCH64_FEATURE_RDMA
),
8949 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8950 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8951 | AARCH64_FEATURE_DOTPROD
8952 | AARCH64_FEATURE_SSBS
),
8954 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8955 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8956 | AARCH64_FEATURE_DOTPROD
8957 | AARCH64_FEATURE_PROFILE
),
8959 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8960 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8961 | AARCH64_FEATURE_RDMA
),
8962 "Qualcomm QDF24XX"},
8963 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8964 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8965 "Qualcomm Saphira"},
8966 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8967 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8969 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8970 AARCH64_FEATURE_CRYPTO
),
8972 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8973 in earlier releases and is superseded by 'xgene1' in all
8975 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8976 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8977 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8978 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8979 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
8980 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8981 AARCH64_FEATURE_PROFILE
8982 | AARCH64_FEATURE_CVADP
8983 | AARCH64_FEATURE_SVE
8984 | AARCH64_FEATURE_SSBS
8985 | AARCH64_FEATURE_RNG
8986 | AARCH64_FEATURE_BFLOAT16
8987 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
8988 {"generic", AARCH64_ARCH_V8
, NULL
},
8990 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8993 struct aarch64_arch_option_table
8996 const aarch64_feature_set value
;
8999 /* This list should, at a minimum, contain all the architecture names
9000 recognized by GCC. */
9001 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9002 {"all", AARCH64_ANY
},
9003 {"armv8-a", AARCH64_ARCH_V8
},
9004 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9005 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9006 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9007 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9008 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9009 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9010 {"armv8-r", AARCH64_ARCH_V8_R
},
9011 {NULL
, AARCH64_ARCH_NONE
}
9014 /* ISA extensions. */
9015 struct aarch64_option_cpu_value_table
9018 const aarch64_feature_set value
;
9019 const aarch64_feature_set require
; /* Feature dependencies. */
9022 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9023 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9025 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9026 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9027 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9029 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9031 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9032 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9033 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9035 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9037 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9039 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9040 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9041 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9042 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9043 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9044 AARCH64_FEATURE (AARCH64_FEATURE_FP
9045 | AARCH64_FEATURE_F16
, 0)},
9046 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9048 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9049 AARCH64_FEATURE (AARCH64_FEATURE_F16
9050 | AARCH64_FEATURE_SIMD
9051 | AARCH64_FEATURE_COMPNUM
, 0)},
9052 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9054 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9055 AARCH64_FEATURE (AARCH64_FEATURE_F16
9056 | AARCH64_FEATURE_SIMD
, 0)},
9057 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9059 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9061 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9063 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9065 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9067 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9069 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9071 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9072 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9073 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9075 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9077 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9079 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9080 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9081 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9082 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9083 | AARCH64_FEATURE_SM4
, 0)},
9084 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9085 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9086 | AARCH64_FEATURE_AES
, 0)},
9087 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9088 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9089 | AARCH64_FEATURE_SHA3
, 0)},
9090 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9091 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9092 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9094 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9096 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9097 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9098 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9099 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9100 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9103 struct aarch64_long_option_table
9105 const char *option
; /* Substring to match. */
9106 const char *help
; /* Help information. */
9107 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9108 char *deprecated
; /* If non-null, print this message. */
9111 /* Transitive closure of features depending on set. */
9112 static aarch64_feature_set
9113 aarch64_feature_disable_set (aarch64_feature_set set
)
9115 const struct aarch64_option_cpu_value_table
*opt
;
9116 aarch64_feature_set prev
= 0;
9118 while (prev
!= set
) {
9120 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9121 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9122 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9127 /* Transitive closure of dependencies of set. */
9128 static aarch64_feature_set
9129 aarch64_feature_enable_set (aarch64_feature_set set
)
9131 const struct aarch64_option_cpu_value_table
*opt
;
9132 aarch64_feature_set prev
= 0;
9134 while (prev
!= set
) {
9136 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9137 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9138 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9144 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9145 bfd_boolean ext_only
)
9147 /* We insist on extensions being added before being removed. We achieve
9148 this by using the ADDING_VALUE variable to indicate whether we are
9149 adding an extension (1) or removing it (0) and only allowing it to
9150 change in the order -1 -> 1 -> 0. */
9151 int adding_value
= -1;
9152 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9154 /* Copy the feature set, so that we can modify it. */
9158 while (str
!= NULL
&& *str
!= 0)
9160 const struct aarch64_option_cpu_value_table
*opt
;
9161 const char *ext
= NULL
;
9168 as_bad (_("invalid architectural extension"));
9172 ext
= strchr (++str
, '+');
9178 optlen
= strlen (str
);
9180 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9182 if (adding_value
!= 0)
9187 else if (optlen
> 0)
9189 if (adding_value
== -1)
9191 else if (adding_value
!= 1)
9193 as_bad (_("must specify extensions to add before specifying "
9194 "those to remove"));
9201 as_bad (_("missing architectural extension"));
9205 gas_assert (adding_value
!= -1);
9207 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9208 if (strncmp (opt
->name
, str
, optlen
) == 0)
9210 aarch64_feature_set set
;
9212 /* Add or remove the extension. */
9215 set
= aarch64_feature_enable_set (opt
->value
);
9216 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9220 set
= aarch64_feature_disable_set (opt
->value
);
9221 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9226 if (opt
->name
== NULL
)
9228 as_bad (_("unknown architectural extension `%s'"), str
);
9239 aarch64_parse_cpu (const char *str
)
9241 const struct aarch64_cpu_option_table
*opt
;
9242 const char *ext
= strchr (str
, '+');
9248 optlen
= strlen (str
);
9252 as_bad (_("missing cpu name `%s'"), str
);
9256 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9257 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9259 mcpu_cpu_opt
= &opt
->value
;
9261 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9266 as_bad (_("unknown cpu `%s'"), str
);
9271 aarch64_parse_arch (const char *str
)
9273 const struct aarch64_arch_option_table
*opt
;
9274 const char *ext
= strchr (str
, '+');
9280 optlen
= strlen (str
);
9284 as_bad (_("missing architecture name `%s'"), str
);
9288 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9289 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9291 march_cpu_opt
= &opt
->value
;
9293 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9298 as_bad (_("unknown architecture `%s'\n"), str
);
9303 struct aarch64_option_abi_value_table
9306 enum aarch64_abi_type value
;
9309 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9310 {"ilp32", AARCH64_ABI_ILP32
},
9311 {"lp64", AARCH64_ABI_LP64
},
9315 aarch64_parse_abi (const char *str
)
9321 as_bad (_("missing abi name `%s'"), str
);
9325 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9326 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9328 aarch64_abi
= aarch64_abis
[i
].value
;
9332 as_bad (_("unknown abi `%s'\n"), str
);
9336 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9338 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9339 aarch64_parse_abi
, NULL
},
9340 #endif /* OBJ_ELF */
9341 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9342 aarch64_parse_cpu
, NULL
},
9343 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9344 aarch64_parse_arch
, NULL
},
9345 {NULL
, NULL
, 0, NULL
}
9349 md_parse_option (int c
, const char *arg
)
9351 struct aarch64_option_table
*opt
;
9352 struct aarch64_long_option_table
*lopt
;
9358 target_big_endian
= 1;
9364 target_big_endian
= 0;
9369 /* Listing option. Just ignore these, we don't support additional
9374 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9376 if (c
== opt
->option
[0]
9377 && ((arg
== NULL
&& opt
->option
[1] == 0)
9378 || streq (arg
, opt
->option
+ 1)))
9380 /* If the option is deprecated, tell the user. */
9381 if (opt
->deprecated
!= NULL
)
9382 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9383 arg
? arg
: "", _(opt
->deprecated
));
9385 if (opt
->var
!= NULL
)
9386 *opt
->var
= opt
->value
;
9392 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9394 /* These options are expected to have an argument. */
9395 if (c
== lopt
->option
[0]
9397 && strncmp (arg
, lopt
->option
+ 1,
9398 strlen (lopt
->option
+ 1)) == 0)
9400 /* If the option is deprecated, tell the user. */
9401 if (lopt
->deprecated
!= NULL
)
9402 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9403 _(lopt
->deprecated
));
9405 /* Call the sup-option parser. */
9406 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9417 md_show_usage (FILE * fp
)
9419 struct aarch64_option_table
*opt
;
9420 struct aarch64_long_option_table
*lopt
;
9422 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9424 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9425 if (opt
->help
!= NULL
)
9426 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9428 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9429 if (lopt
->help
!= NULL
)
9430 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9434 -EB assemble code for a big-endian cpu\n"));
9439 -EL assemble code for a little-endian cpu\n"));
9443 /* Parse a .cpu directive. */
9446 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9448 const struct aarch64_cpu_option_table
*opt
;
9454 name
= input_line_pointer
;
9455 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9456 input_line_pointer
++;
9457 saved_char
= *input_line_pointer
;
9458 *input_line_pointer
= 0;
9460 ext
= strchr (name
, '+');
9463 optlen
= ext
- name
;
9465 optlen
= strlen (name
);
9467 /* Skip the first "all" entry. */
9468 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9469 if (strlen (opt
->name
) == optlen
9470 && strncmp (name
, opt
->name
, optlen
) == 0)
9472 mcpu_cpu_opt
= &opt
->value
;
9474 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9477 cpu_variant
= *mcpu_cpu_opt
;
9479 *input_line_pointer
= saved_char
;
9480 demand_empty_rest_of_line ();
9483 as_bad (_("unknown cpu `%s'"), name
);
9484 *input_line_pointer
= saved_char
;
9485 ignore_rest_of_line ();
9489 /* Parse a .arch directive. */
9492 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9494 const struct aarch64_arch_option_table
*opt
;
9500 name
= input_line_pointer
;
9501 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9502 input_line_pointer
++;
9503 saved_char
= *input_line_pointer
;
9504 *input_line_pointer
= 0;
9506 ext
= strchr (name
, '+');
9509 optlen
= ext
- name
;
9511 optlen
= strlen (name
);
9513 /* Skip the first "all" entry. */
9514 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9515 if (strlen (opt
->name
) == optlen
9516 && strncmp (name
, opt
->name
, optlen
) == 0)
9518 mcpu_cpu_opt
= &opt
->value
;
9520 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9523 cpu_variant
= *mcpu_cpu_opt
;
9525 *input_line_pointer
= saved_char
;
9526 demand_empty_rest_of_line ();
9530 as_bad (_("unknown architecture `%s'\n"), name
);
9531 *input_line_pointer
= saved_char
;
9532 ignore_rest_of_line ();
9535 /* Parse a .arch_extension directive. */
9538 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9541 char *ext
= input_line_pointer
;;
9543 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9544 input_line_pointer
++;
9545 saved_char
= *input_line_pointer
;
9546 *input_line_pointer
= 0;
9548 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9551 cpu_variant
= *mcpu_cpu_opt
;
9553 *input_line_pointer
= saved_char
;
9554 demand_empty_rest_of_line ();
9557 /* Copy symbol information. */
9560 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9562 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
9566 /* Same as elf_copy_symbol_attributes, but without copying st_other.
9567 This is needed so AArch64 specific st_other values can be independently
9568 specified for an IFUNC resolver (that is called by the dynamic linker)
9569 and the symbol it resolves (aliased to the resolver). In particular,
9570 if a function symbol has special st_other value set via directives,
9571 then attaching an IFUNC resolver to that symbol should not override
9572 the st_other setting. Requiring the directive on the IFUNC resolver
9573 symbol would be unexpected and problematic in C code, where the two
9574 symbols appear as two independent function declarations. */
9577 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
9579 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
9580 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
9583 if (destelf
->size
== NULL
)
9584 destelf
->size
= XNEW (expressionS
);
9585 *destelf
->size
= *srcelf
->size
;
9589 free (destelf
->size
);
9590 destelf
->size
= NULL
;
9592 S_SET_SIZE (dest
, S_GET_SIZE (src
));