1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 static const aarch64_feature_set aarch64_arch_any
= AARCH64_ANY
;
59 static const aarch64_feature_set aarch64_arch_none
= AARCH64_ARCH_NONE
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
72 /* AArch64 ABI for the output file. */
73 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
75 /* When non-zero, program to a 32-bit model, in which the C data types
76 int, long and all pointer types are 32-bit objects (ILP32); or to a
77 64-bit model, in which the C int type is 32-bits but the C long type
78 and all pointer types are 64-bit objects (LP64). */
79 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
92 /* Bits for DEFINED field in neon_type_el. */
94 #define NTA_HASINDEX 2
98 enum neon_el_type type
;
99 unsigned char defined
;
104 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
108 bfd_reloc_code_real_type type
;
111 enum aarch64_opnd opnd
;
113 unsigned need_libopcodes_p
: 1;
116 struct aarch64_instruction
118 /* libopcodes structure for instruction intermediate representation. */
120 /* Record assembly errors found during the parsing. */
123 enum aarch64_operand_error_kind kind
;
126 /* The condition that appears in the assembly line. */
128 /* Relocation information (including the GAS internal fixup). */
130 /* Need to generate an immediate in the literal pool. */
131 unsigned gen_lit_pool
: 1;
134 typedef struct aarch64_instruction aarch64_instruction
;
136 static aarch64_instruction inst
;
138 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
139 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
141 /* Diagnostics inline function utilites.
143 These are lightweight utlities which should only be called by parse_operands
144 and other parsers. GAS processes each assembly line by parsing it against
145 instruction template(s), in the case of multiple templates (for the same
146 mnemonic name), those templates are tried one by one until one succeeds or
147 all fail. An assembly line may fail a few templates before being
148 successfully parsed; an error saved here in most cases is not a user error
149 but an error indicating the current template is not the right template.
150 Therefore it is very important that errors can be saved at a low cost during
151 the parsing; we don't want to slow down the whole parsing by recording
152 non-user errors in detail.
154 Remember that the objective is to help GAS pick up the most approapriate
155 error message in the case of multiple templates, e.g. FMOV which has 8
161 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
162 inst
.parsing_error
.error
= NULL
;
165 static inline bfd_boolean
168 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
171 static inline const char *
172 get_error_message (void)
174 return inst
.parsing_error
.error
;
178 set_error_message (const char *error
)
180 inst
.parsing_error
.error
= error
;
183 static inline enum aarch64_operand_error_kind
184 get_error_kind (void)
186 return inst
.parsing_error
.kind
;
190 set_error_kind (enum aarch64_operand_error_kind kind
)
192 inst
.parsing_error
.kind
= kind
;
196 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
198 inst
.parsing_error
.kind
= kind
;
199 inst
.parsing_error
.error
= error
;
203 set_recoverable_error (const char *error
)
205 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
208 /* Use the DESC field of the corresponding aarch64_operand entry to compose
209 the error message. */
211 set_default_error (void)
213 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
217 set_syntax_error (const char *error
)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
223 set_first_syntax_error (const char *error
)
226 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
230 set_fatal_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
235 /* Number of littlenums required to hold an extended precision number. */
236 #define MAX_LITTLENUMS 6
238 /* Return value for certain parsers when the parsing fails; those parsers
239 return the information of the parsed result, e.g. register number, on
241 #define PARSE_FAIL -1
243 /* This is an invalid condition code that means no conditional field is
245 #define COND_ALWAYS 0x10
249 const char *template;
255 const char *template;
262 bfd_reloc_code_real_type reloc
;
265 /* Structure for a hash table entry for a register. */
269 unsigned char number
;
271 unsigned char builtin
;
274 /* Macros to define the register types and masks for the purpose
277 #undef AARCH64_REG_TYPES
278 #define AARCH64_REG_TYPES \
279 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
280 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
281 BASIC_REG_TYPE(SP_32) /* wsp */ \
282 BASIC_REG_TYPE(SP_64) /* sp */ \
283 BASIC_REG_TYPE(Z_32) /* wzr */ \
284 BASIC_REG_TYPE(Z_64) /* xzr */ \
285 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
286 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
287 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
288 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
289 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
290 BASIC_REG_TYPE(CN) /* c[0-7] */ \
291 BASIC_REG_TYPE(VN) /* v[0-31] */ \
292 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
293 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
294 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
295 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
296 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
298 /* Typecheck: any [BHSDQ]P FP. */ \
299 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
300 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
301 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
302 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
303 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
304 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
305 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
306 /* Any integer register; used for error messages only. */ \
307 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
308 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
309 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
310 /* Pseudo type to mark the end of the enumerator sequence. */ \
313 #undef BASIC_REG_TYPE
314 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
315 #undef MULTI_REG_TYPE
316 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
318 /* Register type enumerators. */
321 /* A list of REG_TYPE_*. */
325 #undef BASIC_REG_TYPE
326 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
328 #define REG_TYPE(T) (1 << REG_TYPE_##T)
329 #undef MULTI_REG_TYPE
330 #define MULTI_REG_TYPE(T,V) V,
332 /* Values indexed by aarch64_reg_type to assist the type checking. */
333 static const unsigned reg_type_masks
[] =
338 #undef BASIC_REG_TYPE
340 #undef MULTI_REG_TYPE
341 #undef AARCH64_REG_TYPES
343 /* Diagnostics used when we don't get a register of the expected type.
344 Note: this has to synchronized with aarch64_reg_type definitions
347 get_reg_expected_msg (aarch64_reg_type reg_type
)
354 msg
= N_("integer 32-bit register expected");
357 msg
= N_("integer 64-bit register expected");
360 msg
= N_("integer register expected");
362 case REG_TYPE_R_Z_SP
:
363 msg
= N_("integer, zero or SP register expected");
366 msg
= N_("8-bit SIMD scalar register expected");
369 msg
= N_("16-bit SIMD scalar or floating-point half precision "
370 "register expected");
373 msg
= N_("32-bit SIMD scalar or floating-point single precision "
374 "register expected");
377 msg
= N_("64-bit SIMD scalar or floating-point double precision "
378 "register expected");
381 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
382 "register expected");
385 msg
= N_("C0 - C15 expected");
387 case REG_TYPE_R_Z_BHSDQ_V
:
388 msg
= N_("register expected");
390 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
391 msg
= N_("SIMD scalar or floating-point register expected");
393 case REG_TYPE_VN
: /* any V reg */
394 msg
= N_("vector register expected");
397 as_fatal (_("invalid register type %d"), reg_type
);
402 /* Some well known registers that we refer to directly elsewhere. */
405 /* Instructions take 4 bytes in the object file. */
408 /* Define some common error messages. */
409 #define BAD_SP _("SP not allowed here")
411 static struct hash_control
*aarch64_ops_hsh
;
412 static struct hash_control
*aarch64_cond_hsh
;
413 static struct hash_control
*aarch64_shift_hsh
;
414 static struct hash_control
*aarch64_sys_regs_hsh
;
415 static struct hash_control
*aarch64_pstatefield_hsh
;
416 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
417 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
418 static struct hash_control
*aarch64_sys_regs_at_hsh
;
419 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
420 static struct hash_control
*aarch64_reg_hsh
;
421 static struct hash_control
*aarch64_barrier_opt_hsh
;
422 static struct hash_control
*aarch64_nzcv_hsh
;
423 static struct hash_control
*aarch64_pldop_hsh
;
425 /* Stuff needed to resolve the label ambiguity
434 static symbolS
*last_label_seen
;
436 /* Literal pool structure. Held on a per-section
437 and per-sub-section basis. */
439 #define MAX_LITERAL_POOL_SIZE 1024
440 typedef struct literal_expression
443 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
444 LITTLENUM_TYPE
* bignum
;
445 } literal_expression
;
447 typedef struct literal_pool
449 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
450 unsigned int next_free_entry
;
456 struct literal_pool
*next
;
459 /* Pointer to a linked list of literal pools. */
460 static literal_pool
*list_of_pools
= NULL
;
464 /* This array holds the chars that always start a comment. If the
465 pre-processor is disabled, these aren't very useful. */
466 const char comment_chars
[] = "";
468 /* This array holds the chars that only start a comment at the beginning of
469 a line. If the line seems to have the form '# 123 filename'
470 .line and .file directives will appear in the pre-processed output. */
471 /* Note that input_file.c hand checks for '#' at the beginning of the
472 first line of the input file. This is because the compiler outputs
473 #NO_APP at the beginning of its output. */
474 /* Also note that comments like this one will always work. */
475 const char line_comment_chars
[] = "#";
477 const char line_separator_chars
[] = ";";
479 /* Chars that can be used to separate mant
480 from exp in floating point numbers. */
481 const char EXP_CHARS
[] = "eE";
483 /* Chars that mean this number is a floating point constant. */
487 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
489 /* Prefix character that indicates the start of an immediate value. */
490 #define is_immediate_prefix(C) ((C) == '#')
492 /* Separator character handling. */
494 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
496 static inline bfd_boolean
497 skip_past_char (char **str
, char c
)
508 #define skip_past_comma(str) skip_past_char (str, ',')
510 /* Arithmetic expressions (possibly involving symbols). */
512 static bfd_boolean in_my_get_expression_p
= FALSE
;
514 /* Third argument to my_get_expression. */
515 #define GE_NO_PREFIX 0
516 #define GE_OPT_PREFIX 1
518 /* Return TRUE if the string pointed by *STR is successfully parsed
519 as an valid expression; *EP will be filled with the information of
520 such an expression. Otherwise return FALSE. */
523 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
528 int prefix_present_p
= 0;
535 if (is_immediate_prefix (**str
))
538 prefix_present_p
= 1;
545 memset (ep
, 0, sizeof (expressionS
));
547 save_in
= input_line_pointer
;
548 input_line_pointer
= *str
;
549 in_my_get_expression_p
= TRUE
;
550 seg
= expression (ep
);
551 in_my_get_expression_p
= FALSE
;
553 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
555 /* We found a bad expression in md_operand(). */
556 *str
= input_line_pointer
;
557 input_line_pointer
= save_in
;
558 if (prefix_present_p
&& ! error_p ())
559 set_fatal_syntax_error (_("bad expression"));
561 set_first_syntax_error (_("bad expression"));
566 if (seg
!= absolute_section
567 && seg
!= text_section
568 && seg
!= data_section
569 && seg
!= bss_section
&& seg
!= undefined_section
)
571 set_syntax_error (_("bad segment"));
572 *str
= input_line_pointer
;
573 input_line_pointer
= save_in
;
580 *str
= input_line_pointer
;
581 input_line_pointer
= save_in
;
585 /* Turn a string in input_line_pointer into a floating point constant
586 of type TYPE, and store the appropriate bytes in *LITP. The number
587 of LITTLENUMS emitted is stored in *SIZEP. An error message is
588 returned, or NULL on OK. */
591 md_atof (int type
, char *litP
, int *sizeP
)
593 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
596 /* We handle all bad expressions here, so that we can report the faulty
597 instruction in the error message. */
599 md_operand (expressionS
* exp
)
601 if (in_my_get_expression_p
)
602 exp
->X_op
= O_illegal
;
605 /* Immediate values. */
607 /* Errors may be set multiple times during parsing or bit encoding
608 (particularly in the Neon bits), but usually the earliest error which is set
609 will be the most meaningful. Avoid overwriting it with later (cascading)
610 errors by calling this function. */
613 first_error (const char *error
)
616 set_syntax_error (error
);
619 /* Similiar to first_error, but this function accepts formatted error
622 first_error_fmt (const char *format
, ...)
627 /* N.B. this single buffer will not cause error messages for different
628 instructions to pollute each other; this is because at the end of
629 processing of each assembly line, error message if any will be
630 collected by as_bad. */
631 static char buffer
[size
];
635 int ret ATTRIBUTE_UNUSED
;
636 va_start (args
, format
);
637 ret
= vsnprintf (buffer
, size
, format
, args
);
638 know (ret
<= size
- 1 && ret
>= 0);
640 set_syntax_error (buffer
);
644 /* Register parsing. */
646 /* Generic register parser which is called by other specialized
648 CCP points to what should be the beginning of a register name.
649 If it is indeed a valid register name, advance CCP over it and
650 return the reg_entry structure; otherwise return NULL.
651 It does not issue diagnostics. */
654 parse_reg (char **ccp
)
660 #ifdef REGISTER_PREFIX
661 if (*start
!= REGISTER_PREFIX
)
667 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
672 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
674 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
683 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
686 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
688 if (reg
->type
== type
)
693 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
694 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
695 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
696 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
697 case REG_TYPE_VN
: /* Vector register. */
698 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
699 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
700 == reg_type_masks
[reg
->type
]);
702 as_fatal ("unhandled type %d", type
);
707 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
708 Return the register number otherwise. *ISREG32 is set to one if the
709 register is 32-bit wide; *ISREGZERO is set to one if the register is
710 of type Z_32 or Z_64.
711 Note that this function does not issue any diagnostics. */
714 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
715 int *isreg32
, int *isregzero
)
718 const reg_entry
*reg
= parse_reg (&str
);
723 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
732 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
737 *isreg32
= reg
->type
== REG_TYPE_R_32
;
744 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
756 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
757 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
758 otherwise return FALSE.
760 Accept only one occurrence of:
761 8b 16b 4h 8h 2s 4s 1d 2d
764 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
768 unsigned element_size
;
769 enum neon_el_type type
;
779 width
= strtoul (ptr
, &ptr
, 10);
780 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
782 first_error_fmt (_("bad size %d in vector width specifier"), width
);
787 switch (TOLOWER (*ptr
))
815 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
817 first_error (_("missing element size"));
820 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
823 ("invalid element size %d and vector size combination %c"),
829 parsed_type
->type
= type
;
830 parsed_type
->width
= width
;
837 /* Parse a single type, e.g. ".8b", leading period included.
838 Only applicable to Vn registers.
840 Return TRUE on success; otherwise return FALSE. */
842 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
848 if (! parse_neon_type_for_operand (vectype
, &str
))
850 first_error (_("vector type expected"));
862 /* Parse a register of the type TYPE.
864 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
865 name or the parsed register is not of TYPE.
867 Otherwise return the register number, and optionally fill in the actual
868 type of the register in *RTYPE when multiple alternatives were given, and
869 return the register shape and element index information in *TYPEINFO.
871 IN_REG_LIST should be set with TRUE if the caller is parsing a register
875 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
876 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
879 const reg_entry
*reg
= parse_reg (&str
);
880 struct neon_type_el atype
;
881 struct neon_type_el parsetype
;
882 bfd_boolean is_typed_vecreg
= FALSE
;
885 atype
.type
= NT_invtype
;
893 set_default_error ();
897 if (! aarch64_check_reg_type (reg
, type
))
899 DEBUG_TRACE ("reg type check failed");
900 set_default_error ();
905 if (type
== REG_TYPE_VN
906 && parse_neon_operand_type (&parsetype
, &str
))
908 /* Register if of the form Vn.[bhsdq]. */
909 is_typed_vecreg
= TRUE
;
911 if (parsetype
.width
== 0)
912 /* Expect index. In the new scheme we cannot have
913 Vn.[bhsdq] represent a scalar. Therefore any
914 Vn.[bhsdq] should have an index following it.
915 Except in reglists ofcourse. */
916 atype
.defined
|= NTA_HASINDEX
;
918 atype
.defined
|= NTA_HASTYPE
;
920 atype
.type
= parsetype
.type
;
921 atype
.width
= parsetype
.width
;
924 if (skip_past_char (&str
, '['))
928 /* Reject Sn[index] syntax. */
929 if (!is_typed_vecreg
)
931 first_error (_("this type of register can't be indexed"));
935 if (in_reg_list
== TRUE
)
937 first_error (_("index not allowed inside register list"));
941 atype
.defined
|= NTA_HASINDEX
;
943 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
945 if (exp
.X_op
!= O_constant
)
947 first_error (_("constant expression required"));
951 if (! skip_past_char (&str
, ']'))
954 atype
.index
= exp
.X_add_number
;
956 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
958 /* Indexed vector register expected. */
959 first_error (_("indexed vector register expected"));
963 /* A vector reg Vn should be typed or indexed. */
964 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
966 first_error (_("invalid use of vector register"));
982 Return the register number on success; return PARSE_FAIL otherwise.
984 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
985 the register (e.g. NEON double or quad reg when either has been requested).
987 If this is a NEON vector register with additional type information, fill
988 in the struct pointed to by VECTYPE (if non-NULL).
990 This parser does not handle register list. */
993 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
994 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
996 struct neon_type_el atype
;
998 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
999 /*in_reg_list= */ FALSE
);
1001 if (reg
== PARSE_FAIL
)
1012 static inline bfd_boolean
1013 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1017 && e1
.defined
== e2
.defined
1018 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1021 /* This function parses the NEON register list. On success, it returns
1022 the parsed register list information in the following encoded format:
1024 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1025 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1027 The information of the register shape and/or index is returned in
1030 It returns PARSE_FAIL if the register list is invalid.
1032 The list contains one to four registers.
1033 Each register can be one of:
1036 All <T> should be identical.
1037 All <index> should be identical.
1038 There are restrictions on <Vt> numbers which are checked later
1039 (by reg_list_valid_p). */
1042 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1046 struct neon_type_el typeinfo
, typeinfo_first
;
1051 bfd_boolean error
= FALSE
;
1052 bfd_boolean expect_index
= FALSE
;
1056 set_syntax_error (_("expecting {"));
1062 typeinfo_first
.defined
= 0;
1063 typeinfo_first
.type
= NT_invtype
;
1064 typeinfo_first
.width
= -1;
1065 typeinfo_first
.index
= 0;
1074 str
++; /* skip over '-' */
1077 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1078 /*in_reg_list= */ TRUE
);
1079 if (val
== PARSE_FAIL
)
1081 set_first_syntax_error (_("invalid vector register in list"));
1085 /* reject [bhsd]n */
1086 if (typeinfo
.defined
== 0)
1088 set_first_syntax_error (_("invalid scalar register in list"));
1093 if (typeinfo
.defined
& NTA_HASINDEX
)
1094 expect_index
= TRUE
;
1098 if (val
< val_range
)
1100 set_first_syntax_error
1101 (_("invalid range in vector register list"));
1110 typeinfo_first
= typeinfo
;
1111 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1113 set_first_syntax_error
1114 (_("type mismatch in vector register list"));
1119 for (i
= val_range
; i
<= val
; i
++)
1121 ret_val
|= i
<< (5 * nb_regs
);
1126 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1128 skip_whitespace (str
);
1131 set_first_syntax_error (_("end of vector register list not found"));
1136 skip_whitespace (str
);
1140 if (skip_past_char (&str
, '['))
1144 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1145 if (exp
.X_op
!= O_constant
)
1147 set_first_syntax_error (_("constant expression required."));
1150 if (! skip_past_char (&str
, ']'))
1153 typeinfo_first
.index
= exp
.X_add_number
;
1157 set_first_syntax_error (_("expected index"));
1164 set_first_syntax_error (_("too many registers in vector register list"));
1167 else if (nb_regs
== 0)
1169 set_first_syntax_error (_("empty vector register list"));
1175 *vectype
= typeinfo_first
;
1177 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1180 /* Directives: register aliases. */
1183 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1188 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1191 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1194 /* Only warn about a redefinition if it's not defined as the
1196 else if (new->number
!= number
|| new->type
!= type
)
1197 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1202 name
= xstrdup (str
);
1203 new = xmalloc (sizeof (reg_entry
));
1206 new->number
= number
;
1208 new->builtin
= FALSE
;
1210 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1216 /* Look for the .req directive. This is of the form:
1218 new_register_name .req existing_register_name
1220 If we find one, or if it looks sufficiently like one that we want to
1221 handle any error here, return TRUE. Otherwise return FALSE. */
1224 create_register_alias (char *newname
, char *p
)
1226 const reg_entry
*old
;
1227 char *oldname
, *nbuf
;
1230 /* The input scrubber ensures that whitespace after the mnemonic is
1231 collapsed to single spaces. */
1233 if (strncmp (oldname
, " .req ", 6) != 0)
1237 if (*oldname
== '\0')
1240 old
= hash_find (aarch64_reg_hsh
, oldname
);
1243 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1247 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1248 the desired alias name, and p points to its end. If not, then
1249 the desired alias name is in the global original_case_string. */
1250 #ifdef TC_CASE_SENSITIVE
1253 newname
= original_case_string
;
1254 nlen
= strlen (newname
);
1257 nbuf
= alloca (nlen
+ 1);
1258 memcpy (nbuf
, newname
, nlen
);
1261 /* Create aliases under the new name as stated; an all-lowercase
1262 version of the new name; and an all-uppercase version of the new
1264 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1266 for (p
= nbuf
; *p
; p
++)
1269 if (strncmp (nbuf
, newname
, nlen
))
1271 /* If this attempt to create an additional alias fails, do not bother
1272 trying to create the all-lower case alias. We will fail and issue
1273 a second, duplicate error message. This situation arises when the
1274 programmer does something like:
1277 The second .req creates the "Foo" alias but then fails to create
1278 the artificial FOO alias because it has already been created by the
1280 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1284 for (p
= nbuf
; *p
; p
++)
1287 if (strncmp (nbuf
, newname
, nlen
))
1288 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1294 /* Should never be called, as .req goes between the alias and the
1295 register name, not at the beginning of the line. */
1297 s_req (int a ATTRIBUTE_UNUSED
)
1299 as_bad (_("invalid syntax for .req directive"));
1302 /* The .unreq directive deletes an alias which was previously defined
1303 by .req. For example:
1309 s_unreq (int a ATTRIBUTE_UNUSED
)
1314 name
= input_line_pointer
;
1316 while (*input_line_pointer
!= 0
1317 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1318 ++input_line_pointer
;
1320 saved_char
= *input_line_pointer
;
1321 *input_line_pointer
= 0;
1324 as_bad (_("invalid syntax for .unreq directive"));
1327 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1330 as_bad (_("unknown register alias '%s'"), name
);
1331 else if (reg
->builtin
)
1332 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1339 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1340 free ((char *) reg
->name
);
1343 /* Also locate the all upper case and all lower case versions.
1344 Do not complain if we cannot find one or the other as it
1345 was probably deleted above. */
1347 nbuf
= strdup (name
);
1348 for (p
= nbuf
; *p
; p
++)
1350 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1353 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1354 free ((char *) reg
->name
);
1358 for (p
= nbuf
; *p
; p
++)
1360 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1363 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1364 free ((char *) reg
->name
);
1372 *input_line_pointer
= saved_char
;
1373 demand_empty_rest_of_line ();
1376 /* Directives: Instruction set selection. */
1379 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1380 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1381 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1382 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1384 /* Create a new mapping symbol for the transition to STATE. */
1387 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1390 const char *symname
;
1397 type
= BSF_NO_FLAGS
;
1401 type
= BSF_NO_FLAGS
;
1407 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1408 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1410 /* Save the mapping symbols for future reference. Also check that
1411 we do not place two mapping symbols at the same offset within a
1412 frag. We'll handle overlap between frags in
1413 check_mapping_symbols.
1415 If .fill or other data filling directive generates zero sized data,
1416 the mapping symbol for the following code will have the same value
1417 as the one generated for the data filling directive. In this case,
1418 we replace the old symbol with the new one at the same address. */
1421 if (frag
->tc_frag_data
.first_map
!= NULL
)
1423 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1424 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1427 frag
->tc_frag_data
.first_map
= symbolP
;
1429 if (frag
->tc_frag_data
.last_map
!= NULL
)
1431 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1432 S_GET_VALUE (symbolP
));
1433 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1434 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1437 frag
->tc_frag_data
.last_map
= symbolP
;
1440 /* We must sometimes convert a region marked as code to data during
1441 code alignment, if an odd number of bytes have to be padded. The
1442 code mapping symbol is pushed to an aligned address. */
1445 insert_data_mapping_symbol (enum mstate state
,
1446 valueT value
, fragS
* frag
, offsetT bytes
)
1448 /* If there was already a mapping symbol, remove it. */
1449 if (frag
->tc_frag_data
.last_map
!= NULL
1450 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1451 frag
->fr_address
+ value
)
1453 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1457 know (frag
->tc_frag_data
.first_map
== symp
);
1458 frag
->tc_frag_data
.first_map
= NULL
;
1460 frag
->tc_frag_data
.last_map
= NULL
;
1461 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1464 make_mapping_symbol (MAP_DATA
, value
, frag
);
1465 make_mapping_symbol (state
, value
+ bytes
, frag
);
1468 static void mapping_state_2 (enum mstate state
, int max_chars
);
1470 /* Set the mapping state to STATE. Only call this when about to
1471 emit some STATE bytes to the file. */
1474 mapping_state (enum mstate state
)
1476 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1478 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1480 if (mapstate
== state
)
1481 /* The mapping symbol has already been emitted.
1482 There is nothing else to do. */
1484 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
1485 /* This case will be evaluated later in the next else. */
1487 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1489 /* Only add the symbol if the offset is > 0:
1490 if we're at the first frag, check it's size > 0;
1491 if we're not at the first frag, then for sure
1492 the offset is > 0. */
1493 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1494 const int add_symbol
= (frag_now
!= frag_first
)
1495 || (frag_now_fix () > 0);
1498 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1501 mapping_state_2 (state
, 0);
1505 /* Same as mapping_state, but MAX_CHARS bytes have already been
1506 allocated. Put the mapping symbol that far back. */
1509 mapping_state_2 (enum mstate state
, int max_chars
)
1511 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1513 if (!SEG_NORMAL (now_seg
))
1516 if (mapstate
== state
)
1517 /* The mapping symbol has already been emitted.
1518 There is nothing else to do. */
1521 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1522 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1525 #define mapping_state(x) /* nothing */
1526 #define mapping_state_2(x, y) /* nothing */
1529 /* Directives: sectioning and alignment. */
1532 s_bss (int ignore ATTRIBUTE_UNUSED
)
1534 /* We don't support putting frags in the BSS segment, we fake it by
1535 marking in_bss, then looking at s_skip for clues. */
1536 subseg_set (bss_section
, 0);
1537 demand_empty_rest_of_line ();
1538 mapping_state (MAP_DATA
);
1542 s_even (int ignore ATTRIBUTE_UNUSED
)
1544 /* Never make frag if expect extra pass. */
1546 frag_align (1, 0, 0);
1548 record_alignment (now_seg
, 1);
1550 demand_empty_rest_of_line ();
1553 /* Directives: Literal pools. */
1555 static literal_pool
*
1556 find_literal_pool (int size
)
1560 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1562 if (pool
->section
== now_seg
1563 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1570 static literal_pool
*
1571 find_or_make_literal_pool (int size
)
1573 /* Next literal pool ID number. */
1574 static unsigned int latest_pool_num
= 1;
1577 pool
= find_literal_pool (size
);
1581 /* Create a new pool. */
1582 pool
= xmalloc (sizeof (*pool
));
1586 /* Currently we always put the literal pool in the current text
1587 section. If we were generating "small" model code where we
1588 knew that all code and initialised data was within 1MB then
1589 we could output literals to mergeable, read-only data
1592 pool
->next_free_entry
= 0;
1593 pool
->section
= now_seg
;
1594 pool
->sub_section
= now_subseg
;
1596 pool
->next
= list_of_pools
;
1597 pool
->symbol
= NULL
;
1599 /* Add it to the list. */
1600 list_of_pools
= pool
;
1603 /* New pools, and emptied pools, will have a NULL symbol. */
1604 if (pool
->symbol
== NULL
)
1606 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1607 (valueT
) 0, &zero_address_frag
);
1608 pool
->id
= latest_pool_num
++;
1615 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1616 Return TRUE on success, otherwise return FALSE. */
1618 add_to_lit_pool (expressionS
*exp
, int size
)
1623 pool
= find_or_make_literal_pool (size
);
1625 /* Check if this literal value is already in the pool. */
1626 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1628 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1630 if ((litexp
->X_op
== exp
->X_op
)
1631 && (exp
->X_op
== O_constant
)
1632 && (litexp
->X_add_number
== exp
->X_add_number
)
1633 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1636 if ((litexp
->X_op
== exp
->X_op
)
1637 && (exp
->X_op
== O_symbol
)
1638 && (litexp
->X_add_number
== exp
->X_add_number
)
1639 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1640 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1644 /* Do we need to create a new entry? */
1645 if (entry
== pool
->next_free_entry
)
1647 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1649 set_syntax_error (_("literal pool overflow"));
1653 pool
->literals
[entry
].exp
= *exp
;
1654 pool
->next_free_entry
+= 1;
1655 if (exp
->X_op
== O_big
)
1657 /* PR 16688: Bignums are held in a single global array. We must
1658 copy and preserve that value now, before it is overwritten. */
1659 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1660 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1661 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1664 pool
->literals
[entry
].bignum
= NULL
;
1667 exp
->X_op
= O_symbol
;
1668 exp
->X_add_number
= ((int) entry
) * size
;
1669 exp
->X_add_symbol
= pool
->symbol
;
1674 /* Can't use symbol_new here, so have to create a symbol and then at
1675 a later date assign it a value. Thats what these functions do. */
1678 symbol_locate (symbolS
* symbolP
,
1679 const char *name
,/* It is copied, the caller can modify. */
1680 segT segment
, /* Segment identifier (SEG_<something>). */
1681 valueT valu
, /* Symbol value. */
1682 fragS
* frag
) /* Associated fragment. */
1685 char *preserved_copy_of_name
;
1687 name_length
= strlen (name
) + 1; /* +1 for \0. */
1688 obstack_grow (¬es
, name
, name_length
);
1689 preserved_copy_of_name
= obstack_finish (¬es
);
1691 #ifdef tc_canonicalize_symbol_name
1692 preserved_copy_of_name
=
1693 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1696 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1698 S_SET_SEGMENT (symbolP
, segment
);
1699 S_SET_VALUE (symbolP
, valu
);
1700 symbol_clear_list_pointers (symbolP
);
1702 symbol_set_frag (symbolP
, frag
);
1704 /* Link to end of symbol chain. */
1706 extern int symbol_table_frozen
;
1708 if (symbol_table_frozen
)
1712 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1714 obj_symbol_new_hook (symbolP
);
1716 #ifdef tc_symbol_new_hook
1717 tc_symbol_new_hook (symbolP
);
1721 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1722 #endif /* DEBUG_SYMS */
1727 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1734 for (align
= 2; align
<= 4; align
++)
1736 int size
= 1 << align
;
1738 pool
= find_literal_pool (size
);
1739 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1742 mapping_state (MAP_DATA
);
1744 /* Align pool as you have word accesses.
1745 Only make a frag if we have to. */
1747 frag_align (align
, 0, 0);
1749 record_alignment (now_seg
, align
);
1751 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1753 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1754 (valueT
) frag_now_fix (), frag_now
);
1755 symbol_table_insert (pool
->symbol
);
1757 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1759 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1761 if (exp
->X_op
== O_big
)
1763 /* PR 16688: Restore the global bignum value. */
1764 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1765 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1766 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1769 /* First output the expression in the instruction to the pool. */
1770 emit_expr (exp
, size
); /* .word|.xword */
1772 if (exp
->X_op
== O_big
)
1774 free (pool
->literals
[entry
].bignum
);
1775 pool
->literals
[entry
].bignum
= NULL
;
1779 /* Mark the pool as empty. */
1780 pool
->next_free_entry
= 0;
1781 pool
->symbol
= NULL
;
1786 /* Forward declarations for functions below, in the MD interface
1788 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1789 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1791 /* Directives: Data. */
1792 /* N.B. the support for relocation suffix in this directive needs to be
1793 implemented properly. */
1796 s_aarch64_elf_cons (int nbytes
)
1800 #ifdef md_flush_pending_output
1801 md_flush_pending_output ();
1804 if (is_it_end_of_statement ())
1806 demand_empty_rest_of_line ();
1810 #ifdef md_cons_align
1811 md_cons_align (nbytes
);
1814 mapping_state (MAP_DATA
);
1817 struct reloc_table_entry
*reloc
;
1821 if (exp
.X_op
!= O_symbol
)
1822 emit_expr (&exp
, (unsigned int) nbytes
);
1825 skip_past_char (&input_line_pointer
, '#');
1826 if (skip_past_char (&input_line_pointer
, ':'))
1828 reloc
= find_reloc_table_entry (&input_line_pointer
);
1830 as_bad (_("unrecognized relocation suffix"));
1832 as_bad (_("unimplemented relocation suffix"));
1833 ignore_rest_of_line ();
1837 emit_expr (&exp
, (unsigned int) nbytes
);
1840 while (*input_line_pointer
++ == ',');
1842 /* Put terminator back into stream. */
1843 input_line_pointer
--;
1844 demand_empty_rest_of_line ();
1847 #endif /* OBJ_ELF */
1849 /* Output a 32-bit word, but mark as an instruction. */
1852 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1856 #ifdef md_flush_pending_output
1857 md_flush_pending_output ();
1860 if (is_it_end_of_statement ())
1862 demand_empty_rest_of_line ();
1867 frag_align_code (2, 0);
1869 mapping_state (MAP_INSN
);
1875 if (exp
.X_op
!= O_constant
)
1877 as_bad (_("constant expression required"));
1878 ignore_rest_of_line ();
1882 if (target_big_endian
)
1884 unsigned int val
= exp
.X_add_number
;
1885 exp
.X_add_number
= SWAP_32 (val
);
1887 emit_expr (&exp
, 4);
1889 while (*input_line_pointer
++ == ',');
1891 /* Put terminator back into stream. */
1892 input_line_pointer
--;
1893 demand_empty_rest_of_line ();
1897 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1900 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1904 /* Since we're just labelling the code, there's no need to define a
1907 /* Make sure there is enough room in this frag for the following
1908 blr. This trick only works if the blr follows immediately after
1909 the .tlsdesc directive. */
1911 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1912 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1914 demand_empty_rest_of_line ();
1916 #endif /* OBJ_ELF */
1918 static void s_aarch64_arch (int);
1919 static void s_aarch64_cpu (int);
1920 static void s_aarch64_arch_extension (int);
1922 /* This table describes all the machine specific pseudo-ops the assembler
1923 has to support. The fields are:
1924 pseudo-op name without dot
1925 function to call to execute this pseudo-op
1926 Integer arg to pass to the function. */
1928 const pseudo_typeS md_pseudo_table
[] = {
1929 /* Never called because '.req' does not start a line. */
1931 {"unreq", s_unreq
, 0},
1933 {"even", s_even
, 0},
1934 {"ltorg", s_ltorg
, 0},
1935 {"pool", s_ltorg
, 0},
1936 {"cpu", s_aarch64_cpu
, 0},
1937 {"arch", s_aarch64_arch
, 0},
1938 {"arch_extension", s_aarch64_arch_extension
, 0},
1939 {"inst", s_aarch64_inst
, 0},
1941 {"tlsdesccall", s_tlsdesccall
, 0},
1942 {"word", s_aarch64_elf_cons
, 4},
1943 {"long", s_aarch64_elf_cons
, 4},
1944 {"xword", s_aarch64_elf_cons
, 8},
1945 {"dword", s_aarch64_elf_cons
, 8},
1951 /* Check whether STR points to a register name followed by a comma or the
1952 end of line; REG_TYPE indicates which register types are checked
1953 against. Return TRUE if STR is such a register name; otherwise return
1954 FALSE. The function does not intend to produce any diagnostics, but since
1955 the register parser aarch64_reg_parse, which is called by this function,
1956 does produce diagnostics, we call clear_error to clear any diagnostics
1957 that may be generated by aarch64_reg_parse.
1958 Also, the function returns FALSE directly if there is any user error
1959 present at the function entry. This prevents the existing diagnostics
1960 state from being spoiled.
1961 The function currently serves parse_constant_immediate and
1962 parse_big_immediate only. */
1964 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1968 /* Prevent the diagnostics state from being spoiled. */
1972 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1974 /* Clear the parsing error that may be set by the reg parser. */
1977 if (reg
== PARSE_FAIL
)
1980 skip_whitespace (str
);
1981 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1987 /* Parser functions used exclusively in instruction operands. */
1989 /* Parse an immediate expression which may not be constant.
1991 To prevent the expression parser from pushing a register name
1992 into the symbol table as an undefined symbol, firstly a check is
1993 done to find out whether STR is a valid register name followed
1994 by a comma or the end of line. Return FALSE if STR is such a
1998 parse_immediate_expression (char **str
, expressionS
*exp
)
2000 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2002 set_recoverable_error (_("immediate operand required"));
2006 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2008 if (exp
->X_op
== O_absent
)
2010 set_fatal_syntax_error (_("missing immediate expression"));
2017 /* Constant immediate-value read function for use in insn parsing.
2018 STR points to the beginning of the immediate (with the optional
2019 leading #); *VAL receives the value.
2021 Return TRUE on success; otherwise return FALSE. */
2024 parse_constant_immediate (char **str
, int64_t * val
)
2028 if (! parse_immediate_expression (str
, &exp
))
2031 if (exp
.X_op
!= O_constant
)
2033 set_syntax_error (_("constant expression required"));
2037 *val
= exp
.X_add_number
;
2042 encode_imm_float_bits (uint32_t imm
)
2044 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2045 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2048 /* Return TRUE if the single-precision floating-point value encoded in IMM
2049 can be expressed in the AArch64 8-bit signed floating-point format with
2050 3-bit exponent and normalized 4 bits of precision; in other words, the
2051 floating-point value must be expressable as
2052 (+/-) n / 16 * power (2, r)
2053 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2056 aarch64_imm_float_p (uint32_t imm
)
2058 /* If a single-precision floating-point value has the following bit
2059 pattern, it can be expressed in the AArch64 8-bit floating-point
2062 3 32222222 2221111111111
2063 1 09876543 21098765432109876543210
2064 n Eeeeeexx xxxx0000000000000000000
2066 where n, e and each x are either 0 or 1 independently, with
2071 /* Prepare the pattern for 'Eeeeee'. */
2072 if (((imm
>> 30) & 0x1) == 0)
2073 pattern
= 0x3e000000;
2075 pattern
= 0x40000000;
2077 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2078 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2081 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2083 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2084 8-bit signed floating-point format with 3-bit exponent and normalized 4
2085 bits of precision (i.e. can be used in an FMOV instruction); return the
2086 equivalent single-precision encoding in *FPWORD.
2088 Otherwise return FALSE. */
2091 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2093 /* If a double-precision floating-point value has the following bit
2094 pattern, it can be expressed in the AArch64 8-bit floating-point
2097 6 66655555555 554444444...21111111111
2098 3 21098765432 109876543...098765432109876543210
2099 n Eeeeeeeeexx xxxx00000...000000000000000000000
2101 where n, e and each x are either 0 or 1 independently, with
2105 uint32_t high32
= imm
>> 32;
2107 /* Lower 32 bits need to be 0s. */
2108 if ((imm
& 0xffffffff) != 0)
2111 /* Prepare the pattern for 'Eeeeeeeee'. */
2112 if (((high32
>> 30) & 0x1) == 0)
2113 pattern
= 0x3fc00000;
2115 pattern
= 0x40000000;
2117 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2118 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2120 /* Convert to the single-precision encoding.
2122 n Eeeeeeeeexx xxxx00000...000000000000000000000
2124 n Eeeeeexx xxxx0000000000000000000. */
2125 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2126 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2133 /* Parse a floating-point immediate. Return TRUE on success and return the
2134 value in *IMMED in the format of IEEE754 single-precision encoding.
2135 *CCP points to the start of the string; DP_P is TRUE when the immediate
2136 is expected to be in double-precision (N.B. this only matters when
2137 hexadecimal representation is involved).
2139 N.B. 0.0 is accepted by this function. */
2142 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2146 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2147 int found_fpchar
= 0;
2149 unsigned fpword
= 0;
2150 bfd_boolean hex_p
= FALSE
;
2152 skip_past_char (&str
, '#');
2155 skip_whitespace (fpnum
);
2157 if (strncmp (fpnum
, "0x", 2) == 0)
2159 /* Support the hexadecimal representation of the IEEE754 encoding.
2160 Double-precision is expected when DP_P is TRUE, otherwise the
2161 representation should be in single-precision. */
2162 if (! parse_constant_immediate (&str
, &val
))
2167 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2170 else if ((uint64_t) val
> 0xffffffff)
2179 /* We must not accidentally parse an integer as a floating-point number.
2180 Make sure that the value we parse is not an integer by checking for
2181 special characters '.' or 'e'. */
2182 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2183 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2197 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2200 /* Our FP word must be 32 bits (single-precision FP). */
2201 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2203 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2208 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2216 set_fatal_syntax_error (_("invalid floating-point constant"));
2220 /* Less-generic immediate-value read function with the possibility of loading
2221 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2224 To prevent the expression parser from pushing a register name into the
2225 symbol table as an undefined symbol, a check is firstly done to find
2226 out whether STR is a valid register name followed by a comma or the end
2227 of line. Return FALSE if STR is such a register. */
2230 parse_big_immediate (char **str
, int64_t *imm
)
2234 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2236 set_syntax_error (_("immediate operand required"));
2240 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2242 if (inst
.reloc
.exp
.X_op
== O_constant
)
2243 *imm
= inst
.reloc
.exp
.X_add_number
;
2250 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2251 if NEED_LIBOPCODES is non-zero, the fixup will need
2252 assistance from the libopcodes. */
2255 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2256 const aarch64_opnd_info
*operand
,
2257 int need_libopcodes_p
)
2259 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2260 reloc
->opnd
= operand
->type
;
2261 if (need_libopcodes_p
)
2262 reloc
->need_libopcodes_p
= 1;
2265 /* Return TRUE if the instruction needs to be fixed up later internally by
2266 the GAS; otherwise return FALSE. */
2268 static inline bfd_boolean
2269 aarch64_gas_internal_fixup_p (void)
2271 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2274 /* Assign the immediate value to the relavant field in *OPERAND if
2275 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2276 needs an internal fixup in a later stage.
2277 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2278 IMM.VALUE that may get assigned with the constant. */
2280 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2281 aarch64_opnd_info
*operand
,
2283 int need_libopcodes_p
,
2286 if (reloc
->exp
.X_op
== O_constant
)
2289 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2291 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2292 reloc
->type
= BFD_RELOC_UNUSED
;
2296 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2297 /* Tell libopcodes to ignore this operand or not. This is helpful
2298 when one of the operands needs to be fixed up later but we need
2299 libopcodes to check the other operands. */
2300 operand
->skip
= skip_p
;
2304 /* Relocation modifiers. Each entry in the table contains the textual
2305 name for the relocation which may be placed before a symbol used as
2306 a load/store offset, or add immediate. It must be surrounded by a
2307 leading and trailing colon, for example:
2309 ldr x0, [x1, #:rello:varsym]
2310 add x0, x1, #:rello:varsym */
2312 struct reloc_table_entry
2316 bfd_reloc_code_real_type adrp_type
;
2317 bfd_reloc_code_real_type movw_type
;
2318 bfd_reloc_code_real_type add_type
;
2319 bfd_reloc_code_real_type ldst_type
;
2322 static struct reloc_table_entry reloc_table
[] = {
2323 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2327 BFD_RELOC_AARCH64_ADD_LO12
,
2328 BFD_RELOC_AARCH64_LDST_LO12
},
2330 /* Higher 21 bits of pc-relative page offset: ADRP */
2332 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2337 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2339 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2344 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2347 BFD_RELOC_AARCH64_MOVW_G0
,
2351 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2354 BFD_RELOC_AARCH64_MOVW_G0_S
,
2358 /* Less significant bits 0-15 of address/value: MOVK, no check */
2361 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2365 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2368 BFD_RELOC_AARCH64_MOVW_G1
,
2372 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2375 BFD_RELOC_AARCH64_MOVW_G1_S
,
2379 /* Less significant bits 16-31 of address/value: MOVK, no check */
2382 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2386 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2389 BFD_RELOC_AARCH64_MOVW_G2
,
2393 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2396 BFD_RELOC_AARCH64_MOVW_G2_S
,
2400 /* Less significant bits 32-47 of address/value: MOVK, no check */
2403 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2407 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2410 BFD_RELOC_AARCH64_MOVW_G3
,
2414 /* Get to the page containing GOT entry for a symbol. */
2416 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2419 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2421 /* 12 bit offset into the page containing GOT entry for that symbol. */
2426 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
},
2428 /* Get to the page containing GOT TLS entry for a symbol */
2430 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2435 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2439 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2442 /* Get to the page containing GOT TLS entry for a symbol */
2444 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2449 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2453 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2454 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
},
2456 /* Get to the page containing GOT TLS entry for a symbol */
2458 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2463 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2464 {"gottprel_lo12", 0,
2468 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
},
2470 /* Get tp offset for a symbol. */
2474 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2477 /* Get tp offset for a symbol. */
2481 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2484 /* Get tp offset for a symbol. */
2488 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2491 /* Get tp offset for a symbol. */
2492 {"tprel_lo12_nc", 0,
2495 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2498 /* Most significant bits 32-47 of address/value: MOVZ. */
2501 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2505 /* Most significant bits 16-31 of address/value: MOVZ. */
2508 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2512 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2515 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2519 /* Most significant bits 0-15 of address/value: MOVZ. */
2522 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2526 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2529 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2534 /* Given the address of a pointer pointing to the textual name of a
2535 relocation as may appear in assembler source, attempt to find its
2536 details in reloc_table. The pointer will be updated to the character
2537 after the trailing colon. On failure, NULL will be returned;
2538 otherwise return the reloc_table_entry. */
2540 static struct reloc_table_entry
*
2541 find_reloc_table_entry (char **str
)
2544 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2546 int length
= strlen (reloc_table
[i
].name
);
2548 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2549 && (*str
)[length
] == ':')
2551 *str
+= (length
+ 1);
2552 return &reloc_table
[i
];
2559 /* Mode argument to parse_shift and parser_shifter_operand. */
2560 enum parse_shift_mode
2562 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2564 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2566 SHIFTED_LSL
, /* bare "lsl #n" */
2567 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2568 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2571 /* Parse a <shift> operator on an AArch64 data processing instruction.
2572 Return TRUE on success; otherwise return FALSE. */
2574 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2576 const struct aarch64_name_value_pair
*shift_op
;
2577 enum aarch64_modifier_kind kind
;
2583 for (p
= *str
; ISALPHA (*p
); p
++)
2588 set_syntax_error (_("shift expression expected"));
2592 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2594 if (shift_op
== NULL
)
2596 set_syntax_error (_("shift operator expected"));
2600 kind
= aarch64_get_operand_modifier (shift_op
);
2602 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2604 set_syntax_error (_("invalid use of 'MSL'"));
2610 case SHIFTED_LOGIC_IMM
:
2611 if (aarch64_extend_operator_p (kind
) == TRUE
)
2613 set_syntax_error (_("extending shift is not permitted"));
2618 case SHIFTED_ARITH_IMM
:
2619 if (kind
== AARCH64_MOD_ROR
)
2621 set_syntax_error (_("'ROR' shift is not permitted"));
2627 if (kind
!= AARCH64_MOD_LSL
)
2629 set_syntax_error (_("only 'LSL' shift is permitted"));
2634 case SHIFTED_REG_OFFSET
:
2635 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2636 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2638 set_fatal_syntax_error
2639 (_("invalid shift for the register offset addressing mode"));
2644 case SHIFTED_LSL_MSL
:
2645 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2647 set_syntax_error (_("invalid shift operator"));
2656 /* Whitespace can appear here if the next thing is a bare digit. */
2657 skip_whitespace (p
);
2659 /* Parse shift amount. */
2661 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2662 exp
.X_op
= O_absent
;
2665 if (is_immediate_prefix (*p
))
2670 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2672 if (exp
.X_op
== O_absent
)
2674 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2676 set_syntax_error (_("missing shift amount"));
2679 operand
->shifter
.amount
= 0;
2681 else if (exp
.X_op
!= O_constant
)
2683 set_syntax_error (_("constant shift amount required"));
2686 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2688 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2693 operand
->shifter
.amount
= exp
.X_add_number
;
2694 operand
->shifter
.amount_present
= 1;
2697 operand
->shifter
.operator_present
= 1;
2698 operand
->shifter
.kind
= kind
;
2704 /* Parse a <shifter_operand> for a data processing instruction:
2707 #<immediate>, LSL #imm
2709 Validation of immediate operands is deferred to md_apply_fix.
2711 Return TRUE on success; otherwise return FALSE. */
2714 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2715 enum parse_shift_mode mode
)
2719 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2724 /* Accept an immediate expression. */
2725 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2728 /* Accept optional LSL for arithmetic immediate values. */
2729 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2730 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2733 /* Not accept any shifter for logical immediate values. */
2734 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2735 && parse_shift (&p
, operand
, mode
))
2737 set_syntax_error (_("unexpected shift operator"));
2745 /* Parse a <shifter_operand> for a data processing instruction:
2750 #<immediate>, LSL #imm
2752 where <shift> is handled by parse_shift above, and the last two
2753 cases are handled by the function above.
2755 Validation of immediate operands is deferred to md_apply_fix.
2757 Return TRUE on success; otherwise return FALSE. */
2760 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2761 enum parse_shift_mode mode
)
2764 int isreg32
, isregzero
;
2765 enum aarch64_operand_class opd_class
2766 = aarch64_get_operand_class (operand
->type
);
2769 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2771 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2773 set_syntax_error (_("unexpected register in the immediate operand"));
2777 if (!isregzero
&& reg
== REG_SP
)
2779 set_syntax_error (BAD_SP
);
2783 operand
->reg
.regno
= reg
;
2784 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2786 /* Accept optional shift operation on register. */
2787 if (! skip_past_comma (str
))
2790 if (! parse_shift (str
, operand
, mode
))
2795 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2798 (_("integer register expected in the extended/shifted operand "
2803 /* We have a shifted immediate variable. */
2804 return parse_shifter_operand_imm (str
, operand
, mode
);
2807 /* Return TRUE on success; return FALSE otherwise. */
2810 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
2811 enum parse_shift_mode mode
)
2815 /* Determine if we have the sequence of characters #: or just :
2816 coming next. If we do, then we check for a :rello: relocation
2817 modifier. If we don't, punt the whole lot to
2818 parse_shifter_operand. */
2820 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
2822 struct reloc_table_entry
*entry
;
2830 /* Try to parse a relocation. Anything else is an error. */
2831 if (!(entry
= find_reloc_table_entry (str
)))
2833 set_syntax_error (_("unknown relocation modifier"));
2837 if (entry
->add_type
== 0)
2840 (_("this relocation modifier is not allowed on this instruction"));
2844 /* Save str before we decompose it. */
2847 /* Next, we parse the expression. */
2848 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
2851 /* Record the relocation type (use the ADD variant here). */
2852 inst
.reloc
.type
= entry
->add_type
;
2853 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2855 /* If str is empty, we've reached the end, stop here. */
2859 /* Otherwise, we have a shifted reloc modifier, so rewind to
2860 recover the variable name and continue parsing for the shifter. */
2862 return parse_shifter_operand_imm (str
, operand
, mode
);
2865 return parse_shifter_operand (str
, operand
, mode
);
2868 /* Parse all forms of an address expression. Information is written
2869 to *OPERAND and/or inst.reloc.
2871 The A64 instruction set has the following addressing modes:
2874 [base] // in SIMD ld/st structure
2875 [base{,#0}] // in ld/st exclusive
2877 [base,Xm{,LSL #imm}]
2878 [base,Xm,SXTX {#imm}]
2879 [base,Wm,(S|U)XTW {#imm}]
2884 [base],Xm // in SIMD ld/st structure
2885 PC-relative (literal)
2889 (As a convenience, the notation "=immediate" is permitted in conjunction
2890 with the pc-relative literal load instructions to automatically place an
2891 immediate value or symbolic address in a nearby literal pool and generate
2892 a hidden label which references it.)
2894 Upon a successful parsing, the address structure in *OPERAND will be
2895 filled in the following way:
2897 .base_regno = <base>
2898 .offset.is_reg // 1 if the offset is a register
2900 .offset.regno = <Rm>
2902 For different addressing modes defined in the A64 ISA:
2905 .pcrel=0; .preind=1; .postind=0; .writeback=0
2907 .pcrel=0; .preind=1; .postind=0; .writeback=1
2909 .pcrel=0; .preind=0; .postind=1; .writeback=1
2910 PC-relative (literal)
2911 .pcrel=1; .preind=1; .postind=0; .writeback=0
2913 The shift/extension information, if any, will be stored in .shifter.
2915 It is the caller's responsibility to check for addressing modes not
2916 supported by the instruction, and to set inst.reloc.type. */
2919 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
2920 int accept_reg_post_index
)
2924 int isreg32
, isregzero
;
2925 expressionS
*exp
= &inst
.reloc
.exp
;
2927 if (! skip_past_char (&p
, '['))
2929 /* =immediate or label. */
2930 operand
->addr
.pcrel
= 1;
2931 operand
->addr
.preind
= 1;
2933 /* #:<reloc_op>:<symbol> */
2934 skip_past_char (&p
, '#');
2935 if (reloc
&& skip_past_char (&p
, ':'))
2937 struct reloc_table_entry
*entry
;
2939 /* Try to parse a relocation modifier. Anything else is
2941 entry
= find_reloc_table_entry (&p
);
2944 set_syntax_error (_("unknown relocation modifier"));
2948 if (entry
->ldst_type
== 0)
2951 (_("this relocation modifier is not allowed on this "
2957 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
2959 set_syntax_error (_("invalid relocation expression"));
2963 /* #:<reloc_op>:<expr> */
2964 /* Record the load/store relocation type. */
2965 inst
.reloc
.type
= entry
->ldst_type
;
2966 inst
.reloc
.pc_rel
= entry
->pc_rel
;
2971 if (skip_past_char (&p
, '='))
2972 /* =immediate; need to generate the literal in the literal pool. */
2973 inst
.gen_lit_pool
= 1;
2975 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
2977 set_syntax_error (_("invalid address"));
2988 /* Accept SP and reject ZR */
2989 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
2990 if (reg
== PARSE_FAIL
|| isreg32
)
2992 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
2995 operand
->addr
.base_regno
= reg
;
2998 if (skip_past_comma (&p
))
3001 operand
->addr
.preind
= 1;
3003 /* Reject SP and accept ZR */
3004 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3005 if (reg
!= PARSE_FAIL
)
3008 operand
->addr
.offset
.regno
= reg
;
3009 operand
->addr
.offset
.is_reg
= 1;
3010 /* Shifted index. */
3011 if (skip_past_comma (&p
))
3014 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3015 /* Use the diagnostics set in parse_shift, so not set new
3016 error message here. */
3020 [base,Xm{,LSL #imm}]
3021 [base,Xm,SXTX {#imm}]
3022 [base,Wm,(S|U)XTW {#imm}] */
3023 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3024 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3025 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3029 set_syntax_error (_("invalid use of 32-bit register offset"));
3035 set_syntax_error (_("invalid use of 64-bit register offset"));
3041 /* [Xn,#:<reloc_op>:<symbol> */
3042 skip_past_char (&p
, '#');
3043 if (reloc
&& skip_past_char (&p
, ':'))
3045 struct reloc_table_entry
*entry
;
3047 /* Try to parse a relocation modifier. Anything else is
3049 if (!(entry
= find_reloc_table_entry (&p
)))
3051 set_syntax_error (_("unknown relocation modifier"));
3055 if (entry
->ldst_type
== 0)
3058 (_("this relocation modifier is not allowed on this "
3063 /* [Xn,#:<reloc_op>: */
3064 /* We now have the group relocation table entry corresponding to
3065 the name in the assembler source. Next, we parse the
3067 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3069 set_syntax_error (_("invalid relocation expression"));
3073 /* [Xn,#:<reloc_op>:<expr> */
3074 /* Record the load/store relocation type. */
3075 inst
.reloc
.type
= entry
->ldst_type
;
3076 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3078 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3080 set_syntax_error (_("invalid expression in the address"));
3087 if (! skip_past_char (&p
, ']'))
3089 set_syntax_error (_("']' expected"));
3093 if (skip_past_char (&p
, '!'))
3095 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3097 set_syntax_error (_("register offset not allowed in pre-indexed "
3098 "addressing mode"));
3102 operand
->addr
.writeback
= 1;
3104 else if (skip_past_comma (&p
))
3107 operand
->addr
.postind
= 1;
3108 operand
->addr
.writeback
= 1;
3110 if (operand
->addr
.preind
)
3112 set_syntax_error (_("cannot combine pre- and post-indexing"));
3116 if (accept_reg_post_index
3117 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3118 &isregzero
)) != PARSE_FAIL
)
3123 set_syntax_error (_("invalid 32-bit register offset"));
3126 operand
->addr
.offset
.regno
= reg
;
3127 operand
->addr
.offset
.is_reg
= 1;
3129 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3132 set_syntax_error (_("invalid expression in the address"));
3137 /* If at this point neither .preind nor .postind is set, we have a
3138 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3139 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3141 if (operand
->addr
.writeback
)
3144 set_syntax_error (_("missing offset in the pre-indexed address"));
3147 operand
->addr
.preind
= 1;
3148 inst
.reloc
.exp
.X_op
= O_constant
;
3149 inst
.reloc
.exp
.X_add_number
= 0;
3156 /* Return TRUE on success; otherwise return FALSE. */
3158 parse_address (char **str
, aarch64_opnd_info
*operand
,
3159 int accept_reg_post_index
)
3161 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3164 /* Return TRUE on success; otherwise return FALSE. */
3166 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3168 return parse_address_main (str
, operand
, 1, 0);
3171 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3172 Return TRUE on success; otherwise return FALSE. */
3174 parse_half (char **str
, int *internal_fixup_p
)
3180 skip_past_char (&p
, '#');
3182 gas_assert (internal_fixup_p
);
3183 *internal_fixup_p
= 0;
3187 struct reloc_table_entry
*entry
;
3189 /* Try to parse a relocation. Anything else is an error. */
3191 if (!(entry
= find_reloc_table_entry (&p
)))
3193 set_syntax_error (_("unknown relocation modifier"));
3197 if (entry
->movw_type
== 0)
3200 (_("this relocation modifier is not allowed on this instruction"));
3204 inst
.reloc
.type
= entry
->movw_type
;
3207 *internal_fixup_p
= 1;
3209 /* Avoid parsing a register as a general symbol. */
3211 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3215 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3222 /* Parse an operand for an ADRP instruction:
3224 Return TRUE on success; otherwise return FALSE. */
3227 parse_adrp (char **str
)
3234 struct reloc_table_entry
*entry
;
3236 /* Try to parse a relocation. Anything else is an error. */
3238 if (!(entry
= find_reloc_table_entry (&p
)))
3240 set_syntax_error (_("unknown relocation modifier"));
3244 if (entry
->adrp_type
== 0)
3247 (_("this relocation modifier is not allowed on this instruction"));
3251 inst
.reloc
.type
= entry
->adrp_type
;
3254 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3256 inst
.reloc
.pc_rel
= 1;
3258 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3265 /* Miscellaneous. */
3267 /* Parse an option for a preload instruction. Returns the encoding for the
3268 option, or PARSE_FAIL. */
3271 parse_pldop (char **str
)
3274 const struct aarch64_name_value_pair
*o
;
3277 while (ISALNUM (*q
))
3280 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3288 /* Parse an option for a barrier instruction. Returns the encoding for the
3289 option, or PARSE_FAIL. */
3292 parse_barrier (char **str
)
3295 const asm_barrier_opt
*o
;
3298 while (ISALPHA (*q
))
3301 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3309 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3310 Returns the encoding for the option, or PARSE_FAIL.
3312 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3313 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3316 parse_sys_reg (char **str
, struct hash_control
*sys_regs
, int imple_defined_p
)
3320 const aarch64_sys_reg
*o
;
3324 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3326 *p
++ = TOLOWER (*q
);
3328 /* Assert that BUF be large enough. */
3329 gas_assert (p
- buf
== q
- *str
);
3331 o
= hash_find (sys_regs
, buf
);
3334 if (!imple_defined_p
)
3338 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3339 unsigned int op0
, op1
, cn
, cm
, op2
;
3341 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3344 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3346 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3351 if (aarch64_sys_reg_deprecated_p (o
))
3352 as_warn (_("system register name '%s' is deprecated and may be "
3353 "removed in a future release"), buf
);
3361 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3362 for the option, or NULL. */
3364 static const aarch64_sys_ins_reg
*
3365 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3369 const aarch64_sys_ins_reg
*o
;
3372 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3374 *p
++ = TOLOWER (*q
);
3377 o
= hash_find (sys_ins_regs
, buf
);
3385 #define po_char_or_fail(chr) do { \
3386 if (! skip_past_char (&str, chr)) \
3390 #define po_reg_or_fail(regtype) do { \
3391 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3392 if (val == PARSE_FAIL) \
3394 set_default_error (); \
3399 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3400 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3401 &isreg32, &isregzero); \
3402 if (val == PARSE_FAIL) \
3404 set_default_error (); \
3407 info->reg.regno = val; \
3409 info->qualifier = AARCH64_OPND_QLF_W; \
3411 info->qualifier = AARCH64_OPND_QLF_X; \
3414 #define po_imm_nc_or_fail() do { \
3415 if (! parse_constant_immediate (&str, &val)) \
3419 #define po_imm_or_fail(min, max) do { \
3420 if (! parse_constant_immediate (&str, &val)) \
3422 if (val < min || val > max) \
3424 set_fatal_syntax_error (_("immediate value out of range "\
3425 #min " to "#max)); \
3430 #define po_misc_or_fail(expr) do { \
3435 /* encode the 12-bit imm field of Add/sub immediate */
3436 static inline uint32_t
3437 encode_addsub_imm (uint32_t imm
)
3442 /* encode the shift amount field of Add/sub immediate */
3443 static inline uint32_t
3444 encode_addsub_imm_shift_amount (uint32_t cnt
)
3450 /* encode the imm field of Adr instruction */
3451 static inline uint32_t
3452 encode_adr_imm (uint32_t imm
)
3454 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3455 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3458 /* encode the immediate field of Move wide immediate */
3459 static inline uint32_t
3460 encode_movw_imm (uint32_t imm
)
3465 /* encode the 26-bit offset of unconditional branch */
3466 static inline uint32_t
3467 encode_branch_ofs_26 (uint32_t ofs
)
3469 return ofs
& ((1 << 26) - 1);
3472 /* encode the 19-bit offset of conditional branch and compare & branch */
3473 static inline uint32_t
3474 encode_cond_branch_ofs_19 (uint32_t ofs
)
3476 return (ofs
& ((1 << 19) - 1)) << 5;
3479 /* encode the 19-bit offset of ld literal */
3480 static inline uint32_t
3481 encode_ld_lit_ofs_19 (uint32_t ofs
)
3483 return (ofs
& ((1 << 19) - 1)) << 5;
3486 /* Encode the 14-bit offset of test & branch. */
3487 static inline uint32_t
3488 encode_tst_branch_ofs_14 (uint32_t ofs
)
3490 return (ofs
& ((1 << 14) - 1)) << 5;
3493 /* Encode the 16-bit imm field of svc/hvc/smc. */
3494 static inline uint32_t
3495 encode_svc_imm (uint32_t imm
)
3500 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3501 static inline uint32_t
3502 reencode_addsub_switch_add_sub (uint32_t opcode
)
3504 return opcode
^ (1 << 30);
3507 static inline uint32_t
3508 reencode_movzn_to_movz (uint32_t opcode
)
3510 return opcode
| (1 << 30);
3513 static inline uint32_t
3514 reencode_movzn_to_movn (uint32_t opcode
)
3516 return opcode
& ~(1 << 30);
3519 /* Overall per-instruction processing. */
3521 /* We need to be able to fix up arbitrary expressions in some statements.
3522 This is so that we can handle symbols that are an arbitrary distance from
3523 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3524 which returns part of an address in a form which will be valid for
3525 a data instruction. We do this by pushing the expression into a symbol
3526 in the expr_section, and creating a fix for that. */
3529 fix_new_aarch64 (fragS
* frag
,
3531 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3541 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3545 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3552 /* Diagnostics on operands errors. */
3554 /* By default, output verbose error message.
3555 Disable the verbose error message by -mno-verbose-error. */
3556 static int verbose_error_p
= 1;
3558 #ifdef DEBUG_AARCH64
3559 /* N.B. this is only for the purpose of debugging. */
3560 const char* operand_mismatch_kind_names
[] =
3563 "AARCH64_OPDE_RECOVERABLE",
3564 "AARCH64_OPDE_SYNTAX_ERROR",
3565 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3566 "AARCH64_OPDE_INVALID_VARIANT",
3567 "AARCH64_OPDE_OUT_OF_RANGE",
3568 "AARCH64_OPDE_UNALIGNED",
3569 "AARCH64_OPDE_REG_LIST",
3570 "AARCH64_OPDE_OTHER_ERROR",
3572 #endif /* DEBUG_AARCH64 */
3574 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3576 When multiple errors of different kinds are found in the same assembly
3577 line, only the error of the highest severity will be picked up for
3578 issuing the diagnostics. */
3580 static inline bfd_boolean
3581 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3582 enum aarch64_operand_error_kind rhs
)
3584 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3585 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3586 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3587 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3588 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3589 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3590 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3591 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3595 /* Helper routine to get the mnemonic name from the assembly instruction
3596 line; should only be called for the diagnosis purpose, as there is
3597 string copy operation involved, which may affect the runtime
3598 performance if used in elsewhere. */
3601 get_mnemonic_name (const char *str
)
3603 static char mnemonic
[32];
3606 /* Get the first 15 bytes and assume that the full name is included. */
3607 strncpy (mnemonic
, str
, 31);
3608 mnemonic
[31] = '\0';
3610 /* Scan up to the end of the mnemonic, which must end in white space,
3611 '.', or end of string. */
3612 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3617 /* Append '...' to the truncated long name. */
3618 if (ptr
- mnemonic
== 31)
3619 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3625 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3627 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3628 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3631 /* Data strutures storing one user error in the assembly code related to
3634 struct operand_error_record
3636 const aarch64_opcode
*opcode
;
3637 aarch64_operand_error detail
;
3638 struct operand_error_record
*next
;
3641 typedef struct operand_error_record operand_error_record
;
3643 struct operand_errors
3645 operand_error_record
*head
;
3646 operand_error_record
*tail
;
3649 typedef struct operand_errors operand_errors
;
3651 /* Top-level data structure reporting user errors for the current line of
3653 The way md_assemble works is that all opcodes sharing the same mnemonic
3654 name are iterated to find a match to the assembly line. In this data
3655 structure, each of the such opcodes will have one operand_error_record
3656 allocated and inserted. In other words, excessive errors related with
3657 a single opcode are disregarded. */
3658 operand_errors operand_error_report
;
3660 /* Free record nodes. */
3661 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3663 /* Initialize the data structure that stores the operand mismatch
3664 information on assembling one line of the assembly code. */
3666 init_operand_error_report (void)
3668 if (operand_error_report
.head
!= NULL
)
3670 gas_assert (operand_error_report
.tail
!= NULL
);
3671 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3672 free_opnd_error_record_nodes
= operand_error_report
.head
;
3673 operand_error_report
.head
= NULL
;
3674 operand_error_report
.tail
= NULL
;
3677 gas_assert (operand_error_report
.tail
== NULL
);
3680 /* Return TRUE if some operand error has been recorded during the
3681 parsing of the current assembly line using the opcode *OPCODE;
3682 otherwise return FALSE. */
3683 static inline bfd_boolean
3684 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3686 operand_error_record
*record
= operand_error_report
.head
;
3687 return record
&& record
->opcode
== opcode
;
3690 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3691 OPCODE field is initialized with OPCODE.
3692 N.B. only one record for each opcode, i.e. the maximum of one error is
3693 recorded for each instruction template. */
3696 add_operand_error_record (const operand_error_record
* new_record
)
3698 const aarch64_opcode
*opcode
= new_record
->opcode
;
3699 operand_error_record
* record
= operand_error_report
.head
;
3701 /* The record may have been created for this opcode. If not, we need
3703 if (! opcode_has_operand_error_p (opcode
))
3705 /* Get one empty record. */
3706 if (free_opnd_error_record_nodes
== NULL
)
3708 record
= xmalloc (sizeof (operand_error_record
));
3714 record
= free_opnd_error_record_nodes
;
3715 free_opnd_error_record_nodes
= record
->next
;
3717 record
->opcode
= opcode
;
3718 /* Insert at the head. */
3719 record
->next
= operand_error_report
.head
;
3720 operand_error_report
.head
= record
;
3721 if (operand_error_report
.tail
== NULL
)
3722 operand_error_report
.tail
= record
;
3724 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3725 && record
->detail
.index
<= new_record
->detail
.index
3726 && operand_error_higher_severity_p (record
->detail
.kind
,
3727 new_record
->detail
.kind
))
3729 /* In the case of multiple errors found on operands related with a
3730 single opcode, only record the error of the leftmost operand and
3731 only if the error is of higher severity. */
3732 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3733 " the existing error %s on operand %d",
3734 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3735 new_record
->detail
.index
,
3736 operand_mismatch_kind_names
[record
->detail
.kind
],
3737 record
->detail
.index
);
3741 record
->detail
= new_record
->detail
;
3745 record_operand_error_info (const aarch64_opcode
*opcode
,
3746 aarch64_operand_error
*error_info
)
3748 operand_error_record record
;
3749 record
.opcode
= opcode
;
3750 record
.detail
= *error_info
;
3751 add_operand_error_record (&record
);
3754 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3755 error message *ERROR, for operand IDX (count from 0). */
3758 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3759 enum aarch64_operand_error_kind kind
,
3762 aarch64_operand_error info
;
3763 memset(&info
, 0, sizeof (info
));
3767 record_operand_error_info (opcode
, &info
);
3771 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3772 enum aarch64_operand_error_kind kind
,
3773 const char* error
, const int *extra_data
)
3775 aarch64_operand_error info
;
3779 info
.data
[0] = extra_data
[0];
3780 info
.data
[1] = extra_data
[1];
3781 info
.data
[2] = extra_data
[2];
3782 record_operand_error_info (opcode
, &info
);
3786 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
3787 const char* error
, int lower_bound
,
3790 int data
[3] = {lower_bound
, upper_bound
, 0};
3791 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
3795 /* Remove the operand error record for *OPCODE. */
3796 static void ATTRIBUTE_UNUSED
3797 remove_operand_error_record (const aarch64_opcode
*opcode
)
3799 if (opcode_has_operand_error_p (opcode
))
3801 operand_error_record
* record
= operand_error_report
.head
;
3802 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
3803 operand_error_report
.head
= record
->next
;
3804 record
->next
= free_opnd_error_record_nodes
;
3805 free_opnd_error_record_nodes
= record
;
3806 if (operand_error_report
.head
== NULL
)
3808 gas_assert (operand_error_report
.tail
== record
);
3809 operand_error_report
.tail
= NULL
;
3814 /* Given the instruction in *INSTR, return the index of the best matched
3815 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3817 Return -1 if there is no qualifier sequence; return the first match
3818 if there is multiple matches found. */
3821 find_best_match (const aarch64_inst
*instr
,
3822 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
3824 int i
, num_opnds
, max_num_matched
, idx
;
3826 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3829 DEBUG_TRACE ("no operand");
3833 max_num_matched
= 0;
3836 /* For each pattern. */
3837 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
3840 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
3842 /* Most opcodes has much fewer patterns in the list. */
3843 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
3845 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
3846 if (i
!= 0 && idx
== -1)
3847 /* If nothing has been matched, return the 1st sequence. */
3852 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
3853 if (*qualifiers
== instr
->operands
[j
].qualifier
)
3856 if (num_matched
> max_num_matched
)
3858 max_num_matched
= num_matched
;
3863 DEBUG_TRACE ("return with %d", idx
);
3867 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3868 corresponding operands in *INSTR. */
3871 assign_qualifier_sequence (aarch64_inst
*instr
,
3872 const aarch64_opnd_qualifier_t
*qualifiers
)
3875 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
3876 gas_assert (num_opnds
);
3877 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
3878 instr
->operands
[i
].qualifier
= *qualifiers
;
3881 /* Print operands for the diagnosis purpose. */
3884 print_operands (char *buf
, const aarch64_opcode
*opcode
,
3885 const aarch64_opnd_info
*opnds
)
3889 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
3891 const size_t size
= 128;
3894 /* We regard the opcode operand info more, however we also look into
3895 the inst->operands to support the disassembling of the optional
3897 The two operand code should be the same in all cases, apart from
3898 when the operand can be optional. */
3899 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
3900 || opnds
[i
].type
== AARCH64_OPND_NIL
)
3903 /* Generate the operand string in STR. */
3904 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
3908 strcat (buf
, i
== 0 ? " " : ",");
3910 /* Append the operand string. */
3915 /* Send to stderr a string as information. */
3918 output_info (const char *format
, ...)
3924 as_where (&file
, &line
);
3928 fprintf (stderr
, "%s:%u: ", file
, line
);
3930 fprintf (stderr
, "%s: ", file
);
3932 fprintf (stderr
, _("Info: "));
3933 va_start (args
, format
);
3934 vfprintf (stderr
, format
, args
);
3936 (void) putc ('\n', stderr
);
3939 /* Output one operand error record. */
3942 output_operand_error_record (const operand_error_record
*record
, char *str
)
3944 const aarch64_operand_error
*detail
= &record
->detail
;
3945 int idx
= detail
->index
;
3946 const aarch64_opcode
*opcode
= record
->opcode
;
3947 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
3948 : AARCH64_OPND_NIL
);
3950 switch (detail
->kind
)
3952 case AARCH64_OPDE_NIL
:
3956 case AARCH64_OPDE_SYNTAX_ERROR
:
3957 case AARCH64_OPDE_RECOVERABLE
:
3958 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
3959 case AARCH64_OPDE_OTHER_ERROR
:
3960 /* Use the prepared error message if there is, otherwise use the
3961 operand description string to describe the error. */
3962 if (detail
->error
!= NULL
)
3965 as_bad (_("%s -- `%s'"), detail
->error
, str
);
3967 as_bad (_("%s at operand %d -- `%s'"),
3968 detail
->error
, idx
+ 1, str
);
3972 gas_assert (idx
>= 0);
3973 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
3974 aarch64_get_operand_desc (opd_code
), str
);
3978 case AARCH64_OPDE_INVALID_VARIANT
:
3979 as_bad (_("operand mismatch -- `%s'"), str
);
3980 if (verbose_error_p
)
3982 /* We will try to correct the erroneous instruction and also provide
3983 more information e.g. all other valid variants.
3985 The string representation of the corrected instruction and other
3986 valid variants are generated by
3988 1) obtaining the intermediate representation of the erroneous
3990 2) manipulating the IR, e.g. replacing the operand qualifier;
3991 3) printing out the instruction by calling the printer functions
3992 shared with the disassembler.
3994 The limitation of this method is that the exact input assembly
3995 line cannot be accurately reproduced in some cases, for example an
3996 optional operand present in the actual assembly line will be
3997 omitted in the output; likewise for the optional syntax rules,
3998 e.g. the # before the immediate. Another limitation is that the
3999 assembly symbols and relocation operations in the assembly line
4000 currently cannot be printed out in the error report. Last but not
4001 least, when there is other error(s) co-exist with this error, the
4002 'corrected' instruction may be still incorrect, e.g. given
4003 'ldnp h0,h1,[x0,#6]!'
4004 this diagnosis will provide the version:
4005 'ldnp s0,s1,[x0,#6]!'
4006 which is still not right. */
4007 size_t len
= strlen (get_mnemonic_name (str
));
4010 const size_t size
= 2048;
4012 aarch64_inst
*inst_base
= &inst
.base
;
4013 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4016 reset_aarch64_instruction (&inst
);
4017 inst_base
->opcode
= opcode
;
4019 /* Reset the error report so that there is no side effect on the
4020 following operand parsing. */
4021 init_operand_error_report ();
4024 result
= parse_operands (str
+ len
, opcode
)
4025 && programmer_friendly_fixup (&inst
);
4026 gas_assert (result
);
4027 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4029 gas_assert (!result
);
4031 /* Find the most matched qualifier sequence. */
4032 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4033 gas_assert (qlf_idx
> -1);
4035 /* Assign the qualifiers. */
4036 assign_qualifier_sequence (inst_base
,
4037 opcode
->qualifiers_list
[qlf_idx
]);
4039 /* Print the hint. */
4040 output_info (_(" did you mean this?"));
4041 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4042 print_operands (buf
, opcode
, inst_base
->operands
);
4043 output_info (_(" %s"), buf
);
4045 /* Print out other variant(s) if there is any. */
4047 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4048 output_info (_(" other valid variant(s):"));
4050 /* For each pattern. */
4051 qualifiers_list
= opcode
->qualifiers_list
;
4052 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4054 /* Most opcodes has much fewer patterns in the list.
4055 First NIL qualifier indicates the end in the list. */
4056 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4061 /* Mnemonics name. */
4062 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4064 /* Assign the qualifiers. */
4065 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4067 /* Print instruction. */
4068 print_operands (buf
, opcode
, inst_base
->operands
);
4070 output_info (_(" %s"), buf
);
4076 case AARCH64_OPDE_OUT_OF_RANGE
:
4077 if (detail
->data
[0] != detail
->data
[1])
4078 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4079 detail
->error
? detail
->error
: _("immediate value"),
4080 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4082 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4083 detail
->error
? detail
->error
: _("immediate value"),
4084 detail
->data
[0], idx
+ 1, str
);
4087 case AARCH64_OPDE_REG_LIST
:
4088 if (detail
->data
[0] == 1)
4089 as_bad (_("invalid number of registers in the list; "
4090 "only 1 register is expected at operand %d -- `%s'"),
4093 as_bad (_("invalid number of registers in the list; "
4094 "%d registers are expected at operand %d -- `%s'"),
4095 detail
->data
[0], idx
+ 1, str
);
4098 case AARCH64_OPDE_UNALIGNED
:
4099 as_bad (_("immediate value should be a multiple of "
4100 "%d at operand %d -- `%s'"),
4101 detail
->data
[0], idx
+ 1, str
);
4110 /* Process and output the error message about the operand mismatching.
4112 When this function is called, the operand error information had
4113 been collected for an assembly line and there will be multiple
4114 errors in the case of mulitple instruction templates; output the
4115 error message that most closely describes the problem. */
4118 output_operand_error_report (char *str
)
4120 int largest_error_pos
;
4121 const char *msg
= NULL
;
4122 enum aarch64_operand_error_kind kind
;
4123 operand_error_record
*curr
;
4124 operand_error_record
*head
= operand_error_report
.head
;
4125 operand_error_record
*record
= NULL
;
4127 /* No error to report. */
4131 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4133 /* Only one error. */
4134 if (head
== operand_error_report
.tail
)
4136 DEBUG_TRACE ("single opcode entry with error kind: %s",
4137 operand_mismatch_kind_names
[head
->detail
.kind
]);
4138 output_operand_error_record (head
, str
);
4142 /* Find the error kind of the highest severity. */
4143 DEBUG_TRACE ("multiple opcode entres with error kind");
4144 kind
= AARCH64_OPDE_NIL
;
4145 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4147 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4148 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4149 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4150 kind
= curr
->detail
.kind
;
4152 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4154 /* Pick up one of errors of KIND to report. */
4155 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4156 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4158 if (curr
->detail
.kind
!= kind
)
4160 /* If there are multiple errors, pick up the one with the highest
4161 mismatching operand index. In the case of multiple errors with
4162 the equally highest operand index, pick up the first one or the
4163 first one with non-NULL error message. */
4164 if (curr
->detail
.index
> largest_error_pos
4165 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4166 && curr
->detail
.error
!= NULL
))
4168 largest_error_pos
= curr
->detail
.index
;
4170 msg
= record
->detail
.error
;
4174 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4175 DEBUG_TRACE ("Pick up error kind %s to report",
4176 operand_mismatch_kind_names
[record
->detail
.kind
]);
4179 output_operand_error_record (record
, str
);
4182 /* Write an AARCH64 instruction to buf - always little-endian. */
4184 put_aarch64_insn (char *buf
, uint32_t insn
)
4186 unsigned char *where
= (unsigned char *) buf
;
4188 where
[1] = insn
>> 8;
4189 where
[2] = insn
>> 16;
4190 where
[3] = insn
>> 24;
4194 get_aarch64_insn (char *buf
)
4196 unsigned char *where
= (unsigned char *) buf
;
4198 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4203 output_inst (struct aarch64_inst
*new_inst
)
4207 to
= frag_more (INSN_SIZE
);
4209 frag_now
->tc_frag_data
.recorded
= 1;
4211 put_aarch64_insn (to
, inst
.base
.value
);
4213 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4215 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4216 INSN_SIZE
, &inst
.reloc
.exp
,
4219 DEBUG_TRACE ("Prepared relocation fix up");
4220 /* Don't check the addend value against the instruction size,
4221 that's the job of our code in md_apply_fix(). */
4222 fixp
->fx_no_overflow
= 1;
4223 if (new_inst
!= NULL
)
4224 fixp
->tc_fix_data
.inst
= new_inst
;
4225 if (aarch64_gas_internal_fixup_p ())
4227 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4228 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4229 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4233 dwarf2_emit_insn (INSN_SIZE
);
4236 /* Link together opcodes of the same name. */
4240 aarch64_opcode
*opcode
;
4241 struct templates
*next
;
4244 typedef struct templates templates
;
4247 lookup_mnemonic (const char *start
, int len
)
4249 templates
*templ
= NULL
;
4251 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4255 /* Subroutine of md_assemble, responsible for looking up the primary
4256 opcode from the mnemonic the user wrote. STR points to the
4257 beginning of the mnemonic. */
4260 opcode_lookup (char **str
)
4263 const aarch64_cond
*cond
;
4267 /* Scan up to the end of the mnemonic, which must end in white space,
4268 '.', or end of string. */
4269 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4276 inst
.cond
= COND_ALWAYS
;
4278 /* Handle a possible condition. */
4281 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4284 inst
.cond
= cond
->value
;
4298 if (inst
.cond
== COND_ALWAYS
)
4300 /* Look for unaffixed mnemonic. */
4301 return lookup_mnemonic (base
, len
);
4305 /* append ".c" to mnemonic if conditional */
4306 memcpy (condname
, base
, len
);
4307 memcpy (condname
+ len
, ".c", 2);
4310 return lookup_mnemonic (base
, len
);
4316 /* Internal helper routine converting a vector neon_type_el structure
4317 *VECTYPE to a corresponding operand qualifier. */
4319 static inline aarch64_opnd_qualifier_t
4320 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4322 /* Element size in bytes indexed by neon_el_type. */
4323 const unsigned char ele_size
[5]
4326 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4327 goto vectype_conversion_fail
;
4329 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4331 if (vectype
->defined
& NTA_HASINDEX
)
4332 /* Vector element register. */
4333 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4336 /* Vector register. */
4337 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4339 if (reg_size
!= 16 && reg_size
!= 8)
4340 goto vectype_conversion_fail
;
4341 /* The conversion is calculated based on the relation of the order of
4342 qualifiers to the vector element size and vector register size. */
4343 offset
= (vectype
->type
== NT_q
)
4344 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4345 gas_assert (offset
<= 8);
4346 return AARCH64_OPND_QLF_V_8B
+ offset
;
4349 vectype_conversion_fail
:
4350 first_error (_("bad vector arrangement type"));
4351 return AARCH64_OPND_QLF_NIL
;
4354 /* Process an optional operand that is found omitted from the assembly line.
4355 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4356 instruction's opcode entry while IDX is the index of this omitted operand.
4360 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4361 int idx
, aarch64_opnd_info
*operand
)
4363 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4364 gas_assert (optional_operand_p (opcode
, idx
));
4365 gas_assert (!operand
->present
);
4369 case AARCH64_OPND_Rd
:
4370 case AARCH64_OPND_Rn
:
4371 case AARCH64_OPND_Rm
:
4372 case AARCH64_OPND_Rt
:
4373 case AARCH64_OPND_Rt2
:
4374 case AARCH64_OPND_Rs
:
4375 case AARCH64_OPND_Ra
:
4376 case AARCH64_OPND_Rt_SYS
:
4377 case AARCH64_OPND_Rd_SP
:
4378 case AARCH64_OPND_Rn_SP
:
4379 case AARCH64_OPND_Fd
:
4380 case AARCH64_OPND_Fn
:
4381 case AARCH64_OPND_Fm
:
4382 case AARCH64_OPND_Fa
:
4383 case AARCH64_OPND_Ft
:
4384 case AARCH64_OPND_Ft2
:
4385 case AARCH64_OPND_Sd
:
4386 case AARCH64_OPND_Sn
:
4387 case AARCH64_OPND_Sm
:
4388 case AARCH64_OPND_Vd
:
4389 case AARCH64_OPND_Vn
:
4390 case AARCH64_OPND_Vm
:
4391 case AARCH64_OPND_VdD1
:
4392 case AARCH64_OPND_VnD1
:
4393 operand
->reg
.regno
= default_value
;
4396 case AARCH64_OPND_Ed
:
4397 case AARCH64_OPND_En
:
4398 case AARCH64_OPND_Em
:
4399 operand
->reglane
.regno
= default_value
;
4402 case AARCH64_OPND_IDX
:
4403 case AARCH64_OPND_BIT_NUM
:
4404 case AARCH64_OPND_IMMR
:
4405 case AARCH64_OPND_IMMS
:
4406 case AARCH64_OPND_SHLL_IMM
:
4407 case AARCH64_OPND_IMM_VLSL
:
4408 case AARCH64_OPND_IMM_VLSR
:
4409 case AARCH64_OPND_CCMP_IMM
:
4410 case AARCH64_OPND_FBITS
:
4411 case AARCH64_OPND_UIMM4
:
4412 case AARCH64_OPND_UIMM3_OP1
:
4413 case AARCH64_OPND_UIMM3_OP2
:
4414 case AARCH64_OPND_IMM
:
4415 case AARCH64_OPND_WIDTH
:
4416 case AARCH64_OPND_UIMM7
:
4417 case AARCH64_OPND_NZCV
:
4418 operand
->imm
.value
= default_value
;
4421 case AARCH64_OPND_EXCEPTION
:
4422 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4425 case AARCH64_OPND_BARRIER_ISB
:
4426 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4433 /* Process the relocation type for move wide instructions.
4434 Return TRUE on success; otherwise return FALSE. */
4437 process_movw_reloc_info (void)
4442 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4444 if (inst
.base
.opcode
->op
== OP_MOVK
)
4445 switch (inst
.reloc
.type
)
4447 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4448 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4449 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4450 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4451 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4452 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4453 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4454 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4456 (_("the specified relocation type is not allowed for MOVK"));
4462 switch (inst
.reloc
.type
)
4464 case BFD_RELOC_AARCH64_MOVW_G0
:
4465 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4466 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4467 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4468 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4471 case BFD_RELOC_AARCH64_MOVW_G1
:
4472 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4473 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4474 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4475 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4478 case BFD_RELOC_AARCH64_MOVW_G2
:
4479 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4480 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4481 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4484 set_fatal_syntax_error
4485 (_("the specified relocation type is not allowed for 32-bit "
4491 case BFD_RELOC_AARCH64_MOVW_G3
:
4494 set_fatal_syntax_error
4495 (_("the specified relocation type is not allowed for 32-bit "
4502 /* More cases should be added when more MOVW-related relocation types
4503 are supported in GAS. */
4504 gas_assert (aarch64_gas_internal_fixup_p ());
4505 /* The shift amount should have already been set by the parser. */
4508 inst
.base
.operands
[1].shifter
.amount
= shift
;
4512 /* A primitive log caculator. */
4514 static inline unsigned int
4515 get_logsz (unsigned int size
)
4517 const unsigned char ls
[16] =
4518 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4524 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4525 return ls
[size
- 1];
4528 /* Determine and return the real reloc type code for an instruction
4529 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4531 static inline bfd_reloc_code_real_type
4532 ldst_lo12_determine_real_reloc_type (void)
4535 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4536 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4538 const bfd_reloc_code_real_type reloc_ldst_lo12
[5] = {
4539 BFD_RELOC_AARCH64_LDST8_LO12
, BFD_RELOC_AARCH64_LDST16_LO12
,
4540 BFD_RELOC_AARCH64_LDST32_LO12
, BFD_RELOC_AARCH64_LDST64_LO12
,
4541 BFD_RELOC_AARCH64_LDST128_LO12
4544 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
);
4545 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4547 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4549 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4551 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4553 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4554 gas_assert (logsz
>= 0 && logsz
<= 4);
4556 return reloc_ldst_lo12
[logsz
];
4559 /* Check whether a register list REGINFO is valid. The registers must be
4560 numbered in increasing order (modulo 32), in increments of one or two.
4562 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4565 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4568 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4570 uint32_t i
, nb_regs
, prev_regno
, incr
;
4572 nb_regs
= 1 + (reginfo
& 0x3);
4574 prev_regno
= reginfo
& 0x1f;
4575 incr
= accept_alternate
? 2 : 1;
4577 for (i
= 1; i
< nb_regs
; ++i
)
4579 uint32_t curr_regno
;
4581 curr_regno
= reginfo
& 0x1f;
4582 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4584 prev_regno
= curr_regno
;
4590 /* Generic instruction operand parser. This does no encoding and no
4591 semantic validation; it merely squirrels values away in the inst
4592 structure. Returns TRUE or FALSE depending on whether the
4593 specified grammar matched. */
4596 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4599 char *backtrack_pos
= 0;
4600 const enum aarch64_opnd
*operands
= opcode
->operands
;
4603 skip_whitespace (str
);
4605 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4608 int isreg32
, isregzero
;
4609 int comma_skipped_p
= 0;
4610 aarch64_reg_type rtype
;
4611 struct neon_type_el vectype
;
4612 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4614 DEBUG_TRACE ("parse operand %d", i
);
4616 /* Assign the operand code. */
4617 info
->type
= operands
[i
];
4619 if (optional_operand_p (opcode
, i
))
4621 /* Remember where we are in case we need to backtrack. */
4622 gas_assert (!backtrack_pos
);
4623 backtrack_pos
= str
;
4626 /* Expect comma between operands; the backtrack mechanizm will take
4627 care of cases of omitted optional operand. */
4628 if (i
> 0 && ! skip_past_char (&str
, ','))
4630 set_syntax_error (_("comma expected between operands"));
4634 comma_skipped_p
= 1;
4636 switch (operands
[i
])
4638 case AARCH64_OPND_Rd
:
4639 case AARCH64_OPND_Rn
:
4640 case AARCH64_OPND_Rm
:
4641 case AARCH64_OPND_Rt
:
4642 case AARCH64_OPND_Rt2
:
4643 case AARCH64_OPND_Rs
:
4644 case AARCH64_OPND_Ra
:
4645 case AARCH64_OPND_Rt_SYS
:
4646 case AARCH64_OPND_PAIRREG
:
4647 po_int_reg_or_fail (1, 0);
4650 case AARCH64_OPND_Rd_SP
:
4651 case AARCH64_OPND_Rn_SP
:
4652 po_int_reg_or_fail (0, 1);
4655 case AARCH64_OPND_Rm_EXT
:
4656 case AARCH64_OPND_Rm_SFT
:
4657 po_misc_or_fail (parse_shifter_operand
4658 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4660 : SHIFTED_LOGIC_IMM
)));
4661 if (!info
->shifter
.operator_present
)
4663 /* Default to LSL if not present. Libopcodes prefers shifter
4664 kind to be explicit. */
4665 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4666 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4667 /* For Rm_EXT, libopcodes will carry out further check on whether
4668 or not stack pointer is used in the instruction (Recall that
4669 "the extend operator is not optional unless at least one of
4670 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4674 case AARCH64_OPND_Fd
:
4675 case AARCH64_OPND_Fn
:
4676 case AARCH64_OPND_Fm
:
4677 case AARCH64_OPND_Fa
:
4678 case AARCH64_OPND_Ft
:
4679 case AARCH64_OPND_Ft2
:
4680 case AARCH64_OPND_Sd
:
4681 case AARCH64_OPND_Sn
:
4682 case AARCH64_OPND_Sm
:
4683 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4684 if (val
== PARSE_FAIL
)
4686 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4689 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4691 info
->reg
.regno
= val
;
4692 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4695 case AARCH64_OPND_Vd
:
4696 case AARCH64_OPND_Vn
:
4697 case AARCH64_OPND_Vm
:
4698 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4699 if (val
== PARSE_FAIL
)
4701 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4704 if (vectype
.defined
& NTA_HASINDEX
)
4707 info
->reg
.regno
= val
;
4708 info
->qualifier
= vectype_to_qualifier (&vectype
);
4709 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4713 case AARCH64_OPND_VdD1
:
4714 case AARCH64_OPND_VnD1
:
4715 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4716 if (val
== PARSE_FAIL
)
4718 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4721 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4723 set_fatal_syntax_error
4724 (_("the top half of a 128-bit FP/SIMD register is expected"));
4727 info
->reg
.regno
= val
;
4728 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4729 here; it is correct for the purpose of encoding/decoding since
4730 only the register number is explicitly encoded in the related
4731 instructions, although this appears a bit hacky. */
4732 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4735 case AARCH64_OPND_Ed
:
4736 case AARCH64_OPND_En
:
4737 case AARCH64_OPND_Em
:
4738 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4739 if (val
== PARSE_FAIL
)
4741 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4744 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
4747 info
->reglane
.regno
= val
;
4748 info
->reglane
.index
= vectype
.index
;
4749 info
->qualifier
= vectype_to_qualifier (&vectype
);
4750 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4754 case AARCH64_OPND_LVn
:
4755 case AARCH64_OPND_LVt
:
4756 case AARCH64_OPND_LVt_AL
:
4757 case AARCH64_OPND_LEt
:
4758 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
4760 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
4762 set_fatal_syntax_error (_("invalid register list"));
4765 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
4766 info
->reglist
.num_regs
= (val
& 0x3) + 1;
4767 if (operands
[i
] == AARCH64_OPND_LEt
)
4769 if (!(vectype
.defined
& NTA_HASINDEX
))
4771 info
->reglist
.has_index
= 1;
4772 info
->reglist
.index
= vectype
.index
;
4774 else if (!(vectype
.defined
& NTA_HASTYPE
))
4776 info
->qualifier
= vectype_to_qualifier (&vectype
);
4777 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4781 case AARCH64_OPND_Cn
:
4782 case AARCH64_OPND_Cm
:
4783 po_reg_or_fail (REG_TYPE_CN
);
4786 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
4789 inst
.base
.operands
[i
].reg
.regno
= val
;
4792 case AARCH64_OPND_SHLL_IMM
:
4793 case AARCH64_OPND_IMM_VLSR
:
4794 po_imm_or_fail (1, 64);
4795 info
->imm
.value
= val
;
4798 case AARCH64_OPND_CCMP_IMM
:
4799 case AARCH64_OPND_FBITS
:
4800 case AARCH64_OPND_UIMM4
:
4801 case AARCH64_OPND_UIMM3_OP1
:
4802 case AARCH64_OPND_UIMM3_OP2
:
4803 case AARCH64_OPND_IMM_VLSL
:
4804 case AARCH64_OPND_IMM
:
4805 case AARCH64_OPND_WIDTH
:
4806 po_imm_nc_or_fail ();
4807 info
->imm
.value
= val
;
4810 case AARCH64_OPND_UIMM7
:
4811 po_imm_or_fail (0, 127);
4812 info
->imm
.value
= val
;
4815 case AARCH64_OPND_IDX
:
4816 case AARCH64_OPND_BIT_NUM
:
4817 case AARCH64_OPND_IMMR
:
4818 case AARCH64_OPND_IMMS
:
4819 po_imm_or_fail (0, 63);
4820 info
->imm
.value
= val
;
4823 case AARCH64_OPND_IMM0
:
4824 po_imm_nc_or_fail ();
4827 set_fatal_syntax_error (_("immediate zero expected"));
4830 info
->imm
.value
= 0;
4833 case AARCH64_OPND_FPIMM0
:
4836 bfd_boolean res1
= FALSE
, res2
= FALSE
;
4837 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4838 it is probably not worth the effort to support it. */
4839 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
4840 && !(res2
= parse_constant_immediate (&str
, &val
)))
4842 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
4844 info
->imm
.value
= 0;
4845 info
->imm
.is_fp
= 1;
4848 set_fatal_syntax_error (_("immediate zero expected"));
4852 case AARCH64_OPND_IMM_MOV
:
4855 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
4856 reg_name_p (str
, REG_TYPE_VN
))
4859 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
4861 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4862 later. fix_mov_imm_insn will try to determine a machine
4863 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4864 message if the immediate cannot be moved by a single
4866 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
4867 inst
.base
.operands
[i
].skip
= 1;
4871 case AARCH64_OPND_SIMD_IMM
:
4872 case AARCH64_OPND_SIMD_IMM_SFT
:
4873 if (! parse_big_immediate (&str
, &val
))
4875 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4877 /* need_libopcodes_p */ 1,
4880 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4881 shift, we don't check it here; we leave the checking to
4882 the libopcodes (operand_general_constraint_met_p). By
4883 doing this, we achieve better diagnostics. */
4884 if (skip_past_comma (&str
)
4885 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
4887 if (!info
->shifter
.operator_present
4888 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
4890 /* Default to LSL if not present. Libopcodes prefers shifter
4891 kind to be explicit. */
4892 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4893 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4897 case AARCH64_OPND_FPIMM
:
4898 case AARCH64_OPND_SIMD_FPIMM
:
4902 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
4904 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
4908 set_fatal_syntax_error (_("invalid floating-point constant"));
4911 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
4912 inst
.base
.operands
[i
].imm
.is_fp
= 1;
4916 case AARCH64_OPND_LIMM
:
4917 po_misc_or_fail (parse_shifter_operand (&str
, info
,
4918 SHIFTED_LOGIC_IMM
));
4919 if (info
->shifter
.operator_present
)
4921 set_fatal_syntax_error
4922 (_("shift not allowed for bitmask immediate"));
4925 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4927 /* need_libopcodes_p */ 1,
4931 case AARCH64_OPND_AIMM
:
4932 if (opcode
->op
== OP_ADD
)
4933 /* ADD may have relocation types. */
4934 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
4935 SHIFTED_ARITH_IMM
));
4937 po_misc_or_fail (parse_shifter_operand (&str
, info
,
4938 SHIFTED_ARITH_IMM
));
4939 switch (inst
.reloc
.type
)
4941 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
4942 info
->shifter
.amount
= 12;
4944 case BFD_RELOC_UNUSED
:
4945 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
4946 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
4947 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
4948 inst
.reloc
.pc_rel
= 0;
4953 info
->imm
.value
= 0;
4954 if (!info
->shifter
.operator_present
)
4956 /* Default to LSL if not present. Libopcodes prefers shifter
4957 kind to be explicit. */
4958 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4959 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4963 case AARCH64_OPND_HALF
:
4965 /* #<imm16> or relocation. */
4966 int internal_fixup_p
;
4967 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
4968 if (internal_fixup_p
)
4969 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
4970 skip_whitespace (str
);
4971 if (skip_past_comma (&str
))
4973 /* {, LSL #<shift>} */
4974 if (! aarch64_gas_internal_fixup_p ())
4976 set_fatal_syntax_error (_("can't mix relocation modifier "
4977 "with explicit shift"));
4980 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
4983 inst
.base
.operands
[i
].shifter
.amount
= 0;
4984 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
4985 inst
.base
.operands
[i
].imm
.value
= 0;
4986 if (! process_movw_reloc_info ())
4991 case AARCH64_OPND_EXCEPTION
:
4992 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
4993 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
4995 /* need_libopcodes_p */ 0,
4999 case AARCH64_OPND_NZCV
:
5001 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5005 info
->imm
.value
= nzcv
->value
;
5008 po_imm_or_fail (0, 15);
5009 info
->imm
.value
= val
;
5013 case AARCH64_OPND_COND
:
5014 case AARCH64_OPND_COND1
:
5015 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5017 if (info
->cond
== NULL
)
5019 set_syntax_error (_("invalid condition"));
5022 else if (operands
[i
] == AARCH64_OPND_COND1
5023 && (info
->cond
->value
& 0xe) == 0xe)
5025 /* Not allow AL or NV. */
5026 set_default_error ();
5031 case AARCH64_OPND_ADDR_ADRP
:
5032 po_misc_or_fail (parse_adrp (&str
));
5033 /* Clear the value as operand needs to be relocated. */
5034 info
->imm
.value
= 0;
5037 case AARCH64_OPND_ADDR_PCREL14
:
5038 case AARCH64_OPND_ADDR_PCREL19
:
5039 case AARCH64_OPND_ADDR_PCREL21
:
5040 case AARCH64_OPND_ADDR_PCREL26
:
5041 po_misc_or_fail (parse_address_reloc (&str
, info
));
5042 if (!info
->addr
.pcrel
)
5044 set_syntax_error (_("invalid pc-relative address"));
5047 if (inst
.gen_lit_pool
5048 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5050 /* Only permit "=value" in the literal load instructions.
5051 The literal will be generated by programmer_friendly_fixup. */
5052 set_syntax_error (_("invalid use of \"=immediate\""));
5055 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5057 set_syntax_error (_("unrecognized relocation suffix"));
5060 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5062 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5063 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5067 info
->imm
.value
= 0;
5068 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5069 switch (opcode
->iclass
)
5073 /* e.g. CBZ or B.COND */
5074 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5075 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5079 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5080 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5084 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5086 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5087 : BFD_RELOC_AARCH64_JUMP26
;
5090 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5091 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5094 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5095 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5101 inst
.reloc
.pc_rel
= 1;
5105 case AARCH64_OPND_ADDR_SIMPLE
:
5106 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5107 /* [<Xn|SP>{, #<simm>}] */
5108 po_char_or_fail ('[');
5109 po_reg_or_fail (REG_TYPE_R64_SP
);
5110 /* Accept optional ", #0". */
5111 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5112 && skip_past_char (&str
, ','))
5114 skip_past_char (&str
, '#');
5115 if (! skip_past_char (&str
, '0'))
5117 set_fatal_syntax_error
5118 (_("the optional immediate offset can only be 0"));
5122 po_char_or_fail (']');
5123 info
->addr
.base_regno
= val
;
5126 case AARCH64_OPND_ADDR_REGOFF
:
5127 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5128 po_misc_or_fail (parse_address (&str
, info
, 0));
5129 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5130 || !info
->addr
.preind
|| info
->addr
.postind
5131 || info
->addr
.writeback
)
5133 set_syntax_error (_("invalid addressing mode"));
5136 if (!info
->shifter
.operator_present
)
5138 /* Default to LSL if not present. Libopcodes prefers shifter
5139 kind to be explicit. */
5140 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5141 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5143 /* Qualifier to be deduced by libopcodes. */
5146 case AARCH64_OPND_ADDR_SIMM7
:
5147 po_misc_or_fail (parse_address (&str
, info
, 0));
5148 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5149 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5151 set_syntax_error (_("invalid addressing mode"));
5154 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5156 /* need_libopcodes_p */ 1,
5160 case AARCH64_OPND_ADDR_SIMM9
:
5161 case AARCH64_OPND_ADDR_SIMM9_2
:
5162 po_misc_or_fail (parse_address_reloc (&str
, info
));
5163 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5164 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5165 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5166 && info
->addr
.writeback
))
5168 set_syntax_error (_("invalid addressing mode"));
5171 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5173 set_syntax_error (_("relocation not allowed"));
5176 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5178 /* need_libopcodes_p */ 1,
5182 case AARCH64_OPND_ADDR_UIMM12
:
5183 po_misc_or_fail (parse_address_reloc (&str
, info
));
5184 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5185 || !info
->addr
.preind
|| info
->addr
.writeback
)
5187 set_syntax_error (_("invalid addressing mode"));
5190 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5191 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5192 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
)
5193 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5194 /* Leave qualifier to be determined by libopcodes. */
5197 case AARCH64_OPND_SIMD_ADDR_POST
:
5198 /* [<Xn|SP>], <Xm|#<amount>> */
5199 po_misc_or_fail (parse_address (&str
, info
, 1));
5200 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5202 set_syntax_error (_("invalid addressing mode"));
5205 if (!info
->addr
.offset
.is_reg
)
5207 if (inst
.reloc
.exp
.X_op
== O_constant
)
5208 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5211 set_fatal_syntax_error
5212 (_("writeback value should be an immediate constant"));
5219 case AARCH64_OPND_SYSREG
:
5220 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1))
5223 set_syntax_error (_("unknown or missing system register name"));
5226 inst
.base
.operands
[i
].sysreg
= val
;
5229 case AARCH64_OPND_PSTATEFIELD
:
5230 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0))
5233 set_syntax_error (_("unknown or missing PSTATE field name"));
5236 inst
.base
.operands
[i
].pstatefield
= val
;
5239 case AARCH64_OPND_SYSREG_IC
:
5240 inst
.base
.operands
[i
].sysins_op
=
5241 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5243 case AARCH64_OPND_SYSREG_DC
:
5244 inst
.base
.operands
[i
].sysins_op
=
5245 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5247 case AARCH64_OPND_SYSREG_AT
:
5248 inst
.base
.operands
[i
].sysins_op
=
5249 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5251 case AARCH64_OPND_SYSREG_TLBI
:
5252 inst
.base
.operands
[i
].sysins_op
=
5253 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5255 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5257 set_fatal_syntax_error ( _("unknown or missing operation name"));
5262 case AARCH64_OPND_BARRIER
:
5263 case AARCH64_OPND_BARRIER_ISB
:
5264 val
= parse_barrier (&str
);
5265 if (val
!= PARSE_FAIL
5266 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5268 /* ISB only accepts options name 'sy'. */
5270 (_("the specified option is not accepted in ISB"));
5271 /* Turn off backtrack as this optional operand is present. */
5275 /* This is an extension to accept a 0..15 immediate. */
5276 if (val
== PARSE_FAIL
)
5277 po_imm_or_fail (0, 15);
5278 info
->barrier
= aarch64_barrier_options
+ val
;
5281 case AARCH64_OPND_PRFOP
:
5282 val
= parse_pldop (&str
);
5283 /* This is an extension to accept a 0..31 immediate. */
5284 if (val
== PARSE_FAIL
)
5285 po_imm_or_fail (0, 31);
5286 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5290 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5293 /* If we get here, this operand was successfully parsed. */
5294 inst
.base
.operands
[i
].present
= 1;
5298 /* The parse routine should already have set the error, but in case
5299 not, set a default one here. */
5301 set_default_error ();
5303 if (! backtrack_pos
)
5304 goto parse_operands_return
;
5307 /* We reach here because this operand is marked as optional, and
5308 either no operand was supplied or the operand was supplied but it
5309 was syntactically incorrect. In the latter case we report an
5310 error. In the former case we perform a few more checks before
5311 dropping through to the code to insert the default operand. */
5313 char *tmp
= backtrack_pos
;
5314 char endchar
= END_OF_INSN
;
5316 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5318 skip_past_char (&tmp
, ',');
5320 if (*tmp
!= endchar
)
5321 /* The user has supplied an operand in the wrong format. */
5322 goto parse_operands_return
;
5324 /* Make sure there is not a comma before the optional operand.
5325 For example the fifth operand of 'sys' is optional:
5327 sys #0,c0,c0,#0, <--- wrong
5328 sys #0,c0,c0,#0 <--- correct. */
5329 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5331 set_fatal_syntax_error
5332 (_("unexpected comma before the omitted optional operand"));
5333 goto parse_operands_return
;
5337 /* Reaching here means we are dealing with an optional operand that is
5338 omitted from the assembly line. */
5339 gas_assert (optional_operand_p (opcode
, i
));
5341 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5343 /* Try again, skipping the optional operand at backtrack_pos. */
5344 str
= backtrack_pos
;
5347 /* Clear any error record after the omitted optional operand has been
5348 successfully handled. */
5352 /* Check if we have parsed all the operands. */
5353 if (*str
!= '\0' && ! error_p ())
5355 /* Set I to the index of the last present operand; this is
5356 for the purpose of diagnostics. */
5357 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5359 set_fatal_syntax_error
5360 (_("unexpected characters following instruction"));
5363 parse_operands_return
:
5367 DEBUG_TRACE ("parsing FAIL: %s - %s",
5368 operand_mismatch_kind_names
[get_error_kind ()],
5369 get_error_message ());
5370 /* Record the operand error properly; this is useful when there
5371 are multiple instruction templates for a mnemonic name, so that
5372 later on, we can select the error that most closely describes
5374 record_operand_error (opcode
, i
, get_error_kind (),
5375 get_error_message ());
5380 DEBUG_TRACE ("parsing SUCCESS");
5385 /* It does some fix-up to provide some programmer friendly feature while
5386 keeping the libopcodes happy, i.e. libopcodes only accepts
5387 the preferred architectural syntax.
5388 Return FALSE if there is any failure; otherwise return TRUE. */
5391 programmer_friendly_fixup (aarch64_instruction
*instr
)
5393 aarch64_inst
*base
= &instr
->base
;
5394 const aarch64_opcode
*opcode
= base
->opcode
;
5395 enum aarch64_op op
= opcode
->op
;
5396 aarch64_opnd_info
*operands
= base
->operands
;
5398 DEBUG_TRACE ("enter");
5400 switch (opcode
->iclass
)
5403 /* TBNZ Xn|Wn, #uimm6, label
5404 Test and Branch Not Zero: conditionally jumps to label if bit number
5405 uimm6 in register Xn is not zero. The bit number implies the width of
5406 the register, which may be written and should be disassembled as Wn if
5407 uimm is less than 32. */
5408 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5410 if (operands
[1].imm
.value
>= 32)
5412 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5416 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5420 /* LDR Wt, label | =value
5421 As a convenience assemblers will typically permit the notation
5422 "=value" in conjunction with the pc-relative literal load instructions
5423 to automatically place an immediate value or symbolic address in a
5424 nearby literal pool and generate a hidden label which references it.
5425 ISREG has been set to 0 in the case of =value. */
5426 if (instr
->gen_lit_pool
5427 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5429 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5430 if (op
== OP_LDRSW_LIT
)
5432 if (instr
->reloc
.exp
.X_op
!= O_constant
5433 && instr
->reloc
.exp
.X_op
!= O_big
5434 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5436 record_operand_error (opcode
, 1,
5437 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5438 _("constant expression expected"));
5441 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5443 record_operand_error (opcode
, 1,
5444 AARCH64_OPDE_OTHER_ERROR
,
5445 _("literal pool insertion failed"));
5453 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5454 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5455 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5456 A programmer-friendly assembler should accept a destination Xd in
5457 place of Wd, however that is not the preferred form for disassembly.
5459 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5460 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5461 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5462 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5467 /* In the 64-bit form, the final register operand is written as Wm
5468 for all but the (possibly omitted) UXTX/LSL and SXTX
5470 As a programmer-friendly assembler, we accept e.g.
5471 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5472 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5473 int idx
= aarch64_operand_index (opcode
->operands
,
5474 AARCH64_OPND_Rm_EXT
);
5475 gas_assert (idx
== 1 || idx
== 2);
5476 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5477 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5478 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5479 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5480 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5481 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5489 DEBUG_TRACE ("exit with SUCCESS");
5493 /* Check for loads and stores that will cause unpredictable behavior. */
5496 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5498 aarch64_inst
*base
= &instr
->base
;
5499 const aarch64_opcode
*opcode
= base
->opcode
;
5500 const aarch64_opnd_info
*opnds
= base
->operands
;
5501 switch (opcode
->iclass
)
5507 /* Loading/storing the base register is unpredictable if writeback. */
5508 if ((aarch64_get_operand_class (opnds
[0].type
)
5509 == AARCH64_OPND_CLASS_INT_REG
)
5510 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5511 && opnds
[1].addr
.writeback
)
5512 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5515 case ldstnapair_offs
:
5516 case ldstpair_indexed
:
5517 /* Loading/storing the base register is unpredictable if writeback. */
5518 if ((aarch64_get_operand_class (opnds
[0].type
)
5519 == AARCH64_OPND_CLASS_INT_REG
)
5520 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5521 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5522 && opnds
[2].addr
.writeback
)
5523 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5524 /* Load operations must load different registers. */
5525 if ((opcode
->opcode
& (1 << 22))
5526 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5527 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5534 /* A wrapper function to interface with libopcodes on encoding and
5535 record the error message if there is any.
5537 Return TRUE on success; otherwise return FALSE. */
5540 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5543 aarch64_operand_error error_info
;
5544 error_info
.kind
= AARCH64_OPDE_NIL
;
5545 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5549 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5550 record_operand_error_info (opcode
, &error_info
);
5555 #ifdef DEBUG_AARCH64
5557 dump_opcode_operands (const aarch64_opcode
*opcode
)
5560 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5562 aarch64_verbose ("\t\t opnd%d: %s", i
,
5563 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5564 ? aarch64_get_operand_name (opcode
->operands
[i
])
5565 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5569 #endif /* DEBUG_AARCH64 */
5571 /* This is the guts of the machine-dependent assembler. STR points to a
5572 machine dependent instruction. This function is supposed to emit
5573 the frags/bytes it assembles to. */
5576 md_assemble (char *str
)
5579 templates
*template;
5580 aarch64_opcode
*opcode
;
5581 aarch64_inst
*inst_base
;
5582 unsigned saved_cond
;
5584 /* Align the previous label if needed. */
5585 if (last_label_seen
!= NULL
)
5587 symbol_set_frag (last_label_seen
, frag_now
);
5588 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5589 S_SET_SEGMENT (last_label_seen
, now_seg
);
5592 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5594 DEBUG_TRACE ("\n\n");
5595 DEBUG_TRACE ("==============================");
5596 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5598 template = opcode_lookup (&p
);
5601 /* It wasn't an instruction, but it might be a register alias of
5602 the form alias .req reg directive. */
5603 if (!create_register_alias (str
, p
))
5604 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5609 skip_whitespace (p
);
5612 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5613 get_mnemonic_name (str
), str
);
5617 init_operand_error_report ();
5619 saved_cond
= inst
.cond
;
5620 reset_aarch64_instruction (&inst
);
5621 inst
.cond
= saved_cond
;
5623 /* Iterate through all opcode entries with the same mnemonic name. */
5626 opcode
= template->opcode
;
5628 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5629 #ifdef DEBUG_AARCH64
5631 dump_opcode_operands (opcode
);
5632 #endif /* DEBUG_AARCH64 */
5634 mapping_state (MAP_INSN
);
5636 inst_base
= &inst
.base
;
5637 inst_base
->opcode
= opcode
;
5639 /* Truly conditionally executed instructions, e.g. b.cond. */
5640 if (opcode
->flags
& F_COND
)
5642 gas_assert (inst
.cond
!= COND_ALWAYS
);
5643 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5644 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5646 else if (inst
.cond
!= COND_ALWAYS
)
5648 /* It shouldn't arrive here, where the assembly looks like a
5649 conditional instruction but the found opcode is unconditional. */
5654 if (parse_operands (p
, opcode
)
5655 && programmer_friendly_fixup (&inst
)
5656 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5658 /* Check that this instruction is supported for this CPU. */
5659 if (!opcode
->avariant
5660 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5662 as_bad (_("selected processor does not support `%s'"), str
);
5666 warn_unpredictable_ldst (&inst
, str
);
5668 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5669 || !inst
.reloc
.need_libopcodes_p
)
5673 /* If there is relocation generated for the instruction,
5674 store the instruction information for the future fix-up. */
5675 struct aarch64_inst
*copy
;
5676 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5677 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5679 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5685 template = template->next
;
5686 if (template != NULL
)
5688 reset_aarch64_instruction (&inst
);
5689 inst
.cond
= saved_cond
;
5692 while (template != NULL
);
5694 /* Issue the error messages if any. */
5695 output_operand_error_report (str
);
5698 /* Various frobbings of labels and their addresses. */
5701 aarch64_start_line_hook (void)
5703 last_label_seen
= NULL
;
5707 aarch64_frob_label (symbolS
* sym
)
5709 last_label_seen
= sym
;
5711 dwarf2_emit_label (sym
);
5715 aarch64_data_in_code (void)
5717 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5719 *input_line_pointer
= '/';
5720 input_line_pointer
+= 5;
5721 *input_line_pointer
= 0;
5729 aarch64_canonicalize_symbol_name (char *name
)
5733 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
5734 *(name
+ len
- 5) = 0;
5739 /* Table of all register names defined by default. The user can
5740 define additional names with .req. Note that all register names
5741 should appear in both upper and lowercase variants. Some registers
5742 also have mixed-case names. */
5744 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5745 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5746 #define REGSET31(p,t) \
5747 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5748 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5749 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5750 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5751 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5752 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5753 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5754 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5755 #define REGSET(p,t) \
5756 REGSET31(p,t), REGNUM(p,31,t)
5758 /* These go into aarch64_reg_hsh hash-table. */
5759 static const reg_entry reg_names
[] = {
5760 /* Integer registers. */
5761 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
5762 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
5764 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
5765 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
5767 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
5768 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
5770 /* Coprocessor register numbers. */
5771 REGSET (c
, CN
), REGSET (C
, CN
),
5773 /* Floating-point single precision registers. */
5774 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
5776 /* Floating-point double precision registers. */
5777 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
5779 /* Floating-point half precision registers. */
5780 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
5782 /* Floating-point byte precision registers. */
5783 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
5785 /* Floating-point quad precision registers. */
5786 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
5788 /* FP/SIMD registers. */
5789 REGSET (v
, VN
), REGSET (V
, VN
),
5804 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5805 static const asm_nzcv nzcv_names
[] = {
5806 {"nzcv", B (n
, z
, c
, v
)},
5807 {"nzcV", B (n
, z
, c
, V
)},
5808 {"nzCv", B (n
, z
, C
, v
)},
5809 {"nzCV", B (n
, z
, C
, V
)},
5810 {"nZcv", B (n
, Z
, c
, v
)},
5811 {"nZcV", B (n
, Z
, c
, V
)},
5812 {"nZCv", B (n
, Z
, C
, v
)},
5813 {"nZCV", B (n
, Z
, C
, V
)},
5814 {"Nzcv", B (N
, z
, c
, v
)},
5815 {"NzcV", B (N
, z
, c
, V
)},
5816 {"NzCv", B (N
, z
, C
, v
)},
5817 {"NzCV", B (N
, z
, C
, V
)},
5818 {"NZcv", B (N
, Z
, c
, v
)},
5819 {"NZcV", B (N
, Z
, c
, V
)},
5820 {"NZCv", B (N
, Z
, C
, v
)},
5821 {"NZCV", B (N
, Z
, C
, V
)}
5834 /* MD interface: bits in the object file. */
5836 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5837 for use in the a.out file, and stores them in the array pointed to by buf.
5838 This knows about the endian-ness of the target machine and does
5839 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5840 2 (short) and 4 (long) Floating numbers are put out as a series of
5841 LITTLENUMS (shorts, here at least). */
5844 md_number_to_chars (char *buf
, valueT val
, int n
)
5846 if (target_big_endian
)
5847 number_to_chars_bigendian (buf
, val
, n
);
5849 number_to_chars_littleendian (buf
, val
, n
);
5852 /* MD interface: Sections. */
5854 /* Estimate the size of a frag before relaxing. Assume everything fits in
5858 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
5864 /* Round up a section size to the appropriate boundary. */
5867 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5872 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5873 of an rs_align_code fragment.
5875 Here we fill the frag with the appropriate info for padding the
5876 output stream. The resulting frag will consist of a fixed (fr_fix)
5877 and of a repeating (fr_var) part.
5879 The fixed content is always emitted before the repeating content and
5880 these two parts are used as follows in constructing the output:
5881 - the fixed part will be used to align to a valid instruction word
5882 boundary, in case that we start at a misaligned address; as no
5883 executable instruction can live at the misaligned location, we
5884 simply fill with zeros;
5885 - the variable part will be used to cover the remaining padding and
5886 we fill using the AArch64 NOP instruction.
5888 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
5889 enough storage space for up to 3 bytes for padding the back to a valid
5890 instruction alignment and exactly 4 bytes to store the NOP pattern. */
5893 aarch64_handle_align (fragS
* fragP
)
5895 /* NOP = d503201f */
5896 /* AArch64 instructions are always little-endian. */
5897 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5899 int bytes
, fix
, noop_size
;
5902 if (fragP
->fr_type
!= rs_align_code
)
5905 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5906 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
5909 gas_assert (fragP
->tc_frag_data
.recorded
);
5912 noop_size
= sizeof (aarch64_noop
);
5914 fix
= bytes
& (noop_size
- 1);
5918 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
5922 fragP
->fr_fix
+= fix
;
5926 memcpy (p
, aarch64_noop
, noop_size
);
5927 fragP
->fr_var
= noop_size
;
5930 /* Perform target specific initialisation of a frag.
5931 Note - despite the name this initialisation is not done when the frag
5932 is created, but only when its type is assigned. A frag can be created
5933 and used a long time before its type is set, so beware of assuming that
5934 this initialisationis performed first. */
5938 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
5939 int max_chars ATTRIBUTE_UNUSED
)
5943 #else /* OBJ_ELF is defined. */
5945 aarch64_init_frag (fragS
* fragP
, int max_chars
)
5947 /* Record a mapping symbol for alignment frags. We will delete this
5948 later if the alignment ends up empty. */
5949 if (!fragP
->tc_frag_data
.recorded
)
5951 fragP
->tc_frag_data
.recorded
= 1;
5952 switch (fragP
->fr_type
)
5957 mapping_state_2 (MAP_DATA
, max_chars
);
5960 mapping_state_2 (MAP_INSN
, max_chars
);
5968 /* Initialize the DWARF-2 unwind information for this procedure. */
5971 tc_aarch64_frame_initial_instructions (void)
5973 cfi_add_CFA_def_cfa (REG_SP
, 0);
5975 #endif /* OBJ_ELF */
5977 /* Convert REGNAME to a DWARF-2 register number. */
5980 tc_aarch64_regname_to_dw2regnum (char *regname
)
5982 const reg_entry
*reg
= parse_reg (®name
);
5988 case REG_TYPE_SP_32
:
5989 case REG_TYPE_SP_64
:
5999 return reg
->number
+ 64;
6007 /* Implement DWARF2_ADDR_SIZE. */
6010 aarch64_dwarf2_addr_size (void)
6012 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6016 return bfd_arch_bits_per_address (stdoutput
) / 8;
6019 /* MD interface: Symbol and relocation handling. */
6021 /* Return the address within the segment that a PC-relative fixup is
6022 relative to. For AArch64 PC-relative fixups applied to instructions
6023 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6026 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6028 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6030 /* If this is pc-relative and we are going to emit a relocation
6031 then we just want to put out any pipeline compensation that the linker
6032 will need. Otherwise we want to use the calculated base. */
6034 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6035 || aarch64_force_relocation (fixP
)))
6038 /* AArch64 should be consistent for all pc-relative relocations. */
6039 return base
+ AARCH64_PCREL_OFFSET
;
6042 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6043 Otherwise we have no need to default values of symbols. */
6046 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6049 if (name
[0] == '_' && name
[1] == 'G'
6050 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6054 if (symbol_find (name
))
6055 as_bad (_("GOT already in the symbol table"));
6057 GOT_symbol
= symbol_new (name
, undefined_section
,
6058 (valueT
) 0, &zero_address_frag
);
6068 /* Return non-zero if the indicated VALUE has overflowed the maximum
6069 range expressible by a unsigned number with the indicated number of
6073 unsigned_overflow (valueT value
, unsigned bits
)
6076 if (bits
>= sizeof (valueT
) * 8)
6078 lim
= (valueT
) 1 << bits
;
6079 return (value
>= lim
);
6083 /* Return non-zero if the indicated VALUE has overflowed the maximum
6084 range expressible by an signed number with the indicated number of
6088 signed_overflow (offsetT value
, unsigned bits
)
6091 if (bits
>= sizeof (offsetT
) * 8)
6093 lim
= (offsetT
) 1 << (bits
- 1);
6094 return (value
< -lim
|| value
>= lim
);
6097 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6098 unsigned immediate offset load/store instruction, try to encode it as
6099 an unscaled, 9-bit, signed immediate offset load/store instruction.
6100 Return TRUE if it is successful; otherwise return FALSE.
6102 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6103 in response to the standard LDR/STR mnemonics when the immediate offset is
6104 unambiguous, i.e. when it is negative or unaligned. */
6107 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6110 enum aarch64_op new_op
;
6111 const aarch64_opcode
*new_opcode
;
6113 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6115 switch (instr
->opcode
->op
)
6117 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6118 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6119 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6120 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6121 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6122 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6123 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6124 case OP_STR_POS
: new_op
= OP_STUR
; break;
6125 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6126 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6127 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6128 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6129 default: new_op
= OP_NIL
; break;
6132 if (new_op
== OP_NIL
)
6135 new_opcode
= aarch64_get_opcode (new_op
);
6136 gas_assert (new_opcode
!= NULL
);
6138 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6139 instr
->opcode
->op
, new_opcode
->op
);
6141 aarch64_replace_opcode (instr
, new_opcode
);
6143 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6144 qualifier matching may fail because the out-of-date qualifier will
6145 prevent the operand being updated with a new and correct qualifier. */
6146 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6147 AARCH64_OPND_ADDR_SIMM9
);
6148 gas_assert (idx
== 1);
6149 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6151 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6153 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6159 /* Called by fix_insn to fix a MOV immediate alias instruction.
6161 Operand for a generic move immediate instruction, which is an alias
6162 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6163 a 32-bit/64-bit immediate value into general register. An assembler error
6164 shall result if the immediate cannot be created by a single one of these
6165 instructions. If there is a choice, then to ensure reversability an
6166 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6169 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6171 const aarch64_opcode
*opcode
;
6173 /* Need to check if the destination is SP/ZR. The check has to be done
6174 before any aarch64_replace_opcode. */
6175 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6176 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6178 instr
->operands
[1].imm
.value
= value
;
6179 instr
->operands
[1].skip
= 0;
6183 /* Try the MOVZ alias. */
6184 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6185 aarch64_replace_opcode (instr
, opcode
);
6186 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6187 &instr
->value
, NULL
, NULL
))
6189 put_aarch64_insn (buf
, instr
->value
);
6192 /* Try the MOVK alias. */
6193 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6194 aarch64_replace_opcode (instr
, opcode
);
6195 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6196 &instr
->value
, NULL
, NULL
))
6198 put_aarch64_insn (buf
, instr
->value
);
6203 if (try_mov_bitmask_p
)
6205 /* Try the ORR alias. */
6206 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6207 aarch64_replace_opcode (instr
, opcode
);
6208 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6209 &instr
->value
, NULL
, NULL
))
6211 put_aarch64_insn (buf
, instr
->value
);
6216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6217 _("immediate cannot be moved by a single instruction"));
6220 /* An instruction operand which is immediate related may have symbol used
6221 in the assembly, e.g.
6224 .set u32, 0x00ffff00
6226 At the time when the assembly instruction is parsed, a referenced symbol,
6227 like 'u32' in the above example may not have been seen; a fixS is created
6228 in such a case and is handled here after symbols have been resolved.
6229 Instruction is fixed up with VALUE using the information in *FIXP plus
6230 extra information in FLAGS.
6232 This function is called by md_apply_fix to fix up instructions that need
6233 a fix-up described above but does not involve any linker-time relocation. */
6236 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6240 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6241 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6242 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6246 /* Now the instruction is about to be fixed-up, so the operand that
6247 was previously marked as 'ignored' needs to be unmarked in order
6248 to get the encoding done properly. */
6249 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6250 new_inst
->operands
[idx
].skip
= 0;
6253 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6257 case AARCH64_OPND_EXCEPTION
:
6258 if (unsigned_overflow (value
, 16))
6259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6260 _("immediate out of range"));
6261 insn
= get_aarch64_insn (buf
);
6262 insn
|= encode_svc_imm (value
);
6263 put_aarch64_insn (buf
, insn
);
6266 case AARCH64_OPND_AIMM
:
6267 /* ADD or SUB with immediate.
6268 NOTE this assumes we come here with a add/sub shifted reg encoding
6269 3 322|2222|2 2 2 21111 111111
6270 1 098|7654|3 2 1 09876 543210 98765 43210
6271 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6272 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6273 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6274 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6276 3 322|2222|2 2 221111111111
6277 1 098|7654|3 2 109876543210 98765 43210
6278 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6279 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6280 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6281 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6282 Fields sf Rn Rd are already set. */
6283 insn
= get_aarch64_insn (buf
);
6287 insn
= reencode_addsub_switch_add_sub (insn
);
6291 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6292 && unsigned_overflow (value
, 12))
6294 /* Try to shift the value by 12 to make it fit. */
6295 if (((value
>> 12) << 12) == value
6296 && ! unsigned_overflow (value
, 12 + 12))
6299 insn
|= encode_addsub_imm_shift_amount (1);
6303 if (unsigned_overflow (value
, 12))
6304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6305 _("immediate out of range"));
6307 insn
|= encode_addsub_imm (value
);
6309 put_aarch64_insn (buf
, insn
);
6312 case AARCH64_OPND_SIMD_IMM
:
6313 case AARCH64_OPND_SIMD_IMM_SFT
:
6314 case AARCH64_OPND_LIMM
:
6315 /* Bit mask immediate. */
6316 gas_assert (new_inst
!= NULL
);
6317 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6318 new_inst
->operands
[idx
].imm
.value
= value
;
6319 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6320 &new_inst
->value
, NULL
, NULL
))
6321 put_aarch64_insn (buf
, new_inst
->value
);
6323 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6324 _("invalid immediate"));
6327 case AARCH64_OPND_HALF
:
6328 /* 16-bit unsigned immediate. */
6329 if (unsigned_overflow (value
, 16))
6330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6331 _("immediate out of range"));
6332 insn
= get_aarch64_insn (buf
);
6333 insn
|= encode_movw_imm (value
& 0xffff);
6334 put_aarch64_insn (buf
, insn
);
6337 case AARCH64_OPND_IMM_MOV
:
6338 /* Operand for a generic move immediate instruction, which is
6339 an alias instruction that generates a single MOVZ, MOVN or ORR
6340 instruction to loads a 32-bit/64-bit immediate value into general
6341 register. An assembler error shall result if the immediate cannot be
6342 created by a single one of these instructions. If there is a choice,
6343 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6344 and MOVZ or MOVN to ORR. */
6345 gas_assert (new_inst
!= NULL
);
6346 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6349 case AARCH64_OPND_ADDR_SIMM7
:
6350 case AARCH64_OPND_ADDR_SIMM9
:
6351 case AARCH64_OPND_ADDR_SIMM9_2
:
6352 case AARCH64_OPND_ADDR_UIMM12
:
6353 /* Immediate offset in an address. */
6354 insn
= get_aarch64_insn (buf
);
6356 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6357 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6358 || new_inst
->opcode
->operands
[2] == opnd
);
6360 /* Get the index of the address operand. */
6361 if (new_inst
->opcode
->operands
[1] == opnd
)
6362 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6365 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6368 /* Update the resolved offset value. */
6369 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6371 /* Encode/fix-up. */
6372 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6373 &new_inst
->value
, NULL
, NULL
))
6375 put_aarch64_insn (buf
, new_inst
->value
);
6378 else if (new_inst
->opcode
->iclass
== ldst_pos
6379 && try_to_encode_as_unscaled_ldst (new_inst
))
6381 put_aarch64_insn (buf
, new_inst
->value
);
6385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6386 _("immediate offset out of range"));
6391 as_fatal (_("unhandled operand code %d"), opnd
);
6395 /* Apply a fixup (fixP) to segment data, once it has been determined
6396 by our caller that we have all the info we need to fix it up.
6398 Parameter valP is the pointer to the value of the bits. */
6401 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6403 offsetT value
= *valP
;
6405 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6407 unsigned flags
= fixP
->fx_addnumber
;
6409 DEBUG_TRACE ("\n\n");
6410 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6411 DEBUG_TRACE ("Enter md_apply_fix");
6413 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6415 /* Note whether this will delete the relocation. */
6417 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6420 /* Process the relocations. */
6421 switch (fixP
->fx_r_type
)
6423 case BFD_RELOC_NONE
:
6424 /* This will need to go in the object file. */
6429 case BFD_RELOC_8_PCREL
:
6430 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6431 md_number_to_chars (buf
, value
, 1);
6435 case BFD_RELOC_16_PCREL
:
6436 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6437 md_number_to_chars (buf
, value
, 2);
6441 case BFD_RELOC_32_PCREL
:
6442 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6443 md_number_to_chars (buf
, value
, 4);
6447 case BFD_RELOC_64_PCREL
:
6448 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6449 md_number_to_chars (buf
, value
, 8);
6452 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6453 /* We claim that these fixups have been processed here, even if
6454 in fact we generate an error because we do not have a reloc
6455 for them, so tc_gen_reloc() will reject them. */
6457 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6460 _("undefined symbol %s used as an immediate value"),
6461 S_GET_NAME (fixP
->fx_addsy
));
6462 goto apply_fix_return
;
6464 fix_insn (fixP
, flags
, value
);
6467 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6468 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6472 _("pc-relative load offset not word aligned"));
6473 if (signed_overflow (value
, 21))
6474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6475 _("pc-relative load offset out of range"));
6476 insn
= get_aarch64_insn (buf
);
6477 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6478 put_aarch64_insn (buf
, insn
);
6482 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6483 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6485 if (signed_overflow (value
, 21))
6486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6487 _("pc-relative address offset out of range"));
6488 insn
= get_aarch64_insn (buf
);
6489 insn
|= encode_adr_imm (value
);
6490 put_aarch64_insn (buf
, insn
);
6494 case BFD_RELOC_AARCH64_BRANCH19
:
6495 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6499 _("conditional branch target not word aligned"));
6500 if (signed_overflow (value
, 21))
6501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6502 _("conditional branch out of range"));
6503 insn
= get_aarch64_insn (buf
);
6504 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6505 put_aarch64_insn (buf
, insn
);
6509 case BFD_RELOC_AARCH64_TSTBR14
:
6510 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6514 _("conditional branch target not word aligned"));
6515 if (signed_overflow (value
, 16))
6516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6517 _("conditional branch out of range"));
6518 insn
= get_aarch64_insn (buf
);
6519 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6520 put_aarch64_insn (buf
, insn
);
6524 case BFD_RELOC_AARCH64_JUMP26
:
6525 case BFD_RELOC_AARCH64_CALL26
:
6526 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6530 _("branch target not word aligned"));
6531 if (signed_overflow (value
, 28))
6532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6533 _("branch out of range"));
6534 insn
= get_aarch64_insn (buf
);
6535 insn
|= encode_branch_ofs_26 (value
>> 2);
6536 put_aarch64_insn (buf
, insn
);
6540 case BFD_RELOC_AARCH64_MOVW_G0
:
6541 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6542 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6545 case BFD_RELOC_AARCH64_MOVW_G1
:
6546 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6547 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6550 case BFD_RELOC_AARCH64_MOVW_G2
:
6551 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6552 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6555 case BFD_RELOC_AARCH64_MOVW_G3
:
6558 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6560 insn
= get_aarch64_insn (buf
);
6564 /* REL signed addend must fit in 16 bits */
6565 if (signed_overflow (value
, 16))
6566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6567 _("offset out of range"));
6571 /* Check for overflow and scale. */
6572 switch (fixP
->fx_r_type
)
6574 case BFD_RELOC_AARCH64_MOVW_G0
:
6575 case BFD_RELOC_AARCH64_MOVW_G1
:
6576 case BFD_RELOC_AARCH64_MOVW_G2
:
6577 case BFD_RELOC_AARCH64_MOVW_G3
:
6578 if (unsigned_overflow (value
, scale
+ 16))
6579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6580 _("unsigned value out of range"));
6582 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6583 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6584 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6585 /* NOTE: We can only come here with movz or movn. */
6586 if (signed_overflow (value
, scale
+ 16))
6587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6588 _("signed value out of range"));
6591 /* Force use of MOVN. */
6593 insn
= reencode_movzn_to_movn (insn
);
6597 /* Force use of MOVZ. */
6598 insn
= reencode_movzn_to_movz (insn
);
6602 /* Unchecked relocations. */
6608 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6609 insn
|= encode_movw_imm (value
& 0xffff);
6611 put_aarch64_insn (buf
, insn
);
6615 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6616 fixP
->fx_r_type
= (ilp32_p
6617 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6618 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
6619 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6620 /* Should always be exported to object file, see
6621 aarch64_force_relocation(). */
6622 gas_assert (!fixP
->fx_done
);
6623 gas_assert (seg
->use_rela_p
);
6626 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6627 fixP
->fx_r_type
= (ilp32_p
6628 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6629 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
6630 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6631 /* Should always be exported to object file, see
6632 aarch64_force_relocation(). */
6633 gas_assert (!fixP
->fx_done
);
6634 gas_assert (seg
->use_rela_p
);
6637 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6638 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6639 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6640 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6641 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6642 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6643 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6644 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6645 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6646 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6647 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6648 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6649 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6650 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6651 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6652 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6653 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6654 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6655 /* Should always be exported to object file, see
6656 aarch64_force_relocation(). */
6657 gas_assert (!fixP
->fx_done
);
6658 gas_assert (seg
->use_rela_p
);
6661 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6662 /* Should always be exported to object file, see
6663 aarch64_force_relocation(). */
6664 fixP
->fx_r_type
= (ilp32_p
6665 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6666 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
6667 gas_assert (!fixP
->fx_done
);
6668 gas_assert (seg
->use_rela_p
);
6671 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6672 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6673 case BFD_RELOC_AARCH64_ADD_LO12
:
6674 case BFD_RELOC_AARCH64_LDST8_LO12
:
6675 case BFD_RELOC_AARCH64_LDST16_LO12
:
6676 case BFD_RELOC_AARCH64_LDST32_LO12
:
6677 case BFD_RELOC_AARCH64_LDST64_LO12
:
6678 case BFD_RELOC_AARCH64_LDST128_LO12
:
6679 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6680 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6681 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6682 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6683 /* Should always be exported to object file, see
6684 aarch64_force_relocation(). */
6685 gas_assert (!fixP
->fx_done
);
6686 gas_assert (seg
->use_rela_p
);
6689 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6690 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6691 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6694 case BFD_RELOC_UNUSED
:
6695 /* An error will already have been reported. */
6699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6700 _("unexpected %s fixup"),
6701 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6706 /* Free the allocated the struct aarch64_inst.
6707 N.B. currently there are very limited number of fix-up types actually use
6708 this field, so the impact on the performance should be minimal . */
6709 if (fixP
->tc_fix_data
.inst
!= NULL
)
6710 free (fixP
->tc_fix_data
.inst
);
6715 /* Translate internal representation of relocation info to BFD target
6719 tc_gen_reloc (asection
* section
, fixS
* fixp
)
6722 bfd_reloc_code_real_type code
;
6724 reloc
= xmalloc (sizeof (arelent
));
6726 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
6727 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6728 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6732 if (section
->use_rela_p
)
6733 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
6735 fixp
->fx_offset
= reloc
->address
;
6737 reloc
->addend
= fixp
->fx_offset
;
6739 code
= fixp
->fx_r_type
;
6744 code
= BFD_RELOC_16_PCREL
;
6749 code
= BFD_RELOC_32_PCREL
;
6754 code
= BFD_RELOC_64_PCREL
;
6761 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6762 if (reloc
->howto
== NULL
)
6764 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6766 ("cannot represent %s relocation in this object file format"),
6767 bfd_get_reloc_code_name (code
));
6774 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6777 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
6779 bfd_reloc_code_real_type type
;
6783 FIXME: @@ Should look at CPU word size. */
6790 type
= BFD_RELOC_16
;
6793 type
= BFD_RELOC_32
;
6796 type
= BFD_RELOC_64
;
6799 as_bad (_("cannot do %u-byte relocation"), size
);
6800 type
= BFD_RELOC_UNUSED
;
6804 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6808 aarch64_force_relocation (struct fix
*fixp
)
6810 switch (fixp
->fx_r_type
)
6812 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6813 /* Perform these "immediate" internal relocations
6814 even if the symbol is extern or weak. */
6817 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6818 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6819 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6820 /* Pseudo relocs that need to be fixed up according to
6824 case BFD_RELOC_AARCH64_ADD_LO12
:
6825 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6826 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6827 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6828 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6829 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6830 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6831 case BFD_RELOC_AARCH64_LDST128_LO12
:
6832 case BFD_RELOC_AARCH64_LDST16_LO12
:
6833 case BFD_RELOC_AARCH64_LDST32_LO12
:
6834 case BFD_RELOC_AARCH64_LDST64_LO12
:
6835 case BFD_RELOC_AARCH64_LDST8_LO12
:
6836 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6837 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6838 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6839 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6840 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6841 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6842 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6843 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6844 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6845 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6846 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6847 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6848 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6849 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6850 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6851 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6852 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6853 /* Always leave these relocations for the linker. */
6860 return generic_force_reloc (fixp
);
6866 elf64_aarch64_target_format (void)
6868 if (target_big_endian
)
6869 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
6871 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
6875 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
6877 elf_frob_symbol (symp
, puntp
);
6881 /* MD interface: Finalization. */
6883 /* A good place to do this, although this was probably not intended
6884 for this kind of use. We need to dump the literal pool before
6885 references are made to a null symbol pointer. */
6888 aarch64_cleanup (void)
6892 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
6894 /* Put it at the end of the relevant section. */
6895 subseg_set (pool
->section
, pool
->sub_section
);
6901 /* Remove any excess mapping symbols generated for alignment frags in
6902 SEC. We may have created a mapping symbol before a zero byte
6903 alignment; remove it if there's a mapping symbol after the
6906 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
6907 void *dummy ATTRIBUTE_UNUSED
)
6909 segment_info_type
*seginfo
= seg_info (sec
);
6912 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
6915 for (fragp
= seginfo
->frchainP
->frch_root
;
6916 fragp
!= NULL
; fragp
= fragp
->fr_next
)
6918 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
6919 fragS
*next
= fragp
->fr_next
;
6921 /* Variable-sized frags have been converted to fixed size by
6922 this point. But if this was variable-sized to start with,
6923 there will be a fixed-size frag after it. So don't handle
6925 if (sym
== NULL
|| next
== NULL
)
6928 if (S_GET_VALUE (sym
) < next
->fr_address
)
6929 /* Not at the end of this frag. */
6931 know (S_GET_VALUE (sym
) == next
->fr_address
);
6935 if (next
->tc_frag_data
.first_map
!= NULL
)
6937 /* Next frag starts with a mapping symbol. Discard this
6939 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
6943 if (next
->fr_next
== NULL
)
6945 /* This mapping symbol is at the end of the section. Discard
6947 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
6948 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
6952 /* As long as we have empty frags without any mapping symbols,
6954 /* If the next frag is non-empty and does not start with a
6955 mapping symbol, then this mapping symbol is required. */
6956 if (next
->fr_address
!= next
->fr_next
->fr_address
)
6959 next
= next
->fr_next
;
6961 while (next
!= NULL
);
6966 /* Adjust the symbol table. */
6969 aarch64_adjust_symtab (void)
6972 /* Remove any overlapping mapping symbols generated by alignment frags. */
6973 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
6974 /* Now do generic ELF adjustments. */
6975 elf_adjust_symtab ();
6980 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
6982 const char *hash_err
;
6984 hash_err
= hash_insert (table
, key
, value
);
6986 printf ("Internal Error: Can't hash %s\n", key
);
6990 fill_instruction_hash_table (void)
6992 aarch64_opcode
*opcode
= aarch64_opcode_table
;
6994 while (opcode
->name
!= NULL
)
6996 templates
*templ
, *new_templ
;
6997 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
6999 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7000 new_templ
->opcode
= opcode
;
7001 new_templ
->next
= NULL
;
7004 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7007 new_templ
->next
= templ
->next
;
7008 templ
->next
= new_templ
;
7015 convert_to_upper (char *dst
, const char *src
, size_t num
)
7018 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7019 *dst
= TOUPPER (*src
);
7023 /* Assume STR point to a lower-case string, allocate, convert and return
7024 the corresponding upper-case string. */
7025 static inline const char*
7026 get_upper_str (const char *str
)
7029 size_t len
= strlen (str
);
7030 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7032 convert_to_upper (ret
, str
, len
);
7036 /* MD interface: Initialization. */
7044 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7045 || (aarch64_cond_hsh
= hash_new ()) == NULL
7046 || (aarch64_shift_hsh
= hash_new ()) == NULL
7047 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7048 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7049 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7050 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7051 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7052 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7053 || (aarch64_reg_hsh
= hash_new ()) == NULL
7054 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7055 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7056 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
7057 as_fatal (_("virtual memory exhausted"));
7059 fill_instruction_hash_table ();
7061 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7062 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7063 (void *) (aarch64_sys_regs
+ i
));
7065 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7066 checked_hash_insert (aarch64_pstatefield_hsh
,
7067 aarch64_pstatefields
[i
].name
,
7068 (void *) (aarch64_pstatefields
+ i
));
7070 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
7071 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7072 aarch64_sys_regs_ic
[i
].template,
7073 (void *) (aarch64_sys_regs_ic
+ i
));
7075 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
7076 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7077 aarch64_sys_regs_dc
[i
].template,
7078 (void *) (aarch64_sys_regs_dc
+ i
));
7080 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
7081 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7082 aarch64_sys_regs_at
[i
].template,
7083 (void *) (aarch64_sys_regs_at
+ i
));
7085 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
7086 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7087 aarch64_sys_regs_tlbi
[i
].template,
7088 (void *) (aarch64_sys_regs_tlbi
+ i
));
7090 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7091 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7092 (void *) (reg_names
+ i
));
7094 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7095 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7096 (void *) (nzcv_names
+ i
));
7098 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7100 const char *name
= aarch64_operand_modifiers
[i
].name
;
7101 checked_hash_insert (aarch64_shift_hsh
, name
,
7102 (void *) (aarch64_operand_modifiers
+ i
));
7103 /* Also hash the name in the upper case. */
7104 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7105 (void *) (aarch64_operand_modifiers
+ i
));
7108 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7111 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7112 the same condition code. */
7113 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7115 const char *name
= aarch64_conds
[i
].names
[j
];
7118 checked_hash_insert (aarch64_cond_hsh
, name
,
7119 (void *) (aarch64_conds
+ i
));
7120 /* Also hash the name in the upper case. */
7121 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7122 (void *) (aarch64_conds
+ i
));
7126 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7128 const char *name
= aarch64_barrier_options
[i
].name
;
7129 /* Skip xx00 - the unallocated values of option. */
7132 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7133 (void *) (aarch64_barrier_options
+ i
));
7134 /* Also hash the name in the upper case. */
7135 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7136 (void *) (aarch64_barrier_options
+ i
));
7139 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7141 const char* name
= aarch64_prfops
[i
].name
;
7142 /* Skip the unallocated hint encodings. */
7145 checked_hash_insert (aarch64_pldop_hsh
, name
,
7146 (void *) (aarch64_prfops
+ i
));
7147 /* Also hash the name in the upper case. */
7148 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7149 (void *) (aarch64_prfops
+ i
));
7152 /* Set the cpu variant based on the command-line options. */
7154 mcpu_cpu_opt
= march_cpu_opt
;
7157 mcpu_cpu_opt
= &cpu_default
;
7159 cpu_variant
= *mcpu_cpu_opt
;
7161 /* Record the CPU type. */
7162 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7164 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7167 /* Command line processing. */
7169 const char *md_shortopts
= "m:";
7171 #ifdef AARCH64_BI_ENDIAN
7172 #define OPTION_EB (OPTION_MD_BASE + 0)
7173 #define OPTION_EL (OPTION_MD_BASE + 1)
7175 #if TARGET_BYTES_BIG_ENDIAN
7176 #define OPTION_EB (OPTION_MD_BASE + 0)
7178 #define OPTION_EL (OPTION_MD_BASE + 1)
7182 struct option md_longopts
[] = {
7184 {"EB", no_argument
, NULL
, OPTION_EB
},
7187 {"EL", no_argument
, NULL
, OPTION_EL
},
7189 {NULL
, no_argument
, NULL
, 0}
7192 size_t md_longopts_size
= sizeof (md_longopts
);
7194 struct aarch64_option_table
7196 char *option
; /* Option name to match. */
7197 char *help
; /* Help information. */
7198 int *var
; /* Variable to change. */
7199 int value
; /* What to change it to. */
7200 char *deprecated
; /* If non-null, print this message. */
7203 static struct aarch64_option_table aarch64_opts
[] = {
7204 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7205 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7207 #ifdef DEBUG_AARCH64
7208 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7209 #endif /* DEBUG_AARCH64 */
7210 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7212 {"mno-verbose-error", N_("do not output verbose error messages"),
7213 &verbose_error_p
, 0, NULL
},
7214 {NULL
, NULL
, NULL
, 0, NULL
}
7217 struct aarch64_cpu_option_table
7220 const aarch64_feature_set value
;
7221 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7223 const char *canonical_name
;
7226 /* This list should, at a minimum, contain all the cpu names
7227 recognized by GCC. */
7228 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7229 {"all", AARCH64_ANY
, NULL
},
7230 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7231 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7232 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7233 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7234 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7235 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7236 {"thunderx", AARCH64_ARCH_V8
, "Cavium ThunderX"},
7237 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7238 in earlier releases and is superseded by 'xgene1' in all
7240 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7241 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7242 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7243 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7244 {"generic", AARCH64_ARCH_V8
, NULL
},
7246 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7249 struct aarch64_arch_option_table
7252 const aarch64_feature_set value
;
7255 /* This list should, at a minimum, contain all the architecture names
7256 recognized by GCC. */
7257 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7258 {"all", AARCH64_ANY
},
7259 {"armv8-a", AARCH64_ARCH_V8
},
7260 {NULL
, AARCH64_ARCH_NONE
}
7263 /* ISA extensions. */
7264 struct aarch64_option_cpu_value_table
7267 const aarch64_feature_set value
;
7270 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7271 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7272 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7273 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7274 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7275 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7276 {NULL
, AARCH64_ARCH_NONE
}
7279 struct aarch64_long_option_table
7281 char *option
; /* Substring to match. */
7282 char *help
; /* Help information. */
7283 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7284 char *deprecated
; /* If non-null, print this message. */
7288 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7289 bfd_boolean ext_only
)
7291 /* We insist on extensions being added before being removed. We achieve
7292 this by using the ADDING_VALUE variable to indicate whether we are
7293 adding an extension (1) or removing it (0) and only allowing it to
7294 change in the order -1 -> 1 -> 0. */
7295 int adding_value
= -1;
7296 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7298 /* Copy the feature set, so that we can modify it. */
7302 while (str
!= NULL
&& *str
!= 0)
7304 const struct aarch64_option_cpu_value_table
*opt
;
7312 as_bad (_("invalid architectural extension"));
7316 ext
= strchr (++str
, '+');
7322 optlen
= strlen (str
);
7324 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7326 if (adding_value
!= 0)
7331 else if (optlen
> 0)
7333 if (adding_value
== -1)
7335 else if (adding_value
!= 1)
7337 as_bad (_("must specify extensions to add before specifying "
7338 "those to remove"));
7345 as_bad (_("missing architectural extension"));
7349 gas_assert (adding_value
!= -1);
7351 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7352 if (strncmp (opt
->name
, str
, optlen
) == 0)
7354 /* Add or remove the extension. */
7356 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7358 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7362 if (opt
->name
== NULL
)
7364 as_bad (_("unknown architectural extension `%s'"), str
);
7375 aarch64_parse_cpu (char *str
)
7377 const struct aarch64_cpu_option_table
*opt
;
7378 char *ext
= strchr (str
, '+');
7384 optlen
= strlen (str
);
7388 as_bad (_("missing cpu name `%s'"), str
);
7392 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7393 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7395 mcpu_cpu_opt
= &opt
->value
;
7397 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7402 as_bad (_("unknown cpu `%s'"), str
);
7407 aarch64_parse_arch (char *str
)
7409 const struct aarch64_arch_option_table
*opt
;
7410 char *ext
= strchr (str
, '+');
7416 optlen
= strlen (str
);
7420 as_bad (_("missing architecture name `%s'"), str
);
7424 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7425 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7427 march_cpu_opt
= &opt
->value
;
7429 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7434 as_bad (_("unknown architecture `%s'\n"), str
);
7439 struct aarch64_option_abi_value_table
7442 enum aarch64_abi_type value
;
7445 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7446 {"ilp32", AARCH64_ABI_ILP32
},
7447 {"lp64", AARCH64_ABI_LP64
},
7452 aarch64_parse_abi (char *str
)
7454 const struct aarch64_option_abi_value_table
*opt
;
7455 size_t optlen
= strlen (str
);
7459 as_bad (_("missing abi name `%s'"), str
);
7463 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
7464 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7466 aarch64_abi
= opt
->value
;
7470 as_bad (_("unknown abi `%s'\n"), str
);
7474 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7476 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7477 aarch64_parse_abi
, NULL
},
7478 #endif /* OBJ_ELF */
7479 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7480 aarch64_parse_cpu
, NULL
},
7481 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7482 aarch64_parse_arch
, NULL
},
7483 {NULL
, NULL
, 0, NULL
}
7487 md_parse_option (int c
, char *arg
)
7489 struct aarch64_option_table
*opt
;
7490 struct aarch64_long_option_table
*lopt
;
7496 target_big_endian
= 1;
7502 target_big_endian
= 0;
7507 /* Listing option. Just ignore these, we don't support additional
7512 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7514 if (c
== opt
->option
[0]
7515 && ((arg
== NULL
&& opt
->option
[1] == 0)
7516 || streq (arg
, opt
->option
+ 1)))
7518 /* If the option is deprecated, tell the user. */
7519 if (opt
->deprecated
!= NULL
)
7520 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7521 arg
? arg
: "", _(opt
->deprecated
));
7523 if (opt
->var
!= NULL
)
7524 *opt
->var
= opt
->value
;
7530 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7532 /* These options are expected to have an argument. */
7533 if (c
== lopt
->option
[0]
7535 && strncmp (arg
, lopt
->option
+ 1,
7536 strlen (lopt
->option
+ 1)) == 0)
7538 /* If the option is deprecated, tell the user. */
7539 if (lopt
->deprecated
!= NULL
)
7540 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7541 _(lopt
->deprecated
));
7543 /* Call the sup-option parser. */
7544 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7555 md_show_usage (FILE * fp
)
7557 struct aarch64_option_table
*opt
;
7558 struct aarch64_long_option_table
*lopt
;
7560 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7562 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7563 if (opt
->help
!= NULL
)
7564 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7566 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7567 if (lopt
->help
!= NULL
)
7568 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7572 -EB assemble code for a big-endian cpu\n"));
7577 -EL assemble code for a little-endian cpu\n"));
7581 /* Parse a .cpu directive. */
7584 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7586 const struct aarch64_cpu_option_table
*opt
;
7592 name
= input_line_pointer
;
7593 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7594 input_line_pointer
++;
7595 saved_char
= *input_line_pointer
;
7596 *input_line_pointer
= 0;
7598 ext
= strchr (name
, '+');
7601 optlen
= ext
- name
;
7603 optlen
= strlen (name
);
7605 /* Skip the first "all" entry. */
7606 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7607 if (strlen (opt
->name
) == optlen
7608 && strncmp (name
, opt
->name
, optlen
) == 0)
7610 mcpu_cpu_opt
= &opt
->value
;
7612 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7615 cpu_variant
= *mcpu_cpu_opt
;
7617 *input_line_pointer
= saved_char
;
7618 demand_empty_rest_of_line ();
7621 as_bad (_("unknown cpu `%s'"), name
);
7622 *input_line_pointer
= saved_char
;
7623 ignore_rest_of_line ();
7627 /* Parse a .arch directive. */
7630 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7632 const struct aarch64_arch_option_table
*opt
;
7638 name
= input_line_pointer
;
7639 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7640 input_line_pointer
++;
7641 saved_char
= *input_line_pointer
;
7642 *input_line_pointer
= 0;
7644 ext
= strchr (name
, '+');
7647 optlen
= ext
- name
;
7649 optlen
= strlen (name
);
7651 /* Skip the first "all" entry. */
7652 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7653 if (strlen (opt
->name
) == optlen
7654 && strncmp (name
, opt
->name
, optlen
) == 0)
7656 mcpu_cpu_opt
= &opt
->value
;
7658 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7661 cpu_variant
= *mcpu_cpu_opt
;
7663 *input_line_pointer
= saved_char
;
7664 demand_empty_rest_of_line ();
7668 as_bad (_("unknown architecture `%s'\n"), name
);
7669 *input_line_pointer
= saved_char
;
7670 ignore_rest_of_line ();
7673 /* Parse a .arch_extension directive. */
7676 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
7679 char *ext
= input_line_pointer
;;
7681 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7682 input_line_pointer
++;
7683 saved_char
= *input_line_pointer
;
7684 *input_line_pointer
= 0;
7686 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
7689 cpu_variant
= *mcpu_cpu_opt
;
7691 *input_line_pointer
= saved_char
;
7692 demand_empty_rest_of_line ();
7695 /* Copy symbol information. */
7698 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
7700 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);