1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
33 /* Defines section. */
35 #define MAX_INSN_FIXUPS 2
36 #define MAX_CONSTR_STR 20
37 #define FRAG_MAX_GROWTH 8
40 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42 # define pr_debug(fmt, args...)
45 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
46 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
47 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
48 (SUB_OPCODE (x) == 0x28))
50 /* Equal to MAX_PRECISION in atof-ieee.c. */
51 #define MAX_LITTLENUMS 6
53 /* Enum used to enumerate the relaxable ins operands. */
58 REGISTER_S
, /* Register for short instruction(s). */
59 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
60 REGISTER_DUP
, /* Duplication of previous operand of type register. */
94 #define regno(x) ((x) & 0x3F)
95 #define is_ir_num(x) (((x) & ~0x3F) == 0)
96 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
97 #define is_spfp_p(op) (((sc) == SPX))
98 #define is_dpfp_p(op) (((sc) == DPX))
99 #define is_fpuda_p(op) (((sc) == DPA))
100 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
101 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
103 /* Generic assembler global variables which must be defined by all
106 /* Characters which always start a comment. */
107 const char comment_chars
[] = "#;";
109 /* Characters which start a comment at the beginning of a line. */
110 const char line_comment_chars
[] = "#";
112 /* Characters which may be used to separate multiple commands on a
114 const char line_separator_chars
[] = "`";
116 /* Characters which are used to indicate an exponent in a floating
118 const char EXP_CHARS
[] = "eE";
120 /* Chars that mean this number is a floating point constant
121 As in 0f12.456 or 0d1.2345e12. */
122 const char FLT_CHARS
[] = "rRsSfFdD";
125 extern int target_big_endian
;
126 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
127 static int byte_order
= DEFAULT_BYTE_ORDER
;
129 /* By default relaxation is disabled. */
130 static int relaxation_state
= 0;
132 extern int arc_get_mach (char *);
134 /* Forward declarations. */
135 static void arc_lcomm (int);
136 static void arc_option (int);
137 static void arc_extra_reloc (int);
140 const pseudo_typeS md_pseudo_table
[] =
142 /* Make sure that .word is 32 bits. */
145 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
146 { "lcomm", arc_lcomm
, 0 },
147 { "lcommon", arc_lcomm
, 0 },
148 { "cpu", arc_option
, 0 },
150 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
151 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
156 const char *md_shortopts
= "";
160 OPTION_EB
= OPTION_MD_BASE
,
173 /* The following options are deprecated and provided here only for
174 compatibility reasons. */
200 struct option md_longopts
[] =
202 { "EB", no_argument
, NULL
, OPTION_EB
},
203 { "EL", no_argument
, NULL
, OPTION_EL
},
204 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
205 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
206 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
207 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
208 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
209 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
210 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
211 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
212 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
213 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
215 /* The following options are deprecated and provided here only for
216 compatibility reasons. */
217 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
218 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
219 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
220 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
221 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
222 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
223 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
224 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
225 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
226 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
227 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
228 { "mea", no_argument
, NULL
, OPTION_EA
},
229 { "mEA", no_argument
, NULL
, OPTION_EA
},
230 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
231 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
232 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
233 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
234 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
235 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
236 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
237 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
238 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
239 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
240 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
241 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
242 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
243 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
244 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
245 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
246 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
247 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
248 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
249 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
250 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
251 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
252 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
253 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
254 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
255 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
257 { NULL
, no_argument
, NULL
, 0 }
260 size_t md_longopts_size
= sizeof (md_longopts
);
262 /* Local data and data types. */
264 /* Used since new relocation types are introduced in this
265 file (DUMMY_RELOC_LITUSE_*). */
266 typedef int extended_bfd_reloc_code_real_type
;
272 extended_bfd_reloc_code_real_type reloc
;
274 /* index into arc_operands. */
275 unsigned int opindex
;
277 /* PC-relative, used by internals fixups. */
280 /* TRUE if this fixup is for LIMM operand. */
288 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
290 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
292 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
294 bfd_boolean relax
; /* Boolean value: TRUE if needs
298 /* Structure to hold any last two instructions. */
299 static struct arc_last_insn
301 /* Saved instruction opcode. */
302 const struct arc_opcode
*opcode
;
304 /* Boolean value: TRUE if current insn is short. */
305 bfd_boolean has_limm
;
307 /* Boolean value: TRUE if current insn has delay slot. */
308 bfd_boolean has_delay_slot
;
311 /* Structure to hold an entry in ARC_OPCODE_HASH. */
312 struct arc_opcode_hash_entry
314 /* The number of pointers in the OPCODE list. */
317 /* Points to a list of opcode pointers. */
318 const struct arc_opcode
**opcode
;
321 /* Structure used for iterating through an arc_opcode_hash_entry. */
322 struct arc_opcode_hash_entry_iterator
324 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
327 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
328 returned by this iterator. */
329 const struct arc_opcode
*opcode
;
332 /* Forward declaration. */
333 static void assemble_insn
334 (const struct arc_opcode
*, const expressionS
*, int,
335 const struct arc_flags
*, int, struct arc_insn
*);
337 /* The cpu for which we are generating code. */
338 static unsigned arc_target
;
339 static const char *arc_target_name
;
340 static unsigned arc_features
;
342 /* The default architecture. */
343 static int arc_mach_type
;
345 /* Non-zero if the cpu type has been explicitly specified. */
346 static int mach_type_specified_p
= 0;
348 /* The hash table of instruction opcodes. */
349 static struct hash_control
*arc_opcode_hash
;
351 /* The hash table of register symbols. */
352 static struct hash_control
*arc_reg_hash
;
354 /* A table of CPU names and opcode sets. */
355 static const struct cpu_type
365 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
366 E_ARC_MACH_ARC600
, 0x00},
367 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
368 E_ARC_MACH_ARC700
, 0x00},
369 { "nps400", ARC_OPCODE_ARC700
| ARC_OPCODE_NPS400
, bfd_mach_arc_nps400
,
370 E_ARC_MACH_NPS400
, 0x00},
371 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
372 EF_ARC_CPU_ARCV2EM
, ARC_CD
},
373 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
374 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
378 /* Used by the arc_reloc_op table. Order is important. */
379 #define O_gotoff O_md1 /* @gotoff relocation. */
380 #define O_gotpc O_md2 /* @gotpc relocation. */
381 #define O_plt O_md3 /* @plt relocation. */
382 #define O_sda O_md4 /* @sda relocation. */
383 #define O_pcl O_md5 /* @pcl relocation. */
384 #define O_tlsgd O_md6 /* @tlsgd relocation. */
385 #define O_tlsie O_md7 /* @tlsie relocation. */
386 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
387 #define O_tpoff O_md9 /* @tpoff relocation. */
388 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
389 #define O_dtpoff O_md11 /* @dtpoff relocation. */
390 #define O_last O_dtpoff
392 /* Used to define a bracket as operand in tokens. */
393 #define O_bracket O_md32
395 /* Dummy relocation, to be sorted out. */
396 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
398 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
400 /* A table to map the spelling of a relocation operand into an appropriate
401 bfd_reloc_code_real_type type. The table is assumed to be ordered such
402 that op-O_literal indexes into it. */
403 #define ARC_RELOC_TABLE(op) \
404 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
406 : (int) (op) - (int) O_gotoff) ])
408 #define DEF(NAME, RELOC, REQ) \
409 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
411 static const struct arc_reloc_op_tag
413 /* String to lookup. */
415 /* Size of the string. */
417 /* Which operator to use. */
419 extended_bfd_reloc_code_real_type reloc
;
420 /* Allows complex relocation expression like identifier@reloc +
422 unsigned int complex_expr
: 1;
426 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
427 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
428 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
429 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
430 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
431 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
432 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
433 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
434 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
435 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
436 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 0),
439 static const int arc_num_reloc_op
440 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
442 /* Structure for relaxable instruction that have to be swapped with a
443 smaller alternative instruction. */
444 struct arc_relaxable_ins
446 /* Mnemonic that should be checked. */
447 const char *mnemonic_r
;
449 /* Operands that should be checked.
450 Indexes of operands from operand array. */
451 enum rlx_operand_type operands
[6];
453 /* Flags that should be checked. */
454 unsigned flag_classes
[5];
456 /* Mnemonic (smaller) alternative to be used later for relaxation. */
457 const char *mnemonic_alt
;
459 /* Index of operand that generic relaxation has to check. */
462 /* Base subtype index used. */
463 enum arc_rlx_types subtype
;
466 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
467 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
468 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
472 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
473 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
474 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
479 /* ARC relaxation table. */
480 const relax_typeS md_relax_table
[] =
487 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL
),
488 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
492 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B
),
493 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
498 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6
),
499 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM
),
500 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
502 /* LD_S a, [b, u7] ->
503 LD<zz><.x><.aa><.di> a, [b, s9] ->
504 LD<zz><.x><.aa><.di> a, [b, limm] */
505 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9
),
506 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM
),
507 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE
),
512 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12
),
513 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM
),
514 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
518 SUB<.f> a, b, limm. */
519 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6
),
520 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM
),
521 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
523 /* MPY<.f> a, b, u6 ->
524 MPY<.f> a, b, limm. */
525 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM
),
526 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
528 /* MOV<.f><.cc> b, u6 ->
529 MOV<.f><.cc> b, limm. */
530 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM
),
531 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
533 /* ADD<.f><.cc> b, b, u6 ->
534 ADD<.f><.cc> b, b, limm. */
535 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM
),
536 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
539 /* Order of this table's entries matters! */
540 const struct arc_relaxable_ins arc_relaxable_insns
[] =
542 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
543 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
544 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
545 2, ARC_RLX_ADD_RRU6
},
546 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
548 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
550 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
551 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
552 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
553 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
554 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
555 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
556 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
557 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
559 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
561 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
565 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
567 /* Flags to set in the elf header. */
568 static flagword arc_eflag
= 0x00;
570 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
571 symbolS
* GOT_symbol
= 0;
573 /* Set to TRUE when we assemble instructions. */
574 static bfd_boolean assembling_insn
= FALSE
;
576 /* Functions implementation. */
578 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
579 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
580 are no matching entries in ARC_OPCODE_HASH. */
582 static const struct arc_opcode_hash_entry
*
583 arc_find_opcode (const char *name
)
585 const struct arc_opcode_hash_entry
*entry
;
587 entry
= hash_find (arc_opcode_hash
, name
);
591 /* Initialise the iterator ITER. */
594 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
600 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
601 calls to this function. Return NULL when all ARC_OPCODE entries have
604 static const struct arc_opcode
*
605 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
606 struct arc_opcode_hash_entry_iterator
*iter
)
608 if (iter
->opcode
== NULL
&& iter
->index
== 0)
610 gas_assert (entry
->count
> 0);
611 iter
->opcode
= entry
->opcode
[iter
->index
];
613 else if (iter
->opcode
!= NULL
)
615 const char *old_name
= iter
->opcode
->name
;
618 if ((iter
->opcode
- arc_opcodes
>= (int) arc_num_opcodes
)
619 || (strcmp (old_name
, iter
->opcode
->name
) != 0))
622 if (iter
->index
== entry
->count
)
625 iter
->opcode
= entry
->opcode
[iter
->index
];
632 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
633 is encoded as 'middle-endian' for a little-endian target. FIXME!
634 this function is used for regular 4 byte instructions as well. */
637 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
641 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
642 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
646 md_number_to_chars (buf
, val
, n
);
650 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
651 the relevant static global variables. */
654 arc_select_cpu (const char *arg
)
659 for (i
= 0; cpu_types
[i
].name
; ++i
)
661 if (!strcasecmp (cpu_types
[i
].name
, arg
))
663 arc_target
= cpu_types
[i
].flags
;
664 arc_target_name
= cpu_types
[i
].name
;
665 arc_features
= cpu_types
[i
].features
;
666 arc_mach_type
= cpu_types
[i
].mach
;
667 cpu_flags
= cpu_types
[i
].eflags
;
672 if (!cpu_types
[i
].name
)
673 as_fatal (_("unknown architecture: %s\n"), arg
);
674 gas_assert (cpu_flags
!= 0);
675 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
678 /* Here ends all the ARCompact extension instruction assembling
682 arc_extra_reloc (int r_type
)
685 symbolS
*sym
, *lab
= NULL
;
687 if (*input_line_pointer
== '@')
688 input_line_pointer
++;
689 c
= get_symbol_name (&sym_name
);
690 sym
= symbol_find_or_make (sym_name
);
691 restore_line_pointer (c
);
692 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
694 ++input_line_pointer
;
696 c
= get_symbol_name (&lab_name
);
697 lab
= symbol_find_or_make (lab_name
);
698 restore_line_pointer (c
);
701 /* These relocations exist as a mechanism for the compiler to tell the
702 linker how to patch the code if the tls model is optimised. However,
703 the relocation itself does not require any space within the assembler
704 fragment, and so we pass a size of 0.
706 The lines that generate these relocations look like this:
708 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
710 The '.tls_gd_ld @.tdata' is processed first and generates the
711 additional relocation, while the 'bl __tls_get_addr@plt' is processed
712 second and generates the additional branch.
714 It is possible that the additional relocation generated by the
715 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
716 while the 'bl __tls_get_addr@plt' will be generated as the first thing
717 in the next fragment. This will be fine; both relocations will still
718 appear to be at the same address in the generated object file.
719 However, this only works as the additional relocation is generated
720 with size of 0 bytes. */
722 = fix_new (frag_now
, /* Which frag? */
723 frag_now_fix (), /* Where in that frag? */
724 0, /* size: 1, 2, or 4 usually. */
725 sym
, /* X_add_symbol. */
726 0, /* X_add_number. */
727 FALSE
, /* TRUE if PC-relative relocation. */
728 r_type
/* Relocation type. */);
729 fixP
->fx_subsy
= lab
;
733 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
734 symbolS
*symbolP
, addressT size
)
739 if (*input_line_pointer
== ',')
741 align
= parse_align (1);
743 if (align
== (addressT
) -1)
758 bss_alloc (symbolP
, size
, align
);
759 S_CLEAR_EXTERNAL (symbolP
);
765 arc_lcomm (int ignore
)
767 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
770 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
773 /* Select the cpu we're assembling for. */
776 arc_option (int ignore ATTRIBUTE_UNUSED
)
782 c
= get_symbol_name (&cpu
);
783 mach
= arc_get_mach (cpu
);
788 if (!mach_type_specified_p
)
790 if ((!strcmp ("ARC600", cpu
))
791 || (!strcmp ("ARC601", cpu
))
792 || (!strcmp ("A6", cpu
)))
794 md_parse_option (OPTION_MCPU
, "arc600");
796 else if ((!strcmp ("ARC700", cpu
))
797 || (!strcmp ("A7", cpu
)))
799 md_parse_option (OPTION_MCPU
, "arc700");
801 else if (!strcmp ("EM", cpu
))
803 md_parse_option (OPTION_MCPU
, "arcem");
805 else if (!strcmp ("HS", cpu
))
807 md_parse_option (OPTION_MCPU
, "archs");
810 as_fatal (_("could not find the architecture"));
812 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
813 as_fatal (_("could not set architecture and machine"));
816 if (arc_mach_type
!= mach
)
817 as_warn (_("Command-line value overrides \".cpu\" directive"));
819 restore_line_pointer (c
);
820 demand_empty_rest_of_line ();
824 restore_line_pointer (c
);
825 as_bad (_("invalid identifier for \".cpu\""));
826 ignore_rest_of_line ();
829 /* Smartly print an expression. */
832 debug_exp (expressionS
*t
)
834 const char *name ATTRIBUTE_UNUSED
;
835 const char *namemd ATTRIBUTE_UNUSED
;
837 pr_debug ("debug_exp: ");
841 default: name
= "unknown"; break;
842 case O_illegal
: name
= "O_illegal"; break;
843 case O_absent
: name
= "O_absent"; break;
844 case O_constant
: name
= "O_constant"; break;
845 case O_symbol
: name
= "O_symbol"; break;
846 case O_symbol_rva
: name
= "O_symbol_rva"; break;
847 case O_register
: name
= "O_register"; break;
848 case O_big
: name
= "O_big"; break;
849 case O_uminus
: name
= "O_uminus"; break;
850 case O_bit_not
: name
= "O_bit_not"; break;
851 case O_logical_not
: name
= "O_logical_not"; break;
852 case O_multiply
: name
= "O_multiply"; break;
853 case O_divide
: name
= "O_divide"; break;
854 case O_modulus
: name
= "O_modulus"; break;
855 case O_left_shift
: name
= "O_left_shift"; break;
856 case O_right_shift
: name
= "O_right_shift"; break;
857 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
858 case O_bit_or_not
: name
= "O_bit_or_not"; break;
859 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
860 case O_bit_and
: name
= "O_bit_and"; break;
861 case O_add
: name
= "O_add"; break;
862 case O_subtract
: name
= "O_subtract"; break;
863 case O_eq
: name
= "O_eq"; break;
864 case O_ne
: name
= "O_ne"; break;
865 case O_lt
: name
= "O_lt"; break;
866 case O_le
: name
= "O_le"; break;
867 case O_ge
: name
= "O_ge"; break;
868 case O_gt
: name
= "O_gt"; break;
869 case O_logical_and
: name
= "O_logical_and"; break;
870 case O_logical_or
: name
= "O_logical_or"; break;
871 case O_index
: name
= "O_index"; break;
872 case O_bracket
: name
= "O_bracket"; break;
877 default: namemd
= "unknown"; break;
878 case O_gotoff
: namemd
= "O_gotoff"; break;
879 case O_gotpc
: namemd
= "O_gotpc"; break;
880 case O_plt
: namemd
= "O_plt"; break;
881 case O_sda
: namemd
= "O_sda"; break;
882 case O_pcl
: namemd
= "O_pcl"; break;
883 case O_tlsgd
: namemd
= "O_tlsgd"; break;
884 case O_tlsie
: namemd
= "O_tlsie"; break;
885 case O_tpoff9
: namemd
= "O_tpoff9"; break;
886 case O_tpoff
: namemd
= "O_tpoff"; break;
887 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
888 case O_dtpoff
: namemd
= "O_dtpoff"; break;
891 pr_debug ("%s (%s, %s, %d, %s)", name
,
892 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
893 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
894 (int) t
->X_add_number
,
895 (t
->X_md
) ? namemd
: "--");
900 /* Parse the arguments to an opcode. */
903 tokenize_arguments (char *str
,
907 char *old_input_line_pointer
;
908 bfd_boolean saw_comma
= FALSE
;
909 bfd_boolean saw_arg
= FALSE
;
914 const struct arc_reloc_op_tag
*r
;
918 memset (tok
, 0, sizeof (*tok
) * ntok
);
920 /* Save and restore input_line_pointer around this function. */
921 old_input_line_pointer
= input_line_pointer
;
922 input_line_pointer
= str
;
924 while (*input_line_pointer
)
927 switch (*input_line_pointer
)
933 input_line_pointer
++;
934 if (saw_comma
|| !saw_arg
)
941 ++input_line_pointer
;
945 tok
->X_op
= O_bracket
;
952 input_line_pointer
++;
956 tok
->X_op
= O_bracket
;
962 /* We have labels, function names and relocations, all
963 starting with @ symbol. Sort them out. */
964 if (saw_arg
&& !saw_comma
)
968 tok
->X_op
= O_symbol
;
969 tok
->X_md
= O_absent
;
971 if (*input_line_pointer
!= '@')
972 goto normalsymbol
; /* This is not a relocation. */
976 /* A relocation opernad has the following form
977 @identifier@relocation_type. The identifier is already
979 if (tok
->X_op
!= O_symbol
)
981 as_bad (_("No valid label relocation operand"));
985 /* Parse @relocation_type. */
986 input_line_pointer
++;
987 c
= get_symbol_name (&reloc_name
);
988 len
= input_line_pointer
- reloc_name
;
991 as_bad (_("No relocation operand"));
995 /* Go through known relocation and try to find a match. */
996 r
= &arc_reloc_op
[0];
997 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
999 && memcmp (reloc_name
, r
->name
, len
) == 0)
1003 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1007 *input_line_pointer
= c
;
1008 SKIP_WHITESPACE_AFTER_NAME ();
1009 /* Extra check for TLS: base. */
1010 if (*input_line_pointer
== '@')
1013 if (tok
->X_op_symbol
!= NULL
1014 || tok
->X_op
!= O_symbol
)
1016 as_bad (_("Unable to parse TLS base: %s"),
1017 input_line_pointer
);
1020 input_line_pointer
++;
1022 c
= get_symbol_name (&sym_name
);
1023 base
= symbol_find_or_make (sym_name
);
1024 tok
->X_op
= O_subtract
;
1025 tok
->X_op_symbol
= base
;
1026 restore_line_pointer (c
);
1027 tmpE
.X_add_number
= 0;
1029 else if ((*input_line_pointer
!= '+')
1030 && (*input_line_pointer
!= '-'))
1032 tmpE
.X_add_number
= 0;
1036 /* Parse the constant of a complex relocation expression
1037 like @identifier@reloc +/- const. */
1038 if (! r
->complex_expr
)
1040 as_bad (_("@%s is not a complex relocation."), r
->name
);
1044 if (tmpE
.X_op
!= O_constant
)
1046 as_bad (_("Bad expression: @%s + %s."),
1047 r
->name
, input_line_pointer
);
1053 tok
->X_add_number
= tmpE
.X_add_number
;
1064 /* Can be a register. */
1065 ++input_line_pointer
;
1069 if (saw_arg
&& !saw_comma
)
1072 tok
->X_op
= O_absent
;
1073 tok
->X_md
= O_absent
;
1076 /* Legacy: There are cases when we have
1077 identifier@relocation_type, if it is the case parse the
1078 relocation type as well. */
1079 if (*input_line_pointer
== '@')
1085 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1097 if (saw_comma
|| brk_lvl
)
1099 input_line_pointer
= old_input_line_pointer
;
1105 as_bad (_("Brackets in operand field incorrect"));
1107 as_bad (_("extra comma"));
1109 as_bad (_("missing argument"));
1111 as_bad (_("missing comma or colon"));
1112 input_line_pointer
= old_input_line_pointer
;
1116 /* Parse the flags to a structure. */
1119 tokenize_flags (const char *str
,
1120 struct arc_flags flags
[],
1123 char *old_input_line_pointer
;
1124 bfd_boolean saw_flg
= FALSE
;
1125 bfd_boolean saw_dot
= FALSE
;
1129 memset (flags
, 0, sizeof (*flags
) * nflg
);
1131 /* Save and restore input_line_pointer around this function. */
1132 old_input_line_pointer
= input_line_pointer
;
1133 input_line_pointer
= (char *) str
;
1135 while (*input_line_pointer
)
1137 switch (*input_line_pointer
)
1144 input_line_pointer
++;
1152 if (saw_flg
&& !saw_dot
)
1155 if (num_flags
>= nflg
)
1158 flgnamelen
= strspn (input_line_pointer
,
1159 "abcdefghijklmnopqrstuvwxyz0123456789");
1160 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1163 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1165 input_line_pointer
+= flgnamelen
;
1175 input_line_pointer
= old_input_line_pointer
;
1180 as_bad (_("extra dot"));
1182 as_bad (_("unrecognized flag"));
1184 as_bad (_("failed to parse flags"));
1185 input_line_pointer
= old_input_line_pointer
;
1189 /* Apply the fixups in order. */
1192 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1196 for (i
= 0; i
< insn
->nfixups
; i
++)
1198 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1199 int size
, pcrel
, offset
= 0;
1201 /* FIXME! the reloc size is wrong in the BFD file.
1202 When it is fixed please delete me. */
1203 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1206 offset
= (insn
->short_insn
) ? 2 : 4;
1208 /* Some fixups are only used internally, thus no howto. */
1209 if ((int) fixup
->reloc
== 0)
1210 as_fatal (_("Unhandled reloc type"));
1212 if ((int) fixup
->reloc
< 0)
1214 /* FIXME! the reloc size is wrong in the BFD file.
1215 When it is fixed please enable me.
1216 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1217 pcrel
= fixup
->pcrel
;
1221 reloc_howto_type
*reloc_howto
=
1222 bfd_reloc_type_lookup (stdoutput
,
1223 (bfd_reloc_code_real_type
) fixup
->reloc
);
1224 gas_assert (reloc_howto
);
1226 /* FIXME! the reloc size is wrong in the BFD file.
1227 When it is fixed please enable me.
1228 size = bfd_get_reloc_size (reloc_howto); */
1229 pcrel
= reloc_howto
->pc_relative
;
1232 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1234 fragP
->fr_file
, fragP
->fr_line
,
1235 (fixup
->reloc
< 0) ? "Internal" :
1236 bfd_get_reloc_code_name (fixup
->reloc
),
1239 fix_new_exp (fragP
, fix
+ offset
,
1240 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1242 /* Check for ZOLs, and update symbol info if any. */
1243 if (LP_INSN (insn
->insn
))
1245 gas_assert (fixup
->exp
.X_add_symbol
);
1246 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1251 /* Actually output an instruction with its fixup. */
1254 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1258 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1259 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1260 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1262 /* Write out the instruction. */
1263 if (insn
->short_insn
)
1269 md_number_to_chars (f
, insn
->insn
, 2);
1270 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1271 dwarf2_emit_insn (6);
1277 md_number_to_chars (f
, insn
->insn
, 2);
1278 dwarf2_emit_insn (2);
1287 md_number_to_chars_midend (f
, insn
->insn
, 4);
1288 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1289 dwarf2_emit_insn (8);
1295 md_number_to_chars_midend (f
, insn
->insn
, 4);
1296 dwarf2_emit_insn (4);
1301 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1305 emit_insn1 (struct arc_insn
*insn
)
1307 /* How frag_var's args are currently configured:
1308 - rs_machine_dependent, to dictate it's a relaxation frag.
1309 - FRAG_MAX_GROWTH, maximum size of instruction
1310 - 0, variable size that might grow...unused by generic relaxation.
1311 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1312 - s, opand expression.
1313 - 0, offset but it's unused.
1314 - 0, opcode but it's unused. */
1315 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1316 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1318 if (frag_room () < FRAG_MAX_GROWTH
)
1320 /* Handle differently when frag literal memory is exhausted.
1321 This is used because when there's not enough memory left in
1322 the current frag, a new frag is created and the information
1323 we put into frag_now->tc_frag_data is disregarded. */
1325 struct arc_relax_type relax_info_copy
;
1326 relax_substateT subtype
= frag_now
->fr_subtype
;
1328 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1329 sizeof (struct arc_relax_type
));
1331 frag_wane (frag_now
);
1332 frag_grow (FRAG_MAX_GROWTH
);
1334 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1335 sizeof (struct arc_relax_type
));
1337 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1341 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1342 frag_now
->fr_subtype
, s
, 0, 0);
1346 emit_insn (struct arc_insn
*insn
)
1351 emit_insn0 (insn
, NULL
, FALSE
);
1354 /* Check whether a symbol involves a register. */
1357 contains_register (symbolS
*sym
)
1361 expressionS
*ex
= symbol_get_value_expression (sym
);
1363 return ((O_register
== ex
->X_op
)
1364 && !contains_register (ex
->X_add_symbol
)
1365 && !contains_register (ex
->X_op_symbol
));
1371 /* Returns the register number within a symbol. */
1374 get_register (symbolS
*sym
)
1376 if (!contains_register (sym
))
1379 expressionS
*ex
= symbol_get_value_expression (sym
);
1380 return regno (ex
->X_add_number
);
1383 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1384 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1387 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1394 case BFD_RELOC_ARC_SDA_LDST
:
1395 case BFD_RELOC_ARC_SDA_LDST1
:
1396 case BFD_RELOC_ARC_SDA_LDST2
:
1397 case BFD_RELOC_ARC_SDA16_LD
:
1398 case BFD_RELOC_ARC_SDA16_LD1
:
1399 case BFD_RELOC_ARC_SDA16_LD2
:
1400 case BFD_RELOC_ARC_SDA16_ST2
:
1401 case BFD_RELOC_ARC_SDA32_ME
:
1408 /* Allocates a tok entry. */
1411 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1413 if (ntok
> MAX_INSN_ARGS
- 2)
1414 return 0; /* No space left. */
1417 return 0; /* Incorect args. */
1419 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1422 return 1; /* Success. */
1423 return allocate_tok (tok
, ntok
- 1, cidx
);
1426 /* Check if an particular ARC feature is enabled. */
1429 check_cpu_feature (insn_subclass_t sc
)
1431 if (!(arc_features
& ARC_CD
)
1432 && is_code_density_p (sc
))
1435 if (!(arc_features
& ARC_SPFP
)
1439 if (!(arc_features
& ARC_DPFP
)
1443 if (!(arc_features
& ARC_FPUDA
)
1450 /* Search forward through all variants of an opcode looking for a
1453 static const struct arc_opcode
*
1454 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1457 struct arc_flags
*first_pflag
,
1461 const struct arc_opcode
*opcode
;
1462 struct arc_opcode_hash_entry_iterator iter
;
1464 int got_cpu_match
= 0;
1465 expressionS bktok
[MAX_INSN_ARGS
];
1469 arc_opcode_hash_entry_iterator_init (&iter
);
1470 memset (&emptyE
, 0, sizeof (emptyE
));
1471 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1474 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1476 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1478 const unsigned char *opidx
;
1479 const unsigned char *flgidx
;
1480 int tokidx
= 0, lnflg
, i
;
1481 const expressionS
*t
= &emptyE
;
1483 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1484 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1486 /* Don't match opcodes that don't exist on this
1488 if (!(opcode
->cpu
& arc_target
))
1491 if (!check_cpu_feature (opcode
->subclass
))
1497 /* Check the operands. */
1498 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1500 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1502 /* Only take input from real operands. */
1503 if ((operand
->flags
& ARC_OPERAND_FAKE
)
1504 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
1507 /* When we expect input, make sure we have it. */
1511 /* Match operand type with expression type. */
1512 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1514 case ARC_OPERAND_IR
:
1515 /* Check to be a register. */
1516 if ((tok
[tokidx
].X_op
!= O_register
1517 || !is_ir_num (tok
[tokidx
].X_add_number
))
1518 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1521 /* If expect duplicate, make sure it is duplicate. */
1522 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1524 /* Check for duplicate. */
1525 if (t
->X_op
!= O_register
1526 || !is_ir_num (t
->X_add_number
)
1527 || (regno (t
->X_add_number
) !=
1528 regno (tok
[tokidx
].X_add_number
)))
1532 /* Special handling? */
1533 if (operand
->insert
)
1535 const char *errmsg
= NULL
;
1536 (*operand
->insert
)(0,
1537 regno (tok
[tokidx
].X_add_number
),
1541 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1543 /* Missing argument, create one. */
1544 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1547 tok
[tokidx
].X_op
= O_absent
;
1558 case ARC_OPERAND_BRAKET
:
1559 /* Check if bracket is also in opcode table as
1561 if (tok
[tokidx
].X_op
!= O_bracket
)
1565 case ARC_OPERAND_LIMM
:
1566 case ARC_OPERAND_SIGNED
:
1567 case ARC_OPERAND_UNSIGNED
:
1568 switch (tok
[tokidx
].X_op
)
1576 /* Got an (too) early bracket, check if it is an
1577 ignored operand. N.B. This procedure works only
1578 when bracket is the last operand! */
1579 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1581 /* Insert the missing operand. */
1582 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1585 tok
[tokidx
].X_op
= O_absent
;
1593 const struct arc_aux_reg
*auxr
;
1596 if (opcode
->class != AUXREG
)
1598 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1601 auxr
= &arc_aux_regs
[0];
1602 for (j
= 0; j
< arc_num_aux_regs
; j
++, auxr
++)
1603 if (len
== auxr
->length
1604 && strcasecmp (auxr
->name
, p
) == 0
1605 && ((auxr
->subclass
== NONE
)
1606 || check_cpu_feature (auxr
->subclass
)))
1608 /* We modify the token array here, safe in the
1609 knowledge, that if this was the wrong choice
1610 then the original contents will be restored
1612 tok
[tokidx
].X_op
= O_constant
;
1613 tok
[tokidx
].X_add_number
= auxr
->address
;
1617 if (tok
[tokidx
].X_op
!= O_constant
)
1622 /* Check the range. */
1623 if (operand
->bits
!= 32
1624 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1626 offsetT min
, max
, val
;
1627 val
= tok
[tokidx
].X_add_number
;
1629 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1631 max
= (1 << (operand
->bits
- 1)) - 1;
1632 min
= -(1 << (operand
->bits
- 1));
1636 max
= (1 << operand
->bits
) - 1;
1640 if (val
< min
|| val
> max
)
1643 /* Check alignmets. */
1644 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1648 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1652 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1654 if (operand
->insert
)
1656 const char *errmsg
= NULL
;
1657 (*operand
->insert
)(0,
1658 tok
[tokidx
].X_add_number
,
1669 /* Check if it is register range. */
1670 if ((tok
[tokidx
].X_add_number
== 0)
1671 && contains_register (tok
[tokidx
].X_add_symbol
)
1672 && contains_register (tok
[tokidx
].X_op_symbol
))
1676 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1678 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1679 if (operand
->insert
)
1681 const char *errmsg
= NULL
;
1682 (*operand
->insert
)(0,
1694 if (operand
->default_reloc
== 0)
1695 goto match_failed
; /* The operand needs relocation. */
1697 /* Relocs requiring long immediate. FIXME! make it
1698 generic and move it to a function. */
1699 switch (tok
[tokidx
].X_md
)
1708 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1711 if (!generic_reloc_p (operand
->default_reloc
))
1718 /* If expect duplicate, make sure it is duplicate. */
1719 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1721 if (t
->X_op
== O_illegal
1722 || t
->X_op
== O_absent
1723 || t
->X_op
== O_register
1724 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1731 /* Everything else should have been fake. */
1739 /* Setup ready for flag parsing. */
1741 for (i
= 0; i
< nflgs
; i
++)
1742 first_pflag
[i
].code
= 0;
1744 /* Check the flags. Iterate over the valid flag classes. */
1745 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1747 /* Get a valid flag class. */
1748 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1749 const unsigned *flgopridx
;
1752 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1754 const struct arc_flag_operand
*flg_operand
;
1755 struct arc_flags
*pflag
= first_pflag
;
1757 flg_operand
= &arc_flag_operands
[*flgopridx
];
1758 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1760 /* Match against the parsed flags. */
1761 if (!strcmp (flg_operand
->name
, pflag
->name
))
1763 if (pflag
->code
!= 0)
1766 pflag
->code
= *flgopridx
;
1768 break; /* goto next flag class and parsed flag. */
1773 if (cl_flags
->class == F_CLASS_REQUIRED
&& cl_matches
== 0)
1775 if (cl_flags
->class == F_CLASS_OPTIONAL
&& cl_matches
> 1)
1778 /* Did I check all the parsed flags? */
1783 /* Possible match -- did we use all of our input? */
1793 /* Restore the original parameters. */
1794 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1799 *pcpumatch
= got_cpu_match
;
1804 /* Swap operand tokens. */
1807 swap_operand (expressionS
*operand_array
,
1809 unsigned destination
)
1811 expressionS cpy_operand
;
1812 expressionS
*src_operand
;
1813 expressionS
*dst_operand
;
1816 if (source
== destination
)
1819 src_operand
= &operand_array
[source
];
1820 dst_operand
= &operand_array
[destination
];
1821 size
= sizeof (expressionS
);
1823 /* Make copy of operand to swap with and swap. */
1824 memcpy (&cpy_operand
, dst_operand
, size
);
1825 memcpy (dst_operand
, src_operand
, size
);
1826 memcpy (src_operand
, &cpy_operand
, size
);
1829 /* Check if *op matches *tok type.
1830 Returns FALSE if they don't match, TRUE if they match. */
1833 pseudo_operand_match (const expressionS
*tok
,
1834 const struct arc_operand_operation
*op
)
1836 offsetT min
, max
, val
;
1838 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
1844 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
1846 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
1848 val
= tok
->X_add_number
+ op
->count
;
1849 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
1851 max
= (1 << (operand_real
->bits
- 1)) - 1;
1852 min
= -(1 << (operand_real
->bits
- 1));
1856 max
= (1 << operand_real
->bits
) - 1;
1859 if (min
<= val
&& val
<= max
)
1865 /* Handle all symbols as long immediates or signed 9. */
1866 if (operand_real
->flags
& ARC_OPERAND_LIMM
||
1867 ((operand_real
->flags
& ARC_OPERAND_SIGNED
) && operand_real
->bits
== 9))
1872 if (operand_real
->flags
& ARC_OPERAND_IR
)
1877 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
1888 /* Find pseudo instruction in array. */
1890 static const struct arc_pseudo_insn
*
1891 find_pseudo_insn (const char *opname
,
1893 const expressionS
*tok
)
1895 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
1896 const struct arc_operand_operation
*op
;
1900 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
1902 pseudo_insn
= &arc_pseudo_insns
[i
];
1903 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
1905 op
= pseudo_insn
->operand
;
1906 for (j
= 0; j
< ntok
; ++j
)
1907 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
1910 /* Found the right instruction. */
1918 /* Assumes the expressionS *tok is of sufficient size. */
1920 static const struct arc_opcode_hash_entry
*
1921 find_special_case_pseudo (const char *opname
,
1925 struct arc_flags
*pflags
)
1927 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
1928 const struct arc_operand_operation
*operand_pseudo
;
1929 const struct arc_operand
*operand_real
;
1931 char construct_operand
[MAX_CONSTR_STR
];
1933 /* Find whether opname is in pseudo instruction array. */
1934 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
1936 if (pseudo_insn
== NULL
)
1939 /* Handle flag, Limited to one flag at the moment. */
1940 if (pseudo_insn
->flag_r
!= NULL
)
1941 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
1942 MAX_INSN_FLGS
- *nflgs
);
1944 /* Handle operand operations. */
1945 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
1947 operand_pseudo
= &pseudo_insn
->operand
[i
];
1948 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
1950 if (operand_real
->flags
& ARC_OPERAND_BRAKET
&&
1951 !operand_pseudo
->needs_insert
)
1954 /* Has to be inserted (i.e. this token does not exist yet). */
1955 if (operand_pseudo
->needs_insert
)
1957 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
1959 tok
[i
].X_op
= O_bracket
;
1964 /* Check if operand is a register or constant and handle it
1966 if (operand_real
->flags
& ARC_OPERAND_IR
)
1967 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
1968 operand_pseudo
->count
);
1970 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
1971 operand_pseudo
->count
);
1973 tokenize_arguments (construct_operand
, &tok
[i
], 1);
1977 else if (operand_pseudo
->count
)
1979 /* Operand number has to be adjusted accordingly (by operand
1981 switch (tok
[i
].X_op
)
1984 tok
[i
].X_add_number
+= operand_pseudo
->count
;
1997 /* Swap operands if necessary. Only supports one swap at the
1999 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2001 operand_pseudo
= &pseudo_insn
->operand
[i
];
2003 if (operand_pseudo
->swap_operand_idx
== i
)
2006 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2008 /* Prevent a swap back later by breaking out. */
2012 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2015 static const struct arc_opcode_hash_entry
*
2016 find_special_case_flag (const char *opname
,
2018 struct arc_flags
*pflags
)
2022 unsigned flag_idx
, flag_arr_idx
;
2023 size_t flaglen
, oplen
;
2024 const struct arc_flag_special
*arc_flag_special_opcode
;
2025 const struct arc_opcode_hash_entry
*entry
;
2027 /* Search for special case instruction. */
2028 for (i
= 0; i
< arc_num_flag_special
; i
++)
2030 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2031 oplen
= strlen (arc_flag_special_opcode
->name
);
2033 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2036 /* Found a potential special case instruction, now test for
2038 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2040 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2042 break; /* End of array, nothing found. */
2044 flagnm
= arc_flag_operands
[flag_idx
].name
;
2045 flaglen
= strlen (flagnm
);
2046 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2048 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2050 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2052 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2053 pflags
[*nflgs
].name
[flaglen
] = '\0';
2062 /* Used to find special case opcode. */
2064 static const struct arc_opcode_hash_entry
*
2065 find_special_case (const char *opname
,
2067 struct arc_flags
*pflags
,
2071 const struct arc_opcode_hash_entry
*entry
;
2073 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2076 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2081 /* Given an opcode name, pre-tockenized set of argumenst and the
2082 opcode flags, take it all the way through emission. */
2085 assemble_tokens (const char *opname
,
2088 struct arc_flags
*pflags
,
2091 bfd_boolean found_something
= FALSE
;
2092 const struct arc_opcode_hash_entry
*entry
;
2095 /* Search opcodes. */
2096 entry
= arc_find_opcode (opname
);
2098 /* Couldn't find opcode conventional way, try special cases. */
2100 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2104 const struct arc_opcode
*opcode
;
2106 pr_debug ("%s:%d: assemble_tokens: %s\n",
2107 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2108 found_something
= TRUE
;
2109 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2113 struct arc_insn insn
;
2115 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2121 if (found_something
)
2124 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2126 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2130 as_bad (_("unknown opcode '%s'"), opname
);
2133 /* The public interface to the instruction assembler. */
2136 md_assemble (char *str
)
2139 expressionS tok
[MAX_INSN_ARGS
];
2142 struct arc_flags flags
[MAX_INSN_FLGS
];
2144 /* Split off the opcode. */
2145 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2146 opname
= xmalloc (opnamelen
+ 1);
2147 memcpy (opname
, str
, opnamelen
);
2148 opname
[opnamelen
] = '\0';
2150 /* Signalize we are assmbling the instructions. */
2151 assembling_insn
= TRUE
;
2153 /* Tokenize the flags. */
2154 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2156 as_bad (_("syntax error"));
2160 /* Scan up to the end of the mnemonic which must end in space or end
2163 for (; *str
!= '\0'; str
++)
2167 /* Tokenize the rest of the line. */
2168 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2170 as_bad (_("syntax error"));
2174 /* Finish it off. */
2175 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2176 assembling_insn
= FALSE
;
2179 /* Callback to insert a register into the hash table. */
2182 declare_register (const char *name
, int number
)
2185 symbolS
*regS
= symbol_create (name
, reg_section
,
2186 number
, &zero_address_frag
);
2188 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2190 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2194 /* Construct symbols for each of the general registers. */
2197 declare_register_set (void)
2200 for (i
= 0; i
< 64; ++i
)
2204 sprintf (name
, "r%d", i
);
2205 declare_register (name
, i
);
2206 if ((i
& 0x01) == 0)
2208 sprintf (name
, "r%dr%d", i
, i
+1);
2209 declare_register (name
, i
);
2214 /* Port-specific assembler initialization. This function is called
2215 once, at assembler startup time. */
2222 if (!mach_type_specified_p
)
2223 arc_select_cpu ("arc700");
2225 /* The endianness can be chosen "at the factory". */
2226 target_big_endian
= byte_order
== BIG_ENDIAN
;
2228 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2229 as_warn (_("could not set architecture and machine"));
2231 /* Set elf header flags. */
2232 bfd_set_private_flags (stdoutput
, arc_eflag
);
2234 /* Set up a hash table for the instructions. */
2235 arc_opcode_hash
= hash_new ();
2236 if (arc_opcode_hash
== NULL
)
2237 as_fatal (_("Virtual memory exhausted"));
2239 /* Initialize the hash table with the insns. */
2240 for (i
= 0; i
< arc_num_opcodes
;)
2242 const char *name
, *retval
;
2243 struct arc_opcode_hash_entry
*entry
;
2245 name
= arc_opcodes
[i
].name
;
2247 entry
= hash_find (arc_opcode_hash
, name
);
2250 entry
= xmalloc (sizeof (*entry
));
2252 entry
->opcode
= NULL
;
2254 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
2256 as_fatal (_("internal error: can't hash opcode '%s': %s"),
2260 entry
->opcode
= xrealloc (entry
->opcode
,
2261 sizeof (const struct arc_opcode
*)
2262 * entry
->count
+ 1);
2263 entry
->opcode
[entry
->count
] = &arc_opcodes
[i
];
2266 while (++i
< arc_num_opcodes
2267 && (arc_opcodes
[i
].name
== name
2268 || !strcmp (arc_opcodes
[i
].name
, name
)))
2272 /* Register declaration. */
2273 arc_reg_hash
= hash_new ();
2274 if (arc_reg_hash
== NULL
)
2275 as_fatal (_("Virtual memory exhausted"));
2277 declare_register_set ();
2278 declare_register ("gp", 26);
2279 declare_register ("fp", 27);
2280 declare_register ("sp", 28);
2281 declare_register ("ilink", 29);
2282 declare_register ("ilink1", 29);
2283 declare_register ("ilink2", 30);
2284 declare_register ("blink", 31);
2286 declare_register ("mlo", 57);
2287 declare_register ("mmid", 58);
2288 declare_register ("mhi", 59);
2290 declare_register ("acc1", 56);
2291 declare_register ("acc2", 57);
2293 declare_register ("lp_count", 60);
2294 declare_register ("pcl", 63);
2296 /* Initialize the last instructions. */
2297 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2300 /* Write a value out to the object file, using the appropriate
2304 md_number_to_chars (char *buf
,
2308 if (target_big_endian
)
2309 number_to_chars_bigendian (buf
, val
, n
);
2311 number_to_chars_littleendian (buf
, val
, n
);
2314 /* Round up a section size to the appropriate boundary. */
2317 md_section_align (segT segment
,
2320 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2322 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2325 /* The location from which a PC relative jump should be calculated,
2326 given a PC relative reloc. */
2329 md_pcrel_from_section (fixS
*fixP
,
2332 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2334 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2336 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2337 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2338 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2340 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2342 /* The symbol is undefined (or is defined but not in this section).
2343 Let the linker figure it out. */
2347 if ((int) fixP
->fx_r_type
< 0)
2349 /* These are the "internal" relocations. Align them to
2350 32 bit boundary (PCL), for the moment. */
2355 switch (fixP
->fx_r_type
)
2357 case BFD_RELOC_ARC_PC32
:
2358 /* The hardware calculates relative to the start of the
2359 insn, but this relocation is relative to location of the
2360 LIMM, compensate. The base always needs to be
2361 substracted by 4 as we do not support this type of PCrel
2362 relocation for short instructions. */
2365 case BFD_RELOC_ARC_PLT32
:
2366 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2367 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2368 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2369 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2371 case BFD_RELOC_ARC_S21H_PCREL
:
2372 case BFD_RELOC_ARC_S25H_PCREL
:
2373 case BFD_RELOC_ARC_S13_PCREL
:
2374 case BFD_RELOC_ARC_S21W_PCREL
:
2375 case BFD_RELOC_ARC_S25W_PCREL
:
2379 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2380 _("unhandled reloc %s in md_pcrel_from_section"),
2381 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2386 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2387 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2388 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2389 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2394 /* Given a BFD relocation find the coresponding operand. */
2396 static const struct arc_operand
*
2397 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2401 for (i
= 0; i
< arc_num_operands
; i
++)
2402 if (arc_operands
[i
].default_reloc
== reloc
)
2403 return &arc_operands
[i
];
2407 /* Insert an operand value into an instruction. */
2410 insert_operand (unsigned insn
,
2411 const struct arc_operand
*operand
,
2416 offsetT min
= 0, max
= 0;
2418 if (operand
->bits
!= 32
2419 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2420 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2422 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2424 max
= (1 << (operand
->bits
- 1)) - 1;
2425 min
= -(1 << (operand
->bits
- 1));
2429 max
= (1 << operand
->bits
) - 1;
2433 if (val
< min
|| val
> max
)
2434 as_bad_value_out_of_range (_("operand"),
2435 val
, min
, max
, file
, line
);
2438 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2439 min
, val
, max
, insn
);
2441 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2443 as_bad_where (file
, line
,
2444 _("Unaligned operand. Needs to be 32bit aligned"));
2446 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2448 as_bad_where (file
, line
,
2449 _("Unaligned operand. Needs to be 16bit aligned"));
2451 if (operand
->insert
)
2453 const char *errmsg
= NULL
;
2455 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2457 as_warn_where (file
, line
, "%s", errmsg
);
2461 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2463 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2465 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2468 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2473 /* Apply a fixup to the object code. At this point all symbol values
2474 should be fully resolved, and we attempt to completely resolve the
2475 reloc. If we can not do that, we determine the correct reloc code
2476 and put it back in the fixup. To indicate that a fixup has been
2477 eliminated, set fixP->fx_done. */
2480 md_apply_fix (fixS
*fixP
,
2484 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2485 valueT value
= *valP
;
2487 symbolS
*fx_addsy
, *fx_subsy
;
2489 segT add_symbol_segment
= absolute_section
;
2490 segT sub_symbol_segment
= absolute_section
;
2491 const struct arc_operand
*operand
= NULL
;
2492 extended_bfd_reloc_code_real_type reloc
;
2494 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2495 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2496 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2497 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2500 fx_addsy
= fixP
->fx_addsy
;
2501 fx_subsy
= fixP
->fx_subsy
;
2506 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2510 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2511 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2512 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2514 resolve_symbol_value (fx_subsy
);
2515 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2517 if (sub_symbol_segment
== absolute_section
)
2519 /* The symbol is really a constant. */
2520 fx_offset
-= S_GET_VALUE (fx_subsy
);
2525 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2526 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2527 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2528 segment_name (add_symbol_segment
),
2529 S_GET_NAME (fx_subsy
),
2530 segment_name (sub_symbol_segment
));
2536 && !S_IS_WEAK (fx_addsy
))
2538 if (add_symbol_segment
== seg
2541 value
+= S_GET_VALUE (fx_addsy
);
2542 value
-= md_pcrel_from_section (fixP
, seg
);
2544 fixP
->fx_pcrel
= FALSE
;
2546 else if (add_symbol_segment
== absolute_section
)
2548 value
= fixP
->fx_offset
;
2549 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2551 fixP
->fx_pcrel
= FALSE
;
2556 fixP
->fx_done
= TRUE
;
2561 && ((S_IS_DEFINED (fx_addsy
)
2562 && S_GET_SEGMENT (fx_addsy
) != seg
)
2563 || S_IS_WEAK (fx_addsy
)))
2564 value
+= md_pcrel_from_section (fixP
, seg
);
2566 switch (fixP
->fx_r_type
)
2568 case BFD_RELOC_ARC_32_ME
:
2569 /* This is a pc-relative value in a LIMM. Adjust it to the
2570 address of the instruction not to the address of the
2571 LIMM. Note: it is not anylonger valid this afirmation as
2572 the linker consider ARC_PC32 a fixup to entire 64 bit
2574 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2577 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2579 case BFD_RELOC_ARC_PC32
:
2580 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2583 if ((int) fixP
->fx_r_type
< 0)
2584 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2590 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2591 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2592 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2593 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2597 /* Now check for TLS relocations. */
2598 reloc
= fixP
->fx_r_type
;
2601 case BFD_RELOC_ARC_TLS_DTPOFF
:
2602 case BFD_RELOC_ARC_TLS_LE_32
:
2606 case BFD_RELOC_ARC_TLS_GD_GOT
:
2607 case BFD_RELOC_ARC_TLS_IE_GOT
:
2608 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2611 case BFD_RELOC_ARC_TLS_GD_LD
:
2612 gas_assert (!fixP
->fx_offset
);
2615 = (S_GET_VALUE (fixP
->fx_subsy
)
2616 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2617 fixP
->fx_subsy
= NULL
;
2619 case BFD_RELOC_ARC_TLS_GD_CALL
:
2620 /* These two relocs are there just to allow ld to change the tls
2621 model for this symbol, by patching the code. The offset -
2622 and scale, if any - will be installed by the linker. */
2623 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2626 case BFD_RELOC_ARC_TLS_LE_S9
:
2627 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2628 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2640 /* Addjust the value if we have a constant. */
2643 /* For hosts with longs bigger than 32-bits make sure that the top
2644 bits of a 32-bit negative value read in by the parser are set,
2645 so that the correct comparisons are made. */
2646 if (value
& 0x80000000)
2647 value
|= (-1L << 31);
2649 reloc
= fixP
->fx_r_type
;
2657 case BFD_RELOC_ARC_32_PCREL
:
2658 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2661 case BFD_RELOC_ARC_GOTPC32
:
2662 /* I cannot fix an GOTPC relocation because I need to relax it
2663 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2664 as_bad (_("Unsupported operation on reloc"));
2667 case BFD_RELOC_ARC_TLS_DTPOFF
:
2668 case BFD_RELOC_ARC_TLS_LE_32
:
2669 gas_assert (!fixP
->fx_addsy
);
2670 gas_assert (!fixP
->fx_subsy
);
2672 case BFD_RELOC_ARC_GOTOFF
:
2673 case BFD_RELOC_ARC_32_ME
:
2674 case BFD_RELOC_ARC_PC32
:
2675 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2678 case BFD_RELOC_ARC_PLT32
:
2679 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2682 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2683 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2686 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2687 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2690 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2691 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2694 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2695 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2697 case BFD_RELOC_ARC_S25W_PCREL
:
2698 case BFD_RELOC_ARC_S21W_PCREL
:
2699 case BFD_RELOC_ARC_S21H_PCREL
:
2700 case BFD_RELOC_ARC_S25H_PCREL
:
2701 case BFD_RELOC_ARC_S13_PCREL
:
2703 operand
= find_operand_for_reloc (reloc
);
2704 gas_assert (operand
);
2709 if ((int) fixP
->fx_r_type
>= 0)
2710 as_fatal (_("unhandled relocation type %s"),
2711 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2713 /* The rest of these fixups needs to be completely resolved as
2715 if (fixP
->fx_addsy
!= 0
2716 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2718 _("non-absolute expression in constant field"));
2720 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2721 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
2726 if (target_big_endian
)
2728 switch (fixP
->fx_size
)
2731 insn
= bfd_getb32 (fixpos
);
2734 insn
= bfd_getb16 (fixpos
);
2737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2738 _("unknown fixup size"));
2744 switch (fixP
->fx_size
)
2747 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
2750 insn
= bfd_getl16 (fixpos
);
2753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2754 _("unknown fixup size"));
2758 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
2759 fixP
->fx_file
, fixP
->fx_line
);
2761 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
2764 /* Prepare machine-dependent frags for relaxation.
2766 Called just before relaxation starts. Any symbol that is now undefined
2767 will not become defined.
2769 Return the correct fr_subtype in the frag.
2771 Return the initial "guess for fr_var" to caller. The guess for fr_var
2772 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2773 or fr_var contributes to our returned value.
2775 Although it may not be explicit in the frag, pretend
2776 fr_var starts with a value. */
2779 md_estimate_size_before_relax (fragS
*fragP
,
2784 /* If the symbol is not located within the same section AND it's not
2785 an absolute section, use the maximum. OR if the symbol is a
2786 constant AND the insn is by nature not pc-rel, use the maximum.
2787 OR if the symbol is being equated against another symbol, use the
2788 maximum. OR if the symbol is weak use the maximum. */
2789 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
2790 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2791 || (symbol_constant_p (fragP
->fr_symbol
)
2792 && !fragP
->tc_frag_data
.pcrel
)
2793 || symbol_equated_p (fragP
->fr_symbol
)
2794 || S_IS_WEAK (fragP
->fr_symbol
))
2796 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
2797 ++fragP
->fr_subtype
;
2800 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
2801 fragP
->fr_var
= growth
;
2803 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2804 fragP
->fr_file
, fragP
->fr_line
, growth
);
2809 /* Translate internal representation of relocation info to BFD target
2813 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
2817 bfd_reloc_code_real_type code
;
2819 reloc
= (arelent
*) xmalloc (sizeof (* reloc
));
2820 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2821 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
2822 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2824 /* Make sure none of our internal relocations make it this far.
2825 They'd better have been fully resolved by this point. */
2826 gas_assert ((int) fixP
->fx_r_type
> 0);
2828 code
= fixP
->fx_r_type
;
2830 /* if we have something like add gp, pcl,
2831 _GLOBAL_OFFSET_TABLE_@gotpc. */
2832 if (code
== BFD_RELOC_ARC_GOTPC32
2834 && fixP
->fx_addsy
== GOT_symbol
)
2835 code
= BFD_RELOC_ARC_GOTPC
;
2837 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2838 if (reloc
->howto
== NULL
)
2840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2841 _("cannot represent `%s' relocation in object file"),
2842 bfd_get_reloc_code_name (code
));
2846 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
2847 as_fatal (_("internal error? cannot generate `%s' relocation"),
2848 bfd_get_reloc_code_name (code
));
2850 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
2852 if (code
== BFD_RELOC_ARC_TLS_DTPOFF
2853 || code
== BFD_RELOC_ARC_TLS_DTPOFF_S9
)
2856 = fixP
->fx_subsy
? symbol_get_bfdsym (fixP
->fx_subsy
) : NULL
;
2857 /* We just want to store a 24 bit index, but we have to wait
2858 till after write_contents has been called via
2859 bfd_map_over_sections before we can get the index from
2860 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2861 function is elf32-arc.c has to pick up the slack.
2862 Unfortunately, this leads to problems with hosts that have
2863 pointers wider than long (bfd_vma). There would be various
2864 ways to handle this, all error-prone :-( */
2865 reloc
->addend
= (bfd_vma
) sym
;
2866 if ((asymbol
*) reloc
->addend
!= sym
)
2868 as_bad ("Can't store pointer\n");
2873 reloc
->addend
= fixP
->fx_offset
;
2878 /* Perform post-processing of machine-dependent frags after relaxation.
2879 Called after relaxation is finished.
2880 In: Address of frag.
2881 fr_type == rs_machine_dependent.
2882 fr_subtype is what the address relaxed to.
2884 Out: Any fixS:s and constants are set up. */
2887 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
2888 segT segment ATTRIBUTE_UNUSED
,
2891 const relax_typeS
*table_entry
;
2893 const struct arc_opcode
*opcode
;
2894 struct arc_insn insn
;
2896 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
2898 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
2899 dest
= fragP
->fr_literal
+ fix
;
2900 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
2902 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
2903 fragP
->fr_file
, fragP
->fr_line
,
2904 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
2906 if (fragP
->fr_subtype
<= 0
2907 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
2908 as_fatal (_("no relaxation found for this instruction."));
2910 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
2912 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
2913 relax_arg
->nflg
, &insn
);
2915 apply_fixups (&insn
, fragP
, fix
);
2917 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
2918 gas_assert (table_entry
->rlx_length
== size
);
2919 emit_insn0 (&insn
, dest
, TRUE
);
2921 fragP
->fr_fix
+= table_entry
->rlx_length
;
2925 /* We have no need to default values of symbols. We could catch
2926 register names here, but that is handled by inserting them all in
2927 the symbol table to begin with. */
2930 md_undefined_symbol (char *name
)
2932 /* The arc abi demands that a GOT[0] should be referencible as
2933 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
2934 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
2936 && (*(name
+1) == 'G')
2937 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
2939 && (*(name
+1) == 'D')
2940 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
2944 if (symbol_find (name
))
2945 as_bad ("GOT already in symbol table");
2947 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
2948 (valueT
) 0, &zero_address_frag
);
2955 /* Turn a string in input_line_pointer into a floating point constant
2956 of type type, and store the appropriate bytes in *litP. The number
2957 of LITTLENUMS emitted is stored in *sizeP. An error message is
2958 returned, or NULL on OK. */
2961 md_atof (int type
, char *litP
, int *sizeP
)
2963 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
2966 /* Called for any expression that can not be recognized. When the
2967 function is called, `input_line_pointer' will point to the start of
2971 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
2973 char *p
= input_line_pointer
;
2976 input_line_pointer
++;
2977 expressionP
->X_op
= O_symbol
;
2978 expression (expressionP
);
2982 /* This function is called from the function 'expression', it attempts
2983 to parse special names (in our case register names). It fills in
2984 the expression with the identified register. It returns TRUE if
2985 it is a register and FALSE otherwise. */
2988 arc_parse_name (const char *name
,
2989 struct expressionS
*e
)
2993 if (!assembling_insn
)
2996 /* Handle only registers. */
2997 if (e
->X_op
!= O_absent
)
3000 sym
= hash_find (arc_reg_hash
, name
);
3003 e
->X_op
= O_register
;
3004 e
->X_add_number
= S_GET_VALUE (sym
);
3011 Invocation line includes a switch not recognized by the base assembler.
3012 See if it's a processor-specific option.
3014 New options (supported) are:
3016 -mcpu=<cpu name> Assemble for selected processor
3017 -EB/-mbig-endian Big-endian
3018 -EL/-mlittle-endian Little-endian
3019 -mrelax Enable relaxation
3021 The following CPU names are recognized:
3022 arc700, av2em, av2hs. */
3025 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3031 return md_parse_option (OPTION_MCPU
, "arc600");
3034 return md_parse_option (OPTION_MCPU
, "arc700");
3037 return md_parse_option (OPTION_MCPU
, "arcem");
3040 return md_parse_option (OPTION_MCPU
, "archs");
3044 arc_select_cpu (arg
);
3045 mach_type_specified_p
= 1;
3050 arc_target_format
= "elf32-bigarc";
3051 byte_order
= BIG_ENDIAN
;
3055 arc_target_format
= "elf32-littlearc";
3056 byte_order
= LITTLE_ENDIAN
;
3060 /* This option has an effect only on ARC EM. */
3061 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3062 arc_features
|= ARC_CD
;
3064 as_warn (_("Code density option invalid for selected CPU"));
3068 relaxation_state
= 1;
3071 case OPTION_USER_MODE
:
3072 case OPTION_LD_EXT_MASK
:
3075 case OPTION_BARREL_SHIFT
:
3076 case OPTION_MIN_MAX
:
3081 /* Dummy options are accepted but have no effect. */
3085 arc_features
|= ARC_SPFP
;
3089 arc_features
|= ARC_DPFP
;
3092 case OPTION_XMAC_D16
:
3093 case OPTION_XMAC_24
:
3094 case OPTION_DSP_PACKA
:
3097 case OPTION_TELEPHONY
:
3098 case OPTION_XYMEMORY
:
3102 /* Dummy options are accepted but have no effect. */
3106 /* This option has an effect only on ARC EM. */
3107 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3108 arc_features
|= ARC_FPUDA
;
3110 as_warn (_("FPUDA invalid for selected CPU"));
3121 md_show_usage (FILE *stream
)
3123 fprintf (stream
, _("ARC-specific assembler options:\n"));
3125 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3127 " -mcode-density\t enable code density option for ARC EM\n");
3129 fprintf (stream
, _("\
3130 -EB assemble code for a big-endian cpu\n"));
3131 fprintf (stream
, _("\
3132 -EL assemble code for a little-endian cpu\n"));
3133 fprintf (stream
, _("\
3134 -mrelax Enable relaxation\n"));
3138 /* Find the proper relocation for the given opcode. */
3140 static extended_bfd_reloc_code_real_type
3141 find_reloc (const char *name
,
3142 const char *opcodename
,
3143 const struct arc_flags
*pflags
,
3145 extended_bfd_reloc_code_real_type reloc
)
3149 bfd_boolean found_flag
, tmp
;
3150 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3152 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3154 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3156 /* Find the entry. */
3157 if (strcmp (name
, r
->name
))
3159 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3166 unsigned * psflg
= (unsigned *)r
->flags
;
3170 for (j
= 0; j
< nflg
; j
++)
3171 if (!strcmp (pflags
[j
].name
,
3172 arc_flag_operands
[*psflg
].name
))
3193 if (reloc
!= r
->oldreloc
)
3200 if (ret
== BFD_RELOC_UNUSED
)
3201 as_bad (_("Unable to find %s relocation for instruction %s"),
3206 /* All the symbol types that are allowed to be used for
3210 may_relax_expr (expressionS tok
)
3212 /* Check if we have unrelaxable relocs. */
3237 /* Checks if flags are in line with relaxable insn. */
3240 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3241 const struct arc_flags
*pflags
,
3244 unsigned flag_class
,
3249 const struct arc_flag_operand
*flag_opand
;
3250 int i
, counttrue
= 0;
3252 /* Iterate through flags classes. */
3253 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3255 /* Iterate through flags in flag class. */
3256 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3259 flag_opand
= &arc_flag_operands
[flag
];
3260 /* Iterate through flags in ins to compare. */
3261 for (i
= 0; i
< nflgs
; ++i
)
3263 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3274 /* If counttrue == nflgs, then all flags have been found. */
3275 return (counttrue
== nflgs
? TRUE
: FALSE
);
3278 /* Checks if operands are in line with relaxable insn. */
3281 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3282 const expressionS
*tok
,
3285 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3288 while (*operand
!= EMPTY
)
3290 const expressionS
*epr
= &tok
[i
];
3292 if (i
!= 0 && i
>= ntok
)
3298 if (!(epr
->X_op
== O_multiply
3299 || epr
->X_op
== O_divide
3300 || epr
->X_op
== O_modulus
3301 || epr
->X_op
== O_add
3302 || epr
->X_op
== O_subtract
3303 || epr
->X_op
== O_symbol
))
3309 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3313 if (epr
->X_op
!= O_register
)
3318 if (epr
->X_op
!= O_register
)
3321 switch (epr
->X_add_number
)
3323 case 0: case 1: case 2: case 3:
3324 case 12: case 13: case 14: case 15:
3331 case REGISTER_NO_GP
:
3332 if ((epr
->X_op
!= O_register
)
3333 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3338 if (epr
->X_op
!= O_bracket
)
3343 /* Don't understand, bail out. */
3349 operand
= &ins
->operands
[i
];
3352 return (i
== ntok
? TRUE
: FALSE
);
3355 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3358 relax_insn_p (const struct arc_opcode
*opcode
,
3359 const expressionS
*tok
,
3361 const struct arc_flags
*pflags
,
3365 bfd_boolean rv
= FALSE
;
3367 /* Check the relaxation table. */
3368 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3370 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3372 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3373 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3374 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3375 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3378 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3379 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3380 sizeof (expressionS
) * ntok
);
3381 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3382 sizeof (struct arc_flags
) * nflg
);
3383 frag_now
->tc_frag_data
.nflg
= nflg
;
3384 frag_now
->tc_frag_data
.ntok
= ntok
;
3392 /* Turn an opcode description and a set of arguments into
3393 an instruction and a fixup. */
3396 assemble_insn (const struct arc_opcode
*opcode
,
3397 const expressionS
*tok
,
3399 const struct arc_flags
*pflags
,
3401 struct arc_insn
*insn
)
3403 const expressionS
*reloc_exp
= NULL
;
3405 const unsigned char *argidx
;
3408 unsigned char pcrel
= 0;
3409 bfd_boolean needGOTSymbol
;
3410 bfd_boolean has_delay_slot
= FALSE
;
3411 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3413 memset (insn
, 0, sizeof (*insn
));
3414 image
= opcode
->opcode
;
3416 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3417 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3420 /* Handle operands. */
3421 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3423 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3424 const expressionS
*t
= (const expressionS
*) 0;
3426 if ((operand
->flags
& ARC_OPERAND_FAKE
)
3427 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
3430 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3432 /* Duplicate operand, already inserted. */
3444 /* Regardless if we have a reloc or not mark the instruction
3445 limm if it is the case. */
3446 if (operand
->flags
& ARC_OPERAND_LIMM
)
3447 insn
->has_limm
= TRUE
;
3452 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3457 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3459 if (operand
->flags
& ARC_OPERAND_LIMM
)
3460 insn
->limm
= t
->X_add_number
;
3464 /* Ignore brackets. */
3468 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3472 /* Maybe register range. */
3473 if ((t
->X_add_number
== 0)
3474 && contains_register (t
->X_add_symbol
)
3475 && contains_register (t
->X_op_symbol
))
3479 regs
= get_register (t
->X_add_symbol
);
3481 regs
|= get_register (t
->X_op_symbol
);
3482 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3487 /* This operand needs a relocation. */
3488 needGOTSymbol
= FALSE
;
3493 if (opcode
->class == JUMP
)
3494 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3495 _("Unable to use @plt relocatio for insn %s"),
3497 needGOTSymbol
= TRUE
;
3498 reloc
= find_reloc ("plt", opcode
->name
,
3500 operand
->default_reloc
);
3505 needGOTSymbol
= TRUE
;
3506 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3509 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3510 if (ARC_SHORT (opcode
->mask
) || opcode
->class == JUMP
)
3511 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3512 _("Unable to use @pcl relocation for insn %s"),
3516 reloc
= find_reloc ("sda", opcode
->name
,
3518 operand
->default_reloc
);
3522 needGOTSymbol
= TRUE
;
3527 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3530 case O_tpoff9
: /*FIXME! Check for the conditionality of
3532 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3534 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3538 /* Just consider the default relocation. */
3539 reloc
= operand
->default_reloc
;
3543 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3544 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3551 /* sanity checks. */
3552 reloc_howto_type
*reloc_howto
3553 = bfd_reloc_type_lookup (stdoutput
,
3554 (bfd_reloc_code_real_type
) reloc
);
3555 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3556 if (reloc_howto
->rightshift
)
3557 reloc_bitsize
-= reloc_howto
->rightshift
;
3558 if (reloc_bitsize
!= operand
->bits
)
3560 as_bad (_("invalid relocation %s for field"),
3561 bfd_get_reloc_code_name (reloc
));
3566 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3567 as_fatal (_("too many fixups"));
3569 struct arc_fixup
*fixup
;
3570 fixup
= &insn
->fixups
[insn
->nfixups
++];
3572 fixup
->reloc
= reloc
;
3573 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3574 fixup
->pcrel
= pcrel
;
3575 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3582 for (i
= 0; i
< nflg
; i
++)
3584 const struct arc_flag_operand
*flg_operand
=
3585 &arc_flag_operands
[pflags
[i
].code
];
3587 /* Check if the instruction has a delay slot. */
3588 if (!strcmp (flg_operand
->name
, "d"))
3589 has_delay_slot
= TRUE
;
3591 /* There is an exceptional case when we cannot insert a flag
3592 just as it is. The .T flag must be handled in relation with
3593 the relative address. */
3594 if (!strcmp (flg_operand
->name
, "t")
3595 || !strcmp (flg_operand
->name
, "nt"))
3597 unsigned bitYoperand
= 0;
3598 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3599 if (!strcmp (flg_operand
->name
, "t"))
3600 if (!strcmp (opcode
->name
, "bbit0")
3601 || !strcmp (opcode
->name
, "bbit1"))
3602 bitYoperand
= arc_NToperand
;
3604 bitYoperand
= arc_Toperand
;
3606 if (!strcmp (opcode
->name
, "bbit0")
3607 || !strcmp (opcode
->name
, "bbit1"))
3608 bitYoperand
= arc_Toperand
;
3610 bitYoperand
= arc_NToperand
;
3612 gas_assert (reloc_exp
!= NULL
);
3613 if (reloc_exp
->X_op
== O_constant
)
3615 /* Check if we have a constant and solved it
3617 offsetT val
= reloc_exp
->X_add_number
;
3618 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3623 struct arc_fixup
*fixup
;
3625 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3626 as_fatal (_("too many fixups"));
3628 fixup
= &insn
->fixups
[insn
->nfixups
++];
3629 fixup
->exp
= *reloc_exp
;
3630 fixup
->reloc
= -bitYoperand
;
3631 fixup
->pcrel
= pcrel
;
3632 fixup
->islong
= FALSE
;
3636 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3637 << flg_operand
->shift
;
3640 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3642 /* Short instruction? */
3643 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
3647 /* Update last insn status. */
3648 arc_last_insns
[1] = arc_last_insns
[0];
3649 arc_last_insns
[0].opcode
= opcode
;
3650 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3651 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3653 /* Check if the current instruction is legally used. */
3654 if (arc_last_insns
[1].has_delay_slot
3655 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3656 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3657 _("A jump/branch instruction in delay slot."));
3661 arc_handle_align (fragS
* fragP
)
3663 if ((fragP
)->fr_type
== rs_align_code
)
3665 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3666 valueT count
= ((fragP
)->fr_next
->fr_address
3667 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3669 (fragP
)->fr_var
= 2;
3671 if (count
& 1)/* Padding in the gap till the next 2-byte
3672 boundary with 0s. */
3677 /* Writing nop_s. */
3678 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
3682 /* Here we decide which fixups can be adjusted to make them relative
3683 to the beginning of the section instead of the symbol. Basically
3684 we need to make sure that the dynamic relocations are done
3685 correctly, so in some cases we force the original symbol to be
3689 tc_arc_fix_adjustable (fixS
*fixP
)
3692 /* Prevent all adjustments to global symbols. */
3693 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
3695 if (S_IS_WEAK (fixP
->fx_addsy
))
3698 /* Adjust_reloc_syms doesn't know about the GOT. */
3699 switch (fixP
->fx_r_type
)
3701 case BFD_RELOC_ARC_GOTPC32
:
3702 case BFD_RELOC_ARC_PLT32
:
3703 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3704 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3705 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3706 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3716 /* Compute the reloc type of an expression EXP. */
3719 arc_check_reloc (expressionS
*exp
,
3720 bfd_reloc_code_real_type
*r_type_p
)
3722 if (*r_type_p
== BFD_RELOC_32
3723 && exp
->X_op
== O_subtract
3724 && exp
->X_op_symbol
!= NULL
3725 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
3726 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
3730 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3733 arc_cons_fix_new (fragS
*frag
,
3737 bfd_reloc_code_real_type r_type
)
3739 r_type
= BFD_RELOC_UNUSED
;
3744 r_type
= BFD_RELOC_8
;
3748 r_type
= BFD_RELOC_16
;
3752 r_type
= BFD_RELOC_24
;
3756 r_type
= BFD_RELOC_32
;
3757 arc_check_reloc (exp
, &r_type
);
3761 r_type
= BFD_RELOC_64
;
3765 as_bad (_("unsupported BFD relocation size %u"), size
);
3766 r_type
= BFD_RELOC_UNUSED
;
3769 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
3772 /* The actual routine that checks the ZOL conditions. */
3775 check_zol (symbolS
*s
)
3777 switch (arc_mach_type
)
3779 case bfd_mach_arc_arcv2
:
3780 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3783 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
3784 || arc_last_insns
[1].has_delay_slot
)
3785 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3789 case bfd_mach_arc_arc600
:
3791 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
3792 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3795 if (arc_last_insns
[0].has_limm
3796 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3797 as_bad (_("A jump instruction with long immediate detected at the \
3798 end of the ZOL label @%s"), S_GET_NAME (s
));
3801 case bfd_mach_arc_nps400
:
3802 case bfd_mach_arc_arc700
:
3803 if (arc_last_insns
[0].has_delay_slot
)
3804 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3813 /* If ZOL end check the last two instruction for illegals. */
3815 arc_frob_label (symbolS
* sym
)
3817 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
3820 dwarf2_emit_label (sym
);
3823 /* Used because generic relaxation assumes a pc-rel value whilst we
3824 also relax instructions that use an absolute value resolved out of
3825 relative values (if that makes any sense). An example: 'add r1,
3826 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3827 but if they're in the same section we can subtract the section
3828 offset relocation which ends up in a resolved value. So if @.L2 is
3829 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3830 .text + 0x40 = 0x10. */
3832 arc_pcrel_adjust (fragS
*fragP
)
3834 if (!fragP
->tc_frag_data
.pcrel
)
3835 return fragP
->fr_address
+ fragP
->fr_fix
;
3840 /* Initialize the DWARF-2 unwind information for this procedure. */
3843 tc_arc_frame_initial_instructions (void)
3845 /* Stack pointer is register 28. */
3846 cfi_add_CFA_def_cfa_register (28);
3850 tc_arc_regname_to_dw2regnum (char *regname
)
3854 sym
= hash_find (arc_reg_hash
, regname
);
3856 return S_GET_VALUE (sym
);