1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
33 /* Defines section. */
35 #define MAX_INSN_FIXUPS 2
36 #define MAX_CONSTR_STR 20
37 #define FRAG_MAX_GROWTH 8
40 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42 # define pr_debug(fmt, args...)
45 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
46 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
47 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
48 (SUB_OPCODE (x) == 0x28))
50 /* Equal to MAX_PRECISION in atof-ieee.c. */
51 #define MAX_LITTLENUMS 6
53 /* Enum used to enumerate the relaxable ins operands. */
58 REGISTER_S
, /* Register for short instruction(s). */
59 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
60 REGISTER_DUP
, /* Duplication of previous operand of type register. */
94 #define regno(x) ((x) & 0x3F)
95 #define is_ir_num(x) (((x) & ~0x3F) == 0)
96 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
97 #define is_spfp_p(op) (((sc) == SPX))
98 #define is_dpfp_p(op) (((sc) == DPX))
99 #define is_fpuda_p(op) (((sc) == DPA))
100 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
101 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
103 /* Generic assembler global variables which must be defined by all
106 /* Characters which always start a comment. */
107 const char comment_chars
[] = "#;";
109 /* Characters which start a comment at the beginning of a line. */
110 const char line_comment_chars
[] = "#";
112 /* Characters which may be used to separate multiple commands on a
114 const char line_separator_chars
[] = "`";
116 /* Characters which are used to indicate an exponent in a floating
118 const char EXP_CHARS
[] = "eE";
120 /* Chars that mean this number is a floating point constant
121 As in 0f12.456 or 0d1.2345e12. */
122 const char FLT_CHARS
[] = "rRsSfFdD";
125 extern int target_big_endian
;
126 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
127 static int byte_order
= DEFAULT_BYTE_ORDER
;
129 /* By default relaxation is disabled. */
130 static int relaxation_state
= 0;
132 extern int arc_get_mach (char *);
134 /* Forward declarations. */
135 static void arc_lcomm (int);
136 static void arc_option (int);
137 static void arc_extra_reloc (int);
140 const pseudo_typeS md_pseudo_table
[] =
142 /* Make sure that .word is 32 bits. */
145 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
146 { "lcomm", arc_lcomm
, 0 },
147 { "lcommon", arc_lcomm
, 0 },
148 { "cpu", arc_option
, 0 },
150 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
151 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
156 const char *md_shortopts
= "";
160 OPTION_EB
= OPTION_MD_BASE
,
173 /* The following options are deprecated and provided here only for
174 compatibility reasons. */
200 struct option md_longopts
[] =
202 { "EB", no_argument
, NULL
, OPTION_EB
},
203 { "EL", no_argument
, NULL
, OPTION_EL
},
204 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
205 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
206 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
207 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
208 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
209 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
210 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
211 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
212 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
213 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
215 /* The following options are deprecated and provided here only for
216 compatibility reasons. */
217 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
218 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
219 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
220 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
221 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
222 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
223 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
224 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
225 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
226 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
227 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
228 { "mea", no_argument
, NULL
, OPTION_EA
},
229 { "mEA", no_argument
, NULL
, OPTION_EA
},
230 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
231 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
232 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
233 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
234 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
235 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
236 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
237 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
238 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
239 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
240 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
241 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
242 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
243 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
244 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
245 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
246 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
247 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
248 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
249 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
250 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
251 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
252 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
253 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
254 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
255 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
257 { NULL
, no_argument
, NULL
, 0 }
260 size_t md_longopts_size
= sizeof (md_longopts
);
262 /* Local data and data types. */
264 /* Used since new relocation types are introduced in this
265 file (DUMMY_RELOC_LITUSE_*). */
266 typedef int extended_bfd_reloc_code_real_type
;
272 extended_bfd_reloc_code_real_type reloc
;
274 /* index into arc_operands. */
275 unsigned int opindex
;
277 /* PC-relative, used by internals fixups. */
280 /* TRUE if this fixup is for LIMM operand. */
288 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
290 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
292 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
294 bfd_boolean relax
; /* Boolean value: TRUE if needs
298 /* Structure to hold any last two instructions. */
299 static struct arc_last_insn
301 /* Saved instruction opcode. */
302 const struct arc_opcode
*opcode
;
304 /* Boolean value: TRUE if current insn is short. */
305 bfd_boolean has_limm
;
307 /* Boolean value: TRUE if current insn has delay slot. */
308 bfd_boolean has_delay_slot
;
311 /* Structure to hold an entry in ARC_OPCODE_HASH. */
312 struct arc_opcode_hash_entry
314 /* The number of pointers in the OPCODE list. */
317 /* Points to a list of opcode pointers. */
318 const struct arc_opcode
**opcode
;
321 /* Forward declaration. */
322 static void assemble_insn
323 (const struct arc_opcode
*, const expressionS
*, int,
324 const struct arc_flags
*, int, struct arc_insn
*);
326 /* The cpu for which we are generating code. */
327 static unsigned arc_target
;
328 static const char *arc_target_name
;
329 static unsigned arc_features
;
331 /* The default architecture. */
332 static int arc_mach_type
;
334 /* Non-zero if the cpu type has been explicitly specified. */
335 static int mach_type_specified_p
= 0;
337 /* The hash table of instruction opcodes. */
338 static struct hash_control
*arc_opcode_hash
;
340 /* The hash table of register symbols. */
341 static struct hash_control
*arc_reg_hash
;
343 /* A table of CPU names and opcode sets. */
344 static const struct cpu_type
354 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
355 E_ARC_MACH_ARC600
, 0x00},
356 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
357 E_ARC_MACH_ARC700
, 0x00},
358 { "nps400", ARC_OPCODE_ARC700
| ARC_OPCODE_NPS400
, bfd_mach_arc_nps400
,
359 E_ARC_MACH_NPS400
, 0x00},
360 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
361 EF_ARC_CPU_ARCV2EM
, ARC_CD
},
362 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
363 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
367 /* Used by the arc_reloc_op table. Order is important. */
368 #define O_gotoff O_md1 /* @gotoff relocation. */
369 #define O_gotpc O_md2 /* @gotpc relocation. */
370 #define O_plt O_md3 /* @plt relocation. */
371 #define O_sda O_md4 /* @sda relocation. */
372 #define O_pcl O_md5 /* @pcl relocation. */
373 #define O_tlsgd O_md6 /* @tlsgd relocation. */
374 #define O_tlsie O_md7 /* @tlsie relocation. */
375 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
376 #define O_tpoff O_md9 /* @tpoff relocation. */
377 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
378 #define O_dtpoff O_md11 /* @dtpoff relocation. */
379 #define O_last O_dtpoff
381 /* Used to define a bracket as operand in tokens. */
382 #define O_bracket O_md32
384 /* Dummy relocation, to be sorted out. */
385 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
387 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
389 /* A table to map the spelling of a relocation operand into an appropriate
390 bfd_reloc_code_real_type type. The table is assumed to be ordered such
391 that op-O_literal indexes into it. */
392 #define ARC_RELOC_TABLE(op) \
393 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
395 : (int) (op) - (int) O_gotoff) ])
397 #define DEF(NAME, RELOC, REQ) \
398 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
400 static const struct arc_reloc_op_tag
402 /* String to lookup. */
404 /* Size of the string. */
406 /* Which operator to use. */
408 extended_bfd_reloc_code_real_type reloc
;
409 /* Allows complex relocation expression like identifier@reloc +
411 unsigned int complex_expr
: 1;
415 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
416 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
417 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
418 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
419 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
420 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
421 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
422 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
423 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
424 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
425 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 0),
428 static const int arc_num_reloc_op
429 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
431 /* Structure for relaxable instruction that have to be swapped with a
432 smaller alternative instruction. */
433 struct arc_relaxable_ins
435 /* Mnemonic that should be checked. */
436 const char *mnemonic_r
;
438 /* Operands that should be checked.
439 Indexes of operands from operand array. */
440 enum rlx_operand_type operands
[6];
442 /* Flags that should be checked. */
443 unsigned flag_classes
[5];
445 /* Mnemonic (smaller) alternative to be used later for relaxation. */
446 const char *mnemonic_alt
;
448 /* Index of operand that generic relaxation has to check. */
451 /* Base subtype index used. */
452 enum arc_rlx_types subtype
;
455 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
456 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
457 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
461 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
462 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
463 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
468 /* ARC relaxation table. */
469 const relax_typeS md_relax_table
[] =
476 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL
),
477 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
481 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B
),
482 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
487 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6
),
488 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM
),
489 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
491 /* LD_S a, [b, u7] ->
492 LD<zz><.x><.aa><.di> a, [b, s9] ->
493 LD<zz><.x><.aa><.di> a, [b, limm] */
494 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9
),
495 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM
),
496 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE
),
501 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12
),
502 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM
),
503 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
507 SUB<.f> a, b, limm. */
508 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6
),
509 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM
),
510 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
512 /* MPY<.f> a, b, u6 ->
513 MPY<.f> a, b, limm. */
514 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM
),
515 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
517 /* MOV<.f><.cc> b, u6 ->
518 MOV<.f><.cc> b, limm. */
519 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM
),
520 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
522 /* ADD<.f><.cc> b, b, u6 ->
523 ADD<.f><.cc> b, b, limm. */
524 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM
),
525 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
528 /* Order of this table's entries matters! */
529 const struct arc_relaxable_ins arc_relaxable_insns
[] =
531 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
532 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
533 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
534 2, ARC_RLX_ADD_RRU6
},
535 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
537 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
539 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
540 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
541 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
542 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
543 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
544 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
545 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
546 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
548 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
550 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
554 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
556 /* Flags to set in the elf header. */
557 static flagword arc_eflag
= 0x00;
559 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
560 symbolS
* GOT_symbol
= 0;
562 /* Set to TRUE when we assemble instructions. */
563 static bfd_boolean assembling_insn
= FALSE
;
565 /* Functions implementation. */
567 /* Return a pointer to the first entry in ARC_OPCODE_HASH that matches
568 NAME, or NULL if there are no matching entries. */
570 static const struct arc_opcode
*
571 arc_find_opcode (const char *name
)
573 const struct arc_opcode_hash_entry
*entry
;
574 const struct arc_opcode
*opcode
;
576 entry
= hash_find (arc_opcode_hash
, name
);
579 if (entry
->count
> 1)
580 as_fatal (_("unable to lookup `%s', too many opcode chains"),
582 opcode
= *entry
->opcode
;
590 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
591 is encoded as 'middle-endian' for a little-endian target. FIXME!
592 this function is used for regular 4 byte instructions as well. */
595 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
599 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
600 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
604 md_number_to_chars (buf
, val
, n
);
608 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
609 the relevant static global variables. */
612 arc_select_cpu (const char *arg
)
617 for (i
= 0; cpu_types
[i
].name
; ++i
)
619 if (!strcasecmp (cpu_types
[i
].name
, arg
))
621 arc_target
= cpu_types
[i
].flags
;
622 arc_target_name
= cpu_types
[i
].name
;
623 arc_features
= cpu_types
[i
].features
;
624 arc_mach_type
= cpu_types
[i
].mach
;
625 cpu_flags
= cpu_types
[i
].eflags
;
630 if (!cpu_types
[i
].name
)
631 as_fatal (_("unknown architecture: %s\n"), arg
);
632 gas_assert (cpu_flags
!= 0);
633 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
636 /* Here ends all the ARCompact extension instruction assembling
640 arc_extra_reloc (int r_type
)
643 symbolS
*sym
, *lab
= NULL
;
645 if (*input_line_pointer
== '@')
646 input_line_pointer
++;
647 c
= get_symbol_name (&sym_name
);
648 sym
= symbol_find_or_make (sym_name
);
649 restore_line_pointer (c
);
650 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
652 ++input_line_pointer
;
654 c
= get_symbol_name (&lab_name
);
655 lab
= symbol_find_or_make (lab_name
);
656 restore_line_pointer (c
);
659 /* These relocations exist as a mechanism for the compiler to tell the
660 linker how to patch the code if the tls model is optimised. However,
661 the relocation itself does not require any space within the assembler
662 fragment, and so we pass a size of 0.
664 The lines that generate these relocations look like this:
666 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
668 The '.tls_gd_ld @.tdata' is processed first and generates the
669 additional relocation, while the 'bl __tls_get_addr@plt' is processed
670 second and generates the additional branch.
672 It is possible that the additional relocation generated by the
673 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
674 while the 'bl __tls_get_addr@plt' will be generated as the first thing
675 in the next fragment. This will be fine; both relocations will still
676 appear to be at the same address in the generated object file.
677 However, this only works as the additional relocation is generated
678 with size of 0 bytes. */
680 = fix_new (frag_now
, /* Which frag? */
681 frag_now_fix (), /* Where in that frag? */
682 0, /* size: 1, 2, or 4 usually. */
683 sym
, /* X_add_symbol. */
684 0, /* X_add_number. */
685 FALSE
, /* TRUE if PC-relative relocation. */
686 r_type
/* Relocation type. */);
687 fixP
->fx_subsy
= lab
;
691 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
692 symbolS
*symbolP
, addressT size
)
697 if (*input_line_pointer
== ',')
699 align
= parse_align (1);
701 if (align
== (addressT
) -1)
716 bss_alloc (symbolP
, size
, align
);
717 S_CLEAR_EXTERNAL (symbolP
);
723 arc_lcomm (int ignore
)
725 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
728 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
731 /* Select the cpu we're assembling for. */
734 arc_option (int ignore ATTRIBUTE_UNUSED
)
740 c
= get_symbol_name (&cpu
);
741 mach
= arc_get_mach (cpu
);
746 if (!mach_type_specified_p
)
748 if ((!strcmp ("ARC600", cpu
))
749 || (!strcmp ("ARC601", cpu
))
750 || (!strcmp ("A6", cpu
)))
752 md_parse_option (OPTION_MCPU
, "arc600");
754 else if ((!strcmp ("ARC700", cpu
))
755 || (!strcmp ("A7", cpu
)))
757 md_parse_option (OPTION_MCPU
, "arc700");
759 else if (!strcmp ("EM", cpu
))
761 md_parse_option (OPTION_MCPU
, "arcem");
763 else if (!strcmp ("HS", cpu
))
765 md_parse_option (OPTION_MCPU
, "archs");
768 as_fatal (_("could not find the architecture"));
770 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
771 as_fatal (_("could not set architecture and machine"));
774 if (arc_mach_type
!= mach
)
775 as_warn (_("Command-line value overrides \".cpu\" directive"));
777 restore_line_pointer (c
);
778 demand_empty_rest_of_line ();
782 restore_line_pointer (c
);
783 as_bad (_("invalid identifier for \".cpu\""));
784 ignore_rest_of_line ();
787 /* Smartly print an expression. */
790 debug_exp (expressionS
*t
)
792 const char *name ATTRIBUTE_UNUSED
;
793 const char *namemd ATTRIBUTE_UNUSED
;
795 pr_debug ("debug_exp: ");
799 default: name
= "unknown"; break;
800 case O_illegal
: name
= "O_illegal"; break;
801 case O_absent
: name
= "O_absent"; break;
802 case O_constant
: name
= "O_constant"; break;
803 case O_symbol
: name
= "O_symbol"; break;
804 case O_symbol_rva
: name
= "O_symbol_rva"; break;
805 case O_register
: name
= "O_register"; break;
806 case O_big
: name
= "O_big"; break;
807 case O_uminus
: name
= "O_uminus"; break;
808 case O_bit_not
: name
= "O_bit_not"; break;
809 case O_logical_not
: name
= "O_logical_not"; break;
810 case O_multiply
: name
= "O_multiply"; break;
811 case O_divide
: name
= "O_divide"; break;
812 case O_modulus
: name
= "O_modulus"; break;
813 case O_left_shift
: name
= "O_left_shift"; break;
814 case O_right_shift
: name
= "O_right_shift"; break;
815 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
816 case O_bit_or_not
: name
= "O_bit_or_not"; break;
817 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
818 case O_bit_and
: name
= "O_bit_and"; break;
819 case O_add
: name
= "O_add"; break;
820 case O_subtract
: name
= "O_subtract"; break;
821 case O_eq
: name
= "O_eq"; break;
822 case O_ne
: name
= "O_ne"; break;
823 case O_lt
: name
= "O_lt"; break;
824 case O_le
: name
= "O_le"; break;
825 case O_ge
: name
= "O_ge"; break;
826 case O_gt
: name
= "O_gt"; break;
827 case O_logical_and
: name
= "O_logical_and"; break;
828 case O_logical_or
: name
= "O_logical_or"; break;
829 case O_index
: name
= "O_index"; break;
830 case O_bracket
: name
= "O_bracket"; break;
835 default: namemd
= "unknown"; break;
836 case O_gotoff
: namemd
= "O_gotoff"; break;
837 case O_gotpc
: namemd
= "O_gotpc"; break;
838 case O_plt
: namemd
= "O_plt"; break;
839 case O_sda
: namemd
= "O_sda"; break;
840 case O_pcl
: namemd
= "O_pcl"; break;
841 case O_tlsgd
: namemd
= "O_tlsgd"; break;
842 case O_tlsie
: namemd
= "O_tlsie"; break;
843 case O_tpoff9
: namemd
= "O_tpoff9"; break;
844 case O_tpoff
: namemd
= "O_tpoff"; break;
845 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
846 case O_dtpoff
: namemd
= "O_dtpoff"; break;
849 pr_debug ("%s (%s, %s, %d, %s)", name
,
850 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
851 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
852 (int) t
->X_add_number
,
853 (t
->X_md
) ? namemd
: "--");
858 /* Parse the arguments to an opcode. */
861 tokenize_arguments (char *str
,
865 char *old_input_line_pointer
;
866 bfd_boolean saw_comma
= FALSE
;
867 bfd_boolean saw_arg
= FALSE
;
872 const struct arc_reloc_op_tag
*r
;
876 memset (tok
, 0, sizeof (*tok
) * ntok
);
878 /* Save and restore input_line_pointer around this function. */
879 old_input_line_pointer
= input_line_pointer
;
880 input_line_pointer
= str
;
882 while (*input_line_pointer
)
885 switch (*input_line_pointer
)
891 input_line_pointer
++;
892 if (saw_comma
|| !saw_arg
)
899 ++input_line_pointer
;
903 tok
->X_op
= O_bracket
;
910 input_line_pointer
++;
914 tok
->X_op
= O_bracket
;
920 /* We have labels, function names and relocations, all
921 starting with @ symbol. Sort them out. */
922 if (saw_arg
&& !saw_comma
)
926 tok
->X_op
= O_symbol
;
927 tok
->X_md
= O_absent
;
929 if (*input_line_pointer
!= '@')
930 goto normalsymbol
; /* This is not a relocation. */
934 /* A relocation opernad has the following form
935 @identifier@relocation_type. The identifier is already
937 if (tok
->X_op
!= O_symbol
)
939 as_bad (_("No valid label relocation operand"));
943 /* Parse @relocation_type. */
944 input_line_pointer
++;
945 c
= get_symbol_name (&reloc_name
);
946 len
= input_line_pointer
- reloc_name
;
949 as_bad (_("No relocation operand"));
953 /* Go through known relocation and try to find a match. */
954 r
= &arc_reloc_op
[0];
955 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
957 && memcmp (reloc_name
, r
->name
, len
) == 0)
961 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
965 *input_line_pointer
= c
;
966 SKIP_WHITESPACE_AFTER_NAME ();
967 /* Extra check for TLS: base. */
968 if (*input_line_pointer
== '@')
971 if (tok
->X_op_symbol
!= NULL
972 || tok
->X_op
!= O_symbol
)
974 as_bad (_("Unable to parse TLS base: %s"),
978 input_line_pointer
++;
980 c
= get_symbol_name (&sym_name
);
981 base
= symbol_find_or_make (sym_name
);
982 tok
->X_op
= O_subtract
;
983 tok
->X_op_symbol
= base
;
984 restore_line_pointer (c
);
985 tmpE
.X_add_number
= 0;
987 else if ((*input_line_pointer
!= '+')
988 && (*input_line_pointer
!= '-'))
990 tmpE
.X_add_number
= 0;
994 /* Parse the constant of a complex relocation expression
995 like @identifier@reloc +/- const. */
996 if (! r
->complex_expr
)
998 as_bad (_("@%s is not a complex relocation."), r
->name
);
1002 if (tmpE
.X_op
!= O_constant
)
1004 as_bad (_("Bad expression: @%s + %s."),
1005 r
->name
, input_line_pointer
);
1011 tok
->X_add_number
= tmpE
.X_add_number
;
1022 /* Can be a register. */
1023 ++input_line_pointer
;
1027 if (saw_arg
&& !saw_comma
)
1030 tok
->X_op
= O_absent
;
1031 tok
->X_md
= O_absent
;
1034 /* Legacy: There are cases when we have
1035 identifier@relocation_type, if it is the case parse the
1036 relocation type as well. */
1037 if (*input_line_pointer
== '@')
1043 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1055 if (saw_comma
|| brk_lvl
)
1057 input_line_pointer
= old_input_line_pointer
;
1063 as_bad (_("Brackets in operand field incorrect"));
1065 as_bad (_("extra comma"));
1067 as_bad (_("missing argument"));
1069 as_bad (_("missing comma or colon"));
1070 input_line_pointer
= old_input_line_pointer
;
1074 /* Parse the flags to a structure. */
1077 tokenize_flags (const char *str
,
1078 struct arc_flags flags
[],
1081 char *old_input_line_pointer
;
1082 bfd_boolean saw_flg
= FALSE
;
1083 bfd_boolean saw_dot
= FALSE
;
1087 memset (flags
, 0, sizeof (*flags
) * nflg
);
1089 /* Save and restore input_line_pointer around this function. */
1090 old_input_line_pointer
= input_line_pointer
;
1091 input_line_pointer
= (char *) str
;
1093 while (*input_line_pointer
)
1095 switch (*input_line_pointer
)
1102 input_line_pointer
++;
1110 if (saw_flg
&& !saw_dot
)
1113 if (num_flags
>= nflg
)
1116 flgnamelen
= strspn (input_line_pointer
,
1117 "abcdefghijklmnopqrstuvwxyz0123456789");
1118 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1121 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1123 input_line_pointer
+= flgnamelen
;
1133 input_line_pointer
= old_input_line_pointer
;
1138 as_bad (_("extra dot"));
1140 as_bad (_("unrecognized flag"));
1142 as_bad (_("failed to parse flags"));
1143 input_line_pointer
= old_input_line_pointer
;
1147 /* Apply the fixups in order. */
1150 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1154 for (i
= 0; i
< insn
->nfixups
; i
++)
1156 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1157 int size
, pcrel
, offset
= 0;
1159 /* FIXME! the reloc size is wrong in the BFD file.
1160 When it is fixed please delete me. */
1161 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1164 offset
= (insn
->short_insn
) ? 2 : 4;
1166 /* Some fixups are only used internally, thus no howto. */
1167 if ((int) fixup
->reloc
== 0)
1168 as_fatal (_("Unhandled reloc type"));
1170 if ((int) fixup
->reloc
< 0)
1172 /* FIXME! the reloc size is wrong in the BFD file.
1173 When it is fixed please enable me.
1174 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1175 pcrel
= fixup
->pcrel
;
1179 reloc_howto_type
*reloc_howto
=
1180 bfd_reloc_type_lookup (stdoutput
,
1181 (bfd_reloc_code_real_type
) fixup
->reloc
);
1182 gas_assert (reloc_howto
);
1184 /* FIXME! the reloc size is wrong in the BFD file.
1185 When it is fixed please enable me.
1186 size = bfd_get_reloc_size (reloc_howto); */
1187 pcrel
= reloc_howto
->pc_relative
;
1190 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1192 fragP
->fr_file
, fragP
->fr_line
,
1193 (fixup
->reloc
< 0) ? "Internal" :
1194 bfd_get_reloc_code_name (fixup
->reloc
),
1197 fix_new_exp (fragP
, fix
+ offset
,
1198 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1200 /* Check for ZOLs, and update symbol info if any. */
1201 if (LP_INSN (insn
->insn
))
1203 gas_assert (fixup
->exp
.X_add_symbol
);
1204 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1209 /* Actually output an instruction with its fixup. */
1212 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1216 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1217 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1218 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1220 /* Write out the instruction. */
1221 if (insn
->short_insn
)
1227 md_number_to_chars (f
, insn
->insn
, 2);
1228 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1229 dwarf2_emit_insn (6);
1235 md_number_to_chars (f
, insn
->insn
, 2);
1236 dwarf2_emit_insn (2);
1245 md_number_to_chars_midend (f
, insn
->insn
, 4);
1246 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1247 dwarf2_emit_insn (8);
1253 md_number_to_chars_midend (f
, insn
->insn
, 4);
1254 dwarf2_emit_insn (4);
1259 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1263 emit_insn1 (struct arc_insn
*insn
)
1265 /* How frag_var's args are currently configured:
1266 - rs_machine_dependent, to dictate it's a relaxation frag.
1267 - FRAG_MAX_GROWTH, maximum size of instruction
1268 - 0, variable size that might grow...unused by generic relaxation.
1269 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1270 - s, opand expression.
1271 - 0, offset but it's unused.
1272 - 0, opcode but it's unused. */
1273 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1274 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1276 if (frag_room () < FRAG_MAX_GROWTH
)
1278 /* Handle differently when frag literal memory is exhausted.
1279 This is used because when there's not enough memory left in
1280 the current frag, a new frag is created and the information
1281 we put into frag_now->tc_frag_data is disregarded. */
1283 struct arc_relax_type relax_info_copy
;
1284 relax_substateT subtype
= frag_now
->fr_subtype
;
1286 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1287 sizeof (struct arc_relax_type
));
1289 frag_wane (frag_now
);
1290 frag_grow (FRAG_MAX_GROWTH
);
1292 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1293 sizeof (struct arc_relax_type
));
1295 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1299 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1300 frag_now
->fr_subtype
, s
, 0, 0);
1304 emit_insn (struct arc_insn
*insn
)
1309 emit_insn0 (insn
, NULL
, FALSE
);
1312 /* Check whether a symbol involves a register. */
1315 contains_register (symbolS
*sym
)
1319 expressionS
*ex
= symbol_get_value_expression (sym
);
1321 return ((O_register
== ex
->X_op
)
1322 && !contains_register (ex
->X_add_symbol
)
1323 && !contains_register (ex
->X_op_symbol
));
1329 /* Returns the register number within a symbol. */
1332 get_register (symbolS
*sym
)
1334 if (!contains_register (sym
))
1337 expressionS
*ex
= symbol_get_value_expression (sym
);
1338 return regno (ex
->X_add_number
);
1341 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1342 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1345 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1352 case BFD_RELOC_ARC_SDA_LDST
:
1353 case BFD_RELOC_ARC_SDA_LDST1
:
1354 case BFD_RELOC_ARC_SDA_LDST2
:
1355 case BFD_RELOC_ARC_SDA16_LD
:
1356 case BFD_RELOC_ARC_SDA16_LD1
:
1357 case BFD_RELOC_ARC_SDA16_LD2
:
1358 case BFD_RELOC_ARC_SDA16_ST2
:
1359 case BFD_RELOC_ARC_SDA32_ME
:
1366 /* Allocates a tok entry. */
1369 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1371 if (ntok
> MAX_INSN_ARGS
- 2)
1372 return 0; /* No space left. */
1375 return 0; /* Incorect args. */
1377 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1380 return 1; /* Success. */
1381 return allocate_tok (tok
, ntok
- 1, cidx
);
1384 /* Check if an particular ARC feature is enabled. */
1387 check_cpu_feature (insn_subclass_t sc
)
1389 if (!(arc_features
& ARC_CD
)
1390 && is_code_density_p (sc
))
1393 if (!(arc_features
& ARC_SPFP
)
1397 if (!(arc_features
& ARC_DPFP
)
1401 if (!(arc_features
& ARC_FPUDA
)
1408 /* Search forward through all variants of an opcode looking for a
1411 static const struct arc_opcode
*
1412 find_opcode_match (const struct arc_opcode
*first_opcode
,
1415 struct arc_flags
*first_pflag
,
1419 const struct arc_opcode
*opcode
= first_opcode
;
1421 int got_cpu_match
= 0;
1422 expressionS bktok
[MAX_INSN_ARGS
];
1426 memset (&emptyE
, 0, sizeof (emptyE
));
1427 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1432 const unsigned char *opidx
;
1433 const unsigned char *flgidx
;
1434 int tokidx
= 0, lnflg
, i
;
1435 const expressionS
*t
= &emptyE
;
1437 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1438 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1440 /* Don't match opcodes that don't exist on this
1442 if (!(opcode
->cpu
& arc_target
))
1445 if (!check_cpu_feature (opcode
->subclass
))
1451 /* Check the operands. */
1452 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1454 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1456 /* Only take input from real operands. */
1457 if ((operand
->flags
& ARC_OPERAND_FAKE
)
1458 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
1461 /* When we expect input, make sure we have it. */
1465 /* Match operand type with expression type. */
1466 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1468 case ARC_OPERAND_IR
:
1469 /* Check to be a register. */
1470 if ((tok
[tokidx
].X_op
!= O_register
1471 || !is_ir_num (tok
[tokidx
].X_add_number
))
1472 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1475 /* If expect duplicate, make sure it is duplicate. */
1476 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1478 /* Check for duplicate. */
1479 if (t
->X_op
!= O_register
1480 || !is_ir_num (t
->X_add_number
)
1481 || (regno (t
->X_add_number
) !=
1482 regno (tok
[tokidx
].X_add_number
)))
1486 /* Special handling? */
1487 if (operand
->insert
)
1489 const char *errmsg
= NULL
;
1490 (*operand
->insert
)(0,
1491 regno (tok
[tokidx
].X_add_number
),
1495 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1497 /* Missing argument, create one. */
1498 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1501 tok
[tokidx
].X_op
= O_absent
;
1512 case ARC_OPERAND_BRAKET
:
1513 /* Check if bracket is also in opcode table as
1515 if (tok
[tokidx
].X_op
!= O_bracket
)
1519 case ARC_OPERAND_LIMM
:
1520 case ARC_OPERAND_SIGNED
:
1521 case ARC_OPERAND_UNSIGNED
:
1522 switch (tok
[tokidx
].X_op
)
1530 /* Got an (too) early bracket, check if it is an
1531 ignored operand. N.B. This procedure works only
1532 when bracket is the last operand! */
1533 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1535 /* Insert the missing operand. */
1536 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1539 tok
[tokidx
].X_op
= O_absent
;
1547 const struct arc_aux_reg
*auxr
;
1550 if (opcode
->class != AUXREG
)
1552 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1555 auxr
= &arc_aux_regs
[0];
1556 for (j
= 0; j
< arc_num_aux_regs
; j
++, auxr
++)
1557 if (len
== auxr
->length
1558 && strcasecmp (auxr
->name
, p
) == 0
1559 && ((auxr
->subclass
== NONE
)
1560 || check_cpu_feature (auxr
->subclass
)))
1562 /* We modify the token array here, safe in the
1563 knowledge, that if this was the wrong choice
1564 then the original contents will be restored
1566 tok
[tokidx
].X_op
= O_constant
;
1567 tok
[tokidx
].X_add_number
= auxr
->address
;
1571 if (tok
[tokidx
].X_op
!= O_constant
)
1576 /* Check the range. */
1577 if (operand
->bits
!= 32
1578 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1580 offsetT min
, max
, val
;
1581 val
= tok
[tokidx
].X_add_number
;
1583 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1585 max
= (1 << (operand
->bits
- 1)) - 1;
1586 min
= -(1 << (operand
->bits
- 1));
1590 max
= (1 << operand
->bits
) - 1;
1594 if (val
< min
|| val
> max
)
1597 /* Check alignmets. */
1598 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1602 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1606 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1608 if (operand
->insert
)
1610 const char *errmsg
= NULL
;
1611 (*operand
->insert
)(0,
1612 tok
[tokidx
].X_add_number
,
1623 /* Check if it is register range. */
1624 if ((tok
[tokidx
].X_add_number
== 0)
1625 && contains_register (tok
[tokidx
].X_add_symbol
)
1626 && contains_register (tok
[tokidx
].X_op_symbol
))
1630 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1632 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1633 if (operand
->insert
)
1635 const char *errmsg
= NULL
;
1636 (*operand
->insert
)(0,
1648 if (operand
->default_reloc
== 0)
1649 goto match_failed
; /* The operand needs relocation. */
1651 /* Relocs requiring long immediate. FIXME! make it
1652 generic and move it to a function. */
1653 switch (tok
[tokidx
].X_md
)
1662 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1665 if (!generic_reloc_p (operand
->default_reloc
))
1672 /* If expect duplicate, make sure it is duplicate. */
1673 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1675 if (t
->X_op
== O_illegal
1676 || t
->X_op
== O_absent
1677 || t
->X_op
== O_register
1678 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1685 /* Everything else should have been fake. */
1693 /* Setup ready for flag parsing. */
1695 for (i
= 0; i
< nflgs
; i
++)
1696 first_pflag
[i
].code
= 0;
1698 /* Check the flags. Iterate over the valid flag classes. */
1699 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1701 /* Get a valid flag class. */
1702 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1703 const unsigned *flgopridx
;
1706 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1708 const struct arc_flag_operand
*flg_operand
;
1709 struct arc_flags
*pflag
= first_pflag
;
1711 flg_operand
= &arc_flag_operands
[*flgopridx
];
1712 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1714 /* Match against the parsed flags. */
1715 if (!strcmp (flg_operand
->name
, pflag
->name
))
1717 if (pflag
->code
!= 0)
1720 pflag
->code
= *flgopridx
;
1722 break; /* goto next flag class and parsed flag. */
1727 if (cl_flags
->class == F_CLASS_REQUIRED
&& cl_matches
== 0)
1729 if (cl_flags
->class == F_CLASS_OPTIONAL
&& cl_matches
> 1)
1732 /* Did I check all the parsed flags? */
1737 /* Possible match -- did we use all of our input? */
1747 /* Restore the original parameters. */
1748 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1751 while (++opcode
- arc_opcodes
< (int) arc_num_opcodes
1752 && !strcmp (opcode
->name
, first_opcode
->name
));
1755 *pcpumatch
= got_cpu_match
;
1760 /* Swap operand tokens. */
1763 swap_operand (expressionS
*operand_array
,
1765 unsigned destination
)
1767 expressionS cpy_operand
;
1768 expressionS
*src_operand
;
1769 expressionS
*dst_operand
;
1772 if (source
== destination
)
1775 src_operand
= &operand_array
[source
];
1776 dst_operand
= &operand_array
[destination
];
1777 size
= sizeof (expressionS
);
1779 /* Make copy of operand to swap with and swap. */
1780 memcpy (&cpy_operand
, dst_operand
, size
);
1781 memcpy (dst_operand
, src_operand
, size
);
1782 memcpy (src_operand
, &cpy_operand
, size
);
1785 /* Check if *op matches *tok type.
1786 Returns FALSE if they don't match, TRUE if they match. */
1789 pseudo_operand_match (const expressionS
*tok
,
1790 const struct arc_operand_operation
*op
)
1792 offsetT min
, max
, val
;
1794 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
1800 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
1802 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
1804 val
= tok
->X_add_number
+ op
->count
;
1805 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
1807 max
= (1 << (operand_real
->bits
- 1)) - 1;
1808 min
= -(1 << (operand_real
->bits
- 1));
1812 max
= (1 << operand_real
->bits
) - 1;
1815 if (min
<= val
&& val
<= max
)
1821 /* Handle all symbols as long immediates or signed 9. */
1822 if (operand_real
->flags
& ARC_OPERAND_LIMM
||
1823 ((operand_real
->flags
& ARC_OPERAND_SIGNED
) && operand_real
->bits
== 9))
1828 if (operand_real
->flags
& ARC_OPERAND_IR
)
1833 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
1844 /* Find pseudo instruction in array. */
1846 static const struct arc_pseudo_insn
*
1847 find_pseudo_insn (const char *opname
,
1849 const expressionS
*tok
)
1851 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
1852 const struct arc_operand_operation
*op
;
1856 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
1858 pseudo_insn
= &arc_pseudo_insns
[i
];
1859 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
1861 op
= pseudo_insn
->operand
;
1862 for (j
= 0; j
< ntok
; ++j
)
1863 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
1866 /* Found the right instruction. */
1874 /* Assumes the expressionS *tok is of sufficient size. */
1876 static const struct arc_opcode
*
1877 find_special_case_pseudo (const char *opname
,
1881 struct arc_flags
*pflags
)
1883 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
1884 const struct arc_operand_operation
*operand_pseudo
;
1885 const struct arc_operand
*operand_real
;
1887 char construct_operand
[MAX_CONSTR_STR
];
1889 /* Find whether opname is in pseudo instruction array. */
1890 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
1892 if (pseudo_insn
== NULL
)
1895 /* Handle flag, Limited to one flag at the moment. */
1896 if (pseudo_insn
->flag_r
!= NULL
)
1897 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
1898 MAX_INSN_FLGS
- *nflgs
);
1900 /* Handle operand operations. */
1901 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
1903 operand_pseudo
= &pseudo_insn
->operand
[i
];
1904 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
1906 if (operand_real
->flags
& ARC_OPERAND_BRAKET
&&
1907 !operand_pseudo
->needs_insert
)
1910 /* Has to be inserted (i.e. this token does not exist yet). */
1911 if (operand_pseudo
->needs_insert
)
1913 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
1915 tok
[i
].X_op
= O_bracket
;
1920 /* Check if operand is a register or constant and handle it
1922 if (operand_real
->flags
& ARC_OPERAND_IR
)
1923 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
1924 operand_pseudo
->count
);
1926 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
1927 operand_pseudo
->count
);
1929 tokenize_arguments (construct_operand
, &tok
[i
], 1);
1933 else if (operand_pseudo
->count
)
1935 /* Operand number has to be adjusted accordingly (by operand
1937 switch (tok
[i
].X_op
)
1940 tok
[i
].X_add_number
+= operand_pseudo
->count
;
1953 /* Swap operands if necessary. Only supports one swap at the
1955 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
1957 operand_pseudo
= &pseudo_insn
->operand
[i
];
1959 if (operand_pseudo
->swap_operand_idx
== i
)
1962 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
1964 /* Prevent a swap back later by breaking out. */
1968 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
1971 static const struct arc_opcode
*
1972 find_special_case_flag (const char *opname
,
1974 struct arc_flags
*pflags
)
1978 unsigned flag_idx
, flag_arr_idx
;
1979 size_t flaglen
, oplen
;
1980 const struct arc_flag_special
*arc_flag_special_opcode
;
1981 const struct arc_opcode
*opcode
;
1983 /* Search for special case instruction. */
1984 for (i
= 0; i
< arc_num_flag_special
; i
++)
1986 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
1987 oplen
= strlen (arc_flag_special_opcode
->name
);
1989 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
1992 /* Found a potential special case instruction, now test for
1994 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
1996 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
1998 break; /* End of array, nothing found. */
2000 flagnm
= arc_flag_operands
[flag_idx
].name
;
2001 flaglen
= strlen (flagnm
);
2002 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2004 opcode
= arc_find_opcode (arc_flag_special_opcode
->name
);
2006 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2008 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2009 pflags
[*nflgs
].name
[flaglen
] = '\0';
2018 /* Used to find special case opcode. */
2020 static const struct arc_opcode
*
2021 find_special_case (const char *opname
,
2023 struct arc_flags
*pflags
,
2027 const struct arc_opcode
*opcode
;
2029 opcode
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2032 opcode
= find_special_case_flag (opname
, nflgs
, pflags
);
2037 /* Given an opcode name, pre-tockenized set of argumenst and the
2038 opcode flags, take it all the way through emission. */
2041 assemble_tokens (const char *opname
,
2044 struct arc_flags
*pflags
,
2047 bfd_boolean found_something
= FALSE
;
2048 const struct arc_opcode
*opcode
;
2051 /* Search opcodes. */
2052 opcode
= arc_find_opcode (opname
);
2054 /* Couldn't find opcode conventional way, try special cases. */
2056 opcode
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2060 pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n",
2061 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
2064 found_something
= TRUE
;
2065 opcode
= find_opcode_match (opcode
, tok
, &ntok
, pflags
, nflgs
, &cpumatch
);
2068 struct arc_insn insn
;
2069 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2075 if (found_something
)
2078 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2080 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2084 as_bad (_("unknown opcode '%s'"), opname
);
2087 /* The public interface to the instruction assembler. */
2090 md_assemble (char *str
)
2093 expressionS tok
[MAX_INSN_ARGS
];
2096 struct arc_flags flags
[MAX_INSN_FLGS
];
2098 /* Split off the opcode. */
2099 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2100 opname
= xmalloc (opnamelen
+ 1);
2101 memcpy (opname
, str
, opnamelen
);
2102 opname
[opnamelen
] = '\0';
2104 /* Signalize we are assmbling the instructions. */
2105 assembling_insn
= TRUE
;
2107 /* Tokenize the flags. */
2108 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2110 as_bad (_("syntax error"));
2114 /* Scan up to the end of the mnemonic which must end in space or end
2117 for (; *str
!= '\0'; str
++)
2121 /* Tokenize the rest of the line. */
2122 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2124 as_bad (_("syntax error"));
2128 /* Finish it off. */
2129 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2130 assembling_insn
= FALSE
;
2133 /* Callback to insert a register into the hash table. */
2136 declare_register (const char *name
, int number
)
2139 symbolS
*regS
= symbol_create (name
, reg_section
,
2140 number
, &zero_address_frag
);
2142 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2144 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2148 /* Construct symbols for each of the general registers. */
2151 declare_register_set (void)
2154 for (i
= 0; i
< 64; ++i
)
2158 sprintf (name
, "r%d", i
);
2159 declare_register (name
, i
);
2160 if ((i
& 0x01) == 0)
2162 sprintf (name
, "r%dr%d", i
, i
+1);
2163 declare_register (name
, i
);
2168 /* Port-specific assembler initialization. This function is called
2169 once, at assembler startup time. */
2176 if (!mach_type_specified_p
)
2177 arc_select_cpu ("arc700");
2179 /* The endianness can be chosen "at the factory". */
2180 target_big_endian
= byte_order
== BIG_ENDIAN
;
2182 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2183 as_warn (_("could not set architecture and machine"));
2185 /* Set elf header flags. */
2186 bfd_set_private_flags (stdoutput
, arc_eflag
);
2188 /* Set up a hash table for the instructions. */
2189 arc_opcode_hash
= hash_new ();
2190 if (arc_opcode_hash
== NULL
)
2191 as_fatal (_("Virtual memory exhausted"));
2193 /* Initialize the hash table with the insns. */
2194 for (i
= 0; i
< arc_num_opcodes
;)
2196 const char *name
, *retval
;
2197 struct arc_opcode_hash_entry
*entry
;
2199 name
= arc_opcodes
[i
].name
;
2201 entry
= hash_find (arc_opcode_hash
, name
);
2204 entry
= xmalloc (sizeof (*entry
));
2206 entry
->opcode
= NULL
;
2208 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
2210 as_fatal (_("internal error: can't hash opcode '%s': %s"),
2214 entry
->opcode
= xrealloc (entry
->opcode
,
2215 sizeof (const struct arc_opcode
*)
2216 * entry
->count
+ 1);
2217 entry
->opcode
[entry
->count
] = &arc_opcodes
[i
];
2220 while (++i
< arc_num_opcodes
2221 && (arc_opcodes
[i
].name
== name
2222 || !strcmp (arc_opcodes
[i
].name
, name
)))
2226 /* Register declaration. */
2227 arc_reg_hash
= hash_new ();
2228 if (arc_reg_hash
== NULL
)
2229 as_fatal (_("Virtual memory exhausted"));
2231 declare_register_set ();
2232 declare_register ("gp", 26);
2233 declare_register ("fp", 27);
2234 declare_register ("sp", 28);
2235 declare_register ("ilink", 29);
2236 declare_register ("ilink1", 29);
2237 declare_register ("ilink2", 30);
2238 declare_register ("blink", 31);
2240 declare_register ("mlo", 57);
2241 declare_register ("mmid", 58);
2242 declare_register ("mhi", 59);
2244 declare_register ("acc1", 56);
2245 declare_register ("acc2", 57);
2247 declare_register ("lp_count", 60);
2248 declare_register ("pcl", 63);
2250 /* Initialize the last instructions. */
2251 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2254 /* Write a value out to the object file, using the appropriate
2258 md_number_to_chars (char *buf
,
2262 if (target_big_endian
)
2263 number_to_chars_bigendian (buf
, val
, n
);
2265 number_to_chars_littleendian (buf
, val
, n
);
2268 /* Round up a section size to the appropriate boundary. */
2271 md_section_align (segT segment
,
2274 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2276 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2279 /* The location from which a PC relative jump should be calculated,
2280 given a PC relative reloc. */
2283 md_pcrel_from_section (fixS
*fixP
,
2286 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2288 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2290 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2291 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2292 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2294 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2296 /* The symbol is undefined (or is defined but not in this section).
2297 Let the linker figure it out. */
2301 if ((int) fixP
->fx_r_type
< 0)
2303 /* These are the "internal" relocations. Align them to
2304 32 bit boundary (PCL), for the moment. */
2309 switch (fixP
->fx_r_type
)
2311 case BFD_RELOC_ARC_PC32
:
2312 /* The hardware calculates relative to the start of the
2313 insn, but this relocation is relative to location of the
2314 LIMM, compensate. The base always needs to be
2315 substracted by 4 as we do not support this type of PCrel
2316 relocation for short instructions. */
2319 case BFD_RELOC_ARC_PLT32
:
2320 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2321 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2322 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2323 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2325 case BFD_RELOC_ARC_S21H_PCREL
:
2326 case BFD_RELOC_ARC_S25H_PCREL
:
2327 case BFD_RELOC_ARC_S13_PCREL
:
2328 case BFD_RELOC_ARC_S21W_PCREL
:
2329 case BFD_RELOC_ARC_S25W_PCREL
:
2333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2334 _("unhandled reloc %s in md_pcrel_from_section"),
2335 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2340 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2341 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2342 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2343 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2348 /* Given a BFD relocation find the coresponding operand. */
2350 static const struct arc_operand
*
2351 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2355 for (i
= 0; i
< arc_num_operands
; i
++)
2356 if (arc_operands
[i
].default_reloc
== reloc
)
2357 return &arc_operands
[i
];
2361 /* Insert an operand value into an instruction. */
2364 insert_operand (unsigned insn
,
2365 const struct arc_operand
*operand
,
2370 offsetT min
= 0, max
= 0;
2372 if (operand
->bits
!= 32
2373 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2374 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2376 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2378 max
= (1 << (operand
->bits
- 1)) - 1;
2379 min
= -(1 << (operand
->bits
- 1));
2383 max
= (1 << operand
->bits
) - 1;
2387 if (val
< min
|| val
> max
)
2388 as_bad_value_out_of_range (_("operand"),
2389 val
, min
, max
, file
, line
);
2392 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2393 min
, val
, max
, insn
);
2395 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2397 as_bad_where (file
, line
,
2398 _("Unaligned operand. Needs to be 32bit aligned"));
2400 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2402 as_bad_where (file
, line
,
2403 _("Unaligned operand. Needs to be 16bit aligned"));
2405 if (operand
->insert
)
2407 const char *errmsg
= NULL
;
2409 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2411 as_warn_where (file
, line
, "%s", errmsg
);
2415 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2417 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2419 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2422 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2427 /* Apply a fixup to the object code. At this point all symbol values
2428 should be fully resolved, and we attempt to completely resolve the
2429 reloc. If we can not do that, we determine the correct reloc code
2430 and put it back in the fixup. To indicate that a fixup has been
2431 eliminated, set fixP->fx_done. */
2434 md_apply_fix (fixS
*fixP
,
2438 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2439 valueT value
= *valP
;
2441 symbolS
*fx_addsy
, *fx_subsy
;
2443 segT add_symbol_segment
= absolute_section
;
2444 segT sub_symbol_segment
= absolute_section
;
2445 const struct arc_operand
*operand
= NULL
;
2446 extended_bfd_reloc_code_real_type reloc
;
2448 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2449 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2450 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2451 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2454 fx_addsy
= fixP
->fx_addsy
;
2455 fx_subsy
= fixP
->fx_subsy
;
2460 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2464 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2465 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2466 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2468 resolve_symbol_value (fx_subsy
);
2469 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2471 if (sub_symbol_segment
== absolute_section
)
2473 /* The symbol is really a constant. */
2474 fx_offset
-= S_GET_VALUE (fx_subsy
);
2479 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2480 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2481 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2482 segment_name (add_symbol_segment
),
2483 S_GET_NAME (fx_subsy
),
2484 segment_name (sub_symbol_segment
));
2490 && !S_IS_WEAK (fx_addsy
))
2492 if (add_symbol_segment
== seg
2495 value
+= S_GET_VALUE (fx_addsy
);
2496 value
-= md_pcrel_from_section (fixP
, seg
);
2498 fixP
->fx_pcrel
= FALSE
;
2500 else if (add_symbol_segment
== absolute_section
)
2502 value
= fixP
->fx_offset
;
2503 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2505 fixP
->fx_pcrel
= FALSE
;
2510 fixP
->fx_done
= TRUE
;
2515 && ((S_IS_DEFINED (fx_addsy
)
2516 && S_GET_SEGMENT (fx_addsy
) != seg
)
2517 || S_IS_WEAK (fx_addsy
)))
2518 value
+= md_pcrel_from_section (fixP
, seg
);
2520 switch (fixP
->fx_r_type
)
2522 case BFD_RELOC_ARC_32_ME
:
2523 /* This is a pc-relative value in a LIMM. Adjust it to the
2524 address of the instruction not to the address of the
2525 LIMM. Note: it is not anylonger valid this afirmation as
2526 the linker consider ARC_PC32 a fixup to entire 64 bit
2528 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2531 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2533 case BFD_RELOC_ARC_PC32
:
2534 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2537 if ((int) fixP
->fx_r_type
< 0)
2538 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2544 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2545 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2546 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2547 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2551 /* Now check for TLS relocations. */
2552 reloc
= fixP
->fx_r_type
;
2555 case BFD_RELOC_ARC_TLS_DTPOFF
:
2556 case BFD_RELOC_ARC_TLS_LE_32
:
2560 case BFD_RELOC_ARC_TLS_GD_GOT
:
2561 case BFD_RELOC_ARC_TLS_IE_GOT
:
2562 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2565 case BFD_RELOC_ARC_TLS_GD_LD
:
2566 gas_assert (!fixP
->fx_offset
);
2569 = (S_GET_VALUE (fixP
->fx_subsy
)
2570 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2571 fixP
->fx_subsy
= NULL
;
2573 case BFD_RELOC_ARC_TLS_GD_CALL
:
2574 /* These two relocs are there just to allow ld to change the tls
2575 model for this symbol, by patching the code. The offset -
2576 and scale, if any - will be installed by the linker. */
2577 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2580 case BFD_RELOC_ARC_TLS_LE_S9
:
2581 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2582 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2594 /* Addjust the value if we have a constant. */
2597 /* For hosts with longs bigger than 32-bits make sure that the top
2598 bits of a 32-bit negative value read in by the parser are set,
2599 so that the correct comparisons are made. */
2600 if (value
& 0x80000000)
2601 value
|= (-1L << 31);
2603 reloc
= fixP
->fx_r_type
;
2611 case BFD_RELOC_ARC_32_PCREL
:
2612 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2615 case BFD_RELOC_ARC_GOTPC32
:
2616 /* I cannot fix an GOTPC relocation because I need to relax it
2617 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2618 as_bad (_("Unsupported operation on reloc"));
2621 case BFD_RELOC_ARC_TLS_DTPOFF
:
2622 case BFD_RELOC_ARC_TLS_LE_32
:
2623 gas_assert (!fixP
->fx_addsy
);
2624 gas_assert (!fixP
->fx_subsy
);
2626 case BFD_RELOC_ARC_GOTOFF
:
2627 case BFD_RELOC_ARC_32_ME
:
2628 case BFD_RELOC_ARC_PC32
:
2629 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2632 case BFD_RELOC_ARC_PLT32
:
2633 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2636 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2637 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2640 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2641 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2644 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2645 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2648 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2649 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2651 case BFD_RELOC_ARC_S25W_PCREL
:
2652 case BFD_RELOC_ARC_S21W_PCREL
:
2653 case BFD_RELOC_ARC_S21H_PCREL
:
2654 case BFD_RELOC_ARC_S25H_PCREL
:
2655 case BFD_RELOC_ARC_S13_PCREL
:
2657 operand
= find_operand_for_reloc (reloc
);
2658 gas_assert (operand
);
2663 if ((int) fixP
->fx_r_type
>= 0)
2664 as_fatal (_("unhandled relocation type %s"),
2665 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2667 /* The rest of these fixups needs to be completely resolved as
2669 if (fixP
->fx_addsy
!= 0
2670 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2672 _("non-absolute expression in constant field"));
2674 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2675 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
2680 if (target_big_endian
)
2682 switch (fixP
->fx_size
)
2685 insn
= bfd_getb32 (fixpos
);
2688 insn
= bfd_getb16 (fixpos
);
2691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2692 _("unknown fixup size"));
2698 switch (fixP
->fx_size
)
2701 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
2704 insn
= bfd_getl16 (fixpos
);
2707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2708 _("unknown fixup size"));
2712 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
2713 fixP
->fx_file
, fixP
->fx_line
);
2715 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
2718 /* Prepare machine-dependent frags for relaxation.
2720 Called just before relaxation starts. Any symbol that is now undefined
2721 will not become defined.
2723 Return the correct fr_subtype in the frag.
2725 Return the initial "guess for fr_var" to caller. The guess for fr_var
2726 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2727 or fr_var contributes to our returned value.
2729 Although it may not be explicit in the frag, pretend
2730 fr_var starts with a value. */
2733 md_estimate_size_before_relax (fragS
*fragP
,
2738 /* If the symbol is not located within the same section AND it's not
2739 an absolute section, use the maximum. OR if the symbol is a
2740 constant AND the insn is by nature not pc-rel, use the maximum.
2741 OR if the symbol is being equated against another symbol, use the
2742 maximum. OR if the symbol is weak use the maximum. */
2743 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
2744 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2745 || (symbol_constant_p (fragP
->fr_symbol
)
2746 && !fragP
->tc_frag_data
.pcrel
)
2747 || symbol_equated_p (fragP
->fr_symbol
)
2748 || S_IS_WEAK (fragP
->fr_symbol
))
2750 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
2751 ++fragP
->fr_subtype
;
2754 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
2755 fragP
->fr_var
= growth
;
2757 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2758 fragP
->fr_file
, fragP
->fr_line
, growth
);
2763 /* Translate internal representation of relocation info to BFD target
2767 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
2771 bfd_reloc_code_real_type code
;
2773 reloc
= (arelent
*) xmalloc (sizeof (* reloc
));
2774 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2775 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
2776 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2778 /* Make sure none of our internal relocations make it this far.
2779 They'd better have been fully resolved by this point. */
2780 gas_assert ((int) fixP
->fx_r_type
> 0);
2782 code
= fixP
->fx_r_type
;
2784 /* if we have something like add gp, pcl,
2785 _GLOBAL_OFFSET_TABLE_@gotpc. */
2786 if (code
== BFD_RELOC_ARC_GOTPC32
2788 && fixP
->fx_addsy
== GOT_symbol
)
2789 code
= BFD_RELOC_ARC_GOTPC
;
2791 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2792 if (reloc
->howto
== NULL
)
2794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2795 _("cannot represent `%s' relocation in object file"),
2796 bfd_get_reloc_code_name (code
));
2800 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
2801 as_fatal (_("internal error? cannot generate `%s' relocation"),
2802 bfd_get_reloc_code_name (code
));
2804 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
2806 if (code
== BFD_RELOC_ARC_TLS_DTPOFF
2807 || code
== BFD_RELOC_ARC_TLS_DTPOFF_S9
)
2810 = fixP
->fx_subsy
? symbol_get_bfdsym (fixP
->fx_subsy
) : NULL
;
2811 /* We just want to store a 24 bit index, but we have to wait
2812 till after write_contents has been called via
2813 bfd_map_over_sections before we can get the index from
2814 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2815 function is elf32-arc.c has to pick up the slack.
2816 Unfortunately, this leads to problems with hosts that have
2817 pointers wider than long (bfd_vma). There would be various
2818 ways to handle this, all error-prone :-( */
2819 reloc
->addend
= (bfd_vma
) sym
;
2820 if ((asymbol
*) reloc
->addend
!= sym
)
2822 as_bad ("Can't store pointer\n");
2827 reloc
->addend
= fixP
->fx_offset
;
2832 /* Perform post-processing of machine-dependent frags after relaxation.
2833 Called after relaxation is finished.
2834 In: Address of frag.
2835 fr_type == rs_machine_dependent.
2836 fr_subtype is what the address relaxed to.
2838 Out: Any fixS:s and constants are set up. */
2841 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
2842 segT segment ATTRIBUTE_UNUSED
,
2845 const relax_typeS
*table_entry
;
2847 const struct arc_opcode
*opcode
;
2848 struct arc_insn insn
;
2850 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
2852 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
2853 dest
= fragP
->fr_literal
+ fix
;
2854 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
2856 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
2857 fragP
->fr_file
, fragP
->fr_line
,
2858 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
2860 if (fragP
->fr_subtype
<= 0
2861 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
2862 as_fatal (_("no relaxation found for this instruction."));
2864 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
2866 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
2867 relax_arg
->nflg
, &insn
);
2869 apply_fixups (&insn
, fragP
, fix
);
2871 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
2872 gas_assert (table_entry
->rlx_length
== size
);
2873 emit_insn0 (&insn
, dest
, TRUE
);
2875 fragP
->fr_fix
+= table_entry
->rlx_length
;
2879 /* We have no need to default values of symbols. We could catch
2880 register names here, but that is handled by inserting them all in
2881 the symbol table to begin with. */
2884 md_undefined_symbol (char *name
)
2886 /* The arc abi demands that a GOT[0] should be referencible as
2887 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
2888 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
2890 && (*(name
+1) == 'G')
2891 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
2893 && (*(name
+1) == 'D')
2894 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
2898 if (symbol_find (name
))
2899 as_bad ("GOT already in symbol table");
2901 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
2902 (valueT
) 0, &zero_address_frag
);
2909 /* Turn a string in input_line_pointer into a floating point constant
2910 of type type, and store the appropriate bytes in *litP. The number
2911 of LITTLENUMS emitted is stored in *sizeP. An error message is
2912 returned, or NULL on OK. */
2915 md_atof (int type
, char *litP
, int *sizeP
)
2917 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
2920 /* Called for any expression that can not be recognized. When the
2921 function is called, `input_line_pointer' will point to the start of
2925 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
2927 char *p
= input_line_pointer
;
2930 input_line_pointer
++;
2931 expressionP
->X_op
= O_symbol
;
2932 expression (expressionP
);
2936 /* This function is called from the function 'expression', it attempts
2937 to parse special names (in our case register names). It fills in
2938 the expression with the identified register. It returns TRUE if
2939 it is a register and FALSE otherwise. */
2942 arc_parse_name (const char *name
,
2943 struct expressionS
*e
)
2947 if (!assembling_insn
)
2950 /* Handle only registers. */
2951 if (e
->X_op
!= O_absent
)
2954 sym
= hash_find (arc_reg_hash
, name
);
2957 e
->X_op
= O_register
;
2958 e
->X_add_number
= S_GET_VALUE (sym
);
2965 Invocation line includes a switch not recognized by the base assembler.
2966 See if it's a processor-specific option.
2968 New options (supported) are:
2970 -mcpu=<cpu name> Assemble for selected processor
2971 -EB/-mbig-endian Big-endian
2972 -EL/-mlittle-endian Little-endian
2973 -mrelax Enable relaxation
2975 The following CPU names are recognized:
2976 arc700, av2em, av2hs. */
2979 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
2985 return md_parse_option (OPTION_MCPU
, "arc600");
2988 return md_parse_option (OPTION_MCPU
, "arc700");
2991 return md_parse_option (OPTION_MCPU
, "arcem");
2994 return md_parse_option (OPTION_MCPU
, "archs");
2998 arc_select_cpu (arg
);
2999 mach_type_specified_p
= 1;
3004 arc_target_format
= "elf32-bigarc";
3005 byte_order
= BIG_ENDIAN
;
3009 arc_target_format
= "elf32-littlearc";
3010 byte_order
= LITTLE_ENDIAN
;
3014 /* This option has an effect only on ARC EM. */
3015 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3016 arc_features
|= ARC_CD
;
3018 as_warn (_("Code density option invalid for selected CPU"));
3022 relaxation_state
= 1;
3025 case OPTION_USER_MODE
:
3026 case OPTION_LD_EXT_MASK
:
3029 case OPTION_BARREL_SHIFT
:
3030 case OPTION_MIN_MAX
:
3035 /* Dummy options are accepted but have no effect. */
3039 arc_features
|= ARC_SPFP
;
3043 arc_features
|= ARC_DPFP
;
3046 case OPTION_XMAC_D16
:
3047 case OPTION_XMAC_24
:
3048 case OPTION_DSP_PACKA
:
3051 case OPTION_TELEPHONY
:
3052 case OPTION_XYMEMORY
:
3056 /* Dummy options are accepted but have no effect. */
3060 /* This option has an effect only on ARC EM. */
3061 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3062 arc_features
|= ARC_FPUDA
;
3064 as_warn (_("FPUDA invalid for selected CPU"));
3075 md_show_usage (FILE *stream
)
3077 fprintf (stream
, _("ARC-specific assembler options:\n"));
3079 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3081 " -mcode-density\t enable code density option for ARC EM\n");
3083 fprintf (stream
, _("\
3084 -EB assemble code for a big-endian cpu\n"));
3085 fprintf (stream
, _("\
3086 -EL assemble code for a little-endian cpu\n"));
3087 fprintf (stream
, _("\
3088 -mrelax Enable relaxation\n"));
3092 /* Find the proper relocation for the given opcode. */
3094 static extended_bfd_reloc_code_real_type
3095 find_reloc (const char *name
,
3096 const char *opcodename
,
3097 const struct arc_flags
*pflags
,
3099 extended_bfd_reloc_code_real_type reloc
)
3103 bfd_boolean found_flag
, tmp
;
3104 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3106 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3108 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3110 /* Find the entry. */
3111 if (strcmp (name
, r
->name
))
3113 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3120 unsigned * psflg
= (unsigned *)r
->flags
;
3124 for (j
= 0; j
< nflg
; j
++)
3125 if (!strcmp (pflags
[j
].name
,
3126 arc_flag_operands
[*psflg
].name
))
3147 if (reloc
!= r
->oldreloc
)
3154 if (ret
== BFD_RELOC_UNUSED
)
3155 as_bad (_("Unable to find %s relocation for instruction %s"),
3160 /* All the symbol types that are allowed to be used for
3164 may_relax_expr (expressionS tok
)
3166 /* Check if we have unrelaxable relocs. */
3191 /* Checks if flags are in line with relaxable insn. */
3194 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3195 const struct arc_flags
*pflags
,
3198 unsigned flag_class
,
3203 const struct arc_flag_operand
*flag_opand
;
3204 int i
, counttrue
= 0;
3206 /* Iterate through flags classes. */
3207 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3209 /* Iterate through flags in flag class. */
3210 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3213 flag_opand
= &arc_flag_operands
[flag
];
3214 /* Iterate through flags in ins to compare. */
3215 for (i
= 0; i
< nflgs
; ++i
)
3217 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3228 /* If counttrue == nflgs, then all flags have been found. */
3229 return (counttrue
== nflgs
? TRUE
: FALSE
);
3232 /* Checks if operands are in line with relaxable insn. */
3235 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3236 const expressionS
*tok
,
3239 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3242 while (*operand
!= EMPTY
)
3244 const expressionS
*epr
= &tok
[i
];
3246 if (i
!= 0 && i
>= ntok
)
3252 if (!(epr
->X_op
== O_multiply
3253 || epr
->X_op
== O_divide
3254 || epr
->X_op
== O_modulus
3255 || epr
->X_op
== O_add
3256 || epr
->X_op
== O_subtract
3257 || epr
->X_op
== O_symbol
))
3263 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3267 if (epr
->X_op
!= O_register
)
3272 if (epr
->X_op
!= O_register
)
3275 switch (epr
->X_add_number
)
3277 case 0: case 1: case 2: case 3:
3278 case 12: case 13: case 14: case 15:
3285 case REGISTER_NO_GP
:
3286 if ((epr
->X_op
!= O_register
)
3287 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3292 if (epr
->X_op
!= O_bracket
)
3297 /* Don't understand, bail out. */
3303 operand
= &ins
->operands
[i
];
3306 return (i
== ntok
? TRUE
: FALSE
);
3309 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3312 relax_insn_p (const struct arc_opcode
*opcode
,
3313 const expressionS
*tok
,
3315 const struct arc_flags
*pflags
,
3319 bfd_boolean rv
= FALSE
;
3321 /* Check the relaxation table. */
3322 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3324 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3326 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3327 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3328 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3329 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3332 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3333 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3334 sizeof (expressionS
) * ntok
);
3335 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3336 sizeof (struct arc_flags
) * nflg
);
3337 frag_now
->tc_frag_data
.nflg
= nflg
;
3338 frag_now
->tc_frag_data
.ntok
= ntok
;
3346 /* Turn an opcode description and a set of arguments into
3347 an instruction and a fixup. */
3350 assemble_insn (const struct arc_opcode
*opcode
,
3351 const expressionS
*tok
,
3353 const struct arc_flags
*pflags
,
3355 struct arc_insn
*insn
)
3357 const expressionS
*reloc_exp
= NULL
;
3359 const unsigned char *argidx
;
3362 unsigned char pcrel
= 0;
3363 bfd_boolean needGOTSymbol
;
3364 bfd_boolean has_delay_slot
= FALSE
;
3365 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3367 memset (insn
, 0, sizeof (*insn
));
3368 image
= opcode
->opcode
;
3370 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3371 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3374 /* Handle operands. */
3375 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3377 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3378 const expressionS
*t
= (const expressionS
*) 0;
3380 if ((operand
->flags
& ARC_OPERAND_FAKE
)
3381 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
3384 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3386 /* Duplicate operand, already inserted. */
3398 /* Regardless if we have a reloc or not mark the instruction
3399 limm if it is the case. */
3400 if (operand
->flags
& ARC_OPERAND_LIMM
)
3401 insn
->has_limm
= TRUE
;
3406 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3411 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3413 if (operand
->flags
& ARC_OPERAND_LIMM
)
3414 insn
->limm
= t
->X_add_number
;
3418 /* Ignore brackets. */
3422 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3426 /* Maybe register range. */
3427 if ((t
->X_add_number
== 0)
3428 && contains_register (t
->X_add_symbol
)
3429 && contains_register (t
->X_op_symbol
))
3433 regs
= get_register (t
->X_add_symbol
);
3435 regs
|= get_register (t
->X_op_symbol
);
3436 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3441 /* This operand needs a relocation. */
3442 needGOTSymbol
= FALSE
;
3447 if (opcode
->class == JUMP
)
3448 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3449 _("Unable to use @plt relocatio for insn %s"),
3451 needGOTSymbol
= TRUE
;
3452 reloc
= find_reloc ("plt", opcode
->name
,
3454 operand
->default_reloc
);
3459 needGOTSymbol
= TRUE
;
3460 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3463 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3464 if (ARC_SHORT (opcode
->mask
) || opcode
->class == JUMP
)
3465 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3466 _("Unable to use @pcl relocation for insn %s"),
3470 reloc
= find_reloc ("sda", opcode
->name
,
3472 operand
->default_reloc
);
3476 needGOTSymbol
= TRUE
;
3481 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3484 case O_tpoff9
: /*FIXME! Check for the conditionality of
3486 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3488 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3492 /* Just consider the default relocation. */
3493 reloc
= operand
->default_reloc
;
3497 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3498 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3505 /* sanity checks. */
3506 reloc_howto_type
*reloc_howto
3507 = bfd_reloc_type_lookup (stdoutput
,
3508 (bfd_reloc_code_real_type
) reloc
);
3509 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3510 if (reloc_howto
->rightshift
)
3511 reloc_bitsize
-= reloc_howto
->rightshift
;
3512 if (reloc_bitsize
!= operand
->bits
)
3514 as_bad (_("invalid relocation %s for field"),
3515 bfd_get_reloc_code_name (reloc
));
3520 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3521 as_fatal (_("too many fixups"));
3523 struct arc_fixup
*fixup
;
3524 fixup
= &insn
->fixups
[insn
->nfixups
++];
3526 fixup
->reloc
= reloc
;
3527 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3528 fixup
->pcrel
= pcrel
;
3529 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3536 for (i
= 0; i
< nflg
; i
++)
3538 const struct arc_flag_operand
*flg_operand
=
3539 &arc_flag_operands
[pflags
[i
].code
];
3541 /* Check if the instruction has a delay slot. */
3542 if (!strcmp (flg_operand
->name
, "d"))
3543 has_delay_slot
= TRUE
;
3545 /* There is an exceptional case when we cannot insert a flag
3546 just as it is. The .T flag must be handled in relation with
3547 the relative address. */
3548 if (!strcmp (flg_operand
->name
, "t")
3549 || !strcmp (flg_operand
->name
, "nt"))
3551 unsigned bitYoperand
= 0;
3552 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3553 if (!strcmp (flg_operand
->name
, "t"))
3554 if (!strcmp (opcode
->name
, "bbit0")
3555 || !strcmp (opcode
->name
, "bbit1"))
3556 bitYoperand
= arc_NToperand
;
3558 bitYoperand
= arc_Toperand
;
3560 if (!strcmp (opcode
->name
, "bbit0")
3561 || !strcmp (opcode
->name
, "bbit1"))
3562 bitYoperand
= arc_Toperand
;
3564 bitYoperand
= arc_NToperand
;
3566 gas_assert (reloc_exp
!= NULL
);
3567 if (reloc_exp
->X_op
== O_constant
)
3569 /* Check if we have a constant and solved it
3571 offsetT val
= reloc_exp
->X_add_number
;
3572 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3577 struct arc_fixup
*fixup
;
3579 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3580 as_fatal (_("too many fixups"));
3582 fixup
= &insn
->fixups
[insn
->nfixups
++];
3583 fixup
->exp
= *reloc_exp
;
3584 fixup
->reloc
= -bitYoperand
;
3585 fixup
->pcrel
= pcrel
;
3586 fixup
->islong
= FALSE
;
3590 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3591 << flg_operand
->shift
;
3594 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3596 /* Short instruction? */
3597 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
3601 /* Update last insn status. */
3602 arc_last_insns
[1] = arc_last_insns
[0];
3603 arc_last_insns
[0].opcode
= opcode
;
3604 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3605 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3607 /* Check if the current instruction is legally used. */
3608 if (arc_last_insns
[1].has_delay_slot
3609 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3610 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3611 _("A jump/branch instruction in delay slot."));
3615 arc_handle_align (fragS
* fragP
)
3617 if ((fragP
)->fr_type
== rs_align_code
)
3619 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3620 valueT count
= ((fragP
)->fr_next
->fr_address
3621 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3623 (fragP
)->fr_var
= 2;
3625 if (count
& 1)/* Padding in the gap till the next 2-byte
3626 boundary with 0s. */
3631 /* Writing nop_s. */
3632 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
3636 /* Here we decide which fixups can be adjusted to make them relative
3637 to the beginning of the section instead of the symbol. Basically
3638 we need to make sure that the dynamic relocations are done
3639 correctly, so in some cases we force the original symbol to be
3643 tc_arc_fix_adjustable (fixS
*fixP
)
3646 /* Prevent all adjustments to global symbols. */
3647 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
3649 if (S_IS_WEAK (fixP
->fx_addsy
))
3652 /* Adjust_reloc_syms doesn't know about the GOT. */
3653 switch (fixP
->fx_r_type
)
3655 case BFD_RELOC_ARC_GOTPC32
:
3656 case BFD_RELOC_ARC_PLT32
:
3657 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3658 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3659 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3660 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3670 /* Compute the reloc type of an expression EXP. */
3673 arc_check_reloc (expressionS
*exp
,
3674 bfd_reloc_code_real_type
*r_type_p
)
3676 if (*r_type_p
== BFD_RELOC_32
3677 && exp
->X_op
== O_subtract
3678 && exp
->X_op_symbol
!= NULL
3679 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
3680 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
3684 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3687 arc_cons_fix_new (fragS
*frag
,
3691 bfd_reloc_code_real_type r_type
)
3693 r_type
= BFD_RELOC_UNUSED
;
3698 r_type
= BFD_RELOC_8
;
3702 r_type
= BFD_RELOC_16
;
3706 r_type
= BFD_RELOC_24
;
3710 r_type
= BFD_RELOC_32
;
3711 arc_check_reloc (exp
, &r_type
);
3715 r_type
= BFD_RELOC_64
;
3719 as_bad (_("unsupported BFD relocation size %u"), size
);
3720 r_type
= BFD_RELOC_UNUSED
;
3723 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
3726 /* The actual routine that checks the ZOL conditions. */
3729 check_zol (symbolS
*s
)
3731 switch (arc_mach_type
)
3733 case bfd_mach_arc_arcv2
:
3734 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3737 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
3738 || arc_last_insns
[1].has_delay_slot
)
3739 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3743 case bfd_mach_arc_arc600
:
3745 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
3746 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3749 if (arc_last_insns
[0].has_limm
3750 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3751 as_bad (_("A jump instruction with long immediate detected at the \
3752 end of the ZOL label @%s"), S_GET_NAME (s
));
3755 case bfd_mach_arc_nps400
:
3756 case bfd_mach_arc_arc700
:
3757 if (arc_last_insns
[0].has_delay_slot
)
3758 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3767 /* If ZOL end check the last two instruction for illegals. */
3769 arc_frob_label (symbolS
* sym
)
3771 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
3774 dwarf2_emit_label (sym
);
3777 /* Used because generic relaxation assumes a pc-rel value whilst we
3778 also relax instructions that use an absolute value resolved out of
3779 relative values (if that makes any sense). An example: 'add r1,
3780 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3781 but if they're in the same section we can subtract the section
3782 offset relocation which ends up in a resolved value. So if @.L2 is
3783 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3784 .text + 0x40 = 0x10. */
3786 arc_pcrel_adjust (fragS
*fragP
)
3788 if (!fragP
->tc_frag_data
.pcrel
)
3789 return fragP
->fr_address
+ fragP
->fr_fix
;
3794 /* Initialize the DWARF-2 unwind information for this procedure. */
3797 tc_arc_frame_initial_instructions (void)
3799 /* Stack pointer is register 28. */
3800 cfi_add_CFA_def_cfa_register (28);
3804 tc_arc_regname_to_dw2regnum (char *regname
)
3808 sym
= hash_find (arc_reg_hash
, regname
);
3810 return S_GET_VALUE (sym
);