1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
49 (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 /* Enum used to enumerate the relaxable ins operands. */
59 REGISTER_S
, /* Register for short instruction(s). */
60 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
61 REGISTER_DUP
, /* Duplication of previous operand of type register. */
95 #define regno(x) ((x) & 0x3F)
96 #define is_ir_num(x) (((x) & ~0x3F) == 0)
97 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
98 #define is_spfp_p(op) (((sc) == SPX))
99 #define is_dpfp_p(op) (((sc) == DPX))
100 #define is_fpuda_p(op) (((sc) == DPA))
101 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH || (op)->insn_class == JUMP))
102 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
104 /* Generic assembler global variables which must be defined by all
107 /* Characters which always start a comment. */
108 const char comment_chars
[] = "#;";
110 /* Characters which start a comment at the beginning of a line. */
111 const char line_comment_chars
[] = "#";
113 /* Characters which may be used to separate multiple commands on a
115 const char line_separator_chars
[] = "`";
117 /* Characters which are used to indicate an exponent in a floating
119 const char EXP_CHARS
[] = "eE";
121 /* Chars that mean this number is a floating point constant
122 As in 0f12.456 or 0d1.2345e12. */
123 const char FLT_CHARS
[] = "rRsSfFdD";
126 extern int target_big_endian
;
127 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
128 static int byte_order
= DEFAULT_BYTE_ORDER
;
130 /* Arc extension section. */
131 static segT arcext_section
;
133 /* By default relaxation is disabled. */
134 static int relaxation_state
= 0;
136 extern int arc_get_mach (char *);
138 /* Forward declarations. */
139 static void arc_lcomm (int);
140 static void arc_option (int);
141 static void arc_extra_reloc (int);
142 static void arc_extinsn (int);
143 static void arc_extcorereg (int);
145 const pseudo_typeS md_pseudo_table
[] =
147 /* Make sure that .word is 32 bits. */
150 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
151 { "lcomm", arc_lcomm
, 0 },
152 { "lcommon", arc_lcomm
, 0 },
153 { "cpu", arc_option
, 0 },
155 { "extinstruction", arc_extinsn
, 0 },
156 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
157 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
158 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
160 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
161 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
166 const char *md_shortopts
= "";
170 OPTION_EB
= OPTION_MD_BASE
,
183 /* The following options are deprecated and provided here only for
184 compatibility reasons. */
210 struct option md_longopts
[] =
212 { "EB", no_argument
, NULL
, OPTION_EB
},
213 { "EL", no_argument
, NULL
, OPTION_EL
},
214 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
215 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
216 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
217 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
218 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
219 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
220 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
221 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
222 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
223 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
225 /* The following options are deprecated and provided here only for
226 compatibility reasons. */
227 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
228 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
229 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
230 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
231 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
232 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
233 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
234 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
235 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
236 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
237 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
238 { "mea", no_argument
, NULL
, OPTION_EA
},
239 { "mEA", no_argument
, NULL
, OPTION_EA
},
240 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
241 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
242 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
243 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
244 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
245 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
246 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
247 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
248 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
249 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
250 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
251 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
252 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
253 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
254 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
255 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
256 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
257 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
258 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
259 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
260 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
261 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
262 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
263 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
264 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
265 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
267 { NULL
, no_argument
, NULL
, 0 }
270 size_t md_longopts_size
= sizeof (md_longopts
);
272 /* Local data and data types. */
274 /* Used since new relocation types are introduced in this
275 file (DUMMY_RELOC_LITUSE_*). */
276 typedef int extended_bfd_reloc_code_real_type
;
282 extended_bfd_reloc_code_real_type reloc
;
284 /* index into arc_operands. */
285 unsigned int opindex
;
287 /* PC-relative, used by internals fixups. */
290 /* TRUE if this fixup is for LIMM operand. */
298 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
300 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
302 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
304 bfd_boolean relax
; /* Boolean value: TRUE if needs
308 /* Structure to hold any last two instructions. */
309 static struct arc_last_insn
311 /* Saved instruction opcode. */
312 const struct arc_opcode
*opcode
;
314 /* Boolean value: TRUE if current insn is short. */
315 bfd_boolean has_limm
;
317 /* Boolean value: TRUE if current insn has delay slot. */
318 bfd_boolean has_delay_slot
;
321 /* Extension instruction suffix classes. */
329 static const attributes_t suffixclass
[] =
331 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
332 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
333 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
336 /* Extension instruction syntax classes. */
337 static const attributes_t syntaxclass
[] =
339 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
340 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
341 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
342 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
345 /* Extension instruction syntax classes modifiers. */
346 static const attributes_t syntaxclassmod
[] =
348 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
349 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
352 /* Extension register type. */
360 /* A structure to hold the additional conditional codes. */
363 struct arc_flag_operand
*arc_ext_condcode
;
365 } ext_condcode
= { NULL
, 0 };
367 /* Structure to hold an entry in ARC_OPCODE_HASH. */
368 struct arc_opcode_hash_entry
370 /* The number of pointers in the OPCODE list. */
373 /* Points to a list of opcode pointers. */
374 const struct arc_opcode
**opcode
;
377 /* Structure used for iterating through an arc_opcode_hash_entry. */
378 struct arc_opcode_hash_entry_iterator
380 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
383 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
384 returned by this iterator. */
385 const struct arc_opcode
*opcode
;
388 /* Forward declaration. */
389 static void assemble_insn
390 (const struct arc_opcode
*, const expressionS
*, int,
391 const struct arc_flags
*, int, struct arc_insn
*);
393 /* The cpu for which we are generating code. */
394 static unsigned arc_target
;
395 static const char *arc_target_name
;
396 static unsigned arc_features
;
398 /* The default architecture. */
399 static int arc_mach_type
;
401 /* TRUE if the cpu type has been explicitly specified. */
402 static bfd_boolean mach_type_specified_p
= FALSE
;
404 /* The hash table of instruction opcodes. */
405 static struct hash_control
*arc_opcode_hash
;
407 /* The hash table of register symbols. */
408 static struct hash_control
*arc_reg_hash
;
410 /* The hash table of aux register symbols. */
411 static struct hash_control
*arc_aux_hash
;
413 /* A table of CPU names and opcode sets. */
414 static const struct cpu_type
424 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
425 E_ARC_MACH_ARC600
, 0x00},
426 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
427 E_ARC_MACH_ARC700
, 0x00},
428 { "nps400", ARC_OPCODE_ARC700
| ARC_OPCODE_NPS400
, bfd_mach_arc_nps400
,
429 E_ARC_MACH_NPS400
, 0x00},
430 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
431 EF_ARC_CPU_ARCV2EM
, 0x00},
432 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
433 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
437 /* Used by the arc_reloc_op table. Order is important. */
438 #define O_gotoff O_md1 /* @gotoff relocation. */
439 #define O_gotpc O_md2 /* @gotpc relocation. */
440 #define O_plt O_md3 /* @plt relocation. */
441 #define O_sda O_md4 /* @sda relocation. */
442 #define O_pcl O_md5 /* @pcl relocation. */
443 #define O_tlsgd O_md6 /* @tlsgd relocation. */
444 #define O_tlsie O_md7 /* @tlsie relocation. */
445 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
446 #define O_tpoff O_md9 /* @tpoff relocation. */
447 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
448 #define O_dtpoff O_md11 /* @dtpoff relocation. */
449 #define O_last O_dtpoff
451 /* Used to define a bracket as operand in tokens. */
452 #define O_bracket O_md32
454 /* Dummy relocation, to be sorted out. */
455 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
457 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
459 /* A table to map the spelling of a relocation operand into an appropriate
460 bfd_reloc_code_real_type type. The table is assumed to be ordered such
461 that op-O_literal indexes into it. */
462 #define ARC_RELOC_TABLE(op) \
463 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
465 : (int) (op) - (int) O_gotoff) ])
467 #define DEF(NAME, RELOC, REQ) \
468 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
470 static const struct arc_reloc_op_tag
472 /* String to lookup. */
474 /* Size of the string. */
476 /* Which operator to use. */
478 extended_bfd_reloc_code_real_type reloc
;
479 /* Allows complex relocation expression like identifier@reloc +
481 unsigned int complex_expr
: 1;
485 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
486 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
487 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
488 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
489 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
490 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
491 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
492 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
493 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
494 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
495 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 0),
498 static const int arc_num_reloc_op
499 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
501 /* Structure for relaxable instruction that have to be swapped with a
502 smaller alternative instruction. */
503 struct arc_relaxable_ins
505 /* Mnemonic that should be checked. */
506 const char *mnemonic_r
;
508 /* Operands that should be checked.
509 Indexes of operands from operand array. */
510 enum rlx_operand_type operands
[6];
512 /* Flags that should be checked. */
513 unsigned flag_classes
[5];
515 /* Mnemonic (smaller) alternative to be used later for relaxation. */
516 const char *mnemonic_alt
;
518 /* Index of operand that generic relaxation has to check. */
521 /* Base subtype index used. */
522 enum arc_rlx_types subtype
;
525 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
526 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
527 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
531 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
532 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
533 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
538 /* ARC relaxation table. */
539 const relax_typeS md_relax_table
[] =
546 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL
),
547 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
551 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B
),
552 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
557 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6
),
558 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM
),
559 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
561 /* LD_S a, [b, u7] ->
562 LD<zz><.x><.aa><.di> a, [b, s9] ->
563 LD<zz><.x><.aa><.di> a, [b, limm] */
564 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9
),
565 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM
),
566 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE
),
571 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12
),
572 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM
),
573 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
577 SUB<.f> a, b, limm. */
578 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6
),
579 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM
),
580 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
582 /* MPY<.f> a, b, u6 ->
583 MPY<.f> a, b, limm. */
584 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM
),
585 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
587 /* MOV<.f><.cc> b, u6 ->
588 MOV<.f><.cc> b, limm. */
589 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM
),
590 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
592 /* ADD<.f><.cc> b, b, u6 ->
593 ADD<.f><.cc> b, b, limm. */
594 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM
),
595 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
598 /* Order of this table's entries matters! */
599 const struct arc_relaxable_ins arc_relaxable_insns
[] =
601 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
602 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
603 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
604 2, ARC_RLX_ADD_RRU6
},
605 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
607 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
609 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
610 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
611 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
612 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
613 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
614 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
615 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
616 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
618 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
620 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
624 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
626 /* Flags to set in the elf header. */
627 static flagword arc_eflag
= 0x00;
629 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
630 symbolS
* GOT_symbol
= 0;
632 /* Set to TRUE when we assemble instructions. */
633 static bfd_boolean assembling_insn
= FALSE
;
635 /* Functions implementation. */
637 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
638 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
639 are no matching entries in ARC_OPCODE_HASH. */
641 static const struct arc_opcode_hash_entry
*
642 arc_find_opcode (const char *name
)
644 const struct arc_opcode_hash_entry
*entry
;
646 entry
= hash_find (arc_opcode_hash
, name
);
650 /* Initialise the iterator ITER. */
653 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
659 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
660 calls to this function. Return NULL when all ARC_OPCODE entries have
663 static const struct arc_opcode
*
664 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
665 struct arc_opcode_hash_entry_iterator
*iter
)
667 if (iter
->opcode
== NULL
&& iter
->index
== 0)
669 gas_assert (entry
->count
> 0);
670 iter
->opcode
= entry
->opcode
[iter
->index
];
672 else if (iter
->opcode
!= NULL
)
674 const char *old_name
= iter
->opcode
->name
;
677 if (iter
->opcode
->name
== NULL
678 || strcmp (old_name
, iter
->opcode
->name
) != 0)
681 if (iter
->index
== entry
->count
)
684 iter
->opcode
= entry
->opcode
[iter
->index
];
691 /* Insert an opcode into opcode hash structure. */
694 arc_insert_opcode (const struct arc_opcode
*opcode
)
696 const char *name
, *retval
;
697 struct arc_opcode_hash_entry
*entry
;
700 entry
= hash_find (arc_opcode_hash
, name
);
703 entry
= XNEW (struct arc_opcode_hash_entry
);
705 entry
->opcode
= NULL
;
707 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
709 as_fatal (_("internal error: can't hash opcode '%s': %s"),
713 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
716 if (entry
->opcode
== NULL
)
717 as_fatal (_("Virtual memory exhausted"));
719 entry
->opcode
[entry
->count
] = opcode
;
724 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
725 is encoded as 'middle-endian' for a little-endian target. FIXME!
726 this function is used for regular 4 byte instructions as well. */
729 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
733 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
734 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
738 md_number_to_chars (buf
, val
, n
);
742 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
743 the relevant static global variables. */
746 arc_select_cpu (const char *arg
)
751 for (i
= 0; cpu_types
[i
].name
; ++i
)
753 if (!strcasecmp (cpu_types
[i
].name
, arg
))
755 arc_target
= cpu_types
[i
].flags
;
756 arc_target_name
= cpu_types
[i
].name
;
757 arc_features
= cpu_types
[i
].features
;
758 arc_mach_type
= cpu_types
[i
].mach
;
759 cpu_flags
= cpu_types
[i
].eflags
;
764 if (!cpu_types
[i
].name
)
765 as_fatal (_("unknown architecture: %s\n"), arg
);
766 gas_assert (cpu_flags
!= 0);
767 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
770 /* Here ends all the ARCompact extension instruction assembling
774 arc_extra_reloc (int r_type
)
777 symbolS
*sym
, *lab
= NULL
;
779 if (*input_line_pointer
== '@')
780 input_line_pointer
++;
781 c
= get_symbol_name (&sym_name
);
782 sym
= symbol_find_or_make (sym_name
);
783 restore_line_pointer (c
);
784 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
786 ++input_line_pointer
;
788 c
= get_symbol_name (&lab_name
);
789 lab
= symbol_find_or_make (lab_name
);
790 restore_line_pointer (c
);
793 /* These relocations exist as a mechanism for the compiler to tell the
794 linker how to patch the code if the tls model is optimised. However,
795 the relocation itself does not require any space within the assembler
796 fragment, and so we pass a size of 0.
798 The lines that generate these relocations look like this:
800 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
802 The '.tls_gd_ld @.tdata' is processed first and generates the
803 additional relocation, while the 'bl __tls_get_addr@plt' is processed
804 second and generates the additional branch.
806 It is possible that the additional relocation generated by the
807 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
808 while the 'bl __tls_get_addr@plt' will be generated as the first thing
809 in the next fragment. This will be fine; both relocations will still
810 appear to be at the same address in the generated object file.
811 However, this only works as the additional relocation is generated
812 with size of 0 bytes. */
814 = fix_new (frag_now
, /* Which frag? */
815 frag_now_fix (), /* Where in that frag? */
816 0, /* size: 1, 2, or 4 usually. */
817 sym
, /* X_add_symbol. */
818 0, /* X_add_number. */
819 FALSE
, /* TRUE if PC-relative relocation. */
820 r_type
/* Relocation type. */);
821 fixP
->fx_subsy
= lab
;
825 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
826 symbolS
*symbolP
, addressT size
)
831 if (*input_line_pointer
== ',')
833 align
= parse_align (1);
835 if (align
== (addressT
) -1)
850 bss_alloc (symbolP
, size
, align
);
851 S_CLEAR_EXTERNAL (symbolP
);
857 arc_lcomm (int ignore
)
859 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
862 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
865 /* Select the cpu we're assembling for. */
868 arc_option (int ignore ATTRIBUTE_UNUSED
)
874 c
= get_symbol_name (&cpu
);
875 mach
= arc_get_mach (cpu
);
880 if (!mach_type_specified_p
)
882 if ((!strcmp ("ARC600", cpu
))
883 || (!strcmp ("ARC601", cpu
))
884 || (!strcmp ("A6", cpu
)))
886 md_parse_option (OPTION_MCPU
, "arc600");
888 else if ((!strcmp ("ARC700", cpu
))
889 || (!strcmp ("A7", cpu
)))
891 md_parse_option (OPTION_MCPU
, "arc700");
893 else if (!strcmp ("EM", cpu
))
895 md_parse_option (OPTION_MCPU
, "arcem");
897 else if (!strcmp ("HS", cpu
))
899 md_parse_option (OPTION_MCPU
, "archs");
901 else if (!strcmp ("NPS400", cpu
))
903 md_parse_option (OPTION_MCPU
, "nps400");
906 as_fatal (_("could not find the architecture"));
908 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
909 as_fatal (_("could not set architecture and machine"));
911 /* Set elf header flags. */
912 bfd_set_private_flags (stdoutput
, arc_eflag
);
915 if (arc_mach_type
!= mach
)
916 as_warn (_("Command-line value overrides \".cpu\" directive"));
918 restore_line_pointer (c
);
919 demand_empty_rest_of_line ();
923 restore_line_pointer (c
);
924 as_bad (_("invalid identifier for \".cpu\""));
925 ignore_rest_of_line ();
928 /* Smartly print an expression. */
931 debug_exp (expressionS
*t
)
933 const char *name ATTRIBUTE_UNUSED
;
934 const char *namemd ATTRIBUTE_UNUSED
;
936 pr_debug ("debug_exp: ");
940 default: name
= "unknown"; break;
941 case O_illegal
: name
= "O_illegal"; break;
942 case O_absent
: name
= "O_absent"; break;
943 case O_constant
: name
= "O_constant"; break;
944 case O_symbol
: name
= "O_symbol"; break;
945 case O_symbol_rva
: name
= "O_symbol_rva"; break;
946 case O_register
: name
= "O_register"; break;
947 case O_big
: name
= "O_big"; break;
948 case O_uminus
: name
= "O_uminus"; break;
949 case O_bit_not
: name
= "O_bit_not"; break;
950 case O_logical_not
: name
= "O_logical_not"; break;
951 case O_multiply
: name
= "O_multiply"; break;
952 case O_divide
: name
= "O_divide"; break;
953 case O_modulus
: name
= "O_modulus"; break;
954 case O_left_shift
: name
= "O_left_shift"; break;
955 case O_right_shift
: name
= "O_right_shift"; break;
956 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
957 case O_bit_or_not
: name
= "O_bit_or_not"; break;
958 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
959 case O_bit_and
: name
= "O_bit_and"; break;
960 case O_add
: name
= "O_add"; break;
961 case O_subtract
: name
= "O_subtract"; break;
962 case O_eq
: name
= "O_eq"; break;
963 case O_ne
: name
= "O_ne"; break;
964 case O_lt
: name
= "O_lt"; break;
965 case O_le
: name
= "O_le"; break;
966 case O_ge
: name
= "O_ge"; break;
967 case O_gt
: name
= "O_gt"; break;
968 case O_logical_and
: name
= "O_logical_and"; break;
969 case O_logical_or
: name
= "O_logical_or"; break;
970 case O_index
: name
= "O_index"; break;
971 case O_bracket
: name
= "O_bracket"; break;
976 default: namemd
= "unknown"; break;
977 case O_gotoff
: namemd
= "O_gotoff"; break;
978 case O_gotpc
: namemd
= "O_gotpc"; break;
979 case O_plt
: namemd
= "O_plt"; break;
980 case O_sda
: namemd
= "O_sda"; break;
981 case O_pcl
: namemd
= "O_pcl"; break;
982 case O_tlsgd
: namemd
= "O_tlsgd"; break;
983 case O_tlsie
: namemd
= "O_tlsie"; break;
984 case O_tpoff9
: namemd
= "O_tpoff9"; break;
985 case O_tpoff
: namemd
= "O_tpoff"; break;
986 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
987 case O_dtpoff
: namemd
= "O_dtpoff"; break;
990 pr_debug ("%s (%s, %s, %d, %s)", name
,
991 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
992 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
993 (int) t
->X_add_number
,
994 (t
->X_md
) ? namemd
: "--");
999 /* Parse the arguments to an opcode. */
1002 tokenize_arguments (char *str
,
1006 char *old_input_line_pointer
;
1007 bfd_boolean saw_comma
= FALSE
;
1008 bfd_boolean saw_arg
= FALSE
;
1013 const struct arc_reloc_op_tag
*r
;
1015 char *reloc_name
, c
;
1017 memset (tok
, 0, sizeof (*tok
) * ntok
);
1019 /* Save and restore input_line_pointer around this function. */
1020 old_input_line_pointer
= input_line_pointer
;
1021 input_line_pointer
= str
;
1023 while (*input_line_pointer
)
1026 switch (*input_line_pointer
)
1032 input_line_pointer
++;
1033 if (saw_comma
|| !saw_arg
)
1040 ++input_line_pointer
;
1042 if (!saw_arg
|| num_args
== ntok
)
1044 tok
->X_op
= O_bracket
;
1051 input_line_pointer
++;
1052 if (brk_lvl
|| num_args
== ntok
)
1055 tok
->X_op
= O_bracket
;
1061 /* We have labels, function names and relocations, all
1062 starting with @ symbol. Sort them out. */
1063 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1067 tok
->X_op
= O_symbol
;
1068 tok
->X_md
= O_absent
;
1070 if (*input_line_pointer
!= '@')
1071 goto normalsymbol
; /* This is not a relocation. */
1075 /* A relocation opernad has the following form
1076 @identifier@relocation_type. The identifier is already
1078 if (tok
->X_op
!= O_symbol
)
1080 as_bad (_("No valid label relocation operand"));
1084 /* Parse @relocation_type. */
1085 input_line_pointer
++;
1086 c
= get_symbol_name (&reloc_name
);
1087 len
= input_line_pointer
- reloc_name
;
1090 as_bad (_("No relocation operand"));
1094 /* Go through known relocation and try to find a match. */
1095 r
= &arc_reloc_op
[0];
1096 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1097 if (len
== r
->length
1098 && memcmp (reloc_name
, r
->name
, len
) == 0)
1102 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1106 *input_line_pointer
= c
;
1107 SKIP_WHITESPACE_AFTER_NAME ();
1108 /* Extra check for TLS: base. */
1109 if (*input_line_pointer
== '@')
1112 if (tok
->X_op_symbol
!= NULL
1113 || tok
->X_op
!= O_symbol
)
1115 as_bad (_("Unable to parse TLS base: %s"),
1116 input_line_pointer
);
1119 input_line_pointer
++;
1121 c
= get_symbol_name (&sym_name
);
1122 base
= symbol_find_or_make (sym_name
);
1123 tok
->X_op
= O_subtract
;
1124 tok
->X_op_symbol
= base
;
1125 restore_line_pointer (c
);
1126 tmpE
.X_add_number
= 0;
1128 else if ((*input_line_pointer
!= '+')
1129 && (*input_line_pointer
!= '-'))
1131 tmpE
.X_add_number
= 0;
1135 /* Parse the constant of a complex relocation expression
1136 like @identifier@reloc +/- const. */
1137 if (! r
->complex_expr
)
1139 as_bad (_("@%s is not a complex relocation."), r
->name
);
1143 if (tmpE
.X_op
!= O_constant
)
1145 as_bad (_("Bad expression: @%s + %s."),
1146 r
->name
, input_line_pointer
);
1152 tok
->X_add_number
= tmpE
.X_add_number
;
1163 /* Can be a register. */
1164 ++input_line_pointer
;
1168 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1171 tok
->X_op
= O_absent
;
1172 tok
->X_md
= O_absent
;
1175 /* Legacy: There are cases when we have
1176 identifier@relocation_type, if it is the case parse the
1177 relocation type as well. */
1178 if (*input_line_pointer
== '@')
1184 if (tok
->X_op
== O_illegal
1185 || tok
->X_op
== O_absent
1186 || num_args
== ntok
)
1198 if (saw_comma
|| brk_lvl
)
1200 input_line_pointer
= old_input_line_pointer
;
1206 as_bad (_("Brackets in operand field incorrect"));
1208 as_bad (_("extra comma"));
1210 as_bad (_("missing argument"));
1212 as_bad (_("missing comma or colon"));
1213 input_line_pointer
= old_input_line_pointer
;
1217 /* Parse the flags to a structure. */
1220 tokenize_flags (const char *str
,
1221 struct arc_flags flags
[],
1224 char *old_input_line_pointer
;
1225 bfd_boolean saw_flg
= FALSE
;
1226 bfd_boolean saw_dot
= FALSE
;
1230 memset (flags
, 0, sizeof (*flags
) * nflg
);
1232 /* Save and restore input_line_pointer around this function. */
1233 old_input_line_pointer
= input_line_pointer
;
1234 input_line_pointer
= (char *) str
;
1236 while (*input_line_pointer
)
1238 switch (*input_line_pointer
)
1245 input_line_pointer
++;
1253 if (saw_flg
&& !saw_dot
)
1256 if (num_flags
>= nflg
)
1259 flgnamelen
= strspn (input_line_pointer
,
1260 "abcdefghijklmnopqrstuvwxyz0123456789");
1261 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1264 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1266 input_line_pointer
+= flgnamelen
;
1276 input_line_pointer
= old_input_line_pointer
;
1281 as_bad (_("extra dot"));
1283 as_bad (_("unrecognized flag"));
1285 as_bad (_("failed to parse flags"));
1286 input_line_pointer
= old_input_line_pointer
;
1290 /* Apply the fixups in order. */
1293 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1297 for (i
= 0; i
< insn
->nfixups
; i
++)
1299 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1300 int size
, pcrel
, offset
= 0;
1302 /* FIXME! the reloc size is wrong in the BFD file.
1303 When it is fixed please delete me. */
1304 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1307 offset
= (insn
->short_insn
) ? 2 : 4;
1309 /* Some fixups are only used internally, thus no howto. */
1310 if ((int) fixup
->reloc
== 0)
1311 as_fatal (_("Unhandled reloc type"));
1313 if ((int) fixup
->reloc
< 0)
1315 /* FIXME! the reloc size is wrong in the BFD file.
1316 When it is fixed please enable me.
1317 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1318 pcrel
= fixup
->pcrel
;
1322 reloc_howto_type
*reloc_howto
=
1323 bfd_reloc_type_lookup (stdoutput
,
1324 (bfd_reloc_code_real_type
) fixup
->reloc
);
1325 gas_assert (reloc_howto
);
1327 /* FIXME! the reloc size is wrong in the BFD file.
1328 When it is fixed please enable me.
1329 size = bfd_get_reloc_size (reloc_howto); */
1330 pcrel
= reloc_howto
->pc_relative
;
1333 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1335 fragP
->fr_file
, fragP
->fr_line
,
1336 (fixup
->reloc
< 0) ? "Internal" :
1337 bfd_get_reloc_code_name (fixup
->reloc
),
1340 fix_new_exp (fragP
, fix
+ offset
,
1341 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1343 /* Check for ZOLs, and update symbol info if any. */
1344 if (LP_INSN (insn
->insn
))
1346 gas_assert (fixup
->exp
.X_add_symbol
);
1347 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1352 /* Actually output an instruction with its fixup. */
1355 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1359 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1360 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1361 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1363 /* Write out the instruction. */
1364 if (insn
->short_insn
)
1370 md_number_to_chars (f
, insn
->insn
, 2);
1371 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1372 dwarf2_emit_insn (6);
1378 md_number_to_chars (f
, insn
->insn
, 2);
1379 dwarf2_emit_insn (2);
1388 md_number_to_chars_midend (f
, insn
->insn
, 4);
1389 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1390 dwarf2_emit_insn (8);
1396 md_number_to_chars_midend (f
, insn
->insn
, 4);
1397 dwarf2_emit_insn (4);
1402 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1406 emit_insn1 (struct arc_insn
*insn
)
1408 /* How frag_var's args are currently configured:
1409 - rs_machine_dependent, to dictate it's a relaxation frag.
1410 - FRAG_MAX_GROWTH, maximum size of instruction
1411 - 0, variable size that might grow...unused by generic relaxation.
1412 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1413 - s, opand expression.
1414 - 0, offset but it's unused.
1415 - 0, opcode but it's unused. */
1416 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1417 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1419 if (frag_room () < FRAG_MAX_GROWTH
)
1421 /* Handle differently when frag literal memory is exhausted.
1422 This is used because when there's not enough memory left in
1423 the current frag, a new frag is created and the information
1424 we put into frag_now->tc_frag_data is disregarded. */
1426 struct arc_relax_type relax_info_copy
;
1427 relax_substateT subtype
= frag_now
->fr_subtype
;
1429 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1430 sizeof (struct arc_relax_type
));
1432 frag_wane (frag_now
);
1433 frag_grow (FRAG_MAX_GROWTH
);
1435 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1436 sizeof (struct arc_relax_type
));
1438 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1442 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1443 frag_now
->fr_subtype
, s
, 0, 0);
1447 emit_insn (struct arc_insn
*insn
)
1452 emit_insn0 (insn
, NULL
, FALSE
);
1455 /* Check whether a symbol involves a register. */
1458 contains_register (symbolS
*sym
)
1462 expressionS
*ex
= symbol_get_value_expression (sym
);
1464 return ((O_register
== ex
->X_op
)
1465 && !contains_register (ex
->X_add_symbol
)
1466 && !contains_register (ex
->X_op_symbol
));
1472 /* Returns the register number within a symbol. */
1475 get_register (symbolS
*sym
)
1477 if (!contains_register (sym
))
1480 expressionS
*ex
= symbol_get_value_expression (sym
);
1481 return regno (ex
->X_add_number
);
1484 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1485 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1488 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1495 case BFD_RELOC_ARC_SDA_LDST
:
1496 case BFD_RELOC_ARC_SDA_LDST1
:
1497 case BFD_RELOC_ARC_SDA_LDST2
:
1498 case BFD_RELOC_ARC_SDA16_LD
:
1499 case BFD_RELOC_ARC_SDA16_LD1
:
1500 case BFD_RELOC_ARC_SDA16_LD2
:
1501 case BFD_RELOC_ARC_SDA16_ST2
:
1502 case BFD_RELOC_ARC_SDA32_ME
:
1509 /* Allocates a tok entry. */
1512 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1514 if (ntok
> MAX_INSN_ARGS
- 2)
1515 return 0; /* No space left. */
1518 return 0; /* Incorect args. */
1520 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1523 return 1; /* Success. */
1524 return allocate_tok (tok
, ntok
- 1, cidx
);
1527 /* Check if an particular ARC feature is enabled. */
1530 check_cpu_feature (insn_subclass_t sc
)
1532 if (!(arc_features
& ARC_CD
)
1533 && is_code_density_p (sc
))
1536 if (!(arc_features
& ARC_SPFP
)
1540 if (!(arc_features
& ARC_DPFP
)
1544 if (!(arc_features
& ARC_FPUDA
)
1551 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1552 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1553 array and returns TRUE if the flag operands all match, otherwise,
1554 returns FALSE, in which case the FIRST_PFLAG array may have been
1558 parse_opcode_flags (const struct arc_opcode
*opcode
,
1560 struct arc_flags
*first_pflag
)
1563 const unsigned char *flgidx
;
1566 for (i
= 0; i
< nflgs
; i
++)
1567 first_pflag
[i
].flgp
= NULL
;
1569 /* Check the flags. Iterate over the valid flag classes. */
1570 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1572 /* Get a valid flag class. */
1573 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1574 const unsigned *flgopridx
;
1576 struct arc_flags
*pflag
= NULL
;
1578 /* Check for extension conditional codes. */
1579 if (ext_condcode
.arc_ext_condcode
1580 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1582 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1585 pflag
= first_pflag
;
1586 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1588 if (!strcmp (pf
->name
, pflag
->name
))
1590 if (pflag
->flgp
!= NULL
)
1603 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1605 const struct arc_flag_operand
*flg_operand
;
1607 pflag
= first_pflag
;
1608 flg_operand
= &arc_flag_operands
[*flgopridx
];
1609 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1611 /* Match against the parsed flags. */
1612 if (!strcmp (flg_operand
->name
, pflag
->name
))
1614 if (pflag
->flgp
!= NULL
)
1617 pflag
->flgp
= flg_operand
;
1619 break; /* goto next flag class and parsed flag. */
1624 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1626 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1630 /* Did I check all the parsed flags? */
1631 return lnflg
? FALSE
: TRUE
;
1635 /* Search forward through all variants of an opcode looking for a
1638 static const struct arc_opcode
*
1639 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1642 struct arc_flags
*first_pflag
,
1646 const struct arc_opcode
*opcode
;
1647 struct arc_opcode_hash_entry_iterator iter
;
1649 int got_cpu_match
= 0;
1650 expressionS bktok
[MAX_INSN_ARGS
];
1654 arc_opcode_hash_entry_iterator_init (&iter
);
1655 memset (&emptyE
, 0, sizeof (emptyE
));
1656 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1659 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1661 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1663 const unsigned char *opidx
;
1665 const expressionS
*t
= &emptyE
;
1667 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1668 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1670 /* Don't match opcodes that don't exist on this
1672 if (!(opcode
->cpu
& arc_target
))
1675 if (!check_cpu_feature (opcode
->subclass
))
1681 /* Check the operands. */
1682 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1684 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1686 /* Only take input from real operands. */
1687 if ((operand
->flags
& ARC_OPERAND_FAKE
)
1688 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
1691 /* When we expect input, make sure we have it. */
1695 /* Match operand type with expression type. */
1696 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1698 case ARC_OPERAND_IR
:
1699 /* Check to be a register. */
1700 if ((tok
[tokidx
].X_op
!= O_register
1701 || !is_ir_num (tok
[tokidx
].X_add_number
))
1702 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1705 /* If expect duplicate, make sure it is duplicate. */
1706 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1708 /* Check for duplicate. */
1709 if (t
->X_op
!= O_register
1710 || !is_ir_num (t
->X_add_number
)
1711 || (regno (t
->X_add_number
) !=
1712 regno (tok
[tokidx
].X_add_number
)))
1716 /* Special handling? */
1717 if (operand
->insert
)
1719 const char *errmsg
= NULL
;
1720 (*operand
->insert
)(0,
1721 regno (tok
[tokidx
].X_add_number
),
1725 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1727 /* Missing argument, create one. */
1728 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1731 tok
[tokidx
].X_op
= O_absent
;
1742 case ARC_OPERAND_BRAKET
:
1743 /* Check if bracket is also in opcode table as
1745 if (tok
[tokidx
].X_op
!= O_bracket
)
1749 case ARC_OPERAND_LIMM
:
1750 case ARC_OPERAND_SIGNED
:
1751 case ARC_OPERAND_UNSIGNED
:
1752 switch (tok
[tokidx
].X_op
)
1760 /* Got an (too) early bracket, check if it is an
1761 ignored operand. N.B. This procedure works only
1762 when bracket is the last operand! */
1763 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1765 /* Insert the missing operand. */
1766 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1769 tok
[tokidx
].X_op
= O_absent
;
1776 const struct arc_aux_reg
*auxr
;
1778 if (opcode
->insn_class
!= AUXREG
)
1780 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1782 auxr
= hash_find (arc_aux_hash
, p
);
1785 /* We modify the token array here, safe in the
1786 knowledge, that if this was the wrong
1787 choice then the original contents will be
1788 restored from BKTOK. */
1789 tok
[tokidx
].X_op
= O_constant
;
1790 tok
[tokidx
].X_add_number
= auxr
->address
;
1791 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1794 if (tok
[tokidx
].X_op
!= O_constant
)
1799 /* Check the range. */
1800 if (operand
->bits
!= 32
1801 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1803 offsetT min
, max
, val
;
1804 val
= tok
[tokidx
].X_add_number
;
1806 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1808 max
= (1 << (operand
->bits
- 1)) - 1;
1809 min
= -(1 << (operand
->bits
- 1));
1813 max
= (1 << operand
->bits
) - 1;
1817 if (val
< min
|| val
> max
)
1820 /* Check alignmets. */
1821 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1825 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1829 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1831 if (operand
->insert
)
1833 const char *errmsg
= NULL
;
1834 (*operand
->insert
)(0,
1835 tok
[tokidx
].X_add_number
,
1840 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1846 /* Check if it is register range. */
1847 if ((tok
[tokidx
].X_add_number
== 0)
1848 && contains_register (tok
[tokidx
].X_add_symbol
)
1849 && contains_register (tok
[tokidx
].X_op_symbol
))
1853 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1855 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1856 if (operand
->insert
)
1858 const char *errmsg
= NULL
;
1859 (*operand
->insert
)(0,
1871 if (operand
->default_reloc
== 0)
1872 goto match_failed
; /* The operand needs relocation. */
1874 /* Relocs requiring long immediate. FIXME! make it
1875 generic and move it to a function. */
1876 switch (tok
[tokidx
].X_md
)
1885 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1888 if (!generic_reloc_p (operand
->default_reloc
))
1895 /* If expect duplicate, make sure it is duplicate. */
1896 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1898 if (t
->X_op
== O_illegal
1899 || t
->X_op
== O_absent
1900 || t
->X_op
== O_register
1901 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1908 /* Everything else should have been fake. */
1916 /* Setup ready for flag parsing. */
1917 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
1921 /* Possible match -- did we use all of our input? */
1931 /* Restore the original parameters. */
1932 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1937 *pcpumatch
= got_cpu_match
;
1942 /* Swap operand tokens. */
1945 swap_operand (expressionS
*operand_array
,
1947 unsigned destination
)
1949 expressionS cpy_operand
;
1950 expressionS
*src_operand
;
1951 expressionS
*dst_operand
;
1954 if (source
== destination
)
1957 src_operand
= &operand_array
[source
];
1958 dst_operand
= &operand_array
[destination
];
1959 size
= sizeof (expressionS
);
1961 /* Make copy of operand to swap with and swap. */
1962 memcpy (&cpy_operand
, dst_operand
, size
);
1963 memcpy (dst_operand
, src_operand
, size
);
1964 memcpy (src_operand
, &cpy_operand
, size
);
1967 /* Check if *op matches *tok type.
1968 Returns FALSE if they don't match, TRUE if they match. */
1971 pseudo_operand_match (const expressionS
*tok
,
1972 const struct arc_operand_operation
*op
)
1974 offsetT min
, max
, val
;
1976 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
1982 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
1984 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
1986 val
= tok
->X_add_number
+ op
->count
;
1987 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
1989 max
= (1 << (operand_real
->bits
- 1)) - 1;
1990 min
= -(1 << (operand_real
->bits
- 1));
1994 max
= (1 << operand_real
->bits
) - 1;
1997 if (min
<= val
&& val
<= max
)
2003 /* Handle all symbols as long immediates or signed 9. */
2004 if (operand_real
->flags
& ARC_OPERAND_LIMM
||
2005 ((operand_real
->flags
& ARC_OPERAND_SIGNED
) && operand_real
->bits
== 9))
2010 if (operand_real
->flags
& ARC_OPERAND_IR
)
2015 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2026 /* Find pseudo instruction in array. */
2028 static const struct arc_pseudo_insn
*
2029 find_pseudo_insn (const char *opname
,
2031 const expressionS
*tok
)
2033 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2034 const struct arc_operand_operation
*op
;
2038 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2040 pseudo_insn
= &arc_pseudo_insns
[i
];
2041 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2043 op
= pseudo_insn
->operand
;
2044 for (j
= 0; j
< ntok
; ++j
)
2045 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2048 /* Found the right instruction. */
2056 /* Assumes the expressionS *tok is of sufficient size. */
2058 static const struct arc_opcode_hash_entry
*
2059 find_special_case_pseudo (const char *opname
,
2063 struct arc_flags
*pflags
)
2065 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2066 const struct arc_operand_operation
*operand_pseudo
;
2067 const struct arc_operand
*operand_real
;
2069 char construct_operand
[MAX_CONSTR_STR
];
2071 /* Find whether opname is in pseudo instruction array. */
2072 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2074 if (pseudo_insn
== NULL
)
2077 /* Handle flag, Limited to one flag at the moment. */
2078 if (pseudo_insn
->flag_r
!= NULL
)
2079 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2080 MAX_INSN_FLGS
- *nflgs
);
2082 /* Handle operand operations. */
2083 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2085 operand_pseudo
= &pseudo_insn
->operand
[i
];
2086 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2088 if (operand_real
->flags
& ARC_OPERAND_BRAKET
&&
2089 !operand_pseudo
->needs_insert
)
2092 /* Has to be inserted (i.e. this token does not exist yet). */
2093 if (operand_pseudo
->needs_insert
)
2095 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2097 tok
[i
].X_op
= O_bracket
;
2102 /* Check if operand is a register or constant and handle it
2104 if (operand_real
->flags
& ARC_OPERAND_IR
)
2105 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2106 operand_pseudo
->count
);
2108 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2109 operand_pseudo
->count
);
2111 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2115 else if (operand_pseudo
->count
)
2117 /* Operand number has to be adjusted accordingly (by operand
2119 switch (tok
[i
].X_op
)
2122 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2135 /* Swap operands if necessary. Only supports one swap at the
2137 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2139 operand_pseudo
= &pseudo_insn
->operand
[i
];
2141 if (operand_pseudo
->swap_operand_idx
== i
)
2144 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2146 /* Prevent a swap back later by breaking out. */
2150 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2153 static const struct arc_opcode_hash_entry
*
2154 find_special_case_flag (const char *opname
,
2156 struct arc_flags
*pflags
)
2160 unsigned flag_idx
, flag_arr_idx
;
2161 size_t flaglen
, oplen
;
2162 const struct arc_flag_special
*arc_flag_special_opcode
;
2163 const struct arc_opcode_hash_entry
*entry
;
2165 /* Search for special case instruction. */
2166 for (i
= 0; i
< arc_num_flag_special
; i
++)
2168 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2169 oplen
= strlen (arc_flag_special_opcode
->name
);
2171 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2174 /* Found a potential special case instruction, now test for
2176 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2178 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2180 break; /* End of array, nothing found. */
2182 flagnm
= arc_flag_operands
[flag_idx
].name
;
2183 flaglen
= strlen (flagnm
);
2184 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2186 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2188 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2190 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2191 pflags
[*nflgs
].name
[flaglen
] = '\0';
2200 /* The long instructions are not stored in a hash (there's not many of
2201 them) and so there's no arc_opcode_hash_entry structure to return. This
2202 helper function for find_special_case_long_opcode takes an arc_opcode
2203 result and places it into a fake arc_opcode_hash_entry that points to
2204 the single arc_opcode OPCODE, which is then returned. */
2206 static const struct arc_opcode_hash_entry
*
2207 build_fake_opcode_hash_entry (const struct arc_opcode
*opcode
)
2209 static struct arc_opcode_hash_entry entry
;
2210 static struct arc_opcode tmp
[2];
2211 static const struct arc_opcode
*ptr
[2];
2213 memcpy (&tmp
[0], opcode
, sizeof (struct arc_opcode
));
2214 memset (&tmp
[1], 0, sizeof (struct arc_opcode
));
2223 /* Used by the assembler to match the list of tokens against a long (48 or
2224 64 bits) instruction. If a matching long instruction is found, then
2225 some of the tokens are consumed in this function and converted into a
2226 single LIMM value, which is then added to the end of the token list,
2227 where it will be consumed by a LIMM operand that exists in the base
2228 opcode of the long instruction. */
2230 static const struct arc_opcode_hash_entry
*
2231 find_special_case_long_opcode (const char *opname
,
2232 int *ntok ATTRIBUTE_UNUSED
,
2233 expressionS
*tok ATTRIBUTE_UNUSED
,
2235 struct arc_flags
*pflags
)
2239 if (*ntok
== MAX_INSN_ARGS
)
2242 for (i
= 0; i
< arc_num_long_opcodes
; ++i
)
2244 struct arc_opcode fake_opcode
;
2245 const struct arc_opcode
*opcode
;
2246 struct arc_insn insn
;
2247 expressionS
*limm_token
;
2249 opcode
= &arc_long_opcodes
[i
].base_opcode
;
2251 if (!(opcode
->cpu
& arc_target
))
2254 if (!check_cpu_feature (opcode
->subclass
))
2257 if (strcmp (opname
, opcode
->name
) != 0)
2260 /* Check that the flags are a match. */
2261 if (!parse_opcode_flags (opcode
, *nflgs
, pflags
))
2264 /* Parse the LIMM operands into the LIMM template. */
2265 memset (&fake_opcode
, 0, sizeof (fake_opcode
));
2266 fake_opcode
.name
= "fake limm";
2267 fake_opcode
.opcode
= arc_long_opcodes
[i
].limm_template
;
2268 fake_opcode
.mask
= arc_long_opcodes
[i
].limm_mask
;
2269 fake_opcode
.cpu
= opcode
->cpu
;
2270 fake_opcode
.insn_class
= opcode
->insn_class
;
2271 fake_opcode
.subclass
= opcode
->subclass
;
2272 memcpy (&fake_opcode
.operands
[0],
2273 &arc_long_opcodes
[i
].operands
,
2275 /* Leave fake_opcode.flags as zero. */
2277 pr_debug ("Calling assemble_insn to build fake limm value\n");
2278 assemble_insn (&fake_opcode
, tok
, *ntok
,
2280 pr_debug (" got limm value: 0x%x\n", insn
.insn
);
2282 /* Now create a new token at the end of the token array (We know this
2283 is safe as the token array is always created with enough space for
2284 MAX_INSN_ARGS, and we check at the start at the start of this
2285 function that we're not there yet). This new token will
2286 correspond to a LIMM operand that will be contained in the
2287 base_opcode of the arc_long_opcode. */
2288 limm_token
= &tok
[(*ntok
)];
2291 /* Modify the LIMM token to hold the constant. */
2292 limm_token
->X_op
= O_constant
;
2293 limm_token
->X_add_number
= insn
.insn
;
2295 /* Return the base opcode. */
2296 return build_fake_opcode_hash_entry (opcode
);
2302 /* Used to find special case opcode. */
2304 static const struct arc_opcode_hash_entry
*
2305 find_special_case (const char *opname
,
2307 struct arc_flags
*pflags
,
2311 const struct arc_opcode_hash_entry
*entry
;
2313 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2316 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2319 entry
= find_special_case_long_opcode (opname
, ntok
, tok
, nflgs
, pflags
);
2324 /* Given an opcode name, pre-tockenized set of argumenst and the
2325 opcode flags, take it all the way through emission. */
2328 assemble_tokens (const char *opname
,
2331 struct arc_flags
*pflags
,
2334 bfd_boolean found_something
= FALSE
;
2335 const struct arc_opcode_hash_entry
*entry
;
2338 /* Search opcodes. */
2339 entry
= arc_find_opcode (opname
);
2341 /* Couldn't find opcode conventional way, try special cases. */
2343 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2347 const struct arc_opcode
*opcode
;
2349 pr_debug ("%s:%d: assemble_tokens: %s\n",
2350 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2351 found_something
= TRUE
;
2352 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2356 struct arc_insn insn
;
2358 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2364 if (found_something
)
2367 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2369 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2373 as_bad (_("unknown opcode '%s'"), opname
);
2376 /* The public interface to the instruction assembler. */
2379 md_assemble (char *str
)
2382 expressionS tok
[MAX_INSN_ARGS
];
2385 struct arc_flags flags
[MAX_INSN_FLGS
];
2387 /* Split off the opcode. */
2388 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2389 opname
= xmemdup0 (str
, opnamelen
);
2391 /* Signalize we are assmbling the instructions. */
2392 assembling_insn
= TRUE
;
2394 /* Tokenize the flags. */
2395 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2397 as_bad (_("syntax error"));
2401 /* Scan up to the end of the mnemonic which must end in space or end
2404 for (; *str
!= '\0'; str
++)
2408 /* Tokenize the rest of the line. */
2409 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2411 as_bad (_("syntax error"));
2415 /* Finish it off. */
2416 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2417 assembling_insn
= FALSE
;
2420 /* Callback to insert a register into the hash table. */
2423 declare_register (const char *name
, int number
)
2426 symbolS
*regS
= symbol_create (name
, reg_section
,
2427 number
, &zero_address_frag
);
2429 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2431 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2435 /* Construct symbols for each of the general registers. */
2438 declare_register_set (void)
2441 for (i
= 0; i
< 64; ++i
)
2445 sprintf (name
, "r%d", i
);
2446 declare_register (name
, i
);
2447 if ((i
& 0x01) == 0)
2449 sprintf (name
, "r%dr%d", i
, i
+1);
2450 declare_register (name
, i
);
2455 /* Port-specific assembler initialization. This function is called
2456 once, at assembler startup time. */
2461 const struct arc_opcode
*opcode
= arc_opcodes
;
2463 if (!mach_type_specified_p
)
2464 arc_select_cpu ("arc700");
2466 /* The endianness can be chosen "at the factory". */
2467 target_big_endian
= byte_order
== BIG_ENDIAN
;
2469 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2470 as_warn (_("could not set architecture and machine"));
2472 /* Set elf header flags. */
2473 bfd_set_private_flags (stdoutput
, arc_eflag
);
2475 /* Set up a hash table for the instructions. */
2476 arc_opcode_hash
= hash_new ();
2477 if (arc_opcode_hash
== NULL
)
2478 as_fatal (_("Virtual memory exhausted"));
2480 /* Initialize the hash table with the insns. */
2483 const char *name
= opcode
->name
;
2485 arc_insert_opcode (opcode
);
2487 while (++opcode
&& opcode
->name
2488 && (opcode
->name
== name
2489 || !strcmp (opcode
->name
, name
)))
2491 }while (opcode
->name
);
2493 /* Register declaration. */
2494 arc_reg_hash
= hash_new ();
2495 if (arc_reg_hash
== NULL
)
2496 as_fatal (_("Virtual memory exhausted"));
2498 declare_register_set ();
2499 declare_register ("gp", 26);
2500 declare_register ("fp", 27);
2501 declare_register ("sp", 28);
2502 declare_register ("ilink", 29);
2503 declare_register ("ilink1", 29);
2504 declare_register ("ilink2", 30);
2505 declare_register ("blink", 31);
2507 /* XY memory registers. */
2508 declare_register ("x0_u0", 32);
2509 declare_register ("x0_u1", 33);
2510 declare_register ("x1_u0", 34);
2511 declare_register ("x1_u1", 35);
2512 declare_register ("x2_u0", 36);
2513 declare_register ("x2_u1", 37);
2514 declare_register ("x3_u0", 38);
2515 declare_register ("x3_u1", 39);
2516 declare_register ("y0_u0", 40);
2517 declare_register ("y0_u1", 41);
2518 declare_register ("y1_u0", 42);
2519 declare_register ("y1_u1", 43);
2520 declare_register ("y2_u0", 44);
2521 declare_register ("y2_u1", 45);
2522 declare_register ("y3_u0", 46);
2523 declare_register ("y3_u1", 47);
2524 declare_register ("x0_nu", 48);
2525 declare_register ("x1_nu", 49);
2526 declare_register ("x2_nu", 50);
2527 declare_register ("x3_nu", 51);
2528 declare_register ("y0_nu", 52);
2529 declare_register ("y1_nu", 53);
2530 declare_register ("y2_nu", 54);
2531 declare_register ("y3_nu", 55);
2533 declare_register ("mlo", 57);
2534 declare_register ("mmid", 58);
2535 declare_register ("mhi", 59);
2537 declare_register ("acc1", 56);
2538 declare_register ("acc2", 57);
2540 declare_register ("lp_count", 60);
2541 declare_register ("pcl", 63);
2543 /* Initialize the last instructions. */
2544 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2546 /* Aux register declaration. */
2547 arc_aux_hash
= hash_new ();
2548 if (arc_aux_hash
== NULL
)
2549 as_fatal (_("Virtual memory exhausted"));
2551 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2553 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2557 if (!(auxr
->cpu
& arc_target
))
2560 if ((auxr
->subclass
!= NONE
)
2561 && !check_cpu_feature (auxr
->subclass
))
2564 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2566 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2567 auxr
->name
, retval
);
2571 /* Write a value out to the object file, using the appropriate
2575 md_number_to_chars (char *buf
,
2579 if (target_big_endian
)
2580 number_to_chars_bigendian (buf
, val
, n
);
2582 number_to_chars_littleendian (buf
, val
, n
);
2585 /* Round up a section size to the appropriate boundary. */
2588 md_section_align (segT segment
,
2591 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2593 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2596 /* The location from which a PC relative jump should be calculated,
2597 given a PC relative reloc. */
2600 md_pcrel_from_section (fixS
*fixP
,
2603 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2605 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2607 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2608 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2609 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2611 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2613 /* The symbol is undefined (or is defined but not in this section).
2614 Let the linker figure it out. */
2618 if ((int) fixP
->fx_r_type
< 0)
2620 /* These are the "internal" relocations. Align them to
2621 32 bit boundary (PCL), for the moment. */
2626 switch (fixP
->fx_r_type
)
2628 case BFD_RELOC_ARC_PC32
:
2629 /* The hardware calculates relative to the start of the
2630 insn, but this relocation is relative to location of the
2631 LIMM, compensate. The base always needs to be
2632 substracted by 4 as we do not support this type of PCrel
2633 relocation for short instructions. */
2636 case BFD_RELOC_ARC_PLT32
:
2637 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2638 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2639 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2640 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2642 case BFD_RELOC_ARC_S21H_PCREL
:
2643 case BFD_RELOC_ARC_S25H_PCREL
:
2644 case BFD_RELOC_ARC_S13_PCREL
:
2645 case BFD_RELOC_ARC_S21W_PCREL
:
2646 case BFD_RELOC_ARC_S25W_PCREL
:
2650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2651 _("unhandled reloc %s in md_pcrel_from_section"),
2652 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2657 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2658 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2659 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2660 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2661 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2666 /* Given a BFD relocation find the coresponding operand. */
2668 static const struct arc_operand
*
2669 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2673 for (i
= 0; i
< arc_num_operands
; i
++)
2674 if (arc_operands
[i
].default_reloc
== reloc
)
2675 return &arc_operands
[i
];
2679 /* Insert an operand value into an instruction. */
2682 insert_operand (unsigned insn
,
2683 const struct arc_operand
*operand
,
2688 offsetT min
= 0, max
= 0;
2690 if (operand
->bits
!= 32
2691 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2692 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2694 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2696 max
= (1 << (operand
->bits
- 1)) - 1;
2697 min
= -(1 << (operand
->bits
- 1));
2701 max
= (1 << operand
->bits
) - 1;
2705 if (val
< min
|| val
> max
)
2706 as_bad_value_out_of_range (_("operand"),
2707 val
, min
, max
, file
, line
);
2710 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2711 min
, val
, max
, insn
);
2713 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2715 as_bad_where (file
, line
,
2716 _("Unaligned operand. Needs to be 32bit aligned"));
2718 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2720 as_bad_where (file
, line
,
2721 _("Unaligned operand. Needs to be 16bit aligned"));
2723 if (operand
->insert
)
2725 const char *errmsg
= NULL
;
2727 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2729 as_warn_where (file
, line
, "%s", errmsg
);
2733 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2735 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2737 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2740 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2745 /* Apply a fixup to the object code. At this point all symbol values
2746 should be fully resolved, and we attempt to completely resolve the
2747 reloc. If we can not do that, we determine the correct reloc code
2748 and put it back in the fixup. To indicate that a fixup has been
2749 eliminated, set fixP->fx_done. */
2752 md_apply_fix (fixS
*fixP
,
2756 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2757 valueT value
= *valP
;
2759 symbolS
*fx_addsy
, *fx_subsy
;
2761 segT add_symbol_segment
= absolute_section
;
2762 segT sub_symbol_segment
= absolute_section
;
2763 const struct arc_operand
*operand
= NULL
;
2764 extended_bfd_reloc_code_real_type reloc
;
2766 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2767 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2768 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2769 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2772 fx_addsy
= fixP
->fx_addsy
;
2773 fx_subsy
= fixP
->fx_subsy
;
2778 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2782 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2783 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2784 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2786 resolve_symbol_value (fx_subsy
);
2787 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2789 if (sub_symbol_segment
== absolute_section
)
2791 /* The symbol is really a constant. */
2792 fx_offset
-= S_GET_VALUE (fx_subsy
);
2797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2798 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2799 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2800 segment_name (add_symbol_segment
),
2801 S_GET_NAME (fx_subsy
),
2802 segment_name (sub_symbol_segment
));
2808 && !S_IS_WEAK (fx_addsy
))
2810 if (add_symbol_segment
== seg
2813 value
+= S_GET_VALUE (fx_addsy
);
2814 value
-= md_pcrel_from_section (fixP
, seg
);
2816 fixP
->fx_pcrel
= FALSE
;
2818 else if (add_symbol_segment
== absolute_section
)
2820 value
= fixP
->fx_offset
;
2821 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2823 fixP
->fx_pcrel
= FALSE
;
2828 fixP
->fx_done
= TRUE
;
2833 && ((S_IS_DEFINED (fx_addsy
)
2834 && S_GET_SEGMENT (fx_addsy
) != seg
)
2835 || S_IS_WEAK (fx_addsy
)))
2836 value
+= md_pcrel_from_section (fixP
, seg
);
2838 switch (fixP
->fx_r_type
)
2840 case BFD_RELOC_ARC_32_ME
:
2841 /* This is a pc-relative value in a LIMM. Adjust it to the
2842 address of the instruction not to the address of the
2843 LIMM. Note: it is not anylonger valid this afirmation as
2844 the linker consider ARC_PC32 a fixup to entire 64 bit
2846 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2849 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2851 case BFD_RELOC_ARC_PC32
:
2852 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2855 if ((int) fixP
->fx_r_type
< 0)
2856 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2862 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2863 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2864 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2865 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2869 /* Now check for TLS relocations. */
2870 reloc
= fixP
->fx_r_type
;
2873 case BFD_RELOC_ARC_TLS_DTPOFF
:
2874 case BFD_RELOC_ARC_TLS_LE_32
:
2878 case BFD_RELOC_ARC_TLS_GD_GOT
:
2879 case BFD_RELOC_ARC_TLS_IE_GOT
:
2880 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2883 case BFD_RELOC_ARC_TLS_GD_LD
:
2884 gas_assert (!fixP
->fx_offset
);
2887 = (S_GET_VALUE (fixP
->fx_subsy
)
2888 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2889 fixP
->fx_subsy
= NULL
;
2891 case BFD_RELOC_ARC_TLS_GD_CALL
:
2892 /* These two relocs are there just to allow ld to change the tls
2893 model for this symbol, by patching the code. The offset -
2894 and scale, if any - will be installed by the linker. */
2895 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2898 case BFD_RELOC_ARC_TLS_LE_S9
:
2899 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2900 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2912 /* Addjust the value if we have a constant. */
2915 /* For hosts with longs bigger than 32-bits make sure that the top
2916 bits of a 32-bit negative value read in by the parser are set,
2917 so that the correct comparisons are made. */
2918 if (value
& 0x80000000)
2919 value
|= (-1UL << 31);
2921 reloc
= fixP
->fx_r_type
;
2929 case BFD_RELOC_ARC_32_PCREL
:
2930 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2933 case BFD_RELOC_ARC_GOTPC32
:
2934 /* I cannot fix an GOTPC relocation because I need to relax it
2935 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2936 as_bad (_("Unsupported operation on reloc"));
2939 case BFD_RELOC_ARC_TLS_DTPOFF
:
2940 case BFD_RELOC_ARC_TLS_LE_32
:
2941 gas_assert (!fixP
->fx_addsy
);
2942 gas_assert (!fixP
->fx_subsy
);
2944 case BFD_RELOC_ARC_GOTOFF
:
2945 case BFD_RELOC_ARC_32_ME
:
2946 case BFD_RELOC_ARC_PC32
:
2947 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2950 case BFD_RELOC_ARC_PLT32
:
2951 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2954 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2955 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2958 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2959 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2962 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2963 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2966 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2967 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2969 case BFD_RELOC_ARC_S25W_PCREL
:
2970 case BFD_RELOC_ARC_S21W_PCREL
:
2971 case BFD_RELOC_ARC_S21H_PCREL
:
2972 case BFD_RELOC_ARC_S25H_PCREL
:
2973 case BFD_RELOC_ARC_S13_PCREL
:
2975 operand
= find_operand_for_reloc (reloc
);
2976 gas_assert (operand
);
2981 if ((int) fixP
->fx_r_type
>= 0)
2982 as_fatal (_("unhandled relocation type %s"),
2983 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2985 /* The rest of these fixups needs to be completely resolved as
2987 if (fixP
->fx_addsy
!= 0
2988 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2990 _("non-absolute expression in constant field"));
2992 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2993 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
2998 if (target_big_endian
)
3000 switch (fixP
->fx_size
)
3003 insn
= bfd_getb32 (fixpos
);
3006 insn
= bfd_getb16 (fixpos
);
3009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3010 _("unknown fixup size"));
3016 switch (fixP
->fx_size
)
3019 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3022 insn
= bfd_getl16 (fixpos
);
3025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3026 _("unknown fixup size"));
3030 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3031 fixP
->fx_file
, fixP
->fx_line
);
3033 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3036 /* Prepare machine-dependent frags for relaxation.
3038 Called just before relaxation starts. Any symbol that is now undefined
3039 will not become defined.
3041 Return the correct fr_subtype in the frag.
3043 Return the initial "guess for fr_var" to caller. The guess for fr_var
3044 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3045 or fr_var contributes to our returned value.
3047 Although it may not be explicit in the frag, pretend
3048 fr_var starts with a value. */
3051 md_estimate_size_before_relax (fragS
*fragP
,
3056 /* If the symbol is not located within the same section AND it's not
3057 an absolute section, use the maximum. OR if the symbol is a
3058 constant AND the insn is by nature not pc-rel, use the maximum.
3059 OR if the symbol is being equated against another symbol, use the
3060 maximum. OR if the symbol is weak use the maximum. */
3061 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3062 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3063 || (symbol_constant_p (fragP
->fr_symbol
)
3064 && !fragP
->tc_frag_data
.pcrel
)
3065 || symbol_equated_p (fragP
->fr_symbol
)
3066 || S_IS_WEAK (fragP
->fr_symbol
))
3068 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3069 ++fragP
->fr_subtype
;
3072 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3073 fragP
->fr_var
= growth
;
3075 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3076 fragP
->fr_file
, fragP
->fr_line
, growth
);
3081 /* Translate internal representation of relocation info to BFD target
3085 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3089 bfd_reloc_code_real_type code
;
3091 reloc
= XNEW (arelent
);
3092 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3093 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3094 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3096 /* Make sure none of our internal relocations make it this far.
3097 They'd better have been fully resolved by this point. */
3098 gas_assert ((int) fixP
->fx_r_type
> 0);
3100 code
= fixP
->fx_r_type
;
3102 /* if we have something like add gp, pcl,
3103 _GLOBAL_OFFSET_TABLE_@gotpc. */
3104 if (code
== BFD_RELOC_ARC_GOTPC32
3106 && fixP
->fx_addsy
== GOT_symbol
)
3107 code
= BFD_RELOC_ARC_GOTPC
;
3109 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3110 if (reloc
->howto
== NULL
)
3112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3113 _("cannot represent `%s' relocation in object file"),
3114 bfd_get_reloc_code_name (code
));
3118 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3119 as_fatal (_("internal error? cannot generate `%s' relocation"),
3120 bfd_get_reloc_code_name (code
));
3122 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3124 if (code
== BFD_RELOC_ARC_TLS_DTPOFF
3125 || code
== BFD_RELOC_ARC_TLS_DTPOFF_S9
)
3128 = fixP
->fx_subsy
? symbol_get_bfdsym (fixP
->fx_subsy
) : NULL
;
3129 /* We just want to store a 24 bit index, but we have to wait
3130 till after write_contents has been called via
3131 bfd_map_over_sections before we can get the index from
3132 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
3133 function is elf32-arc.c has to pick up the slack.
3134 Unfortunately, this leads to problems with hosts that have
3135 pointers wider than long (bfd_vma). There would be various
3136 ways to handle this, all error-prone :-( */
3137 reloc
->addend
= (bfd_vma
) sym
;
3138 if ((asymbol
*) reloc
->addend
!= sym
)
3140 as_bad ("Can't store pointer\n");
3145 reloc
->addend
= fixP
->fx_offset
;
3150 /* Perform post-processing of machine-dependent frags after relaxation.
3151 Called after relaxation is finished.
3152 In: Address of frag.
3153 fr_type == rs_machine_dependent.
3154 fr_subtype is what the address relaxed to.
3156 Out: Any fixS:s and constants are set up. */
3159 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3160 segT segment ATTRIBUTE_UNUSED
,
3163 const relax_typeS
*table_entry
;
3165 const struct arc_opcode
*opcode
;
3166 struct arc_insn insn
;
3168 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3170 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3171 dest
= fragP
->fr_literal
+ fix
;
3172 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3174 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3175 "var: %"BFD_VMA_FMT
"d\n",
3176 fragP
->fr_file
, fragP
->fr_line
,
3177 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3179 if (fragP
->fr_subtype
<= 0
3180 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3181 as_fatal (_("no relaxation found for this instruction."));
3183 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3185 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3186 relax_arg
->nflg
, &insn
);
3188 apply_fixups (&insn
, fragP
, fix
);
3190 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
3191 gas_assert (table_entry
->rlx_length
== size
);
3192 emit_insn0 (&insn
, dest
, TRUE
);
3194 fragP
->fr_fix
+= table_entry
->rlx_length
;
3198 /* We have no need to default values of symbols. We could catch
3199 register names here, but that is handled by inserting them all in
3200 the symbol table to begin with. */
3203 md_undefined_symbol (char *name
)
3205 /* The arc abi demands that a GOT[0] should be referencible as
3206 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3207 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3209 && (*(name
+1) == 'G')
3210 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3212 && (*(name
+1) == 'D')
3213 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3217 if (symbol_find (name
))
3218 as_bad ("GOT already in symbol table");
3220 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3221 (valueT
) 0, &zero_address_frag
);
3228 /* Turn a string in input_line_pointer into a floating point constant
3229 of type type, and store the appropriate bytes in *litP. The number
3230 of LITTLENUMS emitted is stored in *sizeP. An error message is
3231 returned, or NULL on OK. */
3234 md_atof (int type
, char *litP
, int *sizeP
)
3236 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3239 /* Called for any expression that can not be recognized. When the
3240 function is called, `input_line_pointer' will point to the start of
3244 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3246 char *p
= input_line_pointer
;
3249 input_line_pointer
++;
3250 expressionP
->X_op
= O_symbol
;
3251 expression (expressionP
);
3255 /* This function is called from the function 'expression', it attempts
3256 to parse special names (in our case register names). It fills in
3257 the expression with the identified register. It returns TRUE if
3258 it is a register and FALSE otherwise. */
3261 arc_parse_name (const char *name
,
3262 struct expressionS
*e
)
3266 if (!assembling_insn
)
3269 /* Handle only registers. */
3270 if (e
->X_op
!= O_absent
)
3273 sym
= hash_find (arc_reg_hash
, name
);
3276 e
->X_op
= O_register
;
3277 e
->X_add_number
= S_GET_VALUE (sym
);
3284 Invocation line includes a switch not recognized by the base assembler.
3285 See if it's a processor-specific option.
3287 New options (supported) are:
3289 -mcpu=<cpu name> Assemble for selected processor
3290 -EB/-mbig-endian Big-endian
3291 -EL/-mlittle-endian Little-endian
3292 -mrelax Enable relaxation
3294 The following CPU names are recognized:
3295 arc700, av2em, av2hs. */
3298 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3304 return md_parse_option (OPTION_MCPU
, "arc600");
3307 return md_parse_option (OPTION_MCPU
, "arc700");
3310 return md_parse_option (OPTION_MCPU
, "arcem");
3313 return md_parse_option (OPTION_MCPU
, "archs");
3317 arc_select_cpu (arg
);
3318 mach_type_specified_p
= TRUE
;
3323 arc_target_format
= "elf32-bigarc";
3324 byte_order
= BIG_ENDIAN
;
3328 arc_target_format
= "elf32-littlearc";
3329 byte_order
= LITTLE_ENDIAN
;
3333 /* This option has an effect only on ARC EM. */
3334 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3335 arc_features
|= ARC_CD
;
3337 as_warn (_("Code density option invalid for selected CPU"));
3341 relaxation_state
= 1;
3344 case OPTION_USER_MODE
:
3345 case OPTION_LD_EXT_MASK
:
3348 case OPTION_BARREL_SHIFT
:
3349 case OPTION_MIN_MAX
:
3354 /* Dummy options are accepted but have no effect. */
3358 arc_features
|= ARC_SPFP
;
3362 arc_features
|= ARC_DPFP
;
3365 case OPTION_XMAC_D16
:
3366 case OPTION_XMAC_24
:
3367 case OPTION_DSP_PACKA
:
3370 case OPTION_TELEPHONY
:
3371 case OPTION_XYMEMORY
:
3375 /* Dummy options are accepted but have no effect. */
3379 /* This option has an effect only on ARC EM. */
3380 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3381 arc_features
|= ARC_FPUDA
;
3383 as_warn (_("FPUDA invalid for selected CPU"));
3394 md_show_usage (FILE *stream
)
3396 fprintf (stream
, _("ARC-specific assembler options:\n"));
3398 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3400 " -mcode-density\t enable code density option for ARC EM\n");
3402 fprintf (stream
, _("\
3403 -EB assemble code for a big-endian cpu\n"));
3404 fprintf (stream
, _("\
3405 -EL assemble code for a little-endian cpu\n"));
3406 fprintf (stream
, _("\
3407 -mrelax Enable relaxation\n"));
3411 /* Find the proper relocation for the given opcode. */
3413 static extended_bfd_reloc_code_real_type
3414 find_reloc (const char *name
,
3415 const char *opcodename
,
3416 const struct arc_flags
*pflags
,
3418 extended_bfd_reloc_code_real_type reloc
)
3422 bfd_boolean found_flag
, tmp
;
3423 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3425 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3427 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3429 /* Find the entry. */
3430 if (strcmp (name
, r
->name
))
3432 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3439 unsigned * psflg
= (unsigned *)r
->flags
;
3443 for (j
= 0; j
< nflg
; j
++)
3444 if (!strcmp (pflags
[j
].name
,
3445 arc_flag_operands
[*psflg
].name
))
3466 if (reloc
!= r
->oldreloc
)
3473 if (ret
== BFD_RELOC_UNUSED
)
3474 as_bad (_("Unable to find %s relocation for instruction %s"),
3479 /* All the symbol types that are allowed to be used for
3483 may_relax_expr (expressionS tok
)
3485 /* Check if we have unrelaxable relocs. */
3510 /* Checks if flags are in line with relaxable insn. */
3513 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3514 const struct arc_flags
*pflags
,
3517 unsigned flag_class
,
3522 const struct arc_flag_operand
*flag_opand
;
3523 int i
, counttrue
= 0;
3525 /* Iterate through flags classes. */
3526 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3528 /* Iterate through flags in flag class. */
3529 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3532 flag_opand
= &arc_flag_operands
[flag
];
3533 /* Iterate through flags in ins to compare. */
3534 for (i
= 0; i
< nflgs
; ++i
)
3536 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3547 /* If counttrue == nflgs, then all flags have been found. */
3548 return (counttrue
== nflgs
? TRUE
: FALSE
);
3551 /* Checks if operands are in line with relaxable insn. */
3554 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3555 const expressionS
*tok
,
3558 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3561 while (*operand
!= EMPTY
)
3563 const expressionS
*epr
= &tok
[i
];
3565 if (i
!= 0 && i
>= ntok
)
3571 if (!(epr
->X_op
== O_multiply
3572 || epr
->X_op
== O_divide
3573 || epr
->X_op
== O_modulus
3574 || epr
->X_op
== O_add
3575 || epr
->X_op
== O_subtract
3576 || epr
->X_op
== O_symbol
))
3582 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3586 if (epr
->X_op
!= O_register
)
3591 if (epr
->X_op
!= O_register
)
3594 switch (epr
->X_add_number
)
3596 case 0: case 1: case 2: case 3:
3597 case 12: case 13: case 14: case 15:
3604 case REGISTER_NO_GP
:
3605 if ((epr
->X_op
!= O_register
)
3606 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3611 if (epr
->X_op
!= O_bracket
)
3616 /* Don't understand, bail out. */
3622 operand
= &ins
->operands
[i
];
3625 return (i
== ntok
? TRUE
: FALSE
);
3628 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3631 relax_insn_p (const struct arc_opcode
*opcode
,
3632 const expressionS
*tok
,
3634 const struct arc_flags
*pflags
,
3638 bfd_boolean rv
= FALSE
;
3640 /* Check the relaxation table. */
3641 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3643 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3645 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3646 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3647 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3648 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3651 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3652 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3653 sizeof (expressionS
) * ntok
);
3654 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3655 sizeof (struct arc_flags
) * nflg
);
3656 frag_now
->tc_frag_data
.nflg
= nflg
;
3657 frag_now
->tc_frag_data
.ntok
= ntok
;
3665 /* Turn an opcode description and a set of arguments into
3666 an instruction and a fixup. */
3669 assemble_insn (const struct arc_opcode
*opcode
,
3670 const expressionS
*tok
,
3672 const struct arc_flags
*pflags
,
3674 struct arc_insn
*insn
)
3676 const expressionS
*reloc_exp
= NULL
;
3678 const unsigned char *argidx
;
3681 unsigned char pcrel
= 0;
3682 bfd_boolean needGOTSymbol
;
3683 bfd_boolean has_delay_slot
= FALSE
;
3684 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3686 memset (insn
, 0, sizeof (*insn
));
3687 image
= opcode
->opcode
;
3689 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3690 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3693 /* Handle operands. */
3694 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3696 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3697 const expressionS
*t
= (const expressionS
*) 0;
3699 if ((operand
->flags
& ARC_OPERAND_FAKE
)
3700 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
3703 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3705 /* Duplicate operand, already inserted. */
3717 /* Regardless if we have a reloc or not mark the instruction
3718 limm if it is the case. */
3719 if (operand
->flags
& ARC_OPERAND_LIMM
)
3720 insn
->has_limm
= TRUE
;
3725 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3730 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3732 if (operand
->flags
& ARC_OPERAND_LIMM
)
3733 insn
->limm
= t
->X_add_number
;
3737 /* Ignore brackets. */
3741 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3745 /* Maybe register range. */
3746 if ((t
->X_add_number
== 0)
3747 && contains_register (t
->X_add_symbol
)
3748 && contains_register (t
->X_op_symbol
))
3752 regs
= get_register (t
->X_add_symbol
);
3754 regs
|= get_register (t
->X_op_symbol
);
3755 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3760 /* This operand needs a relocation. */
3761 needGOTSymbol
= FALSE
;
3766 if (opcode
->insn_class
== JUMP
)
3767 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3768 _("Unable to use @plt relocatio for insn %s"),
3770 needGOTSymbol
= TRUE
;
3771 reloc
= find_reloc ("plt", opcode
->name
,
3773 operand
->default_reloc
);
3778 needGOTSymbol
= TRUE
;
3779 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3782 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3783 if (ARC_SHORT (opcode
->mask
) || opcode
->insn_class
== JUMP
)
3784 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3785 _("Unable to use @pcl relocation for insn %s"),
3789 reloc
= find_reloc ("sda", opcode
->name
,
3791 operand
->default_reloc
);
3795 needGOTSymbol
= TRUE
;
3800 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3803 case O_tpoff9
: /*FIXME! Check for the conditionality of
3805 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3807 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3811 /* Just consider the default relocation. */
3812 reloc
= operand
->default_reloc
;
3816 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3817 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3824 /* sanity checks. */
3825 reloc_howto_type
*reloc_howto
3826 = bfd_reloc_type_lookup (stdoutput
,
3827 (bfd_reloc_code_real_type
) reloc
);
3828 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3829 if (reloc_howto
->rightshift
)
3830 reloc_bitsize
-= reloc_howto
->rightshift
;
3831 if (reloc_bitsize
!= operand
->bits
)
3833 as_bad (_("invalid relocation %s for field"),
3834 bfd_get_reloc_code_name (reloc
));
3839 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3840 as_fatal (_("too many fixups"));
3842 struct arc_fixup
*fixup
;
3843 fixup
= &insn
->fixups
[insn
->nfixups
++];
3845 fixup
->reloc
= reloc
;
3846 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3847 fixup
->pcrel
= pcrel
;
3848 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3855 for (i
= 0; i
< nflg
; i
++)
3857 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3859 /* Check if the instruction has a delay slot. */
3860 if (!strcmp (flg_operand
->name
, "d"))
3861 has_delay_slot
= TRUE
;
3863 /* There is an exceptional case when we cannot insert a flag
3864 just as it is. The .T flag must be handled in relation with
3865 the relative address. */
3866 if (!strcmp (flg_operand
->name
, "t")
3867 || !strcmp (flg_operand
->name
, "nt"))
3869 unsigned bitYoperand
= 0;
3870 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3871 if (!strcmp (flg_operand
->name
, "t"))
3872 if (!strcmp (opcode
->name
, "bbit0")
3873 || !strcmp (opcode
->name
, "bbit1"))
3874 bitYoperand
= arc_NToperand
;
3876 bitYoperand
= arc_Toperand
;
3878 if (!strcmp (opcode
->name
, "bbit0")
3879 || !strcmp (opcode
->name
, "bbit1"))
3880 bitYoperand
= arc_Toperand
;
3882 bitYoperand
= arc_NToperand
;
3884 gas_assert (reloc_exp
!= NULL
);
3885 if (reloc_exp
->X_op
== O_constant
)
3887 /* Check if we have a constant and solved it
3889 offsetT val
= reloc_exp
->X_add_number
;
3890 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3895 struct arc_fixup
*fixup
;
3897 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3898 as_fatal (_("too many fixups"));
3900 fixup
= &insn
->fixups
[insn
->nfixups
++];
3901 fixup
->exp
= *reloc_exp
;
3902 fixup
->reloc
= -bitYoperand
;
3903 fixup
->pcrel
= pcrel
;
3904 fixup
->islong
= FALSE
;
3908 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3909 << flg_operand
->shift
;
3912 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3914 /* Short instruction? */
3915 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
3919 /* Update last insn status. */
3920 arc_last_insns
[1] = arc_last_insns
[0];
3921 arc_last_insns
[0].opcode
= opcode
;
3922 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3923 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3925 /* Check if the current instruction is legally used. */
3926 if (arc_last_insns
[1].has_delay_slot
3927 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3928 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3929 _("A jump/branch instruction in delay slot."));
3933 arc_handle_align (fragS
* fragP
)
3935 if ((fragP
)->fr_type
== rs_align_code
)
3937 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3938 valueT count
= ((fragP
)->fr_next
->fr_address
3939 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3941 (fragP
)->fr_var
= 2;
3943 if (count
& 1)/* Padding in the gap till the next 2-byte
3944 boundary with 0s. */
3949 /* Writing nop_s. */
3950 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
3954 /* Here we decide which fixups can be adjusted to make them relative
3955 to the beginning of the section instead of the symbol. Basically
3956 we need to make sure that the dynamic relocations are done
3957 correctly, so in some cases we force the original symbol to be
3961 tc_arc_fix_adjustable (fixS
*fixP
)
3964 /* Prevent all adjustments to global symbols. */
3965 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
3967 if (S_IS_WEAK (fixP
->fx_addsy
))
3970 /* Adjust_reloc_syms doesn't know about the GOT. */
3971 switch (fixP
->fx_r_type
)
3973 case BFD_RELOC_ARC_GOTPC32
:
3974 case BFD_RELOC_ARC_PLT32
:
3975 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3976 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3977 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3978 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3988 /* Compute the reloc type of an expression EXP. */
3991 arc_check_reloc (expressionS
*exp
,
3992 bfd_reloc_code_real_type
*r_type_p
)
3994 if (*r_type_p
== BFD_RELOC_32
3995 && exp
->X_op
== O_subtract
3996 && exp
->X_op_symbol
!= NULL
3997 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
3998 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4002 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4005 arc_cons_fix_new (fragS
*frag
,
4009 bfd_reloc_code_real_type r_type
)
4011 r_type
= BFD_RELOC_UNUSED
;
4016 r_type
= BFD_RELOC_8
;
4020 r_type
= BFD_RELOC_16
;
4024 r_type
= BFD_RELOC_24
;
4028 r_type
= BFD_RELOC_32
;
4029 arc_check_reloc (exp
, &r_type
);
4033 r_type
= BFD_RELOC_64
;
4037 as_bad (_("unsupported BFD relocation size %u"), size
);
4038 r_type
= BFD_RELOC_UNUSED
;
4041 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4044 /* The actual routine that checks the ZOL conditions. */
4047 check_zol (symbolS
*s
)
4049 switch (arc_mach_type
)
4051 case bfd_mach_arc_arcv2
:
4052 if (arc_target
& ARC_OPCODE_ARCv2EM
)
4055 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4056 || arc_last_insns
[1].has_delay_slot
)
4057 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4061 case bfd_mach_arc_arc600
:
4063 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4064 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4067 if (arc_last_insns
[0].has_limm
4068 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4069 as_bad (_("A jump instruction with long immediate detected at the \
4070 end of the ZOL label @%s"), S_GET_NAME (s
));
4073 case bfd_mach_arc_nps400
:
4074 case bfd_mach_arc_arc700
:
4075 if (arc_last_insns
[0].has_delay_slot
)
4076 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4085 /* If ZOL end check the last two instruction for illegals. */
4087 arc_frob_label (symbolS
* sym
)
4089 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4092 dwarf2_emit_label (sym
);
4095 /* Used because generic relaxation assumes a pc-rel value whilst we
4096 also relax instructions that use an absolute value resolved out of
4097 relative values (if that makes any sense). An example: 'add r1,
4098 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4099 but if they're in the same section we can subtract the section
4100 offset relocation which ends up in a resolved value. So if @.L2 is
4101 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4102 .text + 0x40 = 0x10. */
4104 arc_pcrel_adjust (fragS
*fragP
)
4106 if (!fragP
->tc_frag_data
.pcrel
)
4107 return fragP
->fr_address
+ fragP
->fr_fix
;
4112 /* Initialize the DWARF-2 unwind information for this procedure. */
4115 tc_arc_frame_initial_instructions (void)
4117 /* Stack pointer is register 28. */
4118 cfi_add_CFA_def_cfa_register (28);
4122 tc_arc_regname_to_dw2regnum (char *regname
)
4126 sym
= hash_find (arc_reg_hash
, regname
);
4128 return S_GET_VALUE (sym
);
4133 /* Adjust the symbol table. Delete found AUX register symbols. */
4136 arc_adjust_symtab (void)
4140 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4142 /* I've created a symbol during parsing process. Now, remove
4143 the symbol as it is found to be an AUX register. */
4144 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4145 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4148 /* Now do generic ELF adjustments. */
4149 elf_adjust_symtab ();
4153 tokenize_extinsn (extInstruction_t
*einsn
)
4157 unsigned char major_opcode
;
4158 unsigned char sub_opcode
;
4159 unsigned char syntax_class
= 0;
4160 unsigned char syntax_class_modifiers
= 0;
4161 unsigned char suffix_class
= 0;
4166 /* 1st: get instruction name. */
4167 p
= input_line_pointer
;
4168 c
= get_symbol_name (&p
);
4170 insn_name
= xstrdup (p
);
4171 restore_line_pointer (c
);
4173 /* 2nd: get major opcode. */
4174 if (*input_line_pointer
!= ',')
4176 as_bad (_("expected comma after instruction name"));
4177 ignore_rest_of_line ();
4180 input_line_pointer
++;
4181 major_opcode
= get_absolute_expression ();
4183 /* 3rd: get sub-opcode. */
4186 if (*input_line_pointer
!= ',')
4188 as_bad (_("expected comma after major opcode"));
4189 ignore_rest_of_line ();
4192 input_line_pointer
++;
4193 sub_opcode
= get_absolute_expression ();
4195 /* 4th: get suffix class. */
4198 if (*input_line_pointer
!= ',')
4200 as_bad ("expected comma after sub opcode");
4201 ignore_rest_of_line ();
4204 input_line_pointer
++;
4210 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4212 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4213 suffixclass
[i
].len
))
4215 suffix_class
|= suffixclass
[i
].attr_class
;
4216 input_line_pointer
+= suffixclass
[i
].len
;
4221 if (i
== ARRAY_SIZE (suffixclass
))
4223 as_bad ("invalid suffix class");
4224 ignore_rest_of_line ();
4230 if (*input_line_pointer
== '|')
4231 input_line_pointer
++;
4236 /* 5th: get syntax class and syntax class modifiers. */
4237 if (*input_line_pointer
!= ',')
4239 as_bad ("expected comma after suffix class");
4240 ignore_rest_of_line ();
4243 input_line_pointer
++;
4249 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4251 if (!strncmp (syntaxclassmod
[i
].name
,
4253 syntaxclassmod
[i
].len
))
4255 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4256 input_line_pointer
+= syntaxclassmod
[i
].len
;
4261 if (i
== ARRAY_SIZE (syntaxclassmod
))
4263 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4265 if (!strncmp (syntaxclass
[i
].name
,
4267 syntaxclass
[i
].len
))
4269 syntax_class
|= syntaxclass
[i
].attr_class
;
4270 input_line_pointer
+= syntaxclass
[i
].len
;
4275 if (i
== ARRAY_SIZE (syntaxclass
))
4277 as_bad ("missing syntax class");
4278 ignore_rest_of_line ();
4285 if (*input_line_pointer
== '|')
4286 input_line_pointer
++;
4291 demand_empty_rest_of_line ();
4293 einsn
->name
= insn_name
;
4294 einsn
->major
= major_opcode
;
4295 einsn
->minor
= sub_opcode
;
4296 einsn
->syntax
= syntax_class
;
4297 einsn
->modsyn
= syntax_class_modifiers
;
4298 einsn
->suffix
= suffix_class
;
4299 einsn
->flags
= syntax_class
4300 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4303 /* Generate an extension section. */
4306 arc_set_ext_seg (void)
4308 if (!arcext_section
)
4310 arcext_section
= subseg_new (".arcextmap", 0);
4311 bfd_set_section_flags (stdoutput
, arcext_section
,
4312 SEC_READONLY
| SEC_HAS_CONTENTS
);
4315 subseg_set (arcext_section
, 0);
4319 /* Create an extension instruction description in the arc extension
4320 section of the output file.
4321 The structure for an instruction is like this:
4322 [0]: Length of the record.
4323 [1]: Type of the record.
4327 [4]: Syntax (flags).
4328 [5]+ Name instruction.
4330 The sequence is terminated by an empty entry. */
4333 create_extinst_section (extInstruction_t
*einsn
)
4336 segT old_sec
= now_seg
;
4337 int old_subsec
= now_subseg
;
4339 int name_len
= strlen (einsn
->name
);
4344 *p
= 5 + name_len
+ 1;
4346 *p
= EXT_INSTRUCTION
;
4353 p
= frag_more (name_len
+ 1);
4354 strcpy (p
, einsn
->name
);
4356 subseg_set (old_sec
, old_subsec
);
4359 /* Handler .extinstruction pseudo-op. */
4362 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4364 extInstruction_t einsn
;
4365 struct arc_opcode
*arc_ext_opcodes
;
4366 const char *errmsg
= NULL
;
4367 unsigned char moplow
, mophigh
;
4369 memset (&einsn
, 0, sizeof (einsn
));
4370 tokenize_extinsn (&einsn
);
4372 /* Check if the name is already used. */
4373 if (arc_find_opcode (einsn
.name
))
4374 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4376 /* Check the opcode ranges. */
4378 mophigh
= (arc_target
& (ARC_OPCODE_ARCv2EM
4379 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4381 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4382 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4384 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4385 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4386 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4388 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4390 case ARC_SYNTAX_3OP
:
4391 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4392 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4394 case ARC_SYNTAX_2OP
:
4395 case ARC_SYNTAX_1OP
:
4396 case ARC_SYNTAX_NOP
:
4397 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4398 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4404 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, arc_target
, &errmsg
);
4405 if (arc_ext_opcodes
== NULL
)
4408 as_fatal ("%s", errmsg
);
4410 as_fatal (_("Couldn't generate extension instruction opcodes"));
4413 as_warn ("%s", errmsg
);
4415 /* Insert the extension instruction. */
4416 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4418 create_extinst_section (&einsn
);
4422 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4428 int number
, imode
= 0;
4429 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4430 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4431 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4433 /* 1st: get register name. */
4435 p
= input_line_pointer
;
4436 c
= get_symbol_name (&p
);
4439 restore_line_pointer (c
);
4441 /* 2nd: get register number. */
4444 if (*input_line_pointer
!= ',')
4446 as_bad (_("expected comma after register name"));
4447 ignore_rest_of_line ();
4451 input_line_pointer
++;
4452 number
= get_absolute_expression ();
4456 as_bad (_("negative operand number %d"), number
);
4457 ignore_rest_of_line ();
4464 /* 3rd: get register mode. */
4467 if (*input_line_pointer
!= ',')
4469 as_bad (_("expected comma after register number"));
4470 ignore_rest_of_line ();
4475 input_line_pointer
++;
4476 mode
= input_line_pointer
;
4478 if (!strncmp (mode
, "r|w", 3))
4481 input_line_pointer
+= 3;
4483 else if (!strncmp (mode
, "r", 1))
4485 imode
= ARC_REGISTER_READONLY
;
4486 input_line_pointer
+= 1;
4488 else if (strncmp (mode
, "w", 1))
4490 as_bad (_("invalid mode"));
4491 ignore_rest_of_line ();
4497 imode
= ARC_REGISTER_WRITEONLY
;
4498 input_line_pointer
+= 1;
4504 /* 4th: get core register shortcut. */
4506 if (*input_line_pointer
!= ',')
4508 as_bad (_("expected comma after register mode"));
4509 ignore_rest_of_line ();
4514 input_line_pointer
++;
4516 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4518 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4519 input_line_pointer
+= 15;
4521 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4523 as_bad (_("shortcut designator invalid"));
4524 ignore_rest_of_line ();
4530 input_line_pointer
+= 12;
4533 demand_empty_rest_of_line ();
4536 ereg
->number
= number
;
4537 ereg
->imode
= imode
;
4540 /* Create an extension register/condition description in the arc
4541 extension section of the output file.
4543 The structure for an instruction is like this:
4544 [0]: Length of the record.
4545 [1]: Type of the record.
4547 For core regs and condition codes:
4551 For auxilirary registers:
4555 The sequence is terminated by an empty entry. */
4558 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4560 segT old_sec
= now_seg
;
4561 int old_subsec
= now_subseg
;
4563 int name_len
= strlen (ereg
->name
);
4570 case EXT_CORE_REGISTER
:
4572 *p
= 3 + name_len
+ 1;
4578 case EXT_AUX_REGISTER
:
4580 *p
= 6 + name_len
+ 1;
4582 *p
= EXT_AUX_REGISTER
;
4584 *p
= (ereg
->number
>> 24) & 0xff;
4586 *p
= (ereg
->number
>> 16) & 0xff;
4588 *p
= (ereg
->number
>> 8) & 0xff;
4590 *p
= (ereg
->number
) & 0xff;
4596 p
= frag_more (name_len
+ 1);
4597 strcpy (p
, ereg
->name
);
4599 subseg_set (old_sec
, old_subsec
);
4602 /* Handler .extCoreRegister pseudo-op. */
4605 arc_extcorereg (int opertype
)
4608 struct arc_aux_reg
*auxr
;
4610 struct arc_flag_operand
*ccode
;
4612 memset (&ereg
, 0, sizeof (ereg
));
4613 tokenize_extregister (&ereg
, opertype
);
4617 case EXT_CORE_REGISTER
:
4618 /* Core register. */
4619 if (ereg
.number
> 60)
4620 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4622 declare_register (ereg
.name
, ereg
.number
);
4624 case EXT_AUX_REGISTER
:
4625 /* Auxiliary register. */
4626 auxr
= XNEW (struct arc_aux_reg
);
4627 auxr
->name
= ereg
.name
;
4628 auxr
->cpu
= arc_target
;
4629 auxr
->subclass
= NONE
;
4630 auxr
->address
= ereg
.number
;
4631 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4633 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4634 auxr
->name
, retval
);
4637 /* Condition code. */
4638 if (ereg
.number
> 31)
4639 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4641 ext_condcode
.size
++;
4642 ext_condcode
.arc_ext_condcode
=
4643 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4644 ext_condcode
.size
+ 1);
4645 if (ext_condcode
.arc_ext_condcode
== NULL
)
4646 as_fatal (_("Virtual memory exhausted"));
4648 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4649 ccode
->name
= ereg
.name
;
4650 ccode
->code
= ereg
.number
;
4653 ccode
->favail
= 0; /* not used. */
4655 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4658 as_bad (_("Unknown extension"));
4661 create_extcore_section (&ereg
, opertype
);
4665 eval: (c-set-style "gnu")