1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27 #include "safe-ctype.h"
29 #include "opcode/arc.h"
30 #include "opcode/arc-attrs.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 #ifndef TARGET_WITH_CPU
52 #define TARGET_WITH_CPU "arc700"
53 #endif /* TARGET_WITH_CPU */
55 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57 #define streq(a, b) (strcmp (a, b) == 0)
59 /* Enum used to enumerate the relaxable ins operands. */
64 REGISTER_S
, /* Register for short instruction(s). */
65 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
66 REGISTER_DUP
, /* Duplication of previous operand of type register. */
100 #define regno(x) ((x) & 0x3F)
101 #define is_ir_num(x) (((x) & ~0x3F) == 0)
102 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103 #define is_spfp_p(op) (((sc) == SPX))
104 #define is_dpfp_p(op) (((sc) == DPX))
105 #define is_fpuda_p(op) (((sc) == DPA))
106 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
118 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
119 #define is_nps400_p(op) (((sc) == NPS400))
121 /* Generic assembler global variables which must be defined by all
124 /* Characters which always start a comment. */
125 const char comment_chars
[] = "#;";
127 /* Characters which start a comment at the beginning of a line. */
128 const char line_comment_chars
[] = "#";
130 /* Characters which may be used to separate multiple commands on a
132 const char line_separator_chars
[] = "`";
134 /* Characters which are used to indicate an exponent in a floating
136 const char EXP_CHARS
[] = "eE";
138 /* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
140 const char FLT_CHARS
[] = "rRsSfFdD";
143 extern int target_big_endian
;
144 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
145 static int byte_order
= DEFAULT_BYTE_ORDER
;
147 /* Arc extension section. */
148 static segT arcext_section
;
150 /* By default relaxation is disabled. */
151 static int relaxation_state
= 0;
153 extern int arc_get_mach (char *);
155 /* Forward declarations. */
156 static void arc_lcomm (int);
157 static void arc_option (int);
158 static void arc_extra_reloc (int);
159 static void arc_extinsn (int);
160 static void arc_extcorereg (int);
161 static void arc_attribute (int);
163 const pseudo_typeS md_pseudo_table
[] =
165 /* Make sure that .word is 32 bits. */
168 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm
, 0 },
170 { "lcommon", arc_lcomm
, 0 },
171 { "cpu", arc_option
, 0 },
173 { "arc_attribute", arc_attribute
, 0 },
174 { "extinstruction", arc_extinsn
, 0 },
175 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
176 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
177 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
179 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
180 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
185 const char *md_shortopts
= "";
189 OPTION_EB
= OPTION_MD_BASE
,
207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
231 struct option md_longopts
[] =
233 { "EB", no_argument
, NULL
, OPTION_EB
},
234 { "EL", no_argument
, NULL
, OPTION_EL
},
235 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
236 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
237 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
238 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
239 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
240 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
241 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
242 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
243 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
244 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
245 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
247 /* Floating point options */
248 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
249 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
250 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
251 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
252 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
253 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
254 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
255 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
256 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
257 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
258 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
263 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
264 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
265 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
266 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
267 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
268 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
269 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
270 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
271 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
272 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
273 { "mea", no_argument
, NULL
, OPTION_EA
},
274 { "mEA", no_argument
, NULL
, OPTION_EA
},
275 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
276 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
277 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
278 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
279 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
280 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
281 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
282 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
283 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
284 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
285 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
286 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
287 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
288 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
289 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
291 { NULL
, no_argument
, NULL
, 0 }
294 size_t md_longopts_size
= sizeof (md_longopts
);
296 /* Local data and data types. */
298 /* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300 typedef int extended_bfd_reloc_code_real_type
;
306 extended_bfd_reloc_code_real_type reloc
;
308 /* index into arc_operands. */
309 unsigned int opindex
;
311 /* PC-relative, used by internals fixups. */
314 /* TRUE if this fixup is for LIMM operand. */
320 unsigned long long int insn
;
322 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
324 unsigned int len
; /* Length of instruction in bytes. */
325 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
327 bfd_boolean relax
; /* Boolean value: TRUE if needs
331 /* Structure to hold any last two instructions. */
332 static struct arc_last_insn
334 /* Saved instruction opcode. */
335 const struct arc_opcode
*opcode
;
337 /* Boolean value: TRUE if current insn is short. */
338 bfd_boolean has_limm
;
340 /* Boolean value: TRUE if current insn has delay slot. */
341 bfd_boolean has_delay_slot
;
344 /* Extension instruction suffix classes. */
352 static const attributes_t suffixclass
[] =
354 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
355 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
356 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
359 /* Extension instruction syntax classes. */
360 static const attributes_t syntaxclass
[] =
362 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
363 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
364 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
365 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
368 /* Extension instruction syntax classes modifiers. */
369 static const attributes_t syntaxclassmod
[] =
371 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
372 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
375 /* Extension register type. */
383 /* A structure to hold the additional conditional codes. */
386 struct arc_flag_operand
*arc_ext_condcode
;
388 } ext_condcode
= { NULL
, 0 };
390 /* Structure to hold an entry in ARC_OPCODE_HASH. */
391 struct arc_opcode_hash_entry
393 /* The number of pointers in the OPCODE list. */
396 /* Points to a list of opcode pointers. */
397 const struct arc_opcode
**opcode
;
400 /* Structure used for iterating through an arc_opcode_hash_entry. */
401 struct arc_opcode_hash_entry_iterator
403 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
406 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
407 returned by this iterator. */
408 const struct arc_opcode
*opcode
;
411 /* Forward declaration. */
412 static void assemble_insn
413 (const struct arc_opcode
*, const expressionS
*, int,
414 const struct arc_flags
*, int, struct arc_insn
*);
416 /* The selection of the machine type can come from different sources. This
417 enum is used to track how the selection was made in order to perform
419 enum mach_selection_type
422 MACH_SELECTION_FROM_DEFAULT
,
423 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
424 MACH_SELECTION_FROM_COMMAND_LINE
427 /* How the current machine type was selected. */
428 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
430 /* The hash table of instruction opcodes. */
431 static struct hash_control
*arc_opcode_hash
;
433 /* The hash table of register symbols. */
434 static struct hash_control
*arc_reg_hash
;
436 /* The hash table of aux register symbols. */
437 static struct hash_control
*arc_aux_hash
;
439 /* The hash table of address types. */
440 static struct hash_control
*arc_addrtype_hash
;
442 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
444 E_ARC_MACH_ARC600, EXTRA}
445 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
447 E_ARC_MACH_ARC700, EXTRA}
448 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
449 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
450 EF_ARC_CPU_ARCV2EM, EXTRA}
451 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
452 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
453 EF_ARC_CPU_ARCV2HS, EXTRA}
454 #define ARC_CPU_TYPE_NONE \
457 /* A table of CPU names and opcode sets. */
458 static const struct cpu_type
468 #include "elf/arc-cpu.def"
471 /* Information about the cpu/variant we're assembling for. */
472 static struct cpu_type selected_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
474 /* TRUE if current assembly code uses RF16 only registers. */
475 static bfd_boolean rf16_only
= TRUE
;
478 static unsigned mpy_option
= 0;
481 static unsigned pic_option
= 0;
483 /* Use small data. */
484 static unsigned sda_option
= 0;
487 static unsigned tls_option
= 0;
489 /* Command line given features. */
490 static unsigned cl_features
= 0;
492 /* Used by the arc_reloc_op table. Order is important. */
493 #define O_gotoff O_md1 /* @gotoff relocation. */
494 #define O_gotpc O_md2 /* @gotpc relocation. */
495 #define O_plt O_md3 /* @plt relocation. */
496 #define O_sda O_md4 /* @sda relocation. */
497 #define O_pcl O_md5 /* @pcl relocation. */
498 #define O_tlsgd O_md6 /* @tlsgd relocation. */
499 #define O_tlsie O_md7 /* @tlsie relocation. */
500 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
501 #define O_tpoff O_md9 /* @tpoff relocation. */
502 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
503 #define O_dtpoff O_md11 /* @dtpoff relocation. */
504 #define O_last O_dtpoff
506 /* Used to define a bracket as operand in tokens. */
507 #define O_bracket O_md32
509 /* Used to define a colon as an operand in tokens. */
510 #define O_colon O_md31
512 /* Used to define address types in nps400. */
513 #define O_addrtype O_md30
515 /* Dummy relocation, to be sorted out. */
516 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
518 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
520 /* A table to map the spelling of a relocation operand into an appropriate
521 bfd_reloc_code_real_type type. The table is assumed to be ordered such
522 that op-O_literal indexes into it. */
523 #define ARC_RELOC_TABLE(op) \
524 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
526 : (int) (op) - (int) O_gotoff) ])
528 #define DEF(NAME, RELOC, REQ) \
529 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
531 static const struct arc_reloc_op_tag
533 /* String to lookup. */
535 /* Size of the string. */
537 /* Which operator to use. */
539 extended_bfd_reloc_code_real_type reloc
;
540 /* Allows complex relocation expression like identifier@reloc +
542 unsigned int complex_expr
: 1;
546 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
547 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
548 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
549 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
550 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
551 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
552 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
553 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
554 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
555 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
556 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
559 static const int arc_num_reloc_op
560 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
562 /* Structure for relaxable instruction that have to be swapped with a
563 smaller alternative instruction. */
564 struct arc_relaxable_ins
566 /* Mnemonic that should be checked. */
567 const char *mnemonic_r
;
569 /* Operands that should be checked.
570 Indexes of operands from operand array. */
571 enum rlx_operand_type operands
[6];
573 /* Flags that should be checked. */
574 unsigned flag_classes
[5];
576 /* Mnemonic (smaller) alternative to be used later for relaxation. */
577 const char *mnemonic_alt
;
579 /* Index of operand that generic relaxation has to check. */
582 /* Base subtype index used. */
583 enum arc_rlx_types subtype
;
586 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
587 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
588 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
592 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
593 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
594 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
599 /* ARC relaxation table. */
600 const relax_typeS md_relax_table
[] =
607 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
608 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
612 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
613 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
618 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
619 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
620 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
622 /* LD_S a, [b, u7] ->
623 LD<zz><.x><.aa><.di> a, [b, s9] ->
624 LD<zz><.x><.aa><.di> a, [b, limm] */
625 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
626 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
627 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
632 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
633 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
634 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
638 SUB<.f> a, b, limm. */
639 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
640 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
641 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
643 /* MPY<.f> a, b, u6 ->
644 MPY<.f> a, b, limm. */
645 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
646 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
648 /* MOV<.f><.cc> b, u6 ->
649 MOV<.f><.cc> b, limm. */
650 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
651 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
653 /* ADD<.f><.cc> b, b, u6 ->
654 ADD<.f><.cc> b, b, limm. */
655 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
656 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
659 /* Order of this table's entries matters! */
660 const struct arc_relaxable_ins arc_relaxable_insns
[] =
662 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
663 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
664 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
665 2, ARC_RLX_ADD_RRU6
},
666 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
668 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
670 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
671 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
672 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
673 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
674 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
675 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
676 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
677 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
679 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
681 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
685 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
687 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
688 symbolS
* GOT_symbol
= 0;
690 /* Set to TRUE when we assemble instructions. */
691 static bfd_boolean assembling_insn
= FALSE
;
693 /* List with attributes set explicitly. */
694 static bfd_boolean attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
696 /* Functions implementation. */
698 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
699 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
700 are no matching entries in ARC_OPCODE_HASH. */
702 static const struct arc_opcode_hash_entry
*
703 arc_find_opcode (const char *name
)
705 const struct arc_opcode_hash_entry
*entry
;
707 entry
= hash_find (arc_opcode_hash
, name
);
711 /* Initialise the iterator ITER. */
714 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
720 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
721 calls to this function. Return NULL when all ARC_OPCODE entries have
724 static const struct arc_opcode
*
725 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
726 struct arc_opcode_hash_entry_iterator
*iter
)
728 if (iter
->opcode
== NULL
&& iter
->index
== 0)
730 gas_assert (entry
->count
> 0);
731 iter
->opcode
= entry
->opcode
[iter
->index
];
733 else if (iter
->opcode
!= NULL
)
735 const char *old_name
= iter
->opcode
->name
;
738 if (iter
->opcode
->name
== NULL
739 || strcmp (old_name
, iter
->opcode
->name
) != 0)
742 if (iter
->index
== entry
->count
)
745 iter
->opcode
= entry
->opcode
[iter
->index
];
752 /* Insert an opcode into opcode hash structure. */
755 arc_insert_opcode (const struct arc_opcode
*opcode
)
757 const char *name
, *retval
;
758 struct arc_opcode_hash_entry
*entry
;
761 entry
= hash_find (arc_opcode_hash
, name
);
764 entry
= XNEW (struct arc_opcode_hash_entry
);
766 entry
->opcode
= NULL
;
768 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
770 as_fatal (_("internal error: can't hash opcode '%s': %s"),
774 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
777 if (entry
->opcode
== NULL
)
778 as_fatal (_("Virtual memory exhausted"));
780 entry
->opcode
[entry
->count
] = opcode
;
785 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
786 value, is encoded as 'middle-endian' for a little-endian target. This
787 function is used for regular 4, 6, and 8 byte instructions as well. */
790 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
795 md_number_to_chars (buf
, val
, n
);
798 md_number_to_chars (buf
, (val
& 0xffff00000000ull
) >> 32, 2);
799 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
802 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
803 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
806 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000ull
) >> 32, 4);
807 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
814 /* Check if a feature is allowed for a specific CPU. */
817 arc_check_feature (void)
821 if (!selected_cpu
.features
822 || !selected_cpu
.name
)
825 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
826 if ((selected_cpu
.features
& feature_list
[i
].feature
)
827 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
828 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
831 for (i
= 0; i
< ARRAY_SIZE (conflict_list
); i
++)
832 if ((selected_cpu
.features
& conflict_list
[i
]) == conflict_list
[i
])
833 as_bad(_("conflicting ISA extension attributes."));
836 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
837 the relevant static global variables. Parameter SEL describes where
838 this selection originated from. */
841 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
845 /* We should only set a default if we've not made a selection from some
847 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
848 || mach_selection_mode
== MACH_SELECTION_NONE
);
850 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
851 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
852 as_bad (_("Multiple .cpu directives found"));
854 /* Look for a matching entry in CPU_TYPES array. */
855 for (i
= 0; cpu_types
[i
].name
; ++i
)
857 if (!strcasecmp (cpu_types
[i
].name
, arg
))
859 /* If a previous selection was made on the command line, then we
860 allow later selections on the command line to override earlier
861 ones. However, a selection from a '.cpu NAME' directive must
862 match the command line selection, or we give a warning. */
863 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
865 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
866 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
867 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
868 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
870 as_warn (_("Command-line value overrides \".cpu\" directive"));
875 /* Initialise static global data about selected machine type. */
876 selected_cpu
.flags
= cpu_types
[i
].flags
;
877 selected_cpu
.name
= cpu_types
[i
].name
;
878 selected_cpu
.features
= cpu_types
[i
].features
| cl_features
;
879 selected_cpu
.mach
= cpu_types
[i
].mach
;
880 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_MACH_MSK
)
881 | cpu_types
[i
].eflags
);
886 if (!cpu_types
[i
].name
)
887 as_fatal (_("unknown architecture: %s\n"), arg
);
889 /* Check if set features are compatible with the chosen CPU. */
890 arc_check_feature ();
892 mach_selection_mode
= sel
;
895 /* Here ends all the ARCompact extension instruction assembling
899 arc_extra_reloc (int r_type
)
902 symbolS
*sym
, *lab
= NULL
;
904 if (*input_line_pointer
== '@')
905 input_line_pointer
++;
906 c
= get_symbol_name (&sym_name
);
907 sym
= symbol_find_or_make (sym_name
);
908 restore_line_pointer (c
);
909 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
911 ++input_line_pointer
;
913 c
= get_symbol_name (&lab_name
);
914 lab
= symbol_find_or_make (lab_name
);
915 restore_line_pointer (c
);
918 /* These relocations exist as a mechanism for the compiler to tell the
919 linker how to patch the code if the tls model is optimised. However,
920 the relocation itself does not require any space within the assembler
921 fragment, and so we pass a size of 0.
923 The lines that generate these relocations look like this:
925 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
927 The '.tls_gd_ld @.tdata' is processed first and generates the
928 additional relocation, while the 'bl __tls_get_addr@plt' is processed
929 second and generates the additional branch.
931 It is possible that the additional relocation generated by the
932 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
933 while the 'bl __tls_get_addr@plt' will be generated as the first thing
934 in the next fragment. This will be fine; both relocations will still
935 appear to be at the same address in the generated object file.
936 However, this only works as the additional relocation is generated
937 with size of 0 bytes. */
939 = fix_new (frag_now
, /* Which frag? */
940 frag_now_fix (), /* Where in that frag? */
941 0, /* size: 1, 2, or 4 usually. */
942 sym
, /* X_add_symbol. */
943 0, /* X_add_number. */
944 FALSE
, /* TRUE if PC-relative relocation. */
945 r_type
/* Relocation type. */);
946 fixP
->fx_subsy
= lab
;
950 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
951 symbolS
*symbolP
, addressT size
)
956 if (*input_line_pointer
== ',')
958 align
= parse_align (1);
960 if (align
== (addressT
) -1)
975 bss_alloc (symbolP
, size
, align
);
976 S_CLEAR_EXTERNAL (symbolP
);
982 arc_lcomm (int ignore
)
984 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
987 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
990 /* Select the cpu we're assembling for. */
993 arc_option (int ignore ATTRIBUTE_UNUSED
)
997 const char *cpu_name
;
999 c
= get_symbol_name (&cpu
);
1002 if ((!strcmp ("ARC600", cpu
))
1003 || (!strcmp ("ARC601", cpu
))
1004 || (!strcmp ("A6", cpu
)))
1005 cpu_name
= "arc600";
1006 else if ((!strcmp ("ARC700", cpu
))
1007 || (!strcmp ("A7", cpu
)))
1008 cpu_name
= "arc700";
1009 else if (!strcmp ("EM", cpu
))
1011 else if (!strcmp ("HS", cpu
))
1013 else if (!strcmp ("NPS400", cpu
))
1014 cpu_name
= "nps400";
1016 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1018 restore_line_pointer (c
);
1019 demand_empty_rest_of_line ();
1022 /* Smartly print an expression. */
1025 debug_exp (expressionS
*t
)
1027 const char *name ATTRIBUTE_UNUSED
;
1028 const char *namemd ATTRIBUTE_UNUSED
;
1030 pr_debug ("debug_exp: ");
1034 default: name
= "unknown"; break;
1035 case O_illegal
: name
= "O_illegal"; break;
1036 case O_absent
: name
= "O_absent"; break;
1037 case O_constant
: name
= "O_constant"; break;
1038 case O_symbol
: name
= "O_symbol"; break;
1039 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1040 case O_register
: name
= "O_register"; break;
1041 case O_big
: name
= "O_big"; break;
1042 case O_uminus
: name
= "O_uminus"; break;
1043 case O_bit_not
: name
= "O_bit_not"; break;
1044 case O_logical_not
: name
= "O_logical_not"; break;
1045 case O_multiply
: name
= "O_multiply"; break;
1046 case O_divide
: name
= "O_divide"; break;
1047 case O_modulus
: name
= "O_modulus"; break;
1048 case O_left_shift
: name
= "O_left_shift"; break;
1049 case O_right_shift
: name
= "O_right_shift"; break;
1050 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1051 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1052 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1053 case O_bit_and
: name
= "O_bit_and"; break;
1054 case O_add
: name
= "O_add"; break;
1055 case O_subtract
: name
= "O_subtract"; break;
1056 case O_eq
: name
= "O_eq"; break;
1057 case O_ne
: name
= "O_ne"; break;
1058 case O_lt
: name
= "O_lt"; break;
1059 case O_le
: name
= "O_le"; break;
1060 case O_ge
: name
= "O_ge"; break;
1061 case O_gt
: name
= "O_gt"; break;
1062 case O_logical_and
: name
= "O_logical_and"; break;
1063 case O_logical_or
: name
= "O_logical_or"; break;
1064 case O_index
: name
= "O_index"; break;
1065 case O_bracket
: name
= "O_bracket"; break;
1066 case O_colon
: name
= "O_colon"; break;
1067 case O_addrtype
: name
= "O_addrtype"; break;
1072 default: namemd
= "unknown"; break;
1073 case O_gotoff
: namemd
= "O_gotoff"; break;
1074 case O_gotpc
: namemd
= "O_gotpc"; break;
1075 case O_plt
: namemd
= "O_plt"; break;
1076 case O_sda
: namemd
= "O_sda"; break;
1077 case O_pcl
: namemd
= "O_pcl"; break;
1078 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1079 case O_tlsie
: namemd
= "O_tlsie"; break;
1080 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1081 case O_tpoff
: namemd
= "O_tpoff"; break;
1082 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1083 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1086 pr_debug ("%s (%s, %s, %d, %s)", name
,
1087 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1088 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1089 (int) t
->X_add_number
,
1090 (t
->X_md
) ? namemd
: "--");
1095 /* Helper for parsing an argument, used for sorting out the relocation
1099 parse_reloc_symbol (expressionS
*resultP
)
1101 char *reloc_name
, c
, *sym_name
;
1104 const struct arc_reloc_op_tag
*r
;
1108 /* A relocation operand has the following form
1109 @identifier@relocation_type. The identifier is already in
1111 if (resultP
->X_op
!= O_symbol
)
1113 as_bad (_("No valid label relocation operand"));
1114 resultP
->X_op
= O_illegal
;
1118 /* Parse @relocation_type. */
1119 input_line_pointer
++;
1120 c
= get_symbol_name (&reloc_name
);
1121 len
= input_line_pointer
- reloc_name
;
1124 as_bad (_("No relocation operand"));
1125 resultP
->X_op
= O_illegal
;
1129 /* Go through known relocation and try to find a match. */
1130 r
= &arc_reloc_op
[0];
1131 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1132 if (len
== r
->length
1133 && memcmp (reloc_name
, r
->name
, len
) == 0)
1137 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1138 resultP
->X_op
= O_illegal
;
1142 *input_line_pointer
= c
;
1143 SKIP_WHITESPACE_AFTER_NAME ();
1144 /* Extra check for TLS: base. */
1145 if (*input_line_pointer
== '@')
1147 if (resultP
->X_op_symbol
!= NULL
1148 || resultP
->X_op
!= O_symbol
)
1150 as_bad (_("Unable to parse TLS base: %s"),
1151 input_line_pointer
);
1152 resultP
->X_op
= O_illegal
;
1155 input_line_pointer
++;
1156 c
= get_symbol_name (&sym_name
);
1157 base
= symbol_find_or_make (sym_name
);
1158 resultP
->X_op
= O_subtract
;
1159 resultP
->X_op_symbol
= base
;
1160 restore_line_pointer (c
);
1161 right
.X_add_number
= 0;
1164 if ((*input_line_pointer
!= '+')
1165 && (*input_line_pointer
!= '-'))
1166 right
.X_add_number
= 0;
1169 /* Parse the constant of a complex relocation expression
1170 like @identifier@reloc +/- const. */
1171 if (! r
->complex_expr
)
1173 as_bad (_("@%s is not a complex relocation."), r
->name
);
1174 resultP
->X_op
= O_illegal
;
1177 expression (&right
);
1178 if (right
.X_op
!= O_constant
)
1180 as_bad (_("Bad expression: @%s + %s."),
1181 r
->name
, input_line_pointer
);
1182 resultP
->X_op
= O_illegal
;
1187 resultP
->X_md
= r
->op
;
1188 resultP
->X_add_number
= right
.X_add_number
;
1191 /* Parse the arguments to an opcode. */
1194 tokenize_arguments (char *str
,
1198 char *old_input_line_pointer
;
1199 bfd_boolean saw_comma
= FALSE
;
1200 bfd_boolean saw_arg
= FALSE
;
1204 memset (tok
, 0, sizeof (*tok
) * ntok
);
1206 /* Save and restore input_line_pointer around this function. */
1207 old_input_line_pointer
= input_line_pointer
;
1208 input_line_pointer
= str
;
1210 while (*input_line_pointer
)
1213 switch (*input_line_pointer
)
1219 input_line_pointer
++;
1220 if (saw_comma
|| !saw_arg
)
1227 ++input_line_pointer
;
1229 if (!saw_arg
|| num_args
== ntok
)
1231 tok
->X_op
= O_bracket
;
1238 input_line_pointer
++;
1239 if (brk_lvl
|| num_args
== ntok
)
1242 tok
->X_op
= O_bracket
;
1248 input_line_pointer
++;
1249 if (!saw_arg
|| num_args
== ntok
)
1251 tok
->X_op
= O_colon
;
1258 /* We have labels, function names and relocations, all
1259 starting with @ symbol. Sort them out. */
1260 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1264 input_line_pointer
++;
1265 tok
->X_op
= O_symbol
;
1266 tok
->X_md
= O_absent
;
1269 if (*input_line_pointer
== '@')
1270 parse_reloc_symbol (tok
);
1274 if (tok
->X_op
== O_illegal
1275 || tok
->X_op
== O_absent
1276 || num_args
== ntok
)
1286 /* Can be a register. */
1287 ++input_line_pointer
;
1291 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1294 tok
->X_op
= O_absent
;
1295 tok
->X_md
= O_absent
;
1298 /* Legacy: There are cases when we have
1299 identifier@relocation_type, if it is the case parse the
1300 relocation type as well. */
1301 if (*input_line_pointer
== '@')
1302 parse_reloc_symbol (tok
);
1306 if (tok
->X_op
== O_illegal
1307 || tok
->X_op
== O_absent
1308 || num_args
== ntok
)
1320 if (saw_comma
|| brk_lvl
)
1322 input_line_pointer
= old_input_line_pointer
;
1328 as_bad (_("Brackets in operand field incorrect"));
1330 as_bad (_("extra comma"));
1332 as_bad (_("missing argument"));
1334 as_bad (_("missing comma or colon"));
1335 input_line_pointer
= old_input_line_pointer
;
1339 /* Parse the flags to a structure. */
1342 tokenize_flags (const char *str
,
1343 struct arc_flags flags
[],
1346 char *old_input_line_pointer
;
1347 bfd_boolean saw_flg
= FALSE
;
1348 bfd_boolean saw_dot
= FALSE
;
1352 memset (flags
, 0, sizeof (*flags
) * nflg
);
1354 /* Save and restore input_line_pointer around this function. */
1355 old_input_line_pointer
= input_line_pointer
;
1356 input_line_pointer
= (char *) str
;
1358 while (*input_line_pointer
)
1360 switch (*input_line_pointer
)
1367 input_line_pointer
++;
1375 if (saw_flg
&& !saw_dot
)
1378 if (num_flags
>= nflg
)
1381 flgnamelen
= strspn (input_line_pointer
,
1382 "abcdefghijklmnopqrstuvwxyz0123456789");
1383 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1386 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1388 input_line_pointer
+= flgnamelen
;
1398 input_line_pointer
= old_input_line_pointer
;
1403 as_bad (_("extra dot"));
1405 as_bad (_("unrecognized flag"));
1407 as_bad (_("failed to parse flags"));
1408 input_line_pointer
= old_input_line_pointer
;
1412 /* Apply the fixups in order. */
1415 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1419 for (i
= 0; i
< insn
->nfixups
; i
++)
1421 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1422 int size
, pcrel
, offset
= 0;
1424 /* FIXME! the reloc size is wrong in the BFD file.
1425 When it is fixed please delete me. */
1426 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1431 /* Some fixups are only used internally, thus no howto. */
1432 if ((int) fixup
->reloc
== 0)
1433 as_fatal (_("Unhandled reloc type"));
1435 if ((int) fixup
->reloc
< 0)
1437 /* FIXME! the reloc size is wrong in the BFD file.
1438 When it is fixed please enable me.
1439 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1440 pcrel
= fixup
->pcrel
;
1444 reloc_howto_type
*reloc_howto
=
1445 bfd_reloc_type_lookup (stdoutput
,
1446 (bfd_reloc_code_real_type
) fixup
->reloc
);
1447 gas_assert (reloc_howto
);
1449 /* FIXME! the reloc size is wrong in the BFD file.
1450 When it is fixed please enable me.
1451 size = bfd_get_reloc_size (reloc_howto); */
1452 pcrel
= reloc_howto
->pc_relative
;
1455 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1457 fragP
->fr_file
, fragP
->fr_line
,
1458 (fixup
->reloc
< 0) ? "Internal" :
1459 bfd_get_reloc_code_name (fixup
->reloc
),
1462 fix_new_exp (fragP
, fix
+ offset
,
1463 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1465 /* Check for ZOLs, and update symbol info if any. */
1466 if (LP_INSN (insn
->insn
))
1468 gas_assert (fixup
->exp
.X_add_symbol
);
1469 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1474 /* Actually output an instruction with its fixup. */
1477 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1482 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1483 pr_debug ("\tLength : 0x%d\n", insn
->len
);
1484 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1486 /* Write out the instruction. */
1487 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1489 f
= frag_more (total_len
);
1491 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1494 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1495 dwarf2_emit_insn (total_len
);
1498 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1502 emit_insn1 (struct arc_insn
*insn
)
1504 /* How frag_var's args are currently configured:
1505 - rs_machine_dependent, to dictate it's a relaxation frag.
1506 - FRAG_MAX_GROWTH, maximum size of instruction
1507 - 0, variable size that might grow...unused by generic relaxation.
1508 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1509 - s, opand expression.
1510 - 0, offset but it's unused.
1511 - 0, opcode but it's unused. */
1512 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1513 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1515 if (frag_room () < FRAG_MAX_GROWTH
)
1517 /* Handle differently when frag literal memory is exhausted.
1518 This is used because when there's not enough memory left in
1519 the current frag, a new frag is created and the information
1520 we put into frag_now->tc_frag_data is disregarded. */
1522 struct arc_relax_type relax_info_copy
;
1523 relax_substateT subtype
= frag_now
->fr_subtype
;
1525 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1526 sizeof (struct arc_relax_type
));
1528 frag_wane (frag_now
);
1529 frag_grow (FRAG_MAX_GROWTH
);
1531 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1532 sizeof (struct arc_relax_type
));
1534 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1538 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1539 frag_now
->fr_subtype
, s
, 0, 0);
1543 emit_insn (struct arc_insn
*insn
)
1548 emit_insn0 (insn
, NULL
, FALSE
);
1551 /* Check whether a symbol involves a register. */
1554 contains_register (symbolS
*sym
)
1558 expressionS
*ex
= symbol_get_value_expression (sym
);
1560 return ((O_register
== ex
->X_op
)
1561 && !contains_register (ex
->X_add_symbol
)
1562 && !contains_register (ex
->X_op_symbol
));
1568 /* Returns the register number within a symbol. */
1571 get_register (symbolS
*sym
)
1573 if (!contains_register (sym
))
1576 expressionS
*ex
= symbol_get_value_expression (sym
);
1577 return regno (ex
->X_add_number
);
1580 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1581 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1584 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1591 case BFD_RELOC_ARC_SDA_LDST
:
1592 case BFD_RELOC_ARC_SDA_LDST1
:
1593 case BFD_RELOC_ARC_SDA_LDST2
:
1594 case BFD_RELOC_ARC_SDA16_LD
:
1595 case BFD_RELOC_ARC_SDA16_LD1
:
1596 case BFD_RELOC_ARC_SDA16_LD2
:
1597 case BFD_RELOC_ARC_SDA16_ST2
:
1598 case BFD_RELOC_ARC_SDA32_ME
:
1605 /* Allocates a tok entry. */
1608 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1610 if (ntok
> MAX_INSN_ARGS
- 2)
1611 return 0; /* No space left. */
1614 return 0; /* Incorrect args. */
1616 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1619 return 1; /* Success. */
1620 return allocate_tok (tok
, ntok
- 1, cidx
);
1623 /* Check if an particular ARC feature is enabled. */
1626 check_cpu_feature (insn_subclass_t sc
)
1628 if (is_code_density_p (sc
) && !(selected_cpu
.features
& CD
))
1631 if (is_spfp_p (sc
) && !(selected_cpu
.features
& SPX
))
1634 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& DPX
))
1637 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& DPA
))
1640 if (is_nps400_p (sc
) && !(selected_cpu
.features
& NPS400
))
1646 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1647 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1648 array and returns TRUE if the flag operands all match, otherwise,
1649 returns FALSE, in which case the FIRST_PFLAG array may have been
1653 parse_opcode_flags (const struct arc_opcode
*opcode
,
1655 struct arc_flags
*first_pflag
)
1658 const unsigned char *flgidx
;
1661 for (i
= 0; i
< nflgs
; i
++)
1662 first_pflag
[i
].flgp
= NULL
;
1664 /* Check the flags. Iterate over the valid flag classes. */
1665 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1667 /* Get a valid flag class. */
1668 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1669 const unsigned *flgopridx
;
1671 struct arc_flags
*pflag
= NULL
;
1673 /* Check if opcode has implicit flag classes. */
1674 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
1677 /* Check for extension conditional codes. */
1678 if (ext_condcode
.arc_ext_condcode
1679 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1681 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1684 pflag
= first_pflag
;
1685 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1687 if (!strcmp (pf
->name
, pflag
->name
))
1689 if (pflag
->flgp
!= NULL
)
1702 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1704 const struct arc_flag_operand
*flg_operand
;
1706 pflag
= first_pflag
;
1707 flg_operand
= &arc_flag_operands
[*flgopridx
];
1708 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1710 /* Match against the parsed flags. */
1711 if (!strcmp (flg_operand
->name
, pflag
->name
))
1713 if (pflag
->flgp
!= NULL
)
1716 pflag
->flgp
= flg_operand
;
1718 break; /* goto next flag class and parsed flag. */
1723 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1725 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1729 /* Did I check all the parsed flags? */
1730 return lnflg
? FALSE
: TRUE
;
1734 /* Search forward through all variants of an opcode looking for a
1737 static const struct arc_opcode
*
1738 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1741 struct arc_flags
*first_pflag
,
1744 const char **errmsg
)
1746 const struct arc_opcode
*opcode
;
1747 struct arc_opcode_hash_entry_iterator iter
;
1749 int got_cpu_match
= 0;
1750 expressionS bktok
[MAX_INSN_ARGS
];
1754 arc_opcode_hash_entry_iterator_init (&iter
);
1755 memset (&emptyE
, 0, sizeof (emptyE
));
1756 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1759 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1761 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1763 const unsigned char *opidx
;
1765 const expressionS
*t
= &emptyE
;
1767 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1768 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1770 /* Don't match opcodes that don't exist on this
1772 if (!(opcode
->cpu
& selected_cpu
.flags
))
1775 if (!check_cpu_feature (opcode
->subclass
))
1781 /* Check the operands. */
1782 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1784 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1786 /* Only take input from real operands. */
1787 if (ARC_OPERAND_IS_FAKE (operand
))
1790 /* When we expect input, make sure we have it. */
1794 /* Match operand type with expression type. */
1795 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1797 case ARC_OPERAND_ADDRTYPE
:
1801 /* Check to be an address type. */
1802 if (tok
[tokidx
].X_op
!= O_addrtype
)
1805 /* All address type operands need to have an insert
1806 method in order to check that we have the correct
1808 gas_assert (operand
->insert
!= NULL
);
1809 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1811 if (*errmsg
!= NULL
)
1816 case ARC_OPERAND_IR
:
1817 /* Check to be a register. */
1818 if ((tok
[tokidx
].X_op
!= O_register
1819 || !is_ir_num (tok
[tokidx
].X_add_number
))
1820 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1823 /* If expect duplicate, make sure it is duplicate. */
1824 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1826 /* Check for duplicate. */
1827 if (t
->X_op
!= O_register
1828 || !is_ir_num (t
->X_add_number
)
1829 || (regno (t
->X_add_number
) !=
1830 regno (tok
[tokidx
].X_add_number
)))
1834 /* Special handling? */
1835 if (operand
->insert
)
1838 (*operand
->insert
)(0,
1839 regno (tok
[tokidx
].X_add_number
),
1843 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1845 /* Missing argument, create one. */
1846 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1849 tok
[tokidx
].X_op
= O_absent
;
1860 case ARC_OPERAND_BRAKET
:
1861 /* Check if bracket is also in opcode table as
1863 if (tok
[tokidx
].X_op
!= O_bracket
)
1867 case ARC_OPERAND_COLON
:
1868 /* Check if colon is also in opcode table as operand. */
1869 if (tok
[tokidx
].X_op
!= O_colon
)
1873 case ARC_OPERAND_LIMM
:
1874 case ARC_OPERAND_SIGNED
:
1875 case ARC_OPERAND_UNSIGNED
:
1876 switch (tok
[tokidx
].X_op
)
1884 /* Got an (too) early bracket, check if it is an
1885 ignored operand. N.B. This procedure works only
1886 when bracket is the last operand! */
1887 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1889 /* Insert the missing operand. */
1890 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1893 tok
[tokidx
].X_op
= O_absent
;
1901 const struct arc_aux_reg
*auxr
;
1903 if (opcode
->insn_class
!= AUXREG
)
1905 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1907 /* For compatibility reasons, an aux register can
1908 be spelled with upper or lower case
1911 for (pp
= tmpp
; *pp
; ++pp
) *pp
= TOLOWER (*pp
);
1913 auxr
= hash_find (arc_aux_hash
, tmpp
);
1916 /* We modify the token array here, safe in the
1917 knowledge, that if this was the wrong
1918 choice then the original contents will be
1919 restored from BKTOK. */
1920 tok
[tokidx
].X_op
= O_constant
;
1921 tok
[tokidx
].X_add_number
= auxr
->address
;
1922 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1926 if (tok
[tokidx
].X_op
!= O_constant
)
1931 /* Check the range. */
1932 if (operand
->bits
!= 32
1933 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1935 offsetT min
, max
, val
;
1936 val
= tok
[tokidx
].X_add_number
;
1938 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1940 max
= (1 << (operand
->bits
- 1)) - 1;
1941 min
= -(1 << (operand
->bits
- 1));
1945 max
= (1 << operand
->bits
) - 1;
1949 if (val
< min
|| val
> max
)
1952 /* Check alignments. */
1953 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1957 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1961 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1963 if (operand
->insert
)
1966 (*operand
->insert
)(0,
1967 tok
[tokidx
].X_add_number
,
1972 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1978 /* Check if it is register range. */
1979 if ((tok
[tokidx
].X_add_number
== 0)
1980 && contains_register (tok
[tokidx
].X_add_symbol
)
1981 && contains_register (tok
[tokidx
].X_op_symbol
))
1985 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1987 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1988 if (operand
->insert
)
1991 (*operand
->insert
)(0,
2004 if (operand
->default_reloc
== 0)
2005 goto match_failed
; /* The operand needs relocation. */
2007 /* Relocs requiring long immediate. FIXME! make it
2008 generic and move it to a function. */
2009 switch (tok
[tokidx
].X_md
)
2018 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
2022 if (!generic_reloc_p (operand
->default_reloc
))
2030 /* If expect duplicate, make sure it is duplicate. */
2031 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
2033 if (t
->X_op
== O_illegal
2034 || t
->X_op
== O_absent
2035 || t
->X_op
== O_register
2036 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2043 /* Everything else should have been fake. */
2051 /* Setup ready for flag parsing. */
2052 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2056 /* Possible match -- did we use all of our input? */
2066 /* Restore the original parameters. */
2067 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2072 *pcpumatch
= got_cpu_match
;
2077 /* Swap operand tokens. */
2080 swap_operand (expressionS
*operand_array
,
2082 unsigned destination
)
2084 expressionS cpy_operand
;
2085 expressionS
*src_operand
;
2086 expressionS
*dst_operand
;
2089 if (source
== destination
)
2092 src_operand
= &operand_array
[source
];
2093 dst_operand
= &operand_array
[destination
];
2094 size
= sizeof (expressionS
);
2096 /* Make copy of operand to swap with and swap. */
2097 memcpy (&cpy_operand
, dst_operand
, size
);
2098 memcpy (dst_operand
, src_operand
, size
);
2099 memcpy (src_operand
, &cpy_operand
, size
);
2102 /* Check if *op matches *tok type.
2103 Returns FALSE if they don't match, TRUE if they match. */
2106 pseudo_operand_match (const expressionS
*tok
,
2107 const struct arc_operand_operation
*op
)
2109 offsetT min
, max
, val
;
2111 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2117 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2119 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2121 val
= tok
->X_add_number
+ op
->count
;
2122 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2124 max
= (1 << (operand_real
->bits
- 1)) - 1;
2125 min
= -(1 << (operand_real
->bits
- 1));
2129 max
= (1 << operand_real
->bits
) - 1;
2132 if (min
<= val
&& val
<= max
)
2138 /* Handle all symbols as long immediates or signed 9. */
2139 if (operand_real
->flags
& ARC_OPERAND_LIMM
2140 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2141 && operand_real
->bits
== 9))
2146 if (operand_real
->flags
& ARC_OPERAND_IR
)
2151 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2162 /* Find pseudo instruction in array. */
2164 static const struct arc_pseudo_insn
*
2165 find_pseudo_insn (const char *opname
,
2167 const expressionS
*tok
)
2169 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2170 const struct arc_operand_operation
*op
;
2174 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2176 pseudo_insn
= &arc_pseudo_insns
[i
];
2177 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2179 op
= pseudo_insn
->operand
;
2180 for (j
= 0; j
< ntok
; ++j
)
2181 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2184 /* Found the right instruction. */
2192 /* Assumes the expressionS *tok is of sufficient size. */
2194 static const struct arc_opcode_hash_entry
*
2195 find_special_case_pseudo (const char *opname
,
2199 struct arc_flags
*pflags
)
2201 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2202 const struct arc_operand_operation
*operand_pseudo
;
2203 const struct arc_operand
*operand_real
;
2205 char construct_operand
[MAX_CONSTR_STR
];
2207 /* Find whether opname is in pseudo instruction array. */
2208 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2210 if (pseudo_insn
== NULL
)
2213 /* Handle flag, Limited to one flag at the moment. */
2214 if (pseudo_insn
->flag_r
!= NULL
)
2215 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2216 MAX_INSN_FLGS
- *nflgs
);
2218 /* Handle operand operations. */
2219 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2221 operand_pseudo
= &pseudo_insn
->operand
[i
];
2222 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2224 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2225 && !operand_pseudo
->needs_insert
)
2228 /* Has to be inserted (i.e. this token does not exist yet). */
2229 if (operand_pseudo
->needs_insert
)
2231 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2233 tok
[i
].X_op
= O_bracket
;
2238 /* Check if operand is a register or constant and handle it
2240 if (operand_real
->flags
& ARC_OPERAND_IR
)
2241 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2242 operand_pseudo
->count
);
2244 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2245 operand_pseudo
->count
);
2247 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2251 else if (operand_pseudo
->count
)
2253 /* Operand number has to be adjusted accordingly (by operand
2255 switch (tok
[i
].X_op
)
2258 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2271 /* Swap operands if necessary. Only supports one swap at the
2273 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2275 operand_pseudo
= &pseudo_insn
->operand
[i
];
2277 if (operand_pseudo
->swap_operand_idx
== i
)
2280 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2282 /* Prevent a swap back later by breaking out. */
2286 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2289 static const struct arc_opcode_hash_entry
*
2290 find_special_case_flag (const char *opname
,
2292 struct arc_flags
*pflags
)
2296 unsigned flag_idx
, flag_arr_idx
;
2297 size_t flaglen
, oplen
;
2298 const struct arc_flag_special
*arc_flag_special_opcode
;
2299 const struct arc_opcode_hash_entry
*entry
;
2301 /* Search for special case instruction. */
2302 for (i
= 0; i
< arc_num_flag_special
; i
++)
2304 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2305 oplen
= strlen (arc_flag_special_opcode
->name
);
2307 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2310 /* Found a potential special case instruction, now test for
2312 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2314 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2316 break; /* End of array, nothing found. */
2318 flagnm
= arc_flag_operands
[flag_idx
].name
;
2319 flaglen
= strlen (flagnm
);
2320 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2322 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2324 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2326 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2327 pflags
[*nflgs
].name
[flaglen
] = '\0';
2336 /* Used to find special case opcode. */
2338 static const struct arc_opcode_hash_entry
*
2339 find_special_case (const char *opname
,
2341 struct arc_flags
*pflags
,
2345 const struct arc_opcode_hash_entry
*entry
;
2347 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2350 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2355 /* Autodetect cpu attribute list. */
2358 autodetect_attributes (const struct arc_opcode
*opcode
,
2359 const expressionS
*tok
,
2367 } mpy_list
[] = {{ MPY1E
, 1 }, { MPY6E
, 6 }, { MPY7E
, 7 }, { MPY8E
, 8 },
2370 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
2371 if (opcode
->subclass
== feature_list
[i
].feature
)
2372 selected_cpu
.features
|= feature_list
[i
].feature
;
2374 for (i
= 0; i
< ARRAY_SIZE (mpy_list
); i
++)
2375 if (opcode
->subclass
== mpy_list
[i
].feature
)
2376 mpy_option
= mpy_list
[i
].encoding
;
2378 for (i
= 0; i
< (unsigned) ntok
; i
++)
2380 switch (tok
[i
].X_md
)
2402 switch (tok
[i
].X_op
)
2405 if ((tok
[i
].X_add_number
>= 4 && tok
[i
].X_add_number
<= 9)
2406 || (tok
[i
].X_add_number
>= 16 && tok
[i
].X_add_number
<= 25))
2415 /* Given an opcode name, pre-tockenized set of argumenst and the
2416 opcode flags, take it all the way through emission. */
2419 assemble_tokens (const char *opname
,
2422 struct arc_flags
*pflags
,
2425 bfd_boolean found_something
= FALSE
;
2426 const struct arc_opcode_hash_entry
*entry
;
2428 const char *errmsg
= NULL
;
2430 /* Search opcodes. */
2431 entry
= arc_find_opcode (opname
);
2433 /* Couldn't find opcode conventional way, try special cases. */
2435 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2439 const struct arc_opcode
*opcode
;
2441 pr_debug ("%s:%d: assemble_tokens: %s\n",
2442 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2443 found_something
= TRUE
;
2444 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2445 nflgs
, &cpumatch
, &errmsg
);
2448 struct arc_insn insn
;
2450 autodetect_attributes (opcode
, tok
, ntok
);
2451 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2457 if (found_something
)
2461 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2463 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2465 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2469 as_bad (_("unknown opcode '%s'"), opname
);
2472 /* The public interface to the instruction assembler. */
2475 md_assemble (char *str
)
2478 expressionS tok
[MAX_INSN_ARGS
];
2481 struct arc_flags flags
[MAX_INSN_FLGS
];
2483 /* Split off the opcode. */
2484 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2485 opname
= xmemdup0 (str
, opnamelen
);
2487 /* Signalize we are assembling the instructions. */
2488 assembling_insn
= TRUE
;
2490 /* Tokenize the flags. */
2491 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2493 as_bad (_("syntax error"));
2497 /* Scan up to the end of the mnemonic which must end in space or end
2500 for (; *str
!= '\0'; str
++)
2504 /* Tokenize the rest of the line. */
2505 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2507 as_bad (_("syntax error"));
2511 /* Finish it off. */
2512 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2513 assembling_insn
= FALSE
;
2516 /* Callback to insert a register into the hash table. */
2519 declare_register (const char *name
, int number
)
2522 symbolS
*regS
= symbol_create (name
, reg_section
,
2523 number
, &zero_address_frag
);
2525 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2527 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2531 /* Construct symbols for each of the general registers. */
2534 declare_register_set (void)
2537 for (i
= 0; i
< 64; ++i
)
2541 sprintf (name
, "r%d", i
);
2542 declare_register (name
, i
);
2543 if ((i
& 0x01) == 0)
2545 sprintf (name
, "r%dr%d", i
, i
+1);
2546 declare_register (name
, i
);
2551 /* Construct a symbol for an address type. */
2554 declare_addrtype (const char *name
, int number
)
2557 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2558 number
, &zero_address_frag
);
2560 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2561 (void *) addrtypeS
);
2563 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2567 /* Port-specific assembler initialization. This function is called
2568 once, at assembler startup time. */
2573 const struct arc_opcode
*opcode
= arc_opcodes
;
2575 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2576 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2578 /* The endianness can be chosen "at the factory". */
2579 target_big_endian
= byte_order
== BIG_ENDIAN
;
2581 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2582 as_warn (_("could not set architecture and machine"));
2584 /* Set elf header flags. */
2585 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2587 /* Set up a hash table for the instructions. */
2588 arc_opcode_hash
= hash_new ();
2589 if (arc_opcode_hash
== NULL
)
2590 as_fatal (_("Virtual memory exhausted"));
2592 /* Initialize the hash table with the insns. */
2595 const char *name
= opcode
->name
;
2597 arc_insert_opcode (opcode
);
2599 while (++opcode
&& opcode
->name
2600 && (opcode
->name
== name
2601 || !strcmp (opcode
->name
, name
)))
2603 }while (opcode
->name
);
2605 /* Register declaration. */
2606 arc_reg_hash
= hash_new ();
2607 if (arc_reg_hash
== NULL
)
2608 as_fatal (_("Virtual memory exhausted"));
2610 declare_register_set ();
2611 declare_register ("gp", 26);
2612 declare_register ("fp", 27);
2613 declare_register ("sp", 28);
2614 declare_register ("ilink", 29);
2615 declare_register ("ilink1", 29);
2616 declare_register ("ilink2", 30);
2617 declare_register ("blink", 31);
2619 /* XY memory registers. */
2620 declare_register ("x0_u0", 32);
2621 declare_register ("x0_u1", 33);
2622 declare_register ("x1_u0", 34);
2623 declare_register ("x1_u1", 35);
2624 declare_register ("x2_u0", 36);
2625 declare_register ("x2_u1", 37);
2626 declare_register ("x3_u0", 38);
2627 declare_register ("x3_u1", 39);
2628 declare_register ("y0_u0", 40);
2629 declare_register ("y0_u1", 41);
2630 declare_register ("y1_u0", 42);
2631 declare_register ("y1_u1", 43);
2632 declare_register ("y2_u0", 44);
2633 declare_register ("y2_u1", 45);
2634 declare_register ("y3_u0", 46);
2635 declare_register ("y3_u1", 47);
2636 declare_register ("x0_nu", 48);
2637 declare_register ("x1_nu", 49);
2638 declare_register ("x2_nu", 50);
2639 declare_register ("x3_nu", 51);
2640 declare_register ("y0_nu", 52);
2641 declare_register ("y1_nu", 53);
2642 declare_register ("y2_nu", 54);
2643 declare_register ("y3_nu", 55);
2645 declare_register ("mlo", 57);
2646 declare_register ("mmid", 58);
2647 declare_register ("mhi", 59);
2649 declare_register ("acc1", 56);
2650 declare_register ("acc2", 57);
2652 declare_register ("lp_count", 60);
2653 declare_register ("pcl", 63);
2655 /* Initialize the last instructions. */
2656 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2658 /* Aux register declaration. */
2659 arc_aux_hash
= hash_new ();
2660 if (arc_aux_hash
== NULL
)
2661 as_fatal (_("Virtual memory exhausted"));
2663 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2665 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2669 if (!(auxr
->cpu
& selected_cpu
.flags
))
2672 if ((auxr
->subclass
!= NONE
)
2673 && !check_cpu_feature (auxr
->subclass
))
2676 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2678 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2679 auxr
->name
, retval
);
2682 /* Address type declaration. */
2683 arc_addrtype_hash
= hash_new ();
2684 if (arc_addrtype_hash
== NULL
)
2685 as_fatal (_("Virtual memory exhausted"));
2687 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2688 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2689 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2690 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2691 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2692 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2693 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2694 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2695 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2696 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2697 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2698 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2699 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2700 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2701 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2702 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2705 /* Write a value out to the object file, using the appropriate
2709 md_number_to_chars (char *buf
,
2713 if (target_big_endian
)
2714 number_to_chars_bigendian (buf
, val
, n
);
2716 number_to_chars_littleendian (buf
, val
, n
);
2719 /* Round up a section size to the appropriate boundary. */
2722 md_section_align (segT segment
,
2725 int align
= bfd_section_alignment (segment
);
2727 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2730 /* The location from which a PC relative jump should be calculated,
2731 given a PC relative reloc. */
2734 md_pcrel_from_section (fixS
*fixP
,
2737 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2739 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2741 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2742 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2743 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2745 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2747 /* The symbol is undefined (or is defined but not in this section).
2748 Let the linker figure it out. */
2752 if ((int) fixP
->fx_r_type
< 0)
2754 /* These are the "internal" relocations. Align them to
2755 32 bit boundary (PCL), for the moment. */
2760 switch (fixP
->fx_r_type
)
2762 case BFD_RELOC_ARC_PC32
:
2763 /* The hardware calculates relative to the start of the
2764 insn, but this relocation is relative to location of the
2765 LIMM, compensate. The base always needs to be
2766 subtracted by 4 as we do not support this type of PCrel
2767 relocation for short instructions. */
2770 case BFD_RELOC_ARC_PLT32
:
2771 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2772 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2773 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2774 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2776 case BFD_RELOC_ARC_S21H_PCREL
:
2777 case BFD_RELOC_ARC_S25H_PCREL
:
2778 case BFD_RELOC_ARC_S13_PCREL
:
2779 case BFD_RELOC_ARC_S21W_PCREL
:
2780 case BFD_RELOC_ARC_S25W_PCREL
:
2784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2785 _("unhandled reloc %s in md_pcrel_from_section"),
2786 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2791 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2792 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2793 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2794 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2795 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2800 /* Given a BFD relocation find the corresponding operand. */
2802 static const struct arc_operand
*
2803 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2807 for (i
= 0; i
< arc_num_operands
; i
++)
2808 if (arc_operands
[i
].default_reloc
== reloc
)
2809 return &arc_operands
[i
];
2813 /* Insert an operand value into an instruction. */
2815 static unsigned long long
2816 insert_operand (unsigned long long insn
,
2817 const struct arc_operand
*operand
,
2822 offsetT min
= 0, max
= 0;
2824 if (operand
->bits
!= 32
2825 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2826 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2828 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2830 max
= (1 << (operand
->bits
- 1)) - 1;
2831 min
= -(1 << (operand
->bits
- 1));
2835 max
= (1 << operand
->bits
) - 1;
2839 if (val
< min
|| val
> max
)
2840 as_bad_value_out_of_range (_("operand"),
2841 val
, min
, max
, file
, line
);
2844 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2845 min
, val
, max
, insn
);
2847 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2849 as_bad_where (file
, line
,
2850 _("Unaligned operand. Needs to be 32bit aligned"));
2852 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2854 as_bad_where (file
, line
,
2855 _("Unaligned operand. Needs to be 16bit aligned"));
2857 if (operand
->insert
)
2859 const char *errmsg
= NULL
;
2861 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2863 as_warn_where (file
, line
, "%s", errmsg
);
2867 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2869 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2871 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2874 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2879 /* Apply a fixup to the object code. At this point all symbol values
2880 should be fully resolved, and we attempt to completely resolve the
2881 reloc. If we can not do that, we determine the correct reloc code
2882 and put it back in the fixup. To indicate that a fixup has been
2883 eliminated, set fixP->fx_done. */
2886 md_apply_fix (fixS
*fixP
,
2890 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2891 valueT value
= *valP
;
2893 symbolS
*fx_addsy
, *fx_subsy
;
2895 segT add_symbol_segment
= absolute_section
;
2896 segT sub_symbol_segment
= absolute_section
;
2897 const struct arc_operand
*operand
= NULL
;
2898 extended_bfd_reloc_code_real_type reloc
;
2900 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2901 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2902 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2903 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2906 fx_addsy
= fixP
->fx_addsy
;
2907 fx_subsy
= fixP
->fx_subsy
;
2912 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2916 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2917 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2918 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2920 resolve_symbol_value (fx_subsy
);
2921 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2923 if (sub_symbol_segment
== absolute_section
)
2925 /* The symbol is really a constant. */
2926 fx_offset
-= S_GET_VALUE (fx_subsy
);
2931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2932 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2933 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2934 segment_name (add_symbol_segment
),
2935 S_GET_NAME (fx_subsy
),
2936 segment_name (sub_symbol_segment
));
2942 && !S_IS_WEAK (fx_addsy
))
2944 if (add_symbol_segment
== seg
2947 value
+= S_GET_VALUE (fx_addsy
);
2948 value
-= md_pcrel_from_section (fixP
, seg
);
2950 fixP
->fx_pcrel
= FALSE
;
2952 else if (add_symbol_segment
== absolute_section
)
2954 value
= fixP
->fx_offset
;
2955 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2957 fixP
->fx_pcrel
= FALSE
;
2962 fixP
->fx_done
= TRUE
;
2967 && ((S_IS_DEFINED (fx_addsy
)
2968 && S_GET_SEGMENT (fx_addsy
) != seg
)
2969 || S_IS_WEAK (fx_addsy
)))
2970 value
+= md_pcrel_from_section (fixP
, seg
);
2972 switch (fixP
->fx_r_type
)
2974 case BFD_RELOC_ARC_32_ME
:
2975 /* This is a pc-relative value in a LIMM. Adjust it to the
2976 address of the instruction not to the address of the
2977 LIMM. Note: it is not any longer valid this affirmation as
2978 the linker consider ARC_PC32 a fixup to entire 64 bit
2980 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2983 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2985 case BFD_RELOC_ARC_PC32
:
2986 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2989 if ((int) fixP
->fx_r_type
< 0)
2990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2991 _("PC relative relocation not allowed for (internal)"
2998 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2999 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
3000 ((int) fixP
->fx_r_type
< 0) ? "Internal":
3001 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
3005 /* Now check for TLS relocations. */
3006 reloc
= fixP
->fx_r_type
;
3009 case BFD_RELOC_ARC_TLS_DTPOFF
:
3010 case BFD_RELOC_ARC_TLS_LE_32
:
3014 case BFD_RELOC_ARC_TLS_GD_GOT
:
3015 case BFD_RELOC_ARC_TLS_IE_GOT
:
3016 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3019 case BFD_RELOC_ARC_TLS_GD_LD
:
3020 gas_assert (!fixP
->fx_offset
);
3023 = (S_GET_VALUE (fixP
->fx_subsy
)
3024 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
3025 fixP
->fx_subsy
= NULL
;
3027 case BFD_RELOC_ARC_TLS_GD_CALL
:
3028 /* These two relocs are there just to allow ld to change the tls
3029 model for this symbol, by patching the code. The offset -
3030 and scale, if any - will be installed by the linker. */
3031 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3034 case BFD_RELOC_ARC_TLS_LE_S9
:
3035 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
3036 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3048 /* Adjust the value if we have a constant. */
3051 /* For hosts with longs bigger than 32-bits make sure that the top
3052 bits of a 32-bit negative value read in by the parser are set,
3053 so that the correct comparisons are made. */
3054 if (value
& 0x80000000)
3055 value
|= (-1UL << 31);
3057 reloc
= fixP
->fx_r_type
;
3065 case BFD_RELOC_ARC_32_PCREL
:
3066 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3069 case BFD_RELOC_ARC_GOTPC32
:
3070 /* I cannot fix an GOTPC relocation because I need to relax it
3071 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3072 as_bad (_("Unsupported operation on reloc"));
3075 case BFD_RELOC_ARC_TLS_DTPOFF
:
3076 case BFD_RELOC_ARC_TLS_LE_32
:
3077 gas_assert (!fixP
->fx_addsy
);
3078 gas_assert (!fixP
->fx_subsy
);
3081 case BFD_RELOC_ARC_GOTOFF
:
3082 case BFD_RELOC_ARC_32_ME
:
3083 case BFD_RELOC_ARC_PC32
:
3084 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3087 case BFD_RELOC_ARC_PLT32
:
3088 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3091 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3092 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3095 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3096 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3099 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3100 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3103 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3104 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3107 case BFD_RELOC_ARC_S25W_PCREL
:
3108 case BFD_RELOC_ARC_S21W_PCREL
:
3109 case BFD_RELOC_ARC_S21H_PCREL
:
3110 case BFD_RELOC_ARC_S25H_PCREL
:
3111 case BFD_RELOC_ARC_S13_PCREL
:
3113 operand
= find_operand_for_reloc (reloc
);
3114 gas_assert (operand
);
3119 if ((int) fixP
->fx_r_type
>= 0)
3120 as_fatal (_("unhandled relocation type %s"),
3121 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3123 /* The rest of these fixups needs to be completely resolved as
3125 if (fixP
->fx_addsy
!= 0
3126 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3128 _("non-absolute expression in constant field"));
3130 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3131 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3136 if (target_big_endian
)
3138 switch (fixP
->fx_size
)
3141 insn
= bfd_getb32 (fixpos
);
3144 insn
= bfd_getb16 (fixpos
);
3147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3148 _("unknown fixup size"));
3154 switch (fixP
->fx_size
)
3157 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3160 insn
= bfd_getl16 (fixpos
);
3163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3164 _("unknown fixup size"));
3168 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3169 fixP
->fx_file
, fixP
->fx_line
);
3171 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3174 /* Prepare machine-dependent frags for relaxation.
3176 Called just before relaxation starts. Any symbol that is now undefined
3177 will not become defined.
3179 Return the correct fr_subtype in the frag.
3181 Return the initial "guess for fr_var" to caller. The guess for fr_var
3182 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3183 or fr_var contributes to our returned value.
3185 Although it may not be explicit in the frag, pretend
3186 fr_var starts with a value. */
3189 md_estimate_size_before_relax (fragS
*fragP
,
3194 /* If the symbol is not located within the same section AND it's not
3195 an absolute section, use the maximum. OR if the symbol is a
3196 constant AND the insn is by nature not pc-rel, use the maximum.
3197 OR if the symbol is being equated against another symbol, use the
3198 maximum. OR if the symbol is weak use the maximum. */
3199 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3200 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3201 || (symbol_constant_p (fragP
->fr_symbol
)
3202 && !fragP
->tc_frag_data
.pcrel
)
3203 || symbol_equated_p (fragP
->fr_symbol
)
3204 || S_IS_WEAK (fragP
->fr_symbol
))
3206 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3207 ++fragP
->fr_subtype
;
3210 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3211 fragP
->fr_var
= growth
;
3213 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3214 fragP
->fr_file
, fragP
->fr_line
, growth
);
3219 /* Translate internal representation of relocation info to BFD target
3223 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3227 bfd_reloc_code_real_type code
;
3229 reloc
= XNEW (arelent
);
3230 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3231 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3232 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3234 /* Make sure none of our internal relocations make it this far.
3235 They'd better have been fully resolved by this point. */
3236 gas_assert ((int) fixP
->fx_r_type
> 0);
3238 code
= fixP
->fx_r_type
;
3240 /* if we have something like add gp, pcl,
3241 _GLOBAL_OFFSET_TABLE_@gotpc. */
3242 if (code
== BFD_RELOC_ARC_GOTPC32
3244 && fixP
->fx_addsy
== GOT_symbol
)
3245 code
= BFD_RELOC_ARC_GOTPC
;
3247 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3248 if (reloc
->howto
== NULL
)
3250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3251 _("cannot represent `%s' relocation in object file"),
3252 bfd_get_reloc_code_name (code
));
3256 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3257 as_fatal (_("internal error? cannot generate `%s' relocation"),
3258 bfd_get_reloc_code_name (code
));
3260 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3262 reloc
->addend
= fixP
->fx_offset
;
3267 /* Perform post-processing of machine-dependent frags after relaxation.
3268 Called after relaxation is finished.
3269 In: Address of frag.
3270 fr_type == rs_machine_dependent.
3271 fr_subtype is what the address relaxed to.
3273 Out: Any fixS:s and constants are set up. */
3276 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3277 segT segment ATTRIBUTE_UNUSED
,
3280 const relax_typeS
*table_entry
;
3282 const struct arc_opcode
*opcode
;
3283 struct arc_insn insn
;
3285 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3287 fix
= fragP
->fr_fix
;
3288 dest
= fragP
->fr_literal
+ fix
;
3289 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3291 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3292 "var: %"BFD_VMA_FMT
"d\n",
3293 fragP
->fr_file
, fragP
->fr_line
,
3294 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3296 if (fragP
->fr_subtype
<= 0
3297 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3298 as_fatal (_("no relaxation found for this instruction."));
3300 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3302 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3303 relax_arg
->nflg
, &insn
);
3305 apply_fixups (&insn
, fragP
, fix
);
3307 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3308 gas_assert (table_entry
->rlx_length
== size
);
3309 emit_insn0 (&insn
, dest
, TRUE
);
3311 fragP
->fr_fix
+= table_entry
->rlx_length
;
3315 /* We have no need to default values of symbols. We could catch
3316 register names here, but that is handled by inserting them all in
3317 the symbol table to begin with. */
3320 md_undefined_symbol (char *name
)
3322 /* The arc abi demands that a GOT[0] should be referencible as
3323 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3324 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3326 && (*(name
+1) == 'G')
3327 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)))
3331 if (symbol_find (name
))
3332 as_bad ("GOT already in symbol table");
3334 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3335 (valueT
) 0, &zero_address_frag
);
3342 /* Turn a string in input_line_pointer into a floating point constant
3343 of type type, and store the appropriate bytes in *litP. The number
3344 of LITTLENUMS emitted is stored in *sizeP. An error message is
3345 returned, or NULL on OK. */
3348 md_atof (int type
, char *litP
, int *sizeP
)
3350 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3353 /* Called for any expression that can not be recognized. When the
3354 function is called, `input_line_pointer' will point to the start of
3355 the expression. We use it when we have complex operations like
3356 @label1 - @label2. */
3359 md_operand (expressionS
*expressionP
)
3361 char *p
= input_line_pointer
;
3364 input_line_pointer
++;
3365 expressionP
->X_op
= O_symbol
;
3366 expressionP
->X_md
= O_absent
;
3367 expression (expressionP
);
3371 /* This function is called from the function 'expression', it attempts
3372 to parse special names (in our case register names). It fills in
3373 the expression with the identified register. It returns TRUE if
3374 it is a register and FALSE otherwise. */
3377 arc_parse_name (const char *name
,
3378 struct expressionS
*e
)
3382 if (!assembling_insn
)
3385 if (e
->X_op
== O_symbol
3386 && e
->X_md
== O_absent
)
3389 sym
= hash_find (arc_reg_hash
, name
);
3392 e
->X_op
= O_register
;
3393 e
->X_add_number
= S_GET_VALUE (sym
);
3397 sym
= hash_find (arc_addrtype_hash
, name
);
3400 e
->X_op
= O_addrtype
;
3401 e
->X_add_number
= S_GET_VALUE (sym
);
3409 Invocation line includes a switch not recognized by the base assembler.
3410 See if it's a processor-specific option.
3412 New options (supported) are:
3414 -mcpu=<cpu name> Assemble for selected processor
3415 -EB/-mbig-endian Big-endian
3416 -EL/-mlittle-endian Little-endian
3417 -mrelax Enable relaxation
3419 The following CPU names are recognized:
3420 arc600, arc700, arcem, archs, nps400. */
3423 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3429 return md_parse_option (OPTION_MCPU
, "arc600");
3432 return md_parse_option (OPTION_MCPU
, "arc700");
3435 return md_parse_option (OPTION_MCPU
, "arcem");
3438 return md_parse_option (OPTION_MCPU
, "archs");
3442 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3447 arc_target_format
= "elf32-bigarc";
3448 byte_order
= BIG_ENDIAN
;
3452 arc_target_format
= "elf32-littlearc";
3453 byte_order
= LITTLE_ENDIAN
;
3457 selected_cpu
.features
|= CD
;
3459 arc_check_feature ();
3463 relaxation_state
= 1;
3467 selected_cpu
.features
|= NPS400
;
3468 cl_features
|= NPS400
;
3469 arc_check_feature ();
3473 selected_cpu
.features
|= SPX
;
3475 arc_check_feature ();
3479 selected_cpu
.features
|= DPX
;
3481 arc_check_feature ();
3485 selected_cpu
.features
|= DPA
;
3487 arc_check_feature ();
3490 /* Dummy options are accepted but have no effect. */
3491 case OPTION_USER_MODE
:
3492 case OPTION_LD_EXT_MASK
:
3495 case OPTION_BARREL_SHIFT
:
3496 case OPTION_MIN_MAX
:
3501 case OPTION_XMAC_D16
:
3502 case OPTION_XMAC_24
:
3503 case OPTION_DSP_PACKA
:
3506 case OPTION_TELEPHONY
:
3507 case OPTION_XYMEMORY
:
3520 /* Display the list of cpu names for use in the help text. */
3523 arc_show_cpu_list (FILE *stream
)
3526 static const char *space_buf
= " ";
3528 fprintf (stream
, "%s", space_buf
);
3529 offset
= strlen (space_buf
);
3530 for (i
= 0; cpu_types
[i
].name
!= NULL
; ++i
)
3532 bfd_boolean last
= (cpu_types
[i
+ 1].name
== NULL
);
3534 /* If displaying the new cpu name string, and the ', ' (for all
3535 but the last one) will take us past a target width of 80
3536 characters, then it's time for a new line. */
3537 if (offset
+ strlen (cpu_types
[i
].name
) + (last
? 0 : 2) > 80)
3539 fprintf (stream
, "\n%s", space_buf
);
3540 offset
= strlen (space_buf
);
3543 fprintf (stream
, "%s%s", cpu_types
[i
].name
, (last
? "\n" : ", "));
3544 offset
+= strlen (cpu_types
[i
].name
) + (last
? 0 : 2);
3549 md_show_usage (FILE *stream
)
3551 fprintf (stream
, _("ARC-specific assembler options:\n"));
3553 fprintf (stream
, " -mcpu=<cpu name>\t (default: %s), assemble for"
3554 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU
);
3555 arc_show_cpu_list (stream
);
3556 fprintf (stream
, "\n");
3557 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3558 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3559 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3560 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3562 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3563 fprintf (stream
, " -mspfp\t\t enable single-precision floating point"
3565 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point"
3567 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3568 "point\n\t\t\t instructions for ARC EM\n");
3571 " -mcode-density\t enable code density option for ARC EM\n");
3573 fprintf (stream
, _("\
3574 -EB assemble code for a big-endian cpu\n"));
3575 fprintf (stream
, _("\
3576 -EL assemble code for a little-endian cpu\n"));
3577 fprintf (stream
, _("\
3578 -mrelax enable relaxation\n"));
3580 fprintf (stream
, _("The following ARC-specific assembler options are "
3581 "deprecated and are accepted\nfor compatibility only:\n"));
3583 fprintf (stream
, _(" -mEA\n"
3584 " -mbarrel-shifter\n"
3585 " -mbarrel_shifter\n"
3590 " -mld-extension-reg-mask\n"
3606 " -muser-mode-only\n"
3610 /* Find the proper relocation for the given opcode. */
3612 static extended_bfd_reloc_code_real_type
3613 find_reloc (const char *name
,
3614 const char *opcodename
,
3615 const struct arc_flags
*pflags
,
3617 extended_bfd_reloc_code_real_type reloc
)
3621 bfd_boolean found_flag
, tmp
;
3622 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3624 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3626 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3628 /* Find the entry. */
3629 if (strcmp (name
, r
->name
))
3631 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3638 unsigned * psflg
= (unsigned *)r
->flags
;
3642 for (j
= 0; j
< nflg
; j
++)
3643 if (!strcmp (pflags
[j
].name
,
3644 arc_flag_operands
[*psflg
].name
))
3665 if (reloc
!= r
->oldreloc
)
3672 if (ret
== BFD_RELOC_UNUSED
)
3673 as_bad (_("Unable to find %s relocation for instruction %s"),
3678 /* All the symbol types that are allowed to be used for
3682 may_relax_expr (expressionS tok
)
3684 /* Check if we have unrelaxable relocs. */
3709 /* Checks if flags are in line with relaxable insn. */
3712 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3713 const struct arc_flags
*pflags
,
3716 unsigned flag_class
,
3721 const struct arc_flag_operand
*flag_opand
;
3722 int i
, counttrue
= 0;
3724 /* Iterate through flags classes. */
3725 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3727 /* Iterate through flags in flag class. */
3728 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3731 flag_opand
= &arc_flag_operands
[flag
];
3732 /* Iterate through flags in ins to compare. */
3733 for (i
= 0; i
< nflgs
; ++i
)
3735 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3746 /* If counttrue == nflgs, then all flags have been found. */
3747 return (counttrue
== nflgs
? TRUE
: FALSE
);
3750 /* Checks if operands are in line with relaxable insn. */
3753 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3754 const expressionS
*tok
,
3757 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3760 while (*operand
!= EMPTY
)
3762 const expressionS
*epr
= &tok
[i
];
3764 if (i
!= 0 && i
>= ntok
)
3770 if (!(epr
->X_op
== O_multiply
3771 || epr
->X_op
== O_divide
3772 || epr
->X_op
== O_modulus
3773 || epr
->X_op
== O_add
3774 || epr
->X_op
== O_subtract
3775 || epr
->X_op
== O_symbol
))
3781 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3785 if (epr
->X_op
!= O_register
)
3790 if (epr
->X_op
!= O_register
)
3793 switch (epr
->X_add_number
)
3795 case 0: case 1: case 2: case 3:
3796 case 12: case 13: case 14: case 15:
3803 case REGISTER_NO_GP
:
3804 if ((epr
->X_op
!= O_register
)
3805 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3810 if (epr
->X_op
!= O_bracket
)
3815 /* Don't understand, bail out. */
3821 operand
= &ins
->operands
[i
];
3824 return (i
== ntok
? TRUE
: FALSE
);
3827 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3830 relax_insn_p (const struct arc_opcode
*opcode
,
3831 const expressionS
*tok
,
3833 const struct arc_flags
*pflags
,
3837 bfd_boolean rv
= FALSE
;
3839 /* Check the relaxation table. */
3840 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3842 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3844 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3845 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3846 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3847 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3850 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3851 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3852 sizeof (expressionS
) * ntok
);
3853 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3854 sizeof (struct arc_flags
) * nflg
);
3855 frag_now
->tc_frag_data
.nflg
= nflg
;
3856 frag_now
->tc_frag_data
.ntok
= ntok
;
3864 /* Turn an opcode description and a set of arguments into
3865 an instruction and a fixup. */
3868 assemble_insn (const struct arc_opcode
*opcode
,
3869 const expressionS
*tok
,
3871 const struct arc_flags
*pflags
,
3873 struct arc_insn
*insn
)
3875 const expressionS
*reloc_exp
= NULL
;
3876 unsigned long long image
;
3877 const unsigned char *argidx
;
3880 unsigned char pcrel
= 0;
3881 bfd_boolean needGOTSymbol
;
3882 bfd_boolean has_delay_slot
= FALSE
;
3883 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3885 memset (insn
, 0, sizeof (*insn
));
3886 image
= opcode
->opcode
;
3888 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3889 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3892 /* Handle operands. */
3893 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3895 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3896 const expressionS
*t
= (const expressionS
*) 0;
3898 if (ARC_OPERAND_IS_FAKE (operand
))
3901 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3903 /* Duplicate operand, already inserted. */
3915 /* Regardless if we have a reloc or not mark the instruction
3916 limm if it is the case. */
3917 if (operand
->flags
& ARC_OPERAND_LIMM
)
3918 insn
->has_limm
= TRUE
;
3923 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3928 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3930 if (operand
->flags
& ARC_OPERAND_LIMM
)
3931 insn
->limm
= t
->X_add_number
;
3937 /* Ignore brackets, colons, and address types. */
3941 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3945 /* Maybe register range. */
3946 if ((t
->X_add_number
== 0)
3947 && contains_register (t
->X_add_symbol
)
3948 && contains_register (t
->X_op_symbol
))
3952 regs
= get_register (t
->X_add_symbol
);
3954 regs
|= get_register (t
->X_op_symbol
);
3955 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3961 /* This operand needs a relocation. */
3962 needGOTSymbol
= FALSE
;
3967 if (opcode
->insn_class
== JUMP
)
3968 as_bad (_("Unable to use @plt relocation for insn %s"),
3970 needGOTSymbol
= TRUE
;
3971 reloc
= find_reloc ("plt", opcode
->name
,
3973 operand
->default_reloc
);
3978 needGOTSymbol
= TRUE
;
3979 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3982 if (operand
->flags
& ARC_OPERAND_LIMM
)
3984 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3985 if (arc_opcode_len (opcode
) == 2
3986 || opcode
->insn_class
== JUMP
)
3987 as_bad (_("Unable to use @pcl relocation for insn %s"),
3992 /* This is a relaxed operand which initially was
3993 limm, choose whatever we have defined in the
3995 reloc
= operand
->default_reloc
;
3999 reloc
= find_reloc ("sda", opcode
->name
,
4001 operand
->default_reloc
);
4005 needGOTSymbol
= TRUE
;
4010 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
4013 case O_tpoff9
: /*FIXME! Check for the conditionality of
4015 case O_dtpoff9
: /*FIXME! Check for the conditionality of
4017 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4021 /* Just consider the default relocation. */
4022 reloc
= operand
->default_reloc
;
4026 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
4027 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4034 /* sanity checks. */
4035 reloc_howto_type
*reloc_howto
4036 = bfd_reloc_type_lookup (stdoutput
,
4037 (bfd_reloc_code_real_type
) reloc
);
4038 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
4039 if (reloc_howto
->rightshift
)
4040 reloc_bitsize
-= reloc_howto
->rightshift
;
4041 if (reloc_bitsize
!= operand
->bits
)
4043 as_bad (_("invalid relocation %s for field"),
4044 bfd_get_reloc_code_name (reloc
));
4049 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4050 as_fatal (_("too many fixups"));
4052 struct arc_fixup
*fixup
;
4053 fixup
= &insn
->fixups
[insn
->nfixups
++];
4055 fixup
->reloc
= reloc
;
4056 if ((int) reloc
< 0)
4057 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
4060 reloc_howto_type
*reloc_howto
=
4061 bfd_reloc_type_lookup (stdoutput
,
4062 (bfd_reloc_code_real_type
) fixup
->reloc
);
4063 pcrel
= reloc_howto
->pc_relative
;
4065 fixup
->pcrel
= pcrel
;
4066 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
4073 for (i
= 0; i
< nflg
; i
++)
4075 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
4077 /* Check if the instruction has a delay slot. */
4078 if (!strcmp (flg_operand
->name
, "d"))
4079 has_delay_slot
= TRUE
;
4081 /* There is an exceptional case when we cannot insert a flag just as
4082 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4083 relation with the relative address. Unfortunately, some of the
4084 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4085 handled in the normal way.
4087 Flag operands don't have an architecture field, so we can't
4088 directly validate that FLAG_OPERAND is valid for the current
4089 architecture, what we do instead is just validate that we're
4090 assembling for an ARCv2 architecture. */
4091 if ((selected_cpu
.flags
& ARC_OPCODE_ARCV2
)
4092 && (!strcmp (flg_operand
->name
, "t")
4093 || !strcmp (flg_operand
->name
, "nt")))
4095 unsigned bitYoperand
= 0;
4096 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4097 if (!strcmp (flg_operand
->name
, "t"))
4098 if (!strcmp (opcode
->name
, "bbit0")
4099 || !strcmp (opcode
->name
, "bbit1"))
4100 bitYoperand
= arc_NToperand
;
4102 bitYoperand
= arc_Toperand
;
4104 if (!strcmp (opcode
->name
, "bbit0")
4105 || !strcmp (opcode
->name
, "bbit1"))
4106 bitYoperand
= arc_Toperand
;
4108 bitYoperand
= arc_NToperand
;
4110 gas_assert (reloc_exp
!= NULL
);
4111 if (reloc_exp
->X_op
== O_constant
)
4113 /* Check if we have a constant and solved it
4115 offsetT val
= reloc_exp
->X_add_number
;
4116 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4121 struct arc_fixup
*fixup
;
4123 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4124 as_fatal (_("too many fixups"));
4126 fixup
= &insn
->fixups
[insn
->nfixups
++];
4127 fixup
->exp
= *reloc_exp
;
4128 fixup
->reloc
= -bitYoperand
;
4129 fixup
->pcrel
= pcrel
;
4130 fixup
->islong
= FALSE
;
4134 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4135 << flg_operand
->shift
;
4138 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4140 /* Instruction length. */
4141 insn
->len
= arc_opcode_len (opcode
);
4145 /* Update last insn status. */
4146 arc_last_insns
[1] = arc_last_insns
[0];
4147 arc_last_insns
[0].opcode
= opcode
;
4148 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4149 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4151 /* Check if the current instruction is legally used. */
4152 if (arc_last_insns
[1].has_delay_slot
4153 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4154 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4155 arc_last_insns
[1].opcode
->name
,
4156 arc_last_insns
[0].opcode
->name
);
4157 if (arc_last_insns
[1].has_delay_slot
4158 && arc_last_insns
[0].has_limm
)
4159 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4160 arc_last_insns
[1].opcode
->name
,
4161 arc_last_insns
[0].opcode
->name
);
4165 arc_handle_align (fragS
* fragP
)
4167 if ((fragP
)->fr_type
== rs_align_code
)
4169 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4170 valueT count
= ((fragP
)->fr_next
->fr_address
4171 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4173 (fragP
)->fr_var
= 2;
4175 if (count
& 1)/* Padding in the gap till the next 2-byte
4176 boundary with 0s. */
4181 /* Writing nop_s. */
4182 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4186 /* Here we decide which fixups can be adjusted to make them relative
4187 to the beginning of the section instead of the symbol. Basically
4188 we need to make sure that the dynamic relocations are done
4189 correctly, so in some cases we force the original symbol to be
4193 tc_arc_fix_adjustable (fixS
*fixP
)
4196 /* Prevent all adjustments to global symbols. */
4197 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4199 if (S_IS_WEAK (fixP
->fx_addsy
))
4202 /* Adjust_reloc_syms doesn't know about the GOT. */
4203 switch (fixP
->fx_r_type
)
4205 case BFD_RELOC_ARC_GOTPC32
:
4206 case BFD_RELOC_ARC_PLT32
:
4207 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4208 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4209 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4210 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4220 /* Compute the reloc type of an expression EXP. */
4223 arc_check_reloc (expressionS
*exp
,
4224 bfd_reloc_code_real_type
*r_type_p
)
4226 if (*r_type_p
== BFD_RELOC_32
4227 && exp
->X_op
== O_subtract
4228 && exp
->X_op_symbol
!= NULL
4229 && S_GET_SEGMENT (exp
->X_op_symbol
) == now_seg
)
4230 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4234 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4237 arc_cons_fix_new (fragS
*frag
,
4241 bfd_reloc_code_real_type r_type
)
4243 r_type
= BFD_RELOC_UNUSED
;
4248 r_type
= BFD_RELOC_8
;
4252 r_type
= BFD_RELOC_16
;
4256 r_type
= BFD_RELOC_24
;
4260 r_type
= BFD_RELOC_32
;
4261 arc_check_reloc (exp
, &r_type
);
4265 r_type
= BFD_RELOC_64
;
4269 as_bad (_("unsupported BFD relocation size %u"), size
);
4270 r_type
= BFD_RELOC_UNUSED
;
4273 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4276 /* The actual routine that checks the ZOL conditions. */
4279 check_zol (symbolS
*s
)
4281 switch (selected_cpu
.mach
)
4283 case bfd_mach_arc_arcv2
:
4284 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4287 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4288 || arc_last_insns
[1].has_delay_slot
)
4289 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4293 case bfd_mach_arc_arc600
:
4295 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4296 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4299 if (arc_last_insns
[0].has_limm
4300 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4301 as_bad (_("A jump instruction with long immediate detected at the \
4302 end of the ZOL label @%s"), S_GET_NAME (s
));
4305 case bfd_mach_arc_arc700
:
4306 if (arc_last_insns
[0].has_delay_slot
)
4307 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4316 /* If ZOL end check the last two instruction for illegals. */
4318 arc_frob_label (symbolS
* sym
)
4320 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4323 dwarf2_emit_label (sym
);
4326 /* Used because generic relaxation assumes a pc-rel value whilst we
4327 also relax instructions that use an absolute value resolved out of
4328 relative values (if that makes any sense). An example: 'add r1,
4329 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4330 but if they're in the same section we can subtract the section
4331 offset relocation which ends up in a resolved value. So if @.L2 is
4332 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4333 .text + 0x40 = 0x10. */
4335 arc_pcrel_adjust (fragS
*fragP
)
4337 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4338 fragP
->fr_address
, fragP
->fr_fix
,
4339 fragP
->tc_frag_data
.pcrel
? "Y" : "N");
4341 if (!fragP
->tc_frag_data
.pcrel
)
4342 return fragP
->fr_address
+ fragP
->fr_fix
;
4344 /* Take into account the PCL rounding. */
4345 return (fragP
->fr_address
+ fragP
->fr_fix
) & 0x03;
4348 /* Initialize the DWARF-2 unwind information for this procedure. */
4351 tc_arc_frame_initial_instructions (void)
4353 /* Stack pointer is register 28. */
4354 cfi_add_CFA_def_cfa (28, 0);
4358 tc_arc_regname_to_dw2regnum (char *regname
)
4362 sym
= hash_find (arc_reg_hash
, regname
);
4364 return S_GET_VALUE (sym
);
4369 /* Adjust the symbol table. Delete found AUX register symbols. */
4372 arc_adjust_symtab (void)
4376 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4378 /* I've created a symbol during parsing process. Now, remove
4379 the symbol as it is found to be an AUX register. */
4380 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4381 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4384 /* Now do generic ELF adjustments. */
4385 elf_adjust_symtab ();
4389 tokenize_extinsn (extInstruction_t
*einsn
)
4393 unsigned char major_opcode
;
4394 unsigned char sub_opcode
;
4395 unsigned char syntax_class
= 0;
4396 unsigned char syntax_class_modifiers
= 0;
4397 unsigned char suffix_class
= 0;
4402 /* 1st: get instruction name. */
4403 p
= input_line_pointer
;
4404 c
= get_symbol_name (&p
);
4406 insn_name
= xstrdup (p
);
4407 restore_line_pointer (c
);
4409 /* Convert to lower case. */
4410 for (p
= insn_name
; *p
; ++p
)
4413 /* 2nd: get major opcode. */
4414 if (*input_line_pointer
!= ',')
4416 as_bad (_("expected comma after instruction name"));
4417 ignore_rest_of_line ();
4420 input_line_pointer
++;
4421 major_opcode
= get_absolute_expression ();
4423 /* 3rd: get sub-opcode. */
4426 if (*input_line_pointer
!= ',')
4428 as_bad (_("expected comma after major opcode"));
4429 ignore_rest_of_line ();
4432 input_line_pointer
++;
4433 sub_opcode
= get_absolute_expression ();
4435 /* 4th: get suffix class. */
4438 if (*input_line_pointer
!= ',')
4440 as_bad ("expected comma after sub opcode");
4441 ignore_rest_of_line ();
4444 input_line_pointer
++;
4450 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4452 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4453 suffixclass
[i
].len
))
4455 suffix_class
|= suffixclass
[i
].attr_class
;
4456 input_line_pointer
+= suffixclass
[i
].len
;
4461 if (i
== ARRAY_SIZE (suffixclass
))
4463 as_bad ("invalid suffix class");
4464 ignore_rest_of_line ();
4470 if (*input_line_pointer
== '|')
4471 input_line_pointer
++;
4476 /* 5th: get syntax class and syntax class modifiers. */
4477 if (*input_line_pointer
!= ',')
4479 as_bad ("expected comma after suffix class");
4480 ignore_rest_of_line ();
4483 input_line_pointer
++;
4489 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4491 if (!strncmp (syntaxclassmod
[i
].name
,
4493 syntaxclassmod
[i
].len
))
4495 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4496 input_line_pointer
+= syntaxclassmod
[i
].len
;
4501 if (i
== ARRAY_SIZE (syntaxclassmod
))
4503 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4505 if (!strncmp (syntaxclass
[i
].name
,
4507 syntaxclass
[i
].len
))
4509 syntax_class
|= syntaxclass
[i
].attr_class
;
4510 input_line_pointer
+= syntaxclass
[i
].len
;
4515 if (i
== ARRAY_SIZE (syntaxclass
))
4517 as_bad ("missing syntax class");
4518 ignore_rest_of_line ();
4525 if (*input_line_pointer
== '|')
4526 input_line_pointer
++;
4531 demand_empty_rest_of_line ();
4533 einsn
->name
= insn_name
;
4534 einsn
->major
= major_opcode
;
4535 einsn
->minor
= sub_opcode
;
4536 einsn
->syntax
= syntax_class
;
4537 einsn
->modsyn
= syntax_class_modifiers
;
4538 einsn
->suffix
= suffix_class
;
4539 einsn
->flags
= syntax_class
4540 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4543 /* Generate an extension section. */
4546 arc_set_ext_seg (void)
4548 if (!arcext_section
)
4550 arcext_section
= subseg_new (".arcextmap", 0);
4551 bfd_set_section_flags (arcext_section
, SEC_READONLY
| SEC_HAS_CONTENTS
);
4554 subseg_set (arcext_section
, 0);
4558 /* Create an extension instruction description in the arc extension
4559 section of the output file.
4560 The structure for an instruction is like this:
4561 [0]: Length of the record.
4562 [1]: Type of the record.
4566 [4]: Syntax (flags).
4567 [5]+ Name instruction.
4569 The sequence is terminated by an empty entry. */
4572 create_extinst_section (extInstruction_t
*einsn
)
4575 segT old_sec
= now_seg
;
4576 int old_subsec
= now_subseg
;
4578 int name_len
= strlen (einsn
->name
);
4583 *p
= 5 + name_len
+ 1;
4585 *p
= EXT_INSTRUCTION
;
4592 p
= frag_more (name_len
+ 1);
4593 strcpy (p
, einsn
->name
);
4595 subseg_set (old_sec
, old_subsec
);
4598 /* Handler .extinstruction pseudo-op. */
4601 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4603 extInstruction_t einsn
;
4604 struct arc_opcode
*arc_ext_opcodes
;
4605 const char *errmsg
= NULL
;
4606 unsigned char moplow
, mophigh
;
4608 memset (&einsn
, 0, sizeof (einsn
));
4609 tokenize_extinsn (&einsn
);
4611 /* Check if the name is already used. */
4612 if (arc_find_opcode (einsn
.name
))
4613 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4615 /* Check the opcode ranges. */
4617 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4618 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4620 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4621 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4623 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4624 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4625 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4627 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4629 case ARC_SYNTAX_3OP
:
4630 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4631 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4633 case ARC_SYNTAX_2OP
:
4634 case ARC_SYNTAX_1OP
:
4635 case ARC_SYNTAX_NOP
:
4636 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4637 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4643 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4644 if (arc_ext_opcodes
== NULL
)
4647 as_fatal ("%s", errmsg
);
4649 as_fatal (_("Couldn't generate extension instruction opcodes"));
4652 as_warn ("%s", errmsg
);
4654 /* Insert the extension instruction. */
4655 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4657 create_extinst_section (&einsn
);
4661 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4667 int number
, imode
= 0;
4668 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4669 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4670 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4672 /* 1st: get register name. */
4674 p
= input_line_pointer
;
4675 c
= get_symbol_name (&p
);
4678 restore_line_pointer (c
);
4680 /* 2nd: get register number. */
4683 if (*input_line_pointer
!= ',')
4685 as_bad (_("expected comma after name"));
4686 ignore_rest_of_line ();
4690 input_line_pointer
++;
4691 number
= get_absolute_expression ();
4694 && (opertype
!= EXT_AUX_REGISTER
))
4696 as_bad (_("%s second argument cannot be a negative number %d"),
4697 isCore_p
? "extCoreRegister's" : "extCondCode's",
4699 ignore_rest_of_line ();
4706 /* 3rd: get register mode. */
4709 if (*input_line_pointer
!= ',')
4711 as_bad (_("expected comma after register number"));
4712 ignore_rest_of_line ();
4717 input_line_pointer
++;
4718 mode
= input_line_pointer
;
4720 if (!strncmp (mode
, "r|w", 3))
4723 input_line_pointer
+= 3;
4725 else if (!strncmp (mode
, "r", 1))
4727 imode
= ARC_REGISTER_READONLY
;
4728 input_line_pointer
+= 1;
4730 else if (strncmp (mode
, "w", 1))
4732 as_bad (_("invalid mode"));
4733 ignore_rest_of_line ();
4739 imode
= ARC_REGISTER_WRITEONLY
;
4740 input_line_pointer
+= 1;
4746 /* 4th: get core register shortcut. */
4748 if (*input_line_pointer
!= ',')
4750 as_bad (_("expected comma after register mode"));
4751 ignore_rest_of_line ();
4756 input_line_pointer
++;
4758 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4760 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4761 input_line_pointer
+= 15;
4763 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4765 as_bad (_("shortcut designator invalid"));
4766 ignore_rest_of_line ();
4772 input_line_pointer
+= 12;
4775 demand_empty_rest_of_line ();
4778 ereg
->number
= number
;
4779 ereg
->imode
= imode
;
4783 /* Create an extension register/condition description in the arc
4784 extension section of the output file.
4786 The structure for an instruction is like this:
4787 [0]: Length of the record.
4788 [1]: Type of the record.
4790 For core regs and condition codes:
4794 For auxiliary registers:
4798 The sequence is terminated by an empty entry. */
4801 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4803 segT old_sec
= now_seg
;
4804 int old_subsec
= now_subseg
;
4806 int name_len
= strlen (ereg
->name
);
4813 case EXT_CORE_REGISTER
:
4815 *p
= 3 + name_len
+ 1;
4821 case EXT_AUX_REGISTER
:
4823 *p
= 6 + name_len
+ 1;
4825 *p
= EXT_AUX_REGISTER
;
4827 *p
= (ereg
->number
>> 24) & 0xff;
4829 *p
= (ereg
->number
>> 16) & 0xff;
4831 *p
= (ereg
->number
>> 8) & 0xff;
4833 *p
= (ereg
->number
) & 0xff;
4839 p
= frag_more (name_len
+ 1);
4840 strcpy (p
, ereg
->name
);
4842 subseg_set (old_sec
, old_subsec
);
4845 /* Handler .extCoreRegister pseudo-op. */
4848 arc_extcorereg (int opertype
)
4851 struct arc_aux_reg
*auxr
;
4853 struct arc_flag_operand
*ccode
;
4855 memset (&ereg
, 0, sizeof (ereg
));
4856 if (!tokenize_extregister (&ereg
, opertype
))
4861 case EXT_CORE_REGISTER
:
4862 /* Core register. */
4863 if (ereg
.number
> 60)
4864 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4866 declare_register (ereg
.name
, ereg
.number
);
4868 case EXT_AUX_REGISTER
:
4869 /* Auxiliary register. */
4870 auxr
= XNEW (struct arc_aux_reg
);
4871 auxr
->name
= ereg
.name
;
4872 auxr
->cpu
= selected_cpu
.flags
;
4873 auxr
->subclass
= NONE
;
4874 auxr
->address
= ereg
.number
;
4875 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4877 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4878 auxr
->name
, retval
);
4881 /* Condition code. */
4882 if (ereg
.number
> 31)
4883 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4885 ext_condcode
.size
++;
4886 ext_condcode
.arc_ext_condcode
=
4887 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4888 ext_condcode
.size
+ 1);
4889 if (ext_condcode
.arc_ext_condcode
== NULL
)
4890 as_fatal (_("Virtual memory exhausted"));
4892 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4893 ccode
->name
= ereg
.name
;
4894 ccode
->code
= ereg
.number
;
4897 ccode
->favail
= 0; /* not used. */
4899 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4902 as_bad (_("Unknown extension"));
4905 create_extcore_section (&ereg
, opertype
);
4908 /* Parse a .arc_attribute directive. */
4911 arc_attribute (int ignored ATTRIBUTE_UNUSED
)
4913 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4915 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4916 attributes_set_explicitly
[tag
] = TRUE
;
4919 /* Set an attribute if it has not already been set by the user. */
4922 arc_set_attribute_int (int tag
, int value
)
4925 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4926 || !attributes_set_explicitly
[tag
])
4927 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
4931 arc_set_attribute_string (int tag
, const char *value
)
4934 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4935 || !attributes_set_explicitly
[tag
])
4936 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
4939 /* Allocate and concatenate two strings. s1 can be NULL but not
4940 s2. s1 pointer is freed at end of this procedure. */
4943 arc_stralloc (char * s1
, const char * s2
)
4949 len
= strlen (s1
) + 1;
4951 /* Only s1 can be null. */
4953 len
+= strlen (s2
) + 1;
4955 p
= (char *) xmalloc (len
);
4957 as_fatal (_("Virtual memory exhausted"));
4972 /* Set the public ARC object attributes. */
4975 arc_set_public_attributes (void)
4981 /* Tag_ARC_CPU_name. */
4982 arc_set_attribute_string (Tag_ARC_CPU_name
, selected_cpu
.name
);
4984 /* Tag_ARC_CPU_base. */
4985 switch (selected_cpu
.eflags
& EF_ARC_MACH_MSK
)
4987 case E_ARC_MACH_ARC600
:
4988 case E_ARC_MACH_ARC601
:
4989 base
= TAG_CPU_ARC6xx
;
4991 case E_ARC_MACH_ARC700
:
4992 base
= TAG_CPU_ARC7xx
;
4994 case EF_ARC_CPU_ARCV2EM
:
4995 base
= TAG_CPU_ARCEM
;
4997 case EF_ARC_CPU_ARCV2HS
:
4998 base
= TAG_CPU_ARCHS
;
5004 if (attributes_set_explicitly
[Tag_ARC_CPU_base
]
5005 && (base
!= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5007 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5008 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_CPU_base
, base
);
5010 /* Tag_ARC_ABI_osver. */
5011 if (attributes_set_explicitly
[Tag_ARC_ABI_osver
])
5013 int val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5016 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_OSABI_MSK
)
5017 | (val
& 0x0f << 8));
5021 arc_set_attribute_int (Tag_ARC_ABI_osver
, E_ARC_OSABI_CURRENT
>> 8);
5024 /* Tag_ARC_ISA_config. */
5025 arc_check_feature();
5027 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
5028 if (selected_cpu
.features
& feature_list
[i
].feature
)
5029 s
= arc_stralloc (s
, feature_list
[i
].attr
);
5032 arc_set_attribute_string (Tag_ARC_ISA_config
, s
);
5034 /* Tag_ARC_ISA_mpy_option. */
5035 arc_set_attribute_int (Tag_ARC_ISA_mpy_option
, mpy_option
);
5037 /* Tag_ARC_ABI_pic. */
5038 arc_set_attribute_int (Tag_ARC_ABI_pic
, pic_option
);
5040 /* Tag_ARC_ABI_sda. */
5041 arc_set_attribute_int (Tag_ARC_ABI_sda
, sda_option
);
5043 /* Tag_ARC_ABI_tls. */
5044 arc_set_attribute_int (Tag_ARC_ABI_tls
, tls_option
);
5046 /* Tag_ARC_ATR_version. */
5047 arc_set_attribute_int (Tag_ARC_ATR_version
, 1);
5049 /* Tag_ARC_ABI_rf16. */
5050 if (attributes_set_explicitly
[Tag_ARC_ABI_rf16
]
5051 && bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5055 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5057 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_ABI_rf16
, 0);
5061 /* Add the default contents for the .ARC.attributes section. */
5066 arc_set_public_attributes ();
5068 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
5069 as_fatal (_("could not set architecture and machine"));
5071 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
5074 void arc_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
5076 ARC_GET_FLAG (dest
) = ARC_GET_FLAG (src
);
5079 int arc_convert_symbolic_attribute (const char *name
)
5088 #define T(tag) {#tag, tag}
5089 T (Tag_ARC_PCS_config
),
5090 T (Tag_ARC_CPU_base
),
5091 T (Tag_ARC_CPU_variation
),
5092 T (Tag_ARC_CPU_name
),
5093 T (Tag_ARC_ABI_rf16
),
5094 T (Tag_ARC_ABI_osver
),
5095 T (Tag_ARC_ABI_sda
),
5096 T (Tag_ARC_ABI_pic
),
5097 T (Tag_ARC_ABI_tls
),
5098 T (Tag_ARC_ABI_enumsize
),
5099 T (Tag_ARC_ABI_exceptions
),
5100 T (Tag_ARC_ABI_double_size
),
5101 T (Tag_ARC_ISA_config
),
5102 T (Tag_ARC_ISA_apex
),
5103 T (Tag_ARC_ISA_mpy_option
),
5104 T (Tag_ARC_ATR_version
)
5112 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
5113 if (streq (name
, attribute_table
[i
].name
))
5114 return attribute_table
[i
].tag
;
5120 eval: (c-set-style "gnu")