1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 #ifndef TARGET_WITH_CPU
55 #define TARGET_WITH_CPU "arc700"
56 #endif /* TARGET_WITH_CPU */
58 /* Enum used to enumerate the relaxable ins operands. */
63 REGISTER_S
, /* Register for short instruction(s). */
64 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
65 REGISTER_DUP
, /* Duplication of previous operand of type register. */
99 #define regno(x) ((x) & 0x3F)
100 #define is_ir_num(x) (((x) & ~0x3F) == 0)
101 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
102 #define is_spfp_p(op) (((sc) == SPX))
103 #define is_dpfp_p(op) (((sc) == DPX))
104 #define is_fpuda_p(op) (((sc) == DPA))
105 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
106 || (op)->insn_class == JUMP))
107 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
108 #define is_nps400_p(op) (((sc) == NPS400))
110 /* Generic assembler global variables which must be defined by all
113 /* Characters which always start a comment. */
114 const char comment_chars
[] = "#;";
116 /* Characters which start a comment at the beginning of a line. */
117 const char line_comment_chars
[] = "#";
119 /* Characters which may be used to separate multiple commands on a
121 const char line_separator_chars
[] = "`";
123 /* Characters which are used to indicate an exponent in a floating
125 const char EXP_CHARS
[] = "eE";
127 /* Chars that mean this number is a floating point constant
128 As in 0f12.456 or 0d1.2345e12. */
129 const char FLT_CHARS
[] = "rRsSfFdD";
132 extern int target_big_endian
;
133 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
134 static int byte_order
= DEFAULT_BYTE_ORDER
;
136 /* Arc extension section. */
137 static segT arcext_section
;
139 /* By default relaxation is disabled. */
140 static int relaxation_state
= 0;
142 extern int arc_get_mach (char *);
144 /* Forward declarations. */
145 static void arc_lcomm (int);
146 static void arc_option (int);
147 static void arc_extra_reloc (int);
148 static void arc_extinsn (int);
149 static void arc_extcorereg (int);
151 const pseudo_typeS md_pseudo_table
[] =
153 /* Make sure that .word is 32 bits. */
156 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
157 { "lcomm", arc_lcomm
, 0 },
158 { "lcommon", arc_lcomm
, 0 },
159 { "cpu", arc_option
, 0 },
161 { "extinstruction", arc_extinsn
, 0 },
162 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
163 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
164 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
166 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
167 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
172 const char *md_shortopts
= "";
176 OPTION_EB
= OPTION_MD_BASE
,
194 /* The following options are deprecated and provided here only for
195 compatibility reasons. */
218 struct option md_longopts
[] =
220 { "EB", no_argument
, NULL
, OPTION_EB
},
221 { "EL", no_argument
, NULL
, OPTION_EL
},
222 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
223 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
224 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
225 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
226 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
227 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
228 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
229 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
230 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
231 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
232 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
234 /* Floating point options */
235 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
236 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
237 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
238 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
239 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
240 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
241 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
242 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
243 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
244 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
245 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
247 /* The following options are deprecated and provided here only for
248 compatibility reasons. */
249 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
250 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
251 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
252 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
253 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
254 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
255 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
256 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
257 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
258 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
259 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
260 { "mea", no_argument
, NULL
, OPTION_EA
},
261 { "mEA", no_argument
, NULL
, OPTION_EA
},
262 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
263 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
264 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
265 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
266 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
267 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
268 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
269 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
270 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
271 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
272 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
273 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
274 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
275 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
276 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
278 { NULL
, no_argument
, NULL
, 0 }
281 size_t md_longopts_size
= sizeof (md_longopts
);
283 /* Local data and data types. */
285 /* Used since new relocation types are introduced in this
286 file (DUMMY_RELOC_LITUSE_*). */
287 typedef int extended_bfd_reloc_code_real_type
;
293 extended_bfd_reloc_code_real_type reloc
;
295 /* index into arc_operands. */
296 unsigned int opindex
;
298 /* PC-relative, used by internals fixups. */
301 /* TRUE if this fixup is for LIMM operand. */
307 unsigned long long int insn
;
309 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
311 unsigned int len
; /* Length of instruction in bytes. */
312 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
314 bfd_boolean relax
; /* Boolean value: TRUE if needs
318 /* Structure to hold any last two instructions. */
319 static struct arc_last_insn
321 /* Saved instruction opcode. */
322 const struct arc_opcode
*opcode
;
324 /* Boolean value: TRUE if current insn is short. */
325 bfd_boolean has_limm
;
327 /* Boolean value: TRUE if current insn has delay slot. */
328 bfd_boolean has_delay_slot
;
331 /* Extension instruction suffix classes. */
339 static const attributes_t suffixclass
[] =
341 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
342 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
343 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
346 /* Extension instruction syntax classes. */
347 static const attributes_t syntaxclass
[] =
349 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
350 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
351 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
352 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
355 /* Extension instruction syntax classes modifiers. */
356 static const attributes_t syntaxclassmod
[] =
358 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
359 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
362 /* Extension register type. */
370 /* A structure to hold the additional conditional codes. */
373 struct arc_flag_operand
*arc_ext_condcode
;
375 } ext_condcode
= { NULL
, 0 };
377 /* Structure to hold an entry in ARC_OPCODE_HASH. */
378 struct arc_opcode_hash_entry
380 /* The number of pointers in the OPCODE list. */
383 /* Points to a list of opcode pointers. */
384 const struct arc_opcode
**opcode
;
387 /* Structure used for iterating through an arc_opcode_hash_entry. */
388 struct arc_opcode_hash_entry_iterator
390 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
393 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
394 returned by this iterator. */
395 const struct arc_opcode
*opcode
;
398 /* Forward declaration. */
399 static void assemble_insn
400 (const struct arc_opcode
*, const expressionS
*, int,
401 const struct arc_flags
*, int, struct arc_insn
*);
403 /* The selection of the machine type can come from different sources. This
404 enum is used to track how the selection was made in order to perform
406 enum mach_selection_type
409 MACH_SELECTION_FROM_DEFAULT
,
410 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
411 MACH_SELECTION_FROM_COMMAND_LINE
414 /* How the current machine type was selected. */
415 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
417 /* The hash table of instruction opcodes. */
418 static struct hash_control
*arc_opcode_hash
;
420 /* The hash table of register symbols. */
421 static struct hash_control
*arc_reg_hash
;
423 /* The hash table of aux register symbols. */
424 static struct hash_control
*arc_aux_hash
;
426 /* The hash table of address types. */
427 static struct hash_control
*arc_addrtype_hash
;
429 /* A table of CPU names and opcode sets. */
430 static const struct cpu_type
440 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
441 E_ARC_MACH_ARC600
, 0x00},
442 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
443 E_ARC_MACH_ARC700
, 0x00},
444 { "nps400", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
445 E_ARC_MACH_ARC700
, ARC_NPS400
},
446 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
447 EF_ARC_CPU_ARCV2EM
, 0x00},
448 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
449 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
453 /* Information about the cpu/variant we're assembling for. */
454 static struct cpu_type selected_cpu
= { 0, 0, 0, 0, 0 };
456 /* A table with options. */
457 static const struct feature_type
465 { ARC_CD
, ARC_OPCODE_ARCV2
, "code-density" },
466 { ARC_NPS400
, ARC_OPCODE_ARC700
, "nps400" },
467 { ARC_SPFP
, ARC_OPCODE_ARCFPX
, "single-precision FPX" },
468 { ARC_DPFP
, ARC_OPCODE_ARCFPX
, "double-precision FPX" },
469 { ARC_FPUDA
, ARC_OPCODE_ARCv2EM
, "double assist FP" }
472 /* Used by the arc_reloc_op table. Order is important. */
473 #define O_gotoff O_md1 /* @gotoff relocation. */
474 #define O_gotpc O_md2 /* @gotpc relocation. */
475 #define O_plt O_md3 /* @plt relocation. */
476 #define O_sda O_md4 /* @sda relocation. */
477 #define O_pcl O_md5 /* @pcl relocation. */
478 #define O_tlsgd O_md6 /* @tlsgd relocation. */
479 #define O_tlsie O_md7 /* @tlsie relocation. */
480 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
481 #define O_tpoff O_md9 /* @tpoff relocation. */
482 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
483 #define O_dtpoff O_md11 /* @dtpoff relocation. */
484 #define O_last O_dtpoff
486 /* Used to define a bracket as operand in tokens. */
487 #define O_bracket O_md32
489 /* Used to define a colon as an operand in tokens. */
490 #define O_colon O_md31
492 /* Used to define address types in nps400. */
493 #define O_addrtype O_md30
495 /* Dummy relocation, to be sorted out. */
496 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
498 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
500 /* A table to map the spelling of a relocation operand into an appropriate
501 bfd_reloc_code_real_type type. The table is assumed to be ordered such
502 that op-O_literal indexes into it. */
503 #define ARC_RELOC_TABLE(op) \
504 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
506 : (int) (op) - (int) O_gotoff) ])
508 #define DEF(NAME, RELOC, REQ) \
509 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
511 static const struct arc_reloc_op_tag
513 /* String to lookup. */
515 /* Size of the string. */
517 /* Which operator to use. */
519 extended_bfd_reloc_code_real_type reloc
;
520 /* Allows complex relocation expression like identifier@reloc +
522 unsigned int complex_expr
: 1;
526 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
527 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
528 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
529 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
530 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
531 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
532 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
533 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
534 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
535 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
536 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
539 static const int arc_num_reloc_op
540 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
542 /* Structure for relaxable instruction that have to be swapped with a
543 smaller alternative instruction. */
544 struct arc_relaxable_ins
546 /* Mnemonic that should be checked. */
547 const char *mnemonic_r
;
549 /* Operands that should be checked.
550 Indexes of operands from operand array. */
551 enum rlx_operand_type operands
[6];
553 /* Flags that should be checked. */
554 unsigned flag_classes
[5];
556 /* Mnemonic (smaller) alternative to be used later for relaxation. */
557 const char *mnemonic_alt
;
559 /* Index of operand that generic relaxation has to check. */
562 /* Base subtype index used. */
563 enum arc_rlx_types subtype
;
566 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
567 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
568 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
572 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
573 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
574 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
579 /* ARC relaxation table. */
580 const relax_typeS md_relax_table
[] =
587 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
588 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
592 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
593 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
598 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
599 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
600 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
602 /* LD_S a, [b, u7] ->
603 LD<zz><.x><.aa><.di> a, [b, s9] ->
604 LD<zz><.x><.aa><.di> a, [b, limm] */
605 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
606 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
607 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
612 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
613 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
614 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
618 SUB<.f> a, b, limm. */
619 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
620 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
621 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
623 /* MPY<.f> a, b, u6 ->
624 MPY<.f> a, b, limm. */
625 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
626 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
628 /* MOV<.f><.cc> b, u6 ->
629 MOV<.f><.cc> b, limm. */
630 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
631 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
633 /* ADD<.f><.cc> b, b, u6 ->
634 ADD<.f><.cc> b, b, limm. */
635 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
636 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
639 /* Order of this table's entries matters! */
640 const struct arc_relaxable_ins arc_relaxable_insns
[] =
642 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
643 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
644 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
645 2, ARC_RLX_ADD_RRU6
},
646 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
648 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
650 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
651 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
652 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
653 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
654 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
655 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
656 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
657 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
659 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
661 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
665 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
667 /* Flags to set in the elf header. */
668 static const flagword arc_initial_eflag
= 0x00;
670 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
671 symbolS
* GOT_symbol
= 0;
673 /* Set to TRUE when we assemble instructions. */
674 static bfd_boolean assembling_insn
= FALSE
;
676 /* Functions implementation. */
678 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
679 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
680 are no matching entries in ARC_OPCODE_HASH. */
682 static const struct arc_opcode_hash_entry
*
683 arc_find_opcode (const char *name
)
685 const struct arc_opcode_hash_entry
*entry
;
687 entry
= hash_find (arc_opcode_hash
, name
);
691 /* Initialise the iterator ITER. */
694 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
700 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
701 calls to this function. Return NULL when all ARC_OPCODE entries have
704 static const struct arc_opcode
*
705 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
706 struct arc_opcode_hash_entry_iterator
*iter
)
708 if (iter
->opcode
== NULL
&& iter
->index
== 0)
710 gas_assert (entry
->count
> 0);
711 iter
->opcode
= entry
->opcode
[iter
->index
];
713 else if (iter
->opcode
!= NULL
)
715 const char *old_name
= iter
->opcode
->name
;
718 if (iter
->opcode
->name
== NULL
719 || strcmp (old_name
, iter
->opcode
->name
) != 0)
722 if (iter
->index
== entry
->count
)
725 iter
->opcode
= entry
->opcode
[iter
->index
];
732 /* Insert an opcode into opcode hash structure. */
735 arc_insert_opcode (const struct arc_opcode
*opcode
)
737 const char *name
, *retval
;
738 struct arc_opcode_hash_entry
*entry
;
741 entry
= hash_find (arc_opcode_hash
, name
);
744 entry
= XNEW (struct arc_opcode_hash_entry
);
746 entry
->opcode
= NULL
;
748 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
750 as_fatal (_("internal error: can't hash opcode '%s': %s"),
754 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
757 if (entry
->opcode
== NULL
)
758 as_fatal (_("Virtual memory exhausted"));
760 entry
->opcode
[entry
->count
] = opcode
;
765 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
766 value, is encoded as 'middle-endian' for a little-endian target. This
767 function is used for regular 4, 6, and 8 byte instructions as well. */
770 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
775 md_number_to_chars (buf
, val
, n
);
778 md_number_to_chars (buf
, (val
& 0xffff00000000) >> 32, 2);
779 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
782 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
783 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
786 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000) >> 32, 4);
787 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
794 /* Check if a feature is allowed for a specific CPU. */
797 arc_check_feature (void)
801 if (!selected_cpu
.features
802 || !selected_cpu
.name
)
804 for (i
= 0; (i
< ARRAY_SIZE (feature_list
)); i
++)
806 if ((selected_cpu
.features
& feature_list
[i
].feature
)
807 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
809 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
815 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
816 the relevant static global variables. Parameter SEL describes where
817 this selection originated from. */
820 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
825 /* We should only set a default if we've not made a selection from some
827 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
828 || mach_selection_mode
== MACH_SELECTION_NONE
);
830 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
831 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
832 as_bad (_("Multiple .cpu directives found"));
834 /* Look for a matching entry in CPU_TYPES array. */
835 for (i
= 0; cpu_types
[i
].name
; ++i
)
837 if (!strcasecmp (cpu_types
[i
].name
, arg
))
839 /* If a previous selection was made on the command line, then we
840 allow later selections on the command line to override earlier
841 ones. However, a selection from a '.cpu NAME' directive must
842 match the command line selection, or we give a warning. */
843 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
845 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
846 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
847 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
848 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
850 as_warn (_("Command-line value overrides \".cpu\" directive"));
855 /* Initialise static global data about selected machine type. */
856 selected_cpu
.flags
= cpu_types
[i
].flags
;
857 selected_cpu
.name
= cpu_types
[i
].name
;
858 selected_cpu
.features
|= cpu_types
[i
].features
;
859 selected_cpu
.mach
= cpu_types
[i
].mach
;
860 cpu_flags
= cpu_types
[i
].eflags
;
865 if (!cpu_types
[i
].name
)
866 as_fatal (_("unknown architecture: %s\n"), arg
);
868 /* Check if set features are compatible with the chosen CPU. */
869 arc_check_feature ();
870 gas_assert (cpu_flags
!= 0);
871 selected_cpu
.eflags
= (arc_initial_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
872 mach_selection_mode
= sel
;
875 /* Here ends all the ARCompact extension instruction assembling
879 arc_extra_reloc (int r_type
)
882 symbolS
*sym
, *lab
= NULL
;
884 if (*input_line_pointer
== '@')
885 input_line_pointer
++;
886 c
= get_symbol_name (&sym_name
);
887 sym
= symbol_find_or_make (sym_name
);
888 restore_line_pointer (c
);
889 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
891 ++input_line_pointer
;
893 c
= get_symbol_name (&lab_name
);
894 lab
= symbol_find_or_make (lab_name
);
895 restore_line_pointer (c
);
898 /* These relocations exist as a mechanism for the compiler to tell the
899 linker how to patch the code if the tls model is optimised. However,
900 the relocation itself does not require any space within the assembler
901 fragment, and so we pass a size of 0.
903 The lines that generate these relocations look like this:
905 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
907 The '.tls_gd_ld @.tdata' is processed first and generates the
908 additional relocation, while the 'bl __tls_get_addr@plt' is processed
909 second and generates the additional branch.
911 It is possible that the additional relocation generated by the
912 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
913 while the 'bl __tls_get_addr@plt' will be generated as the first thing
914 in the next fragment. This will be fine; both relocations will still
915 appear to be at the same address in the generated object file.
916 However, this only works as the additional relocation is generated
917 with size of 0 bytes. */
919 = fix_new (frag_now
, /* Which frag? */
920 frag_now_fix (), /* Where in that frag? */
921 0, /* size: 1, 2, or 4 usually. */
922 sym
, /* X_add_symbol. */
923 0, /* X_add_number. */
924 FALSE
, /* TRUE if PC-relative relocation. */
925 r_type
/* Relocation type. */);
926 fixP
->fx_subsy
= lab
;
930 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
931 symbolS
*symbolP
, addressT size
)
936 if (*input_line_pointer
== ',')
938 align
= parse_align (1);
940 if (align
== (addressT
) -1)
955 bss_alloc (symbolP
, size
, align
);
956 S_CLEAR_EXTERNAL (symbolP
);
962 arc_lcomm (int ignore
)
964 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
967 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
970 /* Select the cpu we're assembling for. */
973 arc_option (int ignore ATTRIBUTE_UNUSED
)
977 const char *cpu_name
;
979 c
= get_symbol_name (&cpu
);
981 if ((!strcmp ("ARC600", cpu
))
982 || (!strcmp ("ARC601", cpu
))
983 || (!strcmp ("A6", cpu
)))
985 else if ((!strcmp ("ARC700", cpu
))
986 || (!strcmp ("A7", cpu
)))
988 else if (!strcmp ("EM", cpu
))
990 else if (!strcmp ("HS", cpu
))
992 else if (!strcmp ("NPS400", cpu
))
997 if (cpu_name
!= NULL
)
998 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1000 as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu
);
1002 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
1003 as_fatal (_("could not set architecture and machine"));
1005 /* Set elf header flags. */
1006 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
1008 restore_line_pointer (c
);
1009 demand_empty_rest_of_line ();
1012 /* Smartly print an expression. */
1015 debug_exp (expressionS
*t
)
1017 const char *name ATTRIBUTE_UNUSED
;
1018 const char *namemd ATTRIBUTE_UNUSED
;
1020 pr_debug ("debug_exp: ");
1024 default: name
= "unknown"; break;
1025 case O_illegal
: name
= "O_illegal"; break;
1026 case O_absent
: name
= "O_absent"; break;
1027 case O_constant
: name
= "O_constant"; break;
1028 case O_symbol
: name
= "O_symbol"; break;
1029 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1030 case O_register
: name
= "O_register"; break;
1031 case O_big
: name
= "O_big"; break;
1032 case O_uminus
: name
= "O_uminus"; break;
1033 case O_bit_not
: name
= "O_bit_not"; break;
1034 case O_logical_not
: name
= "O_logical_not"; break;
1035 case O_multiply
: name
= "O_multiply"; break;
1036 case O_divide
: name
= "O_divide"; break;
1037 case O_modulus
: name
= "O_modulus"; break;
1038 case O_left_shift
: name
= "O_left_shift"; break;
1039 case O_right_shift
: name
= "O_right_shift"; break;
1040 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1041 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1042 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1043 case O_bit_and
: name
= "O_bit_and"; break;
1044 case O_add
: name
= "O_add"; break;
1045 case O_subtract
: name
= "O_subtract"; break;
1046 case O_eq
: name
= "O_eq"; break;
1047 case O_ne
: name
= "O_ne"; break;
1048 case O_lt
: name
= "O_lt"; break;
1049 case O_le
: name
= "O_le"; break;
1050 case O_ge
: name
= "O_ge"; break;
1051 case O_gt
: name
= "O_gt"; break;
1052 case O_logical_and
: name
= "O_logical_and"; break;
1053 case O_logical_or
: name
= "O_logical_or"; break;
1054 case O_index
: name
= "O_index"; break;
1055 case O_bracket
: name
= "O_bracket"; break;
1056 case O_colon
: name
= "O_colon"; break;
1057 case O_addrtype
: name
= "O_addrtype"; break;
1062 default: namemd
= "unknown"; break;
1063 case O_gotoff
: namemd
= "O_gotoff"; break;
1064 case O_gotpc
: namemd
= "O_gotpc"; break;
1065 case O_plt
: namemd
= "O_plt"; break;
1066 case O_sda
: namemd
= "O_sda"; break;
1067 case O_pcl
: namemd
= "O_pcl"; break;
1068 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1069 case O_tlsie
: namemd
= "O_tlsie"; break;
1070 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1071 case O_tpoff
: namemd
= "O_tpoff"; break;
1072 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1073 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1076 pr_debug ("%s (%s, %s, %d, %s)", name
,
1077 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1078 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1079 (int) t
->X_add_number
,
1080 (t
->X_md
) ? namemd
: "--");
1085 /* Parse the arguments to an opcode. */
1088 tokenize_arguments (char *str
,
1092 char *old_input_line_pointer
;
1093 bfd_boolean saw_comma
= FALSE
;
1094 bfd_boolean saw_arg
= FALSE
;
1099 const struct arc_reloc_op_tag
*r
;
1101 char *reloc_name
, c
;
1103 memset (tok
, 0, sizeof (*tok
) * ntok
);
1105 /* Save and restore input_line_pointer around this function. */
1106 old_input_line_pointer
= input_line_pointer
;
1107 input_line_pointer
= str
;
1109 while (*input_line_pointer
)
1112 switch (*input_line_pointer
)
1118 input_line_pointer
++;
1119 if (saw_comma
|| !saw_arg
)
1126 ++input_line_pointer
;
1128 if (!saw_arg
|| num_args
== ntok
)
1130 tok
->X_op
= O_bracket
;
1137 input_line_pointer
++;
1138 if (brk_lvl
|| num_args
== ntok
)
1141 tok
->X_op
= O_bracket
;
1147 input_line_pointer
++;
1148 if (!saw_arg
|| num_args
== ntok
)
1150 tok
->X_op
= O_colon
;
1157 /* We have labels, function names and relocations, all
1158 starting with @ symbol. Sort them out. */
1159 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1163 tok
->X_op
= O_symbol
;
1164 tok
->X_md
= O_absent
;
1166 if (*input_line_pointer
!= '@')
1167 goto normalsymbol
; /* This is not a relocation. */
1171 /* A relocation opernad has the following form
1172 @identifier@relocation_type. The identifier is already
1174 if (tok
->X_op
!= O_symbol
)
1176 as_bad (_("No valid label relocation operand"));
1180 /* Parse @relocation_type. */
1181 input_line_pointer
++;
1182 c
= get_symbol_name (&reloc_name
);
1183 len
= input_line_pointer
- reloc_name
;
1186 as_bad (_("No relocation operand"));
1190 /* Go through known relocation and try to find a match. */
1191 r
= &arc_reloc_op
[0];
1192 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1193 if (len
== r
->length
1194 && memcmp (reloc_name
, r
->name
, len
) == 0)
1198 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1202 *input_line_pointer
= c
;
1203 SKIP_WHITESPACE_AFTER_NAME ();
1204 /* Extra check for TLS: base. */
1205 if (*input_line_pointer
== '@')
1208 if (tok
->X_op_symbol
!= NULL
1209 || tok
->X_op
!= O_symbol
)
1211 as_bad (_("Unable to parse TLS base: %s"),
1212 input_line_pointer
);
1215 input_line_pointer
++;
1217 c
= get_symbol_name (&sym_name
);
1218 base
= symbol_find_or_make (sym_name
);
1219 tok
->X_op
= O_subtract
;
1220 tok
->X_op_symbol
= base
;
1221 restore_line_pointer (c
);
1222 tmpE
.X_add_number
= 0;
1224 if ((*input_line_pointer
!= '+')
1225 && (*input_line_pointer
!= '-'))
1227 tmpE
.X_add_number
= 0;
1231 /* Parse the constant of a complex relocation expression
1232 like @identifier@reloc +/- const. */
1233 if (! r
->complex_expr
)
1235 as_bad (_("@%s is not a complex relocation."), r
->name
);
1239 if (tmpE
.X_op
!= O_constant
)
1241 as_bad (_("Bad expression: @%s + %s."),
1242 r
->name
, input_line_pointer
);
1248 tok
->X_add_number
= tmpE
.X_add_number
;
1259 /* Can be a register. */
1260 ++input_line_pointer
;
1264 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1267 tok
->X_op
= O_absent
;
1268 tok
->X_md
= O_absent
;
1271 /* Legacy: There are cases when we have
1272 identifier@relocation_type, if it is the case parse the
1273 relocation type as well. */
1274 if (*input_line_pointer
== '@')
1280 if (tok
->X_op
== O_illegal
1281 || tok
->X_op
== O_absent
1282 || num_args
== ntok
)
1294 if (saw_comma
|| brk_lvl
)
1296 input_line_pointer
= old_input_line_pointer
;
1302 as_bad (_("Brackets in operand field incorrect"));
1304 as_bad (_("extra comma"));
1306 as_bad (_("missing argument"));
1308 as_bad (_("missing comma or colon"));
1309 input_line_pointer
= old_input_line_pointer
;
1313 /* Parse the flags to a structure. */
1316 tokenize_flags (const char *str
,
1317 struct arc_flags flags
[],
1320 char *old_input_line_pointer
;
1321 bfd_boolean saw_flg
= FALSE
;
1322 bfd_boolean saw_dot
= FALSE
;
1326 memset (flags
, 0, sizeof (*flags
) * nflg
);
1328 /* Save and restore input_line_pointer around this function. */
1329 old_input_line_pointer
= input_line_pointer
;
1330 input_line_pointer
= (char *) str
;
1332 while (*input_line_pointer
)
1334 switch (*input_line_pointer
)
1341 input_line_pointer
++;
1349 if (saw_flg
&& !saw_dot
)
1352 if (num_flags
>= nflg
)
1355 flgnamelen
= strspn (input_line_pointer
,
1356 "abcdefghijklmnopqrstuvwxyz0123456789");
1357 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1360 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1362 input_line_pointer
+= flgnamelen
;
1372 input_line_pointer
= old_input_line_pointer
;
1377 as_bad (_("extra dot"));
1379 as_bad (_("unrecognized flag"));
1381 as_bad (_("failed to parse flags"));
1382 input_line_pointer
= old_input_line_pointer
;
1386 /* Apply the fixups in order. */
1389 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1393 for (i
= 0; i
< insn
->nfixups
; i
++)
1395 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1396 int size
, pcrel
, offset
= 0;
1398 /* FIXME! the reloc size is wrong in the BFD file.
1399 When it is fixed please delete me. */
1400 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1405 /* Some fixups are only used internally, thus no howto. */
1406 if ((int) fixup
->reloc
== 0)
1407 as_fatal (_("Unhandled reloc type"));
1409 if ((int) fixup
->reloc
< 0)
1411 /* FIXME! the reloc size is wrong in the BFD file.
1412 When it is fixed please enable me.
1413 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1414 pcrel
= fixup
->pcrel
;
1418 reloc_howto_type
*reloc_howto
=
1419 bfd_reloc_type_lookup (stdoutput
,
1420 (bfd_reloc_code_real_type
) fixup
->reloc
);
1421 gas_assert (reloc_howto
);
1423 /* FIXME! the reloc size is wrong in the BFD file.
1424 When it is fixed please enable me.
1425 size = bfd_get_reloc_size (reloc_howto); */
1426 pcrel
= reloc_howto
->pc_relative
;
1429 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1431 fragP
->fr_file
, fragP
->fr_line
,
1432 (fixup
->reloc
< 0) ? "Internal" :
1433 bfd_get_reloc_code_name (fixup
->reloc
),
1436 fix_new_exp (fragP
, fix
+ offset
,
1437 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1439 /* Check for ZOLs, and update symbol info if any. */
1440 if (LP_INSN (insn
->insn
))
1442 gas_assert (fixup
->exp
.X_add_symbol
);
1443 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1448 /* Actually output an instruction with its fixup. */
1451 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1456 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1457 pr_debug ("\tLength : 0x%d\n", insn
->len
);
1458 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1460 /* Write out the instruction. */
1461 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1463 f
= frag_more (total_len
);
1465 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1468 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1469 dwarf2_emit_insn (total_len
);
1472 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1476 emit_insn1 (struct arc_insn
*insn
)
1478 /* How frag_var's args are currently configured:
1479 - rs_machine_dependent, to dictate it's a relaxation frag.
1480 - FRAG_MAX_GROWTH, maximum size of instruction
1481 - 0, variable size that might grow...unused by generic relaxation.
1482 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1483 - s, opand expression.
1484 - 0, offset but it's unused.
1485 - 0, opcode but it's unused. */
1486 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1487 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1489 if (frag_room () < FRAG_MAX_GROWTH
)
1491 /* Handle differently when frag literal memory is exhausted.
1492 This is used because when there's not enough memory left in
1493 the current frag, a new frag is created and the information
1494 we put into frag_now->tc_frag_data is disregarded. */
1496 struct arc_relax_type relax_info_copy
;
1497 relax_substateT subtype
= frag_now
->fr_subtype
;
1499 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1500 sizeof (struct arc_relax_type
));
1502 frag_wane (frag_now
);
1503 frag_grow (FRAG_MAX_GROWTH
);
1505 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1506 sizeof (struct arc_relax_type
));
1508 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1512 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1513 frag_now
->fr_subtype
, s
, 0, 0);
1517 emit_insn (struct arc_insn
*insn
)
1522 emit_insn0 (insn
, NULL
, FALSE
);
1525 /* Check whether a symbol involves a register. */
1528 contains_register (symbolS
*sym
)
1532 expressionS
*ex
= symbol_get_value_expression (sym
);
1534 return ((O_register
== ex
->X_op
)
1535 && !contains_register (ex
->X_add_symbol
)
1536 && !contains_register (ex
->X_op_symbol
));
1542 /* Returns the register number within a symbol. */
1545 get_register (symbolS
*sym
)
1547 if (!contains_register (sym
))
1550 expressionS
*ex
= symbol_get_value_expression (sym
);
1551 return regno (ex
->X_add_number
);
1554 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1555 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1558 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1565 case BFD_RELOC_ARC_SDA_LDST
:
1566 case BFD_RELOC_ARC_SDA_LDST1
:
1567 case BFD_RELOC_ARC_SDA_LDST2
:
1568 case BFD_RELOC_ARC_SDA16_LD
:
1569 case BFD_RELOC_ARC_SDA16_LD1
:
1570 case BFD_RELOC_ARC_SDA16_LD2
:
1571 case BFD_RELOC_ARC_SDA16_ST2
:
1572 case BFD_RELOC_ARC_SDA32_ME
:
1579 /* Allocates a tok entry. */
1582 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1584 if (ntok
> MAX_INSN_ARGS
- 2)
1585 return 0; /* No space left. */
1588 return 0; /* Incorect args. */
1590 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1593 return 1; /* Success. */
1594 return allocate_tok (tok
, ntok
- 1, cidx
);
1597 /* Check if an particular ARC feature is enabled. */
1600 check_cpu_feature (insn_subclass_t sc
)
1602 if (is_code_density_p (sc
) && !(selected_cpu
.features
& ARC_CD
))
1605 if (is_spfp_p (sc
) && !(selected_cpu
.features
& ARC_SPFP
))
1608 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& ARC_DPFP
))
1611 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& ARC_FPUDA
))
1614 if (is_nps400_p (sc
) && !(selected_cpu
.features
& ARC_NPS400
))
1620 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1621 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1622 array and returns TRUE if the flag operands all match, otherwise,
1623 returns FALSE, in which case the FIRST_PFLAG array may have been
1627 parse_opcode_flags (const struct arc_opcode
*opcode
,
1629 struct arc_flags
*first_pflag
)
1632 const unsigned char *flgidx
;
1635 for (i
= 0; i
< nflgs
; i
++)
1636 first_pflag
[i
].flgp
= NULL
;
1638 /* Check the flags. Iterate over the valid flag classes. */
1639 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1641 /* Get a valid flag class. */
1642 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1643 const unsigned *flgopridx
;
1645 struct arc_flags
*pflag
= NULL
;
1647 /* Check for extension conditional codes. */
1648 if (ext_condcode
.arc_ext_condcode
1649 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1651 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1654 pflag
= first_pflag
;
1655 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1657 if (!strcmp (pf
->name
, pflag
->name
))
1659 if (pflag
->flgp
!= NULL
)
1672 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1674 const struct arc_flag_operand
*flg_operand
;
1676 pflag
= first_pflag
;
1677 flg_operand
= &arc_flag_operands
[*flgopridx
];
1678 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1680 /* Match against the parsed flags. */
1681 if (!strcmp (flg_operand
->name
, pflag
->name
))
1683 if (pflag
->flgp
!= NULL
)
1686 pflag
->flgp
= flg_operand
;
1688 break; /* goto next flag class and parsed flag. */
1693 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1695 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1699 /* Did I check all the parsed flags? */
1700 return lnflg
? FALSE
: TRUE
;
1704 /* Search forward through all variants of an opcode looking for a
1707 static const struct arc_opcode
*
1708 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1711 struct arc_flags
*first_pflag
,
1714 const char **errmsg
)
1716 const struct arc_opcode
*opcode
;
1717 struct arc_opcode_hash_entry_iterator iter
;
1719 int got_cpu_match
= 0;
1720 expressionS bktok
[MAX_INSN_ARGS
];
1724 arc_opcode_hash_entry_iterator_init (&iter
);
1725 memset (&emptyE
, 0, sizeof (emptyE
));
1726 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1729 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1731 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1733 const unsigned char *opidx
;
1735 const expressionS
*t
= &emptyE
;
1737 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1738 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1740 /* Don't match opcodes that don't exist on this
1742 if (!(opcode
->cpu
& selected_cpu
.flags
))
1745 if (!check_cpu_feature (opcode
->subclass
))
1751 /* Check the operands. */
1752 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1754 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1756 /* Only take input from real operands. */
1757 if (ARC_OPERAND_IS_FAKE (operand
))
1760 /* When we expect input, make sure we have it. */
1764 /* Match operand type with expression type. */
1765 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1767 case ARC_OPERAND_ADDRTYPE
:
1771 /* Check to be an address type. */
1772 if (tok
[tokidx
].X_op
!= O_addrtype
)
1775 /* All address type operands need to have an insert
1776 method in order to check that we have the correct
1778 gas_assert (operand
->insert
!= NULL
);
1779 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1781 if (*errmsg
!= NULL
)
1786 case ARC_OPERAND_IR
:
1787 /* Check to be a register. */
1788 if ((tok
[tokidx
].X_op
!= O_register
1789 || !is_ir_num (tok
[tokidx
].X_add_number
))
1790 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1793 /* If expect duplicate, make sure it is duplicate. */
1794 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1796 /* Check for duplicate. */
1797 if (t
->X_op
!= O_register
1798 || !is_ir_num (t
->X_add_number
)
1799 || (regno (t
->X_add_number
) !=
1800 regno (tok
[tokidx
].X_add_number
)))
1804 /* Special handling? */
1805 if (operand
->insert
)
1808 (*operand
->insert
)(0,
1809 regno (tok
[tokidx
].X_add_number
),
1813 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1815 /* Missing argument, create one. */
1816 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1819 tok
[tokidx
].X_op
= O_absent
;
1830 case ARC_OPERAND_BRAKET
:
1831 /* Check if bracket is also in opcode table as
1833 if (tok
[tokidx
].X_op
!= O_bracket
)
1837 case ARC_OPERAND_COLON
:
1838 /* Check if colon is also in opcode table as operand. */
1839 if (tok
[tokidx
].X_op
!= O_colon
)
1843 case ARC_OPERAND_LIMM
:
1844 case ARC_OPERAND_SIGNED
:
1845 case ARC_OPERAND_UNSIGNED
:
1846 switch (tok
[tokidx
].X_op
)
1854 /* Got an (too) early bracket, check if it is an
1855 ignored operand. N.B. This procedure works only
1856 when bracket is the last operand! */
1857 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1859 /* Insert the missing operand. */
1860 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1863 tok
[tokidx
].X_op
= O_absent
;
1870 const struct arc_aux_reg
*auxr
;
1872 if (opcode
->insn_class
!= AUXREG
)
1874 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1876 auxr
= hash_find (arc_aux_hash
, p
);
1879 /* We modify the token array here, safe in the
1880 knowledge, that if this was the wrong
1881 choice then the original contents will be
1882 restored from BKTOK. */
1883 tok
[tokidx
].X_op
= O_constant
;
1884 tok
[tokidx
].X_add_number
= auxr
->address
;
1885 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1888 if (tok
[tokidx
].X_op
!= O_constant
)
1893 /* Check the range. */
1894 if (operand
->bits
!= 32
1895 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1897 offsetT min
, max
, val
;
1898 val
= tok
[tokidx
].X_add_number
;
1900 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1902 max
= (1 << (operand
->bits
- 1)) - 1;
1903 min
= -(1 << (operand
->bits
- 1));
1907 max
= (1 << operand
->bits
) - 1;
1911 if (val
< min
|| val
> max
)
1914 /* Check alignmets. */
1915 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1919 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1923 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1925 if (operand
->insert
)
1928 (*operand
->insert
)(0,
1929 tok
[tokidx
].X_add_number
,
1934 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1940 /* Check if it is register range. */
1941 if ((tok
[tokidx
].X_add_number
== 0)
1942 && contains_register (tok
[tokidx
].X_add_symbol
)
1943 && contains_register (tok
[tokidx
].X_op_symbol
))
1947 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1949 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1950 if (operand
->insert
)
1953 (*operand
->insert
)(0,
1966 if (operand
->default_reloc
== 0)
1967 goto match_failed
; /* The operand needs relocation. */
1969 /* Relocs requiring long immediate. FIXME! make it
1970 generic and move it to a function. */
1971 switch (tok
[tokidx
].X_md
)
1980 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1984 if (!generic_reloc_p (operand
->default_reloc
))
1992 /* If expect duplicate, make sure it is duplicate. */
1993 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1995 if (t
->X_op
== O_illegal
1996 || t
->X_op
== O_absent
1997 || t
->X_op
== O_register
1998 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2005 /* Everything else should have been fake. */
2013 /* Setup ready for flag parsing. */
2014 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2018 /* Possible match -- did we use all of our input? */
2028 /* Restore the original parameters. */
2029 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2034 *pcpumatch
= got_cpu_match
;
2039 /* Swap operand tokens. */
2042 swap_operand (expressionS
*operand_array
,
2044 unsigned destination
)
2046 expressionS cpy_operand
;
2047 expressionS
*src_operand
;
2048 expressionS
*dst_operand
;
2051 if (source
== destination
)
2054 src_operand
= &operand_array
[source
];
2055 dst_operand
= &operand_array
[destination
];
2056 size
= sizeof (expressionS
);
2058 /* Make copy of operand to swap with and swap. */
2059 memcpy (&cpy_operand
, dst_operand
, size
);
2060 memcpy (dst_operand
, src_operand
, size
);
2061 memcpy (src_operand
, &cpy_operand
, size
);
2064 /* Check if *op matches *tok type.
2065 Returns FALSE if they don't match, TRUE if they match. */
2068 pseudo_operand_match (const expressionS
*tok
,
2069 const struct arc_operand_operation
*op
)
2071 offsetT min
, max
, val
;
2073 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2079 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2081 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2083 val
= tok
->X_add_number
+ op
->count
;
2084 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2086 max
= (1 << (operand_real
->bits
- 1)) - 1;
2087 min
= -(1 << (operand_real
->bits
- 1));
2091 max
= (1 << operand_real
->bits
) - 1;
2094 if (min
<= val
&& val
<= max
)
2100 /* Handle all symbols as long immediates or signed 9. */
2101 if (operand_real
->flags
& ARC_OPERAND_LIMM
2102 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2103 && operand_real
->bits
== 9))
2108 if (operand_real
->flags
& ARC_OPERAND_IR
)
2113 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2124 /* Find pseudo instruction in array. */
2126 static const struct arc_pseudo_insn
*
2127 find_pseudo_insn (const char *opname
,
2129 const expressionS
*tok
)
2131 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2132 const struct arc_operand_operation
*op
;
2136 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2138 pseudo_insn
= &arc_pseudo_insns
[i
];
2139 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2141 op
= pseudo_insn
->operand
;
2142 for (j
= 0; j
< ntok
; ++j
)
2143 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2146 /* Found the right instruction. */
2154 /* Assumes the expressionS *tok is of sufficient size. */
2156 static const struct arc_opcode_hash_entry
*
2157 find_special_case_pseudo (const char *opname
,
2161 struct arc_flags
*pflags
)
2163 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2164 const struct arc_operand_operation
*operand_pseudo
;
2165 const struct arc_operand
*operand_real
;
2167 char construct_operand
[MAX_CONSTR_STR
];
2169 /* Find whether opname is in pseudo instruction array. */
2170 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2172 if (pseudo_insn
== NULL
)
2175 /* Handle flag, Limited to one flag at the moment. */
2176 if (pseudo_insn
->flag_r
!= NULL
)
2177 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2178 MAX_INSN_FLGS
- *nflgs
);
2180 /* Handle operand operations. */
2181 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2183 operand_pseudo
= &pseudo_insn
->operand
[i
];
2184 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2186 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2187 && !operand_pseudo
->needs_insert
)
2190 /* Has to be inserted (i.e. this token does not exist yet). */
2191 if (operand_pseudo
->needs_insert
)
2193 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2195 tok
[i
].X_op
= O_bracket
;
2200 /* Check if operand is a register or constant and handle it
2202 if (operand_real
->flags
& ARC_OPERAND_IR
)
2203 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2204 operand_pseudo
->count
);
2206 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2207 operand_pseudo
->count
);
2209 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2213 else if (operand_pseudo
->count
)
2215 /* Operand number has to be adjusted accordingly (by operand
2217 switch (tok
[i
].X_op
)
2220 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2233 /* Swap operands if necessary. Only supports one swap at the
2235 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2237 operand_pseudo
= &pseudo_insn
->operand
[i
];
2239 if (operand_pseudo
->swap_operand_idx
== i
)
2242 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2244 /* Prevent a swap back later by breaking out. */
2248 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2251 static const struct arc_opcode_hash_entry
*
2252 find_special_case_flag (const char *opname
,
2254 struct arc_flags
*pflags
)
2258 unsigned flag_idx
, flag_arr_idx
;
2259 size_t flaglen
, oplen
;
2260 const struct arc_flag_special
*arc_flag_special_opcode
;
2261 const struct arc_opcode_hash_entry
*entry
;
2263 /* Search for special case instruction. */
2264 for (i
= 0; i
< arc_num_flag_special
; i
++)
2266 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2267 oplen
= strlen (arc_flag_special_opcode
->name
);
2269 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2272 /* Found a potential special case instruction, now test for
2274 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2276 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2278 break; /* End of array, nothing found. */
2280 flagnm
= arc_flag_operands
[flag_idx
].name
;
2281 flaglen
= strlen (flagnm
);
2282 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2284 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2286 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2288 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2289 pflags
[*nflgs
].name
[flaglen
] = '\0';
2298 /* Used to find special case opcode. */
2300 static const struct arc_opcode_hash_entry
*
2301 find_special_case (const char *opname
,
2303 struct arc_flags
*pflags
,
2307 const struct arc_opcode_hash_entry
*entry
;
2309 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2312 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2317 /* Given an opcode name, pre-tockenized set of argumenst and the
2318 opcode flags, take it all the way through emission. */
2321 assemble_tokens (const char *opname
,
2324 struct arc_flags
*pflags
,
2327 bfd_boolean found_something
= FALSE
;
2328 const struct arc_opcode_hash_entry
*entry
;
2330 const char *errmsg
= NULL
;
2332 /* Search opcodes. */
2333 entry
= arc_find_opcode (opname
);
2335 /* Couldn't find opcode conventional way, try special cases. */
2337 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2341 const struct arc_opcode
*opcode
;
2343 pr_debug ("%s:%d: assemble_tokens: %s\n",
2344 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2345 found_something
= TRUE
;
2346 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2347 nflgs
, &cpumatch
, &errmsg
);
2350 struct arc_insn insn
;
2352 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2358 if (found_something
)
2362 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2364 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2366 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2370 as_bad (_("unknown opcode '%s'"), opname
);
2373 /* The public interface to the instruction assembler. */
2376 md_assemble (char *str
)
2379 expressionS tok
[MAX_INSN_ARGS
];
2382 struct arc_flags flags
[MAX_INSN_FLGS
];
2384 /* Split off the opcode. */
2385 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2386 opname
= xmemdup0 (str
, opnamelen
);
2388 /* Signalize we are assmbling the instructions. */
2389 assembling_insn
= TRUE
;
2391 /* Tokenize the flags. */
2392 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2394 as_bad (_("syntax error"));
2398 /* Scan up to the end of the mnemonic which must end in space or end
2401 for (; *str
!= '\0'; str
++)
2405 /* Tokenize the rest of the line. */
2406 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2408 as_bad (_("syntax error"));
2412 /* Finish it off. */
2413 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2414 assembling_insn
= FALSE
;
2417 /* Callback to insert a register into the hash table. */
2420 declare_register (const char *name
, int number
)
2423 symbolS
*regS
= symbol_create (name
, reg_section
,
2424 number
, &zero_address_frag
);
2426 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2428 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2432 /* Construct symbols for each of the general registers. */
2435 declare_register_set (void)
2438 for (i
= 0; i
< 64; ++i
)
2442 sprintf (name
, "r%d", i
);
2443 declare_register (name
, i
);
2444 if ((i
& 0x01) == 0)
2446 sprintf (name
, "r%dr%d", i
, i
+1);
2447 declare_register (name
, i
);
2452 /* Construct a symbol for an address type. */
2455 declare_addrtype (const char *name
, int number
)
2458 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2459 number
, &zero_address_frag
);
2461 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2462 (void *) addrtypeS
);
2464 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2468 /* Port-specific assembler initialization. This function is called
2469 once, at assembler startup time. */
2474 const struct arc_opcode
*opcode
= arc_opcodes
;
2476 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2477 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2479 /* The endianness can be chosen "at the factory". */
2480 target_big_endian
= byte_order
== BIG_ENDIAN
;
2482 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2483 as_warn (_("could not set architecture and machine"));
2485 /* Set elf header flags. */
2486 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2488 /* Set up a hash table for the instructions. */
2489 arc_opcode_hash
= hash_new ();
2490 if (arc_opcode_hash
== NULL
)
2491 as_fatal (_("Virtual memory exhausted"));
2493 /* Initialize the hash table with the insns. */
2496 const char *name
= opcode
->name
;
2498 arc_insert_opcode (opcode
);
2500 while (++opcode
&& opcode
->name
2501 && (opcode
->name
== name
2502 || !strcmp (opcode
->name
, name
)))
2504 }while (opcode
->name
);
2506 /* Register declaration. */
2507 arc_reg_hash
= hash_new ();
2508 if (arc_reg_hash
== NULL
)
2509 as_fatal (_("Virtual memory exhausted"));
2511 declare_register_set ();
2512 declare_register ("gp", 26);
2513 declare_register ("fp", 27);
2514 declare_register ("sp", 28);
2515 declare_register ("ilink", 29);
2516 declare_register ("ilink1", 29);
2517 declare_register ("ilink2", 30);
2518 declare_register ("blink", 31);
2520 /* XY memory registers. */
2521 declare_register ("x0_u0", 32);
2522 declare_register ("x0_u1", 33);
2523 declare_register ("x1_u0", 34);
2524 declare_register ("x1_u1", 35);
2525 declare_register ("x2_u0", 36);
2526 declare_register ("x2_u1", 37);
2527 declare_register ("x3_u0", 38);
2528 declare_register ("x3_u1", 39);
2529 declare_register ("y0_u0", 40);
2530 declare_register ("y0_u1", 41);
2531 declare_register ("y1_u0", 42);
2532 declare_register ("y1_u1", 43);
2533 declare_register ("y2_u0", 44);
2534 declare_register ("y2_u1", 45);
2535 declare_register ("y3_u0", 46);
2536 declare_register ("y3_u1", 47);
2537 declare_register ("x0_nu", 48);
2538 declare_register ("x1_nu", 49);
2539 declare_register ("x2_nu", 50);
2540 declare_register ("x3_nu", 51);
2541 declare_register ("y0_nu", 52);
2542 declare_register ("y1_nu", 53);
2543 declare_register ("y2_nu", 54);
2544 declare_register ("y3_nu", 55);
2546 declare_register ("mlo", 57);
2547 declare_register ("mmid", 58);
2548 declare_register ("mhi", 59);
2550 declare_register ("acc1", 56);
2551 declare_register ("acc2", 57);
2553 declare_register ("lp_count", 60);
2554 declare_register ("pcl", 63);
2556 /* Initialize the last instructions. */
2557 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2559 /* Aux register declaration. */
2560 arc_aux_hash
= hash_new ();
2561 if (arc_aux_hash
== NULL
)
2562 as_fatal (_("Virtual memory exhausted"));
2564 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2566 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2570 if (!(auxr
->cpu
& selected_cpu
.flags
))
2573 if ((auxr
->subclass
!= NONE
)
2574 && !check_cpu_feature (auxr
->subclass
))
2577 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2579 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2580 auxr
->name
, retval
);
2583 /* Address type declaration. */
2584 arc_addrtype_hash
= hash_new ();
2585 if (arc_addrtype_hash
== NULL
)
2586 as_fatal (_("Virtual memory exhausted"));
2588 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2589 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2590 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2591 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2592 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2593 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2594 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2595 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2596 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2597 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2598 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2599 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2600 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2601 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2602 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2603 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2606 /* Write a value out to the object file, using the appropriate
2610 md_number_to_chars (char *buf
,
2614 if (target_big_endian
)
2615 number_to_chars_bigendian (buf
, val
, n
);
2617 number_to_chars_littleendian (buf
, val
, n
);
2620 /* Round up a section size to the appropriate boundary. */
2623 md_section_align (segT segment
,
2626 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2628 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2631 /* The location from which a PC relative jump should be calculated,
2632 given a PC relative reloc. */
2635 md_pcrel_from_section (fixS
*fixP
,
2638 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2640 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2642 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2643 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2644 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2646 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2648 /* The symbol is undefined (or is defined but not in this section).
2649 Let the linker figure it out. */
2653 if ((int) fixP
->fx_r_type
< 0)
2655 /* These are the "internal" relocations. Align them to
2656 32 bit boundary (PCL), for the moment. */
2661 switch (fixP
->fx_r_type
)
2663 case BFD_RELOC_ARC_PC32
:
2664 /* The hardware calculates relative to the start of the
2665 insn, but this relocation is relative to location of the
2666 LIMM, compensate. The base always needs to be
2667 subtracted by 4 as we do not support this type of PCrel
2668 relocation for short instructions. */
2671 case BFD_RELOC_ARC_PLT32
:
2672 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2673 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2674 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2675 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2677 case BFD_RELOC_ARC_S21H_PCREL
:
2678 case BFD_RELOC_ARC_S25H_PCREL
:
2679 case BFD_RELOC_ARC_S13_PCREL
:
2680 case BFD_RELOC_ARC_S21W_PCREL
:
2681 case BFD_RELOC_ARC_S25W_PCREL
:
2685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2686 _("unhandled reloc %s in md_pcrel_from_section"),
2687 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2692 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2693 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2694 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2695 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2696 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2701 /* Given a BFD relocation find the coresponding operand. */
2703 static const struct arc_operand
*
2704 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2708 for (i
= 0; i
< arc_num_operands
; i
++)
2709 if (arc_operands
[i
].default_reloc
== reloc
)
2710 return &arc_operands
[i
];
2714 /* Insert an operand value into an instruction. */
2716 static unsigned long long
2717 insert_operand (unsigned long long insn
,
2718 const struct arc_operand
*operand
,
2723 offsetT min
= 0, max
= 0;
2725 if (operand
->bits
!= 32
2726 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2727 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2729 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2731 max
= (1 << (operand
->bits
- 1)) - 1;
2732 min
= -(1 << (operand
->bits
- 1));
2736 max
= (1 << operand
->bits
) - 1;
2740 if (val
< min
|| val
> max
)
2741 as_bad_value_out_of_range (_("operand"),
2742 val
, min
, max
, file
, line
);
2745 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08llx\n",
2746 min
, val
, max
, insn
);
2748 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2750 as_bad_where (file
, line
,
2751 _("Unaligned operand. Needs to be 32bit aligned"));
2753 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2755 as_bad_where (file
, line
,
2756 _("Unaligned operand. Needs to be 16bit aligned"));
2758 if (operand
->insert
)
2760 const char *errmsg
= NULL
;
2762 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2764 as_warn_where (file
, line
, "%s", errmsg
);
2768 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2770 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2772 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2775 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2780 /* Apply a fixup to the object code. At this point all symbol values
2781 should be fully resolved, and we attempt to completely resolve the
2782 reloc. If we can not do that, we determine the correct reloc code
2783 and put it back in the fixup. To indicate that a fixup has been
2784 eliminated, set fixP->fx_done. */
2787 md_apply_fix (fixS
*fixP
,
2791 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2792 valueT value
= *valP
;
2794 symbolS
*fx_addsy
, *fx_subsy
;
2796 segT add_symbol_segment
= absolute_section
;
2797 segT sub_symbol_segment
= absolute_section
;
2798 const struct arc_operand
*operand
= NULL
;
2799 extended_bfd_reloc_code_real_type reloc
;
2801 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2802 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2803 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2804 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2807 fx_addsy
= fixP
->fx_addsy
;
2808 fx_subsy
= fixP
->fx_subsy
;
2813 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2817 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2818 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2819 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2821 resolve_symbol_value (fx_subsy
);
2822 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2824 if (sub_symbol_segment
== absolute_section
)
2826 /* The symbol is really a constant. */
2827 fx_offset
-= S_GET_VALUE (fx_subsy
);
2832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2833 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2834 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2835 segment_name (add_symbol_segment
),
2836 S_GET_NAME (fx_subsy
),
2837 segment_name (sub_symbol_segment
));
2843 && !S_IS_WEAK (fx_addsy
))
2845 if (add_symbol_segment
== seg
2848 value
+= S_GET_VALUE (fx_addsy
);
2849 value
-= md_pcrel_from_section (fixP
, seg
);
2851 fixP
->fx_pcrel
= FALSE
;
2853 else if (add_symbol_segment
== absolute_section
)
2855 value
= fixP
->fx_offset
;
2856 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2858 fixP
->fx_pcrel
= FALSE
;
2863 fixP
->fx_done
= TRUE
;
2868 && ((S_IS_DEFINED (fx_addsy
)
2869 && S_GET_SEGMENT (fx_addsy
) != seg
)
2870 || S_IS_WEAK (fx_addsy
)))
2871 value
+= md_pcrel_from_section (fixP
, seg
);
2873 switch (fixP
->fx_r_type
)
2875 case BFD_RELOC_ARC_32_ME
:
2876 /* This is a pc-relative value in a LIMM. Adjust it to the
2877 address of the instruction not to the address of the
2878 LIMM. Note: it is not anylonger valid this afirmation as
2879 the linker consider ARC_PC32 a fixup to entire 64 bit
2881 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2884 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2886 case BFD_RELOC_ARC_PC32
:
2887 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2890 if ((int) fixP
->fx_r_type
< 0)
2891 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2897 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2898 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2899 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2900 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2904 /* Now check for TLS relocations. */
2905 reloc
= fixP
->fx_r_type
;
2908 case BFD_RELOC_ARC_TLS_DTPOFF
:
2909 case BFD_RELOC_ARC_TLS_LE_32
:
2913 case BFD_RELOC_ARC_TLS_GD_GOT
:
2914 case BFD_RELOC_ARC_TLS_IE_GOT
:
2915 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2918 case BFD_RELOC_ARC_TLS_GD_LD
:
2919 gas_assert (!fixP
->fx_offset
);
2922 = (S_GET_VALUE (fixP
->fx_subsy
)
2923 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2924 fixP
->fx_subsy
= NULL
;
2926 case BFD_RELOC_ARC_TLS_GD_CALL
:
2927 /* These two relocs are there just to allow ld to change the tls
2928 model for this symbol, by patching the code. The offset -
2929 and scale, if any - will be installed by the linker. */
2930 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2933 case BFD_RELOC_ARC_TLS_LE_S9
:
2934 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2935 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2947 /* Addjust the value if we have a constant. */
2950 /* For hosts with longs bigger than 32-bits make sure that the top
2951 bits of a 32-bit negative value read in by the parser are set,
2952 so that the correct comparisons are made. */
2953 if (value
& 0x80000000)
2954 value
|= (-1UL << 31);
2956 reloc
= fixP
->fx_r_type
;
2964 case BFD_RELOC_ARC_32_PCREL
:
2965 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2968 case BFD_RELOC_ARC_GOTPC32
:
2969 /* I cannot fix an GOTPC relocation because I need to relax it
2970 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2971 as_bad (_("Unsupported operation on reloc"));
2974 case BFD_RELOC_ARC_TLS_DTPOFF
:
2975 case BFD_RELOC_ARC_TLS_LE_32
:
2976 gas_assert (!fixP
->fx_addsy
);
2977 gas_assert (!fixP
->fx_subsy
);
2980 case BFD_RELOC_ARC_GOTOFF
:
2981 case BFD_RELOC_ARC_32_ME
:
2982 case BFD_RELOC_ARC_PC32
:
2983 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2986 case BFD_RELOC_ARC_PLT32
:
2987 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2990 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2991 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2994 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2995 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2998 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2999 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3002 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3003 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3006 case BFD_RELOC_ARC_S25W_PCREL
:
3007 case BFD_RELOC_ARC_S21W_PCREL
:
3008 case BFD_RELOC_ARC_S21H_PCREL
:
3009 case BFD_RELOC_ARC_S25H_PCREL
:
3010 case BFD_RELOC_ARC_S13_PCREL
:
3012 operand
= find_operand_for_reloc (reloc
);
3013 gas_assert (operand
);
3018 if ((int) fixP
->fx_r_type
>= 0)
3019 as_fatal (_("unhandled relocation type %s"),
3020 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3022 /* The rest of these fixups needs to be completely resolved as
3024 if (fixP
->fx_addsy
!= 0
3025 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3027 _("non-absolute expression in constant field"));
3029 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3030 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3035 if (target_big_endian
)
3037 switch (fixP
->fx_size
)
3040 insn
= bfd_getb32 (fixpos
);
3043 insn
= bfd_getb16 (fixpos
);
3046 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3047 _("unknown fixup size"));
3053 switch (fixP
->fx_size
)
3056 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3059 insn
= bfd_getl16 (fixpos
);
3062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3063 _("unknown fixup size"));
3067 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3068 fixP
->fx_file
, fixP
->fx_line
);
3070 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3073 /* Prepare machine-dependent frags for relaxation.
3075 Called just before relaxation starts. Any symbol that is now undefined
3076 will not become defined.
3078 Return the correct fr_subtype in the frag.
3080 Return the initial "guess for fr_var" to caller. The guess for fr_var
3081 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3082 or fr_var contributes to our returned value.
3084 Although it may not be explicit in the frag, pretend
3085 fr_var starts with a value. */
3088 md_estimate_size_before_relax (fragS
*fragP
,
3093 /* If the symbol is not located within the same section AND it's not
3094 an absolute section, use the maximum. OR if the symbol is a
3095 constant AND the insn is by nature not pc-rel, use the maximum.
3096 OR if the symbol is being equated against another symbol, use the
3097 maximum. OR if the symbol is weak use the maximum. */
3098 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3099 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3100 || (symbol_constant_p (fragP
->fr_symbol
)
3101 && !fragP
->tc_frag_data
.pcrel
)
3102 || symbol_equated_p (fragP
->fr_symbol
)
3103 || S_IS_WEAK (fragP
->fr_symbol
))
3105 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3106 ++fragP
->fr_subtype
;
3109 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3110 fragP
->fr_var
= growth
;
3112 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3113 fragP
->fr_file
, fragP
->fr_line
, growth
);
3118 /* Translate internal representation of relocation info to BFD target
3122 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3126 bfd_reloc_code_real_type code
;
3128 reloc
= XNEW (arelent
);
3129 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3130 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3131 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3133 /* Make sure none of our internal relocations make it this far.
3134 They'd better have been fully resolved by this point. */
3135 gas_assert ((int) fixP
->fx_r_type
> 0);
3137 code
= fixP
->fx_r_type
;
3139 /* if we have something like add gp, pcl,
3140 _GLOBAL_OFFSET_TABLE_@gotpc. */
3141 if (code
== BFD_RELOC_ARC_GOTPC32
3143 && fixP
->fx_addsy
== GOT_symbol
)
3144 code
= BFD_RELOC_ARC_GOTPC
;
3146 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3147 if (reloc
->howto
== NULL
)
3149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3150 _("cannot represent `%s' relocation in object file"),
3151 bfd_get_reloc_code_name (code
));
3155 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3156 as_fatal (_("internal error? cannot generate `%s' relocation"),
3157 bfd_get_reloc_code_name (code
));
3159 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3161 reloc
->addend
= fixP
->fx_offset
;
3166 /* Perform post-processing of machine-dependent frags after relaxation.
3167 Called after relaxation is finished.
3168 In: Address of frag.
3169 fr_type == rs_machine_dependent.
3170 fr_subtype is what the address relaxed to.
3172 Out: Any fixS:s and constants are set up. */
3175 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3176 segT segment ATTRIBUTE_UNUSED
,
3179 const relax_typeS
*table_entry
;
3181 const struct arc_opcode
*opcode
;
3182 struct arc_insn insn
;
3184 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3186 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3187 dest
= fragP
->fr_literal
+ fix
;
3188 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3190 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3191 "var: %"BFD_VMA_FMT
"d\n",
3192 fragP
->fr_file
, fragP
->fr_line
,
3193 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3195 if (fragP
->fr_subtype
<= 0
3196 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3197 as_fatal (_("no relaxation found for this instruction."));
3199 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3201 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3202 relax_arg
->nflg
, &insn
);
3204 apply_fixups (&insn
, fragP
, fix
);
3206 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3207 gas_assert (table_entry
->rlx_length
== size
);
3208 emit_insn0 (&insn
, dest
, TRUE
);
3210 fragP
->fr_fix
+= table_entry
->rlx_length
;
3214 /* We have no need to default values of symbols. We could catch
3215 register names here, but that is handled by inserting them all in
3216 the symbol table to begin with. */
3219 md_undefined_symbol (char *name
)
3221 /* The arc abi demands that a GOT[0] should be referencible as
3222 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3223 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3225 && (*(name
+1) == 'G')
3226 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3228 && (*(name
+1) == 'D')
3229 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3233 if (symbol_find (name
))
3234 as_bad ("GOT already in symbol table");
3236 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3237 (valueT
) 0, &zero_address_frag
);
3244 /* Turn a string in input_line_pointer into a floating point constant
3245 of type type, and store the appropriate bytes in *litP. The number
3246 of LITTLENUMS emitted is stored in *sizeP. An error message is
3247 returned, or NULL on OK. */
3250 md_atof (int type
, char *litP
, int *sizeP
)
3252 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3255 /* Called for any expression that can not be recognized. When the
3256 function is called, `input_line_pointer' will point to the start of
3260 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3262 char *p
= input_line_pointer
;
3265 input_line_pointer
++;
3266 expressionP
->X_op
= O_symbol
;
3267 expression (expressionP
);
3271 /* This function is called from the function 'expression', it attempts
3272 to parse special names (in our case register names). It fills in
3273 the expression with the identified register. It returns TRUE if
3274 it is a register and FALSE otherwise. */
3277 arc_parse_name (const char *name
,
3278 struct expressionS
*e
)
3282 if (!assembling_insn
)
3285 if (e
->X_op
== O_symbol
)
3288 sym
= hash_find (arc_reg_hash
, name
);
3291 e
->X_op
= O_register
;
3292 e
->X_add_number
= S_GET_VALUE (sym
);
3296 sym
= hash_find (arc_addrtype_hash
, name
);
3299 e
->X_op
= O_addrtype
;
3300 e
->X_add_number
= S_GET_VALUE (sym
);
3308 Invocation line includes a switch not recognized by the base assembler.
3309 See if it's a processor-specific option.
3311 New options (supported) are:
3313 -mcpu=<cpu name> Assemble for selected processor
3314 -EB/-mbig-endian Big-endian
3315 -EL/-mlittle-endian Little-endian
3316 -mrelax Enable relaxation
3318 The following CPU names are recognized:
3319 arc600, arc700, arcem, archs, nps400. */
3322 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3328 return md_parse_option (OPTION_MCPU
, "arc600");
3331 return md_parse_option (OPTION_MCPU
, "arc700");
3334 return md_parse_option (OPTION_MCPU
, "arcem");
3337 return md_parse_option (OPTION_MCPU
, "archs");
3341 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3346 arc_target_format
= "elf32-bigarc";
3347 byte_order
= BIG_ENDIAN
;
3351 arc_target_format
= "elf32-littlearc";
3352 byte_order
= LITTLE_ENDIAN
;
3356 selected_cpu
.features
|= ARC_CD
;
3357 arc_check_feature ();
3361 relaxation_state
= 1;
3365 selected_cpu
.features
|= ARC_NPS400
;
3366 arc_check_feature ();
3370 selected_cpu
.features
|= ARC_SPFP
;
3371 arc_check_feature ();
3375 selected_cpu
.features
|= ARC_DPFP
;
3376 arc_check_feature ();
3380 selected_cpu
.features
|= ARC_FPUDA
;
3381 arc_check_feature ();
3384 /* Dummy options are accepted but have no effect. */
3385 case OPTION_USER_MODE
:
3386 case OPTION_LD_EXT_MASK
:
3389 case OPTION_BARREL_SHIFT
:
3390 case OPTION_MIN_MAX
:
3395 case OPTION_XMAC_D16
:
3396 case OPTION_XMAC_24
:
3397 case OPTION_DSP_PACKA
:
3400 case OPTION_TELEPHONY
:
3401 case OPTION_XYMEMORY
:
3415 md_show_usage (FILE *stream
)
3417 fprintf (stream
, _("ARC-specific assembler options:\n"));
3419 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
3420 "(default: %s)\n", TARGET_WITH_CPU
);
3421 fprintf (stream
, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
3422 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3423 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3424 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3425 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3427 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3428 fprintf (stream
, " -mspfp\t\t enable single-precision floating point instructions\n");
3429 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point instructions\n");
3430 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3431 "point\n\t\t\t instructions for ARC EM\n");
3434 " -mcode-density\t enable code density option for ARC EM\n");
3436 fprintf (stream
, _("\
3437 -EB assemble code for a big-endian cpu\n"));
3438 fprintf (stream
, _("\
3439 -EL assemble code for a little-endian cpu\n"));
3440 fprintf (stream
, _("\
3441 -mrelax enable relaxation\n"));
3443 fprintf (stream
, _("The following ARC-specific assembler options are "
3444 "deprecated and are accepted\nfor compatibility only:\n"));
3446 fprintf (stream
, _(" -mEA\n"
3447 " -mbarrel-shifter\n"
3448 " -mbarrel_shifter\n"
3453 " -mld-extension-reg-mask\n"
3469 " -muser-mode-only\n"
3473 /* Find the proper relocation for the given opcode. */
3475 static extended_bfd_reloc_code_real_type
3476 find_reloc (const char *name
,
3477 const char *opcodename
,
3478 const struct arc_flags
*pflags
,
3480 extended_bfd_reloc_code_real_type reloc
)
3484 bfd_boolean found_flag
, tmp
;
3485 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3487 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3489 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3491 /* Find the entry. */
3492 if (strcmp (name
, r
->name
))
3494 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3501 unsigned * psflg
= (unsigned *)r
->flags
;
3505 for (j
= 0; j
< nflg
; j
++)
3506 if (!strcmp (pflags
[j
].name
,
3507 arc_flag_operands
[*psflg
].name
))
3528 if (reloc
!= r
->oldreloc
)
3535 if (ret
== BFD_RELOC_UNUSED
)
3536 as_bad (_("Unable to find %s relocation for instruction %s"),
3541 /* All the symbol types that are allowed to be used for
3545 may_relax_expr (expressionS tok
)
3547 /* Check if we have unrelaxable relocs. */
3572 /* Checks if flags are in line with relaxable insn. */
3575 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3576 const struct arc_flags
*pflags
,
3579 unsigned flag_class
,
3584 const struct arc_flag_operand
*flag_opand
;
3585 int i
, counttrue
= 0;
3587 /* Iterate through flags classes. */
3588 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3590 /* Iterate through flags in flag class. */
3591 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3594 flag_opand
= &arc_flag_operands
[flag
];
3595 /* Iterate through flags in ins to compare. */
3596 for (i
= 0; i
< nflgs
; ++i
)
3598 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3609 /* If counttrue == nflgs, then all flags have been found. */
3610 return (counttrue
== nflgs
? TRUE
: FALSE
);
3613 /* Checks if operands are in line with relaxable insn. */
3616 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3617 const expressionS
*tok
,
3620 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3623 while (*operand
!= EMPTY
)
3625 const expressionS
*epr
= &tok
[i
];
3627 if (i
!= 0 && i
>= ntok
)
3633 if (!(epr
->X_op
== O_multiply
3634 || epr
->X_op
== O_divide
3635 || epr
->X_op
== O_modulus
3636 || epr
->X_op
== O_add
3637 || epr
->X_op
== O_subtract
3638 || epr
->X_op
== O_symbol
))
3644 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3648 if (epr
->X_op
!= O_register
)
3653 if (epr
->X_op
!= O_register
)
3656 switch (epr
->X_add_number
)
3658 case 0: case 1: case 2: case 3:
3659 case 12: case 13: case 14: case 15:
3666 case REGISTER_NO_GP
:
3667 if ((epr
->X_op
!= O_register
)
3668 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3673 if (epr
->X_op
!= O_bracket
)
3678 /* Don't understand, bail out. */
3684 operand
= &ins
->operands
[i
];
3687 return (i
== ntok
? TRUE
: FALSE
);
3690 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3693 relax_insn_p (const struct arc_opcode
*opcode
,
3694 const expressionS
*tok
,
3696 const struct arc_flags
*pflags
,
3700 bfd_boolean rv
= FALSE
;
3702 /* Check the relaxation table. */
3703 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3705 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3707 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3708 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3709 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3710 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3713 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3714 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3715 sizeof (expressionS
) * ntok
);
3716 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3717 sizeof (struct arc_flags
) * nflg
);
3718 frag_now
->tc_frag_data
.nflg
= nflg
;
3719 frag_now
->tc_frag_data
.ntok
= ntok
;
3727 /* Turn an opcode description and a set of arguments into
3728 an instruction and a fixup. */
3731 assemble_insn (const struct arc_opcode
*opcode
,
3732 const expressionS
*tok
,
3734 const struct arc_flags
*pflags
,
3736 struct arc_insn
*insn
)
3738 const expressionS
*reloc_exp
= NULL
;
3739 unsigned long long image
;
3740 const unsigned char *argidx
;
3743 unsigned char pcrel
= 0;
3744 bfd_boolean needGOTSymbol
;
3745 bfd_boolean has_delay_slot
= FALSE
;
3746 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3748 memset (insn
, 0, sizeof (*insn
));
3749 image
= opcode
->opcode
;
3751 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3752 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3755 /* Handle operands. */
3756 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3758 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3759 const expressionS
*t
= (const expressionS
*) 0;
3761 if (ARC_OPERAND_IS_FAKE (operand
))
3764 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3766 /* Duplicate operand, already inserted. */
3778 /* Regardless if we have a reloc or not mark the instruction
3779 limm if it is the case. */
3780 if (operand
->flags
& ARC_OPERAND_LIMM
)
3781 insn
->has_limm
= TRUE
;
3786 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3791 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3793 if (operand
->flags
& ARC_OPERAND_LIMM
)
3794 insn
->limm
= t
->X_add_number
;
3800 /* Ignore brackets, colons, and address types. */
3804 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3808 /* Maybe register range. */
3809 if ((t
->X_add_number
== 0)
3810 && contains_register (t
->X_add_symbol
)
3811 && contains_register (t
->X_op_symbol
))
3815 regs
= get_register (t
->X_add_symbol
);
3817 regs
|= get_register (t
->X_op_symbol
);
3818 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3824 /* This operand needs a relocation. */
3825 needGOTSymbol
= FALSE
;
3830 if (opcode
->insn_class
== JUMP
)
3831 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3832 _("Unable to use @plt relocatio for insn %s"),
3834 needGOTSymbol
= TRUE
;
3835 reloc
= find_reloc ("plt", opcode
->name
,
3837 operand
->default_reloc
);
3842 needGOTSymbol
= TRUE
;
3843 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3846 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3847 if (arc_opcode_len (opcode
) == 2
3848 || opcode
->insn_class
== JUMP
)
3849 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3850 _("Unable to use @pcl relocation for insn %s"),
3854 reloc
= find_reloc ("sda", opcode
->name
,
3856 operand
->default_reloc
);
3860 needGOTSymbol
= TRUE
;
3865 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3868 case O_tpoff9
: /*FIXME! Check for the conditionality of
3870 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3872 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3876 /* Just consider the default relocation. */
3877 reloc
= operand
->default_reloc
;
3881 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3882 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3889 /* sanity checks. */
3890 reloc_howto_type
*reloc_howto
3891 = bfd_reloc_type_lookup (stdoutput
,
3892 (bfd_reloc_code_real_type
) reloc
);
3893 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3894 if (reloc_howto
->rightshift
)
3895 reloc_bitsize
-= reloc_howto
->rightshift
;
3896 if (reloc_bitsize
!= operand
->bits
)
3898 as_bad (_("invalid relocation %s for field"),
3899 bfd_get_reloc_code_name (reloc
));
3904 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3905 as_fatal (_("too many fixups"));
3907 struct arc_fixup
*fixup
;
3908 fixup
= &insn
->fixups
[insn
->nfixups
++];
3910 fixup
->reloc
= reloc
;
3911 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3912 fixup
->pcrel
= pcrel
;
3913 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3920 for (i
= 0; i
< nflg
; i
++)
3922 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3924 /* Check if the instruction has a delay slot. */
3925 if (!strcmp (flg_operand
->name
, "d"))
3926 has_delay_slot
= TRUE
;
3928 /* There is an exceptional case when we cannot insert a flag
3929 just as it is. The .T flag must be handled in relation with
3930 the relative address. */
3931 if (!strcmp (flg_operand
->name
, "t")
3932 || !strcmp (flg_operand
->name
, "nt"))
3934 unsigned bitYoperand
= 0;
3935 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3936 if (!strcmp (flg_operand
->name
, "t"))
3937 if (!strcmp (opcode
->name
, "bbit0")
3938 || !strcmp (opcode
->name
, "bbit1"))
3939 bitYoperand
= arc_NToperand
;
3941 bitYoperand
= arc_Toperand
;
3943 if (!strcmp (opcode
->name
, "bbit0")
3944 || !strcmp (opcode
->name
, "bbit1"))
3945 bitYoperand
= arc_Toperand
;
3947 bitYoperand
= arc_NToperand
;
3949 gas_assert (reloc_exp
!= NULL
);
3950 if (reloc_exp
->X_op
== O_constant
)
3952 /* Check if we have a constant and solved it
3954 offsetT val
= reloc_exp
->X_add_number
;
3955 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3960 struct arc_fixup
*fixup
;
3962 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3963 as_fatal (_("too many fixups"));
3965 fixup
= &insn
->fixups
[insn
->nfixups
++];
3966 fixup
->exp
= *reloc_exp
;
3967 fixup
->reloc
= -bitYoperand
;
3968 fixup
->pcrel
= pcrel
;
3969 fixup
->islong
= FALSE
;
3973 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3974 << flg_operand
->shift
;
3977 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3979 /* Instruction length. */
3980 insn
->len
= arc_opcode_len (opcode
);
3984 /* Update last insn status. */
3985 arc_last_insns
[1] = arc_last_insns
[0];
3986 arc_last_insns
[0].opcode
= opcode
;
3987 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3988 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3990 /* Check if the current instruction is legally used. */
3991 if (arc_last_insns
[1].has_delay_slot
3992 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3993 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3994 _("A jump/branch instruction in delay slot."));
3998 arc_handle_align (fragS
* fragP
)
4000 if ((fragP
)->fr_type
== rs_align_code
)
4002 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4003 valueT count
= ((fragP
)->fr_next
->fr_address
4004 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4006 (fragP
)->fr_var
= 2;
4008 if (count
& 1)/* Padding in the gap till the next 2-byte
4009 boundary with 0s. */
4014 /* Writing nop_s. */
4015 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4019 /* Here we decide which fixups can be adjusted to make them relative
4020 to the beginning of the section instead of the symbol. Basically
4021 we need to make sure that the dynamic relocations are done
4022 correctly, so in some cases we force the original symbol to be
4026 tc_arc_fix_adjustable (fixS
*fixP
)
4029 /* Prevent all adjustments to global symbols. */
4030 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4032 if (S_IS_WEAK (fixP
->fx_addsy
))
4035 /* Adjust_reloc_syms doesn't know about the GOT. */
4036 switch (fixP
->fx_r_type
)
4038 case BFD_RELOC_ARC_GOTPC32
:
4039 case BFD_RELOC_ARC_PLT32
:
4040 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4041 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4042 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4043 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4053 /* Compute the reloc type of an expression EXP. */
4056 arc_check_reloc (expressionS
*exp
,
4057 bfd_reloc_code_real_type
*r_type_p
)
4059 if (*r_type_p
== BFD_RELOC_32
4060 && exp
->X_op
== O_subtract
4061 && exp
->X_op_symbol
!= NULL
4062 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4063 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4067 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4070 arc_cons_fix_new (fragS
*frag
,
4074 bfd_reloc_code_real_type r_type
)
4076 r_type
= BFD_RELOC_UNUSED
;
4081 r_type
= BFD_RELOC_8
;
4085 r_type
= BFD_RELOC_16
;
4089 r_type
= BFD_RELOC_24
;
4093 r_type
= BFD_RELOC_32
;
4094 arc_check_reloc (exp
, &r_type
);
4098 r_type
= BFD_RELOC_64
;
4102 as_bad (_("unsupported BFD relocation size %u"), size
);
4103 r_type
= BFD_RELOC_UNUSED
;
4106 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4109 /* The actual routine that checks the ZOL conditions. */
4112 check_zol (symbolS
*s
)
4114 switch (selected_cpu
.mach
)
4116 case bfd_mach_arc_arcv2
:
4117 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4120 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4121 || arc_last_insns
[1].has_delay_slot
)
4122 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4126 case bfd_mach_arc_arc600
:
4128 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4129 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4132 if (arc_last_insns
[0].has_limm
4133 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4134 as_bad (_("A jump instruction with long immediate detected at the \
4135 end of the ZOL label @%s"), S_GET_NAME (s
));
4138 case bfd_mach_arc_arc700
:
4139 if (arc_last_insns
[0].has_delay_slot
)
4140 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4149 /* If ZOL end check the last two instruction for illegals. */
4151 arc_frob_label (symbolS
* sym
)
4153 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4156 dwarf2_emit_label (sym
);
4159 /* Used because generic relaxation assumes a pc-rel value whilst we
4160 also relax instructions that use an absolute value resolved out of
4161 relative values (if that makes any sense). An example: 'add r1,
4162 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4163 but if they're in the same section we can subtract the section
4164 offset relocation which ends up in a resolved value. So if @.L2 is
4165 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4166 .text + 0x40 = 0x10. */
4168 arc_pcrel_adjust (fragS
*fragP
)
4170 if (!fragP
->tc_frag_data
.pcrel
)
4171 return fragP
->fr_address
+ fragP
->fr_fix
;
4176 /* Initialize the DWARF-2 unwind information for this procedure. */
4179 tc_arc_frame_initial_instructions (void)
4181 /* Stack pointer is register 28. */
4182 cfi_add_CFA_def_cfa (28, 0);
4186 tc_arc_regname_to_dw2regnum (char *regname
)
4190 sym
= hash_find (arc_reg_hash
, regname
);
4192 return S_GET_VALUE (sym
);
4197 /* Adjust the symbol table. Delete found AUX register symbols. */
4200 arc_adjust_symtab (void)
4204 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4206 /* I've created a symbol during parsing process. Now, remove
4207 the symbol as it is found to be an AUX register. */
4208 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4209 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4212 /* Now do generic ELF adjustments. */
4213 elf_adjust_symtab ();
4217 tokenize_extinsn (extInstruction_t
*einsn
)
4221 unsigned char major_opcode
;
4222 unsigned char sub_opcode
;
4223 unsigned char syntax_class
= 0;
4224 unsigned char syntax_class_modifiers
= 0;
4225 unsigned char suffix_class
= 0;
4230 /* 1st: get instruction name. */
4231 p
= input_line_pointer
;
4232 c
= get_symbol_name (&p
);
4234 insn_name
= xstrdup (p
);
4235 restore_line_pointer (c
);
4237 /* 2nd: get major opcode. */
4238 if (*input_line_pointer
!= ',')
4240 as_bad (_("expected comma after instruction name"));
4241 ignore_rest_of_line ();
4244 input_line_pointer
++;
4245 major_opcode
= get_absolute_expression ();
4247 /* 3rd: get sub-opcode. */
4250 if (*input_line_pointer
!= ',')
4252 as_bad (_("expected comma after major opcode"));
4253 ignore_rest_of_line ();
4256 input_line_pointer
++;
4257 sub_opcode
= get_absolute_expression ();
4259 /* 4th: get suffix class. */
4262 if (*input_line_pointer
!= ',')
4264 as_bad ("expected comma after sub opcode");
4265 ignore_rest_of_line ();
4268 input_line_pointer
++;
4274 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4276 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4277 suffixclass
[i
].len
))
4279 suffix_class
|= suffixclass
[i
].attr_class
;
4280 input_line_pointer
+= suffixclass
[i
].len
;
4285 if (i
== ARRAY_SIZE (suffixclass
))
4287 as_bad ("invalid suffix class");
4288 ignore_rest_of_line ();
4294 if (*input_line_pointer
== '|')
4295 input_line_pointer
++;
4300 /* 5th: get syntax class and syntax class modifiers. */
4301 if (*input_line_pointer
!= ',')
4303 as_bad ("expected comma after suffix class");
4304 ignore_rest_of_line ();
4307 input_line_pointer
++;
4313 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4315 if (!strncmp (syntaxclassmod
[i
].name
,
4317 syntaxclassmod
[i
].len
))
4319 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4320 input_line_pointer
+= syntaxclassmod
[i
].len
;
4325 if (i
== ARRAY_SIZE (syntaxclassmod
))
4327 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4329 if (!strncmp (syntaxclass
[i
].name
,
4331 syntaxclass
[i
].len
))
4333 syntax_class
|= syntaxclass
[i
].attr_class
;
4334 input_line_pointer
+= syntaxclass
[i
].len
;
4339 if (i
== ARRAY_SIZE (syntaxclass
))
4341 as_bad ("missing syntax class");
4342 ignore_rest_of_line ();
4349 if (*input_line_pointer
== '|')
4350 input_line_pointer
++;
4355 demand_empty_rest_of_line ();
4357 einsn
->name
= insn_name
;
4358 einsn
->major
= major_opcode
;
4359 einsn
->minor
= sub_opcode
;
4360 einsn
->syntax
= syntax_class
;
4361 einsn
->modsyn
= syntax_class_modifiers
;
4362 einsn
->suffix
= suffix_class
;
4363 einsn
->flags
= syntax_class
4364 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4367 /* Generate an extension section. */
4370 arc_set_ext_seg (void)
4372 if (!arcext_section
)
4374 arcext_section
= subseg_new (".arcextmap", 0);
4375 bfd_set_section_flags (stdoutput
, arcext_section
,
4376 SEC_READONLY
| SEC_HAS_CONTENTS
);
4379 subseg_set (arcext_section
, 0);
4383 /* Create an extension instruction description in the arc extension
4384 section of the output file.
4385 The structure for an instruction is like this:
4386 [0]: Length of the record.
4387 [1]: Type of the record.
4391 [4]: Syntax (flags).
4392 [5]+ Name instruction.
4394 The sequence is terminated by an empty entry. */
4397 create_extinst_section (extInstruction_t
*einsn
)
4400 segT old_sec
= now_seg
;
4401 int old_subsec
= now_subseg
;
4403 int name_len
= strlen (einsn
->name
);
4408 *p
= 5 + name_len
+ 1;
4410 *p
= EXT_INSTRUCTION
;
4417 p
= frag_more (name_len
+ 1);
4418 strcpy (p
, einsn
->name
);
4420 subseg_set (old_sec
, old_subsec
);
4423 /* Handler .extinstruction pseudo-op. */
4426 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4428 extInstruction_t einsn
;
4429 struct arc_opcode
*arc_ext_opcodes
;
4430 const char *errmsg
= NULL
;
4431 unsigned char moplow
, mophigh
;
4433 memset (&einsn
, 0, sizeof (einsn
));
4434 tokenize_extinsn (&einsn
);
4436 /* Check if the name is already used. */
4437 if (arc_find_opcode (einsn
.name
))
4438 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4440 /* Check the opcode ranges. */
4442 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4443 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4445 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4446 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4448 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4449 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4450 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4452 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4454 case ARC_SYNTAX_3OP
:
4455 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4456 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4458 case ARC_SYNTAX_2OP
:
4459 case ARC_SYNTAX_1OP
:
4460 case ARC_SYNTAX_NOP
:
4461 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4462 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4468 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4469 if (arc_ext_opcodes
== NULL
)
4472 as_fatal ("%s", errmsg
);
4474 as_fatal (_("Couldn't generate extension instruction opcodes"));
4477 as_warn ("%s", errmsg
);
4479 /* Insert the extension instruction. */
4480 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4482 create_extinst_section (&einsn
);
4486 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4492 int number
, imode
= 0;
4493 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4494 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4495 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4497 /* 1st: get register name. */
4499 p
= input_line_pointer
;
4500 c
= get_symbol_name (&p
);
4503 restore_line_pointer (c
);
4505 /* 2nd: get register number. */
4508 if (*input_line_pointer
!= ',')
4510 as_bad (_("expected comma after register name"));
4511 ignore_rest_of_line ();
4515 input_line_pointer
++;
4516 number
= get_absolute_expression ();
4520 as_bad (_("negative operand number %d"), number
);
4521 ignore_rest_of_line ();
4528 /* 3rd: get register mode. */
4531 if (*input_line_pointer
!= ',')
4533 as_bad (_("expected comma after register number"));
4534 ignore_rest_of_line ();
4539 input_line_pointer
++;
4540 mode
= input_line_pointer
;
4542 if (!strncmp (mode
, "r|w", 3))
4545 input_line_pointer
+= 3;
4547 else if (!strncmp (mode
, "r", 1))
4549 imode
= ARC_REGISTER_READONLY
;
4550 input_line_pointer
+= 1;
4552 else if (strncmp (mode
, "w", 1))
4554 as_bad (_("invalid mode"));
4555 ignore_rest_of_line ();
4561 imode
= ARC_REGISTER_WRITEONLY
;
4562 input_line_pointer
+= 1;
4568 /* 4th: get core register shortcut. */
4570 if (*input_line_pointer
!= ',')
4572 as_bad (_("expected comma after register mode"));
4573 ignore_rest_of_line ();
4578 input_line_pointer
++;
4580 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4582 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4583 input_line_pointer
+= 15;
4585 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4587 as_bad (_("shortcut designator invalid"));
4588 ignore_rest_of_line ();
4594 input_line_pointer
+= 12;
4597 demand_empty_rest_of_line ();
4600 ereg
->number
= number
;
4601 ereg
->imode
= imode
;
4604 /* Create an extension register/condition description in the arc
4605 extension section of the output file.
4607 The structure for an instruction is like this:
4608 [0]: Length of the record.
4609 [1]: Type of the record.
4611 For core regs and condition codes:
4615 For auxilirary registers:
4619 The sequence is terminated by an empty entry. */
4622 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4624 segT old_sec
= now_seg
;
4625 int old_subsec
= now_subseg
;
4627 int name_len
= strlen (ereg
->name
);
4634 case EXT_CORE_REGISTER
:
4636 *p
= 3 + name_len
+ 1;
4642 case EXT_AUX_REGISTER
:
4644 *p
= 6 + name_len
+ 1;
4646 *p
= EXT_AUX_REGISTER
;
4648 *p
= (ereg
->number
>> 24) & 0xff;
4650 *p
= (ereg
->number
>> 16) & 0xff;
4652 *p
= (ereg
->number
>> 8) & 0xff;
4654 *p
= (ereg
->number
) & 0xff;
4660 p
= frag_more (name_len
+ 1);
4661 strcpy (p
, ereg
->name
);
4663 subseg_set (old_sec
, old_subsec
);
4666 /* Handler .extCoreRegister pseudo-op. */
4669 arc_extcorereg (int opertype
)
4672 struct arc_aux_reg
*auxr
;
4674 struct arc_flag_operand
*ccode
;
4676 memset (&ereg
, 0, sizeof (ereg
));
4677 tokenize_extregister (&ereg
, opertype
);
4681 case EXT_CORE_REGISTER
:
4682 /* Core register. */
4683 if (ereg
.number
> 60)
4684 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4686 declare_register (ereg
.name
, ereg
.number
);
4688 case EXT_AUX_REGISTER
:
4689 /* Auxiliary register. */
4690 auxr
= XNEW (struct arc_aux_reg
);
4691 auxr
->name
= ereg
.name
;
4692 auxr
->cpu
= selected_cpu
.flags
;
4693 auxr
->subclass
= NONE
;
4694 auxr
->address
= ereg
.number
;
4695 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4697 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4698 auxr
->name
, retval
);
4701 /* Condition code. */
4702 if (ereg
.number
> 31)
4703 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4705 ext_condcode
.size
++;
4706 ext_condcode
.arc_ext_condcode
=
4707 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4708 ext_condcode
.size
+ 1);
4709 if (ext_condcode
.arc_ext_condcode
== NULL
)
4710 as_fatal (_("Virtual memory exhausted"));
4712 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4713 ccode
->name
= ereg
.name
;
4714 ccode
->code
= ereg
.number
;
4717 ccode
->favail
= 0; /* not used. */
4719 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4722 as_bad (_("Unknown extension"));
4725 create_extcore_section (&ereg
, opertype
);
4729 eval: (c-set-style "gnu")