1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 #ifndef TARGET_WITH_CPU
55 #define TARGET_WITH_CPU "arc700"
56 #endif /* TARGET_WITH_CPU */
58 /* Enum used to enumerate the relaxable ins operands. */
63 REGISTER_S
, /* Register for short instruction(s). */
64 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
65 REGISTER_DUP
, /* Duplication of previous operand of type register. */
99 #define regno(x) ((x) & 0x3F)
100 #define is_ir_num(x) (((x) & ~0x3F) == 0)
101 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
102 #define is_spfp_p(op) (((sc) == SPX))
103 #define is_dpfp_p(op) (((sc) == DPX))
104 #define is_fpuda_p(op) (((sc) == DPA))
105 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
106 || (op)->insn_class == JUMP))
107 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
108 #define is_nps400_p(op) (((sc) == NPS400))
110 /* Generic assembler global variables which must be defined by all
113 /* Characters which always start a comment. */
114 const char comment_chars
[] = "#;";
116 /* Characters which start a comment at the beginning of a line. */
117 const char line_comment_chars
[] = "#";
119 /* Characters which may be used to separate multiple commands on a
121 const char line_separator_chars
[] = "`";
123 /* Characters which are used to indicate an exponent in a floating
125 const char EXP_CHARS
[] = "eE";
127 /* Chars that mean this number is a floating point constant
128 As in 0f12.456 or 0d1.2345e12. */
129 const char FLT_CHARS
[] = "rRsSfFdD";
132 extern int target_big_endian
;
133 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
134 static int byte_order
= DEFAULT_BYTE_ORDER
;
136 /* Arc extension section. */
137 static segT arcext_section
;
139 /* By default relaxation is disabled. */
140 static int relaxation_state
= 0;
142 extern int arc_get_mach (char *);
144 /* Forward declarations. */
145 static void arc_lcomm (int);
146 static void arc_option (int);
147 static void arc_extra_reloc (int);
148 static void arc_extinsn (int);
149 static void arc_extcorereg (int);
151 const pseudo_typeS md_pseudo_table
[] =
153 /* Make sure that .word is 32 bits. */
156 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
157 { "lcomm", arc_lcomm
, 0 },
158 { "lcommon", arc_lcomm
, 0 },
159 { "cpu", arc_option
, 0 },
161 { "extinstruction", arc_extinsn
, 0 },
162 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
163 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
164 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
166 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
167 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
172 const char *md_shortopts
= "";
176 OPTION_EB
= OPTION_MD_BASE
,
194 /* The following options are deprecated and provided here only for
195 compatibility reasons. */
218 struct option md_longopts
[] =
220 { "EB", no_argument
, NULL
, OPTION_EB
},
221 { "EL", no_argument
, NULL
, OPTION_EL
},
222 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
223 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
224 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
225 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
226 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
227 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
228 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
229 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
230 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
231 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
232 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
234 /* Floating point options */
235 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
236 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
237 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
238 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
239 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
240 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
241 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
242 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
243 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
244 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
245 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
247 /* The following options are deprecated and provided here only for
248 compatibility reasons. */
249 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
250 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
251 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
252 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
253 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
254 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
255 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
256 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
257 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
258 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
259 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
260 { "mea", no_argument
, NULL
, OPTION_EA
},
261 { "mEA", no_argument
, NULL
, OPTION_EA
},
262 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
263 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
264 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
265 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
266 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
267 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
268 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
269 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
270 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
271 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
272 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
273 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
274 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
275 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
276 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
278 { NULL
, no_argument
, NULL
, 0 }
281 size_t md_longopts_size
= sizeof (md_longopts
);
283 /* Local data and data types. */
285 /* Used since new relocation types are introduced in this
286 file (DUMMY_RELOC_LITUSE_*). */
287 typedef int extended_bfd_reloc_code_real_type
;
293 extended_bfd_reloc_code_real_type reloc
;
295 /* index into arc_operands. */
296 unsigned int opindex
;
298 /* PC-relative, used by internals fixups. */
301 /* TRUE if this fixup is for LIMM operand. */
307 unsigned long long int insn
;
309 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
311 unsigned int len
; /* Length of instruction in bytes. */
312 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
314 bfd_boolean relax
; /* Boolean value: TRUE if needs
318 /* Structure to hold any last two instructions. */
319 static struct arc_last_insn
321 /* Saved instruction opcode. */
322 const struct arc_opcode
*opcode
;
324 /* Boolean value: TRUE if current insn is short. */
325 bfd_boolean has_limm
;
327 /* Boolean value: TRUE if current insn has delay slot. */
328 bfd_boolean has_delay_slot
;
331 /* Extension instruction suffix classes. */
339 static const attributes_t suffixclass
[] =
341 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
342 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
343 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
346 /* Extension instruction syntax classes. */
347 static const attributes_t syntaxclass
[] =
349 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
350 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
351 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
352 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
355 /* Extension instruction syntax classes modifiers. */
356 static const attributes_t syntaxclassmod
[] =
358 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
359 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
362 /* Extension register type. */
370 /* A structure to hold the additional conditional codes. */
373 struct arc_flag_operand
*arc_ext_condcode
;
375 } ext_condcode
= { NULL
, 0 };
377 /* Structure to hold an entry in ARC_OPCODE_HASH. */
378 struct arc_opcode_hash_entry
380 /* The number of pointers in the OPCODE list. */
383 /* Points to a list of opcode pointers. */
384 const struct arc_opcode
**opcode
;
387 /* Structure used for iterating through an arc_opcode_hash_entry. */
388 struct arc_opcode_hash_entry_iterator
390 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
393 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
394 returned by this iterator. */
395 const struct arc_opcode
*opcode
;
398 /* Forward declaration. */
399 static void assemble_insn
400 (const struct arc_opcode
*, const expressionS
*, int,
401 const struct arc_flags
*, int, struct arc_insn
*);
403 /* The selection of the machine type can come from different sources. This
404 enum is used to track how the selection was made in order to perform
406 enum mach_selection_type
409 MACH_SELECTION_FROM_DEFAULT
,
410 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
411 MACH_SELECTION_FROM_COMMAND_LINE
414 /* How the current machine type was selected. */
415 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
417 /* The hash table of instruction opcodes. */
418 static struct hash_control
*arc_opcode_hash
;
420 /* The hash table of register symbols. */
421 static struct hash_control
*arc_reg_hash
;
423 /* The hash table of aux register symbols. */
424 static struct hash_control
*arc_aux_hash
;
426 /* The hash table of address types. */
427 static struct hash_control
*arc_addrtype_hash
;
429 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
430 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
431 E_ARC_MACH_ARC600, EXTRA}
432 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
433 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
434 E_ARC_MACH_ARC700, EXTRA}
435 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
436 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
437 EF_ARC_CPU_ARCV2EM, EXTRA}
438 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
439 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
440 EF_ARC_CPU_ARCV2HS, EXTRA}
442 /* A table of CPU names and opcode sets. */
443 static const struct cpu_type
453 ARC_CPU_TYPE_A7xx (arc700
, 0x00),
454 ARC_CPU_TYPE_A7xx (nps400
, ARC_NPS400
),
456 ARC_CPU_TYPE_AV2EM (arcem
, 0x00),
457 ARC_CPU_TYPE_AV2EM (em
, 0x00),
458 ARC_CPU_TYPE_AV2EM (em4
, ARC_CD
),
459 ARC_CPU_TYPE_AV2EM (em4_dmips
, ARC_CD
),
460 ARC_CPU_TYPE_AV2EM (em4_fpus
, ARC_CD
),
461 ARC_CPU_TYPE_AV2EM (em4_fpuda
, ARC_CD
| ARC_FPUDA
),
462 ARC_CPU_TYPE_AV2EM (quarkse_em
, ARC_CD
| ARC_SPFP
| ARC_DPFP
),
464 ARC_CPU_TYPE_AV2HS (archs
, ARC_CD
),
465 ARC_CPU_TYPE_AV2HS (hs
, ARC_CD
),
466 ARC_CPU_TYPE_AV2HS (hs34
, ARC_CD
),
467 ARC_CPU_TYPE_AV2HS (hs38
, ARC_CD
),
468 ARC_CPU_TYPE_AV2HS (hs38_linux
, ARC_CD
),
470 ARC_CPU_TYPE_A6xx (arc600
, 0x00),
471 ARC_CPU_TYPE_A6xx (arc600_norm
, 0x00),
472 ARC_CPU_TYPE_A6xx (arc600_mul64
, 0x00),
473 ARC_CPU_TYPE_A6xx (arc600_mul32x16
, 0x00),
474 ARC_CPU_TYPE_A6xx (arc601
, 0x00),
475 ARC_CPU_TYPE_A6xx (arc601_norm
, 0x00),
476 ARC_CPU_TYPE_A6xx (arc601_mul64
, 0x00),
477 ARC_CPU_TYPE_A6xx (arc601_mul32x16
, 0x00),
481 /* Information about the cpu/variant we're assembling for. */
482 static struct cpu_type selected_cpu
= { 0, 0, 0, 0, 0 };
484 /* A table with options. */
485 static const struct feature_type
493 { ARC_CD
, ARC_OPCODE_ARCV2
, "code-density" },
494 { ARC_NPS400
, ARC_OPCODE_ARC700
, "nps400" },
495 { ARC_SPFP
, ARC_OPCODE_ARCFPX
, "single-precision FPX" },
496 { ARC_DPFP
, ARC_OPCODE_ARCFPX
, "double-precision FPX" },
497 { ARC_FPUDA
, ARC_OPCODE_ARCv2EM
, "double assist FP" }
500 /* Command line given features. */
501 static unsigned cl_features
= 0;
503 /* Used by the arc_reloc_op table. Order is important. */
504 #define O_gotoff O_md1 /* @gotoff relocation. */
505 #define O_gotpc O_md2 /* @gotpc relocation. */
506 #define O_plt O_md3 /* @plt relocation. */
507 #define O_sda O_md4 /* @sda relocation. */
508 #define O_pcl O_md5 /* @pcl relocation. */
509 #define O_tlsgd O_md6 /* @tlsgd relocation. */
510 #define O_tlsie O_md7 /* @tlsie relocation. */
511 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
512 #define O_tpoff O_md9 /* @tpoff relocation. */
513 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
514 #define O_dtpoff O_md11 /* @dtpoff relocation. */
515 #define O_last O_dtpoff
517 /* Used to define a bracket as operand in tokens. */
518 #define O_bracket O_md32
520 /* Used to define a colon as an operand in tokens. */
521 #define O_colon O_md31
523 /* Used to define address types in nps400. */
524 #define O_addrtype O_md30
526 /* Dummy relocation, to be sorted out. */
527 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
529 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
531 /* A table to map the spelling of a relocation operand into an appropriate
532 bfd_reloc_code_real_type type. The table is assumed to be ordered such
533 that op-O_literal indexes into it. */
534 #define ARC_RELOC_TABLE(op) \
535 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
537 : (int) (op) - (int) O_gotoff) ])
539 #define DEF(NAME, RELOC, REQ) \
540 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
542 static const struct arc_reloc_op_tag
544 /* String to lookup. */
546 /* Size of the string. */
548 /* Which operator to use. */
550 extended_bfd_reloc_code_real_type reloc
;
551 /* Allows complex relocation expression like identifier@reloc +
553 unsigned int complex_expr
: 1;
557 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
558 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
559 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
560 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
561 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
562 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
563 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
564 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
565 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
566 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
567 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
570 static const int arc_num_reloc_op
571 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
573 /* Structure for relaxable instruction that have to be swapped with a
574 smaller alternative instruction. */
575 struct arc_relaxable_ins
577 /* Mnemonic that should be checked. */
578 const char *mnemonic_r
;
580 /* Operands that should be checked.
581 Indexes of operands from operand array. */
582 enum rlx_operand_type operands
[6];
584 /* Flags that should be checked. */
585 unsigned flag_classes
[5];
587 /* Mnemonic (smaller) alternative to be used later for relaxation. */
588 const char *mnemonic_alt
;
590 /* Index of operand that generic relaxation has to check. */
593 /* Base subtype index used. */
594 enum arc_rlx_types subtype
;
597 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
598 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
599 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
603 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
604 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
605 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
610 /* ARC relaxation table. */
611 const relax_typeS md_relax_table
[] =
618 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
619 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
623 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
624 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
629 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
630 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
631 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
633 /* LD_S a, [b, u7] ->
634 LD<zz><.x><.aa><.di> a, [b, s9] ->
635 LD<zz><.x><.aa><.di> a, [b, limm] */
636 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
637 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
638 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
643 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
644 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
645 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
649 SUB<.f> a, b, limm. */
650 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
651 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
652 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
654 /* MPY<.f> a, b, u6 ->
655 MPY<.f> a, b, limm. */
656 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
657 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
659 /* MOV<.f><.cc> b, u6 ->
660 MOV<.f><.cc> b, limm. */
661 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
662 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
664 /* ADD<.f><.cc> b, b, u6 ->
665 ADD<.f><.cc> b, b, limm. */
666 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
667 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
670 /* Order of this table's entries matters! */
671 const struct arc_relaxable_ins arc_relaxable_insns
[] =
673 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
674 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
675 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
676 2, ARC_RLX_ADD_RRU6
},
677 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
679 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
681 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
682 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
683 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
684 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
685 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
686 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
687 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
688 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
690 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
692 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
696 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
698 /* Flags to set in the elf header. */
699 static const flagword arc_initial_eflag
= 0x00;
701 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
702 symbolS
* GOT_symbol
= 0;
704 /* Set to TRUE when we assemble instructions. */
705 static bfd_boolean assembling_insn
= FALSE
;
707 /* Functions implementation. */
709 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
710 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
711 are no matching entries in ARC_OPCODE_HASH. */
713 static const struct arc_opcode_hash_entry
*
714 arc_find_opcode (const char *name
)
716 const struct arc_opcode_hash_entry
*entry
;
718 entry
= hash_find (arc_opcode_hash
, name
);
722 /* Initialise the iterator ITER. */
725 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
731 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
732 calls to this function. Return NULL when all ARC_OPCODE entries have
735 static const struct arc_opcode
*
736 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
737 struct arc_opcode_hash_entry_iterator
*iter
)
739 if (iter
->opcode
== NULL
&& iter
->index
== 0)
741 gas_assert (entry
->count
> 0);
742 iter
->opcode
= entry
->opcode
[iter
->index
];
744 else if (iter
->opcode
!= NULL
)
746 const char *old_name
= iter
->opcode
->name
;
749 if (iter
->opcode
->name
== NULL
750 || strcmp (old_name
, iter
->opcode
->name
) != 0)
753 if (iter
->index
== entry
->count
)
756 iter
->opcode
= entry
->opcode
[iter
->index
];
763 /* Insert an opcode into opcode hash structure. */
766 arc_insert_opcode (const struct arc_opcode
*opcode
)
768 const char *name
, *retval
;
769 struct arc_opcode_hash_entry
*entry
;
772 entry
= hash_find (arc_opcode_hash
, name
);
775 entry
= XNEW (struct arc_opcode_hash_entry
);
777 entry
->opcode
= NULL
;
779 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
781 as_fatal (_("internal error: can't hash opcode '%s': %s"),
785 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
788 if (entry
->opcode
== NULL
)
789 as_fatal (_("Virtual memory exhausted"));
791 entry
->opcode
[entry
->count
] = opcode
;
796 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
797 value, is encoded as 'middle-endian' for a little-endian target. This
798 function is used for regular 4, 6, and 8 byte instructions as well. */
801 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
806 md_number_to_chars (buf
, val
, n
);
809 md_number_to_chars (buf
, (val
& 0xffff00000000) >> 32, 2);
810 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
813 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
814 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
817 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000) >> 32, 4);
818 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
825 /* Check if a feature is allowed for a specific CPU. */
828 arc_check_feature (void)
832 if (!selected_cpu
.features
833 || !selected_cpu
.name
)
835 for (i
= 0; (i
< ARRAY_SIZE (feature_list
)); i
++)
837 if ((selected_cpu
.features
& feature_list
[i
].feature
)
838 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
840 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
846 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
847 the relevant static global variables. Parameter SEL describes where
848 this selection originated from. */
851 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
856 /* We should only set a default if we've not made a selection from some
858 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
859 || mach_selection_mode
== MACH_SELECTION_NONE
);
861 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
862 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
863 as_bad (_("Multiple .cpu directives found"));
865 /* Look for a matching entry in CPU_TYPES array. */
866 for (i
= 0; cpu_types
[i
].name
; ++i
)
868 if (!strcasecmp (cpu_types
[i
].name
, arg
))
870 /* If a previous selection was made on the command line, then we
871 allow later selections on the command line to override earlier
872 ones. However, a selection from a '.cpu NAME' directive must
873 match the command line selection, or we give a warning. */
874 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
876 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
877 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
878 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
879 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
881 as_warn (_("Command-line value overrides \".cpu\" directive"));
886 /* Initialise static global data about selected machine type. */
887 selected_cpu
.flags
= cpu_types
[i
].flags
;
888 selected_cpu
.name
= cpu_types
[i
].name
;
889 selected_cpu
.features
= cpu_types
[i
].features
| cl_features
;
890 selected_cpu
.mach
= cpu_types
[i
].mach
;
891 cpu_flags
= cpu_types
[i
].eflags
;
896 if (!cpu_types
[i
].name
)
897 as_fatal (_("unknown architecture: %s\n"), arg
);
899 /* Check if set features are compatible with the chosen CPU. */
900 arc_check_feature ();
901 gas_assert (cpu_flags
!= 0);
902 selected_cpu
.eflags
= (arc_initial_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
903 mach_selection_mode
= sel
;
906 /* Here ends all the ARCompact extension instruction assembling
910 arc_extra_reloc (int r_type
)
913 symbolS
*sym
, *lab
= NULL
;
915 if (*input_line_pointer
== '@')
916 input_line_pointer
++;
917 c
= get_symbol_name (&sym_name
);
918 sym
= symbol_find_or_make (sym_name
);
919 restore_line_pointer (c
);
920 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
922 ++input_line_pointer
;
924 c
= get_symbol_name (&lab_name
);
925 lab
= symbol_find_or_make (lab_name
);
926 restore_line_pointer (c
);
929 /* These relocations exist as a mechanism for the compiler to tell the
930 linker how to patch the code if the tls model is optimised. However,
931 the relocation itself does not require any space within the assembler
932 fragment, and so we pass a size of 0.
934 The lines that generate these relocations look like this:
936 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
938 The '.tls_gd_ld @.tdata' is processed first and generates the
939 additional relocation, while the 'bl __tls_get_addr@plt' is processed
940 second and generates the additional branch.
942 It is possible that the additional relocation generated by the
943 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
944 while the 'bl __tls_get_addr@plt' will be generated as the first thing
945 in the next fragment. This will be fine; both relocations will still
946 appear to be at the same address in the generated object file.
947 However, this only works as the additional relocation is generated
948 with size of 0 bytes. */
950 = fix_new (frag_now
, /* Which frag? */
951 frag_now_fix (), /* Where in that frag? */
952 0, /* size: 1, 2, or 4 usually. */
953 sym
, /* X_add_symbol. */
954 0, /* X_add_number. */
955 FALSE
, /* TRUE if PC-relative relocation. */
956 r_type
/* Relocation type. */);
957 fixP
->fx_subsy
= lab
;
961 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
962 symbolS
*symbolP
, addressT size
)
967 if (*input_line_pointer
== ',')
969 align
= parse_align (1);
971 if (align
== (addressT
) -1)
986 bss_alloc (symbolP
, size
, align
);
987 S_CLEAR_EXTERNAL (symbolP
);
993 arc_lcomm (int ignore
)
995 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
998 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
1001 /* Select the cpu we're assembling for. */
1004 arc_option (int ignore ATTRIBUTE_UNUSED
)
1008 const char *cpu_name
;
1010 c
= get_symbol_name (&cpu
);
1013 if ((!strcmp ("ARC600", cpu
))
1014 || (!strcmp ("ARC601", cpu
))
1015 || (!strcmp ("A6", cpu
)))
1016 cpu_name
= "arc600";
1017 else if ((!strcmp ("ARC700", cpu
))
1018 || (!strcmp ("A7", cpu
)))
1019 cpu_name
= "arc700";
1020 else if (!strcmp ("EM", cpu
))
1022 else if (!strcmp ("HS", cpu
))
1024 else if (!strcmp ("NPS400", cpu
))
1025 cpu_name
= "nps400";
1027 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1029 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
1030 as_fatal (_("could not set architecture and machine"));
1032 /* Set elf header flags. */
1033 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
1035 restore_line_pointer (c
);
1036 demand_empty_rest_of_line ();
1039 /* Smartly print an expression. */
1042 debug_exp (expressionS
*t
)
1044 const char *name ATTRIBUTE_UNUSED
;
1045 const char *namemd ATTRIBUTE_UNUSED
;
1047 pr_debug ("debug_exp: ");
1051 default: name
= "unknown"; break;
1052 case O_illegal
: name
= "O_illegal"; break;
1053 case O_absent
: name
= "O_absent"; break;
1054 case O_constant
: name
= "O_constant"; break;
1055 case O_symbol
: name
= "O_symbol"; break;
1056 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1057 case O_register
: name
= "O_register"; break;
1058 case O_big
: name
= "O_big"; break;
1059 case O_uminus
: name
= "O_uminus"; break;
1060 case O_bit_not
: name
= "O_bit_not"; break;
1061 case O_logical_not
: name
= "O_logical_not"; break;
1062 case O_multiply
: name
= "O_multiply"; break;
1063 case O_divide
: name
= "O_divide"; break;
1064 case O_modulus
: name
= "O_modulus"; break;
1065 case O_left_shift
: name
= "O_left_shift"; break;
1066 case O_right_shift
: name
= "O_right_shift"; break;
1067 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1068 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1069 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1070 case O_bit_and
: name
= "O_bit_and"; break;
1071 case O_add
: name
= "O_add"; break;
1072 case O_subtract
: name
= "O_subtract"; break;
1073 case O_eq
: name
= "O_eq"; break;
1074 case O_ne
: name
= "O_ne"; break;
1075 case O_lt
: name
= "O_lt"; break;
1076 case O_le
: name
= "O_le"; break;
1077 case O_ge
: name
= "O_ge"; break;
1078 case O_gt
: name
= "O_gt"; break;
1079 case O_logical_and
: name
= "O_logical_and"; break;
1080 case O_logical_or
: name
= "O_logical_or"; break;
1081 case O_index
: name
= "O_index"; break;
1082 case O_bracket
: name
= "O_bracket"; break;
1083 case O_colon
: name
= "O_colon"; break;
1084 case O_addrtype
: name
= "O_addrtype"; break;
1089 default: namemd
= "unknown"; break;
1090 case O_gotoff
: namemd
= "O_gotoff"; break;
1091 case O_gotpc
: namemd
= "O_gotpc"; break;
1092 case O_plt
: namemd
= "O_plt"; break;
1093 case O_sda
: namemd
= "O_sda"; break;
1094 case O_pcl
: namemd
= "O_pcl"; break;
1095 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1096 case O_tlsie
: namemd
= "O_tlsie"; break;
1097 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1098 case O_tpoff
: namemd
= "O_tpoff"; break;
1099 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1100 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1103 pr_debug ("%s (%s, %s, %d, %s)", name
,
1104 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1105 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1106 (int) t
->X_add_number
,
1107 (t
->X_md
) ? namemd
: "--");
1112 /* Parse the arguments to an opcode. */
1115 tokenize_arguments (char *str
,
1119 char *old_input_line_pointer
;
1120 bfd_boolean saw_comma
= FALSE
;
1121 bfd_boolean saw_arg
= FALSE
;
1126 const struct arc_reloc_op_tag
*r
;
1128 char *reloc_name
, c
;
1130 memset (tok
, 0, sizeof (*tok
) * ntok
);
1132 /* Save and restore input_line_pointer around this function. */
1133 old_input_line_pointer
= input_line_pointer
;
1134 input_line_pointer
= str
;
1136 while (*input_line_pointer
)
1139 switch (*input_line_pointer
)
1145 input_line_pointer
++;
1146 if (saw_comma
|| !saw_arg
)
1153 ++input_line_pointer
;
1155 if (!saw_arg
|| num_args
== ntok
)
1157 tok
->X_op
= O_bracket
;
1164 input_line_pointer
++;
1165 if (brk_lvl
|| num_args
== ntok
)
1168 tok
->X_op
= O_bracket
;
1174 input_line_pointer
++;
1175 if (!saw_arg
|| num_args
== ntok
)
1177 tok
->X_op
= O_colon
;
1184 /* We have labels, function names and relocations, all
1185 starting with @ symbol. Sort them out. */
1186 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1190 tok
->X_op
= O_symbol
;
1191 tok
->X_md
= O_absent
;
1193 if (*input_line_pointer
!= '@')
1194 goto normalsymbol
; /* This is not a relocation. */
1198 /* A relocation operand has the following form
1199 @identifier@relocation_type. The identifier is already
1201 if (tok
->X_op
!= O_symbol
)
1203 as_bad (_("No valid label relocation operand"));
1207 /* Parse @relocation_type. */
1208 input_line_pointer
++;
1209 c
= get_symbol_name (&reloc_name
);
1210 len
= input_line_pointer
- reloc_name
;
1213 as_bad (_("No relocation operand"));
1217 /* Go through known relocation and try to find a match. */
1218 r
= &arc_reloc_op
[0];
1219 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1220 if (len
== r
->length
1221 && memcmp (reloc_name
, r
->name
, len
) == 0)
1225 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1229 *input_line_pointer
= c
;
1230 SKIP_WHITESPACE_AFTER_NAME ();
1231 /* Extra check for TLS: base. */
1232 if (*input_line_pointer
== '@')
1235 if (tok
->X_op_symbol
!= NULL
1236 || tok
->X_op
!= O_symbol
)
1238 as_bad (_("Unable to parse TLS base: %s"),
1239 input_line_pointer
);
1242 input_line_pointer
++;
1244 c
= get_symbol_name (&sym_name
);
1245 base
= symbol_find_or_make (sym_name
);
1246 tok
->X_op
= O_subtract
;
1247 tok
->X_op_symbol
= base
;
1248 restore_line_pointer (c
);
1249 tmpE
.X_add_number
= 0;
1251 if ((*input_line_pointer
!= '+')
1252 && (*input_line_pointer
!= '-'))
1254 tmpE
.X_add_number
= 0;
1258 /* Parse the constant of a complex relocation expression
1259 like @identifier@reloc +/- const. */
1260 if (! r
->complex_expr
)
1262 as_bad (_("@%s is not a complex relocation."), r
->name
);
1266 if (tmpE
.X_op
!= O_constant
)
1268 as_bad (_("Bad expression: @%s + %s."),
1269 r
->name
, input_line_pointer
);
1275 tok
->X_add_number
= tmpE
.X_add_number
;
1286 /* Can be a register. */
1287 ++input_line_pointer
;
1291 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1294 tok
->X_op
= O_absent
;
1295 tok
->X_md
= O_absent
;
1298 /* Legacy: There are cases when we have
1299 identifier@relocation_type, if it is the case parse the
1300 relocation type as well. */
1301 if (*input_line_pointer
== '@')
1307 if (tok
->X_op
== O_illegal
1308 || tok
->X_op
== O_absent
1309 || num_args
== ntok
)
1321 if (saw_comma
|| brk_lvl
)
1323 input_line_pointer
= old_input_line_pointer
;
1329 as_bad (_("Brackets in operand field incorrect"));
1331 as_bad (_("extra comma"));
1333 as_bad (_("missing argument"));
1335 as_bad (_("missing comma or colon"));
1336 input_line_pointer
= old_input_line_pointer
;
1340 /* Parse the flags to a structure. */
1343 tokenize_flags (const char *str
,
1344 struct arc_flags flags
[],
1347 char *old_input_line_pointer
;
1348 bfd_boolean saw_flg
= FALSE
;
1349 bfd_boolean saw_dot
= FALSE
;
1353 memset (flags
, 0, sizeof (*flags
) * nflg
);
1355 /* Save and restore input_line_pointer around this function. */
1356 old_input_line_pointer
= input_line_pointer
;
1357 input_line_pointer
= (char *) str
;
1359 while (*input_line_pointer
)
1361 switch (*input_line_pointer
)
1368 input_line_pointer
++;
1376 if (saw_flg
&& !saw_dot
)
1379 if (num_flags
>= nflg
)
1382 flgnamelen
= strspn (input_line_pointer
,
1383 "abcdefghijklmnopqrstuvwxyz0123456789");
1384 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1387 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1389 input_line_pointer
+= flgnamelen
;
1399 input_line_pointer
= old_input_line_pointer
;
1404 as_bad (_("extra dot"));
1406 as_bad (_("unrecognized flag"));
1408 as_bad (_("failed to parse flags"));
1409 input_line_pointer
= old_input_line_pointer
;
1413 /* Apply the fixups in order. */
1416 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1420 for (i
= 0; i
< insn
->nfixups
; i
++)
1422 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1423 int size
, pcrel
, offset
= 0;
1425 /* FIXME! the reloc size is wrong in the BFD file.
1426 When it is fixed please delete me. */
1427 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1432 /* Some fixups are only used internally, thus no howto. */
1433 if ((int) fixup
->reloc
== 0)
1434 as_fatal (_("Unhandled reloc type"));
1436 if ((int) fixup
->reloc
< 0)
1438 /* FIXME! the reloc size is wrong in the BFD file.
1439 When it is fixed please enable me.
1440 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1441 pcrel
= fixup
->pcrel
;
1445 reloc_howto_type
*reloc_howto
=
1446 bfd_reloc_type_lookup (stdoutput
,
1447 (bfd_reloc_code_real_type
) fixup
->reloc
);
1448 gas_assert (reloc_howto
);
1450 /* FIXME! the reloc size is wrong in the BFD file.
1451 When it is fixed please enable me.
1452 size = bfd_get_reloc_size (reloc_howto); */
1453 pcrel
= reloc_howto
->pc_relative
;
1456 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1458 fragP
->fr_file
, fragP
->fr_line
,
1459 (fixup
->reloc
< 0) ? "Internal" :
1460 bfd_get_reloc_code_name (fixup
->reloc
),
1463 fix_new_exp (fragP
, fix
+ offset
,
1464 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1466 /* Check for ZOLs, and update symbol info if any. */
1467 if (LP_INSN (insn
->insn
))
1469 gas_assert (fixup
->exp
.X_add_symbol
);
1470 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1475 /* Actually output an instruction with its fixup. */
1478 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1483 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1484 pr_debug ("\tLength : 0x%d\n", insn
->len
);
1485 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1487 /* Write out the instruction. */
1488 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1490 f
= frag_more (total_len
);
1492 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1495 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1496 dwarf2_emit_insn (total_len
);
1499 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1503 emit_insn1 (struct arc_insn
*insn
)
1505 /* How frag_var's args are currently configured:
1506 - rs_machine_dependent, to dictate it's a relaxation frag.
1507 - FRAG_MAX_GROWTH, maximum size of instruction
1508 - 0, variable size that might grow...unused by generic relaxation.
1509 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1510 - s, opand expression.
1511 - 0, offset but it's unused.
1512 - 0, opcode but it's unused. */
1513 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1514 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1516 if (frag_room () < FRAG_MAX_GROWTH
)
1518 /* Handle differently when frag literal memory is exhausted.
1519 This is used because when there's not enough memory left in
1520 the current frag, a new frag is created and the information
1521 we put into frag_now->tc_frag_data is disregarded. */
1523 struct arc_relax_type relax_info_copy
;
1524 relax_substateT subtype
= frag_now
->fr_subtype
;
1526 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1527 sizeof (struct arc_relax_type
));
1529 frag_wane (frag_now
);
1530 frag_grow (FRAG_MAX_GROWTH
);
1532 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1533 sizeof (struct arc_relax_type
));
1535 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1539 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1540 frag_now
->fr_subtype
, s
, 0, 0);
1544 emit_insn (struct arc_insn
*insn
)
1549 emit_insn0 (insn
, NULL
, FALSE
);
1552 /* Check whether a symbol involves a register. */
1555 contains_register (symbolS
*sym
)
1559 expressionS
*ex
= symbol_get_value_expression (sym
);
1561 return ((O_register
== ex
->X_op
)
1562 && !contains_register (ex
->X_add_symbol
)
1563 && !contains_register (ex
->X_op_symbol
));
1569 /* Returns the register number within a symbol. */
1572 get_register (symbolS
*sym
)
1574 if (!contains_register (sym
))
1577 expressionS
*ex
= symbol_get_value_expression (sym
);
1578 return regno (ex
->X_add_number
);
1581 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1582 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1585 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1592 case BFD_RELOC_ARC_SDA_LDST
:
1593 case BFD_RELOC_ARC_SDA_LDST1
:
1594 case BFD_RELOC_ARC_SDA_LDST2
:
1595 case BFD_RELOC_ARC_SDA16_LD
:
1596 case BFD_RELOC_ARC_SDA16_LD1
:
1597 case BFD_RELOC_ARC_SDA16_LD2
:
1598 case BFD_RELOC_ARC_SDA16_ST2
:
1599 case BFD_RELOC_ARC_SDA32_ME
:
1606 /* Allocates a tok entry. */
1609 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1611 if (ntok
> MAX_INSN_ARGS
- 2)
1612 return 0; /* No space left. */
1615 return 0; /* Incorrect args. */
1617 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1620 return 1; /* Success. */
1621 return allocate_tok (tok
, ntok
- 1, cidx
);
1624 /* Check if an particular ARC feature is enabled. */
1627 check_cpu_feature (insn_subclass_t sc
)
1629 if (is_code_density_p (sc
) && !(selected_cpu
.features
& ARC_CD
))
1632 if (is_spfp_p (sc
) && !(selected_cpu
.features
& ARC_SPFP
))
1635 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& ARC_DPFP
))
1638 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& ARC_FPUDA
))
1641 if (is_nps400_p (sc
) && !(selected_cpu
.features
& ARC_NPS400
))
1647 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1648 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1649 array and returns TRUE if the flag operands all match, otherwise,
1650 returns FALSE, in which case the FIRST_PFLAG array may have been
1654 parse_opcode_flags (const struct arc_opcode
*opcode
,
1656 struct arc_flags
*first_pflag
)
1659 const unsigned char *flgidx
;
1662 for (i
= 0; i
< nflgs
; i
++)
1663 first_pflag
[i
].flgp
= NULL
;
1665 /* Check the flags. Iterate over the valid flag classes. */
1666 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1668 /* Get a valid flag class. */
1669 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1670 const unsigned *flgopridx
;
1672 struct arc_flags
*pflag
= NULL
;
1674 /* Check if opcode has implicit flag classes. */
1675 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
1678 /* Check for extension conditional codes. */
1679 if (ext_condcode
.arc_ext_condcode
1680 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1682 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1685 pflag
= first_pflag
;
1686 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1688 if (!strcmp (pf
->name
, pflag
->name
))
1690 if (pflag
->flgp
!= NULL
)
1703 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1705 const struct arc_flag_operand
*flg_operand
;
1707 pflag
= first_pflag
;
1708 flg_operand
= &arc_flag_operands
[*flgopridx
];
1709 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1711 /* Match against the parsed flags. */
1712 if (!strcmp (flg_operand
->name
, pflag
->name
))
1714 if (pflag
->flgp
!= NULL
)
1717 pflag
->flgp
= flg_operand
;
1719 break; /* goto next flag class and parsed flag. */
1724 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1726 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1730 /* Did I check all the parsed flags? */
1731 return lnflg
? FALSE
: TRUE
;
1735 /* Search forward through all variants of an opcode looking for a
1738 static const struct arc_opcode
*
1739 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1742 struct arc_flags
*first_pflag
,
1745 const char **errmsg
)
1747 const struct arc_opcode
*opcode
;
1748 struct arc_opcode_hash_entry_iterator iter
;
1750 int got_cpu_match
= 0;
1751 expressionS bktok
[MAX_INSN_ARGS
];
1755 arc_opcode_hash_entry_iterator_init (&iter
);
1756 memset (&emptyE
, 0, sizeof (emptyE
));
1757 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1760 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1762 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1764 const unsigned char *opidx
;
1766 const expressionS
*t
= &emptyE
;
1768 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1769 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1771 /* Don't match opcodes that don't exist on this
1773 if (!(opcode
->cpu
& selected_cpu
.flags
))
1776 if (!check_cpu_feature (opcode
->subclass
))
1782 /* Check the operands. */
1783 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1785 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1787 /* Only take input from real operands. */
1788 if (ARC_OPERAND_IS_FAKE (operand
))
1791 /* When we expect input, make sure we have it. */
1795 /* Match operand type with expression type. */
1796 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1798 case ARC_OPERAND_ADDRTYPE
:
1802 /* Check to be an address type. */
1803 if (tok
[tokidx
].X_op
!= O_addrtype
)
1806 /* All address type operands need to have an insert
1807 method in order to check that we have the correct
1809 gas_assert (operand
->insert
!= NULL
);
1810 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1812 if (*errmsg
!= NULL
)
1817 case ARC_OPERAND_IR
:
1818 /* Check to be a register. */
1819 if ((tok
[tokidx
].X_op
!= O_register
1820 || !is_ir_num (tok
[tokidx
].X_add_number
))
1821 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1824 /* If expect duplicate, make sure it is duplicate. */
1825 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1827 /* Check for duplicate. */
1828 if (t
->X_op
!= O_register
1829 || !is_ir_num (t
->X_add_number
)
1830 || (regno (t
->X_add_number
) !=
1831 regno (tok
[tokidx
].X_add_number
)))
1835 /* Special handling? */
1836 if (operand
->insert
)
1839 (*operand
->insert
)(0,
1840 regno (tok
[tokidx
].X_add_number
),
1844 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1846 /* Missing argument, create one. */
1847 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1850 tok
[tokidx
].X_op
= O_absent
;
1861 case ARC_OPERAND_BRAKET
:
1862 /* Check if bracket is also in opcode table as
1864 if (tok
[tokidx
].X_op
!= O_bracket
)
1868 case ARC_OPERAND_COLON
:
1869 /* Check if colon is also in opcode table as operand. */
1870 if (tok
[tokidx
].X_op
!= O_colon
)
1874 case ARC_OPERAND_LIMM
:
1875 case ARC_OPERAND_SIGNED
:
1876 case ARC_OPERAND_UNSIGNED
:
1877 switch (tok
[tokidx
].X_op
)
1885 /* Got an (too) early bracket, check if it is an
1886 ignored operand. N.B. This procedure works only
1887 when bracket is the last operand! */
1888 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1890 /* Insert the missing operand. */
1891 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1894 tok
[tokidx
].X_op
= O_absent
;
1901 const struct arc_aux_reg
*auxr
;
1903 if (opcode
->insn_class
!= AUXREG
)
1905 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1907 auxr
= hash_find (arc_aux_hash
, p
);
1910 /* We modify the token array here, safe in the
1911 knowledge, that if this was the wrong
1912 choice then the original contents will be
1913 restored from BKTOK. */
1914 tok
[tokidx
].X_op
= O_constant
;
1915 tok
[tokidx
].X_add_number
= auxr
->address
;
1916 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1919 if (tok
[tokidx
].X_op
!= O_constant
)
1924 /* Check the range. */
1925 if (operand
->bits
!= 32
1926 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1928 offsetT min
, max
, val
;
1929 val
= tok
[tokidx
].X_add_number
;
1931 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1933 max
= (1 << (operand
->bits
- 1)) - 1;
1934 min
= -(1 << (operand
->bits
- 1));
1938 max
= (1 << operand
->bits
) - 1;
1942 if (val
< min
|| val
> max
)
1945 /* Check alignments. */
1946 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1950 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1954 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1956 if (operand
->insert
)
1959 (*operand
->insert
)(0,
1960 tok
[tokidx
].X_add_number
,
1965 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1971 /* Check if it is register range. */
1972 if ((tok
[tokidx
].X_add_number
== 0)
1973 && contains_register (tok
[tokidx
].X_add_symbol
)
1974 && contains_register (tok
[tokidx
].X_op_symbol
))
1978 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1980 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1981 if (operand
->insert
)
1984 (*operand
->insert
)(0,
1997 if (operand
->default_reloc
== 0)
1998 goto match_failed
; /* The operand needs relocation. */
2000 /* Relocs requiring long immediate. FIXME! make it
2001 generic and move it to a function. */
2002 switch (tok
[tokidx
].X_md
)
2011 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
2015 if (!generic_reloc_p (operand
->default_reloc
))
2023 /* If expect duplicate, make sure it is duplicate. */
2024 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
2026 if (t
->X_op
== O_illegal
2027 || t
->X_op
== O_absent
2028 || t
->X_op
== O_register
2029 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2036 /* Everything else should have been fake. */
2044 /* Setup ready for flag parsing. */
2045 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2049 /* Possible match -- did we use all of our input? */
2059 /* Restore the original parameters. */
2060 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2065 *pcpumatch
= got_cpu_match
;
2070 /* Swap operand tokens. */
2073 swap_operand (expressionS
*operand_array
,
2075 unsigned destination
)
2077 expressionS cpy_operand
;
2078 expressionS
*src_operand
;
2079 expressionS
*dst_operand
;
2082 if (source
== destination
)
2085 src_operand
= &operand_array
[source
];
2086 dst_operand
= &operand_array
[destination
];
2087 size
= sizeof (expressionS
);
2089 /* Make copy of operand to swap with and swap. */
2090 memcpy (&cpy_operand
, dst_operand
, size
);
2091 memcpy (dst_operand
, src_operand
, size
);
2092 memcpy (src_operand
, &cpy_operand
, size
);
2095 /* Check if *op matches *tok type.
2096 Returns FALSE if they don't match, TRUE if they match. */
2099 pseudo_operand_match (const expressionS
*tok
,
2100 const struct arc_operand_operation
*op
)
2102 offsetT min
, max
, val
;
2104 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2110 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2112 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2114 val
= tok
->X_add_number
+ op
->count
;
2115 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2117 max
= (1 << (operand_real
->bits
- 1)) - 1;
2118 min
= -(1 << (operand_real
->bits
- 1));
2122 max
= (1 << operand_real
->bits
) - 1;
2125 if (min
<= val
&& val
<= max
)
2131 /* Handle all symbols as long immediates or signed 9. */
2132 if (operand_real
->flags
& ARC_OPERAND_LIMM
2133 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2134 && operand_real
->bits
== 9))
2139 if (operand_real
->flags
& ARC_OPERAND_IR
)
2144 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2155 /* Find pseudo instruction in array. */
2157 static const struct arc_pseudo_insn
*
2158 find_pseudo_insn (const char *opname
,
2160 const expressionS
*tok
)
2162 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2163 const struct arc_operand_operation
*op
;
2167 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2169 pseudo_insn
= &arc_pseudo_insns
[i
];
2170 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2172 op
= pseudo_insn
->operand
;
2173 for (j
= 0; j
< ntok
; ++j
)
2174 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2177 /* Found the right instruction. */
2185 /* Assumes the expressionS *tok is of sufficient size. */
2187 static const struct arc_opcode_hash_entry
*
2188 find_special_case_pseudo (const char *opname
,
2192 struct arc_flags
*pflags
)
2194 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2195 const struct arc_operand_operation
*operand_pseudo
;
2196 const struct arc_operand
*operand_real
;
2198 char construct_operand
[MAX_CONSTR_STR
];
2200 /* Find whether opname is in pseudo instruction array. */
2201 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2203 if (pseudo_insn
== NULL
)
2206 /* Handle flag, Limited to one flag at the moment. */
2207 if (pseudo_insn
->flag_r
!= NULL
)
2208 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2209 MAX_INSN_FLGS
- *nflgs
);
2211 /* Handle operand operations. */
2212 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2214 operand_pseudo
= &pseudo_insn
->operand
[i
];
2215 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2217 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2218 && !operand_pseudo
->needs_insert
)
2221 /* Has to be inserted (i.e. this token does not exist yet). */
2222 if (operand_pseudo
->needs_insert
)
2224 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2226 tok
[i
].X_op
= O_bracket
;
2231 /* Check if operand is a register or constant and handle it
2233 if (operand_real
->flags
& ARC_OPERAND_IR
)
2234 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2235 operand_pseudo
->count
);
2237 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2238 operand_pseudo
->count
);
2240 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2244 else if (operand_pseudo
->count
)
2246 /* Operand number has to be adjusted accordingly (by operand
2248 switch (tok
[i
].X_op
)
2251 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2264 /* Swap operands if necessary. Only supports one swap at the
2266 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2268 operand_pseudo
= &pseudo_insn
->operand
[i
];
2270 if (operand_pseudo
->swap_operand_idx
== i
)
2273 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2275 /* Prevent a swap back later by breaking out. */
2279 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2282 static const struct arc_opcode_hash_entry
*
2283 find_special_case_flag (const char *opname
,
2285 struct arc_flags
*pflags
)
2289 unsigned flag_idx
, flag_arr_idx
;
2290 size_t flaglen
, oplen
;
2291 const struct arc_flag_special
*arc_flag_special_opcode
;
2292 const struct arc_opcode_hash_entry
*entry
;
2294 /* Search for special case instruction. */
2295 for (i
= 0; i
< arc_num_flag_special
; i
++)
2297 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2298 oplen
= strlen (arc_flag_special_opcode
->name
);
2300 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2303 /* Found a potential special case instruction, now test for
2305 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2307 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2309 break; /* End of array, nothing found. */
2311 flagnm
= arc_flag_operands
[flag_idx
].name
;
2312 flaglen
= strlen (flagnm
);
2313 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2315 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2317 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2319 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2320 pflags
[*nflgs
].name
[flaglen
] = '\0';
2329 /* Used to find special case opcode. */
2331 static const struct arc_opcode_hash_entry
*
2332 find_special_case (const char *opname
,
2334 struct arc_flags
*pflags
,
2338 const struct arc_opcode_hash_entry
*entry
;
2340 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2343 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2348 /* Given an opcode name, pre-tokenized set of arguments and the
2349 opcode flags, take it all the way through emission. */
2352 assemble_tokens (const char *opname
,
2355 struct arc_flags
*pflags
,
2358 bfd_boolean found_something
= FALSE
;
2359 const struct arc_opcode_hash_entry
*entry
;
2361 const char *errmsg
= NULL
;
2363 /* Search opcodes. */
2364 entry
= arc_find_opcode (opname
);
2366 /* Couldn't find opcode conventional way, try special cases. */
2368 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2372 const struct arc_opcode
*opcode
;
2374 pr_debug ("%s:%d: assemble_tokens: %s\n",
2375 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2376 found_something
= TRUE
;
2377 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2378 nflgs
, &cpumatch
, &errmsg
);
2381 struct arc_insn insn
;
2383 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2389 if (found_something
)
2393 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2395 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2397 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2401 as_bad (_("unknown opcode '%s'"), opname
);
2404 /* The public interface to the instruction assembler. */
2407 md_assemble (char *str
)
2410 expressionS tok
[MAX_INSN_ARGS
];
2413 struct arc_flags flags
[MAX_INSN_FLGS
];
2415 /* Split off the opcode. */
2416 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2417 opname
= xmemdup0 (str
, opnamelen
);
2419 /* Signalize we are assembling the instructions. */
2420 assembling_insn
= TRUE
;
2422 /* Tokenize the flags. */
2423 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2425 as_bad (_("syntax error"));
2429 /* Scan up to the end of the mnemonic which must end in space or end
2432 for (; *str
!= '\0'; str
++)
2436 /* Tokenize the rest of the line. */
2437 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2439 as_bad (_("syntax error"));
2443 /* Finish it off. */
2444 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2445 assembling_insn
= FALSE
;
2448 /* Callback to insert a register into the hash table. */
2451 declare_register (const char *name
, int number
)
2454 symbolS
*regS
= symbol_create (name
, reg_section
,
2455 number
, &zero_address_frag
);
2457 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2459 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2463 /* Construct symbols for each of the general registers. */
2466 declare_register_set (void)
2469 for (i
= 0; i
< 64; ++i
)
2473 sprintf (name
, "r%d", i
);
2474 declare_register (name
, i
);
2475 if ((i
& 0x01) == 0)
2477 sprintf (name
, "r%dr%d", i
, i
+1);
2478 declare_register (name
, i
);
2483 /* Construct a symbol for an address type. */
2486 declare_addrtype (const char *name
, int number
)
2489 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2490 number
, &zero_address_frag
);
2492 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2493 (void *) addrtypeS
);
2495 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2499 /* Port-specific assembler initialization. This function is called
2500 once, at assembler startup time. */
2505 const struct arc_opcode
*opcode
= arc_opcodes
;
2507 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2508 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2510 /* The endianness can be chosen "at the factory". */
2511 target_big_endian
= byte_order
== BIG_ENDIAN
;
2513 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2514 as_warn (_("could not set architecture and machine"));
2516 /* Set elf header flags. */
2517 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2519 /* Set up a hash table for the instructions. */
2520 arc_opcode_hash
= hash_new ();
2521 if (arc_opcode_hash
== NULL
)
2522 as_fatal (_("Virtual memory exhausted"));
2524 /* Initialize the hash table with the insns. */
2527 const char *name
= opcode
->name
;
2529 arc_insert_opcode (opcode
);
2531 while (++opcode
&& opcode
->name
2532 && (opcode
->name
== name
2533 || !strcmp (opcode
->name
, name
)))
2535 }while (opcode
->name
);
2537 /* Register declaration. */
2538 arc_reg_hash
= hash_new ();
2539 if (arc_reg_hash
== NULL
)
2540 as_fatal (_("Virtual memory exhausted"));
2542 declare_register_set ();
2543 declare_register ("gp", 26);
2544 declare_register ("fp", 27);
2545 declare_register ("sp", 28);
2546 declare_register ("ilink", 29);
2547 declare_register ("ilink1", 29);
2548 declare_register ("ilink2", 30);
2549 declare_register ("blink", 31);
2551 /* XY memory registers. */
2552 declare_register ("x0_u0", 32);
2553 declare_register ("x0_u1", 33);
2554 declare_register ("x1_u0", 34);
2555 declare_register ("x1_u1", 35);
2556 declare_register ("x2_u0", 36);
2557 declare_register ("x2_u1", 37);
2558 declare_register ("x3_u0", 38);
2559 declare_register ("x3_u1", 39);
2560 declare_register ("y0_u0", 40);
2561 declare_register ("y0_u1", 41);
2562 declare_register ("y1_u0", 42);
2563 declare_register ("y1_u1", 43);
2564 declare_register ("y2_u0", 44);
2565 declare_register ("y2_u1", 45);
2566 declare_register ("y3_u0", 46);
2567 declare_register ("y3_u1", 47);
2568 declare_register ("x0_nu", 48);
2569 declare_register ("x1_nu", 49);
2570 declare_register ("x2_nu", 50);
2571 declare_register ("x3_nu", 51);
2572 declare_register ("y0_nu", 52);
2573 declare_register ("y1_nu", 53);
2574 declare_register ("y2_nu", 54);
2575 declare_register ("y3_nu", 55);
2577 declare_register ("mlo", 57);
2578 declare_register ("mmid", 58);
2579 declare_register ("mhi", 59);
2581 declare_register ("acc1", 56);
2582 declare_register ("acc2", 57);
2584 declare_register ("lp_count", 60);
2585 declare_register ("pcl", 63);
2587 /* Initialize the last instructions. */
2588 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2590 /* Aux register declaration. */
2591 arc_aux_hash
= hash_new ();
2592 if (arc_aux_hash
== NULL
)
2593 as_fatal (_("Virtual memory exhausted"));
2595 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2597 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2601 if (!(auxr
->cpu
& selected_cpu
.flags
))
2604 if ((auxr
->subclass
!= NONE
)
2605 && !check_cpu_feature (auxr
->subclass
))
2608 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2610 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2611 auxr
->name
, retval
);
2614 /* Address type declaration. */
2615 arc_addrtype_hash
= hash_new ();
2616 if (arc_addrtype_hash
== NULL
)
2617 as_fatal (_("Virtual memory exhausted"));
2619 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2620 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2621 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2622 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2623 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2624 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2625 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2626 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2627 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2628 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2629 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2630 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2631 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2632 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2633 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2634 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2637 /* Write a value out to the object file, using the appropriate
2641 md_number_to_chars (char *buf
,
2645 if (target_big_endian
)
2646 number_to_chars_bigendian (buf
, val
, n
);
2648 number_to_chars_littleendian (buf
, val
, n
);
2651 /* Round up a section size to the appropriate boundary. */
2654 md_section_align (segT segment
,
2657 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2659 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2662 /* The location from which a PC relative jump should be calculated,
2663 given a PC relative reloc. */
2666 md_pcrel_from_section (fixS
*fixP
,
2669 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2671 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2673 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2674 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2675 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2677 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2679 /* The symbol is undefined (or is defined but not in this section).
2680 Let the linker figure it out. */
2684 if ((int) fixP
->fx_r_type
< 0)
2686 /* These are the "internal" relocations. Align them to
2687 32 bit boundary (PCL), for the moment. */
2692 switch (fixP
->fx_r_type
)
2694 case BFD_RELOC_ARC_PC32
:
2695 /* The hardware calculates relative to the start of the
2696 insn, but this relocation is relative to location of the
2697 LIMM, compensate. The base always needs to be
2698 subtracted by 4 as we do not support this type of PCrel
2699 relocation for short instructions. */
2702 case BFD_RELOC_ARC_PLT32
:
2703 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2704 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2705 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2706 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2708 case BFD_RELOC_ARC_S21H_PCREL
:
2709 case BFD_RELOC_ARC_S25H_PCREL
:
2710 case BFD_RELOC_ARC_S13_PCREL
:
2711 case BFD_RELOC_ARC_S21W_PCREL
:
2712 case BFD_RELOC_ARC_S25W_PCREL
:
2716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2717 _("unhandled reloc %s in md_pcrel_from_section"),
2718 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2723 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2724 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2725 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2726 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2727 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2732 /* Given a BFD relocation find the corresponding operand. */
2734 static const struct arc_operand
*
2735 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2739 for (i
= 0; i
< arc_num_operands
; i
++)
2740 if (arc_operands
[i
].default_reloc
== reloc
)
2741 return &arc_operands
[i
];
2745 /* Insert an operand value into an instruction. */
2747 static unsigned long long
2748 insert_operand (unsigned long long insn
,
2749 const struct arc_operand
*operand
,
2754 offsetT min
= 0, max
= 0;
2756 if (operand
->bits
!= 32
2757 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2758 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2760 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2762 max
= (1 << (operand
->bits
- 1)) - 1;
2763 min
= -(1 << (operand
->bits
- 1));
2767 max
= (1 << operand
->bits
) - 1;
2771 if (val
< min
|| val
> max
)
2772 as_bad_value_out_of_range (_("operand"),
2773 val
, min
, max
, file
, line
);
2776 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2777 min
, val
, max
, insn
);
2779 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2781 as_bad_where (file
, line
,
2782 _("Unaligned operand. Needs to be 32bit aligned"));
2784 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2786 as_bad_where (file
, line
,
2787 _("Unaligned operand. Needs to be 16bit aligned"));
2789 if (operand
->insert
)
2791 const char *errmsg
= NULL
;
2793 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2795 as_warn_where (file
, line
, "%s", errmsg
);
2799 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2801 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2803 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2806 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2811 /* Apply a fixup to the object code. At this point all symbol values
2812 should be fully resolved, and we attempt to completely resolve the
2813 reloc. If we can not do that, we determine the correct reloc code
2814 and put it back in the fixup. To indicate that a fixup has been
2815 eliminated, set fixP->fx_done. */
2818 md_apply_fix (fixS
*fixP
,
2822 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2823 valueT value
= *valP
;
2825 symbolS
*fx_addsy
, *fx_subsy
;
2827 segT add_symbol_segment
= absolute_section
;
2828 segT sub_symbol_segment
= absolute_section
;
2829 const struct arc_operand
*operand
= NULL
;
2830 extended_bfd_reloc_code_real_type reloc
;
2832 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2833 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2834 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2835 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2838 fx_addsy
= fixP
->fx_addsy
;
2839 fx_subsy
= fixP
->fx_subsy
;
2844 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2848 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2849 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2850 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2852 resolve_symbol_value (fx_subsy
);
2853 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2855 if (sub_symbol_segment
== absolute_section
)
2857 /* The symbol is really a constant. */
2858 fx_offset
-= S_GET_VALUE (fx_subsy
);
2863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2864 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2865 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2866 segment_name (add_symbol_segment
),
2867 S_GET_NAME (fx_subsy
),
2868 segment_name (sub_symbol_segment
));
2874 && !S_IS_WEAK (fx_addsy
))
2876 if (add_symbol_segment
== seg
2879 value
+= S_GET_VALUE (fx_addsy
);
2880 value
-= md_pcrel_from_section (fixP
, seg
);
2882 fixP
->fx_pcrel
= FALSE
;
2884 else if (add_symbol_segment
== absolute_section
)
2886 value
= fixP
->fx_offset
;
2887 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2889 fixP
->fx_pcrel
= FALSE
;
2894 fixP
->fx_done
= TRUE
;
2899 && ((S_IS_DEFINED (fx_addsy
)
2900 && S_GET_SEGMENT (fx_addsy
) != seg
)
2901 || S_IS_WEAK (fx_addsy
)))
2902 value
+= md_pcrel_from_section (fixP
, seg
);
2904 switch (fixP
->fx_r_type
)
2906 case BFD_RELOC_ARC_32_ME
:
2907 /* This is a pc-relative value in a LIMM. Adjust it to the
2908 address of the instruction not to the address of the
2909 LIMM. Note: it is not any longer valid this affirmation as
2910 the linker consider ARC_PC32 a fixup to entire 64 bit
2912 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2915 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2917 case BFD_RELOC_ARC_PC32
:
2918 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2921 if ((int) fixP
->fx_r_type
< 0)
2922 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2928 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2929 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2930 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2931 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2935 /* Now check for TLS relocations. */
2936 reloc
= fixP
->fx_r_type
;
2939 case BFD_RELOC_ARC_TLS_DTPOFF
:
2940 case BFD_RELOC_ARC_TLS_LE_32
:
2944 case BFD_RELOC_ARC_TLS_GD_GOT
:
2945 case BFD_RELOC_ARC_TLS_IE_GOT
:
2946 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2949 case BFD_RELOC_ARC_TLS_GD_LD
:
2950 gas_assert (!fixP
->fx_offset
);
2953 = (S_GET_VALUE (fixP
->fx_subsy
)
2954 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2955 fixP
->fx_subsy
= NULL
;
2957 case BFD_RELOC_ARC_TLS_GD_CALL
:
2958 /* These two relocs are there just to allow ld to change the tls
2959 model for this symbol, by patching the code. The offset -
2960 and scale, if any - will be installed by the linker. */
2961 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2964 case BFD_RELOC_ARC_TLS_LE_S9
:
2965 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2966 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2978 /* Adjust the value if we have a constant. */
2981 /* For hosts with longs bigger than 32-bits make sure that the top
2982 bits of a 32-bit negative value read in by the parser are set,
2983 so that the correct comparisons are made. */
2984 if (value
& 0x80000000)
2985 value
|= (-1UL << 31);
2987 reloc
= fixP
->fx_r_type
;
2995 case BFD_RELOC_ARC_32_PCREL
:
2996 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2999 case BFD_RELOC_ARC_GOTPC32
:
3000 /* I cannot fix an GOTPC relocation because I need to relax it
3001 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3002 as_bad (_("Unsupported operation on reloc"));
3005 case BFD_RELOC_ARC_TLS_DTPOFF
:
3006 case BFD_RELOC_ARC_TLS_LE_32
:
3007 gas_assert (!fixP
->fx_addsy
);
3008 gas_assert (!fixP
->fx_subsy
);
3011 case BFD_RELOC_ARC_GOTOFF
:
3012 case BFD_RELOC_ARC_32_ME
:
3013 case BFD_RELOC_ARC_PC32
:
3014 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3017 case BFD_RELOC_ARC_PLT32
:
3018 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3021 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3022 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3025 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3026 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3029 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3030 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3033 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3034 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3037 case BFD_RELOC_ARC_S25W_PCREL
:
3038 case BFD_RELOC_ARC_S21W_PCREL
:
3039 case BFD_RELOC_ARC_S21H_PCREL
:
3040 case BFD_RELOC_ARC_S25H_PCREL
:
3041 case BFD_RELOC_ARC_S13_PCREL
:
3043 operand
= find_operand_for_reloc (reloc
);
3044 gas_assert (operand
);
3049 if ((int) fixP
->fx_r_type
>= 0)
3050 as_fatal (_("unhandled relocation type %s"),
3051 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3053 /* The rest of these fixups needs to be completely resolved as
3055 if (fixP
->fx_addsy
!= 0
3056 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3058 _("non-absolute expression in constant field"));
3060 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3061 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3066 if (target_big_endian
)
3068 switch (fixP
->fx_size
)
3071 insn
= bfd_getb32 (fixpos
);
3074 insn
= bfd_getb16 (fixpos
);
3077 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3078 _("unknown fixup size"));
3084 switch (fixP
->fx_size
)
3087 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3090 insn
= bfd_getl16 (fixpos
);
3093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3094 _("unknown fixup size"));
3098 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3099 fixP
->fx_file
, fixP
->fx_line
);
3101 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3104 /* Prepare machine-dependent frags for relaxation.
3106 Called just before relaxation starts. Any symbol that is now undefined
3107 will not become defined.
3109 Return the correct fr_subtype in the frag.
3111 Return the initial "guess for fr_var" to caller. The guess for fr_var
3112 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3113 or fr_var contributes to our returned value.
3115 Although it may not be explicit in the frag, pretend
3116 fr_var starts with a value. */
3119 md_estimate_size_before_relax (fragS
*fragP
,
3124 /* If the symbol is not located within the same section AND it's not
3125 an absolute section, use the maximum. OR if the symbol is a
3126 constant AND the insn is by nature not pc-rel, use the maximum.
3127 OR if the symbol is being equated against another symbol, use the
3128 maximum. OR if the symbol is weak use the maximum. */
3129 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3130 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3131 || (symbol_constant_p (fragP
->fr_symbol
)
3132 && !fragP
->tc_frag_data
.pcrel
)
3133 || symbol_equated_p (fragP
->fr_symbol
)
3134 || S_IS_WEAK (fragP
->fr_symbol
))
3136 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3137 ++fragP
->fr_subtype
;
3140 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3141 fragP
->fr_var
= growth
;
3143 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3144 fragP
->fr_file
, fragP
->fr_line
, growth
);
3149 /* Translate internal representation of relocation info to BFD target
3153 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3157 bfd_reloc_code_real_type code
;
3159 reloc
= XNEW (arelent
);
3160 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3161 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3162 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3164 /* Make sure none of our internal relocations make it this far.
3165 They'd better have been fully resolved by this point. */
3166 gas_assert ((int) fixP
->fx_r_type
> 0);
3168 code
= fixP
->fx_r_type
;
3170 /* if we have something like add gp, pcl,
3171 _GLOBAL_OFFSET_TABLE_@gotpc. */
3172 if (code
== BFD_RELOC_ARC_GOTPC32
3174 && fixP
->fx_addsy
== GOT_symbol
)
3175 code
= BFD_RELOC_ARC_GOTPC
;
3177 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3178 if (reloc
->howto
== NULL
)
3180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3181 _("cannot represent `%s' relocation in object file"),
3182 bfd_get_reloc_code_name (code
));
3186 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3187 as_fatal (_("internal error? cannot generate `%s' relocation"),
3188 bfd_get_reloc_code_name (code
));
3190 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3192 reloc
->addend
= fixP
->fx_offset
;
3197 /* Perform post-processing of machine-dependent frags after relaxation.
3198 Called after relaxation is finished.
3199 In: Address of frag.
3200 fr_type == rs_machine_dependent.
3201 fr_subtype is what the address relaxed to.
3203 Out: Any fixS:s and constants are set up. */
3206 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3207 segT segment ATTRIBUTE_UNUSED
,
3210 const relax_typeS
*table_entry
;
3212 const struct arc_opcode
*opcode
;
3213 struct arc_insn insn
;
3215 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3217 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3218 dest
= fragP
->fr_literal
+ fix
;
3219 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3221 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3222 "var: %"BFD_VMA_FMT
"d\n",
3223 fragP
->fr_file
, fragP
->fr_line
,
3224 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3226 if (fragP
->fr_subtype
<= 0
3227 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3228 as_fatal (_("no relaxation found for this instruction."));
3230 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3232 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3233 relax_arg
->nflg
, &insn
);
3235 apply_fixups (&insn
, fragP
, fix
);
3237 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3238 gas_assert (table_entry
->rlx_length
== size
);
3239 emit_insn0 (&insn
, dest
, TRUE
);
3241 fragP
->fr_fix
+= table_entry
->rlx_length
;
3245 /* We have no need to default values of symbols. We could catch
3246 register names here, but that is handled by inserting them all in
3247 the symbol table to begin with. */
3250 md_undefined_symbol (char *name
)
3252 /* The arc abi demands that a GOT[0] should be referencible as
3253 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3254 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3256 && (*(name
+1) == 'G')
3257 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3259 && (*(name
+1) == 'D')
3260 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3264 if (symbol_find (name
))
3265 as_bad ("GOT already in symbol table");
3267 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3268 (valueT
) 0, &zero_address_frag
);
3275 /* Turn a string in input_line_pointer into a floating point constant
3276 of type type, and store the appropriate bytes in *litP. The number
3277 of LITTLENUMS emitted is stored in *sizeP. An error message is
3278 returned, or NULL on OK. */
3281 md_atof (int type
, char *litP
, int *sizeP
)
3283 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3286 /* Called for any expression that can not be recognized. When the
3287 function is called, `input_line_pointer' will point to the start of
3291 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3293 char *p
= input_line_pointer
;
3296 input_line_pointer
++;
3297 expressionP
->X_op
= O_symbol
;
3298 expression (expressionP
);
3302 /* This function is called from the function 'expression', it attempts
3303 to parse special names (in our case register names). It fills in
3304 the expression with the identified register. It returns TRUE if
3305 it is a register and FALSE otherwise. */
3308 arc_parse_name (const char *name
,
3309 struct expressionS
*e
)
3313 if (!assembling_insn
)
3316 if (e
->X_op
== O_symbol
)
3319 sym
= hash_find (arc_reg_hash
, name
);
3322 e
->X_op
= O_register
;
3323 e
->X_add_number
= S_GET_VALUE (sym
);
3327 sym
= hash_find (arc_addrtype_hash
, name
);
3330 e
->X_op
= O_addrtype
;
3331 e
->X_add_number
= S_GET_VALUE (sym
);
3339 Invocation line includes a switch not recognized by the base assembler.
3340 See if it's a processor-specific option.
3342 New options (supported) are:
3344 -mcpu=<cpu name> Assemble for selected processor
3345 -EB/-mbig-endian Big-endian
3346 -EL/-mlittle-endian Little-endian
3347 -mrelax Enable relaxation
3349 The following CPU names are recognized:
3350 arc600, arc700, arcem, archs, nps400. */
3353 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3359 return md_parse_option (OPTION_MCPU
, "arc600");
3362 return md_parse_option (OPTION_MCPU
, "arc700");
3365 return md_parse_option (OPTION_MCPU
, "arcem");
3368 return md_parse_option (OPTION_MCPU
, "archs");
3372 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3377 arc_target_format
= "elf32-bigarc";
3378 byte_order
= BIG_ENDIAN
;
3382 arc_target_format
= "elf32-littlearc";
3383 byte_order
= LITTLE_ENDIAN
;
3387 selected_cpu
.features
|= ARC_CD
;
3388 cl_features
|= ARC_CD
;
3389 arc_check_feature ();
3393 relaxation_state
= 1;
3397 selected_cpu
.features
|= ARC_NPS400
;
3398 cl_features
|= ARC_NPS400
;
3399 arc_check_feature ();
3403 selected_cpu
.features
|= ARC_SPFP
;
3404 cl_features
|= ARC_SPFP
;
3405 arc_check_feature ();
3409 selected_cpu
.features
|= ARC_DPFP
;
3410 cl_features
|= ARC_DPFP
;
3411 arc_check_feature ();
3415 selected_cpu
.features
|= ARC_FPUDA
;
3416 cl_features
|= ARC_FPUDA
;
3417 arc_check_feature ();
3420 /* Dummy options are accepted but have no effect. */
3421 case OPTION_USER_MODE
:
3422 case OPTION_LD_EXT_MASK
:
3425 case OPTION_BARREL_SHIFT
:
3426 case OPTION_MIN_MAX
:
3431 case OPTION_XMAC_D16
:
3432 case OPTION_XMAC_24
:
3433 case OPTION_DSP_PACKA
:
3436 case OPTION_TELEPHONY
:
3437 case OPTION_XYMEMORY
:
3450 /* Display the list of cpu names for use in the help text. */
3453 arc_show_cpu_list (FILE *stream
)
3456 static const char *space_buf
= " ";
3458 fprintf (stream
, "%s", space_buf
);
3459 offset
= strlen (space_buf
);
3460 for (i
= 0; cpu_types
[i
].name
!= NULL
; ++i
)
3462 bfd_boolean last
= (cpu_types
[i
+ 1].name
== NULL
);
3464 /* If displaying the new cpu name string, and the ', ' (for all
3465 but the last one) will take us past a target width of 80
3466 characters, then it's time for a new line. */
3467 if (offset
+ strlen (cpu_types
[i
].name
) + (last
? 0 : 2) > 80)
3469 fprintf (stream
, "\n%s", space_buf
);
3470 offset
= strlen (space_buf
);
3473 fprintf (stream
, "%s%s", cpu_types
[i
].name
, (last
? "\n" : ", "));
3474 offset
+= strlen (cpu_types
[i
].name
) + (last
? 0 : 2);
3479 md_show_usage (FILE *stream
)
3481 fprintf (stream
, _("ARC-specific assembler options:\n"));
3483 fprintf (stream
, " -mcpu=<cpu name>\t (default: %s), assemble for"
3484 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU
);
3485 arc_show_cpu_list (stream
);
3486 fprintf (stream
, "\n");
3487 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3488 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3489 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3490 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3492 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3493 fprintf (stream
, " -mspfp\t\t enable single-precision floating point"
3495 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point"
3497 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3498 "point\n\t\t\t instructions for ARC EM\n");
3501 " -mcode-density\t enable code density option for ARC EM\n");
3503 fprintf (stream
, _("\
3504 -EB assemble code for a big-endian cpu\n"));
3505 fprintf (stream
, _("\
3506 -EL assemble code for a little-endian cpu\n"));
3507 fprintf (stream
, _("\
3508 -mrelax enable relaxation\n"));
3510 fprintf (stream
, _("The following ARC-specific assembler options are "
3511 "deprecated and are accepted\nfor compatibility only:\n"));
3513 fprintf (stream
, _(" -mEA\n"
3514 " -mbarrel-shifter\n"
3515 " -mbarrel_shifter\n"
3520 " -mld-extension-reg-mask\n"
3536 " -muser-mode-only\n"
3540 /* Find the proper relocation for the given opcode. */
3542 static extended_bfd_reloc_code_real_type
3543 find_reloc (const char *name
,
3544 const char *opcodename
,
3545 const struct arc_flags
*pflags
,
3547 extended_bfd_reloc_code_real_type reloc
)
3551 bfd_boolean found_flag
, tmp
;
3552 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3554 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3556 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3558 /* Find the entry. */
3559 if (strcmp (name
, r
->name
))
3561 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3568 unsigned * psflg
= (unsigned *)r
->flags
;
3572 for (j
= 0; j
< nflg
; j
++)
3573 if (!strcmp (pflags
[j
].name
,
3574 arc_flag_operands
[*psflg
].name
))
3595 if (reloc
!= r
->oldreloc
)
3602 if (ret
== BFD_RELOC_UNUSED
)
3603 as_bad (_("Unable to find %s relocation for instruction %s"),
3608 /* All the symbol types that are allowed to be used for
3612 may_relax_expr (expressionS tok
)
3614 /* Check if we have unrelaxable relocs. */
3639 /* Checks if flags are in line with relaxable insn. */
3642 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3643 const struct arc_flags
*pflags
,
3646 unsigned flag_class
,
3651 const struct arc_flag_operand
*flag_opand
;
3652 int i
, counttrue
= 0;
3654 /* Iterate through flags classes. */
3655 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3657 /* Iterate through flags in flag class. */
3658 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3661 flag_opand
= &arc_flag_operands
[flag
];
3662 /* Iterate through flags in ins to compare. */
3663 for (i
= 0; i
< nflgs
; ++i
)
3665 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3676 /* If counttrue == nflgs, then all flags have been found. */
3677 return (counttrue
== nflgs
? TRUE
: FALSE
);
3680 /* Checks if operands are in line with relaxable insn. */
3683 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3684 const expressionS
*tok
,
3687 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3690 while (*operand
!= EMPTY
)
3692 const expressionS
*epr
= &tok
[i
];
3694 if (i
!= 0 && i
>= ntok
)
3700 if (!(epr
->X_op
== O_multiply
3701 || epr
->X_op
== O_divide
3702 || epr
->X_op
== O_modulus
3703 || epr
->X_op
== O_add
3704 || epr
->X_op
== O_subtract
3705 || epr
->X_op
== O_symbol
))
3711 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3715 if (epr
->X_op
!= O_register
)
3720 if (epr
->X_op
!= O_register
)
3723 switch (epr
->X_add_number
)
3725 case 0: case 1: case 2: case 3:
3726 case 12: case 13: case 14: case 15:
3733 case REGISTER_NO_GP
:
3734 if ((epr
->X_op
!= O_register
)
3735 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3740 if (epr
->X_op
!= O_bracket
)
3745 /* Don't understand, bail out. */
3751 operand
= &ins
->operands
[i
];
3754 return (i
== ntok
? TRUE
: FALSE
);
3757 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3760 relax_insn_p (const struct arc_opcode
*opcode
,
3761 const expressionS
*tok
,
3763 const struct arc_flags
*pflags
,
3767 bfd_boolean rv
= FALSE
;
3769 /* Check the relaxation table. */
3770 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3772 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3774 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3775 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3776 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3777 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3780 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3781 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3782 sizeof (expressionS
) * ntok
);
3783 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3784 sizeof (struct arc_flags
) * nflg
);
3785 frag_now
->tc_frag_data
.nflg
= nflg
;
3786 frag_now
->tc_frag_data
.ntok
= ntok
;
3794 /* Turn an opcode description and a set of arguments into
3795 an instruction and a fixup. */
3798 assemble_insn (const struct arc_opcode
*opcode
,
3799 const expressionS
*tok
,
3801 const struct arc_flags
*pflags
,
3803 struct arc_insn
*insn
)
3805 const expressionS
*reloc_exp
= NULL
;
3806 unsigned long long image
;
3807 const unsigned char *argidx
;
3810 unsigned char pcrel
= 0;
3811 bfd_boolean needGOTSymbol
;
3812 bfd_boolean has_delay_slot
= FALSE
;
3813 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3815 memset (insn
, 0, sizeof (*insn
));
3816 image
= opcode
->opcode
;
3818 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3819 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3822 /* Handle operands. */
3823 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3825 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3826 const expressionS
*t
= (const expressionS
*) 0;
3828 if (ARC_OPERAND_IS_FAKE (operand
))
3831 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3833 /* Duplicate operand, already inserted. */
3845 /* Regardless if we have a reloc or not mark the instruction
3846 limm if it is the case. */
3847 if (operand
->flags
& ARC_OPERAND_LIMM
)
3848 insn
->has_limm
= TRUE
;
3853 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3858 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3860 if (operand
->flags
& ARC_OPERAND_LIMM
)
3861 insn
->limm
= t
->X_add_number
;
3867 /* Ignore brackets, colons, and address types. */
3871 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3875 /* Maybe register range. */
3876 if ((t
->X_add_number
== 0)
3877 && contains_register (t
->X_add_symbol
)
3878 && contains_register (t
->X_op_symbol
))
3882 regs
= get_register (t
->X_add_symbol
);
3884 regs
|= get_register (t
->X_op_symbol
);
3885 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3891 /* This operand needs a relocation. */
3892 needGOTSymbol
= FALSE
;
3897 if (opcode
->insn_class
== JUMP
)
3898 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3899 _("Unable to use @plt relocation for insn %s"),
3901 needGOTSymbol
= TRUE
;
3902 reloc
= find_reloc ("plt", opcode
->name
,
3904 operand
->default_reloc
);
3909 needGOTSymbol
= TRUE
;
3910 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3913 if (operand
->flags
& ARC_OPERAND_LIMM
)
3915 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3916 if (arc_opcode_len (opcode
) == 2
3917 || opcode
->insn_class
== JUMP
)
3918 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3919 _("Unable to use @pcl relocation for insn %s"),
3924 /* This is a relaxed operand which initially was
3925 limm, choose whatever we have defined in the
3927 reloc
= operand
->default_reloc
;
3931 reloc
= find_reloc ("sda", opcode
->name
,
3933 operand
->default_reloc
);
3937 needGOTSymbol
= TRUE
;
3942 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3945 case O_tpoff9
: /*FIXME! Check for the conditionality of
3947 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3949 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3953 /* Just consider the default relocation. */
3954 reloc
= operand
->default_reloc
;
3958 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3959 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3966 /* sanity checks. */
3967 reloc_howto_type
*reloc_howto
3968 = bfd_reloc_type_lookup (stdoutput
,
3969 (bfd_reloc_code_real_type
) reloc
);
3970 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3971 if (reloc_howto
->rightshift
)
3972 reloc_bitsize
-= reloc_howto
->rightshift
;
3973 if (reloc_bitsize
!= operand
->bits
)
3975 as_bad (_("invalid relocation %s for field"),
3976 bfd_get_reloc_code_name (reloc
));
3981 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3982 as_fatal (_("too many fixups"));
3984 struct arc_fixup
*fixup
;
3985 fixup
= &insn
->fixups
[insn
->nfixups
++];
3987 fixup
->reloc
= reloc
;
3988 if ((int) reloc
< 0)
3989 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3992 reloc_howto_type
*reloc_howto
=
3993 bfd_reloc_type_lookup (stdoutput
,
3994 (bfd_reloc_code_real_type
) fixup
->reloc
);
3995 pcrel
= reloc_howto
->pc_relative
;
3997 fixup
->pcrel
= pcrel
;
3998 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
4005 for (i
= 0; i
< nflg
; i
++)
4007 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
4009 /* Check if the instruction has a delay slot. */
4010 if (!strcmp (flg_operand
->name
, "d"))
4011 has_delay_slot
= TRUE
;
4013 /* There is an exceptional case when we cannot insert a flag just as
4014 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4015 relation with the relative address. Unfortunately, some of the
4016 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4017 handled in the normal way.
4019 Flag operands don't have an architecture field, so we can't
4020 directly validate that FLAG_OPERAND is valid for the current
4021 architecture, what we do instead is just validate that we're
4022 assembling for an ARCv2 architecture. */
4023 if ((selected_cpu
.flags
& ARC_OPCODE_ARCV2
)
4024 && (!strcmp (flg_operand
->name
, "t")
4025 || !strcmp (flg_operand
->name
, "nt")))
4027 unsigned bitYoperand
= 0;
4028 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4029 if (!strcmp (flg_operand
->name
, "t"))
4030 if (!strcmp (opcode
->name
, "bbit0")
4031 || !strcmp (opcode
->name
, "bbit1"))
4032 bitYoperand
= arc_NToperand
;
4034 bitYoperand
= arc_Toperand
;
4036 if (!strcmp (opcode
->name
, "bbit0")
4037 || !strcmp (opcode
->name
, "bbit1"))
4038 bitYoperand
= arc_Toperand
;
4040 bitYoperand
= arc_NToperand
;
4042 gas_assert (reloc_exp
!= NULL
);
4043 if (reloc_exp
->X_op
== O_constant
)
4045 /* Check if we have a constant and solved it
4047 offsetT val
= reloc_exp
->X_add_number
;
4048 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4053 struct arc_fixup
*fixup
;
4055 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4056 as_fatal (_("too many fixups"));
4058 fixup
= &insn
->fixups
[insn
->nfixups
++];
4059 fixup
->exp
= *reloc_exp
;
4060 fixup
->reloc
= -bitYoperand
;
4061 fixup
->pcrel
= pcrel
;
4062 fixup
->islong
= FALSE
;
4066 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4067 << flg_operand
->shift
;
4070 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4072 /* Instruction length. */
4073 insn
->len
= arc_opcode_len (opcode
);
4077 /* Update last insn status. */
4078 arc_last_insns
[1] = arc_last_insns
[0];
4079 arc_last_insns
[0].opcode
= opcode
;
4080 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4081 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4083 /* Check if the current instruction is legally used. */
4084 if (arc_last_insns
[1].has_delay_slot
4085 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4086 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4087 _("A jump/branch instruction in delay slot."));
4091 arc_handle_align (fragS
* fragP
)
4093 if ((fragP
)->fr_type
== rs_align_code
)
4095 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4096 valueT count
= ((fragP
)->fr_next
->fr_address
4097 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4099 (fragP
)->fr_var
= 2;
4101 if (count
& 1)/* Padding in the gap till the next 2-byte
4102 boundary with 0s. */
4107 /* Writing nop_s. */
4108 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4112 /* Here we decide which fixups can be adjusted to make them relative
4113 to the beginning of the section instead of the symbol. Basically
4114 we need to make sure that the dynamic relocations are done
4115 correctly, so in some cases we force the original symbol to be
4119 tc_arc_fix_adjustable (fixS
*fixP
)
4122 /* Prevent all adjustments to global symbols. */
4123 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4125 if (S_IS_WEAK (fixP
->fx_addsy
))
4128 /* Adjust_reloc_syms doesn't know about the GOT. */
4129 switch (fixP
->fx_r_type
)
4131 case BFD_RELOC_ARC_GOTPC32
:
4132 case BFD_RELOC_ARC_PLT32
:
4133 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4134 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4135 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4136 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4146 /* Compute the reloc type of an expression EXP. */
4149 arc_check_reloc (expressionS
*exp
,
4150 bfd_reloc_code_real_type
*r_type_p
)
4152 if (*r_type_p
== BFD_RELOC_32
4153 && exp
->X_op
== O_subtract
4154 && exp
->X_op_symbol
!= NULL
4155 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4156 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4160 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4163 arc_cons_fix_new (fragS
*frag
,
4167 bfd_reloc_code_real_type r_type
)
4169 r_type
= BFD_RELOC_UNUSED
;
4174 r_type
= BFD_RELOC_8
;
4178 r_type
= BFD_RELOC_16
;
4182 r_type
= BFD_RELOC_24
;
4186 r_type
= BFD_RELOC_32
;
4187 arc_check_reloc (exp
, &r_type
);
4191 r_type
= BFD_RELOC_64
;
4195 as_bad (_("unsupported BFD relocation size %u"), size
);
4196 r_type
= BFD_RELOC_UNUSED
;
4199 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4202 /* The actual routine that checks the ZOL conditions. */
4205 check_zol (symbolS
*s
)
4207 switch (selected_cpu
.mach
)
4209 case bfd_mach_arc_arcv2
:
4210 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4213 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4214 || arc_last_insns
[1].has_delay_slot
)
4215 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4219 case bfd_mach_arc_arc600
:
4221 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4222 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4225 if (arc_last_insns
[0].has_limm
4226 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4227 as_bad (_("A jump instruction with long immediate detected at the \
4228 end of the ZOL label @%s"), S_GET_NAME (s
));
4231 case bfd_mach_arc_arc700
:
4232 if (arc_last_insns
[0].has_delay_slot
)
4233 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4242 /* If ZOL end check the last two instruction for illegals. */
4244 arc_frob_label (symbolS
* sym
)
4246 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4249 dwarf2_emit_label (sym
);
4252 /* Used because generic relaxation assumes a pc-rel value whilst we
4253 also relax instructions that use an absolute value resolved out of
4254 relative values (if that makes any sense). An example: 'add r1,
4255 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4256 but if they're in the same section we can subtract the section
4257 offset relocation which ends up in a resolved value. So if @.L2 is
4258 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4259 .text + 0x40 = 0x10. */
4261 arc_pcrel_adjust (fragS
*fragP
)
4263 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4264 fragP
->fr_address
, fragP
->fr_fix
,
4265 fragP
->tc_frag_data
.pcrel
? "Y" : "N");
4267 if (!fragP
->tc_frag_data
.pcrel
)
4268 return fragP
->fr_address
+ fragP
->fr_fix
;
4270 /* Take into account the PCL rounding. */
4271 return (fragP
->fr_address
+ fragP
->fr_fix
) & 0x03;
4274 /* Initialize the DWARF-2 unwind information for this procedure. */
4277 tc_arc_frame_initial_instructions (void)
4279 /* Stack pointer is register 28. */
4280 cfi_add_CFA_def_cfa (28, 0);
4284 tc_arc_regname_to_dw2regnum (char *regname
)
4288 sym
= hash_find (arc_reg_hash
, regname
);
4290 return S_GET_VALUE (sym
);
4295 /* Adjust the symbol table. Delete found AUX register symbols. */
4298 arc_adjust_symtab (void)
4302 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4304 /* I've created a symbol during parsing process. Now, remove
4305 the symbol as it is found to be an AUX register. */
4306 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4307 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4310 /* Now do generic ELF adjustments. */
4311 elf_adjust_symtab ();
4315 tokenize_extinsn (extInstruction_t
*einsn
)
4319 unsigned char major_opcode
;
4320 unsigned char sub_opcode
;
4321 unsigned char syntax_class
= 0;
4322 unsigned char syntax_class_modifiers
= 0;
4323 unsigned char suffix_class
= 0;
4328 /* 1st: get instruction name. */
4329 p
= input_line_pointer
;
4330 c
= get_symbol_name (&p
);
4332 insn_name
= xstrdup (p
);
4333 restore_line_pointer (c
);
4335 /* 2nd: get major opcode. */
4336 if (*input_line_pointer
!= ',')
4338 as_bad (_("expected comma after instruction name"));
4339 ignore_rest_of_line ();
4342 input_line_pointer
++;
4343 major_opcode
= get_absolute_expression ();
4345 /* 3rd: get sub-opcode. */
4348 if (*input_line_pointer
!= ',')
4350 as_bad (_("expected comma after major opcode"));
4351 ignore_rest_of_line ();
4354 input_line_pointer
++;
4355 sub_opcode
= get_absolute_expression ();
4357 /* 4th: get suffix class. */
4360 if (*input_line_pointer
!= ',')
4362 as_bad ("expected comma after sub opcode");
4363 ignore_rest_of_line ();
4366 input_line_pointer
++;
4372 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4374 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4375 suffixclass
[i
].len
))
4377 suffix_class
|= suffixclass
[i
].attr_class
;
4378 input_line_pointer
+= suffixclass
[i
].len
;
4383 if (i
== ARRAY_SIZE (suffixclass
))
4385 as_bad ("invalid suffix class");
4386 ignore_rest_of_line ();
4392 if (*input_line_pointer
== '|')
4393 input_line_pointer
++;
4398 /* 5th: get syntax class and syntax class modifiers. */
4399 if (*input_line_pointer
!= ',')
4401 as_bad ("expected comma after suffix class");
4402 ignore_rest_of_line ();
4405 input_line_pointer
++;
4411 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4413 if (!strncmp (syntaxclassmod
[i
].name
,
4415 syntaxclassmod
[i
].len
))
4417 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4418 input_line_pointer
+= syntaxclassmod
[i
].len
;
4423 if (i
== ARRAY_SIZE (syntaxclassmod
))
4425 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4427 if (!strncmp (syntaxclass
[i
].name
,
4429 syntaxclass
[i
].len
))
4431 syntax_class
|= syntaxclass
[i
].attr_class
;
4432 input_line_pointer
+= syntaxclass
[i
].len
;
4437 if (i
== ARRAY_SIZE (syntaxclass
))
4439 as_bad ("missing syntax class");
4440 ignore_rest_of_line ();
4447 if (*input_line_pointer
== '|')
4448 input_line_pointer
++;
4453 demand_empty_rest_of_line ();
4455 einsn
->name
= insn_name
;
4456 einsn
->major
= major_opcode
;
4457 einsn
->minor
= sub_opcode
;
4458 einsn
->syntax
= syntax_class
;
4459 einsn
->modsyn
= syntax_class_modifiers
;
4460 einsn
->suffix
= suffix_class
;
4461 einsn
->flags
= syntax_class
4462 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4465 /* Generate an extension section. */
4468 arc_set_ext_seg (void)
4470 if (!arcext_section
)
4472 arcext_section
= subseg_new (".arcextmap", 0);
4473 bfd_set_section_flags (stdoutput
, arcext_section
,
4474 SEC_READONLY
| SEC_HAS_CONTENTS
);
4477 subseg_set (arcext_section
, 0);
4481 /* Create an extension instruction description in the arc extension
4482 section of the output file.
4483 The structure for an instruction is like this:
4484 [0]: Length of the record.
4485 [1]: Type of the record.
4489 [4]: Syntax (flags).
4490 [5]+ Name instruction.
4492 The sequence is terminated by an empty entry. */
4495 create_extinst_section (extInstruction_t
*einsn
)
4498 segT old_sec
= now_seg
;
4499 int old_subsec
= now_subseg
;
4501 int name_len
= strlen (einsn
->name
);
4506 *p
= 5 + name_len
+ 1;
4508 *p
= EXT_INSTRUCTION
;
4515 p
= frag_more (name_len
+ 1);
4516 strcpy (p
, einsn
->name
);
4518 subseg_set (old_sec
, old_subsec
);
4521 /* Handler .extinstruction pseudo-op. */
4524 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4526 extInstruction_t einsn
;
4527 struct arc_opcode
*arc_ext_opcodes
;
4528 const char *errmsg
= NULL
;
4529 unsigned char moplow
, mophigh
;
4531 memset (&einsn
, 0, sizeof (einsn
));
4532 tokenize_extinsn (&einsn
);
4534 /* Check if the name is already used. */
4535 if (arc_find_opcode (einsn
.name
))
4536 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4538 /* Check the opcode ranges. */
4540 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4541 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4543 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4544 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4546 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4547 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4548 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4550 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4552 case ARC_SYNTAX_3OP
:
4553 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4554 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4556 case ARC_SYNTAX_2OP
:
4557 case ARC_SYNTAX_1OP
:
4558 case ARC_SYNTAX_NOP
:
4559 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4560 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4566 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4567 if (arc_ext_opcodes
== NULL
)
4570 as_fatal ("%s", errmsg
);
4572 as_fatal (_("Couldn't generate extension instruction opcodes"));
4575 as_warn ("%s", errmsg
);
4577 /* Insert the extension instruction. */
4578 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4580 create_extinst_section (&einsn
);
4584 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4590 int number
, imode
= 0;
4591 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4592 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4593 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4595 /* 1st: get register name. */
4597 p
= input_line_pointer
;
4598 c
= get_symbol_name (&p
);
4601 restore_line_pointer (c
);
4603 /* 2nd: get register number. */
4606 if (*input_line_pointer
!= ',')
4608 as_bad (_("expected comma after name"));
4609 ignore_rest_of_line ();
4613 input_line_pointer
++;
4614 number
= get_absolute_expression ();
4617 && (opertype
!= EXT_AUX_REGISTER
))
4619 as_bad (_("%s second argument cannot be a negative number %d"),
4620 isCore_p
? "extCoreRegister's" : "extCondCode's",
4622 ignore_rest_of_line ();
4629 /* 3rd: get register mode. */
4632 if (*input_line_pointer
!= ',')
4634 as_bad (_("expected comma after register number"));
4635 ignore_rest_of_line ();
4640 input_line_pointer
++;
4641 mode
= input_line_pointer
;
4643 if (!strncmp (mode
, "r|w", 3))
4646 input_line_pointer
+= 3;
4648 else if (!strncmp (mode
, "r", 1))
4650 imode
= ARC_REGISTER_READONLY
;
4651 input_line_pointer
+= 1;
4653 else if (strncmp (mode
, "w", 1))
4655 as_bad (_("invalid mode"));
4656 ignore_rest_of_line ();
4662 imode
= ARC_REGISTER_WRITEONLY
;
4663 input_line_pointer
+= 1;
4669 /* 4th: get core register shortcut. */
4671 if (*input_line_pointer
!= ',')
4673 as_bad (_("expected comma after register mode"));
4674 ignore_rest_of_line ();
4679 input_line_pointer
++;
4681 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4683 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4684 input_line_pointer
+= 15;
4686 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4688 as_bad (_("shortcut designator invalid"));
4689 ignore_rest_of_line ();
4695 input_line_pointer
+= 12;
4698 demand_empty_rest_of_line ();
4701 ereg
->number
= number
;
4702 ereg
->imode
= imode
;
4706 /* Create an extension register/condition description in the arc
4707 extension section of the output file.
4709 The structure for an instruction is like this:
4710 [0]: Length of the record.
4711 [1]: Type of the record.
4713 For core regs and condition codes:
4717 For auxiliary registers:
4721 The sequence is terminated by an empty entry. */
4724 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4726 segT old_sec
= now_seg
;
4727 int old_subsec
= now_subseg
;
4729 int name_len
= strlen (ereg
->name
);
4736 case EXT_CORE_REGISTER
:
4738 *p
= 3 + name_len
+ 1;
4744 case EXT_AUX_REGISTER
:
4746 *p
= 6 + name_len
+ 1;
4748 *p
= EXT_AUX_REGISTER
;
4750 *p
= (ereg
->number
>> 24) & 0xff;
4752 *p
= (ereg
->number
>> 16) & 0xff;
4754 *p
= (ereg
->number
>> 8) & 0xff;
4756 *p
= (ereg
->number
) & 0xff;
4762 p
= frag_more (name_len
+ 1);
4763 strcpy (p
, ereg
->name
);
4765 subseg_set (old_sec
, old_subsec
);
4768 /* Handler .extCoreRegister pseudo-op. */
4771 arc_extcorereg (int opertype
)
4774 struct arc_aux_reg
*auxr
;
4776 struct arc_flag_operand
*ccode
;
4778 memset (&ereg
, 0, sizeof (ereg
));
4779 if (!tokenize_extregister (&ereg
, opertype
))
4784 case EXT_CORE_REGISTER
:
4785 /* Core register. */
4786 if (ereg
.number
> 60)
4787 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4789 declare_register (ereg
.name
, ereg
.number
);
4791 case EXT_AUX_REGISTER
:
4792 /* Auxiliary register. */
4793 auxr
= XNEW (struct arc_aux_reg
);
4794 auxr
->name
= ereg
.name
;
4795 auxr
->cpu
= selected_cpu
.flags
;
4796 auxr
->subclass
= NONE
;
4797 auxr
->address
= ereg
.number
;
4798 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4800 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4801 auxr
->name
, retval
);
4804 /* Condition code. */
4805 if (ereg
.number
> 31)
4806 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4808 ext_condcode
.size
++;
4809 ext_condcode
.arc_ext_condcode
=
4810 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4811 ext_condcode
.size
+ 1);
4812 if (ext_condcode
.arc_ext_condcode
== NULL
)
4813 as_fatal (_("Virtual memory exhausted"));
4815 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4816 ccode
->name
= ereg
.name
;
4817 ccode
->code
= ereg
.number
;
4820 ccode
->favail
= 0; /* not used. */
4822 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4825 as_bad (_("Unknown extension"));
4828 create_extcore_section (&ereg
, opertype
);
4832 eval: (c-set-style "gnu")