1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
49 (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 /* Enum used to enumerate the relaxable ins operands. */
59 REGISTER_S
, /* Register for short instruction(s). */
60 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
61 REGISTER_DUP
, /* Duplication of previous operand of type register. */
95 #define regno(x) ((x) & 0x3F)
96 #define is_ir_num(x) (((x) & ~0x3F) == 0)
97 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
98 #define is_spfp_p(op) (((sc) == SPX))
99 #define is_dpfp_p(op) (((sc) == DPX))
100 #define is_fpuda_p(op) (((sc) == DPA))
101 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
102 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
104 /* Generic assembler global variables which must be defined by all
107 /* Characters which always start a comment. */
108 const char comment_chars
[] = "#;";
110 /* Characters which start a comment at the beginning of a line. */
111 const char line_comment_chars
[] = "#";
113 /* Characters which may be used to separate multiple commands on a
115 const char line_separator_chars
[] = "`";
117 /* Characters which are used to indicate an exponent in a floating
119 const char EXP_CHARS
[] = "eE";
121 /* Chars that mean this number is a floating point constant
122 As in 0f12.456 or 0d1.2345e12. */
123 const char FLT_CHARS
[] = "rRsSfFdD";
126 extern int target_big_endian
;
127 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
128 static int byte_order
= DEFAULT_BYTE_ORDER
;
130 /* Arc extension section. */
131 static segT arcext_section
;
133 /* By default relaxation is disabled. */
134 static int relaxation_state
= 0;
136 extern int arc_get_mach (char *);
138 /* Forward declarations. */
139 static void arc_lcomm (int);
140 static void arc_option (int);
141 static void arc_extra_reloc (int);
142 static void arc_extinsn (int);
143 static void arc_extcorereg (int);
145 const pseudo_typeS md_pseudo_table
[] =
147 /* Make sure that .word is 32 bits. */
150 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
151 { "lcomm", arc_lcomm
, 0 },
152 { "lcommon", arc_lcomm
, 0 },
153 { "cpu", arc_option
, 0 },
155 { "extinstruction", arc_extinsn
, 0 },
156 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
157 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
158 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
160 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
161 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
166 const char *md_shortopts
= "";
170 OPTION_EB
= OPTION_MD_BASE
,
183 /* The following options are deprecated and provided here only for
184 compatibility reasons. */
210 struct option md_longopts
[] =
212 { "EB", no_argument
, NULL
, OPTION_EB
},
213 { "EL", no_argument
, NULL
, OPTION_EL
},
214 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
215 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
216 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
217 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
218 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
219 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
220 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
221 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
222 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
223 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
225 /* The following options are deprecated and provided here only for
226 compatibility reasons. */
227 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
228 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
229 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
230 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
231 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
232 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
233 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
234 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
235 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
236 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
237 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
238 { "mea", no_argument
, NULL
, OPTION_EA
},
239 { "mEA", no_argument
, NULL
, OPTION_EA
},
240 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
241 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
242 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
243 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
244 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
245 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
246 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
247 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
248 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
249 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
250 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
251 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
252 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
253 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
254 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
255 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
256 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
257 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
258 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
259 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
260 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
261 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
262 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
263 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
264 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
265 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
267 { NULL
, no_argument
, NULL
, 0 }
270 size_t md_longopts_size
= sizeof (md_longopts
);
272 /* Local data and data types. */
274 /* Used since new relocation types are introduced in this
275 file (DUMMY_RELOC_LITUSE_*). */
276 typedef int extended_bfd_reloc_code_real_type
;
282 extended_bfd_reloc_code_real_type reloc
;
284 /* index into arc_operands. */
285 unsigned int opindex
;
287 /* PC-relative, used by internals fixups. */
290 /* TRUE if this fixup is for LIMM operand. */
298 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
300 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
302 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
304 bfd_boolean relax
; /* Boolean value: TRUE if needs
308 /* Structure to hold any last two instructions. */
309 static struct arc_last_insn
311 /* Saved instruction opcode. */
312 const struct arc_opcode
*opcode
;
314 /* Boolean value: TRUE if current insn is short. */
315 bfd_boolean has_limm
;
317 /* Boolean value: TRUE if current insn has delay slot. */
318 bfd_boolean has_delay_slot
;
321 /* Extension instruction suffix classes. */
329 static const attributes_t suffixclass
[] =
331 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
332 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
333 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
336 /* Extension instruction syntax classes. */
337 static const attributes_t syntaxclass
[] =
339 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
340 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
341 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
342 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
345 /* Extension instruction syntax classes modifiers. */
346 static const attributes_t syntaxclassmod
[] =
348 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
349 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
352 /* Extension register type. */
360 /* A structure to hold the additional conditional codes. */
363 struct arc_flag_operand
*arc_ext_condcode
;
365 } ext_condcode
= { NULL
, 0 };
367 /* Structure to hold an entry in ARC_OPCODE_HASH. */
368 struct arc_opcode_hash_entry
370 /* The number of pointers in the OPCODE list. */
373 /* Points to a list of opcode pointers. */
374 const struct arc_opcode
**opcode
;
377 /* Structure used for iterating through an arc_opcode_hash_entry. */
378 struct arc_opcode_hash_entry_iterator
380 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
383 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
384 returned by this iterator. */
385 const struct arc_opcode
*opcode
;
388 /* Forward declaration. */
389 static void assemble_insn
390 (const struct arc_opcode
*, const expressionS
*, int,
391 const struct arc_flags
*, int, struct arc_insn
*);
393 /* The cpu for which we are generating code. */
394 static unsigned arc_target
;
395 static const char *arc_target_name
;
396 static unsigned arc_features
;
398 /* The default architecture. */
399 static int arc_mach_type
;
401 /* TRUE if the cpu type has been explicitly specified. */
402 static bfd_boolean mach_type_specified_p
= FALSE
;
404 /* The hash table of instruction opcodes. */
405 static struct hash_control
*arc_opcode_hash
;
407 /* The hash table of register symbols. */
408 static struct hash_control
*arc_reg_hash
;
410 /* The hash table of aux register symbols. */
411 static struct hash_control
*arc_aux_hash
;
413 /* A table of CPU names and opcode sets. */
414 static const struct cpu_type
424 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
425 E_ARC_MACH_ARC600
, 0x00},
426 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
427 E_ARC_MACH_ARC700
, 0x00},
428 { "nps400", ARC_OPCODE_ARC700
| ARC_OPCODE_NPS400
, bfd_mach_arc_nps400
,
429 E_ARC_MACH_NPS400
, 0x00},
430 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
431 EF_ARC_CPU_ARCV2EM
, ARC_CD
},
432 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
433 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
437 /* Used by the arc_reloc_op table. Order is important. */
438 #define O_gotoff O_md1 /* @gotoff relocation. */
439 #define O_gotpc O_md2 /* @gotpc relocation. */
440 #define O_plt O_md3 /* @plt relocation. */
441 #define O_sda O_md4 /* @sda relocation. */
442 #define O_pcl O_md5 /* @pcl relocation. */
443 #define O_tlsgd O_md6 /* @tlsgd relocation. */
444 #define O_tlsie O_md7 /* @tlsie relocation. */
445 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
446 #define O_tpoff O_md9 /* @tpoff relocation. */
447 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
448 #define O_dtpoff O_md11 /* @dtpoff relocation. */
449 #define O_last O_dtpoff
451 /* Used to define a bracket as operand in tokens. */
452 #define O_bracket O_md32
454 /* Dummy relocation, to be sorted out. */
455 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
457 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
459 /* A table to map the spelling of a relocation operand into an appropriate
460 bfd_reloc_code_real_type type. The table is assumed to be ordered such
461 that op-O_literal indexes into it. */
462 #define ARC_RELOC_TABLE(op) \
463 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
465 : (int) (op) - (int) O_gotoff) ])
467 #define DEF(NAME, RELOC, REQ) \
468 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
470 static const struct arc_reloc_op_tag
472 /* String to lookup. */
474 /* Size of the string. */
476 /* Which operator to use. */
478 extended_bfd_reloc_code_real_type reloc
;
479 /* Allows complex relocation expression like identifier@reloc +
481 unsigned int complex_expr
: 1;
485 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
486 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
487 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
488 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
489 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
490 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
491 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
492 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
493 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
494 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
495 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 0),
498 static const int arc_num_reloc_op
499 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
501 /* Structure for relaxable instruction that have to be swapped with a
502 smaller alternative instruction. */
503 struct arc_relaxable_ins
505 /* Mnemonic that should be checked. */
506 const char *mnemonic_r
;
508 /* Operands that should be checked.
509 Indexes of operands from operand array. */
510 enum rlx_operand_type operands
[6];
512 /* Flags that should be checked. */
513 unsigned flag_classes
[5];
515 /* Mnemonic (smaller) alternative to be used later for relaxation. */
516 const char *mnemonic_alt
;
518 /* Index of operand that generic relaxation has to check. */
521 /* Base subtype index used. */
522 enum arc_rlx_types subtype
;
525 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
526 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
527 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
531 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
532 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
533 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
538 /* ARC relaxation table. */
539 const relax_typeS md_relax_table
[] =
546 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL
),
547 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
551 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B
),
552 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
557 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6
),
558 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM
),
559 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
561 /* LD_S a, [b, u7] ->
562 LD<zz><.x><.aa><.di> a, [b, s9] ->
563 LD<zz><.x><.aa><.di> a, [b, limm] */
564 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9
),
565 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM
),
566 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE
),
571 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12
),
572 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM
),
573 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
577 SUB<.f> a, b, limm. */
578 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6
),
579 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM
),
580 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
582 /* MPY<.f> a, b, u6 ->
583 MPY<.f> a, b, limm. */
584 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM
),
585 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
587 /* MOV<.f><.cc> b, u6 ->
588 MOV<.f><.cc> b, limm. */
589 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM
),
590 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
592 /* ADD<.f><.cc> b, b, u6 ->
593 ADD<.f><.cc> b, b, limm. */
594 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM
),
595 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
598 /* Order of this table's entries matters! */
599 const struct arc_relaxable_ins arc_relaxable_insns
[] =
601 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
602 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
603 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
604 2, ARC_RLX_ADD_RRU6
},
605 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
607 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
609 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
610 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
611 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
612 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
613 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
614 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
615 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
616 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
618 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
620 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
624 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
626 /* Flags to set in the elf header. */
627 static flagword arc_eflag
= 0x00;
629 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
630 symbolS
* GOT_symbol
= 0;
632 /* Set to TRUE when we assemble instructions. */
633 static bfd_boolean assembling_insn
= FALSE
;
635 /* Functions implementation. */
637 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
638 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
639 are no matching entries in ARC_OPCODE_HASH. */
641 static const struct arc_opcode_hash_entry
*
642 arc_find_opcode (const char *name
)
644 const struct arc_opcode_hash_entry
*entry
;
646 entry
= hash_find (arc_opcode_hash
, name
);
650 /* Initialise the iterator ITER. */
653 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
659 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
660 calls to this function. Return NULL when all ARC_OPCODE entries have
663 static const struct arc_opcode
*
664 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
665 struct arc_opcode_hash_entry_iterator
*iter
)
667 if (iter
->opcode
== NULL
&& iter
->index
== 0)
669 gas_assert (entry
->count
> 0);
670 iter
->opcode
= entry
->opcode
[iter
->index
];
672 else if (iter
->opcode
!= NULL
)
674 const char *old_name
= iter
->opcode
->name
;
677 if (iter
->opcode
->name
678 && (strcmp (old_name
, iter
->opcode
->name
) != 0))
681 if (iter
->index
== entry
->count
)
684 iter
->opcode
= entry
->opcode
[iter
->index
];
691 /* Insert an opcode into opcode hash structure. */
694 arc_insert_opcode (const struct arc_opcode
*opcode
)
696 const char *name
, *retval
;
697 struct arc_opcode_hash_entry
*entry
;
700 entry
= hash_find (arc_opcode_hash
, name
);
703 entry
= XNEW (struct arc_opcode_hash_entry
);
705 entry
->opcode
= NULL
;
707 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
709 as_fatal (_("internal error: can't hash opcode '%s': %s"),
713 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
716 if (entry
->opcode
== NULL
)
717 as_fatal (_("Virtual memory exhausted"));
719 entry
->opcode
[entry
->count
] = opcode
;
724 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
725 is encoded as 'middle-endian' for a little-endian target. FIXME!
726 this function is used for regular 4 byte instructions as well. */
729 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
733 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
734 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
738 md_number_to_chars (buf
, val
, n
);
742 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
743 the relevant static global variables. */
746 arc_select_cpu (const char *arg
)
751 for (i
= 0; cpu_types
[i
].name
; ++i
)
753 if (!strcasecmp (cpu_types
[i
].name
, arg
))
755 arc_target
= cpu_types
[i
].flags
;
756 arc_target_name
= cpu_types
[i
].name
;
757 arc_features
= cpu_types
[i
].features
;
758 arc_mach_type
= cpu_types
[i
].mach
;
759 cpu_flags
= cpu_types
[i
].eflags
;
764 if (!cpu_types
[i
].name
)
765 as_fatal (_("unknown architecture: %s\n"), arg
);
766 gas_assert (cpu_flags
!= 0);
767 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
770 /* Here ends all the ARCompact extension instruction assembling
774 arc_extra_reloc (int r_type
)
777 symbolS
*sym
, *lab
= NULL
;
779 if (*input_line_pointer
== '@')
780 input_line_pointer
++;
781 c
= get_symbol_name (&sym_name
);
782 sym
= symbol_find_or_make (sym_name
);
783 restore_line_pointer (c
);
784 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
786 ++input_line_pointer
;
788 c
= get_symbol_name (&lab_name
);
789 lab
= symbol_find_or_make (lab_name
);
790 restore_line_pointer (c
);
793 /* These relocations exist as a mechanism for the compiler to tell the
794 linker how to patch the code if the tls model is optimised. However,
795 the relocation itself does not require any space within the assembler
796 fragment, and so we pass a size of 0.
798 The lines that generate these relocations look like this:
800 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
802 The '.tls_gd_ld @.tdata' is processed first and generates the
803 additional relocation, while the 'bl __tls_get_addr@plt' is processed
804 second and generates the additional branch.
806 It is possible that the additional relocation generated by the
807 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
808 while the 'bl __tls_get_addr@plt' will be generated as the first thing
809 in the next fragment. This will be fine; both relocations will still
810 appear to be at the same address in the generated object file.
811 However, this only works as the additional relocation is generated
812 with size of 0 bytes. */
814 = fix_new (frag_now
, /* Which frag? */
815 frag_now_fix (), /* Where in that frag? */
816 0, /* size: 1, 2, or 4 usually. */
817 sym
, /* X_add_symbol. */
818 0, /* X_add_number. */
819 FALSE
, /* TRUE if PC-relative relocation. */
820 r_type
/* Relocation type. */);
821 fixP
->fx_subsy
= lab
;
825 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
826 symbolS
*symbolP
, addressT size
)
831 if (*input_line_pointer
== ',')
833 align
= parse_align (1);
835 if (align
== (addressT
) -1)
850 bss_alloc (symbolP
, size
, align
);
851 S_CLEAR_EXTERNAL (symbolP
);
857 arc_lcomm (int ignore
)
859 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
862 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
865 /* Select the cpu we're assembling for. */
868 arc_option (int ignore ATTRIBUTE_UNUSED
)
874 c
= get_symbol_name (&cpu
);
875 mach
= arc_get_mach (cpu
);
880 if (!mach_type_specified_p
)
882 if ((!strcmp ("ARC600", cpu
))
883 || (!strcmp ("ARC601", cpu
))
884 || (!strcmp ("A6", cpu
)))
886 md_parse_option (OPTION_MCPU
, "arc600");
888 else if ((!strcmp ("ARC700", cpu
))
889 || (!strcmp ("A7", cpu
)))
891 md_parse_option (OPTION_MCPU
, "arc700");
893 else if (!strcmp ("EM", cpu
))
895 md_parse_option (OPTION_MCPU
, "arcem");
897 else if (!strcmp ("HS", cpu
))
899 md_parse_option (OPTION_MCPU
, "archs");
901 else if (!strcmp ("NPS400", cpu
))
903 md_parse_option (OPTION_MCPU
, "nps400");
906 as_fatal (_("could not find the architecture"));
908 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
909 as_fatal (_("could not set architecture and machine"));
911 /* Set elf header flags. */
912 bfd_set_private_flags (stdoutput
, arc_eflag
);
915 if (arc_mach_type
!= mach
)
916 as_warn (_("Command-line value overrides \".cpu\" directive"));
918 restore_line_pointer (c
);
919 demand_empty_rest_of_line ();
923 restore_line_pointer (c
);
924 as_bad (_("invalid identifier for \".cpu\""));
925 ignore_rest_of_line ();
928 /* Smartly print an expression. */
931 debug_exp (expressionS
*t
)
933 const char *name ATTRIBUTE_UNUSED
;
934 const char *namemd ATTRIBUTE_UNUSED
;
936 pr_debug ("debug_exp: ");
940 default: name
= "unknown"; break;
941 case O_illegal
: name
= "O_illegal"; break;
942 case O_absent
: name
= "O_absent"; break;
943 case O_constant
: name
= "O_constant"; break;
944 case O_symbol
: name
= "O_symbol"; break;
945 case O_symbol_rva
: name
= "O_symbol_rva"; break;
946 case O_register
: name
= "O_register"; break;
947 case O_big
: name
= "O_big"; break;
948 case O_uminus
: name
= "O_uminus"; break;
949 case O_bit_not
: name
= "O_bit_not"; break;
950 case O_logical_not
: name
= "O_logical_not"; break;
951 case O_multiply
: name
= "O_multiply"; break;
952 case O_divide
: name
= "O_divide"; break;
953 case O_modulus
: name
= "O_modulus"; break;
954 case O_left_shift
: name
= "O_left_shift"; break;
955 case O_right_shift
: name
= "O_right_shift"; break;
956 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
957 case O_bit_or_not
: name
= "O_bit_or_not"; break;
958 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
959 case O_bit_and
: name
= "O_bit_and"; break;
960 case O_add
: name
= "O_add"; break;
961 case O_subtract
: name
= "O_subtract"; break;
962 case O_eq
: name
= "O_eq"; break;
963 case O_ne
: name
= "O_ne"; break;
964 case O_lt
: name
= "O_lt"; break;
965 case O_le
: name
= "O_le"; break;
966 case O_ge
: name
= "O_ge"; break;
967 case O_gt
: name
= "O_gt"; break;
968 case O_logical_and
: name
= "O_logical_and"; break;
969 case O_logical_or
: name
= "O_logical_or"; break;
970 case O_index
: name
= "O_index"; break;
971 case O_bracket
: name
= "O_bracket"; break;
976 default: namemd
= "unknown"; break;
977 case O_gotoff
: namemd
= "O_gotoff"; break;
978 case O_gotpc
: namemd
= "O_gotpc"; break;
979 case O_plt
: namemd
= "O_plt"; break;
980 case O_sda
: namemd
= "O_sda"; break;
981 case O_pcl
: namemd
= "O_pcl"; break;
982 case O_tlsgd
: namemd
= "O_tlsgd"; break;
983 case O_tlsie
: namemd
= "O_tlsie"; break;
984 case O_tpoff9
: namemd
= "O_tpoff9"; break;
985 case O_tpoff
: namemd
= "O_tpoff"; break;
986 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
987 case O_dtpoff
: namemd
= "O_dtpoff"; break;
990 pr_debug ("%s (%s, %s, %d, %s)", name
,
991 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
992 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
993 (int) t
->X_add_number
,
994 (t
->X_md
) ? namemd
: "--");
999 /* Parse the arguments to an opcode. */
1002 tokenize_arguments (char *str
,
1006 char *old_input_line_pointer
;
1007 bfd_boolean saw_comma
= FALSE
;
1008 bfd_boolean saw_arg
= FALSE
;
1013 const struct arc_reloc_op_tag
*r
;
1015 char *reloc_name
, c
;
1017 memset (tok
, 0, sizeof (*tok
) * ntok
);
1019 /* Save and restore input_line_pointer around this function. */
1020 old_input_line_pointer
= input_line_pointer
;
1021 input_line_pointer
= str
;
1023 while (*input_line_pointer
)
1026 switch (*input_line_pointer
)
1032 input_line_pointer
++;
1033 if (saw_comma
|| !saw_arg
)
1040 ++input_line_pointer
;
1044 tok
->X_op
= O_bracket
;
1051 input_line_pointer
++;
1055 tok
->X_op
= O_bracket
;
1061 /* We have labels, function names and relocations, all
1062 starting with @ symbol. Sort them out. */
1063 if (saw_arg
&& !saw_comma
)
1067 tok
->X_op
= O_symbol
;
1068 tok
->X_md
= O_absent
;
1070 if (*input_line_pointer
!= '@')
1071 goto normalsymbol
; /* This is not a relocation. */
1075 /* A relocation opernad has the following form
1076 @identifier@relocation_type. The identifier is already
1078 if (tok
->X_op
!= O_symbol
)
1080 as_bad (_("No valid label relocation operand"));
1084 /* Parse @relocation_type. */
1085 input_line_pointer
++;
1086 c
= get_symbol_name (&reloc_name
);
1087 len
= input_line_pointer
- reloc_name
;
1090 as_bad (_("No relocation operand"));
1094 /* Go through known relocation and try to find a match. */
1095 r
= &arc_reloc_op
[0];
1096 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1097 if (len
== r
->length
1098 && memcmp (reloc_name
, r
->name
, len
) == 0)
1102 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1106 *input_line_pointer
= c
;
1107 SKIP_WHITESPACE_AFTER_NAME ();
1108 /* Extra check for TLS: base. */
1109 if (*input_line_pointer
== '@')
1112 if (tok
->X_op_symbol
!= NULL
1113 || tok
->X_op
!= O_symbol
)
1115 as_bad (_("Unable to parse TLS base: %s"),
1116 input_line_pointer
);
1119 input_line_pointer
++;
1121 c
= get_symbol_name (&sym_name
);
1122 base
= symbol_find_or_make (sym_name
);
1123 tok
->X_op
= O_subtract
;
1124 tok
->X_op_symbol
= base
;
1125 restore_line_pointer (c
);
1126 tmpE
.X_add_number
= 0;
1128 else if ((*input_line_pointer
!= '+')
1129 && (*input_line_pointer
!= '-'))
1131 tmpE
.X_add_number
= 0;
1135 /* Parse the constant of a complex relocation expression
1136 like @identifier@reloc +/- const. */
1137 if (! r
->complex_expr
)
1139 as_bad (_("@%s is not a complex relocation."), r
->name
);
1143 if (tmpE
.X_op
!= O_constant
)
1145 as_bad (_("Bad expression: @%s + %s."),
1146 r
->name
, input_line_pointer
);
1152 tok
->X_add_number
= tmpE
.X_add_number
;
1163 /* Can be a register. */
1164 ++input_line_pointer
;
1168 if (saw_arg
&& !saw_comma
)
1171 tok
->X_op
= O_absent
;
1172 tok
->X_md
= O_absent
;
1175 /* Legacy: There are cases when we have
1176 identifier@relocation_type, if it is the case parse the
1177 relocation type as well. */
1178 if (*input_line_pointer
== '@')
1184 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1196 if (saw_comma
|| brk_lvl
)
1198 input_line_pointer
= old_input_line_pointer
;
1204 as_bad (_("Brackets in operand field incorrect"));
1206 as_bad (_("extra comma"));
1208 as_bad (_("missing argument"));
1210 as_bad (_("missing comma or colon"));
1211 input_line_pointer
= old_input_line_pointer
;
1215 /* Parse the flags to a structure. */
1218 tokenize_flags (const char *str
,
1219 struct arc_flags flags
[],
1222 char *old_input_line_pointer
;
1223 bfd_boolean saw_flg
= FALSE
;
1224 bfd_boolean saw_dot
= FALSE
;
1228 memset (flags
, 0, sizeof (*flags
) * nflg
);
1230 /* Save and restore input_line_pointer around this function. */
1231 old_input_line_pointer
= input_line_pointer
;
1232 input_line_pointer
= (char *) str
;
1234 while (*input_line_pointer
)
1236 switch (*input_line_pointer
)
1243 input_line_pointer
++;
1251 if (saw_flg
&& !saw_dot
)
1254 if (num_flags
>= nflg
)
1257 flgnamelen
= strspn (input_line_pointer
,
1258 "abcdefghijklmnopqrstuvwxyz0123456789");
1259 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1262 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1264 input_line_pointer
+= flgnamelen
;
1274 input_line_pointer
= old_input_line_pointer
;
1279 as_bad (_("extra dot"));
1281 as_bad (_("unrecognized flag"));
1283 as_bad (_("failed to parse flags"));
1284 input_line_pointer
= old_input_line_pointer
;
1288 /* Apply the fixups in order. */
1291 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1295 for (i
= 0; i
< insn
->nfixups
; i
++)
1297 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1298 int size
, pcrel
, offset
= 0;
1300 /* FIXME! the reloc size is wrong in the BFD file.
1301 When it is fixed please delete me. */
1302 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1305 offset
= (insn
->short_insn
) ? 2 : 4;
1307 /* Some fixups are only used internally, thus no howto. */
1308 if ((int) fixup
->reloc
== 0)
1309 as_fatal (_("Unhandled reloc type"));
1311 if ((int) fixup
->reloc
< 0)
1313 /* FIXME! the reloc size is wrong in the BFD file.
1314 When it is fixed please enable me.
1315 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1316 pcrel
= fixup
->pcrel
;
1320 reloc_howto_type
*reloc_howto
=
1321 bfd_reloc_type_lookup (stdoutput
,
1322 (bfd_reloc_code_real_type
) fixup
->reloc
);
1323 gas_assert (reloc_howto
);
1325 /* FIXME! the reloc size is wrong in the BFD file.
1326 When it is fixed please enable me.
1327 size = bfd_get_reloc_size (reloc_howto); */
1328 pcrel
= reloc_howto
->pc_relative
;
1331 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1333 fragP
->fr_file
, fragP
->fr_line
,
1334 (fixup
->reloc
< 0) ? "Internal" :
1335 bfd_get_reloc_code_name (fixup
->reloc
),
1338 fix_new_exp (fragP
, fix
+ offset
,
1339 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1341 /* Check for ZOLs, and update symbol info if any. */
1342 if (LP_INSN (insn
->insn
))
1344 gas_assert (fixup
->exp
.X_add_symbol
);
1345 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1350 /* Actually output an instruction with its fixup. */
1353 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1357 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1358 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1359 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1361 /* Write out the instruction. */
1362 if (insn
->short_insn
)
1368 md_number_to_chars (f
, insn
->insn
, 2);
1369 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1370 dwarf2_emit_insn (6);
1376 md_number_to_chars (f
, insn
->insn
, 2);
1377 dwarf2_emit_insn (2);
1386 md_number_to_chars_midend (f
, insn
->insn
, 4);
1387 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1388 dwarf2_emit_insn (8);
1394 md_number_to_chars_midend (f
, insn
->insn
, 4);
1395 dwarf2_emit_insn (4);
1400 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1404 emit_insn1 (struct arc_insn
*insn
)
1406 /* How frag_var's args are currently configured:
1407 - rs_machine_dependent, to dictate it's a relaxation frag.
1408 - FRAG_MAX_GROWTH, maximum size of instruction
1409 - 0, variable size that might grow...unused by generic relaxation.
1410 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1411 - s, opand expression.
1412 - 0, offset but it's unused.
1413 - 0, opcode but it's unused. */
1414 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1415 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1417 if (frag_room () < FRAG_MAX_GROWTH
)
1419 /* Handle differently when frag literal memory is exhausted.
1420 This is used because when there's not enough memory left in
1421 the current frag, a new frag is created and the information
1422 we put into frag_now->tc_frag_data is disregarded. */
1424 struct arc_relax_type relax_info_copy
;
1425 relax_substateT subtype
= frag_now
->fr_subtype
;
1427 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1428 sizeof (struct arc_relax_type
));
1430 frag_wane (frag_now
);
1431 frag_grow (FRAG_MAX_GROWTH
);
1433 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1434 sizeof (struct arc_relax_type
));
1436 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1440 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1441 frag_now
->fr_subtype
, s
, 0, 0);
1445 emit_insn (struct arc_insn
*insn
)
1450 emit_insn0 (insn
, NULL
, FALSE
);
1453 /* Check whether a symbol involves a register. */
1456 contains_register (symbolS
*sym
)
1460 expressionS
*ex
= symbol_get_value_expression (sym
);
1462 return ((O_register
== ex
->X_op
)
1463 && !contains_register (ex
->X_add_symbol
)
1464 && !contains_register (ex
->X_op_symbol
));
1470 /* Returns the register number within a symbol. */
1473 get_register (symbolS
*sym
)
1475 if (!contains_register (sym
))
1478 expressionS
*ex
= symbol_get_value_expression (sym
);
1479 return regno (ex
->X_add_number
);
1482 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1483 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1486 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1493 case BFD_RELOC_ARC_SDA_LDST
:
1494 case BFD_RELOC_ARC_SDA_LDST1
:
1495 case BFD_RELOC_ARC_SDA_LDST2
:
1496 case BFD_RELOC_ARC_SDA16_LD
:
1497 case BFD_RELOC_ARC_SDA16_LD1
:
1498 case BFD_RELOC_ARC_SDA16_LD2
:
1499 case BFD_RELOC_ARC_SDA16_ST2
:
1500 case BFD_RELOC_ARC_SDA32_ME
:
1507 /* Allocates a tok entry. */
1510 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1512 if (ntok
> MAX_INSN_ARGS
- 2)
1513 return 0; /* No space left. */
1516 return 0; /* Incorect args. */
1518 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1521 return 1; /* Success. */
1522 return allocate_tok (tok
, ntok
- 1, cidx
);
1525 /* Check if an particular ARC feature is enabled. */
1528 check_cpu_feature (insn_subclass_t sc
)
1530 if (!(arc_features
& ARC_CD
)
1531 && is_code_density_p (sc
))
1534 if (!(arc_features
& ARC_SPFP
)
1538 if (!(arc_features
& ARC_DPFP
)
1542 if (!(arc_features
& ARC_FPUDA
)
1549 /* Search forward through all variants of an opcode looking for a
1552 static const struct arc_opcode
*
1553 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1556 struct arc_flags
*first_pflag
,
1560 const struct arc_opcode
*opcode
;
1561 struct arc_opcode_hash_entry_iterator iter
;
1563 int got_cpu_match
= 0;
1564 expressionS bktok
[MAX_INSN_ARGS
];
1568 arc_opcode_hash_entry_iterator_init (&iter
);
1569 memset (&emptyE
, 0, sizeof (emptyE
));
1570 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1573 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1575 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1577 const unsigned char *opidx
;
1578 const unsigned char *flgidx
;
1579 int tokidx
= 0, lnflg
, i
;
1580 const expressionS
*t
= &emptyE
;
1582 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1583 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1585 /* Don't match opcodes that don't exist on this
1587 if (!(opcode
->cpu
& arc_target
))
1590 if (!check_cpu_feature (opcode
->subclass
))
1596 /* Check the operands. */
1597 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1599 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1601 /* Only take input from real operands. */
1602 if ((operand
->flags
& ARC_OPERAND_FAKE
)
1603 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
1606 /* When we expect input, make sure we have it. */
1610 /* Match operand type with expression type. */
1611 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1613 case ARC_OPERAND_IR
:
1614 /* Check to be a register. */
1615 if ((tok
[tokidx
].X_op
!= O_register
1616 || !is_ir_num (tok
[tokidx
].X_add_number
))
1617 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1620 /* If expect duplicate, make sure it is duplicate. */
1621 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1623 /* Check for duplicate. */
1624 if (t
->X_op
!= O_register
1625 || !is_ir_num (t
->X_add_number
)
1626 || (regno (t
->X_add_number
) !=
1627 regno (tok
[tokidx
].X_add_number
)))
1631 /* Special handling? */
1632 if (operand
->insert
)
1634 const char *errmsg
= NULL
;
1635 (*operand
->insert
)(0,
1636 regno (tok
[tokidx
].X_add_number
),
1640 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1642 /* Missing argument, create one. */
1643 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1646 tok
[tokidx
].X_op
= O_absent
;
1657 case ARC_OPERAND_BRAKET
:
1658 /* Check if bracket is also in opcode table as
1660 if (tok
[tokidx
].X_op
!= O_bracket
)
1664 case ARC_OPERAND_LIMM
:
1665 case ARC_OPERAND_SIGNED
:
1666 case ARC_OPERAND_UNSIGNED
:
1667 switch (tok
[tokidx
].X_op
)
1675 /* Got an (too) early bracket, check if it is an
1676 ignored operand. N.B. This procedure works only
1677 when bracket is the last operand! */
1678 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1680 /* Insert the missing operand. */
1681 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1684 tok
[tokidx
].X_op
= O_absent
;
1691 const struct arc_aux_reg
*auxr
;
1693 if (opcode
->class != AUXREG
)
1695 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1697 auxr
= hash_find (arc_aux_hash
, p
);
1700 /* We modify the token array here, safe in the
1701 knowledge, that if this was the wrong
1702 choice then the original contents will be
1703 restored from BKTOK. */
1704 tok
[tokidx
].X_op
= O_constant
;
1705 tok
[tokidx
].X_add_number
= auxr
->address
;
1706 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1709 if (tok
[tokidx
].X_op
!= O_constant
)
1714 /* Check the range. */
1715 if (operand
->bits
!= 32
1716 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1718 offsetT min
, max
, val
;
1719 val
= tok
[tokidx
].X_add_number
;
1721 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1723 max
= (1 << (operand
->bits
- 1)) - 1;
1724 min
= -(1 << (operand
->bits
- 1));
1728 max
= (1 << operand
->bits
) - 1;
1732 if (val
< min
|| val
> max
)
1735 /* Check alignmets. */
1736 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1740 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1744 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1746 if (operand
->insert
)
1748 const char *errmsg
= NULL
;
1749 (*operand
->insert
)(0,
1750 tok
[tokidx
].X_add_number
,
1761 /* Check if it is register range. */
1762 if ((tok
[tokidx
].X_add_number
== 0)
1763 && contains_register (tok
[tokidx
].X_add_symbol
)
1764 && contains_register (tok
[tokidx
].X_op_symbol
))
1768 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1770 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1771 if (operand
->insert
)
1773 const char *errmsg
= NULL
;
1774 (*operand
->insert
)(0,
1786 if (operand
->default_reloc
== 0)
1787 goto match_failed
; /* The operand needs relocation. */
1789 /* Relocs requiring long immediate. FIXME! make it
1790 generic and move it to a function. */
1791 switch (tok
[tokidx
].X_md
)
1800 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1803 if (!generic_reloc_p (operand
->default_reloc
))
1810 /* If expect duplicate, make sure it is duplicate. */
1811 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1813 if (t
->X_op
== O_illegal
1814 || t
->X_op
== O_absent
1815 || t
->X_op
== O_register
1816 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1823 /* Everything else should have been fake. */
1831 /* Setup ready for flag parsing. */
1833 for (i
= 0; i
< nflgs
; i
++)
1834 first_pflag
[i
].flgp
= NULL
;
1836 /* Check the flags. Iterate over the valid flag classes. */
1837 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1839 /* Get a valid flag class. */
1840 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1841 const unsigned *flgopridx
;
1843 struct arc_flags
*pflag
= NULL
;
1845 /* Check for extension conditional codes. */
1846 if (ext_condcode
.arc_ext_condcode
1847 && cl_flags
->class & F_CLASS_EXTEND
)
1849 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1852 pflag
= first_pflag
;
1853 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1855 if (!strcmp (pf
->name
, pflag
->name
))
1857 if (pflag
->flgp
!= NULL
)
1870 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1872 const struct arc_flag_operand
*flg_operand
;
1874 pflag
= first_pflag
;
1875 flg_operand
= &arc_flag_operands
[*flgopridx
];
1876 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1878 /* Match against the parsed flags. */
1879 if (!strcmp (flg_operand
->name
, pflag
->name
))
1881 if (pflag
->flgp
!= NULL
)
1884 pflag
->flgp
= (struct arc_flag_operand
*) flg_operand
;
1886 break; /* goto next flag class and parsed flag. */
1891 if ((cl_flags
->class & F_CLASS_REQUIRED
) && cl_matches
== 0)
1893 if ((cl_flags
->class & F_CLASS_OPTIONAL
) && cl_matches
> 1)
1896 /* Did I check all the parsed flags? */
1901 /* Possible match -- did we use all of our input? */
1911 /* Restore the original parameters. */
1912 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1917 *pcpumatch
= got_cpu_match
;
1922 /* Swap operand tokens. */
1925 swap_operand (expressionS
*operand_array
,
1927 unsigned destination
)
1929 expressionS cpy_operand
;
1930 expressionS
*src_operand
;
1931 expressionS
*dst_operand
;
1934 if (source
== destination
)
1937 src_operand
= &operand_array
[source
];
1938 dst_operand
= &operand_array
[destination
];
1939 size
= sizeof (expressionS
);
1941 /* Make copy of operand to swap with and swap. */
1942 memcpy (&cpy_operand
, dst_operand
, size
);
1943 memcpy (dst_operand
, src_operand
, size
);
1944 memcpy (src_operand
, &cpy_operand
, size
);
1947 /* Check if *op matches *tok type.
1948 Returns FALSE if they don't match, TRUE if they match. */
1951 pseudo_operand_match (const expressionS
*tok
,
1952 const struct arc_operand_operation
*op
)
1954 offsetT min
, max
, val
;
1956 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
1962 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
1964 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
1966 val
= tok
->X_add_number
+ op
->count
;
1967 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
1969 max
= (1 << (operand_real
->bits
- 1)) - 1;
1970 min
= -(1 << (operand_real
->bits
- 1));
1974 max
= (1 << operand_real
->bits
) - 1;
1977 if (min
<= val
&& val
<= max
)
1983 /* Handle all symbols as long immediates or signed 9. */
1984 if (operand_real
->flags
& ARC_OPERAND_LIMM
||
1985 ((operand_real
->flags
& ARC_OPERAND_SIGNED
) && operand_real
->bits
== 9))
1990 if (operand_real
->flags
& ARC_OPERAND_IR
)
1995 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2006 /* Find pseudo instruction in array. */
2008 static const struct arc_pseudo_insn
*
2009 find_pseudo_insn (const char *opname
,
2011 const expressionS
*tok
)
2013 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2014 const struct arc_operand_operation
*op
;
2018 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2020 pseudo_insn
= &arc_pseudo_insns
[i
];
2021 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2023 op
= pseudo_insn
->operand
;
2024 for (j
= 0; j
< ntok
; ++j
)
2025 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2028 /* Found the right instruction. */
2036 /* Assumes the expressionS *tok is of sufficient size. */
2038 static const struct arc_opcode_hash_entry
*
2039 find_special_case_pseudo (const char *opname
,
2043 struct arc_flags
*pflags
)
2045 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2046 const struct arc_operand_operation
*operand_pseudo
;
2047 const struct arc_operand
*operand_real
;
2049 char construct_operand
[MAX_CONSTR_STR
];
2051 /* Find whether opname is in pseudo instruction array. */
2052 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2054 if (pseudo_insn
== NULL
)
2057 /* Handle flag, Limited to one flag at the moment. */
2058 if (pseudo_insn
->flag_r
!= NULL
)
2059 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2060 MAX_INSN_FLGS
- *nflgs
);
2062 /* Handle operand operations. */
2063 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2065 operand_pseudo
= &pseudo_insn
->operand
[i
];
2066 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2068 if (operand_real
->flags
& ARC_OPERAND_BRAKET
&&
2069 !operand_pseudo
->needs_insert
)
2072 /* Has to be inserted (i.e. this token does not exist yet). */
2073 if (operand_pseudo
->needs_insert
)
2075 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2077 tok
[i
].X_op
= O_bracket
;
2082 /* Check if operand is a register or constant and handle it
2084 if (operand_real
->flags
& ARC_OPERAND_IR
)
2085 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2086 operand_pseudo
->count
);
2088 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2089 operand_pseudo
->count
);
2091 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2095 else if (operand_pseudo
->count
)
2097 /* Operand number has to be adjusted accordingly (by operand
2099 switch (tok
[i
].X_op
)
2102 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2115 /* Swap operands if necessary. Only supports one swap at the
2117 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2119 operand_pseudo
= &pseudo_insn
->operand
[i
];
2121 if (operand_pseudo
->swap_operand_idx
== i
)
2124 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2126 /* Prevent a swap back later by breaking out. */
2130 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2133 static const struct arc_opcode_hash_entry
*
2134 find_special_case_flag (const char *opname
,
2136 struct arc_flags
*pflags
)
2140 unsigned flag_idx
, flag_arr_idx
;
2141 size_t flaglen
, oplen
;
2142 const struct arc_flag_special
*arc_flag_special_opcode
;
2143 const struct arc_opcode_hash_entry
*entry
;
2145 /* Search for special case instruction. */
2146 for (i
= 0; i
< arc_num_flag_special
; i
++)
2148 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2149 oplen
= strlen (arc_flag_special_opcode
->name
);
2151 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2154 /* Found a potential special case instruction, now test for
2156 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2158 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2160 break; /* End of array, nothing found. */
2162 flagnm
= arc_flag_operands
[flag_idx
].name
;
2163 flaglen
= strlen (flagnm
);
2164 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2166 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2168 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2170 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2171 pflags
[*nflgs
].name
[flaglen
] = '\0';
2180 /* Used to find special case opcode. */
2182 static const struct arc_opcode_hash_entry
*
2183 find_special_case (const char *opname
,
2185 struct arc_flags
*pflags
,
2189 const struct arc_opcode_hash_entry
*entry
;
2191 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2194 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2199 /* Given an opcode name, pre-tockenized set of argumenst and the
2200 opcode flags, take it all the way through emission. */
2203 assemble_tokens (const char *opname
,
2206 struct arc_flags
*pflags
,
2209 bfd_boolean found_something
= FALSE
;
2210 const struct arc_opcode_hash_entry
*entry
;
2213 /* Search opcodes. */
2214 entry
= arc_find_opcode (opname
);
2216 /* Couldn't find opcode conventional way, try special cases. */
2218 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2222 const struct arc_opcode
*opcode
;
2224 pr_debug ("%s:%d: assemble_tokens: %s\n",
2225 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2226 found_something
= TRUE
;
2227 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2231 struct arc_insn insn
;
2233 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2239 if (found_something
)
2242 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2244 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2248 as_bad (_("unknown opcode '%s'"), opname
);
2251 /* The public interface to the instruction assembler. */
2254 md_assemble (char *str
)
2257 expressionS tok
[MAX_INSN_ARGS
];
2260 struct arc_flags flags
[MAX_INSN_FLGS
];
2262 /* Split off the opcode. */
2263 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2264 opname
= xmemdup0 (str
, opnamelen
);
2266 /* Signalize we are assmbling the instructions. */
2267 assembling_insn
= TRUE
;
2269 /* Tokenize the flags. */
2270 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2272 as_bad (_("syntax error"));
2276 /* Scan up to the end of the mnemonic which must end in space or end
2279 for (; *str
!= '\0'; str
++)
2283 /* Tokenize the rest of the line. */
2284 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2286 as_bad (_("syntax error"));
2290 /* Finish it off. */
2291 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2292 assembling_insn
= FALSE
;
2295 /* Callback to insert a register into the hash table. */
2298 declare_register (const char *name
, int number
)
2301 symbolS
*regS
= symbol_create (name
, reg_section
,
2302 number
, &zero_address_frag
);
2304 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2306 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2310 /* Construct symbols for each of the general registers. */
2313 declare_register_set (void)
2316 for (i
= 0; i
< 64; ++i
)
2320 sprintf (name
, "r%d", i
);
2321 declare_register (name
, i
);
2322 if ((i
& 0x01) == 0)
2324 sprintf (name
, "r%dr%d", i
, i
+1);
2325 declare_register (name
, i
);
2330 /* Port-specific assembler initialization. This function is called
2331 once, at assembler startup time. */
2336 const struct arc_opcode
*opcode
= arc_opcodes
;
2338 if (!mach_type_specified_p
)
2339 arc_select_cpu ("arc700");
2341 /* The endianness can be chosen "at the factory". */
2342 target_big_endian
= byte_order
== BIG_ENDIAN
;
2344 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2345 as_warn (_("could not set architecture and machine"));
2347 /* Set elf header flags. */
2348 bfd_set_private_flags (stdoutput
, arc_eflag
);
2350 /* Set up a hash table for the instructions. */
2351 arc_opcode_hash
= hash_new ();
2352 if (arc_opcode_hash
== NULL
)
2353 as_fatal (_("Virtual memory exhausted"));
2355 /* Initialize the hash table with the insns. */
2358 const char *name
= opcode
->name
;
2360 arc_insert_opcode (opcode
);
2362 while (++opcode
&& opcode
->name
2363 && (opcode
->name
== name
2364 || !strcmp (opcode
->name
, name
)))
2366 }while (opcode
->name
);
2368 /* Register declaration. */
2369 arc_reg_hash
= hash_new ();
2370 if (arc_reg_hash
== NULL
)
2371 as_fatal (_("Virtual memory exhausted"));
2373 declare_register_set ();
2374 declare_register ("gp", 26);
2375 declare_register ("fp", 27);
2376 declare_register ("sp", 28);
2377 declare_register ("ilink", 29);
2378 declare_register ("ilink1", 29);
2379 declare_register ("ilink2", 30);
2380 declare_register ("blink", 31);
2382 declare_register ("mlo", 57);
2383 declare_register ("mmid", 58);
2384 declare_register ("mhi", 59);
2386 declare_register ("acc1", 56);
2387 declare_register ("acc2", 57);
2389 declare_register ("lp_count", 60);
2390 declare_register ("pcl", 63);
2392 /* Initialize the last instructions. */
2393 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2395 /* Aux register declaration. */
2396 arc_aux_hash
= hash_new ();
2397 if (arc_aux_hash
== NULL
)
2398 as_fatal (_("Virtual memory exhausted"));
2400 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2402 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2406 if (!(auxr
->cpu
& arc_target
))
2409 if ((auxr
->subclass
!= NONE
)
2410 && !check_cpu_feature (auxr
->subclass
))
2413 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2415 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2416 auxr
->name
, retval
);
2420 /* Write a value out to the object file, using the appropriate
2424 md_number_to_chars (char *buf
,
2428 if (target_big_endian
)
2429 number_to_chars_bigendian (buf
, val
, n
);
2431 number_to_chars_littleendian (buf
, val
, n
);
2434 /* Round up a section size to the appropriate boundary. */
2437 md_section_align (segT segment
,
2440 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2442 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2445 /* The location from which a PC relative jump should be calculated,
2446 given a PC relative reloc. */
2449 md_pcrel_from_section (fixS
*fixP
,
2452 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2454 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2456 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2457 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2458 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2460 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2462 /* The symbol is undefined (or is defined but not in this section).
2463 Let the linker figure it out. */
2467 if ((int) fixP
->fx_r_type
< 0)
2469 /* These are the "internal" relocations. Align them to
2470 32 bit boundary (PCL), for the moment. */
2475 switch (fixP
->fx_r_type
)
2477 case BFD_RELOC_ARC_PC32
:
2478 /* The hardware calculates relative to the start of the
2479 insn, but this relocation is relative to location of the
2480 LIMM, compensate. The base always needs to be
2481 substracted by 4 as we do not support this type of PCrel
2482 relocation for short instructions. */
2485 case BFD_RELOC_ARC_PLT32
:
2486 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2487 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2488 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2489 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2491 case BFD_RELOC_ARC_S21H_PCREL
:
2492 case BFD_RELOC_ARC_S25H_PCREL
:
2493 case BFD_RELOC_ARC_S13_PCREL
:
2494 case BFD_RELOC_ARC_S21W_PCREL
:
2495 case BFD_RELOC_ARC_S25W_PCREL
:
2499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2500 _("unhandled reloc %s in md_pcrel_from_section"),
2501 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2506 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2507 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2508 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2509 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2514 /* Given a BFD relocation find the coresponding operand. */
2516 static const struct arc_operand
*
2517 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2521 for (i
= 0; i
< arc_num_operands
; i
++)
2522 if (arc_operands
[i
].default_reloc
== reloc
)
2523 return &arc_operands
[i
];
2527 /* Insert an operand value into an instruction. */
2530 insert_operand (unsigned insn
,
2531 const struct arc_operand
*operand
,
2536 offsetT min
= 0, max
= 0;
2538 if (operand
->bits
!= 32
2539 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2540 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2542 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2544 max
= (1 << (operand
->bits
- 1)) - 1;
2545 min
= -(1 << (operand
->bits
- 1));
2549 max
= (1 << operand
->bits
) - 1;
2553 if (val
< min
|| val
> max
)
2554 as_bad_value_out_of_range (_("operand"),
2555 val
, min
, max
, file
, line
);
2558 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2559 min
, val
, max
, insn
);
2561 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2563 as_bad_where (file
, line
,
2564 _("Unaligned operand. Needs to be 32bit aligned"));
2566 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2568 as_bad_where (file
, line
,
2569 _("Unaligned operand. Needs to be 16bit aligned"));
2571 if (operand
->insert
)
2573 const char *errmsg
= NULL
;
2575 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2577 as_warn_where (file
, line
, "%s", errmsg
);
2581 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2583 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2585 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2588 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2593 /* Apply a fixup to the object code. At this point all symbol values
2594 should be fully resolved, and we attempt to completely resolve the
2595 reloc. If we can not do that, we determine the correct reloc code
2596 and put it back in the fixup. To indicate that a fixup has been
2597 eliminated, set fixP->fx_done. */
2600 md_apply_fix (fixS
*fixP
,
2604 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2605 valueT value
= *valP
;
2607 symbolS
*fx_addsy
, *fx_subsy
;
2609 segT add_symbol_segment
= absolute_section
;
2610 segT sub_symbol_segment
= absolute_section
;
2611 const struct arc_operand
*operand
= NULL
;
2612 extended_bfd_reloc_code_real_type reloc
;
2614 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2615 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2616 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2617 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2620 fx_addsy
= fixP
->fx_addsy
;
2621 fx_subsy
= fixP
->fx_subsy
;
2626 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2630 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2631 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2632 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2634 resolve_symbol_value (fx_subsy
);
2635 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2637 if (sub_symbol_segment
== absolute_section
)
2639 /* The symbol is really a constant. */
2640 fx_offset
-= S_GET_VALUE (fx_subsy
);
2645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2646 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2647 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2648 segment_name (add_symbol_segment
),
2649 S_GET_NAME (fx_subsy
),
2650 segment_name (sub_symbol_segment
));
2656 && !S_IS_WEAK (fx_addsy
))
2658 if (add_symbol_segment
== seg
2661 value
+= S_GET_VALUE (fx_addsy
);
2662 value
-= md_pcrel_from_section (fixP
, seg
);
2664 fixP
->fx_pcrel
= FALSE
;
2666 else if (add_symbol_segment
== absolute_section
)
2668 value
= fixP
->fx_offset
;
2669 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2671 fixP
->fx_pcrel
= FALSE
;
2676 fixP
->fx_done
= TRUE
;
2681 && ((S_IS_DEFINED (fx_addsy
)
2682 && S_GET_SEGMENT (fx_addsy
) != seg
)
2683 || S_IS_WEAK (fx_addsy
)))
2684 value
+= md_pcrel_from_section (fixP
, seg
);
2686 switch (fixP
->fx_r_type
)
2688 case BFD_RELOC_ARC_32_ME
:
2689 /* This is a pc-relative value in a LIMM. Adjust it to the
2690 address of the instruction not to the address of the
2691 LIMM. Note: it is not anylonger valid this afirmation as
2692 the linker consider ARC_PC32 a fixup to entire 64 bit
2694 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2697 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2699 case BFD_RELOC_ARC_PC32
:
2700 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2703 if ((int) fixP
->fx_r_type
< 0)
2704 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2710 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2711 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2712 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2713 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2717 /* Now check for TLS relocations. */
2718 reloc
= fixP
->fx_r_type
;
2721 case BFD_RELOC_ARC_TLS_DTPOFF
:
2722 case BFD_RELOC_ARC_TLS_LE_32
:
2726 case BFD_RELOC_ARC_TLS_GD_GOT
:
2727 case BFD_RELOC_ARC_TLS_IE_GOT
:
2728 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2731 case BFD_RELOC_ARC_TLS_GD_LD
:
2732 gas_assert (!fixP
->fx_offset
);
2735 = (S_GET_VALUE (fixP
->fx_subsy
)
2736 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2737 fixP
->fx_subsy
= NULL
;
2739 case BFD_RELOC_ARC_TLS_GD_CALL
:
2740 /* These two relocs are there just to allow ld to change the tls
2741 model for this symbol, by patching the code. The offset -
2742 and scale, if any - will be installed by the linker. */
2743 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2746 case BFD_RELOC_ARC_TLS_LE_S9
:
2747 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2748 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2760 /* Addjust the value if we have a constant. */
2763 /* For hosts with longs bigger than 32-bits make sure that the top
2764 bits of a 32-bit negative value read in by the parser are set,
2765 so that the correct comparisons are made. */
2766 if (value
& 0x80000000)
2767 value
|= (-1L << 31);
2769 reloc
= fixP
->fx_r_type
;
2777 case BFD_RELOC_ARC_32_PCREL
:
2778 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2781 case BFD_RELOC_ARC_GOTPC32
:
2782 /* I cannot fix an GOTPC relocation because I need to relax it
2783 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2784 as_bad (_("Unsupported operation on reloc"));
2787 case BFD_RELOC_ARC_TLS_DTPOFF
:
2788 case BFD_RELOC_ARC_TLS_LE_32
:
2789 gas_assert (!fixP
->fx_addsy
);
2790 gas_assert (!fixP
->fx_subsy
);
2792 case BFD_RELOC_ARC_GOTOFF
:
2793 case BFD_RELOC_ARC_32_ME
:
2794 case BFD_RELOC_ARC_PC32
:
2795 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2798 case BFD_RELOC_ARC_PLT32
:
2799 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2802 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2803 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2806 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2807 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2810 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2811 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2814 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2815 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2817 case BFD_RELOC_ARC_S25W_PCREL
:
2818 case BFD_RELOC_ARC_S21W_PCREL
:
2819 case BFD_RELOC_ARC_S21H_PCREL
:
2820 case BFD_RELOC_ARC_S25H_PCREL
:
2821 case BFD_RELOC_ARC_S13_PCREL
:
2823 operand
= find_operand_for_reloc (reloc
);
2824 gas_assert (operand
);
2829 if ((int) fixP
->fx_r_type
>= 0)
2830 as_fatal (_("unhandled relocation type %s"),
2831 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2833 /* The rest of these fixups needs to be completely resolved as
2835 if (fixP
->fx_addsy
!= 0
2836 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2838 _("non-absolute expression in constant field"));
2840 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2841 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
2846 if (target_big_endian
)
2848 switch (fixP
->fx_size
)
2851 insn
= bfd_getb32 (fixpos
);
2854 insn
= bfd_getb16 (fixpos
);
2857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2858 _("unknown fixup size"));
2864 switch (fixP
->fx_size
)
2867 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
2870 insn
= bfd_getl16 (fixpos
);
2873 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2874 _("unknown fixup size"));
2878 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
2879 fixP
->fx_file
, fixP
->fx_line
);
2881 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
2884 /* Prepare machine-dependent frags for relaxation.
2886 Called just before relaxation starts. Any symbol that is now undefined
2887 will not become defined.
2889 Return the correct fr_subtype in the frag.
2891 Return the initial "guess for fr_var" to caller. The guess for fr_var
2892 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2893 or fr_var contributes to our returned value.
2895 Although it may not be explicit in the frag, pretend
2896 fr_var starts with a value. */
2899 md_estimate_size_before_relax (fragS
*fragP
,
2904 /* If the symbol is not located within the same section AND it's not
2905 an absolute section, use the maximum. OR if the symbol is a
2906 constant AND the insn is by nature not pc-rel, use the maximum.
2907 OR if the symbol is being equated against another symbol, use the
2908 maximum. OR if the symbol is weak use the maximum. */
2909 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
2910 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2911 || (symbol_constant_p (fragP
->fr_symbol
)
2912 && !fragP
->tc_frag_data
.pcrel
)
2913 || symbol_equated_p (fragP
->fr_symbol
)
2914 || S_IS_WEAK (fragP
->fr_symbol
))
2916 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
2917 ++fragP
->fr_subtype
;
2920 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
2921 fragP
->fr_var
= growth
;
2923 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2924 fragP
->fr_file
, fragP
->fr_line
, growth
);
2929 /* Translate internal representation of relocation info to BFD target
2933 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
2937 bfd_reloc_code_real_type code
;
2939 reloc
= XNEW (arelent
);
2940 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
2941 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
2942 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2944 /* Make sure none of our internal relocations make it this far.
2945 They'd better have been fully resolved by this point. */
2946 gas_assert ((int) fixP
->fx_r_type
> 0);
2948 code
= fixP
->fx_r_type
;
2950 /* if we have something like add gp, pcl,
2951 _GLOBAL_OFFSET_TABLE_@gotpc. */
2952 if (code
== BFD_RELOC_ARC_GOTPC32
2954 && fixP
->fx_addsy
== GOT_symbol
)
2955 code
= BFD_RELOC_ARC_GOTPC
;
2957 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2958 if (reloc
->howto
== NULL
)
2960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2961 _("cannot represent `%s' relocation in object file"),
2962 bfd_get_reloc_code_name (code
));
2966 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
2967 as_fatal (_("internal error? cannot generate `%s' relocation"),
2968 bfd_get_reloc_code_name (code
));
2970 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
2972 if (code
== BFD_RELOC_ARC_TLS_DTPOFF
2973 || code
== BFD_RELOC_ARC_TLS_DTPOFF_S9
)
2976 = fixP
->fx_subsy
? symbol_get_bfdsym (fixP
->fx_subsy
) : NULL
;
2977 /* We just want to store a 24 bit index, but we have to wait
2978 till after write_contents has been called via
2979 bfd_map_over_sections before we can get the index from
2980 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2981 function is elf32-arc.c has to pick up the slack.
2982 Unfortunately, this leads to problems with hosts that have
2983 pointers wider than long (bfd_vma). There would be various
2984 ways to handle this, all error-prone :-( */
2985 reloc
->addend
= (bfd_vma
) sym
;
2986 if ((asymbol
*) reloc
->addend
!= sym
)
2988 as_bad ("Can't store pointer\n");
2993 reloc
->addend
= fixP
->fx_offset
;
2998 /* Perform post-processing of machine-dependent frags after relaxation.
2999 Called after relaxation is finished.
3000 In: Address of frag.
3001 fr_type == rs_machine_dependent.
3002 fr_subtype is what the address relaxed to.
3004 Out: Any fixS:s and constants are set up. */
3007 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3008 segT segment ATTRIBUTE_UNUSED
,
3011 const relax_typeS
*table_entry
;
3013 const struct arc_opcode
*opcode
;
3014 struct arc_insn insn
;
3016 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3018 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3019 dest
= fragP
->fr_literal
+ fix
;
3020 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3022 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
3023 fragP
->fr_file
, fragP
->fr_line
,
3024 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3026 if (fragP
->fr_subtype
<= 0
3027 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3028 as_fatal (_("no relaxation found for this instruction."));
3030 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3032 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3033 relax_arg
->nflg
, &insn
);
3035 apply_fixups (&insn
, fragP
, fix
);
3037 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
3038 gas_assert (table_entry
->rlx_length
== size
);
3039 emit_insn0 (&insn
, dest
, TRUE
);
3041 fragP
->fr_fix
+= table_entry
->rlx_length
;
3045 /* We have no need to default values of symbols. We could catch
3046 register names here, but that is handled by inserting them all in
3047 the symbol table to begin with. */
3050 md_undefined_symbol (char *name
)
3052 /* The arc abi demands that a GOT[0] should be referencible as
3053 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3054 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3056 && (*(name
+1) == 'G')
3057 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3059 && (*(name
+1) == 'D')
3060 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3064 if (symbol_find (name
))
3065 as_bad ("GOT already in symbol table");
3067 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3068 (valueT
) 0, &zero_address_frag
);
3075 /* Turn a string in input_line_pointer into a floating point constant
3076 of type type, and store the appropriate bytes in *litP. The number
3077 of LITTLENUMS emitted is stored in *sizeP. An error message is
3078 returned, or NULL on OK. */
3081 md_atof (int type
, char *litP
, int *sizeP
)
3083 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3086 /* Called for any expression that can not be recognized. When the
3087 function is called, `input_line_pointer' will point to the start of
3091 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3093 char *p
= input_line_pointer
;
3096 input_line_pointer
++;
3097 expressionP
->X_op
= O_symbol
;
3098 expression (expressionP
);
3102 /* This function is called from the function 'expression', it attempts
3103 to parse special names (in our case register names). It fills in
3104 the expression with the identified register. It returns TRUE if
3105 it is a register and FALSE otherwise. */
3108 arc_parse_name (const char *name
,
3109 struct expressionS
*e
)
3113 if (!assembling_insn
)
3116 /* Handle only registers. */
3117 if (e
->X_op
!= O_absent
)
3120 sym
= hash_find (arc_reg_hash
, name
);
3123 e
->X_op
= O_register
;
3124 e
->X_add_number
= S_GET_VALUE (sym
);
3131 Invocation line includes a switch not recognized by the base assembler.
3132 See if it's a processor-specific option.
3134 New options (supported) are:
3136 -mcpu=<cpu name> Assemble for selected processor
3137 -EB/-mbig-endian Big-endian
3138 -EL/-mlittle-endian Little-endian
3139 -mrelax Enable relaxation
3141 The following CPU names are recognized:
3142 arc700, av2em, av2hs. */
3145 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3151 return md_parse_option (OPTION_MCPU
, "arc600");
3154 return md_parse_option (OPTION_MCPU
, "arc700");
3157 return md_parse_option (OPTION_MCPU
, "arcem");
3160 return md_parse_option (OPTION_MCPU
, "archs");
3164 arc_select_cpu (arg
);
3165 mach_type_specified_p
= TRUE
;
3170 arc_target_format
= "elf32-bigarc";
3171 byte_order
= BIG_ENDIAN
;
3175 arc_target_format
= "elf32-littlearc";
3176 byte_order
= LITTLE_ENDIAN
;
3180 /* This option has an effect only on ARC EM. */
3181 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3182 arc_features
|= ARC_CD
;
3184 as_warn (_("Code density option invalid for selected CPU"));
3188 relaxation_state
= 1;
3191 case OPTION_USER_MODE
:
3192 case OPTION_LD_EXT_MASK
:
3195 case OPTION_BARREL_SHIFT
:
3196 case OPTION_MIN_MAX
:
3201 /* Dummy options are accepted but have no effect. */
3205 arc_features
|= ARC_SPFP
;
3209 arc_features
|= ARC_DPFP
;
3212 case OPTION_XMAC_D16
:
3213 case OPTION_XMAC_24
:
3214 case OPTION_DSP_PACKA
:
3217 case OPTION_TELEPHONY
:
3218 case OPTION_XYMEMORY
:
3222 /* Dummy options are accepted but have no effect. */
3226 /* This option has an effect only on ARC EM. */
3227 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3228 arc_features
|= ARC_FPUDA
;
3230 as_warn (_("FPUDA invalid for selected CPU"));
3241 md_show_usage (FILE *stream
)
3243 fprintf (stream
, _("ARC-specific assembler options:\n"));
3245 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3247 " -mcode-density\t enable code density option for ARC EM\n");
3249 fprintf (stream
, _("\
3250 -EB assemble code for a big-endian cpu\n"));
3251 fprintf (stream
, _("\
3252 -EL assemble code for a little-endian cpu\n"));
3253 fprintf (stream
, _("\
3254 -mrelax Enable relaxation\n"));
3258 /* Find the proper relocation for the given opcode. */
3260 static extended_bfd_reloc_code_real_type
3261 find_reloc (const char *name
,
3262 const char *opcodename
,
3263 const struct arc_flags
*pflags
,
3265 extended_bfd_reloc_code_real_type reloc
)
3269 bfd_boolean found_flag
, tmp
;
3270 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3272 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3274 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3276 /* Find the entry. */
3277 if (strcmp (name
, r
->name
))
3279 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3286 unsigned * psflg
= (unsigned *)r
->flags
;
3290 for (j
= 0; j
< nflg
; j
++)
3291 if (!strcmp (pflags
[j
].name
,
3292 arc_flag_operands
[*psflg
].name
))
3313 if (reloc
!= r
->oldreloc
)
3320 if (ret
== BFD_RELOC_UNUSED
)
3321 as_bad (_("Unable to find %s relocation for instruction %s"),
3326 /* All the symbol types that are allowed to be used for
3330 may_relax_expr (expressionS tok
)
3332 /* Check if we have unrelaxable relocs. */
3357 /* Checks if flags are in line with relaxable insn. */
3360 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3361 const struct arc_flags
*pflags
,
3364 unsigned flag_class
,
3369 const struct arc_flag_operand
*flag_opand
;
3370 int i
, counttrue
= 0;
3372 /* Iterate through flags classes. */
3373 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3375 /* Iterate through flags in flag class. */
3376 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3379 flag_opand
= &arc_flag_operands
[flag
];
3380 /* Iterate through flags in ins to compare. */
3381 for (i
= 0; i
< nflgs
; ++i
)
3383 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3394 /* If counttrue == nflgs, then all flags have been found. */
3395 return (counttrue
== nflgs
? TRUE
: FALSE
);
3398 /* Checks if operands are in line with relaxable insn. */
3401 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3402 const expressionS
*tok
,
3405 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3408 while (*operand
!= EMPTY
)
3410 const expressionS
*epr
= &tok
[i
];
3412 if (i
!= 0 && i
>= ntok
)
3418 if (!(epr
->X_op
== O_multiply
3419 || epr
->X_op
== O_divide
3420 || epr
->X_op
== O_modulus
3421 || epr
->X_op
== O_add
3422 || epr
->X_op
== O_subtract
3423 || epr
->X_op
== O_symbol
))
3429 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3433 if (epr
->X_op
!= O_register
)
3438 if (epr
->X_op
!= O_register
)
3441 switch (epr
->X_add_number
)
3443 case 0: case 1: case 2: case 3:
3444 case 12: case 13: case 14: case 15:
3451 case REGISTER_NO_GP
:
3452 if ((epr
->X_op
!= O_register
)
3453 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3458 if (epr
->X_op
!= O_bracket
)
3463 /* Don't understand, bail out. */
3469 operand
= &ins
->operands
[i
];
3472 return (i
== ntok
? TRUE
: FALSE
);
3475 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3478 relax_insn_p (const struct arc_opcode
*opcode
,
3479 const expressionS
*tok
,
3481 const struct arc_flags
*pflags
,
3485 bfd_boolean rv
= FALSE
;
3487 /* Check the relaxation table. */
3488 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3490 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3492 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3493 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3494 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3495 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3498 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3499 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3500 sizeof (expressionS
) * ntok
);
3501 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3502 sizeof (struct arc_flags
) * nflg
);
3503 frag_now
->tc_frag_data
.nflg
= nflg
;
3504 frag_now
->tc_frag_data
.ntok
= ntok
;
3512 /* Turn an opcode description and a set of arguments into
3513 an instruction and a fixup. */
3516 assemble_insn (const struct arc_opcode
*opcode
,
3517 const expressionS
*tok
,
3519 const struct arc_flags
*pflags
,
3521 struct arc_insn
*insn
)
3523 const expressionS
*reloc_exp
= NULL
;
3525 const unsigned char *argidx
;
3528 unsigned char pcrel
= 0;
3529 bfd_boolean needGOTSymbol
;
3530 bfd_boolean has_delay_slot
= FALSE
;
3531 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3533 memset (insn
, 0, sizeof (*insn
));
3534 image
= opcode
->opcode
;
3536 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3537 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3540 /* Handle operands. */
3541 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3543 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3544 const expressionS
*t
= (const expressionS
*) 0;
3546 if ((operand
->flags
& ARC_OPERAND_FAKE
)
3547 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
3550 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3552 /* Duplicate operand, already inserted. */
3564 /* Regardless if we have a reloc or not mark the instruction
3565 limm if it is the case. */
3566 if (operand
->flags
& ARC_OPERAND_LIMM
)
3567 insn
->has_limm
= TRUE
;
3572 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3577 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3579 if (operand
->flags
& ARC_OPERAND_LIMM
)
3580 insn
->limm
= t
->X_add_number
;
3584 /* Ignore brackets. */
3588 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3592 /* Maybe register range. */
3593 if ((t
->X_add_number
== 0)
3594 && contains_register (t
->X_add_symbol
)
3595 && contains_register (t
->X_op_symbol
))
3599 regs
= get_register (t
->X_add_symbol
);
3601 regs
|= get_register (t
->X_op_symbol
);
3602 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3607 /* This operand needs a relocation. */
3608 needGOTSymbol
= FALSE
;
3613 if (opcode
->class == JUMP
)
3614 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3615 _("Unable to use @plt relocatio for insn %s"),
3617 needGOTSymbol
= TRUE
;
3618 reloc
= find_reloc ("plt", opcode
->name
,
3620 operand
->default_reloc
);
3625 needGOTSymbol
= TRUE
;
3626 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3629 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3630 if (ARC_SHORT (opcode
->mask
) || opcode
->class == JUMP
)
3631 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3632 _("Unable to use @pcl relocation for insn %s"),
3636 reloc
= find_reloc ("sda", opcode
->name
,
3638 operand
->default_reloc
);
3642 needGOTSymbol
= TRUE
;
3647 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3650 case O_tpoff9
: /*FIXME! Check for the conditionality of
3652 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3654 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3658 /* Just consider the default relocation. */
3659 reloc
= operand
->default_reloc
;
3663 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3664 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3671 /* sanity checks. */
3672 reloc_howto_type
*reloc_howto
3673 = bfd_reloc_type_lookup (stdoutput
,
3674 (bfd_reloc_code_real_type
) reloc
);
3675 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3676 if (reloc_howto
->rightshift
)
3677 reloc_bitsize
-= reloc_howto
->rightshift
;
3678 if (reloc_bitsize
!= operand
->bits
)
3680 as_bad (_("invalid relocation %s for field"),
3681 bfd_get_reloc_code_name (reloc
));
3686 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3687 as_fatal (_("too many fixups"));
3689 struct arc_fixup
*fixup
;
3690 fixup
= &insn
->fixups
[insn
->nfixups
++];
3692 fixup
->reloc
= reloc
;
3693 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3694 fixup
->pcrel
= pcrel
;
3695 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3702 for (i
= 0; i
< nflg
; i
++)
3704 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3706 /* Check if the instruction has a delay slot. */
3707 if (!strcmp (flg_operand
->name
, "d"))
3708 has_delay_slot
= TRUE
;
3710 /* There is an exceptional case when we cannot insert a flag
3711 just as it is. The .T flag must be handled in relation with
3712 the relative address. */
3713 if (!strcmp (flg_operand
->name
, "t")
3714 || !strcmp (flg_operand
->name
, "nt"))
3716 unsigned bitYoperand
= 0;
3717 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3718 if (!strcmp (flg_operand
->name
, "t"))
3719 if (!strcmp (opcode
->name
, "bbit0")
3720 || !strcmp (opcode
->name
, "bbit1"))
3721 bitYoperand
= arc_NToperand
;
3723 bitYoperand
= arc_Toperand
;
3725 if (!strcmp (opcode
->name
, "bbit0")
3726 || !strcmp (opcode
->name
, "bbit1"))
3727 bitYoperand
= arc_Toperand
;
3729 bitYoperand
= arc_NToperand
;
3731 gas_assert (reloc_exp
!= NULL
);
3732 if (reloc_exp
->X_op
== O_constant
)
3734 /* Check if we have a constant and solved it
3736 offsetT val
= reloc_exp
->X_add_number
;
3737 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3742 struct arc_fixup
*fixup
;
3744 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3745 as_fatal (_("too many fixups"));
3747 fixup
= &insn
->fixups
[insn
->nfixups
++];
3748 fixup
->exp
= *reloc_exp
;
3749 fixup
->reloc
= -bitYoperand
;
3750 fixup
->pcrel
= pcrel
;
3751 fixup
->islong
= FALSE
;
3755 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3756 << flg_operand
->shift
;
3759 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3761 /* Short instruction? */
3762 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
3766 /* Update last insn status. */
3767 arc_last_insns
[1] = arc_last_insns
[0];
3768 arc_last_insns
[0].opcode
= opcode
;
3769 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3770 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3772 /* Check if the current instruction is legally used. */
3773 if (arc_last_insns
[1].has_delay_slot
3774 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3775 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3776 _("A jump/branch instruction in delay slot."));
3780 arc_handle_align (fragS
* fragP
)
3782 if ((fragP
)->fr_type
== rs_align_code
)
3784 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3785 valueT count
= ((fragP
)->fr_next
->fr_address
3786 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3788 (fragP
)->fr_var
= 2;
3790 if (count
& 1)/* Padding in the gap till the next 2-byte
3791 boundary with 0s. */
3796 /* Writing nop_s. */
3797 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
3801 /* Here we decide which fixups can be adjusted to make them relative
3802 to the beginning of the section instead of the symbol. Basically
3803 we need to make sure that the dynamic relocations are done
3804 correctly, so in some cases we force the original symbol to be
3808 tc_arc_fix_adjustable (fixS
*fixP
)
3811 /* Prevent all adjustments to global symbols. */
3812 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
3814 if (S_IS_WEAK (fixP
->fx_addsy
))
3817 /* Adjust_reloc_syms doesn't know about the GOT. */
3818 switch (fixP
->fx_r_type
)
3820 case BFD_RELOC_ARC_GOTPC32
:
3821 case BFD_RELOC_ARC_PLT32
:
3822 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3823 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3824 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3825 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3835 /* Compute the reloc type of an expression EXP. */
3838 arc_check_reloc (expressionS
*exp
,
3839 bfd_reloc_code_real_type
*r_type_p
)
3841 if (*r_type_p
== BFD_RELOC_32
3842 && exp
->X_op
== O_subtract
3843 && exp
->X_op_symbol
!= NULL
3844 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
3845 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
3849 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3852 arc_cons_fix_new (fragS
*frag
,
3856 bfd_reloc_code_real_type r_type
)
3858 r_type
= BFD_RELOC_UNUSED
;
3863 r_type
= BFD_RELOC_8
;
3867 r_type
= BFD_RELOC_16
;
3871 r_type
= BFD_RELOC_24
;
3875 r_type
= BFD_RELOC_32
;
3876 arc_check_reloc (exp
, &r_type
);
3880 r_type
= BFD_RELOC_64
;
3884 as_bad (_("unsupported BFD relocation size %u"), size
);
3885 r_type
= BFD_RELOC_UNUSED
;
3888 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
3891 /* The actual routine that checks the ZOL conditions. */
3894 check_zol (symbolS
*s
)
3896 switch (arc_mach_type
)
3898 case bfd_mach_arc_arcv2
:
3899 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3902 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
3903 || arc_last_insns
[1].has_delay_slot
)
3904 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3908 case bfd_mach_arc_arc600
:
3910 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
3911 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3914 if (arc_last_insns
[0].has_limm
3915 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3916 as_bad (_("A jump instruction with long immediate detected at the \
3917 end of the ZOL label @%s"), S_GET_NAME (s
));
3920 case bfd_mach_arc_nps400
:
3921 case bfd_mach_arc_arc700
:
3922 if (arc_last_insns
[0].has_delay_slot
)
3923 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3932 /* If ZOL end check the last two instruction for illegals. */
3934 arc_frob_label (symbolS
* sym
)
3936 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
3939 dwarf2_emit_label (sym
);
3942 /* Used because generic relaxation assumes a pc-rel value whilst we
3943 also relax instructions that use an absolute value resolved out of
3944 relative values (if that makes any sense). An example: 'add r1,
3945 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3946 but if they're in the same section we can subtract the section
3947 offset relocation which ends up in a resolved value. So if @.L2 is
3948 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3949 .text + 0x40 = 0x10. */
3951 arc_pcrel_adjust (fragS
*fragP
)
3953 if (!fragP
->tc_frag_data
.pcrel
)
3954 return fragP
->fr_address
+ fragP
->fr_fix
;
3959 /* Initialize the DWARF-2 unwind information for this procedure. */
3962 tc_arc_frame_initial_instructions (void)
3964 /* Stack pointer is register 28. */
3965 cfi_add_CFA_def_cfa_register (28);
3969 tc_arc_regname_to_dw2regnum (char *regname
)
3973 sym
= hash_find (arc_reg_hash
, regname
);
3975 return S_GET_VALUE (sym
);
3980 /* Adjust the symbol table. Delete found AUX register symbols. */
3983 arc_adjust_symtab (void)
3987 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
3989 /* I've created a symbol during parsing process. Now, remove
3990 the symbol as it is found to be an AUX register. */
3991 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
3992 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
3995 /* Now do generic ELF adjustments. */
3996 elf_adjust_symtab ();
4000 tokenize_extinsn (extInstruction_t
*einsn
)
4004 unsigned char major_opcode
;
4005 unsigned char sub_opcode
;
4006 unsigned char syntax_class
= 0;
4007 unsigned char syntax_class_modifiers
= 0;
4008 unsigned char suffix_class
= 0;
4013 /* 1st: get instruction name. */
4014 p
= input_line_pointer
;
4015 c
= get_symbol_name (&p
);
4017 insn_name
= xstrdup (p
);
4018 restore_line_pointer (c
);
4020 /* 2nd: get major opcode. */
4021 if (*input_line_pointer
!= ',')
4023 as_bad (_("expected comma after instruction name"));
4024 ignore_rest_of_line ();
4027 input_line_pointer
++;
4028 major_opcode
= get_absolute_expression ();
4030 /* 3rd: get sub-opcode. */
4033 if (*input_line_pointer
!= ',')
4035 as_bad (_("expected comma after major opcode"));
4036 ignore_rest_of_line ();
4039 input_line_pointer
++;
4040 sub_opcode
= get_absolute_expression ();
4042 /* 4th: get suffix class. */
4045 if (*input_line_pointer
!= ',')
4047 as_bad ("expected comma after sub opcode");
4048 ignore_rest_of_line ();
4051 input_line_pointer
++;
4057 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4059 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4060 suffixclass
[i
].len
))
4062 suffix_class
|= suffixclass
[i
].class;
4063 input_line_pointer
+= suffixclass
[i
].len
;
4068 if (i
== ARRAY_SIZE (suffixclass
))
4070 as_bad ("invalid suffix class");
4071 ignore_rest_of_line ();
4077 if (*input_line_pointer
== '|')
4078 input_line_pointer
++;
4083 /* 5th: get syntax class and syntax class modifiers. */
4084 if (*input_line_pointer
!= ',')
4086 as_bad ("expected comma after suffix class");
4087 ignore_rest_of_line ();
4090 input_line_pointer
++;
4096 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4098 if (!strncmp (syntaxclassmod
[i
].name
,
4100 syntaxclassmod
[i
].len
))
4102 syntax_class_modifiers
|= syntaxclassmod
[i
].class;
4103 input_line_pointer
+= syntaxclassmod
[i
].len
;
4108 if (i
== ARRAY_SIZE (syntaxclassmod
))
4110 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4112 if (!strncmp (syntaxclass
[i
].name
,
4114 syntaxclass
[i
].len
))
4116 syntax_class
|= syntaxclass
[i
].class;
4117 input_line_pointer
+= syntaxclass
[i
].len
;
4122 if (i
== ARRAY_SIZE (syntaxclass
))
4124 as_bad ("missing syntax class");
4125 ignore_rest_of_line ();
4132 if (*input_line_pointer
== '|')
4133 input_line_pointer
++;
4138 demand_empty_rest_of_line ();
4140 einsn
->name
= insn_name
;
4141 einsn
->major
= major_opcode
;
4142 einsn
->minor
= sub_opcode
;
4143 einsn
->syntax
= syntax_class
;
4144 einsn
->modsyn
= syntax_class_modifiers
;
4145 einsn
->suffix
= suffix_class
;
4146 einsn
->flags
= syntax_class
4147 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4150 /* Generate an extension section. */
4153 arc_set_ext_seg (void)
4155 if (!arcext_section
)
4157 arcext_section
= subseg_new (".arcextmap", 0);
4158 bfd_set_section_flags (stdoutput
, arcext_section
,
4159 SEC_READONLY
| SEC_HAS_CONTENTS
);
4162 subseg_set (arcext_section
, 0);
4166 /* Create an extension instruction description in the arc extension
4167 section of the output file.
4168 The structure for an instruction is like this:
4169 [0]: Length of the record.
4170 [1]: Type of the record.
4174 [4]: Syntax (flags).
4175 [5]+ Name instruction.
4177 The sequence is terminated by an empty entry. */
4180 create_extinst_section (extInstruction_t
*einsn
)
4183 segT old_sec
= now_seg
;
4184 int old_subsec
= now_subseg
;
4186 int name_len
= strlen (einsn
->name
);
4191 *p
= 5 + name_len
+ 1;
4193 *p
= EXT_INSTRUCTION
;
4200 p
= frag_more (name_len
+ 1);
4201 strcpy (p
, einsn
->name
);
4203 subseg_set (old_sec
, old_subsec
);
4206 /* Handler .extinstruction pseudo-op. */
4209 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4211 extInstruction_t einsn
;
4212 struct arc_opcode
*arc_ext_opcodes
;
4213 const char *errmsg
= NULL
;
4214 unsigned char moplow
, mophigh
;
4216 memset (&einsn
, 0, sizeof (einsn
));
4217 tokenize_extinsn (&einsn
);
4219 /* Check if the name is already used. */
4220 if (arc_find_opcode (einsn
.name
))
4221 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4223 /* Check the opcode ranges. */
4225 mophigh
= (arc_target
& (ARC_OPCODE_ARCv2EM
4226 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4228 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4229 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4231 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4232 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4233 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4235 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4237 case ARC_SYNTAX_3OP
:
4238 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4239 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4241 case ARC_SYNTAX_2OP
:
4242 case ARC_SYNTAX_1OP
:
4243 case ARC_SYNTAX_NOP
:
4244 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4245 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4251 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, arc_target
, &errmsg
);
4252 if (arc_ext_opcodes
== NULL
)
4255 as_fatal ("%s", errmsg
);
4257 as_fatal (_("Couldn't generate extension instruction opcodes"));
4260 as_warn ("%s", errmsg
);
4262 /* Insert the extension instruction. */
4263 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4265 create_extinst_section (&einsn
);
4269 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4275 int number
, imode
= 0;
4276 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4277 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4278 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4280 /* 1st: get register name. */
4282 p
= input_line_pointer
;
4283 c
= get_symbol_name (&p
);
4286 restore_line_pointer (c
);
4288 /* 2nd: get register number. */
4291 if (*input_line_pointer
!= ',')
4293 as_bad (_("expected comma after register name"));
4294 ignore_rest_of_line ();
4298 input_line_pointer
++;
4299 number
= get_absolute_expression ();
4303 as_bad (_("negative operand number %d"), number
);
4304 ignore_rest_of_line ();
4311 /* 3rd: get register mode. */
4314 if (*input_line_pointer
!= ',')
4316 as_bad (_("expected comma after register number"));
4317 ignore_rest_of_line ();
4322 input_line_pointer
++;
4323 mode
= input_line_pointer
;
4325 if (!strncmp (mode
, "r|w", 3))
4328 input_line_pointer
+= 3;
4330 else if (!strncmp (mode
, "r", 1))
4332 imode
= ARC_REGISTER_READONLY
;
4333 input_line_pointer
+= 1;
4335 else if (strncmp (mode
, "w", 1))
4337 as_bad (_("invalid mode"));
4338 ignore_rest_of_line ();
4344 imode
= ARC_REGISTER_WRITEONLY
;
4345 input_line_pointer
+= 1;
4351 /* 4th: get core register shortcut. */
4353 if (*input_line_pointer
!= ',')
4355 as_bad (_("expected comma after register mode"));
4356 ignore_rest_of_line ();
4361 input_line_pointer
++;
4363 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4365 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4366 input_line_pointer
+= 15;
4368 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4370 as_bad (_("shortcut designator invalid"));
4371 ignore_rest_of_line ();
4377 input_line_pointer
+= 12;
4380 demand_empty_rest_of_line ();
4383 ereg
->number
= number
;
4384 ereg
->imode
= imode
;
4387 /* Create an extension register/condition description in the arc
4388 extension section of the output file.
4390 The structure for an instruction is like this:
4391 [0]: Length of the record.
4392 [1]: Type of the record.
4394 For core regs and condition codes:
4398 For auxilirary registers:
4402 The sequence is terminated by an empty entry. */
4405 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4407 segT old_sec
= now_seg
;
4408 int old_subsec
= now_subseg
;
4410 int name_len
= strlen (ereg
->name
);
4417 case EXT_CORE_REGISTER
:
4419 *p
= 3 + name_len
+ 1;
4425 case EXT_AUX_REGISTER
:
4427 *p
= 6 + name_len
+ 1;
4429 *p
= EXT_AUX_REGISTER
;
4431 *p
= (ereg
->number
>> 24) & 0xff;
4433 *p
= (ereg
->number
>> 16) & 0xff;
4435 *p
= (ereg
->number
>> 8) & 0xff;
4437 *p
= (ereg
->number
) & 0xff;
4443 p
= frag_more (name_len
+ 1);
4444 strcpy (p
, ereg
->name
);
4446 subseg_set (old_sec
, old_subsec
);
4449 /* Handler .extCoreRegister pseudo-op. */
4452 arc_extcorereg (int opertype
)
4455 struct arc_aux_reg
*auxr
;
4457 struct arc_flag_operand
*ccode
;
4459 memset (&ereg
, 0, sizeof (ereg
));
4460 tokenize_extregister (&ereg
, opertype
);
4464 case EXT_CORE_REGISTER
:
4465 /* Core register. */
4466 if (ereg
.number
> 60)
4467 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4469 declare_register (ereg
.name
, ereg
.number
);
4471 case EXT_AUX_REGISTER
:
4472 /* Auxiliary register. */
4473 auxr
= XNEW (struct arc_aux_reg
);
4474 auxr
->name
= ereg
.name
;
4475 auxr
->cpu
= arc_target
;
4476 auxr
->subclass
= NONE
;
4477 auxr
->address
= ereg
.number
;
4478 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4480 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4481 auxr
->name
, retval
);
4484 /* Condition code. */
4485 if (ereg
.number
> 31)
4486 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4488 ext_condcode
.size
++;
4489 ext_condcode
.arc_ext_condcode
=
4490 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4491 ext_condcode
.size
+ 1);
4492 if (ext_condcode
.arc_ext_condcode
== NULL
)
4493 as_fatal (_("Virtual memory exhausted"));
4495 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4496 ccode
->name
= ereg
.name
;
4497 ccode
->code
= ereg
.number
;
4500 ccode
->favail
= 0; /* not used. */
4502 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4505 as_bad (_("Unknown extension"));
4508 create_extcore_section (&ereg
, opertype
);
4512 eval: (c-set-style "gnu")