1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 #ifndef TARGET_WITH_CPU
55 #define TARGET_WITH_CPU "arc700"
56 #endif /* TARGET_WITH_CPU */
58 /* Enum used to enumerate the relaxable ins operands. */
63 REGISTER_S
, /* Register for short instruction(s). */
64 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
65 REGISTER_DUP
, /* Duplication of previous operand of type register. */
99 #define regno(x) ((x) & 0x3F)
100 #define is_ir_num(x) (((x) & ~0x3F) == 0)
101 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
102 #define is_spfp_p(op) (((sc) == SPX))
103 #define is_dpfp_p(op) (((sc) == DPX))
104 #define is_fpuda_p(op) (((sc) == DPA))
105 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
106 || (op)->insn_class == JUMP))
107 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
108 #define is_nps400_p(op) (((sc) == NPS400))
110 /* Generic assembler global variables which must be defined by all
113 /* Characters which always start a comment. */
114 const char comment_chars
[] = "#;";
116 /* Characters which start a comment at the beginning of a line. */
117 const char line_comment_chars
[] = "#";
119 /* Characters which may be used to separate multiple commands on a
121 const char line_separator_chars
[] = "`";
123 /* Characters which are used to indicate an exponent in a floating
125 const char EXP_CHARS
[] = "eE";
127 /* Chars that mean this number is a floating point constant
128 As in 0f12.456 or 0d1.2345e12. */
129 const char FLT_CHARS
[] = "rRsSfFdD";
132 extern int target_big_endian
;
133 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
134 static int byte_order
= DEFAULT_BYTE_ORDER
;
136 /* Arc extension section. */
137 static segT arcext_section
;
139 /* By default relaxation is disabled. */
140 static int relaxation_state
= 0;
142 extern int arc_get_mach (char *);
144 /* Forward declarations. */
145 static void arc_lcomm (int);
146 static void arc_option (int);
147 static void arc_extra_reloc (int);
148 static void arc_extinsn (int);
149 static void arc_extcorereg (int);
151 const pseudo_typeS md_pseudo_table
[] =
153 /* Make sure that .word is 32 bits. */
156 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
157 { "lcomm", arc_lcomm
, 0 },
158 { "lcommon", arc_lcomm
, 0 },
159 { "cpu", arc_option
, 0 },
161 { "extinstruction", arc_extinsn
, 0 },
162 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
163 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
164 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
166 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
167 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
172 const char *md_shortopts
= "";
176 OPTION_EB
= OPTION_MD_BASE
,
194 /* The following options are deprecated and provided here only for
195 compatibility reasons. */
218 struct option md_longopts
[] =
220 { "EB", no_argument
, NULL
, OPTION_EB
},
221 { "EL", no_argument
, NULL
, OPTION_EL
},
222 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
223 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
224 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
225 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
226 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
227 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
228 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
229 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
230 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
231 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
232 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
234 /* Floating point options */
235 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
236 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
237 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
238 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
239 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
240 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
241 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
242 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
243 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
244 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
245 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
247 /* The following options are deprecated and provided here only for
248 compatibility reasons. */
249 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
250 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
251 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
252 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
253 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
254 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
255 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
256 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
257 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
258 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
259 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
260 { "mea", no_argument
, NULL
, OPTION_EA
},
261 { "mEA", no_argument
, NULL
, OPTION_EA
},
262 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
263 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
264 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
265 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
266 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
267 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
268 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
269 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
270 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
271 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
272 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
273 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
274 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
275 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
276 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
278 { NULL
, no_argument
, NULL
, 0 }
281 size_t md_longopts_size
= sizeof (md_longopts
);
283 /* Local data and data types. */
285 /* Used since new relocation types are introduced in this
286 file (DUMMY_RELOC_LITUSE_*). */
287 typedef int extended_bfd_reloc_code_real_type
;
293 extended_bfd_reloc_code_real_type reloc
;
295 /* index into arc_operands. */
296 unsigned int opindex
;
298 /* PC-relative, used by internals fixups. */
301 /* TRUE if this fixup is for LIMM operand. */
307 unsigned long long int insn
;
309 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
311 unsigned int len
; /* Length of instruction in bytes. */
312 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
314 bfd_boolean relax
; /* Boolean value: TRUE if needs
318 /* Structure to hold any last two instructions. */
319 static struct arc_last_insn
321 /* Saved instruction opcode. */
322 const struct arc_opcode
*opcode
;
324 /* Boolean value: TRUE if current insn is short. */
325 bfd_boolean has_limm
;
327 /* Boolean value: TRUE if current insn has delay slot. */
328 bfd_boolean has_delay_slot
;
331 /* Extension instruction suffix classes. */
339 static const attributes_t suffixclass
[] =
341 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
342 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
343 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
346 /* Extension instruction syntax classes. */
347 static const attributes_t syntaxclass
[] =
349 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
350 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
351 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
352 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
355 /* Extension instruction syntax classes modifiers. */
356 static const attributes_t syntaxclassmod
[] =
358 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
359 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
362 /* Extension register type. */
370 /* A structure to hold the additional conditional codes. */
373 struct arc_flag_operand
*arc_ext_condcode
;
375 } ext_condcode
= { NULL
, 0 };
377 /* Structure to hold an entry in ARC_OPCODE_HASH. */
378 struct arc_opcode_hash_entry
380 /* The number of pointers in the OPCODE list. */
383 /* Points to a list of opcode pointers. */
384 const struct arc_opcode
**opcode
;
387 /* Structure used for iterating through an arc_opcode_hash_entry. */
388 struct arc_opcode_hash_entry_iterator
390 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
393 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
394 returned by this iterator. */
395 const struct arc_opcode
*opcode
;
398 /* Forward declaration. */
399 static void assemble_insn
400 (const struct arc_opcode
*, const expressionS
*, int,
401 const struct arc_flags
*, int, struct arc_insn
*);
403 /* The selection of the machine type can come from different sources. This
404 enum is used to track how the selection was made in order to perform
406 enum mach_selection_type
409 MACH_SELECTION_FROM_DEFAULT
,
410 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
411 MACH_SELECTION_FROM_COMMAND_LINE
414 /* How the current machine type was selected. */
415 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
417 /* The hash table of instruction opcodes. */
418 static struct hash_control
*arc_opcode_hash
;
420 /* The hash table of register symbols. */
421 static struct hash_control
*arc_reg_hash
;
423 /* The hash table of aux register symbols. */
424 static struct hash_control
*arc_aux_hash
;
426 /* The hash table of address types. */
427 static struct hash_control
*arc_addrtype_hash
;
429 /* A table of CPU names and opcode sets. */
430 static const struct cpu_type
440 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
441 E_ARC_MACH_ARC600
, 0x00},
442 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
443 E_ARC_MACH_ARC700
, 0x00},
444 { "nps400", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
445 E_ARC_MACH_ARC700
, ARC_NPS400
},
446 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
447 EF_ARC_CPU_ARCV2EM
, 0x00},
448 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
449 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
453 /* Information about the cpu/variant we're assembling for. */
454 static struct cpu_type selected_cpu
;
456 /* Used by the arc_reloc_op table. Order is important. */
457 #define O_gotoff O_md1 /* @gotoff relocation. */
458 #define O_gotpc O_md2 /* @gotpc relocation. */
459 #define O_plt O_md3 /* @plt relocation. */
460 #define O_sda O_md4 /* @sda relocation. */
461 #define O_pcl O_md5 /* @pcl relocation. */
462 #define O_tlsgd O_md6 /* @tlsgd relocation. */
463 #define O_tlsie O_md7 /* @tlsie relocation. */
464 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
465 #define O_tpoff O_md9 /* @tpoff relocation. */
466 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
467 #define O_dtpoff O_md11 /* @dtpoff relocation. */
468 #define O_last O_dtpoff
470 /* Used to define a bracket as operand in tokens. */
471 #define O_bracket O_md32
473 /* Used to define a colon as an operand in tokens. */
474 #define O_colon O_md31
476 /* Used to define address types in nps400. */
477 #define O_addrtype O_md30
479 /* Dummy relocation, to be sorted out. */
480 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
482 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
484 /* A table to map the spelling of a relocation operand into an appropriate
485 bfd_reloc_code_real_type type. The table is assumed to be ordered such
486 that op-O_literal indexes into it. */
487 #define ARC_RELOC_TABLE(op) \
488 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
490 : (int) (op) - (int) O_gotoff) ])
492 #define DEF(NAME, RELOC, REQ) \
493 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
495 static const struct arc_reloc_op_tag
497 /* String to lookup. */
499 /* Size of the string. */
501 /* Which operator to use. */
503 extended_bfd_reloc_code_real_type reloc
;
504 /* Allows complex relocation expression like identifier@reloc +
506 unsigned int complex_expr
: 1;
510 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
511 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
512 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
513 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
514 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
515 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
516 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
517 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
518 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
519 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
520 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
523 static const int arc_num_reloc_op
524 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
526 /* Structure for relaxable instruction that have to be swapped with a
527 smaller alternative instruction. */
528 struct arc_relaxable_ins
530 /* Mnemonic that should be checked. */
531 const char *mnemonic_r
;
533 /* Operands that should be checked.
534 Indexes of operands from operand array. */
535 enum rlx_operand_type operands
[6];
537 /* Flags that should be checked. */
538 unsigned flag_classes
[5];
540 /* Mnemonic (smaller) alternative to be used later for relaxation. */
541 const char *mnemonic_alt
;
543 /* Index of operand that generic relaxation has to check. */
546 /* Base subtype index used. */
547 enum arc_rlx_types subtype
;
550 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
551 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
552 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
556 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
557 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
558 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
563 /* ARC relaxation table. */
564 const relax_typeS md_relax_table
[] =
571 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
572 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
576 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
577 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
582 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
583 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
584 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
586 /* LD_S a, [b, u7] ->
587 LD<zz><.x><.aa><.di> a, [b, s9] ->
588 LD<zz><.x><.aa><.di> a, [b, limm] */
589 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
590 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
591 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
596 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
597 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
598 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
602 SUB<.f> a, b, limm. */
603 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
604 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
605 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
607 /* MPY<.f> a, b, u6 ->
608 MPY<.f> a, b, limm. */
609 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
610 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
612 /* MOV<.f><.cc> b, u6 ->
613 MOV<.f><.cc> b, limm. */
614 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
615 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
617 /* ADD<.f><.cc> b, b, u6 ->
618 ADD<.f><.cc> b, b, limm. */
619 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
620 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
623 /* Order of this table's entries matters! */
624 const struct arc_relaxable_ins arc_relaxable_insns
[] =
626 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
627 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
628 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
629 2, ARC_RLX_ADD_RRU6
},
630 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
632 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
634 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
635 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
636 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
637 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
638 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
639 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
640 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
641 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
643 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
645 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
649 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
651 /* Flags to set in the elf header. */
652 static const flagword arc_initial_eflag
= 0x00;
654 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
655 symbolS
* GOT_symbol
= 0;
657 /* Set to TRUE when we assemble instructions. */
658 static bfd_boolean assembling_insn
= FALSE
;
660 /* Functions implementation. */
662 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
663 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
664 are no matching entries in ARC_OPCODE_HASH. */
666 static const struct arc_opcode_hash_entry
*
667 arc_find_opcode (const char *name
)
669 const struct arc_opcode_hash_entry
*entry
;
671 entry
= hash_find (arc_opcode_hash
, name
);
675 /* Initialise the iterator ITER. */
678 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
684 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
685 calls to this function. Return NULL when all ARC_OPCODE entries have
688 static const struct arc_opcode
*
689 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
690 struct arc_opcode_hash_entry_iterator
*iter
)
692 if (iter
->opcode
== NULL
&& iter
->index
== 0)
694 gas_assert (entry
->count
> 0);
695 iter
->opcode
= entry
->opcode
[iter
->index
];
697 else if (iter
->opcode
!= NULL
)
699 const char *old_name
= iter
->opcode
->name
;
702 if (iter
->opcode
->name
== NULL
703 || strcmp (old_name
, iter
->opcode
->name
) != 0)
706 if (iter
->index
== entry
->count
)
709 iter
->opcode
= entry
->opcode
[iter
->index
];
716 /* Insert an opcode into opcode hash structure. */
719 arc_insert_opcode (const struct arc_opcode
*opcode
)
721 const char *name
, *retval
;
722 struct arc_opcode_hash_entry
*entry
;
725 entry
= hash_find (arc_opcode_hash
, name
);
728 entry
= XNEW (struct arc_opcode_hash_entry
);
730 entry
->opcode
= NULL
;
732 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
734 as_fatal (_("internal error: can't hash opcode '%s': %s"),
738 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
741 if (entry
->opcode
== NULL
)
742 as_fatal (_("Virtual memory exhausted"));
744 entry
->opcode
[entry
->count
] = opcode
;
749 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
750 value, is encoded as 'middle-endian' for a little-endian target. This
751 function is used for regular 4, 6, and 8 byte instructions as well. */
754 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
759 md_number_to_chars (buf
, val
, n
);
762 md_number_to_chars (buf
, (val
& 0xffff00000000) >> 32, 2);
763 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
766 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
767 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
770 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000) >> 32, 4);
771 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
778 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
779 the relevant static global variables. Parameter SEL describes where
780 this selection originated from. */
783 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
788 /* We should only set a default if we've not made a selection from some
790 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
791 || mach_selection_mode
== MACH_SELECTION_NONE
);
793 /* Look for a matching entry in CPU_TYPES array. */
794 for (i
= 0; cpu_types
[i
].name
; ++i
)
796 if (!strcasecmp (cpu_types
[i
].name
, arg
))
798 /* If a previous selection was made on the command line, then we
799 allow later selections on the command line to override earlier
800 ones. However, a selection from a '.cpu NAME' directive must
801 match the command line selection, or we give a warning. */
802 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
804 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
805 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
806 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
807 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
809 as_warn (_("Command-line value overrides \".cpu\" directive"));
814 /* Initialise static global data about selected machine type. */
815 selected_cpu
.flags
= cpu_types
[i
].flags
;
816 selected_cpu
.name
= cpu_types
[i
].name
;
817 selected_cpu
.features
= cpu_types
[i
].features
;
818 selected_cpu
.mach
= cpu_types
[i
].mach
;
819 cpu_flags
= cpu_types
[i
].eflags
;
824 if (!cpu_types
[i
].name
)
825 as_fatal (_("unknown architecture: %s\n"), arg
);
826 gas_assert (cpu_flags
!= 0);
827 selected_cpu
.eflags
= (arc_initial_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
828 mach_selection_mode
= sel
;
831 /* Here ends all the ARCompact extension instruction assembling
835 arc_extra_reloc (int r_type
)
838 symbolS
*sym
, *lab
= NULL
;
840 if (*input_line_pointer
== '@')
841 input_line_pointer
++;
842 c
= get_symbol_name (&sym_name
);
843 sym
= symbol_find_or_make (sym_name
);
844 restore_line_pointer (c
);
845 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
847 ++input_line_pointer
;
849 c
= get_symbol_name (&lab_name
);
850 lab
= symbol_find_or_make (lab_name
);
851 restore_line_pointer (c
);
854 /* These relocations exist as a mechanism for the compiler to tell the
855 linker how to patch the code if the tls model is optimised. However,
856 the relocation itself does not require any space within the assembler
857 fragment, and so we pass a size of 0.
859 The lines that generate these relocations look like this:
861 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
863 The '.tls_gd_ld @.tdata' is processed first and generates the
864 additional relocation, while the 'bl __tls_get_addr@plt' is processed
865 second and generates the additional branch.
867 It is possible that the additional relocation generated by the
868 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
869 while the 'bl __tls_get_addr@plt' will be generated as the first thing
870 in the next fragment. This will be fine; both relocations will still
871 appear to be at the same address in the generated object file.
872 However, this only works as the additional relocation is generated
873 with size of 0 bytes. */
875 = fix_new (frag_now
, /* Which frag? */
876 frag_now_fix (), /* Where in that frag? */
877 0, /* size: 1, 2, or 4 usually. */
878 sym
, /* X_add_symbol. */
879 0, /* X_add_number. */
880 FALSE
, /* TRUE if PC-relative relocation. */
881 r_type
/* Relocation type. */);
882 fixP
->fx_subsy
= lab
;
886 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
887 symbolS
*symbolP
, addressT size
)
892 if (*input_line_pointer
== ',')
894 align
= parse_align (1);
896 if (align
== (addressT
) -1)
911 bss_alloc (symbolP
, size
, align
);
912 S_CLEAR_EXTERNAL (symbolP
);
918 arc_lcomm (int ignore
)
920 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
923 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
926 /* Select the cpu we're assembling for. */
929 arc_option (int ignore ATTRIBUTE_UNUSED
)
933 const char *cpu_name
;
935 c
= get_symbol_name (&cpu
);
937 if ((!strcmp ("ARC600", cpu
))
938 || (!strcmp ("ARC601", cpu
))
939 || (!strcmp ("A6", cpu
)))
941 else if ((!strcmp ("ARC700", cpu
))
942 || (!strcmp ("A7", cpu
)))
944 else if (!strcmp ("EM", cpu
))
946 else if (!strcmp ("HS", cpu
))
948 else if (!strcmp ("NPS400", cpu
))
953 if (cpu_name
!= NULL
)
954 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
956 as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu
);
958 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
959 as_fatal (_("could not set architecture and machine"));
961 /* Set elf header flags. */
962 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
964 restore_line_pointer (c
);
965 demand_empty_rest_of_line ();
968 /* Smartly print an expression. */
971 debug_exp (expressionS
*t
)
973 const char *name ATTRIBUTE_UNUSED
;
974 const char *namemd ATTRIBUTE_UNUSED
;
976 pr_debug ("debug_exp: ");
980 default: name
= "unknown"; break;
981 case O_illegal
: name
= "O_illegal"; break;
982 case O_absent
: name
= "O_absent"; break;
983 case O_constant
: name
= "O_constant"; break;
984 case O_symbol
: name
= "O_symbol"; break;
985 case O_symbol_rva
: name
= "O_symbol_rva"; break;
986 case O_register
: name
= "O_register"; break;
987 case O_big
: name
= "O_big"; break;
988 case O_uminus
: name
= "O_uminus"; break;
989 case O_bit_not
: name
= "O_bit_not"; break;
990 case O_logical_not
: name
= "O_logical_not"; break;
991 case O_multiply
: name
= "O_multiply"; break;
992 case O_divide
: name
= "O_divide"; break;
993 case O_modulus
: name
= "O_modulus"; break;
994 case O_left_shift
: name
= "O_left_shift"; break;
995 case O_right_shift
: name
= "O_right_shift"; break;
996 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
997 case O_bit_or_not
: name
= "O_bit_or_not"; break;
998 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
999 case O_bit_and
: name
= "O_bit_and"; break;
1000 case O_add
: name
= "O_add"; break;
1001 case O_subtract
: name
= "O_subtract"; break;
1002 case O_eq
: name
= "O_eq"; break;
1003 case O_ne
: name
= "O_ne"; break;
1004 case O_lt
: name
= "O_lt"; break;
1005 case O_le
: name
= "O_le"; break;
1006 case O_ge
: name
= "O_ge"; break;
1007 case O_gt
: name
= "O_gt"; break;
1008 case O_logical_and
: name
= "O_logical_and"; break;
1009 case O_logical_or
: name
= "O_logical_or"; break;
1010 case O_index
: name
= "O_index"; break;
1011 case O_bracket
: name
= "O_bracket"; break;
1012 case O_colon
: name
= "O_colon"; break;
1013 case O_addrtype
: name
= "O_addrtype"; break;
1018 default: namemd
= "unknown"; break;
1019 case O_gotoff
: namemd
= "O_gotoff"; break;
1020 case O_gotpc
: namemd
= "O_gotpc"; break;
1021 case O_plt
: namemd
= "O_plt"; break;
1022 case O_sda
: namemd
= "O_sda"; break;
1023 case O_pcl
: namemd
= "O_pcl"; break;
1024 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1025 case O_tlsie
: namemd
= "O_tlsie"; break;
1026 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1027 case O_tpoff
: namemd
= "O_tpoff"; break;
1028 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1029 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1032 pr_debug ("%s (%s, %s, %d, %s)", name
,
1033 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1034 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1035 (int) t
->X_add_number
,
1036 (t
->X_md
) ? namemd
: "--");
1041 /* Parse the arguments to an opcode. */
1044 tokenize_arguments (char *str
,
1048 char *old_input_line_pointer
;
1049 bfd_boolean saw_comma
= FALSE
;
1050 bfd_boolean saw_arg
= FALSE
;
1055 const struct arc_reloc_op_tag
*r
;
1057 char *reloc_name
, c
;
1059 memset (tok
, 0, sizeof (*tok
) * ntok
);
1061 /* Save and restore input_line_pointer around this function. */
1062 old_input_line_pointer
= input_line_pointer
;
1063 input_line_pointer
= str
;
1065 while (*input_line_pointer
)
1068 switch (*input_line_pointer
)
1074 input_line_pointer
++;
1075 if (saw_comma
|| !saw_arg
)
1082 ++input_line_pointer
;
1084 if (!saw_arg
|| num_args
== ntok
)
1086 tok
->X_op
= O_bracket
;
1093 input_line_pointer
++;
1094 if (brk_lvl
|| num_args
== ntok
)
1097 tok
->X_op
= O_bracket
;
1103 input_line_pointer
++;
1104 if (!saw_arg
|| num_args
== ntok
)
1106 tok
->X_op
= O_colon
;
1113 /* We have labels, function names and relocations, all
1114 starting with @ symbol. Sort them out. */
1115 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1119 tok
->X_op
= O_symbol
;
1120 tok
->X_md
= O_absent
;
1122 if (*input_line_pointer
!= '@')
1123 goto normalsymbol
; /* This is not a relocation. */
1127 /* A relocation opernad has the following form
1128 @identifier@relocation_type. The identifier is already
1130 if (tok
->X_op
!= O_symbol
)
1132 as_bad (_("No valid label relocation operand"));
1136 /* Parse @relocation_type. */
1137 input_line_pointer
++;
1138 c
= get_symbol_name (&reloc_name
);
1139 len
= input_line_pointer
- reloc_name
;
1142 as_bad (_("No relocation operand"));
1146 /* Go through known relocation and try to find a match. */
1147 r
= &arc_reloc_op
[0];
1148 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1149 if (len
== r
->length
1150 && memcmp (reloc_name
, r
->name
, len
) == 0)
1154 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1158 *input_line_pointer
= c
;
1159 SKIP_WHITESPACE_AFTER_NAME ();
1160 /* Extra check for TLS: base. */
1161 if (*input_line_pointer
== '@')
1164 if (tok
->X_op_symbol
!= NULL
1165 || tok
->X_op
!= O_symbol
)
1167 as_bad (_("Unable to parse TLS base: %s"),
1168 input_line_pointer
);
1171 input_line_pointer
++;
1173 c
= get_symbol_name (&sym_name
);
1174 base
= symbol_find_or_make (sym_name
);
1175 tok
->X_op
= O_subtract
;
1176 tok
->X_op_symbol
= base
;
1177 restore_line_pointer (c
);
1178 tmpE
.X_add_number
= 0;
1180 if ((*input_line_pointer
!= '+')
1181 && (*input_line_pointer
!= '-'))
1183 tmpE
.X_add_number
= 0;
1187 /* Parse the constant of a complex relocation expression
1188 like @identifier@reloc +/- const. */
1189 if (! r
->complex_expr
)
1191 as_bad (_("@%s is not a complex relocation."), r
->name
);
1195 if (tmpE
.X_op
!= O_constant
)
1197 as_bad (_("Bad expression: @%s + %s."),
1198 r
->name
, input_line_pointer
);
1204 tok
->X_add_number
= tmpE
.X_add_number
;
1215 /* Can be a register. */
1216 ++input_line_pointer
;
1220 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1223 tok
->X_op
= O_absent
;
1224 tok
->X_md
= O_absent
;
1227 /* Legacy: There are cases when we have
1228 identifier@relocation_type, if it is the case parse the
1229 relocation type as well. */
1230 if (*input_line_pointer
== '@')
1236 if (tok
->X_op
== O_illegal
1237 || tok
->X_op
== O_absent
1238 || num_args
== ntok
)
1250 if (saw_comma
|| brk_lvl
)
1252 input_line_pointer
= old_input_line_pointer
;
1258 as_bad (_("Brackets in operand field incorrect"));
1260 as_bad (_("extra comma"));
1262 as_bad (_("missing argument"));
1264 as_bad (_("missing comma or colon"));
1265 input_line_pointer
= old_input_line_pointer
;
1269 /* Parse the flags to a structure. */
1272 tokenize_flags (const char *str
,
1273 struct arc_flags flags
[],
1276 char *old_input_line_pointer
;
1277 bfd_boolean saw_flg
= FALSE
;
1278 bfd_boolean saw_dot
= FALSE
;
1282 memset (flags
, 0, sizeof (*flags
) * nflg
);
1284 /* Save and restore input_line_pointer around this function. */
1285 old_input_line_pointer
= input_line_pointer
;
1286 input_line_pointer
= (char *) str
;
1288 while (*input_line_pointer
)
1290 switch (*input_line_pointer
)
1297 input_line_pointer
++;
1305 if (saw_flg
&& !saw_dot
)
1308 if (num_flags
>= nflg
)
1311 flgnamelen
= strspn (input_line_pointer
,
1312 "abcdefghijklmnopqrstuvwxyz0123456789");
1313 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1316 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1318 input_line_pointer
+= flgnamelen
;
1328 input_line_pointer
= old_input_line_pointer
;
1333 as_bad (_("extra dot"));
1335 as_bad (_("unrecognized flag"));
1337 as_bad (_("failed to parse flags"));
1338 input_line_pointer
= old_input_line_pointer
;
1342 /* Apply the fixups in order. */
1345 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1349 for (i
= 0; i
< insn
->nfixups
; i
++)
1351 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1352 int size
, pcrel
, offset
= 0;
1354 /* FIXME! the reloc size is wrong in the BFD file.
1355 When it is fixed please delete me. */
1356 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1361 /* Some fixups are only used internally, thus no howto. */
1362 if ((int) fixup
->reloc
== 0)
1363 as_fatal (_("Unhandled reloc type"));
1365 if ((int) fixup
->reloc
< 0)
1367 /* FIXME! the reloc size is wrong in the BFD file.
1368 When it is fixed please enable me.
1369 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1370 pcrel
= fixup
->pcrel
;
1374 reloc_howto_type
*reloc_howto
=
1375 bfd_reloc_type_lookup (stdoutput
,
1376 (bfd_reloc_code_real_type
) fixup
->reloc
);
1377 gas_assert (reloc_howto
);
1379 /* FIXME! the reloc size is wrong in the BFD file.
1380 When it is fixed please enable me.
1381 size = bfd_get_reloc_size (reloc_howto); */
1382 pcrel
= reloc_howto
->pc_relative
;
1385 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1387 fragP
->fr_file
, fragP
->fr_line
,
1388 (fixup
->reloc
< 0) ? "Internal" :
1389 bfd_get_reloc_code_name (fixup
->reloc
),
1392 fix_new_exp (fragP
, fix
+ offset
,
1393 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1395 /* Check for ZOLs, and update symbol info if any. */
1396 if (LP_INSN (insn
->insn
))
1398 gas_assert (fixup
->exp
.X_add_symbol
);
1399 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1404 /* Actually output an instruction with its fixup. */
1407 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1412 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1413 pr_debug ("\tLength : 0x%d\n", insn
->len
);
1414 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1416 /* Write out the instruction. */
1417 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1419 f
= frag_more (total_len
);
1421 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1424 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1425 dwarf2_emit_insn (total_len
);
1428 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1432 emit_insn1 (struct arc_insn
*insn
)
1434 /* How frag_var's args are currently configured:
1435 - rs_machine_dependent, to dictate it's a relaxation frag.
1436 - FRAG_MAX_GROWTH, maximum size of instruction
1437 - 0, variable size that might grow...unused by generic relaxation.
1438 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1439 - s, opand expression.
1440 - 0, offset but it's unused.
1441 - 0, opcode but it's unused. */
1442 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1443 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1445 if (frag_room () < FRAG_MAX_GROWTH
)
1447 /* Handle differently when frag literal memory is exhausted.
1448 This is used because when there's not enough memory left in
1449 the current frag, a new frag is created and the information
1450 we put into frag_now->tc_frag_data is disregarded. */
1452 struct arc_relax_type relax_info_copy
;
1453 relax_substateT subtype
= frag_now
->fr_subtype
;
1455 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1456 sizeof (struct arc_relax_type
));
1458 frag_wane (frag_now
);
1459 frag_grow (FRAG_MAX_GROWTH
);
1461 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1462 sizeof (struct arc_relax_type
));
1464 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1468 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1469 frag_now
->fr_subtype
, s
, 0, 0);
1473 emit_insn (struct arc_insn
*insn
)
1478 emit_insn0 (insn
, NULL
, FALSE
);
1481 /* Check whether a symbol involves a register. */
1484 contains_register (symbolS
*sym
)
1488 expressionS
*ex
= symbol_get_value_expression (sym
);
1490 return ((O_register
== ex
->X_op
)
1491 && !contains_register (ex
->X_add_symbol
)
1492 && !contains_register (ex
->X_op_symbol
));
1498 /* Returns the register number within a symbol. */
1501 get_register (symbolS
*sym
)
1503 if (!contains_register (sym
))
1506 expressionS
*ex
= symbol_get_value_expression (sym
);
1507 return regno (ex
->X_add_number
);
1510 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1511 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1514 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1521 case BFD_RELOC_ARC_SDA_LDST
:
1522 case BFD_RELOC_ARC_SDA_LDST1
:
1523 case BFD_RELOC_ARC_SDA_LDST2
:
1524 case BFD_RELOC_ARC_SDA16_LD
:
1525 case BFD_RELOC_ARC_SDA16_LD1
:
1526 case BFD_RELOC_ARC_SDA16_LD2
:
1527 case BFD_RELOC_ARC_SDA16_ST2
:
1528 case BFD_RELOC_ARC_SDA32_ME
:
1535 /* Allocates a tok entry. */
1538 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1540 if (ntok
> MAX_INSN_ARGS
- 2)
1541 return 0; /* No space left. */
1544 return 0; /* Incorect args. */
1546 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1549 return 1; /* Success. */
1550 return allocate_tok (tok
, ntok
- 1, cidx
);
1553 /* Check if an particular ARC feature is enabled. */
1556 check_cpu_feature (insn_subclass_t sc
)
1558 if (is_code_density_p (sc
) && !(selected_cpu
.features
& ARC_CD
))
1561 if (is_spfp_p (sc
) && !(selected_cpu
.features
& ARC_SPFP
))
1564 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& ARC_DPFP
))
1567 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& ARC_FPUDA
))
1570 if (is_nps400_p (sc
) && !(selected_cpu
.features
& ARC_NPS400
))
1576 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1577 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1578 array and returns TRUE if the flag operands all match, otherwise,
1579 returns FALSE, in which case the FIRST_PFLAG array may have been
1583 parse_opcode_flags (const struct arc_opcode
*opcode
,
1585 struct arc_flags
*first_pflag
)
1588 const unsigned char *flgidx
;
1591 for (i
= 0; i
< nflgs
; i
++)
1592 first_pflag
[i
].flgp
= NULL
;
1594 /* Check the flags. Iterate over the valid flag classes. */
1595 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1597 /* Get a valid flag class. */
1598 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1599 const unsigned *flgopridx
;
1601 struct arc_flags
*pflag
= NULL
;
1603 /* Check for extension conditional codes. */
1604 if (ext_condcode
.arc_ext_condcode
1605 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1607 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1610 pflag
= first_pflag
;
1611 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1613 if (!strcmp (pf
->name
, pflag
->name
))
1615 if (pflag
->flgp
!= NULL
)
1628 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1630 const struct arc_flag_operand
*flg_operand
;
1632 pflag
= first_pflag
;
1633 flg_operand
= &arc_flag_operands
[*flgopridx
];
1634 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1636 /* Match against the parsed flags. */
1637 if (!strcmp (flg_operand
->name
, pflag
->name
))
1639 if (pflag
->flgp
!= NULL
)
1642 pflag
->flgp
= flg_operand
;
1644 break; /* goto next flag class and parsed flag. */
1649 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1651 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1655 /* Did I check all the parsed flags? */
1656 return lnflg
? FALSE
: TRUE
;
1660 /* Search forward through all variants of an opcode looking for a
1663 static const struct arc_opcode
*
1664 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1667 struct arc_flags
*first_pflag
,
1671 const struct arc_opcode
*opcode
;
1672 struct arc_opcode_hash_entry_iterator iter
;
1674 int got_cpu_match
= 0;
1675 expressionS bktok
[MAX_INSN_ARGS
];
1679 arc_opcode_hash_entry_iterator_init (&iter
);
1680 memset (&emptyE
, 0, sizeof (emptyE
));
1681 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1684 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1686 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1688 const unsigned char *opidx
;
1690 const expressionS
*t
= &emptyE
;
1692 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1693 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1695 /* Don't match opcodes that don't exist on this
1697 if (!(opcode
->cpu
& selected_cpu
.flags
))
1700 if (!check_cpu_feature (opcode
->subclass
))
1706 /* Check the operands. */
1707 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1709 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1711 /* Only take input from real operands. */
1712 if (ARC_OPERAND_IS_FAKE (operand
))
1715 /* When we expect input, make sure we have it. */
1719 /* Match operand type with expression type. */
1720 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1722 case ARC_OPERAND_ADDRTYPE
:
1723 /* Check to be an address type. */
1724 if (tok
[tokidx
].X_op
!= O_addrtype
)
1728 case ARC_OPERAND_IR
:
1729 /* Check to be a register. */
1730 if ((tok
[tokidx
].X_op
!= O_register
1731 || !is_ir_num (tok
[tokidx
].X_add_number
))
1732 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1735 /* If expect duplicate, make sure it is duplicate. */
1736 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1738 /* Check for duplicate. */
1739 if (t
->X_op
!= O_register
1740 || !is_ir_num (t
->X_add_number
)
1741 || (regno (t
->X_add_number
) !=
1742 regno (tok
[tokidx
].X_add_number
)))
1746 /* Special handling? */
1747 if (operand
->insert
)
1749 const char *errmsg
= NULL
;
1750 (*operand
->insert
)(0,
1751 regno (tok
[tokidx
].X_add_number
),
1755 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1757 /* Missing argument, create one. */
1758 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1761 tok
[tokidx
].X_op
= O_absent
;
1772 case ARC_OPERAND_BRAKET
:
1773 /* Check if bracket is also in opcode table as
1775 if (tok
[tokidx
].X_op
!= O_bracket
)
1779 case ARC_OPERAND_COLON
:
1780 /* Check if colon is also in opcode table as operand. */
1781 if (tok
[tokidx
].X_op
!= O_colon
)
1785 case ARC_OPERAND_LIMM
:
1786 case ARC_OPERAND_SIGNED
:
1787 case ARC_OPERAND_UNSIGNED
:
1788 switch (tok
[tokidx
].X_op
)
1796 /* Got an (too) early bracket, check if it is an
1797 ignored operand. N.B. This procedure works only
1798 when bracket is the last operand! */
1799 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1801 /* Insert the missing operand. */
1802 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1805 tok
[tokidx
].X_op
= O_absent
;
1812 const struct arc_aux_reg
*auxr
;
1814 if (opcode
->insn_class
!= AUXREG
)
1816 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1818 auxr
= hash_find (arc_aux_hash
, p
);
1821 /* We modify the token array here, safe in the
1822 knowledge, that if this was the wrong
1823 choice then the original contents will be
1824 restored from BKTOK. */
1825 tok
[tokidx
].X_op
= O_constant
;
1826 tok
[tokidx
].X_add_number
= auxr
->address
;
1827 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1830 if (tok
[tokidx
].X_op
!= O_constant
)
1835 /* Check the range. */
1836 if (operand
->bits
!= 32
1837 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1839 offsetT min
, max
, val
;
1840 val
= tok
[tokidx
].X_add_number
;
1842 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1844 max
= (1 << (operand
->bits
- 1)) - 1;
1845 min
= -(1 << (operand
->bits
- 1));
1849 max
= (1 << operand
->bits
) - 1;
1853 if (val
< min
|| val
> max
)
1856 /* Check alignmets. */
1857 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1861 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1865 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1867 if (operand
->insert
)
1869 const char *errmsg
= NULL
;
1870 (*operand
->insert
)(0,
1871 tok
[tokidx
].X_add_number
,
1876 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1882 /* Check if it is register range. */
1883 if ((tok
[tokidx
].X_add_number
== 0)
1884 && contains_register (tok
[tokidx
].X_add_symbol
)
1885 && contains_register (tok
[tokidx
].X_op_symbol
))
1889 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1891 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1892 if (operand
->insert
)
1894 const char *errmsg
= NULL
;
1895 (*operand
->insert
)(0,
1908 if (operand
->default_reloc
== 0)
1909 goto match_failed
; /* The operand needs relocation. */
1911 /* Relocs requiring long immediate. FIXME! make it
1912 generic and move it to a function. */
1913 switch (tok
[tokidx
].X_md
)
1922 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1926 if (!generic_reloc_p (operand
->default_reloc
))
1934 /* If expect duplicate, make sure it is duplicate. */
1935 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1937 if (t
->X_op
== O_illegal
1938 || t
->X_op
== O_absent
1939 || t
->X_op
== O_register
1940 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1947 /* Everything else should have been fake. */
1955 /* Setup ready for flag parsing. */
1956 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
1960 /* Possible match -- did we use all of our input? */
1970 /* Restore the original parameters. */
1971 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1976 *pcpumatch
= got_cpu_match
;
1981 /* Swap operand tokens. */
1984 swap_operand (expressionS
*operand_array
,
1986 unsigned destination
)
1988 expressionS cpy_operand
;
1989 expressionS
*src_operand
;
1990 expressionS
*dst_operand
;
1993 if (source
== destination
)
1996 src_operand
= &operand_array
[source
];
1997 dst_operand
= &operand_array
[destination
];
1998 size
= sizeof (expressionS
);
2000 /* Make copy of operand to swap with and swap. */
2001 memcpy (&cpy_operand
, dst_operand
, size
);
2002 memcpy (dst_operand
, src_operand
, size
);
2003 memcpy (src_operand
, &cpy_operand
, size
);
2006 /* Check if *op matches *tok type.
2007 Returns FALSE if they don't match, TRUE if they match. */
2010 pseudo_operand_match (const expressionS
*tok
,
2011 const struct arc_operand_operation
*op
)
2013 offsetT min
, max
, val
;
2015 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2021 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2023 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2025 val
= tok
->X_add_number
+ op
->count
;
2026 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2028 max
= (1 << (operand_real
->bits
- 1)) - 1;
2029 min
= -(1 << (operand_real
->bits
- 1));
2033 max
= (1 << operand_real
->bits
) - 1;
2036 if (min
<= val
&& val
<= max
)
2042 /* Handle all symbols as long immediates or signed 9. */
2043 if (operand_real
->flags
& ARC_OPERAND_LIMM
2044 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2045 && operand_real
->bits
== 9))
2050 if (operand_real
->flags
& ARC_OPERAND_IR
)
2055 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2066 /* Find pseudo instruction in array. */
2068 static const struct arc_pseudo_insn
*
2069 find_pseudo_insn (const char *opname
,
2071 const expressionS
*tok
)
2073 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2074 const struct arc_operand_operation
*op
;
2078 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2080 pseudo_insn
= &arc_pseudo_insns
[i
];
2081 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2083 op
= pseudo_insn
->operand
;
2084 for (j
= 0; j
< ntok
; ++j
)
2085 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2088 /* Found the right instruction. */
2096 /* Assumes the expressionS *tok is of sufficient size. */
2098 static const struct arc_opcode_hash_entry
*
2099 find_special_case_pseudo (const char *opname
,
2103 struct arc_flags
*pflags
)
2105 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2106 const struct arc_operand_operation
*operand_pseudo
;
2107 const struct arc_operand
*operand_real
;
2109 char construct_operand
[MAX_CONSTR_STR
];
2111 /* Find whether opname is in pseudo instruction array. */
2112 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2114 if (pseudo_insn
== NULL
)
2117 /* Handle flag, Limited to one flag at the moment. */
2118 if (pseudo_insn
->flag_r
!= NULL
)
2119 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2120 MAX_INSN_FLGS
- *nflgs
);
2122 /* Handle operand operations. */
2123 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2125 operand_pseudo
= &pseudo_insn
->operand
[i
];
2126 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2128 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2129 && !operand_pseudo
->needs_insert
)
2132 /* Has to be inserted (i.e. this token does not exist yet). */
2133 if (operand_pseudo
->needs_insert
)
2135 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2137 tok
[i
].X_op
= O_bracket
;
2142 /* Check if operand is a register or constant and handle it
2144 if (operand_real
->flags
& ARC_OPERAND_IR
)
2145 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2146 operand_pseudo
->count
);
2148 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2149 operand_pseudo
->count
);
2151 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2155 else if (operand_pseudo
->count
)
2157 /* Operand number has to be adjusted accordingly (by operand
2159 switch (tok
[i
].X_op
)
2162 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2175 /* Swap operands if necessary. Only supports one swap at the
2177 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2179 operand_pseudo
= &pseudo_insn
->operand
[i
];
2181 if (operand_pseudo
->swap_operand_idx
== i
)
2184 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2186 /* Prevent a swap back later by breaking out. */
2190 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2193 static const struct arc_opcode_hash_entry
*
2194 find_special_case_flag (const char *opname
,
2196 struct arc_flags
*pflags
)
2200 unsigned flag_idx
, flag_arr_idx
;
2201 size_t flaglen
, oplen
;
2202 const struct arc_flag_special
*arc_flag_special_opcode
;
2203 const struct arc_opcode_hash_entry
*entry
;
2205 /* Search for special case instruction. */
2206 for (i
= 0; i
< arc_num_flag_special
; i
++)
2208 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2209 oplen
= strlen (arc_flag_special_opcode
->name
);
2211 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2214 /* Found a potential special case instruction, now test for
2216 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2218 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2220 break; /* End of array, nothing found. */
2222 flagnm
= arc_flag_operands
[flag_idx
].name
;
2223 flaglen
= strlen (flagnm
);
2224 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2226 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2228 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2230 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2231 pflags
[*nflgs
].name
[flaglen
] = '\0';
2240 /* Used to find special case opcode. */
2242 static const struct arc_opcode_hash_entry
*
2243 find_special_case (const char *opname
,
2245 struct arc_flags
*pflags
,
2249 const struct arc_opcode_hash_entry
*entry
;
2251 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2254 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2259 /* Given an opcode name, pre-tockenized set of argumenst and the
2260 opcode flags, take it all the way through emission. */
2263 assemble_tokens (const char *opname
,
2266 struct arc_flags
*pflags
,
2269 bfd_boolean found_something
= FALSE
;
2270 const struct arc_opcode_hash_entry
*entry
;
2273 /* Search opcodes. */
2274 entry
= arc_find_opcode (opname
);
2276 /* Couldn't find opcode conventional way, try special cases. */
2278 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2282 const struct arc_opcode
*opcode
;
2284 pr_debug ("%s:%d: assemble_tokens: %s\n",
2285 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2286 found_something
= TRUE
;
2287 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2291 struct arc_insn insn
;
2293 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2299 if (found_something
)
2302 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2304 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2308 as_bad (_("unknown opcode '%s'"), opname
);
2311 /* The public interface to the instruction assembler. */
2314 md_assemble (char *str
)
2317 expressionS tok
[MAX_INSN_ARGS
];
2320 struct arc_flags flags
[MAX_INSN_FLGS
];
2322 /* Split off the opcode. */
2323 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2324 opname
= xmemdup0 (str
, opnamelen
);
2326 /* Signalize we are assmbling the instructions. */
2327 assembling_insn
= TRUE
;
2329 /* Tokenize the flags. */
2330 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2332 as_bad (_("syntax error"));
2336 /* Scan up to the end of the mnemonic which must end in space or end
2339 for (; *str
!= '\0'; str
++)
2343 /* Tokenize the rest of the line. */
2344 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2346 as_bad (_("syntax error"));
2350 /* Finish it off. */
2351 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2352 assembling_insn
= FALSE
;
2355 /* Callback to insert a register into the hash table. */
2358 declare_register (const char *name
, int number
)
2361 symbolS
*regS
= symbol_create (name
, reg_section
,
2362 number
, &zero_address_frag
);
2364 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2366 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2370 /* Construct symbols for each of the general registers. */
2373 declare_register_set (void)
2376 for (i
= 0; i
< 64; ++i
)
2380 sprintf (name
, "r%d", i
);
2381 declare_register (name
, i
);
2382 if ((i
& 0x01) == 0)
2384 sprintf (name
, "r%dr%d", i
, i
+1);
2385 declare_register (name
, i
);
2390 /* Construct a symbol for an address type. */
2393 declare_addrtype (const char *name
, int number
)
2396 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2397 number
, &zero_address_frag
);
2399 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2400 (void *) addrtypeS
);
2402 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2406 /* Port-specific assembler initialization. This function is called
2407 once, at assembler startup time. */
2412 const struct arc_opcode
*opcode
= arc_opcodes
;
2414 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2415 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2417 /* The endianness can be chosen "at the factory". */
2418 target_big_endian
= byte_order
== BIG_ENDIAN
;
2420 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2421 as_warn (_("could not set architecture and machine"));
2423 /* Set elf header flags. */
2424 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2426 /* Set up a hash table for the instructions. */
2427 arc_opcode_hash
= hash_new ();
2428 if (arc_opcode_hash
== NULL
)
2429 as_fatal (_("Virtual memory exhausted"));
2431 /* Initialize the hash table with the insns. */
2434 const char *name
= opcode
->name
;
2436 arc_insert_opcode (opcode
);
2438 while (++opcode
&& opcode
->name
2439 && (opcode
->name
== name
2440 || !strcmp (opcode
->name
, name
)))
2442 }while (opcode
->name
);
2444 /* Register declaration. */
2445 arc_reg_hash
= hash_new ();
2446 if (arc_reg_hash
== NULL
)
2447 as_fatal (_("Virtual memory exhausted"));
2449 declare_register_set ();
2450 declare_register ("gp", 26);
2451 declare_register ("fp", 27);
2452 declare_register ("sp", 28);
2453 declare_register ("ilink", 29);
2454 declare_register ("ilink1", 29);
2455 declare_register ("ilink2", 30);
2456 declare_register ("blink", 31);
2458 /* XY memory registers. */
2459 declare_register ("x0_u0", 32);
2460 declare_register ("x0_u1", 33);
2461 declare_register ("x1_u0", 34);
2462 declare_register ("x1_u1", 35);
2463 declare_register ("x2_u0", 36);
2464 declare_register ("x2_u1", 37);
2465 declare_register ("x3_u0", 38);
2466 declare_register ("x3_u1", 39);
2467 declare_register ("y0_u0", 40);
2468 declare_register ("y0_u1", 41);
2469 declare_register ("y1_u0", 42);
2470 declare_register ("y1_u1", 43);
2471 declare_register ("y2_u0", 44);
2472 declare_register ("y2_u1", 45);
2473 declare_register ("y3_u0", 46);
2474 declare_register ("y3_u1", 47);
2475 declare_register ("x0_nu", 48);
2476 declare_register ("x1_nu", 49);
2477 declare_register ("x2_nu", 50);
2478 declare_register ("x3_nu", 51);
2479 declare_register ("y0_nu", 52);
2480 declare_register ("y1_nu", 53);
2481 declare_register ("y2_nu", 54);
2482 declare_register ("y3_nu", 55);
2484 declare_register ("mlo", 57);
2485 declare_register ("mmid", 58);
2486 declare_register ("mhi", 59);
2488 declare_register ("acc1", 56);
2489 declare_register ("acc2", 57);
2491 declare_register ("lp_count", 60);
2492 declare_register ("pcl", 63);
2494 /* Initialize the last instructions. */
2495 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2497 /* Aux register declaration. */
2498 arc_aux_hash
= hash_new ();
2499 if (arc_aux_hash
== NULL
)
2500 as_fatal (_("Virtual memory exhausted"));
2502 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2504 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2508 if (!(auxr
->cpu
& selected_cpu
.flags
))
2511 if ((auxr
->subclass
!= NONE
)
2512 && !check_cpu_feature (auxr
->subclass
))
2515 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2517 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2518 auxr
->name
, retval
);
2521 /* Address type declaration. */
2522 arc_addrtype_hash
= hash_new ();
2523 if (arc_addrtype_hash
== NULL
)
2524 as_fatal (_("Virtual memory exhausted"));
2526 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2527 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2528 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2529 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2530 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2531 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2532 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2533 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2534 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2535 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2536 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2537 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2538 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2539 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2540 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2541 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2544 /* Write a value out to the object file, using the appropriate
2548 md_number_to_chars (char *buf
,
2552 if (target_big_endian
)
2553 number_to_chars_bigendian (buf
, val
, n
);
2555 number_to_chars_littleendian (buf
, val
, n
);
2558 /* Round up a section size to the appropriate boundary. */
2561 md_section_align (segT segment
,
2564 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2566 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2569 /* The location from which a PC relative jump should be calculated,
2570 given a PC relative reloc. */
2573 md_pcrel_from_section (fixS
*fixP
,
2576 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2578 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2580 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2581 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2582 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2584 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2586 /* The symbol is undefined (or is defined but not in this section).
2587 Let the linker figure it out. */
2591 if ((int) fixP
->fx_r_type
< 0)
2593 /* These are the "internal" relocations. Align them to
2594 32 bit boundary (PCL), for the moment. */
2599 switch (fixP
->fx_r_type
)
2601 case BFD_RELOC_ARC_PC32
:
2602 /* The hardware calculates relative to the start of the
2603 insn, but this relocation is relative to location of the
2604 LIMM, compensate. The base always needs to be
2605 substracted by 4 as we do not support this type of PCrel
2606 relocation for short instructions. */
2609 case BFD_RELOC_ARC_PLT32
:
2610 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2611 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2612 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2613 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2615 case BFD_RELOC_ARC_S21H_PCREL
:
2616 case BFD_RELOC_ARC_S25H_PCREL
:
2617 case BFD_RELOC_ARC_S13_PCREL
:
2618 case BFD_RELOC_ARC_S21W_PCREL
:
2619 case BFD_RELOC_ARC_S25W_PCREL
:
2623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2624 _("unhandled reloc %s in md_pcrel_from_section"),
2625 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2630 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2631 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2632 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2633 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2634 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2639 /* Given a BFD relocation find the coresponding operand. */
2641 static const struct arc_operand
*
2642 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2646 for (i
= 0; i
< arc_num_operands
; i
++)
2647 if (arc_operands
[i
].default_reloc
== reloc
)
2648 return &arc_operands
[i
];
2652 /* Insert an operand value into an instruction. */
2654 static unsigned long long
2655 insert_operand (unsigned long long insn
,
2656 const struct arc_operand
*operand
,
2661 offsetT min
= 0, max
= 0;
2663 if (operand
->bits
!= 32
2664 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2665 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2667 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2669 max
= (1 << (operand
->bits
- 1)) - 1;
2670 min
= -(1 << (operand
->bits
- 1));
2674 max
= (1 << operand
->bits
) - 1;
2678 if (val
< min
|| val
> max
)
2679 as_bad_value_out_of_range (_("operand"),
2680 val
, min
, max
, file
, line
);
2683 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08llx\n",
2684 min
, val
, max
, insn
);
2686 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2688 as_bad_where (file
, line
,
2689 _("Unaligned operand. Needs to be 32bit aligned"));
2691 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2693 as_bad_where (file
, line
,
2694 _("Unaligned operand. Needs to be 16bit aligned"));
2696 if (operand
->insert
)
2698 const char *errmsg
= NULL
;
2700 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2702 as_warn_where (file
, line
, "%s", errmsg
);
2706 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2708 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2710 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2713 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2718 /* Apply a fixup to the object code. At this point all symbol values
2719 should be fully resolved, and we attempt to completely resolve the
2720 reloc. If we can not do that, we determine the correct reloc code
2721 and put it back in the fixup. To indicate that a fixup has been
2722 eliminated, set fixP->fx_done. */
2725 md_apply_fix (fixS
*fixP
,
2729 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2730 valueT value
= *valP
;
2732 symbolS
*fx_addsy
, *fx_subsy
;
2734 segT add_symbol_segment
= absolute_section
;
2735 segT sub_symbol_segment
= absolute_section
;
2736 const struct arc_operand
*operand
= NULL
;
2737 extended_bfd_reloc_code_real_type reloc
;
2739 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2740 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2741 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2742 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2745 fx_addsy
= fixP
->fx_addsy
;
2746 fx_subsy
= fixP
->fx_subsy
;
2751 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2755 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2756 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2757 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2759 resolve_symbol_value (fx_subsy
);
2760 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2762 if (sub_symbol_segment
== absolute_section
)
2764 /* The symbol is really a constant. */
2765 fx_offset
-= S_GET_VALUE (fx_subsy
);
2770 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2771 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2772 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2773 segment_name (add_symbol_segment
),
2774 S_GET_NAME (fx_subsy
),
2775 segment_name (sub_symbol_segment
));
2781 && !S_IS_WEAK (fx_addsy
))
2783 if (add_symbol_segment
== seg
2786 value
+= S_GET_VALUE (fx_addsy
);
2787 value
-= md_pcrel_from_section (fixP
, seg
);
2789 fixP
->fx_pcrel
= FALSE
;
2791 else if (add_symbol_segment
== absolute_section
)
2793 value
= fixP
->fx_offset
;
2794 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2796 fixP
->fx_pcrel
= FALSE
;
2801 fixP
->fx_done
= TRUE
;
2806 && ((S_IS_DEFINED (fx_addsy
)
2807 && S_GET_SEGMENT (fx_addsy
) != seg
)
2808 || S_IS_WEAK (fx_addsy
)))
2809 value
+= md_pcrel_from_section (fixP
, seg
);
2811 switch (fixP
->fx_r_type
)
2813 case BFD_RELOC_ARC_32_ME
:
2814 /* This is a pc-relative value in a LIMM. Adjust it to the
2815 address of the instruction not to the address of the
2816 LIMM. Note: it is not anylonger valid this afirmation as
2817 the linker consider ARC_PC32 a fixup to entire 64 bit
2819 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2822 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2824 case BFD_RELOC_ARC_PC32
:
2825 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2828 if ((int) fixP
->fx_r_type
< 0)
2829 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2835 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2836 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2837 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2838 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2842 /* Now check for TLS relocations. */
2843 reloc
= fixP
->fx_r_type
;
2846 case BFD_RELOC_ARC_TLS_DTPOFF
:
2847 case BFD_RELOC_ARC_TLS_LE_32
:
2851 case BFD_RELOC_ARC_TLS_GD_GOT
:
2852 case BFD_RELOC_ARC_TLS_IE_GOT
:
2853 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2856 case BFD_RELOC_ARC_TLS_GD_LD
:
2857 gas_assert (!fixP
->fx_offset
);
2860 = (S_GET_VALUE (fixP
->fx_subsy
)
2861 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2862 fixP
->fx_subsy
= NULL
;
2864 case BFD_RELOC_ARC_TLS_GD_CALL
:
2865 /* These two relocs are there just to allow ld to change the tls
2866 model for this symbol, by patching the code. The offset -
2867 and scale, if any - will be installed by the linker. */
2868 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2871 case BFD_RELOC_ARC_TLS_LE_S9
:
2872 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2873 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2885 /* Addjust the value if we have a constant. */
2888 /* For hosts with longs bigger than 32-bits make sure that the top
2889 bits of a 32-bit negative value read in by the parser are set,
2890 so that the correct comparisons are made. */
2891 if (value
& 0x80000000)
2892 value
|= (-1UL << 31);
2894 reloc
= fixP
->fx_r_type
;
2902 case BFD_RELOC_ARC_32_PCREL
:
2903 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2906 case BFD_RELOC_ARC_GOTPC32
:
2907 /* I cannot fix an GOTPC relocation because I need to relax it
2908 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2909 as_bad (_("Unsupported operation on reloc"));
2912 case BFD_RELOC_ARC_TLS_DTPOFF
:
2913 case BFD_RELOC_ARC_TLS_LE_32
:
2914 gas_assert (!fixP
->fx_addsy
);
2915 gas_assert (!fixP
->fx_subsy
);
2918 case BFD_RELOC_ARC_GOTOFF
:
2919 case BFD_RELOC_ARC_32_ME
:
2920 case BFD_RELOC_ARC_PC32
:
2921 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2924 case BFD_RELOC_ARC_PLT32
:
2925 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2928 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2929 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2932 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2933 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2936 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2937 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2940 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2941 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2944 case BFD_RELOC_ARC_S25W_PCREL
:
2945 case BFD_RELOC_ARC_S21W_PCREL
:
2946 case BFD_RELOC_ARC_S21H_PCREL
:
2947 case BFD_RELOC_ARC_S25H_PCREL
:
2948 case BFD_RELOC_ARC_S13_PCREL
:
2950 operand
= find_operand_for_reloc (reloc
);
2951 gas_assert (operand
);
2956 if ((int) fixP
->fx_r_type
>= 0)
2957 as_fatal (_("unhandled relocation type %s"),
2958 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2960 /* The rest of these fixups needs to be completely resolved as
2962 if (fixP
->fx_addsy
!= 0
2963 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2965 _("non-absolute expression in constant field"));
2967 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2968 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
2973 if (target_big_endian
)
2975 switch (fixP
->fx_size
)
2978 insn
= bfd_getb32 (fixpos
);
2981 insn
= bfd_getb16 (fixpos
);
2984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2985 _("unknown fixup size"));
2991 switch (fixP
->fx_size
)
2994 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
2997 insn
= bfd_getl16 (fixpos
);
3000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3001 _("unknown fixup size"));
3005 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3006 fixP
->fx_file
, fixP
->fx_line
);
3008 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3011 /* Prepare machine-dependent frags for relaxation.
3013 Called just before relaxation starts. Any symbol that is now undefined
3014 will not become defined.
3016 Return the correct fr_subtype in the frag.
3018 Return the initial "guess for fr_var" to caller. The guess for fr_var
3019 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3020 or fr_var contributes to our returned value.
3022 Although it may not be explicit in the frag, pretend
3023 fr_var starts with a value. */
3026 md_estimate_size_before_relax (fragS
*fragP
,
3031 /* If the symbol is not located within the same section AND it's not
3032 an absolute section, use the maximum. OR if the symbol is a
3033 constant AND the insn is by nature not pc-rel, use the maximum.
3034 OR if the symbol is being equated against another symbol, use the
3035 maximum. OR if the symbol is weak use the maximum. */
3036 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3037 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3038 || (symbol_constant_p (fragP
->fr_symbol
)
3039 && !fragP
->tc_frag_data
.pcrel
)
3040 || symbol_equated_p (fragP
->fr_symbol
)
3041 || S_IS_WEAK (fragP
->fr_symbol
))
3043 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3044 ++fragP
->fr_subtype
;
3047 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3048 fragP
->fr_var
= growth
;
3050 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3051 fragP
->fr_file
, fragP
->fr_line
, growth
);
3056 /* Translate internal representation of relocation info to BFD target
3060 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3064 bfd_reloc_code_real_type code
;
3066 reloc
= XNEW (arelent
);
3067 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3068 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3069 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3071 /* Make sure none of our internal relocations make it this far.
3072 They'd better have been fully resolved by this point. */
3073 gas_assert ((int) fixP
->fx_r_type
> 0);
3075 code
= fixP
->fx_r_type
;
3077 /* if we have something like add gp, pcl,
3078 _GLOBAL_OFFSET_TABLE_@gotpc. */
3079 if (code
== BFD_RELOC_ARC_GOTPC32
3081 && fixP
->fx_addsy
== GOT_symbol
)
3082 code
= BFD_RELOC_ARC_GOTPC
;
3084 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3085 if (reloc
->howto
== NULL
)
3087 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3088 _("cannot represent `%s' relocation in object file"),
3089 bfd_get_reloc_code_name (code
));
3093 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3094 as_fatal (_("internal error? cannot generate `%s' relocation"),
3095 bfd_get_reloc_code_name (code
));
3097 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3099 reloc
->addend
= fixP
->fx_offset
;
3104 /* Perform post-processing of machine-dependent frags after relaxation.
3105 Called after relaxation is finished.
3106 In: Address of frag.
3107 fr_type == rs_machine_dependent.
3108 fr_subtype is what the address relaxed to.
3110 Out: Any fixS:s and constants are set up. */
3113 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3114 segT segment ATTRIBUTE_UNUSED
,
3117 const relax_typeS
*table_entry
;
3119 const struct arc_opcode
*opcode
;
3120 struct arc_insn insn
;
3122 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3124 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3125 dest
= fragP
->fr_literal
+ fix
;
3126 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3128 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3129 "var: %"BFD_VMA_FMT
"d\n",
3130 fragP
->fr_file
, fragP
->fr_line
,
3131 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3133 if (fragP
->fr_subtype
<= 0
3134 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3135 as_fatal (_("no relaxation found for this instruction."));
3137 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3139 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3140 relax_arg
->nflg
, &insn
);
3142 apply_fixups (&insn
, fragP
, fix
);
3144 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3145 gas_assert (table_entry
->rlx_length
== size
);
3146 emit_insn0 (&insn
, dest
, TRUE
);
3148 fragP
->fr_fix
+= table_entry
->rlx_length
;
3152 /* We have no need to default values of symbols. We could catch
3153 register names here, but that is handled by inserting them all in
3154 the symbol table to begin with. */
3157 md_undefined_symbol (char *name
)
3159 /* The arc abi demands that a GOT[0] should be referencible as
3160 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3161 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3163 && (*(name
+1) == 'G')
3164 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3166 && (*(name
+1) == 'D')
3167 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3171 if (symbol_find (name
))
3172 as_bad ("GOT already in symbol table");
3174 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3175 (valueT
) 0, &zero_address_frag
);
3182 /* Turn a string in input_line_pointer into a floating point constant
3183 of type type, and store the appropriate bytes in *litP. The number
3184 of LITTLENUMS emitted is stored in *sizeP. An error message is
3185 returned, or NULL on OK. */
3188 md_atof (int type
, char *litP
, int *sizeP
)
3190 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3193 /* Called for any expression that can not be recognized. When the
3194 function is called, `input_line_pointer' will point to the start of
3198 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3200 char *p
= input_line_pointer
;
3203 input_line_pointer
++;
3204 expressionP
->X_op
= O_symbol
;
3205 expression (expressionP
);
3209 /* This function is called from the function 'expression', it attempts
3210 to parse special names (in our case register names). It fills in
3211 the expression with the identified register. It returns TRUE if
3212 it is a register and FALSE otherwise. */
3215 arc_parse_name (const char *name
,
3216 struct expressionS
*e
)
3220 if (!assembling_insn
)
3223 if (e
->X_op
== O_symbol
)
3226 sym
= hash_find (arc_reg_hash
, name
);
3229 e
->X_op
= O_register
;
3230 e
->X_add_number
= S_GET_VALUE (sym
);
3234 sym
= hash_find (arc_addrtype_hash
, name
);
3237 e
->X_op
= O_addrtype
;
3238 e
->X_add_number
= S_GET_VALUE (sym
);
3246 Invocation line includes a switch not recognized by the base assembler.
3247 See if it's a processor-specific option.
3249 New options (supported) are:
3251 -mcpu=<cpu name> Assemble for selected processor
3252 -EB/-mbig-endian Big-endian
3253 -EL/-mlittle-endian Little-endian
3254 -mrelax Enable relaxation
3256 The following CPU names are recognized:
3257 arc600, arc700, arcem, archs, nps400. */
3260 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3266 return md_parse_option (OPTION_MCPU
, "arc600");
3269 return md_parse_option (OPTION_MCPU
, "arc700");
3272 return md_parse_option (OPTION_MCPU
, "arcem");
3275 return md_parse_option (OPTION_MCPU
, "archs");
3279 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3284 arc_target_format
= "elf32-bigarc";
3285 byte_order
= BIG_ENDIAN
;
3289 arc_target_format
= "elf32-littlearc";
3290 byte_order
= LITTLE_ENDIAN
;
3294 /* This option has an effect only on ARC EM. */
3295 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
3296 selected_cpu
.features
|= ARC_CD
;
3298 as_warn (_("Code density option invalid for selected CPU"));
3302 relaxation_state
= 1;
3306 selected_cpu
.features
|= ARC_NPS400
;
3310 selected_cpu
.features
|= ARC_SPFP
;
3314 selected_cpu
.features
|= ARC_DPFP
;
3318 /* This option has an effect only on ARC EM. */
3319 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
3320 selected_cpu
.features
|= ARC_FPUDA
;
3322 as_warn (_("FPUDA invalid for selected CPU"));
3325 /* Dummy options are accepted but have no effect. */
3326 case OPTION_USER_MODE
:
3327 case OPTION_LD_EXT_MASK
:
3330 case OPTION_BARREL_SHIFT
:
3331 case OPTION_MIN_MAX
:
3336 case OPTION_XMAC_D16
:
3337 case OPTION_XMAC_24
:
3338 case OPTION_DSP_PACKA
:
3341 case OPTION_TELEPHONY
:
3342 case OPTION_XYMEMORY
:
3356 md_show_usage (FILE *stream
)
3358 fprintf (stream
, _("ARC-specific assembler options:\n"));
3360 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
3361 "(default: %s)\n", TARGET_WITH_CPU
);
3362 fprintf (stream
, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
3363 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3364 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3365 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3366 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3368 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3369 fprintf (stream
, " -mspfp\t\t enable single-precision floating point instructions\n");
3370 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point instructions\n");
3371 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3372 "point\n\t\t\t instructions for ARC EM\n");
3375 " -mcode-density\t enable code density option for ARC EM\n");
3377 fprintf (stream
, _("\
3378 -EB assemble code for a big-endian cpu\n"));
3379 fprintf (stream
, _("\
3380 -EL assemble code for a little-endian cpu\n"));
3381 fprintf (stream
, _("\
3382 -mrelax enable relaxation\n"));
3384 fprintf (stream
, _("The following ARC-specific assembler options are "
3385 "deprecated and are accepted\nfor compatibility only:\n"));
3387 fprintf (stream
, _(" -mEA\n"
3388 " -mbarrel-shifter\n"
3389 " -mbarrel_shifter\n"
3394 " -mld-extension-reg-mask\n"
3410 " -muser-mode-only\n"
3414 /* Find the proper relocation for the given opcode. */
3416 static extended_bfd_reloc_code_real_type
3417 find_reloc (const char *name
,
3418 const char *opcodename
,
3419 const struct arc_flags
*pflags
,
3421 extended_bfd_reloc_code_real_type reloc
)
3425 bfd_boolean found_flag
, tmp
;
3426 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3428 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3430 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3432 /* Find the entry. */
3433 if (strcmp (name
, r
->name
))
3435 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3442 unsigned * psflg
= (unsigned *)r
->flags
;
3446 for (j
= 0; j
< nflg
; j
++)
3447 if (!strcmp (pflags
[j
].name
,
3448 arc_flag_operands
[*psflg
].name
))
3469 if (reloc
!= r
->oldreloc
)
3476 if (ret
== BFD_RELOC_UNUSED
)
3477 as_bad (_("Unable to find %s relocation for instruction %s"),
3482 /* All the symbol types that are allowed to be used for
3486 may_relax_expr (expressionS tok
)
3488 /* Check if we have unrelaxable relocs. */
3513 /* Checks if flags are in line with relaxable insn. */
3516 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3517 const struct arc_flags
*pflags
,
3520 unsigned flag_class
,
3525 const struct arc_flag_operand
*flag_opand
;
3526 int i
, counttrue
= 0;
3528 /* Iterate through flags classes. */
3529 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3531 /* Iterate through flags in flag class. */
3532 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3535 flag_opand
= &arc_flag_operands
[flag
];
3536 /* Iterate through flags in ins to compare. */
3537 for (i
= 0; i
< nflgs
; ++i
)
3539 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3550 /* If counttrue == nflgs, then all flags have been found. */
3551 return (counttrue
== nflgs
? TRUE
: FALSE
);
3554 /* Checks if operands are in line with relaxable insn. */
3557 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3558 const expressionS
*tok
,
3561 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3564 while (*operand
!= EMPTY
)
3566 const expressionS
*epr
= &tok
[i
];
3568 if (i
!= 0 && i
>= ntok
)
3574 if (!(epr
->X_op
== O_multiply
3575 || epr
->X_op
== O_divide
3576 || epr
->X_op
== O_modulus
3577 || epr
->X_op
== O_add
3578 || epr
->X_op
== O_subtract
3579 || epr
->X_op
== O_symbol
))
3585 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3589 if (epr
->X_op
!= O_register
)
3594 if (epr
->X_op
!= O_register
)
3597 switch (epr
->X_add_number
)
3599 case 0: case 1: case 2: case 3:
3600 case 12: case 13: case 14: case 15:
3607 case REGISTER_NO_GP
:
3608 if ((epr
->X_op
!= O_register
)
3609 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3614 if (epr
->X_op
!= O_bracket
)
3619 /* Don't understand, bail out. */
3625 operand
= &ins
->operands
[i
];
3628 return (i
== ntok
? TRUE
: FALSE
);
3631 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3634 relax_insn_p (const struct arc_opcode
*opcode
,
3635 const expressionS
*tok
,
3637 const struct arc_flags
*pflags
,
3641 bfd_boolean rv
= FALSE
;
3643 /* Check the relaxation table. */
3644 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3646 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3648 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3649 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3650 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3651 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3654 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3655 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3656 sizeof (expressionS
) * ntok
);
3657 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3658 sizeof (struct arc_flags
) * nflg
);
3659 frag_now
->tc_frag_data
.nflg
= nflg
;
3660 frag_now
->tc_frag_data
.ntok
= ntok
;
3668 /* Turn an opcode description and a set of arguments into
3669 an instruction and a fixup. */
3672 assemble_insn (const struct arc_opcode
*opcode
,
3673 const expressionS
*tok
,
3675 const struct arc_flags
*pflags
,
3677 struct arc_insn
*insn
)
3679 const expressionS
*reloc_exp
= NULL
;
3680 unsigned long long image
;
3681 const unsigned char *argidx
;
3684 unsigned char pcrel
= 0;
3685 bfd_boolean needGOTSymbol
;
3686 bfd_boolean has_delay_slot
= FALSE
;
3687 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3689 memset (insn
, 0, sizeof (*insn
));
3690 image
= opcode
->opcode
;
3692 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3693 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3696 /* Handle operands. */
3697 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3699 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3700 const expressionS
*t
= (const expressionS
*) 0;
3702 if (ARC_OPERAND_IS_FAKE (operand
))
3705 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3707 /* Duplicate operand, already inserted. */
3719 /* Regardless if we have a reloc or not mark the instruction
3720 limm if it is the case. */
3721 if (operand
->flags
& ARC_OPERAND_LIMM
)
3722 insn
->has_limm
= TRUE
;
3727 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3732 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3734 if (operand
->flags
& ARC_OPERAND_LIMM
)
3735 insn
->limm
= t
->X_add_number
;
3741 /* Ignore brackets, colons, and address types. */
3745 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3749 /* Maybe register range. */
3750 if ((t
->X_add_number
== 0)
3751 && contains_register (t
->X_add_symbol
)
3752 && contains_register (t
->X_op_symbol
))
3756 regs
= get_register (t
->X_add_symbol
);
3758 regs
|= get_register (t
->X_op_symbol
);
3759 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3765 /* This operand needs a relocation. */
3766 needGOTSymbol
= FALSE
;
3771 if (opcode
->insn_class
== JUMP
)
3772 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3773 _("Unable to use @plt relocatio for insn %s"),
3775 needGOTSymbol
= TRUE
;
3776 reloc
= find_reloc ("plt", opcode
->name
,
3778 operand
->default_reloc
);
3783 needGOTSymbol
= TRUE
;
3784 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3787 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3788 if (arc_opcode_len (opcode
) == 2
3789 || opcode
->insn_class
== JUMP
)
3790 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3791 _("Unable to use @pcl relocation for insn %s"),
3795 reloc
= find_reloc ("sda", opcode
->name
,
3797 operand
->default_reloc
);
3801 needGOTSymbol
= TRUE
;
3806 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3809 case O_tpoff9
: /*FIXME! Check for the conditionality of
3811 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3813 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3817 /* Just consider the default relocation. */
3818 reloc
= operand
->default_reloc
;
3822 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3823 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3830 /* sanity checks. */
3831 reloc_howto_type
*reloc_howto
3832 = bfd_reloc_type_lookup (stdoutput
,
3833 (bfd_reloc_code_real_type
) reloc
);
3834 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3835 if (reloc_howto
->rightshift
)
3836 reloc_bitsize
-= reloc_howto
->rightshift
;
3837 if (reloc_bitsize
!= operand
->bits
)
3839 as_bad (_("invalid relocation %s for field"),
3840 bfd_get_reloc_code_name (reloc
));
3845 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3846 as_fatal (_("too many fixups"));
3848 struct arc_fixup
*fixup
;
3849 fixup
= &insn
->fixups
[insn
->nfixups
++];
3851 fixup
->reloc
= reloc
;
3852 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3853 fixup
->pcrel
= pcrel
;
3854 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3861 for (i
= 0; i
< nflg
; i
++)
3863 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3865 /* Check if the instruction has a delay slot. */
3866 if (!strcmp (flg_operand
->name
, "d"))
3867 has_delay_slot
= TRUE
;
3869 /* There is an exceptional case when we cannot insert a flag
3870 just as it is. The .T flag must be handled in relation with
3871 the relative address. */
3872 if (!strcmp (flg_operand
->name
, "t")
3873 || !strcmp (flg_operand
->name
, "nt"))
3875 unsigned bitYoperand
= 0;
3876 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3877 if (!strcmp (flg_operand
->name
, "t"))
3878 if (!strcmp (opcode
->name
, "bbit0")
3879 || !strcmp (opcode
->name
, "bbit1"))
3880 bitYoperand
= arc_NToperand
;
3882 bitYoperand
= arc_Toperand
;
3884 if (!strcmp (opcode
->name
, "bbit0")
3885 || !strcmp (opcode
->name
, "bbit1"))
3886 bitYoperand
= arc_Toperand
;
3888 bitYoperand
= arc_NToperand
;
3890 gas_assert (reloc_exp
!= NULL
);
3891 if (reloc_exp
->X_op
== O_constant
)
3893 /* Check if we have a constant and solved it
3895 offsetT val
= reloc_exp
->X_add_number
;
3896 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3901 struct arc_fixup
*fixup
;
3903 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3904 as_fatal (_("too many fixups"));
3906 fixup
= &insn
->fixups
[insn
->nfixups
++];
3907 fixup
->exp
= *reloc_exp
;
3908 fixup
->reloc
= -bitYoperand
;
3909 fixup
->pcrel
= pcrel
;
3910 fixup
->islong
= FALSE
;
3914 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3915 << flg_operand
->shift
;
3918 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3920 /* Instruction length. */
3921 insn
->len
= arc_opcode_len (opcode
);
3925 /* Update last insn status. */
3926 arc_last_insns
[1] = arc_last_insns
[0];
3927 arc_last_insns
[0].opcode
= opcode
;
3928 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3929 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3931 /* Check if the current instruction is legally used. */
3932 if (arc_last_insns
[1].has_delay_slot
3933 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3934 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3935 _("A jump/branch instruction in delay slot."));
3939 arc_handle_align (fragS
* fragP
)
3941 if ((fragP
)->fr_type
== rs_align_code
)
3943 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3944 valueT count
= ((fragP
)->fr_next
->fr_address
3945 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3947 (fragP
)->fr_var
= 2;
3949 if (count
& 1)/* Padding in the gap till the next 2-byte
3950 boundary with 0s. */
3955 /* Writing nop_s. */
3956 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
3960 /* Here we decide which fixups can be adjusted to make them relative
3961 to the beginning of the section instead of the symbol. Basically
3962 we need to make sure that the dynamic relocations are done
3963 correctly, so in some cases we force the original symbol to be
3967 tc_arc_fix_adjustable (fixS
*fixP
)
3970 /* Prevent all adjustments to global symbols. */
3971 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
3973 if (S_IS_WEAK (fixP
->fx_addsy
))
3976 /* Adjust_reloc_syms doesn't know about the GOT. */
3977 switch (fixP
->fx_r_type
)
3979 case BFD_RELOC_ARC_GOTPC32
:
3980 case BFD_RELOC_ARC_PLT32
:
3981 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3982 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3983 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3984 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3994 /* Compute the reloc type of an expression EXP. */
3997 arc_check_reloc (expressionS
*exp
,
3998 bfd_reloc_code_real_type
*r_type_p
)
4000 if (*r_type_p
== BFD_RELOC_32
4001 && exp
->X_op
== O_subtract
4002 && exp
->X_op_symbol
!= NULL
4003 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4004 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4008 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4011 arc_cons_fix_new (fragS
*frag
,
4015 bfd_reloc_code_real_type r_type
)
4017 r_type
= BFD_RELOC_UNUSED
;
4022 r_type
= BFD_RELOC_8
;
4026 r_type
= BFD_RELOC_16
;
4030 r_type
= BFD_RELOC_24
;
4034 r_type
= BFD_RELOC_32
;
4035 arc_check_reloc (exp
, &r_type
);
4039 r_type
= BFD_RELOC_64
;
4043 as_bad (_("unsupported BFD relocation size %u"), size
);
4044 r_type
= BFD_RELOC_UNUSED
;
4047 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4050 /* The actual routine that checks the ZOL conditions. */
4053 check_zol (symbolS
*s
)
4055 switch (selected_cpu
.mach
)
4057 case bfd_mach_arc_arcv2
:
4058 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4061 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4062 || arc_last_insns
[1].has_delay_slot
)
4063 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4067 case bfd_mach_arc_arc600
:
4069 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4070 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4073 if (arc_last_insns
[0].has_limm
4074 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4075 as_bad (_("A jump instruction with long immediate detected at the \
4076 end of the ZOL label @%s"), S_GET_NAME (s
));
4079 case bfd_mach_arc_arc700
:
4080 if (arc_last_insns
[0].has_delay_slot
)
4081 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4090 /* If ZOL end check the last two instruction for illegals. */
4092 arc_frob_label (symbolS
* sym
)
4094 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4097 dwarf2_emit_label (sym
);
4100 /* Used because generic relaxation assumes a pc-rel value whilst we
4101 also relax instructions that use an absolute value resolved out of
4102 relative values (if that makes any sense). An example: 'add r1,
4103 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4104 but if they're in the same section we can subtract the section
4105 offset relocation which ends up in a resolved value. So if @.L2 is
4106 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4107 .text + 0x40 = 0x10. */
4109 arc_pcrel_adjust (fragS
*fragP
)
4111 if (!fragP
->tc_frag_data
.pcrel
)
4112 return fragP
->fr_address
+ fragP
->fr_fix
;
4117 /* Initialize the DWARF-2 unwind information for this procedure. */
4120 tc_arc_frame_initial_instructions (void)
4122 /* Stack pointer is register 28. */
4123 cfi_add_CFA_def_cfa (28, 0);
4127 tc_arc_regname_to_dw2regnum (char *regname
)
4131 sym
= hash_find (arc_reg_hash
, regname
);
4133 return S_GET_VALUE (sym
);
4138 /* Adjust the symbol table. Delete found AUX register symbols. */
4141 arc_adjust_symtab (void)
4145 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4147 /* I've created a symbol during parsing process. Now, remove
4148 the symbol as it is found to be an AUX register. */
4149 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4150 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4153 /* Now do generic ELF adjustments. */
4154 elf_adjust_symtab ();
4158 tokenize_extinsn (extInstruction_t
*einsn
)
4162 unsigned char major_opcode
;
4163 unsigned char sub_opcode
;
4164 unsigned char syntax_class
= 0;
4165 unsigned char syntax_class_modifiers
= 0;
4166 unsigned char suffix_class
= 0;
4171 /* 1st: get instruction name. */
4172 p
= input_line_pointer
;
4173 c
= get_symbol_name (&p
);
4175 insn_name
= xstrdup (p
);
4176 restore_line_pointer (c
);
4178 /* 2nd: get major opcode. */
4179 if (*input_line_pointer
!= ',')
4181 as_bad (_("expected comma after instruction name"));
4182 ignore_rest_of_line ();
4185 input_line_pointer
++;
4186 major_opcode
= get_absolute_expression ();
4188 /* 3rd: get sub-opcode. */
4191 if (*input_line_pointer
!= ',')
4193 as_bad (_("expected comma after major opcode"));
4194 ignore_rest_of_line ();
4197 input_line_pointer
++;
4198 sub_opcode
= get_absolute_expression ();
4200 /* 4th: get suffix class. */
4203 if (*input_line_pointer
!= ',')
4205 as_bad ("expected comma after sub opcode");
4206 ignore_rest_of_line ();
4209 input_line_pointer
++;
4215 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4217 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4218 suffixclass
[i
].len
))
4220 suffix_class
|= suffixclass
[i
].attr_class
;
4221 input_line_pointer
+= suffixclass
[i
].len
;
4226 if (i
== ARRAY_SIZE (suffixclass
))
4228 as_bad ("invalid suffix class");
4229 ignore_rest_of_line ();
4235 if (*input_line_pointer
== '|')
4236 input_line_pointer
++;
4241 /* 5th: get syntax class and syntax class modifiers. */
4242 if (*input_line_pointer
!= ',')
4244 as_bad ("expected comma after suffix class");
4245 ignore_rest_of_line ();
4248 input_line_pointer
++;
4254 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4256 if (!strncmp (syntaxclassmod
[i
].name
,
4258 syntaxclassmod
[i
].len
))
4260 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4261 input_line_pointer
+= syntaxclassmod
[i
].len
;
4266 if (i
== ARRAY_SIZE (syntaxclassmod
))
4268 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4270 if (!strncmp (syntaxclass
[i
].name
,
4272 syntaxclass
[i
].len
))
4274 syntax_class
|= syntaxclass
[i
].attr_class
;
4275 input_line_pointer
+= syntaxclass
[i
].len
;
4280 if (i
== ARRAY_SIZE (syntaxclass
))
4282 as_bad ("missing syntax class");
4283 ignore_rest_of_line ();
4290 if (*input_line_pointer
== '|')
4291 input_line_pointer
++;
4296 demand_empty_rest_of_line ();
4298 einsn
->name
= insn_name
;
4299 einsn
->major
= major_opcode
;
4300 einsn
->minor
= sub_opcode
;
4301 einsn
->syntax
= syntax_class
;
4302 einsn
->modsyn
= syntax_class_modifiers
;
4303 einsn
->suffix
= suffix_class
;
4304 einsn
->flags
= syntax_class
4305 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4308 /* Generate an extension section. */
4311 arc_set_ext_seg (void)
4313 if (!arcext_section
)
4315 arcext_section
= subseg_new (".arcextmap", 0);
4316 bfd_set_section_flags (stdoutput
, arcext_section
,
4317 SEC_READONLY
| SEC_HAS_CONTENTS
);
4320 subseg_set (arcext_section
, 0);
4324 /* Create an extension instruction description in the arc extension
4325 section of the output file.
4326 The structure for an instruction is like this:
4327 [0]: Length of the record.
4328 [1]: Type of the record.
4332 [4]: Syntax (flags).
4333 [5]+ Name instruction.
4335 The sequence is terminated by an empty entry. */
4338 create_extinst_section (extInstruction_t
*einsn
)
4341 segT old_sec
= now_seg
;
4342 int old_subsec
= now_subseg
;
4344 int name_len
= strlen (einsn
->name
);
4349 *p
= 5 + name_len
+ 1;
4351 *p
= EXT_INSTRUCTION
;
4358 p
= frag_more (name_len
+ 1);
4359 strcpy (p
, einsn
->name
);
4361 subseg_set (old_sec
, old_subsec
);
4364 /* Handler .extinstruction pseudo-op. */
4367 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4369 extInstruction_t einsn
;
4370 struct arc_opcode
*arc_ext_opcodes
;
4371 const char *errmsg
= NULL
;
4372 unsigned char moplow
, mophigh
;
4374 memset (&einsn
, 0, sizeof (einsn
));
4375 tokenize_extinsn (&einsn
);
4377 /* Check if the name is already used. */
4378 if (arc_find_opcode (einsn
.name
))
4379 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4381 /* Check the opcode ranges. */
4383 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4384 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4386 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4387 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4389 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4390 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4391 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4393 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4395 case ARC_SYNTAX_3OP
:
4396 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4397 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4399 case ARC_SYNTAX_2OP
:
4400 case ARC_SYNTAX_1OP
:
4401 case ARC_SYNTAX_NOP
:
4402 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4403 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4409 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4410 if (arc_ext_opcodes
== NULL
)
4413 as_fatal ("%s", errmsg
);
4415 as_fatal (_("Couldn't generate extension instruction opcodes"));
4418 as_warn ("%s", errmsg
);
4420 /* Insert the extension instruction. */
4421 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4423 create_extinst_section (&einsn
);
4427 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4433 int number
, imode
= 0;
4434 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4435 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4436 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4438 /* 1st: get register name. */
4440 p
= input_line_pointer
;
4441 c
= get_symbol_name (&p
);
4444 restore_line_pointer (c
);
4446 /* 2nd: get register number. */
4449 if (*input_line_pointer
!= ',')
4451 as_bad (_("expected comma after register name"));
4452 ignore_rest_of_line ();
4456 input_line_pointer
++;
4457 number
= get_absolute_expression ();
4461 as_bad (_("negative operand number %d"), number
);
4462 ignore_rest_of_line ();
4469 /* 3rd: get register mode. */
4472 if (*input_line_pointer
!= ',')
4474 as_bad (_("expected comma after register number"));
4475 ignore_rest_of_line ();
4480 input_line_pointer
++;
4481 mode
= input_line_pointer
;
4483 if (!strncmp (mode
, "r|w", 3))
4486 input_line_pointer
+= 3;
4488 else if (!strncmp (mode
, "r", 1))
4490 imode
= ARC_REGISTER_READONLY
;
4491 input_line_pointer
+= 1;
4493 else if (strncmp (mode
, "w", 1))
4495 as_bad (_("invalid mode"));
4496 ignore_rest_of_line ();
4502 imode
= ARC_REGISTER_WRITEONLY
;
4503 input_line_pointer
+= 1;
4509 /* 4th: get core register shortcut. */
4511 if (*input_line_pointer
!= ',')
4513 as_bad (_("expected comma after register mode"));
4514 ignore_rest_of_line ();
4519 input_line_pointer
++;
4521 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4523 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4524 input_line_pointer
+= 15;
4526 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4528 as_bad (_("shortcut designator invalid"));
4529 ignore_rest_of_line ();
4535 input_line_pointer
+= 12;
4538 demand_empty_rest_of_line ();
4541 ereg
->number
= number
;
4542 ereg
->imode
= imode
;
4545 /* Create an extension register/condition description in the arc
4546 extension section of the output file.
4548 The structure for an instruction is like this:
4549 [0]: Length of the record.
4550 [1]: Type of the record.
4552 For core regs and condition codes:
4556 For auxilirary registers:
4560 The sequence is terminated by an empty entry. */
4563 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4565 segT old_sec
= now_seg
;
4566 int old_subsec
= now_subseg
;
4568 int name_len
= strlen (ereg
->name
);
4575 case EXT_CORE_REGISTER
:
4577 *p
= 3 + name_len
+ 1;
4583 case EXT_AUX_REGISTER
:
4585 *p
= 6 + name_len
+ 1;
4587 *p
= EXT_AUX_REGISTER
;
4589 *p
= (ereg
->number
>> 24) & 0xff;
4591 *p
= (ereg
->number
>> 16) & 0xff;
4593 *p
= (ereg
->number
>> 8) & 0xff;
4595 *p
= (ereg
->number
) & 0xff;
4601 p
= frag_more (name_len
+ 1);
4602 strcpy (p
, ereg
->name
);
4604 subseg_set (old_sec
, old_subsec
);
4607 /* Handler .extCoreRegister pseudo-op. */
4610 arc_extcorereg (int opertype
)
4613 struct arc_aux_reg
*auxr
;
4615 struct arc_flag_operand
*ccode
;
4617 memset (&ereg
, 0, sizeof (ereg
));
4618 tokenize_extregister (&ereg
, opertype
);
4622 case EXT_CORE_REGISTER
:
4623 /* Core register. */
4624 if (ereg
.number
> 60)
4625 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4627 declare_register (ereg
.name
, ereg
.number
);
4629 case EXT_AUX_REGISTER
:
4630 /* Auxiliary register. */
4631 auxr
= XNEW (struct arc_aux_reg
);
4632 auxr
->name
= ereg
.name
;
4633 auxr
->cpu
= selected_cpu
.flags
;
4634 auxr
->subclass
= NONE
;
4635 auxr
->address
= ereg
.number
;
4636 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4638 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4639 auxr
->name
, retval
);
4642 /* Condition code. */
4643 if (ereg
.number
> 31)
4644 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4646 ext_condcode
.size
++;
4647 ext_condcode
.arc_ext_condcode
=
4648 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4649 ext_condcode
.size
+ 1);
4650 if (ext_condcode
.arc_ext_condcode
== NULL
)
4651 as_fatal (_("Virtual memory exhausted"));
4653 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4654 ccode
->name
= ereg
.name
;
4655 ccode
->code
= ereg
.number
;
4658 ccode
->favail
= 0; /* not used. */
4660 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4663 as_bad (_("Unknown extension"));
4666 create_extcore_section (&ereg
, opertype
);
4670 eval: (c-set-style "gnu")