1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
31 #include "opcode/arc-attrs.h"
33 #include "../opcodes/arc-ext.h"
35 /* Defines section. */
37 #define MAX_INSN_FIXUPS 2
38 #define MAX_CONSTR_STR 20
39 #define FRAG_MAX_GROWTH 8
42 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
44 # define pr_debug(fmt, args...)
47 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
48 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
49 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
50 && (SUB_OPCODE (x) == 0x28))
52 /* Equal to MAX_PRECISION in atof-ieee.c. */
53 #define MAX_LITTLENUMS 6
55 #ifndef TARGET_WITH_CPU
56 #define TARGET_WITH_CPU "arc700"
57 #endif /* TARGET_WITH_CPU */
59 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
60 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
61 #define streq(a, b) (strcmp (a, b) == 0)
63 /* Enum used to enumerate the relaxable ins operands. */
68 REGISTER_S
, /* Register for short instruction(s). */
69 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
70 REGISTER_DUP
, /* Duplication of previous operand of type register. */
102 /* Macros section. */
104 #define regno(x) ((x) & 0x3F)
105 #define is_ir_num(x) (((x) & ~0x3F) == 0)
106 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
107 #define is_spfp_p(op) (((sc) == SPX))
108 #define is_dpfp_p(op) (((sc) == DPX))
109 #define is_fpuda_p(op) (((sc) == DPA))
110 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
111 || (op)->insn_class == JUMP \
112 || (op)->insn_class == BRCC \
113 || (op)->insn_class == BBIT0 \
114 || (op)->insn_class == BBIT1 \
115 || (op)->insn_class == BI \
116 || (op)->insn_class == EI \
117 || (op)->insn_class == ENTER \
118 || (op)->insn_class == JLI \
119 || (op)->insn_class == LOOP \
120 || (op)->insn_class == LEAVE \
122 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
123 #define is_nps400_p(op) (((sc) == NPS400))
125 /* Generic assembler global variables which must be defined by all
128 /* Characters which always start a comment. */
129 const char comment_chars
[] = "#;";
131 /* Characters which start a comment at the beginning of a line. */
132 const char line_comment_chars
[] = "#";
134 /* Characters which may be used to separate multiple commands on a
136 const char line_separator_chars
[] = "`";
138 /* Characters which are used to indicate an exponent in a floating
140 const char EXP_CHARS
[] = "eE";
142 /* Chars that mean this number is a floating point constant
143 As in 0f12.456 or 0d1.2345e12. */
144 const char FLT_CHARS
[] = "rRsSfFdD";
147 extern int target_big_endian
;
148 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
149 static int byte_order
= DEFAULT_BYTE_ORDER
;
151 /* Arc extension section. */
152 static segT arcext_section
;
154 /* By default relaxation is disabled. */
155 static int relaxation_state
= 0;
157 extern int arc_get_mach (char *);
159 /* Forward declarations. */
160 static void arc_lcomm (int);
161 static void arc_option (int);
162 static void arc_extra_reloc (int);
163 static void arc_extinsn (int);
164 static void arc_extcorereg (int);
165 static void arc_attribute (int);
167 const pseudo_typeS md_pseudo_table
[] =
169 /* Make sure that .word is 32 bits. */
172 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
173 { "lcomm", arc_lcomm
, 0 },
174 { "lcommon", arc_lcomm
, 0 },
175 { "cpu", arc_option
, 0 },
177 { "arc_attribute", arc_attribute
, 0 },
178 { "extinstruction", arc_extinsn
, 0 },
179 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
180 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
181 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
183 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
184 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
189 const char *md_shortopts
= "";
193 OPTION_EB
= OPTION_MD_BASE
,
211 /* The following options are deprecated and provided here only for
212 compatibility reasons. */
235 struct option md_longopts
[] =
237 { "EB", no_argument
, NULL
, OPTION_EB
},
238 { "EL", no_argument
, NULL
, OPTION_EL
},
239 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
240 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
241 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
242 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
243 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
244 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
245 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
246 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
247 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
248 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
249 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
251 /* Floating point options */
252 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
253 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
254 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
255 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
256 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
257 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
258 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
259 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
260 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
261 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
262 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
264 /* The following options are deprecated and provided here only for
265 compatibility reasons. */
266 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
267 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
268 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
269 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
270 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
271 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
272 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
273 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
274 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
275 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
276 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
277 { "mea", no_argument
, NULL
, OPTION_EA
},
278 { "mEA", no_argument
, NULL
, OPTION_EA
},
279 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
280 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
281 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
282 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
283 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
284 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
285 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
286 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
287 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
288 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
289 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
290 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
291 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
292 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
293 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
295 { NULL
, no_argument
, NULL
, 0 }
298 size_t md_longopts_size
= sizeof (md_longopts
);
300 /* Local data and data types. */
302 /* Used since new relocation types are introduced in this
303 file (DUMMY_RELOC_LITUSE_*). */
304 typedef int extended_bfd_reloc_code_real_type
;
310 extended_bfd_reloc_code_real_type reloc
;
312 /* index into arc_operands. */
313 unsigned int opindex
;
315 /* PC-relative, used by internals fixups. */
318 /* TRUE if this fixup is for LIMM operand. */
324 unsigned long long int insn
;
326 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
328 unsigned int len
; /* Length of instruction in bytes. */
329 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
331 bfd_boolean relax
; /* Boolean value: TRUE if needs
335 /* Structure to hold any last two instructions. */
336 static struct arc_last_insn
338 /* Saved instruction opcode. */
339 const struct arc_opcode
*opcode
;
341 /* Boolean value: TRUE if current insn is short. */
342 bfd_boolean has_limm
;
344 /* Boolean value: TRUE if current insn has delay slot. */
345 bfd_boolean has_delay_slot
;
348 /* Extension instruction suffix classes. */
356 static const attributes_t suffixclass
[] =
358 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
359 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
360 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
363 /* Extension instruction syntax classes. */
364 static const attributes_t syntaxclass
[] =
366 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
367 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
368 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
369 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
372 /* Extension instruction syntax classes modifiers. */
373 static const attributes_t syntaxclassmod
[] =
375 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
376 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
379 /* Extension register type. */
387 /* A structure to hold the additional conditional codes. */
390 struct arc_flag_operand
*arc_ext_condcode
;
392 } ext_condcode
= { NULL
, 0 };
394 /* Structure to hold an entry in ARC_OPCODE_HASH. */
395 struct arc_opcode_hash_entry
397 /* The number of pointers in the OPCODE list. */
400 /* Points to a list of opcode pointers. */
401 const struct arc_opcode
**opcode
;
404 /* Structure used for iterating through an arc_opcode_hash_entry. */
405 struct arc_opcode_hash_entry_iterator
407 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
410 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
411 returned by this iterator. */
412 const struct arc_opcode
*opcode
;
415 /* Forward declaration. */
416 static void assemble_insn
417 (const struct arc_opcode
*, const expressionS
*, int,
418 const struct arc_flags
*, int, struct arc_insn
*);
420 /* The selection of the machine type can come from different sources. This
421 enum is used to track how the selection was made in order to perform
423 enum mach_selection_type
426 MACH_SELECTION_FROM_DEFAULT
,
427 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
428 MACH_SELECTION_FROM_COMMAND_LINE
431 /* How the current machine type was selected. */
432 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
434 /* The hash table of instruction opcodes. */
435 static struct hash_control
*arc_opcode_hash
;
437 /* The hash table of register symbols. */
438 static struct hash_control
*arc_reg_hash
;
440 /* The hash table of aux register symbols. */
441 static struct hash_control
*arc_aux_hash
;
443 /* The hash table of address types. */
444 static struct hash_control
*arc_addrtype_hash
;
446 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
447 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
448 E_ARC_MACH_ARC600, EXTRA}
449 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
450 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
451 E_ARC_MACH_ARC700, EXTRA}
452 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
453 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
454 EF_ARC_CPU_ARCV2EM, EXTRA}
455 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
456 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
457 EF_ARC_CPU_ARCV2HS, EXTRA}
458 #define ARC_CPU_TYPE_NONE \
461 /* A table of CPU names and opcode sets. */
462 static const struct cpu_type
472 #include "elf/arc-cpu.def"
475 /* Information about the cpu/variant we're assembling for. */
476 static struct cpu_type selected_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
478 /* TRUE if current assembly code uses RF16 only registers. */
479 static bfd_boolean rf16_only
= TRUE
;
482 static unsigned mpy_option
= 0;
485 static unsigned pic_option
= 0;
487 /* Use small data. */
488 static unsigned sda_option
= 0;
491 static unsigned tls_option
= 0;
493 /* Command line given features. */
494 static unsigned cl_features
= 0;
496 /* Used by the arc_reloc_op table. Order is important. */
497 #define O_gotoff O_md1 /* @gotoff relocation. */
498 #define O_gotpc O_md2 /* @gotpc relocation. */
499 #define O_plt O_md3 /* @plt relocation. */
500 #define O_sda O_md4 /* @sda relocation. */
501 #define O_pcl O_md5 /* @pcl relocation. */
502 #define O_tlsgd O_md6 /* @tlsgd relocation. */
503 #define O_tlsie O_md7 /* @tlsie relocation. */
504 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
505 #define O_tpoff O_md9 /* @tpoff relocation. */
506 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
507 #define O_dtpoff O_md11 /* @dtpoff relocation. */
508 #define O_last O_dtpoff
510 /* Used to define a bracket as operand in tokens. */
511 #define O_bracket O_md32
513 /* Used to define a colon as an operand in tokens. */
514 #define O_colon O_md31
516 /* Used to define address types in nps400. */
517 #define O_addrtype O_md30
519 /* Dummy relocation, to be sorted out. */
520 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
522 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
524 /* A table to map the spelling of a relocation operand into an appropriate
525 bfd_reloc_code_real_type type. The table is assumed to be ordered such
526 that op-O_literal indexes into it. */
527 #define ARC_RELOC_TABLE(op) \
528 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
530 : (int) (op) - (int) O_gotoff) ])
532 #define DEF(NAME, RELOC, REQ) \
533 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
535 static const struct arc_reloc_op_tag
537 /* String to lookup. */
539 /* Size of the string. */
541 /* Which operator to use. */
543 extended_bfd_reloc_code_real_type reloc
;
544 /* Allows complex relocation expression like identifier@reloc +
546 unsigned int complex_expr
: 1;
550 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
551 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
552 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
553 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
554 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
555 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
556 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
557 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
558 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
559 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
560 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
563 static const int arc_num_reloc_op
564 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
566 /* Structure for relaxable instruction that have to be swapped with a
567 smaller alternative instruction. */
568 struct arc_relaxable_ins
570 /* Mnemonic that should be checked. */
571 const char *mnemonic_r
;
573 /* Operands that should be checked.
574 Indexes of operands from operand array. */
575 enum rlx_operand_type operands
[6];
577 /* Flags that should be checked. */
578 unsigned flag_classes
[5];
580 /* Mnemonic (smaller) alternative to be used later for relaxation. */
581 const char *mnemonic_alt
;
583 /* Index of operand that generic relaxation has to check. */
586 /* Base subtype index used. */
587 enum arc_rlx_types subtype
;
590 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
591 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
592 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
596 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
597 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
598 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
603 /* ARC relaxation table. */
604 const relax_typeS md_relax_table
[] =
611 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
612 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
616 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
617 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
622 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
623 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
624 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
626 /* LD_S a, [b, u7] ->
627 LD<zz><.x><.aa><.di> a, [b, s9] ->
628 LD<zz><.x><.aa><.di> a, [b, limm] */
629 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
630 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
631 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
636 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
637 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
638 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
642 SUB<.f> a, b, limm. */
643 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
644 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
645 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
647 /* MPY<.f> a, b, u6 ->
648 MPY<.f> a, b, limm. */
649 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
650 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
652 /* MOV<.f><.cc> b, u6 ->
653 MOV<.f><.cc> b, limm. */
654 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
655 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
657 /* ADD<.f><.cc> b, b, u6 ->
658 ADD<.f><.cc> b, b, limm. */
659 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
660 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
663 /* Order of this table's entries matters! */
664 const struct arc_relaxable_ins arc_relaxable_insns
[] =
666 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
667 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
668 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
669 2, ARC_RLX_ADD_RRU6
},
670 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
672 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
674 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
675 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
676 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
677 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
678 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
679 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
680 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
681 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
683 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
685 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
689 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
691 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
692 symbolS
* GOT_symbol
= 0;
694 /* Set to TRUE when we assemble instructions. */
695 static bfd_boolean assembling_insn
= FALSE
;
697 /* List with attributes set explicitly. */
698 static bfd_boolean attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
700 /* Functions implementation. */
702 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
703 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
704 are no matching entries in ARC_OPCODE_HASH. */
706 static const struct arc_opcode_hash_entry
*
707 arc_find_opcode (const char *name
)
709 const struct arc_opcode_hash_entry
*entry
;
711 entry
= hash_find (arc_opcode_hash
, name
);
715 /* Initialise the iterator ITER. */
718 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
724 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
725 calls to this function. Return NULL when all ARC_OPCODE entries have
728 static const struct arc_opcode
*
729 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
730 struct arc_opcode_hash_entry_iterator
*iter
)
732 if (iter
->opcode
== NULL
&& iter
->index
== 0)
734 gas_assert (entry
->count
> 0);
735 iter
->opcode
= entry
->opcode
[iter
->index
];
737 else if (iter
->opcode
!= NULL
)
739 const char *old_name
= iter
->opcode
->name
;
742 if (iter
->opcode
->name
== NULL
743 || strcmp (old_name
, iter
->opcode
->name
) != 0)
746 if (iter
->index
== entry
->count
)
749 iter
->opcode
= entry
->opcode
[iter
->index
];
756 /* Insert an opcode into opcode hash structure. */
759 arc_insert_opcode (const struct arc_opcode
*opcode
)
761 const char *name
, *retval
;
762 struct arc_opcode_hash_entry
*entry
;
765 entry
= hash_find (arc_opcode_hash
, name
);
768 entry
= XNEW (struct arc_opcode_hash_entry
);
770 entry
->opcode
= NULL
;
772 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
774 as_fatal (_("internal error: can't hash opcode '%s': %s"),
778 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
781 if (entry
->opcode
== NULL
)
782 as_fatal (_("Virtual memory exhausted"));
784 entry
->opcode
[entry
->count
] = opcode
;
789 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
790 value, is encoded as 'middle-endian' for a little-endian target. This
791 function is used for regular 4, 6, and 8 byte instructions as well. */
794 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
799 md_number_to_chars (buf
, val
, n
);
802 md_number_to_chars (buf
, (val
& 0xffff00000000ull
) >> 32, 2);
803 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
806 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
807 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
810 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000ull
) >> 32, 4);
811 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
818 /* Check if a feature is allowed for a specific CPU. */
821 arc_check_feature (void)
825 if (!selected_cpu
.features
826 || !selected_cpu
.name
)
829 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
830 if ((selected_cpu
.features
& feature_list
[i
].feature
)
831 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
832 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
835 for (i
= 0; i
< ARRAY_SIZE (conflict_list
); i
++)
836 if ((selected_cpu
.features
& conflict_list
[i
]) == conflict_list
[i
])
837 as_bad(_("conflicting ISA extension attributes."));
840 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
841 the relevant static global variables. Parameter SEL describes where
842 this selection originated from. */
845 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
849 /* We should only set a default if we've not made a selection from some
851 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
852 || mach_selection_mode
== MACH_SELECTION_NONE
);
854 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
855 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
856 as_bad (_("Multiple .cpu directives found"));
858 /* Look for a matching entry in CPU_TYPES array. */
859 for (i
= 0; cpu_types
[i
].name
; ++i
)
861 if (!strcasecmp (cpu_types
[i
].name
, arg
))
863 /* If a previous selection was made on the command line, then we
864 allow later selections on the command line to override earlier
865 ones. However, a selection from a '.cpu NAME' directive must
866 match the command line selection, or we give a warning. */
867 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
869 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
870 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
871 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
872 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
874 as_warn (_("Command-line value overrides \".cpu\" directive"));
879 /* Initialise static global data about selected machine type. */
880 selected_cpu
.flags
= cpu_types
[i
].flags
;
881 selected_cpu
.name
= cpu_types
[i
].name
;
882 selected_cpu
.features
= cpu_types
[i
].features
| cl_features
;
883 selected_cpu
.mach
= cpu_types
[i
].mach
;
884 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_MACH_MSK
)
885 | cpu_types
[i
].eflags
);
890 if (!cpu_types
[i
].name
)
891 as_fatal (_("unknown architecture: %s\n"), arg
);
893 /* Check if set features are compatible with the chosen CPU. */
894 arc_check_feature ();
896 mach_selection_mode
= sel
;
899 /* Here ends all the ARCompact extension instruction assembling
903 arc_extra_reloc (int r_type
)
906 symbolS
*sym
, *lab
= NULL
;
908 if (*input_line_pointer
== '@')
909 input_line_pointer
++;
910 c
= get_symbol_name (&sym_name
);
911 sym
= symbol_find_or_make (sym_name
);
912 restore_line_pointer (c
);
913 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
915 ++input_line_pointer
;
917 c
= get_symbol_name (&lab_name
);
918 lab
= symbol_find_or_make (lab_name
);
919 restore_line_pointer (c
);
922 /* These relocations exist as a mechanism for the compiler to tell the
923 linker how to patch the code if the tls model is optimised. However,
924 the relocation itself does not require any space within the assembler
925 fragment, and so we pass a size of 0.
927 The lines that generate these relocations look like this:
929 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
931 The '.tls_gd_ld @.tdata' is processed first and generates the
932 additional relocation, while the 'bl __tls_get_addr@plt' is processed
933 second and generates the additional branch.
935 It is possible that the additional relocation generated by the
936 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
937 while the 'bl __tls_get_addr@plt' will be generated as the first thing
938 in the next fragment. This will be fine; both relocations will still
939 appear to be at the same address in the generated object file.
940 However, this only works as the additional relocation is generated
941 with size of 0 bytes. */
943 = fix_new (frag_now
, /* Which frag? */
944 frag_now_fix (), /* Where in that frag? */
945 0, /* size: 1, 2, or 4 usually. */
946 sym
, /* X_add_symbol. */
947 0, /* X_add_number. */
948 FALSE
, /* TRUE if PC-relative relocation. */
949 r_type
/* Relocation type. */);
950 fixP
->fx_subsy
= lab
;
954 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
955 symbolS
*symbolP
, addressT size
)
960 if (*input_line_pointer
== ',')
962 align
= parse_align (1);
964 if (align
== (addressT
) -1)
979 bss_alloc (symbolP
, size
, align
);
980 S_CLEAR_EXTERNAL (symbolP
);
986 arc_lcomm (int ignore
)
988 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
991 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
994 /* Select the cpu we're assembling for. */
997 arc_option (int ignore ATTRIBUTE_UNUSED
)
1001 const char *cpu_name
;
1003 c
= get_symbol_name (&cpu
);
1006 if ((!strcmp ("ARC600", cpu
))
1007 || (!strcmp ("ARC601", cpu
))
1008 || (!strcmp ("A6", cpu
)))
1009 cpu_name
= "arc600";
1010 else if ((!strcmp ("ARC700", cpu
))
1011 || (!strcmp ("A7", cpu
)))
1012 cpu_name
= "arc700";
1013 else if (!strcmp ("EM", cpu
))
1015 else if (!strcmp ("HS", cpu
))
1017 else if (!strcmp ("NPS400", cpu
))
1018 cpu_name
= "nps400";
1020 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1022 restore_line_pointer (c
);
1023 demand_empty_rest_of_line ();
1026 /* Smartly print an expression. */
1029 debug_exp (expressionS
*t
)
1031 const char *name ATTRIBUTE_UNUSED
;
1032 const char *namemd ATTRIBUTE_UNUSED
;
1034 pr_debug ("debug_exp: ");
1038 default: name
= "unknown"; break;
1039 case O_illegal
: name
= "O_illegal"; break;
1040 case O_absent
: name
= "O_absent"; break;
1041 case O_constant
: name
= "O_constant"; break;
1042 case O_symbol
: name
= "O_symbol"; break;
1043 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1044 case O_register
: name
= "O_register"; break;
1045 case O_big
: name
= "O_big"; break;
1046 case O_uminus
: name
= "O_uminus"; break;
1047 case O_bit_not
: name
= "O_bit_not"; break;
1048 case O_logical_not
: name
= "O_logical_not"; break;
1049 case O_multiply
: name
= "O_multiply"; break;
1050 case O_divide
: name
= "O_divide"; break;
1051 case O_modulus
: name
= "O_modulus"; break;
1052 case O_left_shift
: name
= "O_left_shift"; break;
1053 case O_right_shift
: name
= "O_right_shift"; break;
1054 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1055 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1056 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1057 case O_bit_and
: name
= "O_bit_and"; break;
1058 case O_add
: name
= "O_add"; break;
1059 case O_subtract
: name
= "O_subtract"; break;
1060 case O_eq
: name
= "O_eq"; break;
1061 case O_ne
: name
= "O_ne"; break;
1062 case O_lt
: name
= "O_lt"; break;
1063 case O_le
: name
= "O_le"; break;
1064 case O_ge
: name
= "O_ge"; break;
1065 case O_gt
: name
= "O_gt"; break;
1066 case O_logical_and
: name
= "O_logical_and"; break;
1067 case O_logical_or
: name
= "O_logical_or"; break;
1068 case O_index
: name
= "O_index"; break;
1069 case O_bracket
: name
= "O_bracket"; break;
1070 case O_colon
: name
= "O_colon"; break;
1071 case O_addrtype
: name
= "O_addrtype"; break;
1076 default: namemd
= "unknown"; break;
1077 case O_gotoff
: namemd
= "O_gotoff"; break;
1078 case O_gotpc
: namemd
= "O_gotpc"; break;
1079 case O_plt
: namemd
= "O_plt"; break;
1080 case O_sda
: namemd
= "O_sda"; break;
1081 case O_pcl
: namemd
= "O_pcl"; break;
1082 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1083 case O_tlsie
: namemd
= "O_tlsie"; break;
1084 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1085 case O_tpoff
: namemd
= "O_tpoff"; break;
1086 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1087 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1090 pr_debug ("%s (%s, %s, %d, %s)", name
,
1091 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1092 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1093 (int) t
->X_add_number
,
1094 (t
->X_md
) ? namemd
: "--");
1099 /* Parse the arguments to an opcode. */
1102 tokenize_arguments (char *str
,
1106 char *old_input_line_pointer
;
1107 bfd_boolean saw_comma
= FALSE
;
1108 bfd_boolean saw_arg
= FALSE
;
1113 const struct arc_reloc_op_tag
*r
;
1115 char *reloc_name
, c
;
1117 memset (tok
, 0, sizeof (*tok
) * ntok
);
1119 /* Save and restore input_line_pointer around this function. */
1120 old_input_line_pointer
= input_line_pointer
;
1121 input_line_pointer
= str
;
1123 while (*input_line_pointer
)
1126 switch (*input_line_pointer
)
1132 input_line_pointer
++;
1133 if (saw_comma
|| !saw_arg
)
1140 ++input_line_pointer
;
1142 if (!saw_arg
|| num_args
== ntok
)
1144 tok
->X_op
= O_bracket
;
1151 input_line_pointer
++;
1152 if (brk_lvl
|| num_args
== ntok
)
1155 tok
->X_op
= O_bracket
;
1161 input_line_pointer
++;
1162 if (!saw_arg
|| num_args
== ntok
)
1164 tok
->X_op
= O_colon
;
1171 /* We have labels, function names and relocations, all
1172 starting with @ symbol. Sort them out. */
1173 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1177 tok
->X_op
= O_symbol
;
1178 tok
->X_md
= O_absent
;
1180 if (*input_line_pointer
!= '@')
1181 goto normalsymbol
; /* This is not a relocation. */
1185 /* A relocation operand has the following form
1186 @identifier@relocation_type. The identifier is already
1188 if (tok
->X_op
!= O_symbol
)
1190 as_bad (_("No valid label relocation operand"));
1194 /* Parse @relocation_type. */
1195 input_line_pointer
++;
1196 c
= get_symbol_name (&reloc_name
);
1197 len
= input_line_pointer
- reloc_name
;
1200 as_bad (_("No relocation operand"));
1204 /* Go through known relocation and try to find a match. */
1205 r
= &arc_reloc_op
[0];
1206 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1207 if (len
== r
->length
1208 && memcmp (reloc_name
, r
->name
, len
) == 0)
1212 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1216 *input_line_pointer
= c
;
1217 SKIP_WHITESPACE_AFTER_NAME ();
1218 /* Extra check for TLS: base. */
1219 if (*input_line_pointer
== '@')
1222 if (tok
->X_op_symbol
!= NULL
1223 || tok
->X_op
!= O_symbol
)
1225 as_bad (_("Unable to parse TLS base: %s"),
1226 input_line_pointer
);
1229 input_line_pointer
++;
1231 c
= get_symbol_name (&sym_name
);
1232 base
= symbol_find_or_make (sym_name
);
1233 tok
->X_op
= O_subtract
;
1234 tok
->X_op_symbol
= base
;
1235 restore_line_pointer (c
);
1236 tmpE
.X_add_number
= 0;
1238 if ((*input_line_pointer
!= '+')
1239 && (*input_line_pointer
!= '-'))
1241 tmpE
.X_add_number
= 0;
1245 /* Parse the constant of a complex relocation expression
1246 like @identifier@reloc +/- const. */
1247 if (! r
->complex_expr
)
1249 as_bad (_("@%s is not a complex relocation."), r
->name
);
1253 if (tmpE
.X_op
!= O_constant
)
1255 as_bad (_("Bad expression: @%s + %s."),
1256 r
->name
, input_line_pointer
);
1262 tok
->X_add_number
= tmpE
.X_add_number
;
1273 /* Can be a register. */
1274 ++input_line_pointer
;
1278 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1281 tok
->X_op
= O_absent
;
1282 tok
->X_md
= O_absent
;
1285 /* Legacy: There are cases when we have
1286 identifier@relocation_type, if it is the case parse the
1287 relocation type as well. */
1288 if (*input_line_pointer
== '@')
1294 if (tok
->X_op
== O_illegal
1295 || tok
->X_op
== O_absent
1296 || num_args
== ntok
)
1308 if (saw_comma
|| brk_lvl
)
1310 input_line_pointer
= old_input_line_pointer
;
1316 as_bad (_("Brackets in operand field incorrect"));
1318 as_bad (_("extra comma"));
1320 as_bad (_("missing argument"));
1322 as_bad (_("missing comma or colon"));
1323 input_line_pointer
= old_input_line_pointer
;
1327 /* Parse the flags to a structure. */
1330 tokenize_flags (const char *str
,
1331 struct arc_flags flags
[],
1334 char *old_input_line_pointer
;
1335 bfd_boolean saw_flg
= FALSE
;
1336 bfd_boolean saw_dot
= FALSE
;
1340 memset (flags
, 0, sizeof (*flags
) * nflg
);
1342 /* Save and restore input_line_pointer around this function. */
1343 old_input_line_pointer
= input_line_pointer
;
1344 input_line_pointer
= (char *) str
;
1346 while (*input_line_pointer
)
1348 switch (*input_line_pointer
)
1355 input_line_pointer
++;
1363 if (saw_flg
&& !saw_dot
)
1366 if (num_flags
>= nflg
)
1369 flgnamelen
= strspn (input_line_pointer
,
1370 "abcdefghijklmnopqrstuvwxyz0123456789");
1371 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1374 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1376 input_line_pointer
+= flgnamelen
;
1386 input_line_pointer
= old_input_line_pointer
;
1391 as_bad (_("extra dot"));
1393 as_bad (_("unrecognized flag"));
1395 as_bad (_("failed to parse flags"));
1396 input_line_pointer
= old_input_line_pointer
;
1400 /* Apply the fixups in order. */
1403 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1407 for (i
= 0; i
< insn
->nfixups
; i
++)
1409 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1410 int size
, pcrel
, offset
= 0;
1412 /* FIXME! the reloc size is wrong in the BFD file.
1413 When it is fixed please delete me. */
1414 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1419 /* Some fixups are only used internally, thus no howto. */
1420 if ((int) fixup
->reloc
== 0)
1421 as_fatal (_("Unhandled reloc type"));
1423 if ((int) fixup
->reloc
< 0)
1425 /* FIXME! the reloc size is wrong in the BFD file.
1426 When it is fixed please enable me.
1427 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1428 pcrel
= fixup
->pcrel
;
1432 reloc_howto_type
*reloc_howto
=
1433 bfd_reloc_type_lookup (stdoutput
,
1434 (bfd_reloc_code_real_type
) fixup
->reloc
);
1435 gas_assert (reloc_howto
);
1437 /* FIXME! the reloc size is wrong in the BFD file.
1438 When it is fixed please enable me.
1439 size = bfd_get_reloc_size (reloc_howto); */
1440 pcrel
= reloc_howto
->pc_relative
;
1443 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1445 fragP
->fr_file
, fragP
->fr_line
,
1446 (fixup
->reloc
< 0) ? "Internal" :
1447 bfd_get_reloc_code_name (fixup
->reloc
),
1450 fix_new_exp (fragP
, fix
+ offset
,
1451 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1453 /* Check for ZOLs, and update symbol info if any. */
1454 if (LP_INSN (insn
->insn
))
1456 gas_assert (fixup
->exp
.X_add_symbol
);
1457 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1462 /* Actually output an instruction with its fixup. */
1465 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1470 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1471 pr_debug ("\tLength : 0x%d\n", insn
->len
);
1472 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1474 /* Write out the instruction. */
1475 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1477 f
= frag_more (total_len
);
1479 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1482 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1483 dwarf2_emit_insn (total_len
);
1486 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1490 emit_insn1 (struct arc_insn
*insn
)
1492 /* How frag_var's args are currently configured:
1493 - rs_machine_dependent, to dictate it's a relaxation frag.
1494 - FRAG_MAX_GROWTH, maximum size of instruction
1495 - 0, variable size that might grow...unused by generic relaxation.
1496 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1497 - s, opand expression.
1498 - 0, offset but it's unused.
1499 - 0, opcode but it's unused. */
1500 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1501 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1503 if (frag_room () < FRAG_MAX_GROWTH
)
1505 /* Handle differently when frag literal memory is exhausted.
1506 This is used because when there's not enough memory left in
1507 the current frag, a new frag is created and the information
1508 we put into frag_now->tc_frag_data is disregarded. */
1510 struct arc_relax_type relax_info_copy
;
1511 relax_substateT subtype
= frag_now
->fr_subtype
;
1513 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1514 sizeof (struct arc_relax_type
));
1516 frag_wane (frag_now
);
1517 frag_grow (FRAG_MAX_GROWTH
);
1519 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1520 sizeof (struct arc_relax_type
));
1522 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1526 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1527 frag_now
->fr_subtype
, s
, 0, 0);
1531 emit_insn (struct arc_insn
*insn
)
1536 emit_insn0 (insn
, NULL
, FALSE
);
1539 /* Check whether a symbol involves a register. */
1542 contains_register (symbolS
*sym
)
1546 expressionS
*ex
= symbol_get_value_expression (sym
);
1548 return ((O_register
== ex
->X_op
)
1549 && !contains_register (ex
->X_add_symbol
)
1550 && !contains_register (ex
->X_op_symbol
));
1556 /* Returns the register number within a symbol. */
1559 get_register (symbolS
*sym
)
1561 if (!contains_register (sym
))
1564 expressionS
*ex
= symbol_get_value_expression (sym
);
1565 return regno (ex
->X_add_number
);
1568 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1569 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1572 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1579 case BFD_RELOC_ARC_SDA_LDST
:
1580 case BFD_RELOC_ARC_SDA_LDST1
:
1581 case BFD_RELOC_ARC_SDA_LDST2
:
1582 case BFD_RELOC_ARC_SDA16_LD
:
1583 case BFD_RELOC_ARC_SDA16_LD1
:
1584 case BFD_RELOC_ARC_SDA16_LD2
:
1585 case BFD_RELOC_ARC_SDA16_ST2
:
1586 case BFD_RELOC_ARC_SDA32_ME
:
1593 /* Allocates a tok entry. */
1596 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1598 if (ntok
> MAX_INSN_ARGS
- 2)
1599 return 0; /* No space left. */
1602 return 0; /* Incorrect args. */
1604 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1607 return 1; /* Success. */
1608 return allocate_tok (tok
, ntok
- 1, cidx
);
1611 /* Check if an particular ARC feature is enabled. */
1614 check_cpu_feature (insn_subclass_t sc
)
1616 if (is_code_density_p (sc
) && !(selected_cpu
.features
& CD
))
1619 if (is_spfp_p (sc
) && !(selected_cpu
.features
& SPX
))
1622 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& DPX
))
1625 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& DPA
))
1628 if (is_nps400_p (sc
) && !(selected_cpu
.features
& NPS400
))
1634 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1635 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1636 array and returns TRUE if the flag operands all match, otherwise,
1637 returns FALSE, in which case the FIRST_PFLAG array may have been
1641 parse_opcode_flags (const struct arc_opcode
*opcode
,
1643 struct arc_flags
*first_pflag
)
1646 const unsigned char *flgidx
;
1649 for (i
= 0; i
< nflgs
; i
++)
1650 first_pflag
[i
].flgp
= NULL
;
1652 /* Check the flags. Iterate over the valid flag classes. */
1653 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1655 /* Get a valid flag class. */
1656 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1657 const unsigned *flgopridx
;
1659 struct arc_flags
*pflag
= NULL
;
1661 /* Check if opcode has implicit flag classes. */
1662 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
1665 /* Check for extension conditional codes. */
1666 if (ext_condcode
.arc_ext_condcode
1667 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1669 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1672 pflag
= first_pflag
;
1673 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1675 if (!strcmp (pf
->name
, pflag
->name
))
1677 if (pflag
->flgp
!= NULL
)
1690 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1692 const struct arc_flag_operand
*flg_operand
;
1694 pflag
= first_pflag
;
1695 flg_operand
= &arc_flag_operands
[*flgopridx
];
1696 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1698 /* Match against the parsed flags. */
1699 if (!strcmp (flg_operand
->name
, pflag
->name
))
1701 if (pflag
->flgp
!= NULL
)
1704 pflag
->flgp
= flg_operand
;
1706 break; /* goto next flag class and parsed flag. */
1711 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1713 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1717 /* Did I check all the parsed flags? */
1718 return lnflg
? FALSE
: TRUE
;
1722 /* Search forward through all variants of an opcode looking for a
1725 static const struct arc_opcode
*
1726 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1729 struct arc_flags
*first_pflag
,
1732 const char **errmsg
)
1734 const struct arc_opcode
*opcode
;
1735 struct arc_opcode_hash_entry_iterator iter
;
1737 int got_cpu_match
= 0;
1738 expressionS bktok
[MAX_INSN_ARGS
];
1742 arc_opcode_hash_entry_iterator_init (&iter
);
1743 memset (&emptyE
, 0, sizeof (emptyE
));
1744 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1747 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1749 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1751 const unsigned char *opidx
;
1753 const expressionS
*t
= &emptyE
;
1755 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1756 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1758 /* Don't match opcodes that don't exist on this
1760 if (!(opcode
->cpu
& selected_cpu
.flags
))
1763 if (!check_cpu_feature (opcode
->subclass
))
1769 /* Check the operands. */
1770 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1772 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1774 /* Only take input from real operands. */
1775 if (ARC_OPERAND_IS_FAKE (operand
))
1778 /* When we expect input, make sure we have it. */
1782 /* Match operand type with expression type. */
1783 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1785 case ARC_OPERAND_ADDRTYPE
:
1789 /* Check to be an address type. */
1790 if (tok
[tokidx
].X_op
!= O_addrtype
)
1793 /* All address type operands need to have an insert
1794 method in order to check that we have the correct
1796 gas_assert (operand
->insert
!= NULL
);
1797 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1799 if (*errmsg
!= NULL
)
1804 case ARC_OPERAND_IR
:
1805 /* Check to be a register. */
1806 if ((tok
[tokidx
].X_op
!= O_register
1807 || !is_ir_num (tok
[tokidx
].X_add_number
))
1808 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1811 /* If expect duplicate, make sure it is duplicate. */
1812 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1814 /* Check for duplicate. */
1815 if (t
->X_op
!= O_register
1816 || !is_ir_num (t
->X_add_number
)
1817 || (regno (t
->X_add_number
) !=
1818 regno (tok
[tokidx
].X_add_number
)))
1822 /* Special handling? */
1823 if (operand
->insert
)
1826 (*operand
->insert
)(0,
1827 regno (tok
[tokidx
].X_add_number
),
1831 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1833 /* Missing argument, create one. */
1834 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1837 tok
[tokidx
].X_op
= O_absent
;
1848 case ARC_OPERAND_BRAKET
:
1849 /* Check if bracket is also in opcode table as
1851 if (tok
[tokidx
].X_op
!= O_bracket
)
1855 case ARC_OPERAND_COLON
:
1856 /* Check if colon is also in opcode table as operand. */
1857 if (tok
[tokidx
].X_op
!= O_colon
)
1861 case ARC_OPERAND_LIMM
:
1862 case ARC_OPERAND_SIGNED
:
1863 case ARC_OPERAND_UNSIGNED
:
1864 switch (tok
[tokidx
].X_op
)
1872 /* Got an (too) early bracket, check if it is an
1873 ignored operand. N.B. This procedure works only
1874 when bracket is the last operand! */
1875 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1877 /* Insert the missing operand. */
1878 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1881 tok
[tokidx
].X_op
= O_absent
;
1889 const struct arc_aux_reg
*auxr
;
1891 if (opcode
->insn_class
!= AUXREG
)
1893 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1895 /* For compatibility reasons, an aux register can
1896 be spelled with upper or lower case
1899 for (pp
= tmpp
; *pp
; ++pp
) *pp
= TOLOWER (*pp
);
1901 auxr
= hash_find (arc_aux_hash
, tmpp
);
1904 /* We modify the token array here, safe in the
1905 knowledge, that if this was the wrong
1906 choice then the original contents will be
1907 restored from BKTOK. */
1908 tok
[tokidx
].X_op
= O_constant
;
1909 tok
[tokidx
].X_add_number
= auxr
->address
;
1910 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1914 if (tok
[tokidx
].X_op
!= O_constant
)
1919 /* Check the range. */
1920 if (operand
->bits
!= 32
1921 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1923 offsetT min
, max
, val
;
1924 val
= tok
[tokidx
].X_add_number
;
1926 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1928 max
= (1 << (operand
->bits
- 1)) - 1;
1929 min
= -(1 << (operand
->bits
- 1));
1933 max
= (1 << operand
->bits
) - 1;
1937 if (val
< min
|| val
> max
)
1940 /* Check alignments. */
1941 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1945 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1949 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1951 if (operand
->insert
)
1954 (*operand
->insert
)(0,
1955 tok
[tokidx
].X_add_number
,
1960 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1966 /* Check if it is register range. */
1967 if ((tok
[tokidx
].X_add_number
== 0)
1968 && contains_register (tok
[tokidx
].X_add_symbol
)
1969 && contains_register (tok
[tokidx
].X_op_symbol
))
1973 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1975 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1976 if (operand
->insert
)
1979 (*operand
->insert
)(0,
1992 if (operand
->default_reloc
== 0)
1993 goto match_failed
; /* The operand needs relocation. */
1995 /* Relocs requiring long immediate. FIXME! make it
1996 generic and move it to a function. */
1997 switch (tok
[tokidx
].X_md
)
2006 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
2010 if (!generic_reloc_p (operand
->default_reloc
))
2018 /* If expect duplicate, make sure it is duplicate. */
2019 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
2021 if (t
->X_op
== O_illegal
2022 || t
->X_op
== O_absent
2023 || t
->X_op
== O_register
2024 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2031 /* Everything else should have been fake. */
2039 /* Setup ready for flag parsing. */
2040 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2044 /* Possible match -- did we use all of our input? */
2054 /* Restore the original parameters. */
2055 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2060 *pcpumatch
= got_cpu_match
;
2065 /* Swap operand tokens. */
2068 swap_operand (expressionS
*operand_array
,
2070 unsigned destination
)
2072 expressionS cpy_operand
;
2073 expressionS
*src_operand
;
2074 expressionS
*dst_operand
;
2077 if (source
== destination
)
2080 src_operand
= &operand_array
[source
];
2081 dst_operand
= &operand_array
[destination
];
2082 size
= sizeof (expressionS
);
2084 /* Make copy of operand to swap with and swap. */
2085 memcpy (&cpy_operand
, dst_operand
, size
);
2086 memcpy (dst_operand
, src_operand
, size
);
2087 memcpy (src_operand
, &cpy_operand
, size
);
2090 /* Check if *op matches *tok type.
2091 Returns FALSE if they don't match, TRUE if they match. */
2094 pseudo_operand_match (const expressionS
*tok
,
2095 const struct arc_operand_operation
*op
)
2097 offsetT min
, max
, val
;
2099 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2105 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2107 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2109 val
= tok
->X_add_number
+ op
->count
;
2110 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2112 max
= (1 << (operand_real
->bits
- 1)) - 1;
2113 min
= -(1 << (operand_real
->bits
- 1));
2117 max
= (1 << operand_real
->bits
) - 1;
2120 if (min
<= val
&& val
<= max
)
2126 /* Handle all symbols as long immediates or signed 9. */
2127 if (operand_real
->flags
& ARC_OPERAND_LIMM
2128 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2129 && operand_real
->bits
== 9))
2134 if (operand_real
->flags
& ARC_OPERAND_IR
)
2139 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2150 /* Find pseudo instruction in array. */
2152 static const struct arc_pseudo_insn
*
2153 find_pseudo_insn (const char *opname
,
2155 const expressionS
*tok
)
2157 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2158 const struct arc_operand_operation
*op
;
2162 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2164 pseudo_insn
= &arc_pseudo_insns
[i
];
2165 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2167 op
= pseudo_insn
->operand
;
2168 for (j
= 0; j
< ntok
; ++j
)
2169 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2172 /* Found the right instruction. */
2180 /* Assumes the expressionS *tok is of sufficient size. */
2182 static const struct arc_opcode_hash_entry
*
2183 find_special_case_pseudo (const char *opname
,
2187 struct arc_flags
*pflags
)
2189 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2190 const struct arc_operand_operation
*operand_pseudo
;
2191 const struct arc_operand
*operand_real
;
2193 char construct_operand
[MAX_CONSTR_STR
];
2195 /* Find whether opname is in pseudo instruction array. */
2196 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2198 if (pseudo_insn
== NULL
)
2201 /* Handle flag, Limited to one flag at the moment. */
2202 if (pseudo_insn
->flag_r
!= NULL
)
2203 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2204 MAX_INSN_FLGS
- *nflgs
);
2206 /* Handle operand operations. */
2207 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2209 operand_pseudo
= &pseudo_insn
->operand
[i
];
2210 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2212 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2213 && !operand_pseudo
->needs_insert
)
2216 /* Has to be inserted (i.e. this token does not exist yet). */
2217 if (operand_pseudo
->needs_insert
)
2219 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2221 tok
[i
].X_op
= O_bracket
;
2226 /* Check if operand is a register or constant and handle it
2228 if (operand_real
->flags
& ARC_OPERAND_IR
)
2229 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2230 operand_pseudo
->count
);
2232 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2233 operand_pseudo
->count
);
2235 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2239 else if (operand_pseudo
->count
)
2241 /* Operand number has to be adjusted accordingly (by operand
2243 switch (tok
[i
].X_op
)
2246 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2259 /* Swap operands if necessary. Only supports one swap at the
2261 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2263 operand_pseudo
= &pseudo_insn
->operand
[i
];
2265 if (operand_pseudo
->swap_operand_idx
== i
)
2268 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2270 /* Prevent a swap back later by breaking out. */
2274 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2277 static const struct arc_opcode_hash_entry
*
2278 find_special_case_flag (const char *opname
,
2280 struct arc_flags
*pflags
)
2284 unsigned flag_idx
, flag_arr_idx
;
2285 size_t flaglen
, oplen
;
2286 const struct arc_flag_special
*arc_flag_special_opcode
;
2287 const struct arc_opcode_hash_entry
*entry
;
2289 /* Search for special case instruction. */
2290 for (i
= 0; i
< arc_num_flag_special
; i
++)
2292 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2293 oplen
= strlen (arc_flag_special_opcode
->name
);
2295 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2298 /* Found a potential special case instruction, now test for
2300 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2302 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2304 break; /* End of array, nothing found. */
2306 flagnm
= arc_flag_operands
[flag_idx
].name
;
2307 flaglen
= strlen (flagnm
);
2308 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2310 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2312 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2314 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2315 pflags
[*nflgs
].name
[flaglen
] = '\0';
2324 /* Used to find special case opcode. */
2326 static const struct arc_opcode_hash_entry
*
2327 find_special_case (const char *opname
,
2329 struct arc_flags
*pflags
,
2333 const struct arc_opcode_hash_entry
*entry
;
2335 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2338 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2343 /* Autodetect cpu attribute list. */
2346 autodetect_attributes (const struct arc_opcode
*opcode
,
2347 const expressionS
*tok
,
2355 } mpy_list
[] = {{ MPY1E
, 1 }, { MPY6E
, 6 }, { MPY7E
, 7 }, { MPY8E
, 8 },
2358 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
2359 if (opcode
->subclass
== feature_list
[i
].feature
)
2360 selected_cpu
.features
|= feature_list
[i
].feature
;
2362 for (i
= 0; i
< ARRAY_SIZE (mpy_list
); i
++)
2363 if (opcode
->subclass
== mpy_list
[i
].feature
)
2364 mpy_option
= mpy_list
[i
].encoding
;
2366 for (i
= 0; i
< (unsigned) ntok
; i
++)
2368 switch (tok
[i
].X_md
)
2390 switch (tok
[i
].X_op
)
2393 if ((tok
[i
].X_add_number
>= 4 && tok
[i
].X_add_number
<= 9)
2394 || (tok
[i
].X_add_number
>= 16 && tok
[i
].X_add_number
<= 25))
2403 /* Given an opcode name, pre-tockenized set of argumenst and the
2404 opcode flags, take it all the way through emission. */
2407 assemble_tokens (const char *opname
,
2410 struct arc_flags
*pflags
,
2413 bfd_boolean found_something
= FALSE
;
2414 const struct arc_opcode_hash_entry
*entry
;
2416 const char *errmsg
= NULL
;
2418 /* Search opcodes. */
2419 entry
= arc_find_opcode (opname
);
2421 /* Couldn't find opcode conventional way, try special cases. */
2423 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2427 const struct arc_opcode
*opcode
;
2429 pr_debug ("%s:%d: assemble_tokens: %s\n",
2430 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2431 found_something
= TRUE
;
2432 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2433 nflgs
, &cpumatch
, &errmsg
);
2436 struct arc_insn insn
;
2438 autodetect_attributes (opcode
, tok
, ntok
);
2439 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2445 if (found_something
)
2449 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2451 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2453 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2457 as_bad (_("unknown opcode '%s'"), opname
);
2460 /* The public interface to the instruction assembler. */
2463 md_assemble (char *str
)
2466 expressionS tok
[MAX_INSN_ARGS
];
2469 struct arc_flags flags
[MAX_INSN_FLGS
];
2471 /* Split off the opcode. */
2472 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2473 opname
= xmemdup0 (str
, opnamelen
);
2475 /* Signalize we are assembling the instructions. */
2476 assembling_insn
= TRUE
;
2478 /* Tokenize the flags. */
2479 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2481 as_bad (_("syntax error"));
2485 /* Scan up to the end of the mnemonic which must end in space or end
2488 for (; *str
!= '\0'; str
++)
2492 /* Tokenize the rest of the line. */
2493 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2495 as_bad (_("syntax error"));
2499 /* Finish it off. */
2500 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2501 assembling_insn
= FALSE
;
2504 /* Callback to insert a register into the hash table. */
2507 declare_register (const char *name
, int number
)
2510 symbolS
*regS
= symbol_create (name
, reg_section
,
2511 number
, &zero_address_frag
);
2513 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2515 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2519 /* Construct symbols for each of the general registers. */
2522 declare_register_set (void)
2525 for (i
= 0; i
< 64; ++i
)
2529 sprintf (name
, "r%d", i
);
2530 declare_register (name
, i
);
2531 if ((i
& 0x01) == 0)
2533 sprintf (name
, "r%dr%d", i
, i
+1);
2534 declare_register (name
, i
);
2539 /* Construct a symbol for an address type. */
2542 declare_addrtype (const char *name
, int number
)
2545 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2546 number
, &zero_address_frag
);
2548 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2549 (void *) addrtypeS
);
2551 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2555 /* Port-specific assembler initialization. This function is called
2556 once, at assembler startup time. */
2561 const struct arc_opcode
*opcode
= arc_opcodes
;
2563 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2564 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2566 /* The endianness can be chosen "at the factory". */
2567 target_big_endian
= byte_order
== BIG_ENDIAN
;
2569 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2570 as_warn (_("could not set architecture and machine"));
2572 /* Set elf header flags. */
2573 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2575 /* Set up a hash table for the instructions. */
2576 arc_opcode_hash
= hash_new ();
2577 if (arc_opcode_hash
== NULL
)
2578 as_fatal (_("Virtual memory exhausted"));
2580 /* Initialize the hash table with the insns. */
2583 const char *name
= opcode
->name
;
2585 arc_insert_opcode (opcode
);
2587 while (++opcode
&& opcode
->name
2588 && (opcode
->name
== name
2589 || !strcmp (opcode
->name
, name
)))
2591 }while (opcode
->name
);
2593 /* Register declaration. */
2594 arc_reg_hash
= hash_new ();
2595 if (arc_reg_hash
== NULL
)
2596 as_fatal (_("Virtual memory exhausted"));
2598 declare_register_set ();
2599 declare_register ("gp", 26);
2600 declare_register ("fp", 27);
2601 declare_register ("sp", 28);
2602 declare_register ("ilink", 29);
2603 declare_register ("ilink1", 29);
2604 declare_register ("ilink2", 30);
2605 declare_register ("blink", 31);
2607 /* XY memory registers. */
2608 declare_register ("x0_u0", 32);
2609 declare_register ("x0_u1", 33);
2610 declare_register ("x1_u0", 34);
2611 declare_register ("x1_u1", 35);
2612 declare_register ("x2_u0", 36);
2613 declare_register ("x2_u1", 37);
2614 declare_register ("x3_u0", 38);
2615 declare_register ("x3_u1", 39);
2616 declare_register ("y0_u0", 40);
2617 declare_register ("y0_u1", 41);
2618 declare_register ("y1_u0", 42);
2619 declare_register ("y1_u1", 43);
2620 declare_register ("y2_u0", 44);
2621 declare_register ("y2_u1", 45);
2622 declare_register ("y3_u0", 46);
2623 declare_register ("y3_u1", 47);
2624 declare_register ("x0_nu", 48);
2625 declare_register ("x1_nu", 49);
2626 declare_register ("x2_nu", 50);
2627 declare_register ("x3_nu", 51);
2628 declare_register ("y0_nu", 52);
2629 declare_register ("y1_nu", 53);
2630 declare_register ("y2_nu", 54);
2631 declare_register ("y3_nu", 55);
2633 declare_register ("mlo", 57);
2634 declare_register ("mmid", 58);
2635 declare_register ("mhi", 59);
2637 declare_register ("acc1", 56);
2638 declare_register ("acc2", 57);
2640 declare_register ("lp_count", 60);
2641 declare_register ("pcl", 63);
2643 /* Initialize the last instructions. */
2644 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2646 /* Aux register declaration. */
2647 arc_aux_hash
= hash_new ();
2648 if (arc_aux_hash
== NULL
)
2649 as_fatal (_("Virtual memory exhausted"));
2651 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2653 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2657 if (!(auxr
->cpu
& selected_cpu
.flags
))
2660 if ((auxr
->subclass
!= NONE
)
2661 && !check_cpu_feature (auxr
->subclass
))
2664 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2666 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2667 auxr
->name
, retval
);
2670 /* Address type declaration. */
2671 arc_addrtype_hash
= hash_new ();
2672 if (arc_addrtype_hash
== NULL
)
2673 as_fatal (_("Virtual memory exhausted"));
2675 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2676 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2677 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2678 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2679 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2680 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2681 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2682 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2683 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2684 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2685 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2686 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2687 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2688 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2689 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2690 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2693 /* Write a value out to the object file, using the appropriate
2697 md_number_to_chars (char *buf
,
2701 if (target_big_endian
)
2702 number_to_chars_bigendian (buf
, val
, n
);
2704 number_to_chars_littleendian (buf
, val
, n
);
2707 /* Round up a section size to the appropriate boundary. */
2710 md_section_align (segT segment
,
2713 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2715 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2718 /* The location from which a PC relative jump should be calculated,
2719 given a PC relative reloc. */
2722 md_pcrel_from_section (fixS
*fixP
,
2725 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2727 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2729 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2730 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2731 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2733 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2735 /* The symbol is undefined (or is defined but not in this section).
2736 Let the linker figure it out. */
2740 if ((int) fixP
->fx_r_type
< 0)
2742 /* These are the "internal" relocations. Align them to
2743 32 bit boundary (PCL), for the moment. */
2748 switch (fixP
->fx_r_type
)
2750 case BFD_RELOC_ARC_PC32
:
2751 /* The hardware calculates relative to the start of the
2752 insn, but this relocation is relative to location of the
2753 LIMM, compensate. The base always needs to be
2754 subtracted by 4 as we do not support this type of PCrel
2755 relocation for short instructions. */
2758 case BFD_RELOC_ARC_PLT32
:
2759 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2760 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2761 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2762 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2764 case BFD_RELOC_ARC_S21H_PCREL
:
2765 case BFD_RELOC_ARC_S25H_PCREL
:
2766 case BFD_RELOC_ARC_S13_PCREL
:
2767 case BFD_RELOC_ARC_S21W_PCREL
:
2768 case BFD_RELOC_ARC_S25W_PCREL
:
2772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2773 _("unhandled reloc %s in md_pcrel_from_section"),
2774 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2779 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2780 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2781 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2782 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2783 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2788 /* Given a BFD relocation find the corresponding operand. */
2790 static const struct arc_operand
*
2791 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2795 for (i
= 0; i
< arc_num_operands
; i
++)
2796 if (arc_operands
[i
].default_reloc
== reloc
)
2797 return &arc_operands
[i
];
2801 /* Insert an operand value into an instruction. */
2803 static unsigned long long
2804 insert_operand (unsigned long long insn
,
2805 const struct arc_operand
*operand
,
2810 offsetT min
= 0, max
= 0;
2812 if (operand
->bits
!= 32
2813 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2814 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2816 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2818 max
= (1 << (operand
->bits
- 1)) - 1;
2819 min
= -(1 << (operand
->bits
- 1));
2823 max
= (1 << operand
->bits
) - 1;
2827 if (val
< min
|| val
> max
)
2828 as_bad_value_out_of_range (_("operand"),
2829 val
, min
, max
, file
, line
);
2832 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2833 min
, val
, max
, insn
);
2835 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2837 as_bad_where (file
, line
,
2838 _("Unaligned operand. Needs to be 32bit aligned"));
2840 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2842 as_bad_where (file
, line
,
2843 _("Unaligned operand. Needs to be 16bit aligned"));
2845 if (operand
->insert
)
2847 const char *errmsg
= NULL
;
2849 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2851 as_warn_where (file
, line
, "%s", errmsg
);
2855 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2857 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2859 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2862 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2867 /* Apply a fixup to the object code. At this point all symbol values
2868 should be fully resolved, and we attempt to completely resolve the
2869 reloc. If we can not do that, we determine the correct reloc code
2870 and put it back in the fixup. To indicate that a fixup has been
2871 eliminated, set fixP->fx_done. */
2874 md_apply_fix (fixS
*fixP
,
2878 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2879 valueT value
= *valP
;
2881 symbolS
*fx_addsy
, *fx_subsy
;
2883 segT add_symbol_segment
= absolute_section
;
2884 segT sub_symbol_segment
= absolute_section
;
2885 const struct arc_operand
*operand
= NULL
;
2886 extended_bfd_reloc_code_real_type reloc
;
2888 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2889 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2890 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2891 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2894 fx_addsy
= fixP
->fx_addsy
;
2895 fx_subsy
= fixP
->fx_subsy
;
2900 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2904 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2905 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2906 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2908 resolve_symbol_value (fx_subsy
);
2909 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2911 if (sub_symbol_segment
== absolute_section
)
2913 /* The symbol is really a constant. */
2914 fx_offset
-= S_GET_VALUE (fx_subsy
);
2919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2920 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2921 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2922 segment_name (add_symbol_segment
),
2923 S_GET_NAME (fx_subsy
),
2924 segment_name (sub_symbol_segment
));
2930 && !S_IS_WEAK (fx_addsy
))
2932 if (add_symbol_segment
== seg
2935 value
+= S_GET_VALUE (fx_addsy
);
2936 value
-= md_pcrel_from_section (fixP
, seg
);
2938 fixP
->fx_pcrel
= FALSE
;
2940 else if (add_symbol_segment
== absolute_section
)
2942 value
= fixP
->fx_offset
;
2943 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2945 fixP
->fx_pcrel
= FALSE
;
2950 fixP
->fx_done
= TRUE
;
2955 && ((S_IS_DEFINED (fx_addsy
)
2956 && S_GET_SEGMENT (fx_addsy
) != seg
)
2957 || S_IS_WEAK (fx_addsy
)))
2958 value
+= md_pcrel_from_section (fixP
, seg
);
2960 switch (fixP
->fx_r_type
)
2962 case BFD_RELOC_ARC_32_ME
:
2963 /* This is a pc-relative value in a LIMM. Adjust it to the
2964 address of the instruction not to the address of the
2965 LIMM. Note: it is not any longer valid this affirmation as
2966 the linker consider ARC_PC32 a fixup to entire 64 bit
2968 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2971 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2973 case BFD_RELOC_ARC_PC32
:
2974 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2977 if ((int) fixP
->fx_r_type
< 0)
2978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2979 _("PC relative relocation not allowed for (internal)"
2986 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2987 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2988 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2989 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2993 /* Now check for TLS relocations. */
2994 reloc
= fixP
->fx_r_type
;
2997 case BFD_RELOC_ARC_TLS_DTPOFF
:
2998 case BFD_RELOC_ARC_TLS_LE_32
:
3002 case BFD_RELOC_ARC_TLS_GD_GOT
:
3003 case BFD_RELOC_ARC_TLS_IE_GOT
:
3004 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3007 case BFD_RELOC_ARC_TLS_GD_LD
:
3008 gas_assert (!fixP
->fx_offset
);
3011 = (S_GET_VALUE (fixP
->fx_subsy
)
3012 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
3013 fixP
->fx_subsy
= NULL
;
3015 case BFD_RELOC_ARC_TLS_GD_CALL
:
3016 /* These two relocs are there just to allow ld to change the tls
3017 model for this symbol, by patching the code. The offset -
3018 and scale, if any - will be installed by the linker. */
3019 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3022 case BFD_RELOC_ARC_TLS_LE_S9
:
3023 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
3024 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3036 /* Adjust the value if we have a constant. */
3039 /* For hosts with longs bigger than 32-bits make sure that the top
3040 bits of a 32-bit negative value read in by the parser are set,
3041 so that the correct comparisons are made. */
3042 if (value
& 0x80000000)
3043 value
|= (-1UL << 31);
3045 reloc
= fixP
->fx_r_type
;
3053 case BFD_RELOC_ARC_32_PCREL
:
3054 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3057 case BFD_RELOC_ARC_GOTPC32
:
3058 /* I cannot fix an GOTPC relocation because I need to relax it
3059 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3060 as_bad (_("Unsupported operation on reloc"));
3063 case BFD_RELOC_ARC_TLS_DTPOFF
:
3064 case BFD_RELOC_ARC_TLS_LE_32
:
3065 gas_assert (!fixP
->fx_addsy
);
3066 gas_assert (!fixP
->fx_subsy
);
3069 case BFD_RELOC_ARC_GOTOFF
:
3070 case BFD_RELOC_ARC_32_ME
:
3071 case BFD_RELOC_ARC_PC32
:
3072 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3075 case BFD_RELOC_ARC_PLT32
:
3076 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3079 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3080 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3083 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3084 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3087 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3088 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3091 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3092 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3095 case BFD_RELOC_ARC_S25W_PCREL
:
3096 case BFD_RELOC_ARC_S21W_PCREL
:
3097 case BFD_RELOC_ARC_S21H_PCREL
:
3098 case BFD_RELOC_ARC_S25H_PCREL
:
3099 case BFD_RELOC_ARC_S13_PCREL
:
3101 operand
= find_operand_for_reloc (reloc
);
3102 gas_assert (operand
);
3107 if ((int) fixP
->fx_r_type
>= 0)
3108 as_fatal (_("unhandled relocation type %s"),
3109 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3111 /* The rest of these fixups needs to be completely resolved as
3113 if (fixP
->fx_addsy
!= 0
3114 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3116 _("non-absolute expression in constant field"));
3118 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3119 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3124 if (target_big_endian
)
3126 switch (fixP
->fx_size
)
3129 insn
= bfd_getb32 (fixpos
);
3132 insn
= bfd_getb16 (fixpos
);
3135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3136 _("unknown fixup size"));
3142 switch (fixP
->fx_size
)
3145 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3148 insn
= bfd_getl16 (fixpos
);
3151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3152 _("unknown fixup size"));
3156 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3157 fixP
->fx_file
, fixP
->fx_line
);
3159 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3162 /* Prepare machine-dependent frags for relaxation.
3164 Called just before relaxation starts. Any symbol that is now undefined
3165 will not become defined.
3167 Return the correct fr_subtype in the frag.
3169 Return the initial "guess for fr_var" to caller. The guess for fr_var
3170 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3171 or fr_var contributes to our returned value.
3173 Although it may not be explicit in the frag, pretend
3174 fr_var starts with a value. */
3177 md_estimate_size_before_relax (fragS
*fragP
,
3182 /* If the symbol is not located within the same section AND it's not
3183 an absolute section, use the maximum. OR if the symbol is a
3184 constant AND the insn is by nature not pc-rel, use the maximum.
3185 OR if the symbol is being equated against another symbol, use the
3186 maximum. OR if the symbol is weak use the maximum. */
3187 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3188 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3189 || (symbol_constant_p (fragP
->fr_symbol
)
3190 && !fragP
->tc_frag_data
.pcrel
)
3191 || symbol_equated_p (fragP
->fr_symbol
)
3192 || S_IS_WEAK (fragP
->fr_symbol
))
3194 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3195 ++fragP
->fr_subtype
;
3198 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3199 fragP
->fr_var
= growth
;
3201 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3202 fragP
->fr_file
, fragP
->fr_line
, growth
);
3207 /* Translate internal representation of relocation info to BFD target
3211 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3215 bfd_reloc_code_real_type code
;
3217 reloc
= XNEW (arelent
);
3218 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3219 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3220 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3222 /* Make sure none of our internal relocations make it this far.
3223 They'd better have been fully resolved by this point. */
3224 gas_assert ((int) fixP
->fx_r_type
> 0);
3226 code
= fixP
->fx_r_type
;
3228 /* if we have something like add gp, pcl,
3229 _GLOBAL_OFFSET_TABLE_@gotpc. */
3230 if (code
== BFD_RELOC_ARC_GOTPC32
3232 && fixP
->fx_addsy
== GOT_symbol
)
3233 code
= BFD_RELOC_ARC_GOTPC
;
3235 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3236 if (reloc
->howto
== NULL
)
3238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3239 _("cannot represent `%s' relocation in object file"),
3240 bfd_get_reloc_code_name (code
));
3244 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3245 as_fatal (_("internal error? cannot generate `%s' relocation"),
3246 bfd_get_reloc_code_name (code
));
3248 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3250 reloc
->addend
= fixP
->fx_offset
;
3255 /* Perform post-processing of machine-dependent frags after relaxation.
3256 Called after relaxation is finished.
3257 In: Address of frag.
3258 fr_type == rs_machine_dependent.
3259 fr_subtype is what the address relaxed to.
3261 Out: Any fixS:s and constants are set up. */
3264 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3265 segT segment ATTRIBUTE_UNUSED
,
3268 const relax_typeS
*table_entry
;
3270 const struct arc_opcode
*opcode
;
3271 struct arc_insn insn
;
3273 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3275 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3276 dest
= fragP
->fr_literal
+ fix
;
3277 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3279 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3280 "var: %"BFD_VMA_FMT
"d\n",
3281 fragP
->fr_file
, fragP
->fr_line
,
3282 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3284 if (fragP
->fr_subtype
<= 0
3285 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3286 as_fatal (_("no relaxation found for this instruction."));
3288 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3290 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3291 relax_arg
->nflg
, &insn
);
3293 apply_fixups (&insn
, fragP
, fix
);
3295 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3296 gas_assert (table_entry
->rlx_length
== size
);
3297 emit_insn0 (&insn
, dest
, TRUE
);
3299 fragP
->fr_fix
+= table_entry
->rlx_length
;
3303 /* We have no need to default values of symbols. We could catch
3304 register names here, but that is handled by inserting them all in
3305 the symbol table to begin with. */
3308 md_undefined_symbol (char *name
)
3310 /* The arc abi demands that a GOT[0] should be referencible as
3311 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3312 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3314 && (*(name
+1) == 'G')
3315 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)))
3319 if (symbol_find (name
))
3320 as_bad ("GOT already in symbol table");
3322 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3323 (valueT
) 0, &zero_address_frag
);
3330 /* Turn a string in input_line_pointer into a floating point constant
3331 of type type, and store the appropriate bytes in *litP. The number
3332 of LITTLENUMS emitted is stored in *sizeP. An error message is
3333 returned, or NULL on OK. */
3336 md_atof (int type
, char *litP
, int *sizeP
)
3338 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3341 /* Called for any expression that can not be recognized. When the
3342 function is called, `input_line_pointer' will point to the start of
3346 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3348 char *p
= input_line_pointer
;
3351 input_line_pointer
++;
3352 expressionP
->X_op
= O_symbol
;
3353 expression (expressionP
);
3357 /* This function is called from the function 'expression', it attempts
3358 to parse special names (in our case register names). It fills in
3359 the expression with the identified register. It returns TRUE if
3360 it is a register and FALSE otherwise. */
3363 arc_parse_name (const char *name
,
3364 struct expressionS
*e
)
3368 if (!assembling_insn
)
3371 if (e
->X_op
== O_symbol
)
3374 sym
= hash_find (arc_reg_hash
, name
);
3377 e
->X_op
= O_register
;
3378 e
->X_add_number
= S_GET_VALUE (sym
);
3382 sym
= hash_find (arc_addrtype_hash
, name
);
3385 e
->X_op
= O_addrtype
;
3386 e
->X_add_number
= S_GET_VALUE (sym
);
3394 Invocation line includes a switch not recognized by the base assembler.
3395 See if it's a processor-specific option.
3397 New options (supported) are:
3399 -mcpu=<cpu name> Assemble for selected processor
3400 -EB/-mbig-endian Big-endian
3401 -EL/-mlittle-endian Little-endian
3402 -mrelax Enable relaxation
3404 The following CPU names are recognized:
3405 arc600, arc700, arcem, archs, nps400. */
3408 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3414 return md_parse_option (OPTION_MCPU
, "arc600");
3417 return md_parse_option (OPTION_MCPU
, "arc700");
3420 return md_parse_option (OPTION_MCPU
, "arcem");
3423 return md_parse_option (OPTION_MCPU
, "archs");
3427 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3432 arc_target_format
= "elf32-bigarc";
3433 byte_order
= BIG_ENDIAN
;
3437 arc_target_format
= "elf32-littlearc";
3438 byte_order
= LITTLE_ENDIAN
;
3442 selected_cpu
.features
|= CD
;
3444 arc_check_feature ();
3448 relaxation_state
= 1;
3452 selected_cpu
.features
|= NPS400
;
3453 cl_features
|= NPS400
;
3454 arc_check_feature ();
3458 selected_cpu
.features
|= SPX
;
3460 arc_check_feature ();
3464 selected_cpu
.features
|= DPX
;
3466 arc_check_feature ();
3470 selected_cpu
.features
|= DPA
;
3472 arc_check_feature ();
3475 /* Dummy options are accepted but have no effect. */
3476 case OPTION_USER_MODE
:
3477 case OPTION_LD_EXT_MASK
:
3480 case OPTION_BARREL_SHIFT
:
3481 case OPTION_MIN_MAX
:
3486 case OPTION_XMAC_D16
:
3487 case OPTION_XMAC_24
:
3488 case OPTION_DSP_PACKA
:
3491 case OPTION_TELEPHONY
:
3492 case OPTION_XYMEMORY
:
3505 /* Display the list of cpu names for use in the help text. */
3508 arc_show_cpu_list (FILE *stream
)
3511 static const char *space_buf
= " ";
3513 fprintf (stream
, "%s", space_buf
);
3514 offset
= strlen (space_buf
);
3515 for (i
= 0; cpu_types
[i
].name
!= NULL
; ++i
)
3517 bfd_boolean last
= (cpu_types
[i
+ 1].name
== NULL
);
3519 /* If displaying the new cpu name string, and the ', ' (for all
3520 but the last one) will take us past a target width of 80
3521 characters, then it's time for a new line. */
3522 if (offset
+ strlen (cpu_types
[i
].name
) + (last
? 0 : 2) > 80)
3524 fprintf (stream
, "\n%s", space_buf
);
3525 offset
= strlen (space_buf
);
3528 fprintf (stream
, "%s%s", cpu_types
[i
].name
, (last
? "\n" : ", "));
3529 offset
+= strlen (cpu_types
[i
].name
) + (last
? 0 : 2);
3534 md_show_usage (FILE *stream
)
3536 fprintf (stream
, _("ARC-specific assembler options:\n"));
3538 fprintf (stream
, " -mcpu=<cpu name>\t (default: %s), assemble for"
3539 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU
);
3540 arc_show_cpu_list (stream
);
3541 fprintf (stream
, "\n");
3542 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3543 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3544 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3545 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3547 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3548 fprintf (stream
, " -mspfp\t\t enable single-precision floating point"
3550 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point"
3552 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3553 "point\n\t\t\t instructions for ARC EM\n");
3556 " -mcode-density\t enable code density option for ARC EM\n");
3558 fprintf (stream
, _("\
3559 -EB assemble code for a big-endian cpu\n"));
3560 fprintf (stream
, _("\
3561 -EL assemble code for a little-endian cpu\n"));
3562 fprintf (stream
, _("\
3563 -mrelax enable relaxation\n"));
3565 fprintf (stream
, _("The following ARC-specific assembler options are "
3566 "deprecated and are accepted\nfor compatibility only:\n"));
3568 fprintf (stream
, _(" -mEA\n"
3569 " -mbarrel-shifter\n"
3570 " -mbarrel_shifter\n"
3575 " -mld-extension-reg-mask\n"
3591 " -muser-mode-only\n"
3595 /* Find the proper relocation for the given opcode. */
3597 static extended_bfd_reloc_code_real_type
3598 find_reloc (const char *name
,
3599 const char *opcodename
,
3600 const struct arc_flags
*pflags
,
3602 extended_bfd_reloc_code_real_type reloc
)
3606 bfd_boolean found_flag
, tmp
;
3607 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3609 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3611 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3613 /* Find the entry. */
3614 if (strcmp (name
, r
->name
))
3616 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3623 unsigned * psflg
= (unsigned *)r
->flags
;
3627 for (j
= 0; j
< nflg
; j
++)
3628 if (!strcmp (pflags
[j
].name
,
3629 arc_flag_operands
[*psflg
].name
))
3650 if (reloc
!= r
->oldreloc
)
3657 if (ret
== BFD_RELOC_UNUSED
)
3658 as_bad (_("Unable to find %s relocation for instruction %s"),
3663 /* All the symbol types that are allowed to be used for
3667 may_relax_expr (expressionS tok
)
3669 /* Check if we have unrelaxable relocs. */
3694 /* Checks if flags are in line with relaxable insn. */
3697 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3698 const struct arc_flags
*pflags
,
3701 unsigned flag_class
,
3706 const struct arc_flag_operand
*flag_opand
;
3707 int i
, counttrue
= 0;
3709 /* Iterate through flags classes. */
3710 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3712 /* Iterate through flags in flag class. */
3713 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3716 flag_opand
= &arc_flag_operands
[flag
];
3717 /* Iterate through flags in ins to compare. */
3718 for (i
= 0; i
< nflgs
; ++i
)
3720 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3731 /* If counttrue == nflgs, then all flags have been found. */
3732 return (counttrue
== nflgs
? TRUE
: FALSE
);
3735 /* Checks if operands are in line with relaxable insn. */
3738 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3739 const expressionS
*tok
,
3742 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3745 while (*operand
!= EMPTY
)
3747 const expressionS
*epr
= &tok
[i
];
3749 if (i
!= 0 && i
>= ntok
)
3755 if (!(epr
->X_op
== O_multiply
3756 || epr
->X_op
== O_divide
3757 || epr
->X_op
== O_modulus
3758 || epr
->X_op
== O_add
3759 || epr
->X_op
== O_subtract
3760 || epr
->X_op
== O_symbol
))
3766 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3770 if (epr
->X_op
!= O_register
)
3775 if (epr
->X_op
!= O_register
)
3778 switch (epr
->X_add_number
)
3780 case 0: case 1: case 2: case 3:
3781 case 12: case 13: case 14: case 15:
3788 case REGISTER_NO_GP
:
3789 if ((epr
->X_op
!= O_register
)
3790 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3795 if (epr
->X_op
!= O_bracket
)
3800 /* Don't understand, bail out. */
3806 operand
= &ins
->operands
[i
];
3809 return (i
== ntok
? TRUE
: FALSE
);
3812 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3815 relax_insn_p (const struct arc_opcode
*opcode
,
3816 const expressionS
*tok
,
3818 const struct arc_flags
*pflags
,
3822 bfd_boolean rv
= FALSE
;
3824 /* Check the relaxation table. */
3825 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3827 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3829 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3830 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3831 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3832 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3835 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3836 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3837 sizeof (expressionS
) * ntok
);
3838 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3839 sizeof (struct arc_flags
) * nflg
);
3840 frag_now
->tc_frag_data
.nflg
= nflg
;
3841 frag_now
->tc_frag_data
.ntok
= ntok
;
3849 /* Turn an opcode description and a set of arguments into
3850 an instruction and a fixup. */
3853 assemble_insn (const struct arc_opcode
*opcode
,
3854 const expressionS
*tok
,
3856 const struct arc_flags
*pflags
,
3858 struct arc_insn
*insn
)
3860 const expressionS
*reloc_exp
= NULL
;
3861 unsigned long long image
;
3862 const unsigned char *argidx
;
3865 unsigned char pcrel
= 0;
3866 bfd_boolean needGOTSymbol
;
3867 bfd_boolean has_delay_slot
= FALSE
;
3868 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3870 memset (insn
, 0, sizeof (*insn
));
3871 image
= opcode
->opcode
;
3873 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3874 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3877 /* Handle operands. */
3878 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3880 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3881 const expressionS
*t
= (const expressionS
*) 0;
3883 if (ARC_OPERAND_IS_FAKE (operand
))
3886 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3888 /* Duplicate operand, already inserted. */
3900 /* Regardless if we have a reloc or not mark the instruction
3901 limm if it is the case. */
3902 if (operand
->flags
& ARC_OPERAND_LIMM
)
3903 insn
->has_limm
= TRUE
;
3908 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3913 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3915 if (operand
->flags
& ARC_OPERAND_LIMM
)
3916 insn
->limm
= t
->X_add_number
;
3922 /* Ignore brackets, colons, and address types. */
3926 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3930 /* Maybe register range. */
3931 if ((t
->X_add_number
== 0)
3932 && contains_register (t
->X_add_symbol
)
3933 && contains_register (t
->X_op_symbol
))
3937 regs
= get_register (t
->X_add_symbol
);
3939 regs
|= get_register (t
->X_op_symbol
);
3940 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3946 /* This operand needs a relocation. */
3947 needGOTSymbol
= FALSE
;
3952 if (opcode
->insn_class
== JUMP
)
3953 as_bad (_("Unable to use @plt relocation for insn %s"),
3955 needGOTSymbol
= TRUE
;
3956 reloc
= find_reloc ("plt", opcode
->name
,
3958 operand
->default_reloc
);
3963 needGOTSymbol
= TRUE
;
3964 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3967 if (operand
->flags
& ARC_OPERAND_LIMM
)
3969 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3970 if (arc_opcode_len (opcode
) == 2
3971 || opcode
->insn_class
== JUMP
)
3972 as_bad (_("Unable to use @pcl relocation for insn %s"),
3977 /* This is a relaxed operand which initially was
3978 limm, choose whatever we have defined in the
3980 reloc
= operand
->default_reloc
;
3984 reloc
= find_reloc ("sda", opcode
->name
,
3986 operand
->default_reloc
);
3990 needGOTSymbol
= TRUE
;
3995 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3998 case O_tpoff9
: /*FIXME! Check for the conditionality of
4000 case O_dtpoff9
: /*FIXME! Check for the conditionality of
4002 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4006 /* Just consider the default relocation. */
4007 reloc
= operand
->default_reloc
;
4011 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
4012 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4019 /* sanity checks. */
4020 reloc_howto_type
*reloc_howto
4021 = bfd_reloc_type_lookup (stdoutput
,
4022 (bfd_reloc_code_real_type
) reloc
);
4023 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
4024 if (reloc_howto
->rightshift
)
4025 reloc_bitsize
-= reloc_howto
->rightshift
;
4026 if (reloc_bitsize
!= operand
->bits
)
4028 as_bad (_("invalid relocation %s for field"),
4029 bfd_get_reloc_code_name (reloc
));
4034 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4035 as_fatal (_("too many fixups"));
4037 struct arc_fixup
*fixup
;
4038 fixup
= &insn
->fixups
[insn
->nfixups
++];
4040 fixup
->reloc
= reloc
;
4041 if ((int) reloc
< 0)
4042 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
4045 reloc_howto_type
*reloc_howto
=
4046 bfd_reloc_type_lookup (stdoutput
,
4047 (bfd_reloc_code_real_type
) fixup
->reloc
);
4048 pcrel
= reloc_howto
->pc_relative
;
4050 fixup
->pcrel
= pcrel
;
4051 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
4058 for (i
= 0; i
< nflg
; i
++)
4060 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
4062 /* Check if the instruction has a delay slot. */
4063 if (!strcmp (flg_operand
->name
, "d"))
4064 has_delay_slot
= TRUE
;
4066 /* There is an exceptional case when we cannot insert a flag just as
4067 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4068 relation with the relative address. Unfortunately, some of the
4069 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4070 handled in the normal way.
4072 Flag operands don't have an architecture field, so we can't
4073 directly validate that FLAG_OPERAND is valid for the current
4074 architecture, what we do instead is just validate that we're
4075 assembling for an ARCv2 architecture. */
4076 if ((selected_cpu
.flags
& ARC_OPCODE_ARCV2
)
4077 && (!strcmp (flg_operand
->name
, "t")
4078 || !strcmp (flg_operand
->name
, "nt")))
4080 unsigned bitYoperand
= 0;
4081 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4082 if (!strcmp (flg_operand
->name
, "t"))
4083 if (!strcmp (opcode
->name
, "bbit0")
4084 || !strcmp (opcode
->name
, "bbit1"))
4085 bitYoperand
= arc_NToperand
;
4087 bitYoperand
= arc_Toperand
;
4089 if (!strcmp (opcode
->name
, "bbit0")
4090 || !strcmp (opcode
->name
, "bbit1"))
4091 bitYoperand
= arc_Toperand
;
4093 bitYoperand
= arc_NToperand
;
4095 gas_assert (reloc_exp
!= NULL
);
4096 if (reloc_exp
->X_op
== O_constant
)
4098 /* Check if we have a constant and solved it
4100 offsetT val
= reloc_exp
->X_add_number
;
4101 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4106 struct arc_fixup
*fixup
;
4108 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4109 as_fatal (_("too many fixups"));
4111 fixup
= &insn
->fixups
[insn
->nfixups
++];
4112 fixup
->exp
= *reloc_exp
;
4113 fixup
->reloc
= -bitYoperand
;
4114 fixup
->pcrel
= pcrel
;
4115 fixup
->islong
= FALSE
;
4119 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4120 << flg_operand
->shift
;
4123 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4125 /* Instruction length. */
4126 insn
->len
= arc_opcode_len (opcode
);
4130 /* Update last insn status. */
4131 arc_last_insns
[1] = arc_last_insns
[0];
4132 arc_last_insns
[0].opcode
= opcode
;
4133 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4134 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4136 /* Check if the current instruction is legally used. */
4137 if (arc_last_insns
[1].has_delay_slot
4138 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4139 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4140 arc_last_insns
[1].opcode
->name
,
4141 arc_last_insns
[0].opcode
->name
);
4142 if (arc_last_insns
[1].has_delay_slot
4143 && arc_last_insns
[0].has_limm
)
4144 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4145 arc_last_insns
[1].opcode
->name
,
4146 arc_last_insns
[0].opcode
->name
);
4150 arc_handle_align (fragS
* fragP
)
4152 if ((fragP
)->fr_type
== rs_align_code
)
4154 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4155 valueT count
= ((fragP
)->fr_next
->fr_address
4156 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4158 (fragP
)->fr_var
= 2;
4160 if (count
& 1)/* Padding in the gap till the next 2-byte
4161 boundary with 0s. */
4166 /* Writing nop_s. */
4167 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4171 /* Here we decide which fixups can be adjusted to make them relative
4172 to the beginning of the section instead of the symbol. Basically
4173 we need to make sure that the dynamic relocations are done
4174 correctly, so in some cases we force the original symbol to be
4178 tc_arc_fix_adjustable (fixS
*fixP
)
4181 /* Prevent all adjustments to global symbols. */
4182 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4184 if (S_IS_WEAK (fixP
->fx_addsy
))
4187 /* Adjust_reloc_syms doesn't know about the GOT. */
4188 switch (fixP
->fx_r_type
)
4190 case BFD_RELOC_ARC_GOTPC32
:
4191 case BFD_RELOC_ARC_PLT32
:
4192 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4193 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4194 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4195 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4205 /* Compute the reloc type of an expression EXP. */
4208 arc_check_reloc (expressionS
*exp
,
4209 bfd_reloc_code_real_type
*r_type_p
)
4211 if (*r_type_p
== BFD_RELOC_32
4212 && exp
->X_op
== O_subtract
4213 && exp
->X_op_symbol
!= NULL
4214 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4215 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4219 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4222 arc_cons_fix_new (fragS
*frag
,
4226 bfd_reloc_code_real_type r_type
)
4228 r_type
= BFD_RELOC_UNUSED
;
4233 r_type
= BFD_RELOC_8
;
4237 r_type
= BFD_RELOC_16
;
4241 r_type
= BFD_RELOC_24
;
4245 r_type
= BFD_RELOC_32
;
4246 arc_check_reloc (exp
, &r_type
);
4250 r_type
= BFD_RELOC_64
;
4254 as_bad (_("unsupported BFD relocation size %u"), size
);
4255 r_type
= BFD_RELOC_UNUSED
;
4258 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4261 /* The actual routine that checks the ZOL conditions. */
4264 check_zol (symbolS
*s
)
4266 switch (selected_cpu
.mach
)
4268 case bfd_mach_arc_arcv2
:
4269 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4272 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4273 || arc_last_insns
[1].has_delay_slot
)
4274 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4278 case bfd_mach_arc_arc600
:
4280 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4281 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4284 if (arc_last_insns
[0].has_limm
4285 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4286 as_bad (_("A jump instruction with long immediate detected at the \
4287 end of the ZOL label @%s"), S_GET_NAME (s
));
4290 case bfd_mach_arc_arc700
:
4291 if (arc_last_insns
[0].has_delay_slot
)
4292 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4301 /* If ZOL end check the last two instruction for illegals. */
4303 arc_frob_label (symbolS
* sym
)
4305 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4308 dwarf2_emit_label (sym
);
4311 /* Used because generic relaxation assumes a pc-rel value whilst we
4312 also relax instructions that use an absolute value resolved out of
4313 relative values (if that makes any sense). An example: 'add r1,
4314 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4315 but if they're in the same section we can subtract the section
4316 offset relocation which ends up in a resolved value. So if @.L2 is
4317 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4318 .text + 0x40 = 0x10. */
4320 arc_pcrel_adjust (fragS
*fragP
)
4322 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4323 fragP
->fr_address
, fragP
->fr_fix
,
4324 fragP
->tc_frag_data
.pcrel
? "Y" : "N");
4326 if (!fragP
->tc_frag_data
.pcrel
)
4327 return fragP
->fr_address
+ fragP
->fr_fix
;
4329 /* Take into account the PCL rounding. */
4330 return (fragP
->fr_address
+ fragP
->fr_fix
) & 0x03;
4333 /* Initialize the DWARF-2 unwind information for this procedure. */
4336 tc_arc_frame_initial_instructions (void)
4338 /* Stack pointer is register 28. */
4339 cfi_add_CFA_def_cfa (28, 0);
4343 tc_arc_regname_to_dw2regnum (char *regname
)
4347 sym
= hash_find (arc_reg_hash
, regname
);
4349 return S_GET_VALUE (sym
);
4354 /* Adjust the symbol table. Delete found AUX register symbols. */
4357 arc_adjust_symtab (void)
4361 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4363 /* I've created a symbol during parsing process. Now, remove
4364 the symbol as it is found to be an AUX register. */
4365 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4366 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4369 /* Now do generic ELF adjustments. */
4370 elf_adjust_symtab ();
4374 tokenize_extinsn (extInstruction_t
*einsn
)
4378 unsigned char major_opcode
;
4379 unsigned char sub_opcode
;
4380 unsigned char syntax_class
= 0;
4381 unsigned char syntax_class_modifiers
= 0;
4382 unsigned char suffix_class
= 0;
4387 /* 1st: get instruction name. */
4388 p
= input_line_pointer
;
4389 c
= get_symbol_name (&p
);
4391 insn_name
= xstrdup (p
);
4392 restore_line_pointer (c
);
4394 /* Convert to lower case. */
4395 for (p
= insn_name
; *p
; ++p
)
4398 /* 2nd: get major opcode. */
4399 if (*input_line_pointer
!= ',')
4401 as_bad (_("expected comma after instruction name"));
4402 ignore_rest_of_line ();
4405 input_line_pointer
++;
4406 major_opcode
= get_absolute_expression ();
4408 /* 3rd: get sub-opcode. */
4411 if (*input_line_pointer
!= ',')
4413 as_bad (_("expected comma after major opcode"));
4414 ignore_rest_of_line ();
4417 input_line_pointer
++;
4418 sub_opcode
= get_absolute_expression ();
4420 /* 4th: get suffix class. */
4423 if (*input_line_pointer
!= ',')
4425 as_bad ("expected comma after sub opcode");
4426 ignore_rest_of_line ();
4429 input_line_pointer
++;
4435 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4437 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4438 suffixclass
[i
].len
))
4440 suffix_class
|= suffixclass
[i
].attr_class
;
4441 input_line_pointer
+= suffixclass
[i
].len
;
4446 if (i
== ARRAY_SIZE (suffixclass
))
4448 as_bad ("invalid suffix class");
4449 ignore_rest_of_line ();
4455 if (*input_line_pointer
== '|')
4456 input_line_pointer
++;
4461 /* 5th: get syntax class and syntax class modifiers. */
4462 if (*input_line_pointer
!= ',')
4464 as_bad ("expected comma after suffix class");
4465 ignore_rest_of_line ();
4468 input_line_pointer
++;
4474 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4476 if (!strncmp (syntaxclassmod
[i
].name
,
4478 syntaxclassmod
[i
].len
))
4480 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4481 input_line_pointer
+= syntaxclassmod
[i
].len
;
4486 if (i
== ARRAY_SIZE (syntaxclassmod
))
4488 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4490 if (!strncmp (syntaxclass
[i
].name
,
4492 syntaxclass
[i
].len
))
4494 syntax_class
|= syntaxclass
[i
].attr_class
;
4495 input_line_pointer
+= syntaxclass
[i
].len
;
4500 if (i
== ARRAY_SIZE (syntaxclass
))
4502 as_bad ("missing syntax class");
4503 ignore_rest_of_line ();
4510 if (*input_line_pointer
== '|')
4511 input_line_pointer
++;
4516 demand_empty_rest_of_line ();
4518 einsn
->name
= insn_name
;
4519 einsn
->major
= major_opcode
;
4520 einsn
->minor
= sub_opcode
;
4521 einsn
->syntax
= syntax_class
;
4522 einsn
->modsyn
= syntax_class_modifiers
;
4523 einsn
->suffix
= suffix_class
;
4524 einsn
->flags
= syntax_class
4525 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4528 /* Generate an extension section. */
4531 arc_set_ext_seg (void)
4533 if (!arcext_section
)
4535 arcext_section
= subseg_new (".arcextmap", 0);
4536 bfd_set_section_flags (stdoutput
, arcext_section
,
4537 SEC_READONLY
| SEC_HAS_CONTENTS
);
4540 subseg_set (arcext_section
, 0);
4544 /* Create an extension instruction description in the arc extension
4545 section of the output file.
4546 The structure for an instruction is like this:
4547 [0]: Length of the record.
4548 [1]: Type of the record.
4552 [4]: Syntax (flags).
4553 [5]+ Name instruction.
4555 The sequence is terminated by an empty entry. */
4558 create_extinst_section (extInstruction_t
*einsn
)
4561 segT old_sec
= now_seg
;
4562 int old_subsec
= now_subseg
;
4564 int name_len
= strlen (einsn
->name
);
4569 *p
= 5 + name_len
+ 1;
4571 *p
= EXT_INSTRUCTION
;
4578 p
= frag_more (name_len
+ 1);
4579 strcpy (p
, einsn
->name
);
4581 subseg_set (old_sec
, old_subsec
);
4584 /* Handler .extinstruction pseudo-op. */
4587 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4589 extInstruction_t einsn
;
4590 struct arc_opcode
*arc_ext_opcodes
;
4591 const char *errmsg
= NULL
;
4592 unsigned char moplow
, mophigh
;
4594 memset (&einsn
, 0, sizeof (einsn
));
4595 tokenize_extinsn (&einsn
);
4597 /* Check if the name is already used. */
4598 if (arc_find_opcode (einsn
.name
))
4599 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4601 /* Check the opcode ranges. */
4603 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4604 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4606 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4607 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4609 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4610 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4611 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4613 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4615 case ARC_SYNTAX_3OP
:
4616 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4617 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4619 case ARC_SYNTAX_2OP
:
4620 case ARC_SYNTAX_1OP
:
4621 case ARC_SYNTAX_NOP
:
4622 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4623 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4629 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4630 if (arc_ext_opcodes
== NULL
)
4633 as_fatal ("%s", errmsg
);
4635 as_fatal (_("Couldn't generate extension instruction opcodes"));
4638 as_warn ("%s", errmsg
);
4640 /* Insert the extension instruction. */
4641 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4643 create_extinst_section (&einsn
);
4647 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4653 int number
, imode
= 0;
4654 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4655 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4656 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4658 /* 1st: get register name. */
4660 p
= input_line_pointer
;
4661 c
= get_symbol_name (&p
);
4664 restore_line_pointer (c
);
4666 /* 2nd: get register number. */
4669 if (*input_line_pointer
!= ',')
4671 as_bad (_("expected comma after name"));
4672 ignore_rest_of_line ();
4676 input_line_pointer
++;
4677 number
= get_absolute_expression ();
4680 && (opertype
!= EXT_AUX_REGISTER
))
4682 as_bad (_("%s second argument cannot be a negative number %d"),
4683 isCore_p
? "extCoreRegister's" : "extCondCode's",
4685 ignore_rest_of_line ();
4692 /* 3rd: get register mode. */
4695 if (*input_line_pointer
!= ',')
4697 as_bad (_("expected comma after register number"));
4698 ignore_rest_of_line ();
4703 input_line_pointer
++;
4704 mode
= input_line_pointer
;
4706 if (!strncmp (mode
, "r|w", 3))
4709 input_line_pointer
+= 3;
4711 else if (!strncmp (mode
, "r", 1))
4713 imode
= ARC_REGISTER_READONLY
;
4714 input_line_pointer
+= 1;
4716 else if (strncmp (mode
, "w", 1))
4718 as_bad (_("invalid mode"));
4719 ignore_rest_of_line ();
4725 imode
= ARC_REGISTER_WRITEONLY
;
4726 input_line_pointer
+= 1;
4732 /* 4th: get core register shortcut. */
4734 if (*input_line_pointer
!= ',')
4736 as_bad (_("expected comma after register mode"));
4737 ignore_rest_of_line ();
4742 input_line_pointer
++;
4744 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4746 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4747 input_line_pointer
+= 15;
4749 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4751 as_bad (_("shortcut designator invalid"));
4752 ignore_rest_of_line ();
4758 input_line_pointer
+= 12;
4761 demand_empty_rest_of_line ();
4764 ereg
->number
= number
;
4765 ereg
->imode
= imode
;
4769 /* Create an extension register/condition description in the arc
4770 extension section of the output file.
4772 The structure for an instruction is like this:
4773 [0]: Length of the record.
4774 [1]: Type of the record.
4776 For core regs and condition codes:
4780 For auxiliary registers:
4784 The sequence is terminated by an empty entry. */
4787 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4789 segT old_sec
= now_seg
;
4790 int old_subsec
= now_subseg
;
4792 int name_len
= strlen (ereg
->name
);
4799 case EXT_CORE_REGISTER
:
4801 *p
= 3 + name_len
+ 1;
4807 case EXT_AUX_REGISTER
:
4809 *p
= 6 + name_len
+ 1;
4811 *p
= EXT_AUX_REGISTER
;
4813 *p
= (ereg
->number
>> 24) & 0xff;
4815 *p
= (ereg
->number
>> 16) & 0xff;
4817 *p
= (ereg
->number
>> 8) & 0xff;
4819 *p
= (ereg
->number
) & 0xff;
4825 p
= frag_more (name_len
+ 1);
4826 strcpy (p
, ereg
->name
);
4828 subseg_set (old_sec
, old_subsec
);
4831 /* Handler .extCoreRegister pseudo-op. */
4834 arc_extcorereg (int opertype
)
4837 struct arc_aux_reg
*auxr
;
4839 struct arc_flag_operand
*ccode
;
4841 memset (&ereg
, 0, sizeof (ereg
));
4842 if (!tokenize_extregister (&ereg
, opertype
))
4847 case EXT_CORE_REGISTER
:
4848 /* Core register. */
4849 if (ereg
.number
> 60)
4850 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4852 declare_register (ereg
.name
, ereg
.number
);
4854 case EXT_AUX_REGISTER
:
4855 /* Auxiliary register. */
4856 auxr
= XNEW (struct arc_aux_reg
);
4857 auxr
->name
= ereg
.name
;
4858 auxr
->cpu
= selected_cpu
.flags
;
4859 auxr
->subclass
= NONE
;
4860 auxr
->address
= ereg
.number
;
4861 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4863 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4864 auxr
->name
, retval
);
4867 /* Condition code. */
4868 if (ereg
.number
> 31)
4869 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4871 ext_condcode
.size
++;
4872 ext_condcode
.arc_ext_condcode
=
4873 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4874 ext_condcode
.size
+ 1);
4875 if (ext_condcode
.arc_ext_condcode
== NULL
)
4876 as_fatal (_("Virtual memory exhausted"));
4878 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4879 ccode
->name
= ereg
.name
;
4880 ccode
->code
= ereg
.number
;
4883 ccode
->favail
= 0; /* not used. */
4885 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4888 as_bad (_("Unknown extension"));
4891 create_extcore_section (&ereg
, opertype
);
4894 /* Parse a .arc_attribute directive. */
4897 arc_attribute (int ignored ATTRIBUTE_UNUSED
)
4899 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4901 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4902 attributes_set_explicitly
[tag
] = TRUE
;
4905 /* Set an attribute if it has not already been set by the user. */
4908 arc_set_attribute_int (int tag
, int value
)
4911 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4912 || !attributes_set_explicitly
[tag
])
4913 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
4917 arc_set_attribute_string (int tag
, const char *value
)
4920 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4921 || !attributes_set_explicitly
[tag
])
4922 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
4925 /* Allocate and concatenate two strings. s1 can be NULL but not
4926 s2. s1 pointer is freed at end of this procedure. */
4929 arc_stralloc (char * s1
, const char * s2
)
4935 len
= strlen (s1
) + 1;
4937 /* Only s1 can be null. */
4939 len
+= strlen (s2
) + 1;
4941 p
= (char *) xmalloc (len
);
4943 as_fatal (_("Virtual memory exhausted"));
4958 /* Set the public ARC object attributes. */
4961 arc_set_public_attributes (void)
4967 /* Tag_ARC_CPU_name. */
4968 arc_set_attribute_string (Tag_ARC_CPU_name
, selected_cpu
.name
);
4970 /* Tag_ARC_CPU_base. */
4971 switch (selected_cpu
.eflags
& EF_ARC_MACH_MSK
)
4973 case E_ARC_MACH_ARC600
:
4974 case E_ARC_MACH_ARC601
:
4975 base
= TAG_CPU_ARC6xx
;
4977 case E_ARC_MACH_ARC700
:
4978 base
= TAG_CPU_ARC7xx
;
4980 case EF_ARC_CPU_ARCV2EM
:
4981 base
= TAG_CPU_ARCEM
;
4983 case EF_ARC_CPU_ARCV2HS
:
4984 base
= TAG_CPU_ARCHS
;
4990 if (attributes_set_explicitly
[Tag_ARC_CPU_base
]
4991 && (base
!= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
4993 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
4994 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_CPU_base
, base
);
4996 /* Tag_ARC_ABI_osver. */
4997 if (attributes_set_explicitly
[Tag_ARC_ABI_osver
])
4999 int val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5002 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_OSABI_MSK
)
5003 | (val
& 0x0f << 8));
5007 arc_set_attribute_int (Tag_ARC_ABI_osver
, E_ARC_OSABI_CURRENT
>> 8);
5010 /* Tag_ARC_ISA_config. */
5011 arc_check_feature();
5013 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
5014 if (selected_cpu
.features
& feature_list
[i
].feature
)
5015 s
= arc_stralloc (s
, feature_list
[i
].attr
);
5018 arc_set_attribute_string (Tag_ARC_ISA_config
, s
);
5020 /* Tag_ARC_ISA_mpy_option. */
5021 arc_set_attribute_int (Tag_ARC_ISA_mpy_option
, mpy_option
);
5023 /* Tag_ARC_ABI_pic. */
5024 arc_set_attribute_int (Tag_ARC_ABI_pic
, pic_option
);
5026 /* Tag_ARC_ABI_sda. */
5027 arc_set_attribute_int (Tag_ARC_ABI_sda
, sda_option
);
5029 /* Tag_ARC_ABI_tls. */
5030 arc_set_attribute_int (Tag_ARC_ABI_tls
, tls_option
);
5032 /* Tag_ARC_ATR_version. */
5033 arc_set_attribute_int (Tag_ARC_ATR_version
, 1);
5035 /* Tag_ARC_ABI_rf16. */
5036 if (attributes_set_explicitly
[Tag_ARC_ABI_rf16
]
5037 && bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5041 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5043 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_ABI_rf16
, 0);
5047 /* Add the default contents for the .ARC.attributes section. */
5052 arc_set_public_attributes ();
5054 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
5055 as_fatal (_("could not set architecture and machine"));
5057 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
5060 void arc_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
5062 ARC_GET_FLAG (dest
) = ARC_GET_FLAG (src
);
5065 int arc_convert_symbolic_attribute (const char *name
)
5074 #define T(tag) {#tag, tag}
5075 T (Tag_ARC_PCS_config
),
5076 T (Tag_ARC_CPU_base
),
5077 T (Tag_ARC_CPU_variation
),
5078 T (Tag_ARC_CPU_name
),
5079 T (Tag_ARC_ABI_rf16
),
5080 T (Tag_ARC_ABI_osver
),
5081 T (Tag_ARC_ABI_sda
),
5082 T (Tag_ARC_ABI_pic
),
5083 T (Tag_ARC_ABI_tls
),
5084 T (Tag_ARC_ABI_enumsize
),
5085 T (Tag_ARC_ABI_exceptions
),
5086 T (Tag_ARC_ABI_double_size
),
5087 T (Tag_ARC_ISA_config
),
5088 T (Tag_ARC_ISA_apex
),
5089 T (Tag_ARC_ISA_mpy_option
),
5090 T (Tag_ARC_ATR_version
)
5098 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
5099 if (streq (name
, attribute_table
[i
].name
))
5100 return attribute_table
[i
].tag
;
5106 eval: (c-set-style "gnu")