1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
49 (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 /* Enum used to enumerate the relaxable ins operands. */
59 REGISTER_S
, /* Register for short instruction(s). */
60 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
61 REGISTER_DUP
, /* Duplication of previous operand of type register. */
95 #define regno(x) ((x) & 0x3F)
96 #define is_ir_num(x) (((x) & ~0x3F) == 0)
97 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
98 #define is_spfp_p(op) (((sc) == SPX))
99 #define is_dpfp_p(op) (((sc) == DPX))
100 #define is_fpuda_p(op) (((sc) == DPA))
101 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH || (op)->insn_class == JUMP))
102 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
103 #define is_nps400_p(op) (((sc) == NPS400))
105 /* Generic assembler global variables which must be defined by all
108 /* Characters which always start a comment. */
109 const char comment_chars
[] = "#;";
111 /* Characters which start a comment at the beginning of a line. */
112 const char line_comment_chars
[] = "#";
114 /* Characters which may be used to separate multiple commands on a
116 const char line_separator_chars
[] = "`";
118 /* Characters which are used to indicate an exponent in a floating
120 const char EXP_CHARS
[] = "eE";
122 /* Chars that mean this number is a floating point constant
123 As in 0f12.456 or 0d1.2345e12. */
124 const char FLT_CHARS
[] = "rRsSfFdD";
127 extern int target_big_endian
;
128 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
129 static int byte_order
= DEFAULT_BYTE_ORDER
;
131 /* Arc extension section. */
132 static segT arcext_section
;
134 /* By default relaxation is disabled. */
135 static int relaxation_state
= 0;
137 extern int arc_get_mach (char *);
139 /* Forward declarations. */
140 static void arc_lcomm (int);
141 static void arc_option (int);
142 static void arc_extra_reloc (int);
143 static void arc_extinsn (int);
144 static void arc_extcorereg (int);
146 const pseudo_typeS md_pseudo_table
[] =
148 /* Make sure that .word is 32 bits. */
151 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
152 { "lcomm", arc_lcomm
, 0 },
153 { "lcommon", arc_lcomm
, 0 },
154 { "cpu", arc_option
, 0 },
156 { "extinstruction", arc_extinsn
, 0 },
157 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
158 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
159 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
161 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
162 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
167 const char *md_shortopts
= "";
171 OPTION_EB
= OPTION_MD_BASE
,
189 /* The following options are deprecated and provided here only for
190 compatibility reasons. */
213 struct option md_longopts
[] =
215 { "EB", no_argument
, NULL
, OPTION_EB
},
216 { "EL", no_argument
, NULL
, OPTION_EL
},
217 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
218 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
219 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
220 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
221 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
222 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
223 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
224 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
225 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
226 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
227 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
229 /* Floating point options */
230 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
231 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
232 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
233 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
234 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
235 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
236 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
237 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
238 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
239 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
240 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
242 /* The following options are deprecated and provided here only for
243 compatibility reasons. */
244 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
245 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
246 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
247 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
248 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
249 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
250 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
251 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
252 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
253 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
254 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
255 { "mea", no_argument
, NULL
, OPTION_EA
},
256 { "mEA", no_argument
, NULL
, OPTION_EA
},
257 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
258 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
259 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
260 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
261 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
262 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
263 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
264 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
265 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
266 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
267 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
268 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
269 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
270 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
271 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
273 { NULL
, no_argument
, NULL
, 0 }
276 size_t md_longopts_size
= sizeof (md_longopts
);
278 /* Local data and data types. */
280 /* Used since new relocation types are introduced in this
281 file (DUMMY_RELOC_LITUSE_*). */
282 typedef int extended_bfd_reloc_code_real_type
;
288 extended_bfd_reloc_code_real_type reloc
;
290 /* index into arc_operands. */
291 unsigned int opindex
;
293 /* PC-relative, used by internals fixups. */
296 /* TRUE if this fixup is for LIMM operand. */
304 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
306 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
308 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
310 bfd_boolean relax
; /* Boolean value: TRUE if needs
314 /* Structure to hold any last two instructions. */
315 static struct arc_last_insn
317 /* Saved instruction opcode. */
318 const struct arc_opcode
*opcode
;
320 /* Boolean value: TRUE if current insn is short. */
321 bfd_boolean has_limm
;
323 /* Boolean value: TRUE if current insn has delay slot. */
324 bfd_boolean has_delay_slot
;
327 /* Extension instruction suffix classes. */
335 static const attributes_t suffixclass
[] =
337 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
338 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
339 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
342 /* Extension instruction syntax classes. */
343 static const attributes_t syntaxclass
[] =
345 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
346 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
347 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
348 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
351 /* Extension instruction syntax classes modifiers. */
352 static const attributes_t syntaxclassmod
[] =
354 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
355 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
358 /* Extension register type. */
366 /* A structure to hold the additional conditional codes. */
369 struct arc_flag_operand
*arc_ext_condcode
;
371 } ext_condcode
= { NULL
, 0 };
373 /* Structure to hold an entry in ARC_OPCODE_HASH. */
374 struct arc_opcode_hash_entry
376 /* The number of pointers in the OPCODE list. */
379 /* Points to a list of opcode pointers. */
380 const struct arc_opcode
**opcode
;
383 /* Structure used for iterating through an arc_opcode_hash_entry. */
384 struct arc_opcode_hash_entry_iterator
386 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
389 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
390 returned by this iterator. */
391 const struct arc_opcode
*opcode
;
394 /* Forward declaration. */
395 static void assemble_insn
396 (const struct arc_opcode
*, const expressionS
*, int,
397 const struct arc_flags
*, int, struct arc_insn
*);
399 /* The cpu for which we are generating code. */
400 static unsigned arc_target
;
401 static const char *arc_target_name
;
402 static unsigned arc_features
;
404 /* The default architecture. */
405 static int arc_mach_type
;
407 /* TRUE if the cpu type has been explicitly specified. */
408 static bfd_boolean mach_type_specified_p
= FALSE
;
410 /* The hash table of instruction opcodes. */
411 static struct hash_control
*arc_opcode_hash
;
413 /* The hash table of register symbols. */
414 static struct hash_control
*arc_reg_hash
;
416 /* The hash table of aux register symbols. */
417 static struct hash_control
*arc_aux_hash
;
419 /* A table of CPU names and opcode sets. */
420 static const struct cpu_type
430 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
431 E_ARC_MACH_ARC600
, 0x00},
432 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
433 E_ARC_MACH_ARC700
, 0x00},
434 { "nps400", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
435 E_ARC_MACH_ARC700
, ARC_NPS400
},
436 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
437 EF_ARC_CPU_ARCV2EM
, 0x00},
438 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
439 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
443 /* Used by the arc_reloc_op table. Order is important. */
444 #define O_gotoff O_md1 /* @gotoff relocation. */
445 #define O_gotpc O_md2 /* @gotpc relocation. */
446 #define O_plt O_md3 /* @plt relocation. */
447 #define O_sda O_md4 /* @sda relocation. */
448 #define O_pcl O_md5 /* @pcl relocation. */
449 #define O_tlsgd O_md6 /* @tlsgd relocation. */
450 #define O_tlsie O_md7 /* @tlsie relocation. */
451 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
452 #define O_tpoff O_md9 /* @tpoff relocation. */
453 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
454 #define O_dtpoff O_md11 /* @dtpoff relocation. */
455 #define O_last O_dtpoff
457 /* Used to define a bracket as operand in tokens. */
458 #define O_bracket O_md32
460 /* Dummy relocation, to be sorted out. */
461 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
463 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
465 /* A table to map the spelling of a relocation operand into an appropriate
466 bfd_reloc_code_real_type type. The table is assumed to be ordered such
467 that op-O_literal indexes into it. */
468 #define ARC_RELOC_TABLE(op) \
469 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
471 : (int) (op) - (int) O_gotoff) ])
473 #define DEF(NAME, RELOC, REQ) \
474 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
476 static const struct arc_reloc_op_tag
478 /* String to lookup. */
480 /* Size of the string. */
482 /* Which operator to use. */
484 extended_bfd_reloc_code_real_type reloc
;
485 /* Allows complex relocation expression like identifier@reloc +
487 unsigned int complex_expr
: 1;
491 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
492 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
493 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
494 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
495 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
496 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
497 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
498 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
499 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
500 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
501 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 0),
504 static const int arc_num_reloc_op
505 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
507 /* Structure for relaxable instruction that have to be swapped with a
508 smaller alternative instruction. */
509 struct arc_relaxable_ins
511 /* Mnemonic that should be checked. */
512 const char *mnemonic_r
;
514 /* Operands that should be checked.
515 Indexes of operands from operand array. */
516 enum rlx_operand_type operands
[6];
518 /* Flags that should be checked. */
519 unsigned flag_classes
[5];
521 /* Mnemonic (smaller) alternative to be used later for relaxation. */
522 const char *mnemonic_alt
;
524 /* Index of operand that generic relaxation has to check. */
527 /* Base subtype index used. */
528 enum arc_rlx_types subtype
;
531 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
532 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
533 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
537 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
538 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
539 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
544 /* ARC relaxation table. */
545 const relax_typeS md_relax_table
[] =
552 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL
),
553 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
557 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B
),
558 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
563 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6
),
564 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM
),
565 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
567 /* LD_S a, [b, u7] ->
568 LD<zz><.x><.aa><.di> a, [b, s9] ->
569 LD<zz><.x><.aa><.di> a, [b, limm] */
570 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9
),
571 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM
),
572 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE
),
577 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12
),
578 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM
),
579 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
583 SUB<.f> a, b, limm. */
584 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6
),
585 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM
),
586 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
588 /* MPY<.f> a, b, u6 ->
589 MPY<.f> a, b, limm. */
590 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM
),
591 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
593 /* MOV<.f><.cc> b, u6 ->
594 MOV<.f><.cc> b, limm. */
595 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM
),
596 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
598 /* ADD<.f><.cc> b, b, u6 ->
599 ADD<.f><.cc> b, b, limm. */
600 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM
),
601 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
604 /* Order of this table's entries matters! */
605 const struct arc_relaxable_ins arc_relaxable_insns
[] =
607 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
608 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
609 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
610 2, ARC_RLX_ADD_RRU6
},
611 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
613 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
615 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
616 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
617 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
618 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
619 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
620 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
621 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
622 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
624 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
626 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
630 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
632 /* Flags to set in the elf header. */
633 static flagword arc_eflag
= 0x00;
635 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
636 symbolS
* GOT_symbol
= 0;
638 /* Set to TRUE when we assemble instructions. */
639 static bfd_boolean assembling_insn
= FALSE
;
641 /* Functions implementation. */
643 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
644 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
645 are no matching entries in ARC_OPCODE_HASH. */
647 static const struct arc_opcode_hash_entry
*
648 arc_find_opcode (const char *name
)
650 const struct arc_opcode_hash_entry
*entry
;
652 entry
= hash_find (arc_opcode_hash
, name
);
656 /* Initialise the iterator ITER. */
659 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
665 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
666 calls to this function. Return NULL when all ARC_OPCODE entries have
669 static const struct arc_opcode
*
670 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
671 struct arc_opcode_hash_entry_iterator
*iter
)
673 if (iter
->opcode
== NULL
&& iter
->index
== 0)
675 gas_assert (entry
->count
> 0);
676 iter
->opcode
= entry
->opcode
[iter
->index
];
678 else if (iter
->opcode
!= NULL
)
680 const char *old_name
= iter
->opcode
->name
;
683 if (iter
->opcode
->name
== NULL
684 || strcmp (old_name
, iter
->opcode
->name
) != 0)
687 if (iter
->index
== entry
->count
)
690 iter
->opcode
= entry
->opcode
[iter
->index
];
697 /* Insert an opcode into opcode hash structure. */
700 arc_insert_opcode (const struct arc_opcode
*opcode
)
702 const char *name
, *retval
;
703 struct arc_opcode_hash_entry
*entry
;
706 entry
= hash_find (arc_opcode_hash
, name
);
709 entry
= XNEW (struct arc_opcode_hash_entry
);
711 entry
->opcode
= NULL
;
713 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
715 as_fatal (_("internal error: can't hash opcode '%s': %s"),
719 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
722 if (entry
->opcode
== NULL
)
723 as_fatal (_("Virtual memory exhausted"));
725 entry
->opcode
[entry
->count
] = opcode
;
730 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
731 is encoded as 'middle-endian' for a little-endian target. FIXME!
732 this function is used for regular 4 byte instructions as well. */
735 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
739 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
740 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
744 md_number_to_chars (buf
, val
, n
);
748 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
749 the relevant static global variables. */
752 arc_select_cpu (const char *arg
)
757 for (i
= 0; cpu_types
[i
].name
; ++i
)
759 if (!strcasecmp (cpu_types
[i
].name
, arg
))
761 arc_target
= cpu_types
[i
].flags
;
762 arc_target_name
= cpu_types
[i
].name
;
763 arc_features
= cpu_types
[i
].features
;
764 arc_mach_type
= cpu_types
[i
].mach
;
765 cpu_flags
= cpu_types
[i
].eflags
;
770 if (!cpu_types
[i
].name
)
771 as_fatal (_("unknown architecture: %s\n"), arg
);
772 gas_assert (cpu_flags
!= 0);
773 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
776 /* Here ends all the ARCompact extension instruction assembling
780 arc_extra_reloc (int r_type
)
783 symbolS
*sym
, *lab
= NULL
;
785 if (*input_line_pointer
== '@')
786 input_line_pointer
++;
787 c
= get_symbol_name (&sym_name
);
788 sym
= symbol_find_or_make (sym_name
);
789 restore_line_pointer (c
);
790 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
792 ++input_line_pointer
;
794 c
= get_symbol_name (&lab_name
);
795 lab
= symbol_find_or_make (lab_name
);
796 restore_line_pointer (c
);
799 /* These relocations exist as a mechanism for the compiler to tell the
800 linker how to patch the code if the tls model is optimised. However,
801 the relocation itself does not require any space within the assembler
802 fragment, and so we pass a size of 0.
804 The lines that generate these relocations look like this:
806 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
808 The '.tls_gd_ld @.tdata' is processed first and generates the
809 additional relocation, while the 'bl __tls_get_addr@plt' is processed
810 second and generates the additional branch.
812 It is possible that the additional relocation generated by the
813 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
814 while the 'bl __tls_get_addr@plt' will be generated as the first thing
815 in the next fragment. This will be fine; both relocations will still
816 appear to be at the same address in the generated object file.
817 However, this only works as the additional relocation is generated
818 with size of 0 bytes. */
820 = fix_new (frag_now
, /* Which frag? */
821 frag_now_fix (), /* Where in that frag? */
822 0, /* size: 1, 2, or 4 usually. */
823 sym
, /* X_add_symbol. */
824 0, /* X_add_number. */
825 FALSE
, /* TRUE if PC-relative relocation. */
826 r_type
/* Relocation type. */);
827 fixP
->fx_subsy
= lab
;
831 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
832 symbolS
*symbolP
, addressT size
)
837 if (*input_line_pointer
== ',')
839 align
= parse_align (1);
841 if (align
== (addressT
) -1)
856 bss_alloc (symbolP
, size
, align
);
857 S_CLEAR_EXTERNAL (symbolP
);
863 arc_lcomm (int ignore
)
865 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
868 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
871 /* Select the cpu we're assembling for. */
874 arc_option (int ignore ATTRIBUTE_UNUSED
)
880 c
= get_symbol_name (&cpu
);
881 mach
= arc_get_mach (cpu
);
886 if (!mach_type_specified_p
)
888 if ((!strcmp ("ARC600", cpu
))
889 || (!strcmp ("ARC601", cpu
))
890 || (!strcmp ("A6", cpu
)))
892 md_parse_option (OPTION_MCPU
, "arc600");
894 else if ((!strcmp ("ARC700", cpu
))
895 || (!strcmp ("A7", cpu
)))
897 md_parse_option (OPTION_MCPU
, "arc700");
899 else if (!strcmp ("EM", cpu
))
901 md_parse_option (OPTION_MCPU
, "arcem");
903 else if (!strcmp ("HS", cpu
))
905 md_parse_option (OPTION_MCPU
, "archs");
907 else if (!strcmp ("NPS400", cpu
))
909 md_parse_option (OPTION_MCPU
, "nps400");
912 as_fatal (_("could not find the architecture"));
914 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
915 as_fatal (_("could not set architecture and machine"));
917 /* Set elf header flags. */
918 bfd_set_private_flags (stdoutput
, arc_eflag
);
921 if (arc_mach_type
!= mach
)
922 as_warn (_("Command-line value overrides \".cpu\" directive"));
924 restore_line_pointer (c
);
925 demand_empty_rest_of_line ();
929 restore_line_pointer (c
);
930 as_bad (_("invalid identifier for \".cpu\""));
931 ignore_rest_of_line ();
934 /* Smartly print an expression. */
937 debug_exp (expressionS
*t
)
939 const char *name ATTRIBUTE_UNUSED
;
940 const char *namemd ATTRIBUTE_UNUSED
;
942 pr_debug ("debug_exp: ");
946 default: name
= "unknown"; break;
947 case O_illegal
: name
= "O_illegal"; break;
948 case O_absent
: name
= "O_absent"; break;
949 case O_constant
: name
= "O_constant"; break;
950 case O_symbol
: name
= "O_symbol"; break;
951 case O_symbol_rva
: name
= "O_symbol_rva"; break;
952 case O_register
: name
= "O_register"; break;
953 case O_big
: name
= "O_big"; break;
954 case O_uminus
: name
= "O_uminus"; break;
955 case O_bit_not
: name
= "O_bit_not"; break;
956 case O_logical_not
: name
= "O_logical_not"; break;
957 case O_multiply
: name
= "O_multiply"; break;
958 case O_divide
: name
= "O_divide"; break;
959 case O_modulus
: name
= "O_modulus"; break;
960 case O_left_shift
: name
= "O_left_shift"; break;
961 case O_right_shift
: name
= "O_right_shift"; break;
962 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
963 case O_bit_or_not
: name
= "O_bit_or_not"; break;
964 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
965 case O_bit_and
: name
= "O_bit_and"; break;
966 case O_add
: name
= "O_add"; break;
967 case O_subtract
: name
= "O_subtract"; break;
968 case O_eq
: name
= "O_eq"; break;
969 case O_ne
: name
= "O_ne"; break;
970 case O_lt
: name
= "O_lt"; break;
971 case O_le
: name
= "O_le"; break;
972 case O_ge
: name
= "O_ge"; break;
973 case O_gt
: name
= "O_gt"; break;
974 case O_logical_and
: name
= "O_logical_and"; break;
975 case O_logical_or
: name
= "O_logical_or"; break;
976 case O_index
: name
= "O_index"; break;
977 case O_bracket
: name
= "O_bracket"; break;
982 default: namemd
= "unknown"; break;
983 case O_gotoff
: namemd
= "O_gotoff"; break;
984 case O_gotpc
: namemd
= "O_gotpc"; break;
985 case O_plt
: namemd
= "O_plt"; break;
986 case O_sda
: namemd
= "O_sda"; break;
987 case O_pcl
: namemd
= "O_pcl"; break;
988 case O_tlsgd
: namemd
= "O_tlsgd"; break;
989 case O_tlsie
: namemd
= "O_tlsie"; break;
990 case O_tpoff9
: namemd
= "O_tpoff9"; break;
991 case O_tpoff
: namemd
= "O_tpoff"; break;
992 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
993 case O_dtpoff
: namemd
= "O_dtpoff"; break;
996 pr_debug ("%s (%s, %s, %d, %s)", name
,
997 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
998 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
999 (int) t
->X_add_number
,
1000 (t
->X_md
) ? namemd
: "--");
1005 /* Parse the arguments to an opcode. */
1008 tokenize_arguments (char *str
,
1012 char *old_input_line_pointer
;
1013 bfd_boolean saw_comma
= FALSE
;
1014 bfd_boolean saw_arg
= FALSE
;
1019 const struct arc_reloc_op_tag
*r
;
1021 char *reloc_name
, c
;
1023 memset (tok
, 0, sizeof (*tok
) * ntok
);
1025 /* Save and restore input_line_pointer around this function. */
1026 old_input_line_pointer
= input_line_pointer
;
1027 input_line_pointer
= str
;
1029 while (*input_line_pointer
)
1032 switch (*input_line_pointer
)
1038 input_line_pointer
++;
1039 if (saw_comma
|| !saw_arg
)
1046 ++input_line_pointer
;
1048 if (!saw_arg
|| num_args
== ntok
)
1050 tok
->X_op
= O_bracket
;
1057 input_line_pointer
++;
1058 if (brk_lvl
|| num_args
== ntok
)
1061 tok
->X_op
= O_bracket
;
1067 /* We have labels, function names and relocations, all
1068 starting with @ symbol. Sort them out. */
1069 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1073 tok
->X_op
= O_symbol
;
1074 tok
->X_md
= O_absent
;
1076 if (*input_line_pointer
!= '@')
1077 goto normalsymbol
; /* This is not a relocation. */
1081 /* A relocation opernad has the following form
1082 @identifier@relocation_type. The identifier is already
1084 if (tok
->X_op
!= O_symbol
)
1086 as_bad (_("No valid label relocation operand"));
1090 /* Parse @relocation_type. */
1091 input_line_pointer
++;
1092 c
= get_symbol_name (&reloc_name
);
1093 len
= input_line_pointer
- reloc_name
;
1096 as_bad (_("No relocation operand"));
1100 /* Go through known relocation and try to find a match. */
1101 r
= &arc_reloc_op
[0];
1102 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1103 if (len
== r
->length
1104 && memcmp (reloc_name
, r
->name
, len
) == 0)
1108 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1112 *input_line_pointer
= c
;
1113 SKIP_WHITESPACE_AFTER_NAME ();
1114 /* Extra check for TLS: base. */
1115 if (*input_line_pointer
== '@')
1118 if (tok
->X_op_symbol
!= NULL
1119 || tok
->X_op
!= O_symbol
)
1121 as_bad (_("Unable to parse TLS base: %s"),
1122 input_line_pointer
);
1125 input_line_pointer
++;
1127 c
= get_symbol_name (&sym_name
);
1128 base
= symbol_find_or_make (sym_name
);
1129 tok
->X_op
= O_subtract
;
1130 tok
->X_op_symbol
= base
;
1131 restore_line_pointer (c
);
1132 tmpE
.X_add_number
= 0;
1134 else if ((*input_line_pointer
!= '+')
1135 && (*input_line_pointer
!= '-'))
1137 tmpE
.X_add_number
= 0;
1141 /* Parse the constant of a complex relocation expression
1142 like @identifier@reloc +/- const. */
1143 if (! r
->complex_expr
)
1145 as_bad (_("@%s is not a complex relocation."), r
->name
);
1149 if (tmpE
.X_op
!= O_constant
)
1151 as_bad (_("Bad expression: @%s + %s."),
1152 r
->name
, input_line_pointer
);
1158 tok
->X_add_number
= tmpE
.X_add_number
;
1169 /* Can be a register. */
1170 ++input_line_pointer
;
1174 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1177 tok
->X_op
= O_absent
;
1178 tok
->X_md
= O_absent
;
1181 /* Legacy: There are cases when we have
1182 identifier@relocation_type, if it is the case parse the
1183 relocation type as well. */
1184 if (*input_line_pointer
== '@')
1190 if (tok
->X_op
== O_illegal
1191 || tok
->X_op
== O_absent
1192 || num_args
== ntok
)
1204 if (saw_comma
|| brk_lvl
)
1206 input_line_pointer
= old_input_line_pointer
;
1212 as_bad (_("Brackets in operand field incorrect"));
1214 as_bad (_("extra comma"));
1216 as_bad (_("missing argument"));
1218 as_bad (_("missing comma or colon"));
1219 input_line_pointer
= old_input_line_pointer
;
1223 /* Parse the flags to a structure. */
1226 tokenize_flags (const char *str
,
1227 struct arc_flags flags
[],
1230 char *old_input_line_pointer
;
1231 bfd_boolean saw_flg
= FALSE
;
1232 bfd_boolean saw_dot
= FALSE
;
1236 memset (flags
, 0, sizeof (*flags
) * nflg
);
1238 /* Save and restore input_line_pointer around this function. */
1239 old_input_line_pointer
= input_line_pointer
;
1240 input_line_pointer
= (char *) str
;
1242 while (*input_line_pointer
)
1244 switch (*input_line_pointer
)
1251 input_line_pointer
++;
1259 if (saw_flg
&& !saw_dot
)
1262 if (num_flags
>= nflg
)
1265 flgnamelen
= strspn (input_line_pointer
,
1266 "abcdefghijklmnopqrstuvwxyz0123456789");
1267 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1270 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1272 input_line_pointer
+= flgnamelen
;
1282 input_line_pointer
= old_input_line_pointer
;
1287 as_bad (_("extra dot"));
1289 as_bad (_("unrecognized flag"));
1291 as_bad (_("failed to parse flags"));
1292 input_line_pointer
= old_input_line_pointer
;
1296 /* Apply the fixups in order. */
1299 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1303 for (i
= 0; i
< insn
->nfixups
; i
++)
1305 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1306 int size
, pcrel
, offset
= 0;
1308 /* FIXME! the reloc size is wrong in the BFD file.
1309 When it is fixed please delete me. */
1310 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1313 offset
= (insn
->short_insn
) ? 2 : 4;
1315 /* Some fixups are only used internally, thus no howto. */
1316 if ((int) fixup
->reloc
== 0)
1317 as_fatal (_("Unhandled reloc type"));
1319 if ((int) fixup
->reloc
< 0)
1321 /* FIXME! the reloc size is wrong in the BFD file.
1322 When it is fixed please enable me.
1323 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1324 pcrel
= fixup
->pcrel
;
1328 reloc_howto_type
*reloc_howto
=
1329 bfd_reloc_type_lookup (stdoutput
,
1330 (bfd_reloc_code_real_type
) fixup
->reloc
);
1331 gas_assert (reloc_howto
);
1333 /* FIXME! the reloc size is wrong in the BFD file.
1334 When it is fixed please enable me.
1335 size = bfd_get_reloc_size (reloc_howto); */
1336 pcrel
= reloc_howto
->pc_relative
;
1339 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1341 fragP
->fr_file
, fragP
->fr_line
,
1342 (fixup
->reloc
< 0) ? "Internal" :
1343 bfd_get_reloc_code_name (fixup
->reloc
),
1346 fix_new_exp (fragP
, fix
+ offset
,
1347 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1349 /* Check for ZOLs, and update symbol info if any. */
1350 if (LP_INSN (insn
->insn
))
1352 gas_assert (fixup
->exp
.X_add_symbol
);
1353 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1358 /* Actually output an instruction with its fixup. */
1361 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1365 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1366 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1367 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1369 /* Write out the instruction. */
1370 if (insn
->short_insn
)
1376 md_number_to_chars (f
, insn
->insn
, 2);
1377 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1378 dwarf2_emit_insn (6);
1384 md_number_to_chars (f
, insn
->insn
, 2);
1385 dwarf2_emit_insn (2);
1394 md_number_to_chars_midend (f
, insn
->insn
, 4);
1395 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1396 dwarf2_emit_insn (8);
1402 md_number_to_chars_midend (f
, insn
->insn
, 4);
1403 dwarf2_emit_insn (4);
1408 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1412 emit_insn1 (struct arc_insn
*insn
)
1414 /* How frag_var's args are currently configured:
1415 - rs_machine_dependent, to dictate it's a relaxation frag.
1416 - FRAG_MAX_GROWTH, maximum size of instruction
1417 - 0, variable size that might grow...unused by generic relaxation.
1418 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1419 - s, opand expression.
1420 - 0, offset but it's unused.
1421 - 0, opcode but it's unused. */
1422 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1423 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1425 if (frag_room () < FRAG_MAX_GROWTH
)
1427 /* Handle differently when frag literal memory is exhausted.
1428 This is used because when there's not enough memory left in
1429 the current frag, a new frag is created and the information
1430 we put into frag_now->tc_frag_data is disregarded. */
1432 struct arc_relax_type relax_info_copy
;
1433 relax_substateT subtype
= frag_now
->fr_subtype
;
1435 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1436 sizeof (struct arc_relax_type
));
1438 frag_wane (frag_now
);
1439 frag_grow (FRAG_MAX_GROWTH
);
1441 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1442 sizeof (struct arc_relax_type
));
1444 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1448 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1449 frag_now
->fr_subtype
, s
, 0, 0);
1453 emit_insn (struct arc_insn
*insn
)
1458 emit_insn0 (insn
, NULL
, FALSE
);
1461 /* Check whether a symbol involves a register. */
1464 contains_register (symbolS
*sym
)
1468 expressionS
*ex
= symbol_get_value_expression (sym
);
1470 return ((O_register
== ex
->X_op
)
1471 && !contains_register (ex
->X_add_symbol
)
1472 && !contains_register (ex
->X_op_symbol
));
1478 /* Returns the register number within a symbol. */
1481 get_register (symbolS
*sym
)
1483 if (!contains_register (sym
))
1486 expressionS
*ex
= symbol_get_value_expression (sym
);
1487 return regno (ex
->X_add_number
);
1490 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1491 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1494 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1501 case BFD_RELOC_ARC_SDA_LDST
:
1502 case BFD_RELOC_ARC_SDA_LDST1
:
1503 case BFD_RELOC_ARC_SDA_LDST2
:
1504 case BFD_RELOC_ARC_SDA16_LD
:
1505 case BFD_RELOC_ARC_SDA16_LD1
:
1506 case BFD_RELOC_ARC_SDA16_LD2
:
1507 case BFD_RELOC_ARC_SDA16_ST2
:
1508 case BFD_RELOC_ARC_SDA32_ME
:
1515 /* Allocates a tok entry. */
1518 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1520 if (ntok
> MAX_INSN_ARGS
- 2)
1521 return 0; /* No space left. */
1524 return 0; /* Incorect args. */
1526 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1529 return 1; /* Success. */
1530 return allocate_tok (tok
, ntok
- 1, cidx
);
1533 /* Check if an particular ARC feature is enabled. */
1536 check_cpu_feature (insn_subclass_t sc
)
1538 if (is_code_density_p (sc
) && !(arc_features
& ARC_CD
))
1541 if (is_spfp_p (sc
) && !(arc_features
& ARC_SPFP
))
1544 if (is_dpfp_p (sc
) && !(arc_features
& ARC_DPFP
))
1547 if (is_fpuda_p (sc
) && !(arc_features
& ARC_FPUDA
))
1550 if (is_nps400_p (sc
) && !(arc_features
& ARC_NPS400
))
1556 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1557 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1558 array and returns TRUE if the flag operands all match, otherwise,
1559 returns FALSE, in which case the FIRST_PFLAG array may have been
1563 parse_opcode_flags (const struct arc_opcode
*opcode
,
1565 struct arc_flags
*first_pflag
)
1568 const unsigned char *flgidx
;
1571 for (i
= 0; i
< nflgs
; i
++)
1572 first_pflag
[i
].flgp
= NULL
;
1574 /* Check the flags. Iterate over the valid flag classes. */
1575 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1577 /* Get a valid flag class. */
1578 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1579 const unsigned *flgopridx
;
1581 struct arc_flags
*pflag
= NULL
;
1583 /* Check for extension conditional codes. */
1584 if (ext_condcode
.arc_ext_condcode
1585 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1587 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1590 pflag
= first_pflag
;
1591 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1593 if (!strcmp (pf
->name
, pflag
->name
))
1595 if (pflag
->flgp
!= NULL
)
1608 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1610 const struct arc_flag_operand
*flg_operand
;
1612 pflag
= first_pflag
;
1613 flg_operand
= &arc_flag_operands
[*flgopridx
];
1614 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1616 /* Match against the parsed flags. */
1617 if (!strcmp (flg_operand
->name
, pflag
->name
))
1619 if (pflag
->flgp
!= NULL
)
1622 pflag
->flgp
= flg_operand
;
1624 break; /* goto next flag class and parsed flag. */
1629 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1631 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1635 /* Did I check all the parsed flags? */
1636 return lnflg
? FALSE
: TRUE
;
1640 /* Search forward through all variants of an opcode looking for a
1643 static const struct arc_opcode
*
1644 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1647 struct arc_flags
*first_pflag
,
1651 const struct arc_opcode
*opcode
;
1652 struct arc_opcode_hash_entry_iterator iter
;
1654 int got_cpu_match
= 0;
1655 expressionS bktok
[MAX_INSN_ARGS
];
1659 arc_opcode_hash_entry_iterator_init (&iter
);
1660 memset (&emptyE
, 0, sizeof (emptyE
));
1661 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1664 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1666 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1668 const unsigned char *opidx
;
1670 const expressionS
*t
= &emptyE
;
1672 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1673 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1675 /* Don't match opcodes that don't exist on this
1677 if (!(opcode
->cpu
& arc_target
))
1680 if (!check_cpu_feature (opcode
->subclass
))
1686 /* Check the operands. */
1687 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1689 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1691 /* Only take input from real operands. */
1692 if ((operand
->flags
& ARC_OPERAND_FAKE
)
1693 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
1696 /* When we expect input, make sure we have it. */
1700 /* Match operand type with expression type. */
1701 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1703 case ARC_OPERAND_IR
:
1704 /* Check to be a register. */
1705 if ((tok
[tokidx
].X_op
!= O_register
1706 || !is_ir_num (tok
[tokidx
].X_add_number
))
1707 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1710 /* If expect duplicate, make sure it is duplicate. */
1711 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1713 /* Check for duplicate. */
1714 if (t
->X_op
!= O_register
1715 || !is_ir_num (t
->X_add_number
)
1716 || (regno (t
->X_add_number
) !=
1717 regno (tok
[tokidx
].X_add_number
)))
1721 /* Special handling? */
1722 if (operand
->insert
)
1724 const char *errmsg
= NULL
;
1725 (*operand
->insert
)(0,
1726 regno (tok
[tokidx
].X_add_number
),
1730 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1732 /* Missing argument, create one. */
1733 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1736 tok
[tokidx
].X_op
= O_absent
;
1747 case ARC_OPERAND_BRAKET
:
1748 /* Check if bracket is also in opcode table as
1750 if (tok
[tokidx
].X_op
!= O_bracket
)
1754 case ARC_OPERAND_LIMM
:
1755 case ARC_OPERAND_SIGNED
:
1756 case ARC_OPERAND_UNSIGNED
:
1757 switch (tok
[tokidx
].X_op
)
1765 /* Got an (too) early bracket, check if it is an
1766 ignored operand. N.B. This procedure works only
1767 when bracket is the last operand! */
1768 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1770 /* Insert the missing operand. */
1771 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1774 tok
[tokidx
].X_op
= O_absent
;
1781 const struct arc_aux_reg
*auxr
;
1783 if (opcode
->insn_class
!= AUXREG
)
1785 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1787 auxr
= hash_find (arc_aux_hash
, p
);
1790 /* We modify the token array here, safe in the
1791 knowledge, that if this was the wrong
1792 choice then the original contents will be
1793 restored from BKTOK. */
1794 tok
[tokidx
].X_op
= O_constant
;
1795 tok
[tokidx
].X_add_number
= auxr
->address
;
1796 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1799 if (tok
[tokidx
].X_op
!= O_constant
)
1804 /* Check the range. */
1805 if (operand
->bits
!= 32
1806 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1808 offsetT min
, max
, val
;
1809 val
= tok
[tokidx
].X_add_number
;
1811 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1813 max
= (1 << (operand
->bits
- 1)) - 1;
1814 min
= -(1 << (operand
->bits
- 1));
1818 max
= (1 << operand
->bits
) - 1;
1822 if (val
< min
|| val
> max
)
1825 /* Check alignmets. */
1826 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1830 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1834 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1836 if (operand
->insert
)
1838 const char *errmsg
= NULL
;
1839 (*operand
->insert
)(0,
1840 tok
[tokidx
].X_add_number
,
1845 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1851 /* Check if it is register range. */
1852 if ((tok
[tokidx
].X_add_number
== 0)
1853 && contains_register (tok
[tokidx
].X_add_symbol
)
1854 && contains_register (tok
[tokidx
].X_op_symbol
))
1858 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1860 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1861 if (operand
->insert
)
1863 const char *errmsg
= NULL
;
1864 (*operand
->insert
)(0,
1876 if (operand
->default_reloc
== 0)
1877 goto match_failed
; /* The operand needs relocation. */
1879 /* Relocs requiring long immediate. FIXME! make it
1880 generic and move it to a function. */
1881 switch (tok
[tokidx
].X_md
)
1890 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1893 if (!generic_reloc_p (operand
->default_reloc
))
1900 /* If expect duplicate, make sure it is duplicate. */
1901 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1903 if (t
->X_op
== O_illegal
1904 || t
->X_op
== O_absent
1905 || t
->X_op
== O_register
1906 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1913 /* Everything else should have been fake. */
1921 /* Setup ready for flag parsing. */
1922 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
1926 /* Possible match -- did we use all of our input? */
1936 /* Restore the original parameters. */
1937 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1942 *pcpumatch
= got_cpu_match
;
1947 /* Swap operand tokens. */
1950 swap_operand (expressionS
*operand_array
,
1952 unsigned destination
)
1954 expressionS cpy_operand
;
1955 expressionS
*src_operand
;
1956 expressionS
*dst_operand
;
1959 if (source
== destination
)
1962 src_operand
= &operand_array
[source
];
1963 dst_operand
= &operand_array
[destination
];
1964 size
= sizeof (expressionS
);
1966 /* Make copy of operand to swap with and swap. */
1967 memcpy (&cpy_operand
, dst_operand
, size
);
1968 memcpy (dst_operand
, src_operand
, size
);
1969 memcpy (src_operand
, &cpy_operand
, size
);
1972 /* Check if *op matches *tok type.
1973 Returns FALSE if they don't match, TRUE if they match. */
1976 pseudo_operand_match (const expressionS
*tok
,
1977 const struct arc_operand_operation
*op
)
1979 offsetT min
, max
, val
;
1981 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
1987 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
1989 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
1991 val
= tok
->X_add_number
+ op
->count
;
1992 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
1994 max
= (1 << (operand_real
->bits
- 1)) - 1;
1995 min
= -(1 << (operand_real
->bits
- 1));
1999 max
= (1 << operand_real
->bits
) - 1;
2002 if (min
<= val
&& val
<= max
)
2008 /* Handle all symbols as long immediates or signed 9. */
2009 if (operand_real
->flags
& ARC_OPERAND_LIMM
||
2010 ((operand_real
->flags
& ARC_OPERAND_SIGNED
) && operand_real
->bits
== 9))
2015 if (operand_real
->flags
& ARC_OPERAND_IR
)
2020 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2031 /* Find pseudo instruction in array. */
2033 static const struct arc_pseudo_insn
*
2034 find_pseudo_insn (const char *opname
,
2036 const expressionS
*tok
)
2038 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2039 const struct arc_operand_operation
*op
;
2043 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2045 pseudo_insn
= &arc_pseudo_insns
[i
];
2046 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2048 op
= pseudo_insn
->operand
;
2049 for (j
= 0; j
< ntok
; ++j
)
2050 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2053 /* Found the right instruction. */
2061 /* Assumes the expressionS *tok is of sufficient size. */
2063 static const struct arc_opcode_hash_entry
*
2064 find_special_case_pseudo (const char *opname
,
2068 struct arc_flags
*pflags
)
2070 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2071 const struct arc_operand_operation
*operand_pseudo
;
2072 const struct arc_operand
*operand_real
;
2074 char construct_operand
[MAX_CONSTR_STR
];
2076 /* Find whether opname is in pseudo instruction array. */
2077 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2079 if (pseudo_insn
== NULL
)
2082 /* Handle flag, Limited to one flag at the moment. */
2083 if (pseudo_insn
->flag_r
!= NULL
)
2084 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2085 MAX_INSN_FLGS
- *nflgs
);
2087 /* Handle operand operations. */
2088 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2090 operand_pseudo
= &pseudo_insn
->operand
[i
];
2091 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2093 if (operand_real
->flags
& ARC_OPERAND_BRAKET
&&
2094 !operand_pseudo
->needs_insert
)
2097 /* Has to be inserted (i.e. this token does not exist yet). */
2098 if (operand_pseudo
->needs_insert
)
2100 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2102 tok
[i
].X_op
= O_bracket
;
2107 /* Check if operand is a register or constant and handle it
2109 if (operand_real
->flags
& ARC_OPERAND_IR
)
2110 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2111 operand_pseudo
->count
);
2113 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2114 operand_pseudo
->count
);
2116 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2120 else if (operand_pseudo
->count
)
2122 /* Operand number has to be adjusted accordingly (by operand
2124 switch (tok
[i
].X_op
)
2127 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2140 /* Swap operands if necessary. Only supports one swap at the
2142 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2144 operand_pseudo
= &pseudo_insn
->operand
[i
];
2146 if (operand_pseudo
->swap_operand_idx
== i
)
2149 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2151 /* Prevent a swap back later by breaking out. */
2155 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2158 static const struct arc_opcode_hash_entry
*
2159 find_special_case_flag (const char *opname
,
2161 struct arc_flags
*pflags
)
2165 unsigned flag_idx
, flag_arr_idx
;
2166 size_t flaglen
, oplen
;
2167 const struct arc_flag_special
*arc_flag_special_opcode
;
2168 const struct arc_opcode_hash_entry
*entry
;
2170 /* Search for special case instruction. */
2171 for (i
= 0; i
< arc_num_flag_special
; i
++)
2173 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2174 oplen
= strlen (arc_flag_special_opcode
->name
);
2176 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2179 /* Found a potential special case instruction, now test for
2181 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2183 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2185 break; /* End of array, nothing found. */
2187 flagnm
= arc_flag_operands
[flag_idx
].name
;
2188 flaglen
= strlen (flagnm
);
2189 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2191 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2193 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2195 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2196 pflags
[*nflgs
].name
[flaglen
] = '\0';
2205 /* The long instructions are not stored in a hash (there's not many of
2206 them) and so there's no arc_opcode_hash_entry structure to return. This
2207 helper function for find_special_case_long_opcode takes an arc_opcode
2208 result and places it into a fake arc_opcode_hash_entry that points to
2209 the single arc_opcode OPCODE, which is then returned. */
2211 static const struct arc_opcode_hash_entry
*
2212 build_fake_opcode_hash_entry (const struct arc_opcode
*opcode
)
2214 static struct arc_opcode_hash_entry entry
;
2215 static struct arc_opcode tmp
[2];
2216 static const struct arc_opcode
*ptr
[2];
2218 memcpy (&tmp
[0], opcode
, sizeof (struct arc_opcode
));
2219 memset (&tmp
[1], 0, sizeof (struct arc_opcode
));
2228 /* Used by the assembler to match the list of tokens against a long (48 or
2229 64 bits) instruction. If a matching long instruction is found, then
2230 some of the tokens are consumed in this function and converted into a
2231 single LIMM value, which is then added to the end of the token list,
2232 where it will be consumed by a LIMM operand that exists in the base
2233 opcode of the long instruction. */
2235 static const struct arc_opcode_hash_entry
*
2236 find_special_case_long_opcode (const char *opname
,
2237 int *ntok ATTRIBUTE_UNUSED
,
2238 expressionS
*tok ATTRIBUTE_UNUSED
,
2240 struct arc_flags
*pflags
)
2244 if (*ntok
== MAX_INSN_ARGS
)
2247 for (i
= 0; i
< arc_num_long_opcodes
; ++i
)
2249 struct arc_opcode fake_opcode
;
2250 const struct arc_opcode
*opcode
;
2251 struct arc_insn insn
;
2252 expressionS
*limm_token
;
2254 opcode
= &arc_long_opcodes
[i
].base_opcode
;
2256 if (!(opcode
->cpu
& arc_target
))
2259 if (!check_cpu_feature (opcode
->subclass
))
2262 if (strcmp (opname
, opcode
->name
) != 0)
2265 /* Check that the flags are a match. */
2266 if (!parse_opcode_flags (opcode
, *nflgs
, pflags
))
2269 /* Parse the LIMM operands into the LIMM template. */
2270 memset (&fake_opcode
, 0, sizeof (fake_opcode
));
2271 fake_opcode
.name
= "fake limm";
2272 fake_opcode
.opcode
= arc_long_opcodes
[i
].limm_template
;
2273 fake_opcode
.mask
= arc_long_opcodes
[i
].limm_mask
;
2274 fake_opcode
.cpu
= opcode
->cpu
;
2275 fake_opcode
.insn_class
= opcode
->insn_class
;
2276 fake_opcode
.subclass
= opcode
->subclass
;
2277 memcpy (&fake_opcode
.operands
[0],
2278 &arc_long_opcodes
[i
].operands
,
2280 /* Leave fake_opcode.flags as zero. */
2282 pr_debug ("Calling assemble_insn to build fake limm value\n");
2283 assemble_insn (&fake_opcode
, tok
, *ntok
,
2285 pr_debug (" got limm value: 0x%x\n", insn
.insn
);
2287 /* Now create a new token at the end of the token array (We know this
2288 is safe as the token array is always created with enough space for
2289 MAX_INSN_ARGS, and we check at the start at the start of this
2290 function that we're not there yet). This new token will
2291 correspond to a LIMM operand that will be contained in the
2292 base_opcode of the arc_long_opcode. */
2293 limm_token
= &tok
[(*ntok
)];
2296 /* Modify the LIMM token to hold the constant. */
2297 limm_token
->X_op
= O_constant
;
2298 limm_token
->X_add_number
= insn
.insn
;
2300 /* Return the base opcode. */
2301 return build_fake_opcode_hash_entry (opcode
);
2307 /* Used to find special case opcode. */
2309 static const struct arc_opcode_hash_entry
*
2310 find_special_case (const char *opname
,
2312 struct arc_flags
*pflags
,
2316 const struct arc_opcode_hash_entry
*entry
;
2318 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2321 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2324 entry
= find_special_case_long_opcode (opname
, ntok
, tok
, nflgs
, pflags
);
2329 /* Given an opcode name, pre-tockenized set of argumenst and the
2330 opcode flags, take it all the way through emission. */
2333 assemble_tokens (const char *opname
,
2336 struct arc_flags
*pflags
,
2339 bfd_boolean found_something
= FALSE
;
2340 const struct arc_opcode_hash_entry
*entry
;
2343 /* Search opcodes. */
2344 entry
= arc_find_opcode (opname
);
2346 /* Couldn't find opcode conventional way, try special cases. */
2348 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2352 const struct arc_opcode
*opcode
;
2354 pr_debug ("%s:%d: assemble_tokens: %s\n",
2355 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2356 found_something
= TRUE
;
2357 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2361 struct arc_insn insn
;
2363 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2369 if (found_something
)
2372 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2374 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2378 as_bad (_("unknown opcode '%s'"), opname
);
2381 /* The public interface to the instruction assembler. */
2384 md_assemble (char *str
)
2387 expressionS tok
[MAX_INSN_ARGS
];
2390 struct arc_flags flags
[MAX_INSN_FLGS
];
2392 /* Split off the opcode. */
2393 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2394 opname
= xmemdup0 (str
, opnamelen
);
2396 /* Signalize we are assmbling the instructions. */
2397 assembling_insn
= TRUE
;
2399 /* Tokenize the flags. */
2400 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2402 as_bad (_("syntax error"));
2406 /* Scan up to the end of the mnemonic which must end in space or end
2409 for (; *str
!= '\0'; str
++)
2413 /* Tokenize the rest of the line. */
2414 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2416 as_bad (_("syntax error"));
2420 /* Finish it off. */
2421 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2422 assembling_insn
= FALSE
;
2425 /* Callback to insert a register into the hash table. */
2428 declare_register (const char *name
, int number
)
2431 symbolS
*regS
= symbol_create (name
, reg_section
,
2432 number
, &zero_address_frag
);
2434 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2436 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2440 /* Construct symbols for each of the general registers. */
2443 declare_register_set (void)
2446 for (i
= 0; i
< 64; ++i
)
2450 sprintf (name
, "r%d", i
);
2451 declare_register (name
, i
);
2452 if ((i
& 0x01) == 0)
2454 sprintf (name
, "r%dr%d", i
, i
+1);
2455 declare_register (name
, i
);
2460 /* Port-specific assembler initialization. This function is called
2461 once, at assembler startup time. */
2466 const struct arc_opcode
*opcode
= arc_opcodes
;
2468 if (!mach_type_specified_p
)
2469 arc_select_cpu ("arc700");
2471 /* The endianness can be chosen "at the factory". */
2472 target_big_endian
= byte_order
== BIG_ENDIAN
;
2474 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2475 as_warn (_("could not set architecture and machine"));
2477 /* Set elf header flags. */
2478 bfd_set_private_flags (stdoutput
, arc_eflag
);
2480 /* Set up a hash table for the instructions. */
2481 arc_opcode_hash
= hash_new ();
2482 if (arc_opcode_hash
== NULL
)
2483 as_fatal (_("Virtual memory exhausted"));
2485 /* Initialize the hash table with the insns. */
2488 const char *name
= opcode
->name
;
2490 arc_insert_opcode (opcode
);
2492 while (++opcode
&& opcode
->name
2493 && (opcode
->name
== name
2494 || !strcmp (opcode
->name
, name
)))
2496 }while (opcode
->name
);
2498 /* Register declaration. */
2499 arc_reg_hash
= hash_new ();
2500 if (arc_reg_hash
== NULL
)
2501 as_fatal (_("Virtual memory exhausted"));
2503 declare_register_set ();
2504 declare_register ("gp", 26);
2505 declare_register ("fp", 27);
2506 declare_register ("sp", 28);
2507 declare_register ("ilink", 29);
2508 declare_register ("ilink1", 29);
2509 declare_register ("ilink2", 30);
2510 declare_register ("blink", 31);
2512 /* XY memory registers. */
2513 declare_register ("x0_u0", 32);
2514 declare_register ("x0_u1", 33);
2515 declare_register ("x1_u0", 34);
2516 declare_register ("x1_u1", 35);
2517 declare_register ("x2_u0", 36);
2518 declare_register ("x2_u1", 37);
2519 declare_register ("x3_u0", 38);
2520 declare_register ("x3_u1", 39);
2521 declare_register ("y0_u0", 40);
2522 declare_register ("y0_u1", 41);
2523 declare_register ("y1_u0", 42);
2524 declare_register ("y1_u1", 43);
2525 declare_register ("y2_u0", 44);
2526 declare_register ("y2_u1", 45);
2527 declare_register ("y3_u0", 46);
2528 declare_register ("y3_u1", 47);
2529 declare_register ("x0_nu", 48);
2530 declare_register ("x1_nu", 49);
2531 declare_register ("x2_nu", 50);
2532 declare_register ("x3_nu", 51);
2533 declare_register ("y0_nu", 52);
2534 declare_register ("y1_nu", 53);
2535 declare_register ("y2_nu", 54);
2536 declare_register ("y3_nu", 55);
2538 declare_register ("mlo", 57);
2539 declare_register ("mmid", 58);
2540 declare_register ("mhi", 59);
2542 declare_register ("acc1", 56);
2543 declare_register ("acc2", 57);
2545 declare_register ("lp_count", 60);
2546 declare_register ("pcl", 63);
2548 /* Initialize the last instructions. */
2549 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2551 /* Aux register declaration. */
2552 arc_aux_hash
= hash_new ();
2553 if (arc_aux_hash
== NULL
)
2554 as_fatal (_("Virtual memory exhausted"));
2556 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2558 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2562 if (!(auxr
->cpu
& arc_target
))
2565 if ((auxr
->subclass
!= NONE
)
2566 && !check_cpu_feature (auxr
->subclass
))
2569 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2571 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2572 auxr
->name
, retval
);
2576 /* Write a value out to the object file, using the appropriate
2580 md_number_to_chars (char *buf
,
2584 if (target_big_endian
)
2585 number_to_chars_bigendian (buf
, val
, n
);
2587 number_to_chars_littleendian (buf
, val
, n
);
2590 /* Round up a section size to the appropriate boundary. */
2593 md_section_align (segT segment
,
2596 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2598 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2601 /* The location from which a PC relative jump should be calculated,
2602 given a PC relative reloc. */
2605 md_pcrel_from_section (fixS
*fixP
,
2608 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2610 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2612 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2613 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2614 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2616 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2618 /* The symbol is undefined (or is defined but not in this section).
2619 Let the linker figure it out. */
2623 if ((int) fixP
->fx_r_type
< 0)
2625 /* These are the "internal" relocations. Align them to
2626 32 bit boundary (PCL), for the moment. */
2631 switch (fixP
->fx_r_type
)
2633 case BFD_RELOC_ARC_PC32
:
2634 /* The hardware calculates relative to the start of the
2635 insn, but this relocation is relative to location of the
2636 LIMM, compensate. The base always needs to be
2637 substracted by 4 as we do not support this type of PCrel
2638 relocation for short instructions. */
2641 case BFD_RELOC_ARC_PLT32
:
2642 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2643 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2644 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2645 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2647 case BFD_RELOC_ARC_S21H_PCREL
:
2648 case BFD_RELOC_ARC_S25H_PCREL
:
2649 case BFD_RELOC_ARC_S13_PCREL
:
2650 case BFD_RELOC_ARC_S21W_PCREL
:
2651 case BFD_RELOC_ARC_S25W_PCREL
:
2655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2656 _("unhandled reloc %s in md_pcrel_from_section"),
2657 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2662 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2663 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2664 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2665 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2666 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2671 /* Given a BFD relocation find the coresponding operand. */
2673 static const struct arc_operand
*
2674 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2678 for (i
= 0; i
< arc_num_operands
; i
++)
2679 if (arc_operands
[i
].default_reloc
== reloc
)
2680 return &arc_operands
[i
];
2684 /* Insert an operand value into an instruction. */
2687 insert_operand (unsigned insn
,
2688 const struct arc_operand
*operand
,
2693 offsetT min
= 0, max
= 0;
2695 if (operand
->bits
!= 32
2696 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2697 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2699 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2701 max
= (1 << (operand
->bits
- 1)) - 1;
2702 min
= -(1 << (operand
->bits
- 1));
2706 max
= (1 << operand
->bits
) - 1;
2710 if (val
< min
|| val
> max
)
2711 as_bad_value_out_of_range (_("operand"),
2712 val
, min
, max
, file
, line
);
2715 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2716 min
, val
, max
, insn
);
2718 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2720 as_bad_where (file
, line
,
2721 _("Unaligned operand. Needs to be 32bit aligned"));
2723 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2725 as_bad_where (file
, line
,
2726 _("Unaligned operand. Needs to be 16bit aligned"));
2728 if (operand
->insert
)
2730 const char *errmsg
= NULL
;
2732 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2734 as_warn_where (file
, line
, "%s", errmsg
);
2738 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2740 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2742 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2745 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2750 /* Apply a fixup to the object code. At this point all symbol values
2751 should be fully resolved, and we attempt to completely resolve the
2752 reloc. If we can not do that, we determine the correct reloc code
2753 and put it back in the fixup. To indicate that a fixup has been
2754 eliminated, set fixP->fx_done. */
2757 md_apply_fix (fixS
*fixP
,
2761 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2762 valueT value
= *valP
;
2764 symbolS
*fx_addsy
, *fx_subsy
;
2766 segT add_symbol_segment
= absolute_section
;
2767 segT sub_symbol_segment
= absolute_section
;
2768 const struct arc_operand
*operand
= NULL
;
2769 extended_bfd_reloc_code_real_type reloc
;
2771 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2772 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2773 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2774 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2777 fx_addsy
= fixP
->fx_addsy
;
2778 fx_subsy
= fixP
->fx_subsy
;
2783 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2787 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2788 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2789 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2791 resolve_symbol_value (fx_subsy
);
2792 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2794 if (sub_symbol_segment
== absolute_section
)
2796 /* The symbol is really a constant. */
2797 fx_offset
-= S_GET_VALUE (fx_subsy
);
2802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2803 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2804 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2805 segment_name (add_symbol_segment
),
2806 S_GET_NAME (fx_subsy
),
2807 segment_name (sub_symbol_segment
));
2813 && !S_IS_WEAK (fx_addsy
))
2815 if (add_symbol_segment
== seg
2818 value
+= S_GET_VALUE (fx_addsy
);
2819 value
-= md_pcrel_from_section (fixP
, seg
);
2821 fixP
->fx_pcrel
= FALSE
;
2823 else if (add_symbol_segment
== absolute_section
)
2825 value
= fixP
->fx_offset
;
2826 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2828 fixP
->fx_pcrel
= FALSE
;
2833 fixP
->fx_done
= TRUE
;
2838 && ((S_IS_DEFINED (fx_addsy
)
2839 && S_GET_SEGMENT (fx_addsy
) != seg
)
2840 || S_IS_WEAK (fx_addsy
)))
2841 value
+= md_pcrel_from_section (fixP
, seg
);
2843 switch (fixP
->fx_r_type
)
2845 case BFD_RELOC_ARC_32_ME
:
2846 /* This is a pc-relative value in a LIMM. Adjust it to the
2847 address of the instruction not to the address of the
2848 LIMM. Note: it is not anylonger valid this afirmation as
2849 the linker consider ARC_PC32 a fixup to entire 64 bit
2851 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2854 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2856 case BFD_RELOC_ARC_PC32
:
2857 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2860 if ((int) fixP
->fx_r_type
< 0)
2861 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2867 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2868 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2869 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2870 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2874 /* Now check for TLS relocations. */
2875 reloc
= fixP
->fx_r_type
;
2878 case BFD_RELOC_ARC_TLS_DTPOFF
:
2879 case BFD_RELOC_ARC_TLS_LE_32
:
2883 case BFD_RELOC_ARC_TLS_GD_GOT
:
2884 case BFD_RELOC_ARC_TLS_IE_GOT
:
2885 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2888 case BFD_RELOC_ARC_TLS_GD_LD
:
2889 gas_assert (!fixP
->fx_offset
);
2892 = (S_GET_VALUE (fixP
->fx_subsy
)
2893 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2894 fixP
->fx_subsy
= NULL
;
2896 case BFD_RELOC_ARC_TLS_GD_CALL
:
2897 /* These two relocs are there just to allow ld to change the tls
2898 model for this symbol, by patching the code. The offset -
2899 and scale, if any - will be installed by the linker. */
2900 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2903 case BFD_RELOC_ARC_TLS_LE_S9
:
2904 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2905 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2917 /* Addjust the value if we have a constant. */
2920 /* For hosts with longs bigger than 32-bits make sure that the top
2921 bits of a 32-bit negative value read in by the parser are set,
2922 so that the correct comparisons are made. */
2923 if (value
& 0x80000000)
2924 value
|= (-1UL << 31);
2926 reloc
= fixP
->fx_r_type
;
2934 case BFD_RELOC_ARC_32_PCREL
:
2935 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2938 case BFD_RELOC_ARC_GOTPC32
:
2939 /* I cannot fix an GOTPC relocation because I need to relax it
2940 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2941 as_bad (_("Unsupported operation on reloc"));
2944 case BFD_RELOC_ARC_TLS_DTPOFF
:
2945 case BFD_RELOC_ARC_TLS_LE_32
:
2946 gas_assert (!fixP
->fx_addsy
);
2947 gas_assert (!fixP
->fx_subsy
);
2949 case BFD_RELOC_ARC_GOTOFF
:
2950 case BFD_RELOC_ARC_32_ME
:
2951 case BFD_RELOC_ARC_PC32
:
2952 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2955 case BFD_RELOC_ARC_PLT32
:
2956 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2959 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2960 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2963 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2964 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2967 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2968 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2971 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2972 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2974 case BFD_RELOC_ARC_S25W_PCREL
:
2975 case BFD_RELOC_ARC_S21W_PCREL
:
2976 case BFD_RELOC_ARC_S21H_PCREL
:
2977 case BFD_RELOC_ARC_S25H_PCREL
:
2978 case BFD_RELOC_ARC_S13_PCREL
:
2980 operand
= find_operand_for_reloc (reloc
);
2981 gas_assert (operand
);
2986 if ((int) fixP
->fx_r_type
>= 0)
2987 as_fatal (_("unhandled relocation type %s"),
2988 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2990 /* The rest of these fixups needs to be completely resolved as
2992 if (fixP
->fx_addsy
!= 0
2993 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2994 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2995 _("non-absolute expression in constant field"));
2997 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2998 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3003 if (target_big_endian
)
3005 switch (fixP
->fx_size
)
3008 insn
= bfd_getb32 (fixpos
);
3011 insn
= bfd_getb16 (fixpos
);
3014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3015 _("unknown fixup size"));
3021 switch (fixP
->fx_size
)
3024 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3027 insn
= bfd_getl16 (fixpos
);
3030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3031 _("unknown fixup size"));
3035 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3036 fixP
->fx_file
, fixP
->fx_line
);
3038 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3041 /* Prepare machine-dependent frags for relaxation.
3043 Called just before relaxation starts. Any symbol that is now undefined
3044 will not become defined.
3046 Return the correct fr_subtype in the frag.
3048 Return the initial "guess for fr_var" to caller. The guess for fr_var
3049 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3050 or fr_var contributes to our returned value.
3052 Although it may not be explicit in the frag, pretend
3053 fr_var starts with a value. */
3056 md_estimate_size_before_relax (fragS
*fragP
,
3061 /* If the symbol is not located within the same section AND it's not
3062 an absolute section, use the maximum. OR if the symbol is a
3063 constant AND the insn is by nature not pc-rel, use the maximum.
3064 OR if the symbol is being equated against another symbol, use the
3065 maximum. OR if the symbol is weak use the maximum. */
3066 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3067 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3068 || (symbol_constant_p (fragP
->fr_symbol
)
3069 && !fragP
->tc_frag_data
.pcrel
)
3070 || symbol_equated_p (fragP
->fr_symbol
)
3071 || S_IS_WEAK (fragP
->fr_symbol
))
3073 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3074 ++fragP
->fr_subtype
;
3077 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3078 fragP
->fr_var
= growth
;
3080 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3081 fragP
->fr_file
, fragP
->fr_line
, growth
);
3086 /* Translate internal representation of relocation info to BFD target
3090 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3094 bfd_reloc_code_real_type code
;
3096 reloc
= XNEW (arelent
);
3097 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3098 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3099 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3101 /* Make sure none of our internal relocations make it this far.
3102 They'd better have been fully resolved by this point. */
3103 gas_assert ((int) fixP
->fx_r_type
> 0);
3105 code
= fixP
->fx_r_type
;
3107 /* if we have something like add gp, pcl,
3108 _GLOBAL_OFFSET_TABLE_@gotpc. */
3109 if (code
== BFD_RELOC_ARC_GOTPC32
3111 && fixP
->fx_addsy
== GOT_symbol
)
3112 code
= BFD_RELOC_ARC_GOTPC
;
3114 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3115 if (reloc
->howto
== NULL
)
3117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3118 _("cannot represent `%s' relocation in object file"),
3119 bfd_get_reloc_code_name (code
));
3123 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3124 as_fatal (_("internal error? cannot generate `%s' relocation"),
3125 bfd_get_reloc_code_name (code
));
3127 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3129 if (code
== BFD_RELOC_ARC_TLS_DTPOFF
3130 || code
== BFD_RELOC_ARC_TLS_DTPOFF_S9
)
3133 = fixP
->fx_subsy
? symbol_get_bfdsym (fixP
->fx_subsy
) : NULL
;
3134 /* We just want to store a 24 bit index, but we have to wait
3135 till after write_contents has been called via
3136 bfd_map_over_sections before we can get the index from
3137 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
3138 function is elf32-arc.c has to pick up the slack.
3139 Unfortunately, this leads to problems with hosts that have
3140 pointers wider than long (bfd_vma). There would be various
3141 ways to handle this, all error-prone :-( */
3142 reloc
->addend
= (bfd_vma
) sym
;
3143 if ((asymbol
*) reloc
->addend
!= sym
)
3145 as_bad ("Can't store pointer\n");
3150 reloc
->addend
= fixP
->fx_offset
;
3155 /* Perform post-processing of machine-dependent frags after relaxation.
3156 Called after relaxation is finished.
3157 In: Address of frag.
3158 fr_type == rs_machine_dependent.
3159 fr_subtype is what the address relaxed to.
3161 Out: Any fixS:s and constants are set up. */
3164 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3165 segT segment ATTRIBUTE_UNUSED
,
3168 const relax_typeS
*table_entry
;
3170 const struct arc_opcode
*opcode
;
3171 struct arc_insn insn
;
3173 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3175 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3176 dest
= fragP
->fr_literal
+ fix
;
3177 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3179 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3180 "var: %"BFD_VMA_FMT
"d\n",
3181 fragP
->fr_file
, fragP
->fr_line
,
3182 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3184 if (fragP
->fr_subtype
<= 0
3185 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3186 as_fatal (_("no relaxation found for this instruction."));
3188 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3190 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3191 relax_arg
->nflg
, &insn
);
3193 apply_fixups (&insn
, fragP
, fix
);
3195 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
3196 gas_assert (table_entry
->rlx_length
== size
);
3197 emit_insn0 (&insn
, dest
, TRUE
);
3199 fragP
->fr_fix
+= table_entry
->rlx_length
;
3203 /* We have no need to default values of symbols. We could catch
3204 register names here, but that is handled by inserting them all in
3205 the symbol table to begin with. */
3208 md_undefined_symbol (char *name
)
3210 /* The arc abi demands that a GOT[0] should be referencible as
3211 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3212 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3214 && (*(name
+1) == 'G')
3215 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3217 && (*(name
+1) == 'D')
3218 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3222 if (symbol_find (name
))
3223 as_bad ("GOT already in symbol table");
3225 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3226 (valueT
) 0, &zero_address_frag
);
3233 /* Turn a string in input_line_pointer into a floating point constant
3234 of type type, and store the appropriate bytes in *litP. The number
3235 of LITTLENUMS emitted is stored in *sizeP. An error message is
3236 returned, or NULL on OK. */
3239 md_atof (int type
, char *litP
, int *sizeP
)
3241 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3244 /* Called for any expression that can not be recognized. When the
3245 function is called, `input_line_pointer' will point to the start of
3249 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3251 char *p
= input_line_pointer
;
3254 input_line_pointer
++;
3255 expressionP
->X_op
= O_symbol
;
3256 expression (expressionP
);
3260 /* This function is called from the function 'expression', it attempts
3261 to parse special names (in our case register names). It fills in
3262 the expression with the identified register. It returns TRUE if
3263 it is a register and FALSE otherwise. */
3266 arc_parse_name (const char *name
,
3267 struct expressionS
*e
)
3271 if (!assembling_insn
)
3274 /* Handle only registers. */
3275 if (e
->X_op
!= O_absent
)
3278 sym
= hash_find (arc_reg_hash
, name
);
3281 e
->X_op
= O_register
;
3282 e
->X_add_number
= S_GET_VALUE (sym
);
3289 Invocation line includes a switch not recognized by the base assembler.
3290 See if it's a processor-specific option.
3292 New options (supported) are:
3294 -mcpu=<cpu name> Assemble for selected processor
3295 -EB/-mbig-endian Big-endian
3296 -EL/-mlittle-endian Little-endian
3297 -mrelax Enable relaxation
3299 The following CPU names are recognized:
3300 arc600, arc700, arcem, archs, nps400. */
3303 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3309 return md_parse_option (OPTION_MCPU
, "arc600");
3312 return md_parse_option (OPTION_MCPU
, "arc700");
3315 return md_parse_option (OPTION_MCPU
, "arcem");
3318 return md_parse_option (OPTION_MCPU
, "archs");
3322 arc_select_cpu (arg
);
3323 mach_type_specified_p
= TRUE
;
3328 arc_target_format
= "elf32-bigarc";
3329 byte_order
= BIG_ENDIAN
;
3333 arc_target_format
= "elf32-littlearc";
3334 byte_order
= LITTLE_ENDIAN
;
3338 /* This option has an effect only on ARC EM. */
3339 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3340 arc_features
|= ARC_CD
;
3342 as_warn (_("Code density option invalid for selected CPU"));
3346 relaxation_state
= 1;
3350 arc_features
|= ARC_NPS400
;
3354 arc_features
|= ARC_SPFP
;
3358 arc_features
|= ARC_DPFP
;
3362 /* This option has an effect only on ARC EM. */
3363 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3364 arc_features
|= ARC_FPUDA
;
3366 as_warn (_("FPUDA invalid for selected CPU"));
3369 /* Dummy options are accepted but have no effect. */
3370 case OPTION_USER_MODE
:
3371 case OPTION_LD_EXT_MASK
:
3374 case OPTION_BARREL_SHIFT
:
3375 case OPTION_MIN_MAX
:
3380 case OPTION_XMAC_D16
:
3381 case OPTION_XMAC_24
:
3382 case OPTION_DSP_PACKA
:
3385 case OPTION_TELEPHONY
:
3386 case OPTION_XYMEMORY
:
3400 md_show_usage (FILE *stream
)
3402 fprintf (stream
, _("ARC-specific assembler options:\n"));
3404 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3405 fprintf (stream
, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
3406 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3407 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3408 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3409 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3411 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3412 fprintf (stream
, " -mspfp\t\t enable single-precision floating point instructions\n");
3413 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point instructions\n");
3414 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3415 "point\n\t\t\t instructions for ARC EM\n");
3418 " -mcode-density\t enable code density option for ARC EM\n");
3420 fprintf (stream
, _("\
3421 -EB assemble code for a big-endian cpu\n"));
3422 fprintf (stream
, _("\
3423 -EL assemble code for a little-endian cpu\n"));
3424 fprintf (stream
, _("\
3425 -mrelax enable relaxation\n"));
3427 fprintf (stream
, _("The following ARC-specific assembler options are "
3428 "deprecated and are accepted\nfor compatibility only:\n"));
3430 fprintf (stream
, _(" -mEA\n"
3431 " -mbarrel-shifter\n"
3432 " -mbarrel_shifter\n"
3437 " -mld-extension-reg-mask\n"
3453 " -muser-mode-only\n"
3457 /* Find the proper relocation for the given opcode. */
3459 static extended_bfd_reloc_code_real_type
3460 find_reloc (const char *name
,
3461 const char *opcodename
,
3462 const struct arc_flags
*pflags
,
3464 extended_bfd_reloc_code_real_type reloc
)
3468 bfd_boolean found_flag
, tmp
;
3469 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3471 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3473 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3475 /* Find the entry. */
3476 if (strcmp (name
, r
->name
))
3478 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3485 unsigned * psflg
= (unsigned *)r
->flags
;
3489 for (j
= 0; j
< nflg
; j
++)
3490 if (!strcmp (pflags
[j
].name
,
3491 arc_flag_operands
[*psflg
].name
))
3512 if (reloc
!= r
->oldreloc
)
3519 if (ret
== BFD_RELOC_UNUSED
)
3520 as_bad (_("Unable to find %s relocation for instruction %s"),
3525 /* All the symbol types that are allowed to be used for
3529 may_relax_expr (expressionS tok
)
3531 /* Check if we have unrelaxable relocs. */
3556 /* Checks if flags are in line with relaxable insn. */
3559 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3560 const struct arc_flags
*pflags
,
3563 unsigned flag_class
,
3568 const struct arc_flag_operand
*flag_opand
;
3569 int i
, counttrue
= 0;
3571 /* Iterate through flags classes. */
3572 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3574 /* Iterate through flags in flag class. */
3575 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3578 flag_opand
= &arc_flag_operands
[flag
];
3579 /* Iterate through flags in ins to compare. */
3580 for (i
= 0; i
< nflgs
; ++i
)
3582 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3593 /* If counttrue == nflgs, then all flags have been found. */
3594 return (counttrue
== nflgs
? TRUE
: FALSE
);
3597 /* Checks if operands are in line with relaxable insn. */
3600 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3601 const expressionS
*tok
,
3604 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3607 while (*operand
!= EMPTY
)
3609 const expressionS
*epr
= &tok
[i
];
3611 if (i
!= 0 && i
>= ntok
)
3617 if (!(epr
->X_op
== O_multiply
3618 || epr
->X_op
== O_divide
3619 || epr
->X_op
== O_modulus
3620 || epr
->X_op
== O_add
3621 || epr
->X_op
== O_subtract
3622 || epr
->X_op
== O_symbol
))
3628 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3632 if (epr
->X_op
!= O_register
)
3637 if (epr
->X_op
!= O_register
)
3640 switch (epr
->X_add_number
)
3642 case 0: case 1: case 2: case 3:
3643 case 12: case 13: case 14: case 15:
3650 case REGISTER_NO_GP
:
3651 if ((epr
->X_op
!= O_register
)
3652 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3657 if (epr
->X_op
!= O_bracket
)
3662 /* Don't understand, bail out. */
3668 operand
= &ins
->operands
[i
];
3671 return (i
== ntok
? TRUE
: FALSE
);
3674 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3677 relax_insn_p (const struct arc_opcode
*opcode
,
3678 const expressionS
*tok
,
3680 const struct arc_flags
*pflags
,
3684 bfd_boolean rv
= FALSE
;
3686 /* Check the relaxation table. */
3687 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3689 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3691 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3692 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3693 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3694 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3697 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3698 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3699 sizeof (expressionS
) * ntok
);
3700 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3701 sizeof (struct arc_flags
) * nflg
);
3702 frag_now
->tc_frag_data
.nflg
= nflg
;
3703 frag_now
->tc_frag_data
.ntok
= ntok
;
3711 /* Turn an opcode description and a set of arguments into
3712 an instruction and a fixup. */
3715 assemble_insn (const struct arc_opcode
*opcode
,
3716 const expressionS
*tok
,
3718 const struct arc_flags
*pflags
,
3720 struct arc_insn
*insn
)
3722 const expressionS
*reloc_exp
= NULL
;
3724 const unsigned char *argidx
;
3727 unsigned char pcrel
= 0;
3728 bfd_boolean needGOTSymbol
;
3729 bfd_boolean has_delay_slot
= FALSE
;
3730 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3732 memset (insn
, 0, sizeof (*insn
));
3733 image
= opcode
->opcode
;
3735 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3736 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3739 /* Handle operands. */
3740 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3742 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3743 const expressionS
*t
= (const expressionS
*) 0;
3745 if ((operand
->flags
& ARC_OPERAND_FAKE
)
3746 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
3749 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3751 /* Duplicate operand, already inserted. */
3763 /* Regardless if we have a reloc or not mark the instruction
3764 limm if it is the case. */
3765 if (operand
->flags
& ARC_OPERAND_LIMM
)
3766 insn
->has_limm
= TRUE
;
3771 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3776 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3778 if (operand
->flags
& ARC_OPERAND_LIMM
)
3779 insn
->limm
= t
->X_add_number
;
3783 /* Ignore brackets. */
3787 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3791 /* Maybe register range. */
3792 if ((t
->X_add_number
== 0)
3793 && contains_register (t
->X_add_symbol
)
3794 && contains_register (t
->X_op_symbol
))
3798 regs
= get_register (t
->X_add_symbol
);
3800 regs
|= get_register (t
->X_op_symbol
);
3801 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3806 /* This operand needs a relocation. */
3807 needGOTSymbol
= FALSE
;
3812 if (opcode
->insn_class
== JUMP
)
3813 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3814 _("Unable to use @plt relocatio for insn %s"),
3816 needGOTSymbol
= TRUE
;
3817 reloc
= find_reloc ("plt", opcode
->name
,
3819 operand
->default_reloc
);
3824 needGOTSymbol
= TRUE
;
3825 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3828 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3829 if (ARC_SHORT (opcode
->mask
) || opcode
->insn_class
== JUMP
)
3830 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3831 _("Unable to use @pcl relocation for insn %s"),
3835 reloc
= find_reloc ("sda", opcode
->name
,
3837 operand
->default_reloc
);
3841 needGOTSymbol
= TRUE
;
3846 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3849 case O_tpoff9
: /*FIXME! Check for the conditionality of
3851 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3853 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3857 /* Just consider the default relocation. */
3858 reloc
= operand
->default_reloc
;
3862 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3863 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3870 /* sanity checks. */
3871 reloc_howto_type
*reloc_howto
3872 = bfd_reloc_type_lookup (stdoutput
,
3873 (bfd_reloc_code_real_type
) reloc
);
3874 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3875 if (reloc_howto
->rightshift
)
3876 reloc_bitsize
-= reloc_howto
->rightshift
;
3877 if (reloc_bitsize
!= operand
->bits
)
3879 as_bad (_("invalid relocation %s for field"),
3880 bfd_get_reloc_code_name (reloc
));
3885 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3886 as_fatal (_("too many fixups"));
3888 struct arc_fixup
*fixup
;
3889 fixup
= &insn
->fixups
[insn
->nfixups
++];
3891 fixup
->reloc
= reloc
;
3892 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3893 fixup
->pcrel
= pcrel
;
3894 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3901 for (i
= 0; i
< nflg
; i
++)
3903 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3905 /* Check if the instruction has a delay slot. */
3906 if (!strcmp (flg_operand
->name
, "d"))
3907 has_delay_slot
= TRUE
;
3909 /* There is an exceptional case when we cannot insert a flag
3910 just as it is. The .T flag must be handled in relation with
3911 the relative address. */
3912 if (!strcmp (flg_operand
->name
, "t")
3913 || !strcmp (flg_operand
->name
, "nt"))
3915 unsigned bitYoperand
= 0;
3916 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3917 if (!strcmp (flg_operand
->name
, "t"))
3918 if (!strcmp (opcode
->name
, "bbit0")
3919 || !strcmp (opcode
->name
, "bbit1"))
3920 bitYoperand
= arc_NToperand
;
3922 bitYoperand
= arc_Toperand
;
3924 if (!strcmp (opcode
->name
, "bbit0")
3925 || !strcmp (opcode
->name
, "bbit1"))
3926 bitYoperand
= arc_Toperand
;
3928 bitYoperand
= arc_NToperand
;
3930 gas_assert (reloc_exp
!= NULL
);
3931 if (reloc_exp
->X_op
== O_constant
)
3933 /* Check if we have a constant and solved it
3935 offsetT val
= reloc_exp
->X_add_number
;
3936 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3941 struct arc_fixup
*fixup
;
3943 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3944 as_fatal (_("too many fixups"));
3946 fixup
= &insn
->fixups
[insn
->nfixups
++];
3947 fixup
->exp
= *reloc_exp
;
3948 fixup
->reloc
= -bitYoperand
;
3949 fixup
->pcrel
= pcrel
;
3950 fixup
->islong
= FALSE
;
3954 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3955 << flg_operand
->shift
;
3958 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3960 /* Short instruction? */
3961 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
3965 /* Update last insn status. */
3966 arc_last_insns
[1] = arc_last_insns
[0];
3967 arc_last_insns
[0].opcode
= opcode
;
3968 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3969 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3971 /* Check if the current instruction is legally used. */
3972 if (arc_last_insns
[1].has_delay_slot
3973 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3974 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3975 _("A jump/branch instruction in delay slot."));
3979 arc_handle_align (fragS
* fragP
)
3981 if ((fragP
)->fr_type
== rs_align_code
)
3983 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3984 valueT count
= ((fragP
)->fr_next
->fr_address
3985 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3987 (fragP
)->fr_var
= 2;
3989 if (count
& 1)/* Padding in the gap till the next 2-byte
3990 boundary with 0s. */
3995 /* Writing nop_s. */
3996 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4000 /* Here we decide which fixups can be adjusted to make them relative
4001 to the beginning of the section instead of the symbol. Basically
4002 we need to make sure that the dynamic relocations are done
4003 correctly, so in some cases we force the original symbol to be
4007 tc_arc_fix_adjustable (fixS
*fixP
)
4010 /* Prevent all adjustments to global symbols. */
4011 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4013 if (S_IS_WEAK (fixP
->fx_addsy
))
4016 /* Adjust_reloc_syms doesn't know about the GOT. */
4017 switch (fixP
->fx_r_type
)
4019 case BFD_RELOC_ARC_GOTPC32
:
4020 case BFD_RELOC_ARC_PLT32
:
4021 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4022 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4023 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4024 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4034 /* Compute the reloc type of an expression EXP. */
4037 arc_check_reloc (expressionS
*exp
,
4038 bfd_reloc_code_real_type
*r_type_p
)
4040 if (*r_type_p
== BFD_RELOC_32
4041 && exp
->X_op
== O_subtract
4042 && exp
->X_op_symbol
!= NULL
4043 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4044 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4048 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4051 arc_cons_fix_new (fragS
*frag
,
4055 bfd_reloc_code_real_type r_type
)
4057 r_type
= BFD_RELOC_UNUSED
;
4062 r_type
= BFD_RELOC_8
;
4066 r_type
= BFD_RELOC_16
;
4070 r_type
= BFD_RELOC_24
;
4074 r_type
= BFD_RELOC_32
;
4075 arc_check_reloc (exp
, &r_type
);
4079 r_type
= BFD_RELOC_64
;
4083 as_bad (_("unsupported BFD relocation size %u"), size
);
4084 r_type
= BFD_RELOC_UNUSED
;
4087 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4090 /* The actual routine that checks the ZOL conditions. */
4093 check_zol (symbolS
*s
)
4095 switch (arc_mach_type
)
4097 case bfd_mach_arc_arcv2
:
4098 if (arc_target
& ARC_OPCODE_ARCv2EM
)
4101 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4102 || arc_last_insns
[1].has_delay_slot
)
4103 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4107 case bfd_mach_arc_arc600
:
4109 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4110 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4113 if (arc_last_insns
[0].has_limm
4114 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4115 as_bad (_("A jump instruction with long immediate detected at the \
4116 end of the ZOL label @%s"), S_GET_NAME (s
));
4119 case bfd_mach_arc_arc700
:
4120 if (arc_last_insns
[0].has_delay_slot
)
4121 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4130 /* If ZOL end check the last two instruction for illegals. */
4132 arc_frob_label (symbolS
* sym
)
4134 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4137 dwarf2_emit_label (sym
);
4140 /* Used because generic relaxation assumes a pc-rel value whilst we
4141 also relax instructions that use an absolute value resolved out of
4142 relative values (if that makes any sense). An example: 'add r1,
4143 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4144 but if they're in the same section we can subtract the section
4145 offset relocation which ends up in a resolved value. So if @.L2 is
4146 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4147 .text + 0x40 = 0x10. */
4149 arc_pcrel_adjust (fragS
*fragP
)
4151 if (!fragP
->tc_frag_data
.pcrel
)
4152 return fragP
->fr_address
+ fragP
->fr_fix
;
4157 /* Initialize the DWARF-2 unwind information for this procedure. */
4160 tc_arc_frame_initial_instructions (void)
4162 /* Stack pointer is register 28. */
4163 cfi_add_CFA_def_cfa_register (28);
4167 tc_arc_regname_to_dw2regnum (char *regname
)
4171 sym
= hash_find (arc_reg_hash
, regname
);
4173 return S_GET_VALUE (sym
);
4178 /* Adjust the symbol table. Delete found AUX register symbols. */
4181 arc_adjust_symtab (void)
4185 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4187 /* I've created a symbol during parsing process. Now, remove
4188 the symbol as it is found to be an AUX register. */
4189 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4190 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4193 /* Now do generic ELF adjustments. */
4194 elf_adjust_symtab ();
4198 tokenize_extinsn (extInstruction_t
*einsn
)
4202 unsigned char major_opcode
;
4203 unsigned char sub_opcode
;
4204 unsigned char syntax_class
= 0;
4205 unsigned char syntax_class_modifiers
= 0;
4206 unsigned char suffix_class
= 0;
4211 /* 1st: get instruction name. */
4212 p
= input_line_pointer
;
4213 c
= get_symbol_name (&p
);
4215 insn_name
= xstrdup (p
);
4216 restore_line_pointer (c
);
4218 /* 2nd: get major opcode. */
4219 if (*input_line_pointer
!= ',')
4221 as_bad (_("expected comma after instruction name"));
4222 ignore_rest_of_line ();
4225 input_line_pointer
++;
4226 major_opcode
= get_absolute_expression ();
4228 /* 3rd: get sub-opcode. */
4231 if (*input_line_pointer
!= ',')
4233 as_bad (_("expected comma after major opcode"));
4234 ignore_rest_of_line ();
4237 input_line_pointer
++;
4238 sub_opcode
= get_absolute_expression ();
4240 /* 4th: get suffix class. */
4243 if (*input_line_pointer
!= ',')
4245 as_bad ("expected comma after sub opcode");
4246 ignore_rest_of_line ();
4249 input_line_pointer
++;
4255 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4257 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4258 suffixclass
[i
].len
))
4260 suffix_class
|= suffixclass
[i
].attr_class
;
4261 input_line_pointer
+= suffixclass
[i
].len
;
4266 if (i
== ARRAY_SIZE (suffixclass
))
4268 as_bad ("invalid suffix class");
4269 ignore_rest_of_line ();
4275 if (*input_line_pointer
== '|')
4276 input_line_pointer
++;
4281 /* 5th: get syntax class and syntax class modifiers. */
4282 if (*input_line_pointer
!= ',')
4284 as_bad ("expected comma after suffix class");
4285 ignore_rest_of_line ();
4288 input_line_pointer
++;
4294 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4296 if (!strncmp (syntaxclassmod
[i
].name
,
4298 syntaxclassmod
[i
].len
))
4300 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4301 input_line_pointer
+= syntaxclassmod
[i
].len
;
4306 if (i
== ARRAY_SIZE (syntaxclassmod
))
4308 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4310 if (!strncmp (syntaxclass
[i
].name
,
4312 syntaxclass
[i
].len
))
4314 syntax_class
|= syntaxclass
[i
].attr_class
;
4315 input_line_pointer
+= syntaxclass
[i
].len
;
4320 if (i
== ARRAY_SIZE (syntaxclass
))
4322 as_bad ("missing syntax class");
4323 ignore_rest_of_line ();
4330 if (*input_line_pointer
== '|')
4331 input_line_pointer
++;
4336 demand_empty_rest_of_line ();
4338 einsn
->name
= insn_name
;
4339 einsn
->major
= major_opcode
;
4340 einsn
->minor
= sub_opcode
;
4341 einsn
->syntax
= syntax_class
;
4342 einsn
->modsyn
= syntax_class_modifiers
;
4343 einsn
->suffix
= suffix_class
;
4344 einsn
->flags
= syntax_class
4345 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4348 /* Generate an extension section. */
4351 arc_set_ext_seg (void)
4353 if (!arcext_section
)
4355 arcext_section
= subseg_new (".arcextmap", 0);
4356 bfd_set_section_flags (stdoutput
, arcext_section
,
4357 SEC_READONLY
| SEC_HAS_CONTENTS
);
4360 subseg_set (arcext_section
, 0);
4364 /* Create an extension instruction description in the arc extension
4365 section of the output file.
4366 The structure for an instruction is like this:
4367 [0]: Length of the record.
4368 [1]: Type of the record.
4372 [4]: Syntax (flags).
4373 [5]+ Name instruction.
4375 The sequence is terminated by an empty entry. */
4378 create_extinst_section (extInstruction_t
*einsn
)
4381 segT old_sec
= now_seg
;
4382 int old_subsec
= now_subseg
;
4384 int name_len
= strlen (einsn
->name
);
4389 *p
= 5 + name_len
+ 1;
4391 *p
= EXT_INSTRUCTION
;
4398 p
= frag_more (name_len
+ 1);
4399 strcpy (p
, einsn
->name
);
4401 subseg_set (old_sec
, old_subsec
);
4404 /* Handler .extinstruction pseudo-op. */
4407 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4409 extInstruction_t einsn
;
4410 struct arc_opcode
*arc_ext_opcodes
;
4411 const char *errmsg
= NULL
;
4412 unsigned char moplow
, mophigh
;
4414 memset (&einsn
, 0, sizeof (einsn
));
4415 tokenize_extinsn (&einsn
);
4417 /* Check if the name is already used. */
4418 if (arc_find_opcode (einsn
.name
))
4419 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4421 /* Check the opcode ranges. */
4423 mophigh
= (arc_target
& (ARC_OPCODE_ARCv2EM
4424 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4426 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4427 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4429 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4430 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4431 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4433 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4435 case ARC_SYNTAX_3OP
:
4436 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4437 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4439 case ARC_SYNTAX_2OP
:
4440 case ARC_SYNTAX_1OP
:
4441 case ARC_SYNTAX_NOP
:
4442 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4443 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4449 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, arc_target
, &errmsg
);
4450 if (arc_ext_opcodes
== NULL
)
4453 as_fatal ("%s", errmsg
);
4455 as_fatal (_("Couldn't generate extension instruction opcodes"));
4458 as_warn ("%s", errmsg
);
4460 /* Insert the extension instruction. */
4461 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4463 create_extinst_section (&einsn
);
4467 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4473 int number
, imode
= 0;
4474 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4475 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4476 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4478 /* 1st: get register name. */
4480 p
= input_line_pointer
;
4481 c
= get_symbol_name (&p
);
4484 restore_line_pointer (c
);
4486 /* 2nd: get register number. */
4489 if (*input_line_pointer
!= ',')
4491 as_bad (_("expected comma after register name"));
4492 ignore_rest_of_line ();
4496 input_line_pointer
++;
4497 number
= get_absolute_expression ();
4501 as_bad (_("negative operand number %d"), number
);
4502 ignore_rest_of_line ();
4509 /* 3rd: get register mode. */
4512 if (*input_line_pointer
!= ',')
4514 as_bad (_("expected comma after register number"));
4515 ignore_rest_of_line ();
4520 input_line_pointer
++;
4521 mode
= input_line_pointer
;
4523 if (!strncmp (mode
, "r|w", 3))
4526 input_line_pointer
+= 3;
4528 else if (!strncmp (mode
, "r", 1))
4530 imode
= ARC_REGISTER_READONLY
;
4531 input_line_pointer
+= 1;
4533 else if (strncmp (mode
, "w", 1))
4535 as_bad (_("invalid mode"));
4536 ignore_rest_of_line ();
4542 imode
= ARC_REGISTER_WRITEONLY
;
4543 input_line_pointer
+= 1;
4549 /* 4th: get core register shortcut. */
4551 if (*input_line_pointer
!= ',')
4553 as_bad (_("expected comma after register mode"));
4554 ignore_rest_of_line ();
4559 input_line_pointer
++;
4561 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4563 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4564 input_line_pointer
+= 15;
4566 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4568 as_bad (_("shortcut designator invalid"));
4569 ignore_rest_of_line ();
4575 input_line_pointer
+= 12;
4578 demand_empty_rest_of_line ();
4581 ereg
->number
= number
;
4582 ereg
->imode
= imode
;
4585 /* Create an extension register/condition description in the arc
4586 extension section of the output file.
4588 The structure for an instruction is like this:
4589 [0]: Length of the record.
4590 [1]: Type of the record.
4592 For core regs and condition codes:
4596 For auxilirary registers:
4600 The sequence is terminated by an empty entry. */
4603 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4605 segT old_sec
= now_seg
;
4606 int old_subsec
= now_subseg
;
4608 int name_len
= strlen (ereg
->name
);
4615 case EXT_CORE_REGISTER
:
4617 *p
= 3 + name_len
+ 1;
4623 case EXT_AUX_REGISTER
:
4625 *p
= 6 + name_len
+ 1;
4627 *p
= EXT_AUX_REGISTER
;
4629 *p
= (ereg
->number
>> 24) & 0xff;
4631 *p
= (ereg
->number
>> 16) & 0xff;
4633 *p
= (ereg
->number
>> 8) & 0xff;
4635 *p
= (ereg
->number
) & 0xff;
4641 p
= frag_more (name_len
+ 1);
4642 strcpy (p
, ereg
->name
);
4644 subseg_set (old_sec
, old_subsec
);
4647 /* Handler .extCoreRegister pseudo-op. */
4650 arc_extcorereg (int opertype
)
4653 struct arc_aux_reg
*auxr
;
4655 struct arc_flag_operand
*ccode
;
4657 memset (&ereg
, 0, sizeof (ereg
));
4658 tokenize_extregister (&ereg
, opertype
);
4662 case EXT_CORE_REGISTER
:
4663 /* Core register. */
4664 if (ereg
.number
> 60)
4665 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4667 declare_register (ereg
.name
, ereg
.number
);
4669 case EXT_AUX_REGISTER
:
4670 /* Auxiliary register. */
4671 auxr
= XNEW (struct arc_aux_reg
);
4672 auxr
->name
= ereg
.name
;
4673 auxr
->cpu
= arc_target
;
4674 auxr
->subclass
= NONE
;
4675 auxr
->address
= ereg
.number
;
4676 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4678 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4679 auxr
->name
, retval
);
4682 /* Condition code. */
4683 if (ereg
.number
> 31)
4684 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4686 ext_condcode
.size
++;
4687 ext_condcode
.arc_ext_condcode
=
4688 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4689 ext_condcode
.size
+ 1);
4690 if (ext_condcode
.arc_ext_condcode
== NULL
)
4691 as_fatal (_("Virtual memory exhausted"));
4693 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4694 ccode
->name
= ereg
.name
;
4695 ccode
->code
= ereg
.number
;
4698 ccode
->favail
= 0; /* not used. */
4700 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4703 as_bad (_("Unknown extension"));
4706 create_extcore_section (&ereg
, opertype
);
4710 eval: (c-set-style "gnu")