1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_v8
= ARM_FEATURE (ARM_EXT_V8
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
202 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
203 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
204 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
205 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
207 static const arm_feature_set arm_arch_any
= ARM_ANY
;
208 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
210 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
211 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
213 static const arm_feature_set arm_cext_iwmmxt2
=
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
215 static const arm_feature_set arm_cext_iwmmxt
=
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
217 static const arm_feature_set arm_cext_xscale
=
218 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
219 static const arm_feature_set arm_cext_maverick
=
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
221 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
222 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v1xd
=
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
225 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
226 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
227 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
228 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
229 static const arm_feature_set fpu_vfp_ext_d32
=
230 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
231 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
233 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
234 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
235 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
236 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static const arm_feature_set fpu_vfp_ext_armv8
=
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8
);
239 static const arm_feature_set fpu_neon_ext_armv8
=
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8
);
241 static const arm_feature_set fpu_crypto_ext_armv8
=
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8
);
244 static int mfloat_abi_opt
= -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name
[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu
.core
== arm_arch_none
.core
255 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
260 static int meabi_flags
= EABI_DEFAULT
;
262 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
265 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
270 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS
* GOT_symbol
;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode
= 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER
= 0x00,
293 IMPLICIT_IT_MODE_ARM
= 0x01,
294 IMPLICIT_IT_MODE_THUMB
= 0x02,
295 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
297 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax
= FALSE
;
324 /* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
326 before a [, which can appear as the first operand for pld. */
327 const char arm_symbol_chars
[] = "#[]";
342 enum neon_el_type type
;
346 #define NEON_MAX_TYPE_ELS 4
350 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
354 enum it_instruction_type
359 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
360 if inside, should be the last one. */
361 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
362 i.e. BKPT and NOP. */
363 IT_INSN
/* The IT insn has been parsed. */
366 /* The maximum number of operands we need. */
367 #define ARM_IT_MAX_OPERANDS 6
372 unsigned long instruction
;
376 /* "uncond_value" is set to the value in place of the conditional field in
377 unconditional versions of the instruction, or -1 if nothing is
380 struct neon_type vectype
;
381 /* This does not indicate an actual NEON instruction, only that
382 the mnemonic accepts neon-style type suffixes. */
384 /* Set to the opcode if the instruction needs relaxation.
385 Zero if the instruction is not relaxed. */
389 bfd_reloc_code_real_type type
;
394 enum it_instruction_type it_insn_type
;
400 struct neon_type_el vectype
;
401 unsigned present
: 1; /* Operand present. */
402 unsigned isreg
: 1; /* Operand was a register. */
403 unsigned immisreg
: 1; /* .imm field is a second register. */
404 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
405 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
406 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
407 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
408 instructions. This allows us to disambiguate ARM <-> vector insns. */
409 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
410 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
411 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
412 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
413 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
414 unsigned writeback
: 1; /* Operand has trailing ! */
415 unsigned preind
: 1; /* Preindexed address. */
416 unsigned postind
: 1; /* Postindexed address. */
417 unsigned negative
: 1; /* Index register was negated. */
418 unsigned shifted
: 1; /* Shift applied to operation. */
419 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
420 } operands
[ARM_IT_MAX_OPERANDS
];
423 static struct arm_it inst
;
425 #define NUM_FLOAT_VALS 8
427 const char * fp_const
[] =
429 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
432 /* Number of littlenums required to hold an extended precision number. */
433 #define MAX_LITTLENUMS 6
435 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
445 #define CP_T_X 0x00008000
446 #define CP_T_Y 0x00400000
448 #define CONDS_BIT 0x00100000
449 #define LOAD_BIT 0x00100000
451 #define DOUBLE_LOAD_FLAG 0x00000001
455 const char * template_name
;
459 #define COND_ALWAYS 0xE
463 const char * template_name
;
467 struct asm_barrier_opt
469 const char * template_name
;
471 const arm_feature_set arch
;
474 /* The bit that distinguishes CPSR and SPSR. */
475 #define SPSR_BIT (1 << 22)
477 /* The individual PSR flag bits. */
478 #define PSR_c (1 << 16)
479 #define PSR_x (1 << 17)
480 #define PSR_s (1 << 18)
481 #define PSR_f (1 << 19)
486 bfd_reloc_code_real_type reloc
;
491 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
492 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
497 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
500 /* Bits for DEFINED field in neon_typed_alias. */
501 #define NTA_HASTYPE 1
502 #define NTA_HASINDEX 2
504 struct neon_typed_alias
506 unsigned char defined
;
508 struct neon_type_el eltype
;
511 /* ARM register categories. This includes coprocessor numbers and various
512 architecture extensions' registers. */
539 /* Structure for a hash table entry for a register.
540 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
541 information which states whether a vector type or index is specified (for a
542 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
548 unsigned char builtin
;
549 struct neon_typed_alias
* neon
;
552 /* Diagnostics used when we don't get a register of the expected type. */
553 const char * const reg_expected_msgs
[] =
555 N_("ARM register expected"),
556 N_("bad or missing co-processor number"),
557 N_("co-processor register expected"),
558 N_("FPA register expected"),
559 N_("VFP single precision register expected"),
560 N_("VFP/Neon double precision register expected"),
561 N_("Neon quad precision register expected"),
562 N_("VFP single or double precision register expected"),
563 N_("Neon double or quad precision register expected"),
564 N_("VFP single, double or Neon quad precision register expected"),
565 N_("VFP system register expected"),
566 N_("Maverick MVF register expected"),
567 N_("Maverick MVD register expected"),
568 N_("Maverick MVFX register expected"),
569 N_("Maverick MVDX register expected"),
570 N_("Maverick MVAX register expected"),
571 N_("Maverick DSPSC register expected"),
572 N_("iWMMXt data register expected"),
573 N_("iWMMXt control register expected"),
574 N_("iWMMXt scalar register expected"),
575 N_("XScale accumulator register expected"),
578 /* Some well known registers that we refer to directly elsewhere. */
584 /* ARM instructions take 4bytes in the object file, Thumb instructions
590 /* Basic string to match. */
591 const char * template_name
;
593 /* Parameters to instruction. */
594 unsigned int operands
[8];
596 /* Conditional tag - see opcode_lookup. */
597 unsigned int tag
: 4;
599 /* Basic instruction code. */
600 unsigned int avalue
: 28;
602 /* Thumb-format instruction code. */
605 /* Which architecture variant provides this instruction. */
606 const arm_feature_set
* avariant
;
607 const arm_feature_set
* tvariant
;
609 /* Function to call to encode instruction in ARM format. */
610 void (* aencode
) (void);
612 /* Function to call to encode instruction in Thumb format. */
613 void (* tencode
) (void);
616 /* Defines for various bits that we will want to toggle. */
617 #define INST_IMMEDIATE 0x02000000
618 #define OFFSET_REG 0x02000000
619 #define HWOFFSET_IMM 0x00400000
620 #define SHIFT_BY_REG 0x00000010
621 #define PRE_INDEX 0x01000000
622 #define INDEX_UP 0x00800000
623 #define WRITE_BACK 0x00200000
624 #define LDM_TYPE_2_OR_3 0x00400000
625 #define CPSI_MMOD 0x00020000
627 #define LITERAL_MASK 0xf000f000
628 #define OPCODE_MASK 0xfe1fffff
629 #define V4_STR_BIT 0x00000020
631 #define T2_SUBS_PC_LR 0xf3de8f00
633 #define DATA_OP_SHIFT 21
635 #define T2_OPCODE_MASK 0xfe1fffff
636 #define T2_DATA_OP_SHIFT 21
638 #define A_COND_MASK 0xf0000000
639 #define A_PUSH_POP_OP_MASK 0x0fff0000
641 /* Opcodes for pushing/poping registers to/from the stack. */
642 #define A1_OPCODE_PUSH 0x092d0000
643 #define A2_OPCODE_PUSH 0x052d0004
644 #define A2_OPCODE_POP 0x049d0004
646 /* Codes to distinguish the arithmetic instructions. */
657 #define OPCODE_CMP 10
658 #define OPCODE_CMN 11
659 #define OPCODE_ORR 12
660 #define OPCODE_MOV 13
661 #define OPCODE_BIC 14
662 #define OPCODE_MVN 15
664 #define T2_OPCODE_AND 0
665 #define T2_OPCODE_BIC 1
666 #define T2_OPCODE_ORR 2
667 #define T2_OPCODE_ORN 3
668 #define T2_OPCODE_EOR 4
669 #define T2_OPCODE_ADD 8
670 #define T2_OPCODE_ADC 10
671 #define T2_OPCODE_SBC 11
672 #define T2_OPCODE_SUB 13
673 #define T2_OPCODE_RSB 14
675 #define T_OPCODE_MUL 0x4340
676 #define T_OPCODE_TST 0x4200
677 #define T_OPCODE_CMN 0x42c0
678 #define T_OPCODE_NEG 0x4240
679 #define T_OPCODE_MVN 0x43c0
681 #define T_OPCODE_ADD_R3 0x1800
682 #define T_OPCODE_SUB_R3 0x1a00
683 #define T_OPCODE_ADD_HI 0x4400
684 #define T_OPCODE_ADD_ST 0xb000
685 #define T_OPCODE_SUB_ST 0xb080
686 #define T_OPCODE_ADD_SP 0xa800
687 #define T_OPCODE_ADD_PC 0xa000
688 #define T_OPCODE_ADD_I8 0x3000
689 #define T_OPCODE_SUB_I8 0x3800
690 #define T_OPCODE_ADD_I3 0x1c00
691 #define T_OPCODE_SUB_I3 0x1e00
693 #define T_OPCODE_ASR_R 0x4100
694 #define T_OPCODE_LSL_R 0x4080
695 #define T_OPCODE_LSR_R 0x40c0
696 #define T_OPCODE_ROR_R 0x41c0
697 #define T_OPCODE_ASR_I 0x1000
698 #define T_OPCODE_LSL_I 0x0000
699 #define T_OPCODE_LSR_I 0x0800
701 #define T_OPCODE_MOV_I8 0x2000
702 #define T_OPCODE_CMP_I8 0x2800
703 #define T_OPCODE_CMP_LR 0x4280
704 #define T_OPCODE_MOV_HR 0x4600
705 #define T_OPCODE_CMP_HR 0x4500
707 #define T_OPCODE_LDR_PC 0x4800
708 #define T_OPCODE_LDR_SP 0x9800
709 #define T_OPCODE_STR_SP 0x9000
710 #define T_OPCODE_LDR_IW 0x6800
711 #define T_OPCODE_STR_IW 0x6000
712 #define T_OPCODE_LDR_IH 0x8800
713 #define T_OPCODE_STR_IH 0x8000
714 #define T_OPCODE_LDR_IB 0x7800
715 #define T_OPCODE_STR_IB 0x7000
716 #define T_OPCODE_LDR_RW 0x5800
717 #define T_OPCODE_STR_RW 0x5000
718 #define T_OPCODE_LDR_RH 0x5a00
719 #define T_OPCODE_STR_RH 0x5200
720 #define T_OPCODE_LDR_RB 0x5c00
721 #define T_OPCODE_STR_RB 0x5400
723 #define T_OPCODE_PUSH 0xb400
724 #define T_OPCODE_POP 0xbc00
726 #define T_OPCODE_BRANCH 0xe000
728 #define THUMB_SIZE 2 /* Size of thumb instruction. */
729 #define THUMB_PP_PC_LR 0x0100
730 #define THUMB_LOAD_BIT 0x0800
731 #define THUMB2_LOAD_BIT 0x00100000
733 #define BAD_ARGS _("bad arguments to instruction")
734 #define BAD_SP _("r13 not allowed here")
735 #define BAD_PC _("r15 not allowed here")
736 #define BAD_COND _("instruction cannot be conditional")
737 #define BAD_OVERLAP _("registers may not be the same")
738 #define BAD_HIREG _("lo register required")
739 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
740 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
741 #define BAD_BRANCH _("branch must be last instruction in IT block")
742 #define BAD_NOT_IT _("instruction not allowed in IT block")
743 #define BAD_FPU _("selected FPU does not support instruction")
744 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
745 #define BAD_IT_COND _("incorrect condition in IT block")
746 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
747 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
748 #define BAD_PC_ADDRESSING \
749 _("cannot use register index with PC-relative addressing")
750 #define BAD_PC_WRITEBACK \
751 _("cannot use writeback with PC-relative addressing")
752 #define BAD_RANGE _("branch out of range")
754 static struct hash_control
* arm_ops_hsh
;
755 static struct hash_control
* arm_cond_hsh
;
756 static struct hash_control
* arm_shift_hsh
;
757 static struct hash_control
* arm_psr_hsh
;
758 static struct hash_control
* arm_v7m_psr_hsh
;
759 static struct hash_control
* arm_reg_hsh
;
760 static struct hash_control
* arm_reloc_hsh
;
761 static struct hash_control
* arm_barrier_opt_hsh
;
763 /* Stuff needed to resolve the label ambiguity
772 symbolS
* last_label_seen
;
773 static int label_is_thumb_function_name
= FALSE
;
775 /* Literal pool structure. Held on a per-section
776 and per-sub-section basis. */
778 #define MAX_LITERAL_POOL_SIZE 1024
779 typedef struct literal_pool
781 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
782 unsigned int next_free_entry
;
788 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
790 struct literal_pool
* next
;
793 /* Pointer to a linked list of literal pools. */
794 literal_pool
* list_of_pools
= NULL
;
797 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
799 static struct current_it now_it
;
803 now_it_compatible (int cond
)
805 return (cond
& ~1) == (now_it
.cc
& ~1);
809 conditional_insn (void)
811 return inst
.cond
!= COND_ALWAYS
;
814 static int in_it_block (void);
816 static int handle_it_state (void);
818 static void force_automatic_it_block_close (void);
820 static void it_fsm_post_encode (void);
822 #define set_it_insn_type(type) \
825 inst.it_insn_type = type; \
826 if (handle_it_state () == FAIL) \
831 #define set_it_insn_type_nonvoid(type, failret) \
834 inst.it_insn_type = type; \
835 if (handle_it_state () == FAIL) \
840 #define set_it_insn_type_last() \
843 if (inst.cond == COND_ALWAYS) \
844 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
846 set_it_insn_type (INSIDE_IT_LAST_INSN); \
852 /* This array holds the chars that always start a comment. If the
853 pre-processor is disabled, these aren't very useful. */
854 const char comment_chars
[] = "@";
856 /* This array holds the chars that only start a comment at the beginning of
857 a line. If the line seems to have the form '# 123 filename'
858 .line and .file directives will appear in the pre-processed output. */
859 /* Note that input_file.c hand checks for '#' at the beginning of the
860 first line of the input file. This is because the compiler outputs
861 #NO_APP at the beginning of its output. */
862 /* Also note that comments like this one will always work. */
863 const char line_comment_chars
[] = "#";
865 const char line_separator_chars
[] = ";";
867 /* Chars that can be used to separate mant
868 from exp in floating point numbers. */
869 const char EXP_CHARS
[] = "eE";
871 /* Chars that mean this number is a floating point constant. */
875 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
877 /* Prefix characters that indicate the start of an immediate
879 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
881 /* Separator character handling. */
883 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
886 skip_past_char (char ** str
, char c
)
888 /* PR gas/14987: Allow for whitespace before the expected character. */
889 skip_whitespace (*str
);
900 #define skip_past_comma(str) skip_past_char (str, ',')
902 /* Arithmetic expressions (possibly involving symbols). */
904 /* Return TRUE if anything in the expression is a bignum. */
907 walk_no_bignums (symbolS
* sp
)
909 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
912 if (symbol_get_value_expression (sp
)->X_add_symbol
)
914 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
915 || (symbol_get_value_expression (sp
)->X_op_symbol
916 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
922 static int in_my_get_expression
= 0;
924 /* Third argument to my_get_expression. */
925 #define GE_NO_PREFIX 0
926 #define GE_IMM_PREFIX 1
927 #define GE_OPT_PREFIX 2
928 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
929 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
930 #define GE_OPT_PREFIX_BIG 3
933 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
938 /* In unified syntax, all prefixes are optional. */
940 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
945 case GE_NO_PREFIX
: break;
947 if (!is_immediate_prefix (**str
))
949 inst
.error
= _("immediate expression requires a # prefix");
955 case GE_OPT_PREFIX_BIG
:
956 if (is_immediate_prefix (**str
))
962 memset (ep
, 0, sizeof (expressionS
));
964 save_in
= input_line_pointer
;
965 input_line_pointer
= *str
;
966 in_my_get_expression
= 1;
967 seg
= expression (ep
);
968 in_my_get_expression
= 0;
970 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
972 /* We found a bad or missing expression in md_operand(). */
973 *str
= input_line_pointer
;
974 input_line_pointer
= save_in
;
975 if (inst
.error
== NULL
)
976 inst
.error
= (ep
->X_op
== O_absent
977 ? _("missing expression") :_("bad expression"));
982 if (seg
!= absolute_section
983 && seg
!= text_section
984 && seg
!= data_section
985 && seg
!= bss_section
986 && seg
!= undefined_section
)
988 inst
.error
= _("bad segment");
989 *str
= input_line_pointer
;
990 input_line_pointer
= save_in
;
997 /* Get rid of any bignums now, so that we don't generate an error for which
998 we can't establish a line number later on. Big numbers are never valid
999 in instructions, which is where this routine is always called. */
1000 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1001 && (ep
->X_op
== O_big
1002 || (ep
->X_add_symbol
1003 && (walk_no_bignums (ep
->X_add_symbol
)
1005 && walk_no_bignums (ep
->X_op_symbol
))))))
1007 inst
.error
= _("invalid constant");
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1013 *str
= input_line_pointer
;
1014 input_line_pointer
= save_in
;
1018 /* Turn a string in input_line_pointer into a floating point constant
1019 of type TYPE, and store the appropriate bytes in *LITP. The number
1020 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1021 returned, or NULL on OK.
1023 Note that fp constants aren't represent in the normal way on the ARM.
1024 In big endian mode, things are as expected. However, in little endian
1025 mode fp constants are big-endian word-wise, and little-endian byte-wise
1026 within the words. For example, (double) 1.1 in big endian mode is
1027 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1028 the byte sequence 99 99 f1 3f 9a 99 99 99.
1030 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1033 md_atof (int type
, char * litP
, int * sizeP
)
1036 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1068 return _("Unrecognized or unsupported floating point constant");
1071 t
= atof_ieee (input_line_pointer
, type
, words
);
1073 input_line_pointer
= t
;
1074 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1076 if (target_big_endian
)
1078 for (i
= 0; i
< prec
; i
++)
1080 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1081 litP
+= sizeof (LITTLENUM_TYPE
);
1086 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1087 for (i
= prec
- 1; i
>= 0; i
--)
1089 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1090 litP
+= sizeof (LITTLENUM_TYPE
);
1093 /* For a 4 byte float the order of elements in `words' is 1 0.
1094 For an 8 byte float the order is 1 0 3 2. */
1095 for (i
= 0; i
< prec
; i
+= 2)
1097 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1098 sizeof (LITTLENUM_TYPE
));
1099 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1100 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1101 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1108 /* We handle all bad expressions here, so that we can report the faulty
1109 instruction in the error message. */
1111 md_operand (expressionS
* exp
)
1113 if (in_my_get_expression
)
1114 exp
->X_op
= O_illegal
;
1117 /* Immediate values. */
1119 /* Generic immediate-value read function for use in directives.
1120 Accepts anything that 'expression' can fold to a constant.
1121 *val receives the number. */
1124 immediate_for_directive (int *val
)
1127 exp
.X_op
= O_illegal
;
1129 if (is_immediate_prefix (*input_line_pointer
))
1131 input_line_pointer
++;
1135 if (exp
.X_op
!= O_constant
)
1137 as_bad (_("expected #constant"));
1138 ignore_rest_of_line ();
1141 *val
= exp
.X_add_number
;
1146 /* Register parsing. */
1148 /* Generic register parser. CCP points to what should be the
1149 beginning of a register name. If it is indeed a valid register
1150 name, advance CCP over it and return the reg_entry structure;
1151 otherwise return NULL. Does not issue diagnostics. */
1153 static struct reg_entry
*
1154 arm_reg_parse_multi (char **ccp
)
1158 struct reg_entry
*reg
;
1160 #ifdef REGISTER_PREFIX
1161 if (*start
!= REGISTER_PREFIX
)
1165 #ifdef OPTIONAL_REGISTER_PREFIX
1166 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1171 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1176 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1178 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1188 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1189 enum arm_reg_type type
)
1191 /* Alternative syntaxes are accepted for a few register classes. */
1198 /* Generic coprocessor register names are allowed for these. */
1199 if (reg
&& reg
->type
== REG_TYPE_CN
)
1204 /* For backward compatibility, a bare number is valid here. */
1206 unsigned long processor
= strtoul (start
, ccp
, 10);
1207 if (*ccp
!= start
&& processor
<= 15)
1211 case REG_TYPE_MMXWC
:
1212 /* WC includes WCG. ??? I'm not sure this is true for all
1213 instructions that take WC registers. */
1214 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1225 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1226 return value is the register number or FAIL. */
1229 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1232 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1235 /* Do not allow a scalar (reg+index) to parse as a register. */
1236 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1239 if (reg
&& reg
->type
== type
)
1242 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1249 /* Parse a Neon type specifier. *STR should point at the leading '.'
1250 character. Does no verification at this stage that the type fits the opcode
1257 Can all be legally parsed by this function.
1259 Fills in neon_type struct pointer with parsed information, and updates STR
1260 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1261 type, FAIL if not. */
1264 parse_neon_type (struct neon_type
*type
, char **str
)
1271 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1273 enum neon_el_type thistype
= NT_untyped
;
1274 unsigned thissize
= -1u;
1281 /* Just a size without an explicit type. */
1285 switch (TOLOWER (*ptr
))
1287 case 'i': thistype
= NT_integer
; break;
1288 case 'f': thistype
= NT_float
; break;
1289 case 'p': thistype
= NT_poly
; break;
1290 case 's': thistype
= NT_signed
; break;
1291 case 'u': thistype
= NT_unsigned
; break;
1293 thistype
= NT_float
;
1298 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1304 /* .f is an abbreviation for .f32. */
1305 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1310 thissize
= strtoul (ptr
, &ptr
, 10);
1312 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1315 as_bad (_("bad size %d in type specifier"), thissize
);
1323 type
->el
[type
->elems
].type
= thistype
;
1324 type
->el
[type
->elems
].size
= thissize
;
1329 /* Empty/missing type is not a successful parse. */
1330 if (type
->elems
== 0)
1338 /* Errors may be set multiple times during parsing or bit encoding
1339 (particularly in the Neon bits), but usually the earliest error which is set
1340 will be the most meaningful. Avoid overwriting it with later (cascading)
1341 errors by calling this function. */
1344 first_error (const char *err
)
1350 /* Parse a single type, e.g. ".s32", leading period included. */
1352 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1355 struct neon_type optype
;
1359 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1361 if (optype
.elems
== 1)
1362 *vectype
= optype
.el
[0];
1365 first_error (_("only one type should be specified for operand"));
1371 first_error (_("vector type expected"));
1383 /* Special meanings for indices (which have a range of 0-7), which will fit into
1386 #define NEON_ALL_LANES 15
1387 #define NEON_INTERLEAVE_LANES 14
1389 /* Parse either a register or a scalar, with an optional type. Return the
1390 register number, and optionally fill in the actual type of the register
1391 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1392 type/index information in *TYPEINFO. */
1395 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1396 enum arm_reg_type
*rtype
,
1397 struct neon_typed_alias
*typeinfo
)
1400 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1401 struct neon_typed_alias atype
;
1402 struct neon_type_el parsetype
;
1406 atype
.eltype
.type
= NT_invtype
;
1407 atype
.eltype
.size
= -1;
1409 /* Try alternate syntax for some types of register. Note these are mutually
1410 exclusive with the Neon syntax extensions. */
1413 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1421 /* Undo polymorphism when a set of register types may be accepted. */
1422 if ((type
== REG_TYPE_NDQ
1423 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1424 || (type
== REG_TYPE_VFSD
1425 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1426 || (type
== REG_TYPE_NSDQ
1427 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1428 || reg
->type
== REG_TYPE_NQ
))
1429 || (type
== REG_TYPE_MMXWC
1430 && (reg
->type
== REG_TYPE_MMXWCG
)))
1431 type
= (enum arm_reg_type
) reg
->type
;
1433 if (type
!= reg
->type
)
1439 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1441 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1443 first_error (_("can't redefine type for operand"));
1446 atype
.defined
|= NTA_HASTYPE
;
1447 atype
.eltype
= parsetype
;
1450 if (skip_past_char (&str
, '[') == SUCCESS
)
1452 if (type
!= REG_TYPE_VFD
)
1454 first_error (_("only D registers may be indexed"));
1458 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1460 first_error (_("can't change index for operand"));
1464 atype
.defined
|= NTA_HASINDEX
;
1466 if (skip_past_char (&str
, ']') == SUCCESS
)
1467 atype
.index
= NEON_ALL_LANES
;
1472 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1474 if (exp
.X_op
!= O_constant
)
1476 first_error (_("constant expression required"));
1480 if (skip_past_char (&str
, ']') == FAIL
)
1483 atype
.index
= exp
.X_add_number
;
1498 /* Like arm_reg_parse, but allow allow the following extra features:
1499 - If RTYPE is non-zero, return the (possibly restricted) type of the
1500 register (e.g. Neon double or quad reg when either has been requested).
1501 - If this is a Neon vector type with additional type information, fill
1502 in the struct pointed to by VECTYPE (if non-NULL).
1503 This function will fault on encountering a scalar. */
1506 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1507 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1509 struct neon_typed_alias atype
;
1511 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1516 /* Do not allow regname(... to parse as a register. */
1520 /* Do not allow a scalar (reg+index) to parse as a register. */
1521 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1523 first_error (_("register operand expected, but got scalar"));
1528 *vectype
= atype
.eltype
;
1535 #define NEON_SCALAR_REG(X) ((X) >> 4)
1536 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1538 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1539 have enough information to be able to do a good job bounds-checking. So, we
1540 just do easy checks here, and do further checks later. */
1543 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1547 struct neon_typed_alias atype
;
1549 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1551 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1554 if (atype
.index
== NEON_ALL_LANES
)
1556 first_error (_("scalar must have an index"));
1559 else if (atype
.index
>= 64 / elsize
)
1561 first_error (_("scalar index out of range"));
1566 *type
= atype
.eltype
;
1570 return reg
* 16 + atype
.index
;
1573 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1576 parse_reg_list (char ** strp
)
1578 char * str
= * strp
;
1582 /* We come back here if we get ranges concatenated by '+' or '|'. */
1597 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1599 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1609 first_error (_("bad range in register list"));
1613 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1615 if (range
& (1 << i
))
1617 (_("Warning: duplicated register (r%d) in register list"),
1625 if (range
& (1 << reg
))
1626 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1628 else if (reg
<= cur_reg
)
1629 as_tsktsk (_("Warning: register range not in ascending order"));
1634 while (skip_past_comma (&str
) != FAIL
1635 || (in_range
= 1, *str
++ == '-'));
1640 first_error (_("missing `}'"));
1648 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1651 if (exp
.X_op
== O_constant
)
1653 if (exp
.X_add_number
1654 != (exp
.X_add_number
& 0x0000ffff))
1656 inst
.error
= _("invalid register mask");
1660 if ((range
& exp
.X_add_number
) != 0)
1662 int regno
= range
& exp
.X_add_number
;
1665 regno
= (1 << regno
) - 1;
1667 (_("Warning: duplicated register (r%d) in register list"),
1671 range
|= exp
.X_add_number
;
1675 if (inst
.reloc
.type
!= 0)
1677 inst
.error
= _("expression too complex");
1681 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1682 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1683 inst
.reloc
.pc_rel
= 0;
1687 if (*str
== '|' || *str
== '+')
1693 while (another_range
);
1699 /* Types of registers in a list. */
1708 /* Parse a VFP register list. If the string is invalid return FAIL.
1709 Otherwise return the number of registers, and set PBASE to the first
1710 register. Parses registers of type ETYPE.
1711 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1712 - Q registers can be used to specify pairs of D registers
1713 - { } can be omitted from around a singleton register list
1714 FIXME: This is not implemented, as it would require backtracking in
1717 This could be done (the meaning isn't really ambiguous), but doesn't
1718 fit in well with the current parsing framework.
1719 - 32 D registers may be used (also true for VFPv3).
1720 FIXME: Types are ignored in these register lists, which is probably a
1724 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1729 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1733 unsigned long mask
= 0;
1738 inst
.error
= _("expecting {");
1747 regtype
= REG_TYPE_VFS
;
1752 regtype
= REG_TYPE_VFD
;
1755 case REGLIST_NEON_D
:
1756 regtype
= REG_TYPE_NDQ
;
1760 if (etype
!= REGLIST_VFP_S
)
1762 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1763 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1767 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1770 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1777 base_reg
= max_regs
;
1781 int setmask
= 1, addregs
= 1;
1783 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1785 if (new_base
== FAIL
)
1787 first_error (_(reg_expected_msgs
[regtype
]));
1791 if (new_base
>= max_regs
)
1793 first_error (_("register out of range in list"));
1797 /* Note: a value of 2 * n is returned for the register Q<n>. */
1798 if (regtype
== REG_TYPE_NQ
)
1804 if (new_base
< base_reg
)
1805 base_reg
= new_base
;
1807 if (mask
& (setmask
<< new_base
))
1809 first_error (_("invalid register list"));
1813 if ((mask
>> new_base
) != 0 && ! warned
)
1815 as_tsktsk (_("register list not in ascending order"));
1819 mask
|= setmask
<< new_base
;
1822 if (*str
== '-') /* We have the start of a range expression */
1828 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1831 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1835 if (high_range
>= max_regs
)
1837 first_error (_("register out of range in list"));
1841 if (regtype
== REG_TYPE_NQ
)
1842 high_range
= high_range
+ 1;
1844 if (high_range
<= new_base
)
1846 inst
.error
= _("register range not in ascending order");
1850 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1852 if (mask
& (setmask
<< new_base
))
1854 inst
.error
= _("invalid register list");
1858 mask
|= setmask
<< new_base
;
1863 while (skip_past_comma (&str
) != FAIL
);
1867 /* Sanity check -- should have raised a parse error above. */
1868 if (count
== 0 || count
> max_regs
)
1873 /* Final test -- the registers must be consecutive. */
1875 for (i
= 0; i
< count
; i
++)
1877 if ((mask
& (1u << i
)) == 0)
1879 inst
.error
= _("non-contiguous register range");
1889 /* True if two alias types are the same. */
1892 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1900 if (a
->defined
!= b
->defined
)
1903 if ((a
->defined
& NTA_HASTYPE
) != 0
1904 && (a
->eltype
.type
!= b
->eltype
.type
1905 || a
->eltype
.size
!= b
->eltype
.size
))
1908 if ((a
->defined
& NTA_HASINDEX
) != 0
1909 && (a
->index
!= b
->index
))
1915 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1916 The base register is put in *PBASE.
1917 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1919 The register stride (minus one) is put in bit 4 of the return value.
1920 Bits [6:5] encode the list length (minus one).
1921 The type of the list elements is put in *ELTYPE, if non-NULL. */
1923 #define NEON_LANE(X) ((X) & 0xf)
1924 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1925 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1928 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1929 struct neon_type_el
*eltype
)
1936 int leading_brace
= 0;
1937 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1938 const char *const incr_error
= _("register stride must be 1 or 2");
1939 const char *const type_error
= _("mismatched element/structure types in list");
1940 struct neon_typed_alias firsttype
;
1942 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1947 struct neon_typed_alias atype
;
1948 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1952 first_error (_(reg_expected_msgs
[rtype
]));
1959 if (rtype
== REG_TYPE_NQ
)
1965 else if (reg_incr
== -1)
1967 reg_incr
= getreg
- base_reg
;
1968 if (reg_incr
< 1 || reg_incr
> 2)
1970 first_error (_(incr_error
));
1974 else if (getreg
!= base_reg
+ reg_incr
* count
)
1976 first_error (_(incr_error
));
1980 if (! neon_alias_types_same (&atype
, &firsttype
))
1982 first_error (_(type_error
));
1986 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1990 struct neon_typed_alias htype
;
1991 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1993 lane
= NEON_INTERLEAVE_LANES
;
1994 else if (lane
!= NEON_INTERLEAVE_LANES
)
1996 first_error (_(type_error
));
2001 else if (reg_incr
!= 1)
2003 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2007 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2010 first_error (_(reg_expected_msgs
[rtype
]));
2013 if (! neon_alias_types_same (&htype
, &firsttype
))
2015 first_error (_(type_error
));
2018 count
+= hireg
+ dregs
- getreg
;
2022 /* If we're using Q registers, we can't use [] or [n] syntax. */
2023 if (rtype
== REG_TYPE_NQ
)
2029 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2033 else if (lane
!= atype
.index
)
2035 first_error (_(type_error
));
2039 else if (lane
== -1)
2040 lane
= NEON_INTERLEAVE_LANES
;
2041 else if (lane
!= NEON_INTERLEAVE_LANES
)
2043 first_error (_(type_error
));
2048 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2050 /* No lane set by [x]. We must be interleaving structures. */
2052 lane
= NEON_INTERLEAVE_LANES
;
2055 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2056 || (count
> 1 && reg_incr
== -1))
2058 first_error (_("error parsing element/structure list"));
2062 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2064 first_error (_("expected }"));
2072 *eltype
= firsttype
.eltype
;
2077 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2080 /* Parse an explicit relocation suffix on an expression. This is
2081 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2082 arm_reloc_hsh contains no entries, so this function can only
2083 succeed if there is no () after the word. Returns -1 on error,
2084 BFD_RELOC_UNUSED if there wasn't any suffix. */
2087 parse_reloc (char **str
)
2089 struct reloc_entry
*r
;
2093 return BFD_RELOC_UNUSED
;
2098 while (*q
&& *q
!= ')' && *q
!= ',')
2103 if ((r
= (struct reloc_entry
*)
2104 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2111 /* Directives: register aliases. */
2113 static struct reg_entry
*
2114 insert_reg_alias (char *str
, unsigned number
, int type
)
2116 struct reg_entry
*new_reg
;
2119 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2121 if (new_reg
->builtin
)
2122 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2124 /* Only warn about a redefinition if it's not defined as the
2126 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2127 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2132 name
= xstrdup (str
);
2133 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2135 new_reg
->name
= name
;
2136 new_reg
->number
= number
;
2137 new_reg
->type
= type
;
2138 new_reg
->builtin
= FALSE
;
2139 new_reg
->neon
= NULL
;
2141 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2148 insert_neon_reg_alias (char *str
, int number
, int type
,
2149 struct neon_typed_alias
*atype
)
2151 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2155 first_error (_("attempt to redefine typed alias"));
2161 reg
->neon
= (struct neon_typed_alias
*)
2162 xmalloc (sizeof (struct neon_typed_alias
));
2163 *reg
->neon
= *atype
;
2167 /* Look for the .req directive. This is of the form:
2169 new_register_name .req existing_register_name
2171 If we find one, or if it looks sufficiently like one that we want to
2172 handle any error here, return TRUE. Otherwise return FALSE. */
2175 create_register_alias (char * newname
, char *p
)
2177 struct reg_entry
*old
;
2178 char *oldname
, *nbuf
;
2181 /* The input scrubber ensures that whitespace after the mnemonic is
2182 collapsed to single spaces. */
2184 if (strncmp (oldname
, " .req ", 6) != 0)
2188 if (*oldname
== '\0')
2191 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2194 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2198 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2199 the desired alias name, and p points to its end. If not, then
2200 the desired alias name is in the global original_case_string. */
2201 #ifdef TC_CASE_SENSITIVE
2204 newname
= original_case_string
;
2205 nlen
= strlen (newname
);
2208 nbuf
= (char *) alloca (nlen
+ 1);
2209 memcpy (nbuf
, newname
, nlen
);
2212 /* Create aliases under the new name as stated; an all-lowercase
2213 version of the new name; and an all-uppercase version of the new
2215 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2217 for (p
= nbuf
; *p
; p
++)
2220 if (strncmp (nbuf
, newname
, nlen
))
2222 /* If this attempt to create an additional alias fails, do not bother
2223 trying to create the all-lower case alias. We will fail and issue
2224 a second, duplicate error message. This situation arises when the
2225 programmer does something like:
2228 The second .req creates the "Foo" alias but then fails to create
2229 the artificial FOO alias because it has already been created by the
2231 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2235 for (p
= nbuf
; *p
; p
++)
2238 if (strncmp (nbuf
, newname
, nlen
))
2239 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2245 /* Create a Neon typed/indexed register alias using directives, e.g.:
2250 These typed registers can be used instead of the types specified after the
2251 Neon mnemonic, so long as all operands given have types. Types can also be
2252 specified directly, e.g.:
2253 vadd d0.s32, d1.s32, d2.s32 */
2256 create_neon_reg_alias (char *newname
, char *p
)
2258 enum arm_reg_type basetype
;
2259 struct reg_entry
*basereg
;
2260 struct reg_entry mybasereg
;
2261 struct neon_type ntype
;
2262 struct neon_typed_alias typeinfo
;
2263 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2266 typeinfo
.defined
= 0;
2267 typeinfo
.eltype
.type
= NT_invtype
;
2268 typeinfo
.eltype
.size
= -1;
2269 typeinfo
.index
= -1;
2273 if (strncmp (p
, " .dn ", 5) == 0)
2274 basetype
= REG_TYPE_VFD
;
2275 else if (strncmp (p
, " .qn ", 5) == 0)
2276 basetype
= REG_TYPE_NQ
;
2285 basereg
= arm_reg_parse_multi (&p
);
2287 if (basereg
&& basereg
->type
!= basetype
)
2289 as_bad (_("bad type for register"));
2293 if (basereg
== NULL
)
2296 /* Try parsing as an integer. */
2297 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2298 if (exp
.X_op
!= O_constant
)
2300 as_bad (_("expression must be constant"));
2303 basereg
= &mybasereg
;
2304 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2310 typeinfo
= *basereg
->neon
;
2312 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2314 /* We got a type. */
2315 if (typeinfo
.defined
& NTA_HASTYPE
)
2317 as_bad (_("can't redefine the type of a register alias"));
2321 typeinfo
.defined
|= NTA_HASTYPE
;
2322 if (ntype
.elems
!= 1)
2324 as_bad (_("you must specify a single type only"));
2327 typeinfo
.eltype
= ntype
.el
[0];
2330 if (skip_past_char (&p
, '[') == SUCCESS
)
2333 /* We got a scalar index. */
2335 if (typeinfo
.defined
& NTA_HASINDEX
)
2337 as_bad (_("can't redefine the index of a scalar alias"));
2341 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2343 if (exp
.X_op
!= O_constant
)
2345 as_bad (_("scalar index must be constant"));
2349 typeinfo
.defined
|= NTA_HASINDEX
;
2350 typeinfo
.index
= exp
.X_add_number
;
2352 if (skip_past_char (&p
, ']') == FAIL
)
2354 as_bad (_("expecting ]"));
2359 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2360 the desired alias name, and p points to its end. If not, then
2361 the desired alias name is in the global original_case_string. */
2362 #ifdef TC_CASE_SENSITIVE
2363 namelen
= nameend
- newname
;
2365 newname
= original_case_string
;
2366 namelen
= strlen (newname
);
2369 namebuf
= (char *) alloca (namelen
+ 1);
2370 strncpy (namebuf
, newname
, namelen
);
2371 namebuf
[namelen
] = '\0';
2373 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2374 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2376 /* Insert name in all uppercase. */
2377 for (p
= namebuf
; *p
; p
++)
2380 if (strncmp (namebuf
, newname
, namelen
))
2381 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2382 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2384 /* Insert name in all lowercase. */
2385 for (p
= namebuf
; *p
; p
++)
2388 if (strncmp (namebuf
, newname
, namelen
))
2389 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2390 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2395 /* Should never be called, as .req goes between the alias and the
2396 register name, not at the beginning of the line. */
2399 s_req (int a ATTRIBUTE_UNUSED
)
2401 as_bad (_("invalid syntax for .req directive"));
2405 s_dn (int a ATTRIBUTE_UNUSED
)
2407 as_bad (_("invalid syntax for .dn directive"));
2411 s_qn (int a ATTRIBUTE_UNUSED
)
2413 as_bad (_("invalid syntax for .qn directive"));
2416 /* The .unreq directive deletes an alias which was previously defined
2417 by .req. For example:
2423 s_unreq (int a ATTRIBUTE_UNUSED
)
2428 name
= input_line_pointer
;
2430 while (*input_line_pointer
!= 0
2431 && *input_line_pointer
!= ' '
2432 && *input_line_pointer
!= '\n')
2433 ++input_line_pointer
;
2435 saved_char
= *input_line_pointer
;
2436 *input_line_pointer
= 0;
2439 as_bad (_("invalid syntax for .unreq directive"));
2442 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2446 as_bad (_("unknown register alias '%s'"), name
);
2447 else if (reg
->builtin
)
2448 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2455 hash_delete (arm_reg_hsh
, name
, FALSE
);
2456 free ((char *) reg
->name
);
2461 /* Also locate the all upper case and all lower case versions.
2462 Do not complain if we cannot find one or the other as it
2463 was probably deleted above. */
2465 nbuf
= strdup (name
);
2466 for (p
= nbuf
; *p
; p
++)
2468 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2471 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2472 free ((char *) reg
->name
);
2478 for (p
= nbuf
; *p
; p
++)
2480 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2483 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2484 free ((char *) reg
->name
);
2494 *input_line_pointer
= saved_char
;
2495 demand_empty_rest_of_line ();
2498 /* Directives: Instruction set selection. */
2501 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2502 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2503 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2504 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2506 /* Create a new mapping symbol for the transition to STATE. */
2509 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2512 const char * symname
;
2519 type
= BSF_NO_FLAGS
;
2523 type
= BSF_NO_FLAGS
;
2527 type
= BSF_NO_FLAGS
;
2533 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2534 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2539 THUMB_SET_FUNC (symbolP
, 0);
2540 ARM_SET_THUMB (symbolP
, 0);
2541 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2545 THUMB_SET_FUNC (symbolP
, 1);
2546 ARM_SET_THUMB (symbolP
, 1);
2547 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2555 /* Save the mapping symbols for future reference. Also check that
2556 we do not place two mapping symbols at the same offset within a
2557 frag. We'll handle overlap between frags in
2558 check_mapping_symbols.
2560 If .fill or other data filling directive generates zero sized data,
2561 the mapping symbol for the following code will have the same value
2562 as the one generated for the data filling directive. In this case,
2563 we replace the old symbol with the new one at the same address. */
2566 if (frag
->tc_frag_data
.first_map
!= NULL
)
2568 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2569 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2571 frag
->tc_frag_data
.first_map
= symbolP
;
2573 if (frag
->tc_frag_data
.last_map
!= NULL
)
2575 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2576 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2577 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2579 frag
->tc_frag_data
.last_map
= symbolP
;
2582 /* We must sometimes convert a region marked as code to data during
2583 code alignment, if an odd number of bytes have to be padded. The
2584 code mapping symbol is pushed to an aligned address. */
2587 insert_data_mapping_symbol (enum mstate state
,
2588 valueT value
, fragS
*frag
, offsetT bytes
)
2590 /* If there was already a mapping symbol, remove it. */
2591 if (frag
->tc_frag_data
.last_map
!= NULL
2592 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2594 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2598 know (frag
->tc_frag_data
.first_map
== symp
);
2599 frag
->tc_frag_data
.first_map
= NULL
;
2601 frag
->tc_frag_data
.last_map
= NULL
;
2602 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2605 make_mapping_symbol (MAP_DATA
, value
, frag
);
2606 make_mapping_symbol (state
, value
+ bytes
, frag
);
2609 static void mapping_state_2 (enum mstate state
, int max_chars
);
2611 /* Set the mapping state to STATE. Only call this when about to
2612 emit some STATE bytes to the file. */
2615 mapping_state (enum mstate state
)
2617 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2619 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2621 if (mapstate
== state
)
2622 /* The mapping symbol has already been emitted.
2623 There is nothing else to do. */
2626 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2628 All ARM instructions require 4-byte alignment.
2629 (Almost) all Thumb instructions require 2-byte alignment.
2631 When emitting instructions into any section, mark the section
2634 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2635 but themselves require 2-byte alignment; this applies to some
2636 PC- relative forms. However, these cases will invovle implicit
2637 literal pool generation or an explicit .align >=2, both of
2638 which will cause the section to me marked with sufficient
2639 alignment. Thus, we don't handle those cases here. */
2640 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2642 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2643 /* This case will be evaluated later in the next else. */
2645 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2646 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2648 /* Only add the symbol if the offset is > 0:
2649 if we're at the first frag, check it's size > 0;
2650 if we're not at the first frag, then for sure
2651 the offset is > 0. */
2652 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2653 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2656 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2659 mapping_state_2 (state
, 0);
2663 /* Same as mapping_state, but MAX_CHARS bytes have already been
2664 allocated. Put the mapping symbol that far back. */
2667 mapping_state_2 (enum mstate state
, int max_chars
)
2669 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2671 if (!SEG_NORMAL (now_seg
))
2674 if (mapstate
== state
)
2675 /* The mapping symbol has already been emitted.
2676 There is nothing else to do. */
2679 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2680 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2683 #define mapping_state(x) ((void)0)
2684 #define mapping_state_2(x, y) ((void)0)
2687 /* Find the real, Thumb encoded start of a Thumb function. */
2691 find_real_start (symbolS
* symbolP
)
2694 const char * name
= S_GET_NAME (symbolP
);
2695 symbolS
* new_target
;
2697 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2698 #define STUB_NAME ".real_start_of"
2703 /* The compiler may generate BL instructions to local labels because
2704 it needs to perform a branch to a far away location. These labels
2705 do not have a corresponding ".real_start_of" label. We check
2706 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2707 the ".real_start_of" convention for nonlocal branches. */
2708 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2711 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2712 new_target
= symbol_find (real_start
);
2714 if (new_target
== NULL
)
2716 as_warn (_("Failed to find real start of function: %s\n"), name
);
2717 new_target
= symbolP
;
2725 opcode_select (int width
)
2732 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2733 as_bad (_("selected processor does not support THUMB opcodes"));
2736 /* No need to force the alignment, since we will have been
2737 coming from ARM mode, which is word-aligned. */
2738 record_alignment (now_seg
, 1);
2745 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2746 as_bad (_("selected processor does not support ARM opcodes"));
2751 frag_align (2, 0, 0);
2753 record_alignment (now_seg
, 1);
2758 as_bad (_("invalid instruction size selected (%d)"), width
);
2763 s_arm (int ignore ATTRIBUTE_UNUSED
)
2766 demand_empty_rest_of_line ();
2770 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2773 demand_empty_rest_of_line ();
2777 s_code (int unused ATTRIBUTE_UNUSED
)
2781 temp
= get_absolute_expression ();
2786 opcode_select (temp
);
2790 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2795 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2797 /* If we are not already in thumb mode go into it, EVEN if
2798 the target processor does not support thumb instructions.
2799 This is used by gcc/config/arm/lib1funcs.asm for example
2800 to compile interworking support functions even if the
2801 target processor should not support interworking. */
2805 record_alignment (now_seg
, 1);
2808 demand_empty_rest_of_line ();
2812 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2816 /* The following label is the name/address of the start of a Thumb function.
2817 We need to know this for the interworking support. */
2818 label_is_thumb_function_name
= TRUE
;
2821 /* Perform a .set directive, but also mark the alias as
2822 being a thumb function. */
2825 s_thumb_set (int equiv
)
2827 /* XXX the following is a duplicate of the code for s_set() in read.c
2828 We cannot just call that code as we need to get at the symbol that
2835 /* Especial apologies for the random logic:
2836 This just grew, and could be parsed much more simply!
2838 name
= input_line_pointer
;
2839 delim
= get_symbol_end ();
2840 end_name
= input_line_pointer
;
2843 if (*input_line_pointer
!= ',')
2846 as_bad (_("expected comma after name \"%s\""), name
);
2848 ignore_rest_of_line ();
2852 input_line_pointer
++;
2855 if (name
[0] == '.' && name
[1] == '\0')
2857 /* XXX - this should not happen to .thumb_set. */
2861 if ((symbolP
= symbol_find (name
)) == NULL
2862 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2865 /* When doing symbol listings, play games with dummy fragments living
2866 outside the normal fragment chain to record the file and line info
2868 if (listing
& LISTING_SYMBOLS
)
2870 extern struct list_info_struct
* listing_tail
;
2871 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2873 memset (dummy_frag
, 0, sizeof (fragS
));
2874 dummy_frag
->fr_type
= rs_fill
;
2875 dummy_frag
->line
= listing_tail
;
2876 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2877 dummy_frag
->fr_symbol
= symbolP
;
2881 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2884 /* "set" symbols are local unless otherwise specified. */
2885 SF_SET_LOCAL (symbolP
);
2886 #endif /* OBJ_COFF */
2887 } /* Make a new symbol. */
2889 symbol_table_insert (symbolP
);
2894 && S_IS_DEFINED (symbolP
)
2895 && S_GET_SEGMENT (symbolP
) != reg_section
)
2896 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2898 pseudo_set (symbolP
);
2900 demand_empty_rest_of_line ();
2902 /* XXX Now we come to the Thumb specific bit of code. */
2904 THUMB_SET_FUNC (symbolP
, 1);
2905 ARM_SET_THUMB (symbolP
, 1);
2906 #if defined OBJ_ELF || defined OBJ_COFF
2907 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2911 /* Directives: Mode selection. */
2913 /* .syntax [unified|divided] - choose the new unified syntax
2914 (same for Arm and Thumb encoding, modulo slight differences in what
2915 can be represented) or the old divergent syntax for each mode. */
2917 s_syntax (int unused ATTRIBUTE_UNUSED
)
2921 name
= input_line_pointer
;
2922 delim
= get_symbol_end ();
2924 if (!strcasecmp (name
, "unified"))
2925 unified_syntax
= TRUE
;
2926 else if (!strcasecmp (name
, "divided"))
2927 unified_syntax
= FALSE
;
2930 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2933 *input_line_pointer
= delim
;
2934 demand_empty_rest_of_line ();
2937 /* Directives: sectioning and alignment. */
2939 /* Same as s_align_ptwo but align 0 => align 2. */
2942 s_align (int unused ATTRIBUTE_UNUSED
)
2947 long max_alignment
= 15;
2949 temp
= get_absolute_expression ();
2950 if (temp
> max_alignment
)
2951 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2954 as_bad (_("alignment negative. 0 assumed."));
2958 if (*input_line_pointer
== ',')
2960 input_line_pointer
++;
2961 temp_fill
= get_absolute_expression ();
2973 /* Only make a frag if we HAVE to. */
2974 if (temp
&& !need_pass_2
)
2976 if (!fill_p
&& subseg_text_p (now_seg
))
2977 frag_align_code (temp
, 0);
2979 frag_align (temp
, (int) temp_fill
, 0);
2981 demand_empty_rest_of_line ();
2983 record_alignment (now_seg
, temp
);
2987 s_bss (int ignore ATTRIBUTE_UNUSED
)
2989 /* We don't support putting frags in the BSS segment, we fake it by
2990 marking in_bss, then looking at s_skip for clues. */
2991 subseg_set (bss_section
, 0);
2992 demand_empty_rest_of_line ();
2994 #ifdef md_elf_section_change_hook
2995 md_elf_section_change_hook ();
3000 s_even (int ignore ATTRIBUTE_UNUSED
)
3002 /* Never make frag if expect extra pass. */
3004 frag_align (1, 0, 0);
3006 record_alignment (now_seg
, 1);
3008 demand_empty_rest_of_line ();
3011 /* Directives: Literal pools. */
3013 static literal_pool
*
3014 find_literal_pool (void)
3016 literal_pool
* pool
;
3018 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3020 if (pool
->section
== now_seg
3021 && pool
->sub_section
== now_subseg
)
3028 static literal_pool
*
3029 find_or_make_literal_pool (void)
3031 /* Next literal pool ID number. */
3032 static unsigned int latest_pool_num
= 1;
3033 literal_pool
* pool
;
3035 pool
= find_literal_pool ();
3039 /* Create a new pool. */
3040 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3044 pool
->next_free_entry
= 0;
3045 pool
->section
= now_seg
;
3046 pool
->sub_section
= now_subseg
;
3047 pool
->next
= list_of_pools
;
3048 pool
->symbol
= NULL
;
3050 /* Add it to the list. */
3051 list_of_pools
= pool
;
3054 /* New pools, and emptied pools, will have a NULL symbol. */
3055 if (pool
->symbol
== NULL
)
3057 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3058 (valueT
) 0, &zero_address_frag
);
3059 pool
->id
= latest_pool_num
++;
3066 /* Add the literal in the global 'inst'
3067 structure to the relevant literal pool. */
3070 add_to_lit_pool (void)
3072 literal_pool
* pool
;
3075 pool
= find_or_make_literal_pool ();
3077 /* Check if this literal value is already in the pool. */
3078 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3080 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3081 && (inst
.reloc
.exp
.X_op
== O_constant
)
3082 && (pool
->literals
[entry
].X_add_number
3083 == inst
.reloc
.exp
.X_add_number
)
3084 && (pool
->literals
[entry
].X_unsigned
3085 == inst
.reloc
.exp
.X_unsigned
))
3088 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3089 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3090 && (pool
->literals
[entry
].X_add_number
3091 == inst
.reloc
.exp
.X_add_number
)
3092 && (pool
->literals
[entry
].X_add_symbol
3093 == inst
.reloc
.exp
.X_add_symbol
)
3094 && (pool
->literals
[entry
].X_op_symbol
3095 == inst
.reloc
.exp
.X_op_symbol
))
3099 /* Do we need to create a new entry? */
3100 if (entry
== pool
->next_free_entry
)
3102 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3104 inst
.error
= _("literal pool overflow");
3108 pool
->literals
[entry
] = inst
.reloc
.exp
;
3110 /* PR ld/12974: Record the location of the first source line to reference
3111 this entry in the literal pool. If it turns out during linking that the
3112 symbol does not exist we will be able to give an accurate line number for
3113 the (first use of the) missing reference. */
3114 if (debug_type
== DEBUG_DWARF2
)
3115 dwarf2_where (pool
->locs
+ entry
);
3117 pool
->next_free_entry
+= 1;
3120 inst
.reloc
.exp
.X_op
= O_symbol
;
3121 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3122 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3127 /* Can't use symbol_new here, so have to create a symbol and then at
3128 a later date assign it a value. Thats what these functions do. */
3131 symbol_locate (symbolS
* symbolP
,
3132 const char * name
, /* It is copied, the caller can modify. */
3133 segT segment
, /* Segment identifier (SEG_<something>). */
3134 valueT valu
, /* Symbol value. */
3135 fragS
* frag
) /* Associated fragment. */
3137 unsigned int name_length
;
3138 char * preserved_copy_of_name
;
3140 name_length
= strlen (name
) + 1; /* +1 for \0. */
3141 obstack_grow (¬es
, name
, name_length
);
3142 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3144 #ifdef tc_canonicalize_symbol_name
3145 preserved_copy_of_name
=
3146 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3149 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3151 S_SET_SEGMENT (symbolP
, segment
);
3152 S_SET_VALUE (symbolP
, valu
);
3153 symbol_clear_list_pointers (symbolP
);
3155 symbol_set_frag (symbolP
, frag
);
3157 /* Link to end of symbol chain. */
3159 extern int symbol_table_frozen
;
3161 if (symbol_table_frozen
)
3165 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3167 obj_symbol_new_hook (symbolP
);
3169 #ifdef tc_symbol_new_hook
3170 tc_symbol_new_hook (symbolP
);
3174 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3175 #endif /* DEBUG_SYMS */
3180 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3183 literal_pool
* pool
;
3186 pool
= find_literal_pool ();
3188 || pool
->symbol
== NULL
3189 || pool
->next_free_entry
== 0)
3192 mapping_state (MAP_DATA
);
3194 /* Align pool as you have word accesses.
3195 Only make a frag if we have to. */
3197 frag_align (2, 0, 0);
3199 record_alignment (now_seg
, 2);
3201 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3203 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3204 (valueT
) frag_now_fix (), frag_now
);
3205 symbol_table_insert (pool
->symbol
);
3207 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3209 #if defined OBJ_COFF || defined OBJ_ELF
3210 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3213 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3216 if (debug_type
== DEBUG_DWARF2
)
3217 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3219 /* First output the expression in the instruction to the pool. */
3220 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3223 /* Mark the pool as empty. */
3224 pool
->next_free_entry
= 0;
3225 pool
->symbol
= NULL
;
3229 /* Forward declarations for functions below, in the MD interface
3231 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3232 static valueT
create_unwind_entry (int);
3233 static void start_unwind_section (const segT
, int);
3234 static void add_unwind_opcode (valueT
, int);
3235 static void flush_pending_unwind (void);
3237 /* Directives: Data. */
3240 s_arm_elf_cons (int nbytes
)
3244 #ifdef md_flush_pending_output
3245 md_flush_pending_output ();
3248 if (is_it_end_of_statement ())
3250 demand_empty_rest_of_line ();
3254 #ifdef md_cons_align
3255 md_cons_align (nbytes
);
3258 mapping_state (MAP_DATA
);
3262 char *base
= input_line_pointer
;
3266 if (exp
.X_op
!= O_symbol
)
3267 emit_expr (&exp
, (unsigned int) nbytes
);
3270 char *before_reloc
= input_line_pointer
;
3271 reloc
= parse_reloc (&input_line_pointer
);
3274 as_bad (_("unrecognized relocation suffix"));
3275 ignore_rest_of_line ();
3278 else if (reloc
== BFD_RELOC_UNUSED
)
3279 emit_expr (&exp
, (unsigned int) nbytes
);
3282 reloc_howto_type
*howto
= (reloc_howto_type
*)
3283 bfd_reloc_type_lookup (stdoutput
,
3284 (bfd_reloc_code_real_type
) reloc
);
3285 int size
= bfd_get_reloc_size (howto
);
3287 if (reloc
== BFD_RELOC_ARM_PLT32
)
3289 as_bad (_("(plt) is only valid on branch targets"));
3290 reloc
= BFD_RELOC_UNUSED
;
3295 as_bad (_("%s relocations do not fit in %d bytes"),
3296 howto
->name
, nbytes
);
3299 /* We've parsed an expression stopping at O_symbol.
3300 But there may be more expression left now that we
3301 have parsed the relocation marker. Parse it again.
3302 XXX Surely there is a cleaner way to do this. */
3303 char *p
= input_line_pointer
;
3305 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3306 memcpy (save_buf
, base
, input_line_pointer
- base
);
3307 memmove (base
+ (input_line_pointer
- before_reloc
),
3308 base
, before_reloc
- base
);
3310 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3312 memcpy (base
, save_buf
, p
- base
);
3314 offset
= nbytes
- size
;
3315 p
= frag_more ((int) nbytes
);
3316 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3317 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3322 while (*input_line_pointer
++ == ',');
3324 /* Put terminator back into stream. */
3325 input_line_pointer
--;
3326 demand_empty_rest_of_line ();
3329 /* Emit an expression containing a 32-bit thumb instruction.
3330 Implementation based on put_thumb32_insn. */
3333 emit_thumb32_expr (expressionS
* exp
)
3335 expressionS exp_high
= *exp
;
3337 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3338 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3339 exp
->X_add_number
&= 0xffff;
3340 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3343 /* Guess the instruction size based on the opcode. */
3346 thumb_insn_size (int opcode
)
3348 if ((unsigned int) opcode
< 0xe800u
)
3350 else if ((unsigned int) opcode
>= 0xe8000000u
)
3357 emit_insn (expressionS
*exp
, int nbytes
)
3361 if (exp
->X_op
== O_constant
)
3366 size
= thumb_insn_size (exp
->X_add_number
);
3370 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3372 as_bad (_(".inst.n operand too big. "\
3373 "Use .inst.w instead"));
3378 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3379 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3381 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3383 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3384 emit_thumb32_expr (exp
);
3386 emit_expr (exp
, (unsigned int) size
);
3388 it_fsm_post_encode ();
3392 as_bad (_("cannot determine Thumb instruction size. " \
3393 "Use .inst.n/.inst.w instead"));
3396 as_bad (_("constant expression required"));
3401 /* Like s_arm_elf_cons but do not use md_cons_align and
3402 set the mapping state to MAP_ARM/MAP_THUMB. */
3405 s_arm_elf_inst (int nbytes
)
3407 if (is_it_end_of_statement ())
3409 demand_empty_rest_of_line ();
3413 /* Calling mapping_state () here will not change ARM/THUMB,
3414 but will ensure not to be in DATA state. */
3417 mapping_state (MAP_THUMB
);
3422 as_bad (_("width suffixes are invalid in ARM mode"));
3423 ignore_rest_of_line ();
3429 mapping_state (MAP_ARM
);
3438 if (! emit_insn (& exp
, nbytes
))
3440 ignore_rest_of_line ();
3444 while (*input_line_pointer
++ == ',');
3446 /* Put terminator back into stream. */
3447 input_line_pointer
--;
3448 demand_empty_rest_of_line ();
3451 /* Parse a .rel31 directive. */
3454 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3461 if (*input_line_pointer
== '1')
3462 highbit
= 0x80000000;
3463 else if (*input_line_pointer
!= '0')
3464 as_bad (_("expected 0 or 1"));
3466 input_line_pointer
++;
3467 if (*input_line_pointer
!= ',')
3468 as_bad (_("missing comma"));
3469 input_line_pointer
++;
3471 #ifdef md_flush_pending_output
3472 md_flush_pending_output ();
3475 #ifdef md_cons_align
3479 mapping_state (MAP_DATA
);
3484 md_number_to_chars (p
, highbit
, 4);
3485 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3486 BFD_RELOC_ARM_PREL31
);
3488 demand_empty_rest_of_line ();
3491 /* Directives: AEABI stack-unwind tables. */
3493 /* Parse an unwind_fnstart directive. Simply records the current location. */
3496 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3498 demand_empty_rest_of_line ();
3499 if (unwind
.proc_start
)
3501 as_bad (_("duplicate .fnstart directive"));
3505 /* Mark the start of the function. */
3506 unwind
.proc_start
= expr_build_dot ();
3508 /* Reset the rest of the unwind info. */
3509 unwind
.opcode_count
= 0;
3510 unwind
.table_entry
= NULL
;
3511 unwind
.personality_routine
= NULL
;
3512 unwind
.personality_index
= -1;
3513 unwind
.frame_size
= 0;
3514 unwind
.fp_offset
= 0;
3515 unwind
.fp_reg
= REG_SP
;
3517 unwind
.sp_restored
= 0;
3521 /* Parse a handlerdata directive. Creates the exception handling table entry
3522 for the function. */
3525 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3527 demand_empty_rest_of_line ();
3528 if (!unwind
.proc_start
)
3529 as_bad (MISSING_FNSTART
);
3531 if (unwind
.table_entry
)
3532 as_bad (_("duplicate .handlerdata directive"));
3534 create_unwind_entry (1);
3537 /* Parse an unwind_fnend directive. Generates the index table entry. */
3540 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3545 unsigned int marked_pr_dependency
;
3547 demand_empty_rest_of_line ();
3549 if (!unwind
.proc_start
)
3551 as_bad (_(".fnend directive without .fnstart"));
3555 /* Add eh table entry. */
3556 if (unwind
.table_entry
== NULL
)
3557 val
= create_unwind_entry (0);
3561 /* Add index table entry. This is two words. */
3562 start_unwind_section (unwind
.saved_seg
, 1);
3563 frag_align (2, 0, 0);
3564 record_alignment (now_seg
, 2);
3566 ptr
= frag_more (8);
3568 where
= frag_now_fix () - 8;
3570 /* Self relative offset of the function start. */
3571 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3572 BFD_RELOC_ARM_PREL31
);
3574 /* Indicate dependency on EHABI-defined personality routines to the
3575 linker, if it hasn't been done already. */
3576 marked_pr_dependency
3577 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3578 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3579 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3581 static const char *const name
[] =
3583 "__aeabi_unwind_cpp_pr0",
3584 "__aeabi_unwind_cpp_pr1",
3585 "__aeabi_unwind_cpp_pr2"
3587 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3588 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3589 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3590 |= 1 << unwind
.personality_index
;
3594 /* Inline exception table entry. */
3595 md_number_to_chars (ptr
+ 4, val
, 4);
3597 /* Self relative offset of the table entry. */
3598 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3599 BFD_RELOC_ARM_PREL31
);
3601 /* Restore the original section. */
3602 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3604 unwind
.proc_start
= NULL
;
3608 /* Parse an unwind_cantunwind directive. */
3611 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3613 demand_empty_rest_of_line ();
3614 if (!unwind
.proc_start
)
3615 as_bad (MISSING_FNSTART
);
3617 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3618 as_bad (_("personality routine specified for cantunwind frame"));
3620 unwind
.personality_index
= -2;
3624 /* Parse a personalityindex directive. */
3627 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3631 if (!unwind
.proc_start
)
3632 as_bad (MISSING_FNSTART
);
3634 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3635 as_bad (_("duplicate .personalityindex directive"));
3639 if (exp
.X_op
!= O_constant
3640 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3642 as_bad (_("bad personality routine number"));
3643 ignore_rest_of_line ();
3647 unwind
.personality_index
= exp
.X_add_number
;
3649 demand_empty_rest_of_line ();
3653 /* Parse a personality directive. */
3656 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3660 if (!unwind
.proc_start
)
3661 as_bad (MISSING_FNSTART
);
3663 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3664 as_bad (_("duplicate .personality directive"));
3666 name
= input_line_pointer
;
3667 c
= get_symbol_end ();
3668 p
= input_line_pointer
;
3669 unwind
.personality_routine
= symbol_find_or_make (name
);
3671 demand_empty_rest_of_line ();
3675 /* Parse a directive saving core registers. */
3678 s_arm_unwind_save_core (void)
3684 range
= parse_reg_list (&input_line_pointer
);
3687 as_bad (_("expected register list"));
3688 ignore_rest_of_line ();
3692 demand_empty_rest_of_line ();
3694 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3695 into .unwind_save {..., sp...}. We aren't bothered about the value of
3696 ip because it is clobbered by calls. */
3697 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3698 && (range
& 0x3000) == 0x1000)
3700 unwind
.opcode_count
--;
3701 unwind
.sp_restored
= 0;
3702 range
= (range
| 0x2000) & ~0x1000;
3703 unwind
.pending_offset
= 0;
3709 /* See if we can use the short opcodes. These pop a block of up to 8
3710 registers starting with r4, plus maybe r14. */
3711 for (n
= 0; n
< 8; n
++)
3713 /* Break at the first non-saved register. */
3714 if ((range
& (1 << (n
+ 4))) == 0)
3717 /* See if there are any other bits set. */
3718 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3720 /* Use the long form. */
3721 op
= 0x8000 | ((range
>> 4) & 0xfff);
3722 add_unwind_opcode (op
, 2);
3726 /* Use the short form. */
3728 op
= 0xa8; /* Pop r14. */
3730 op
= 0xa0; /* Do not pop r14. */
3732 add_unwind_opcode (op
, 1);
3739 op
= 0xb100 | (range
& 0xf);
3740 add_unwind_opcode (op
, 2);
3743 /* Record the number of bytes pushed. */
3744 for (n
= 0; n
< 16; n
++)
3746 if (range
& (1 << n
))
3747 unwind
.frame_size
+= 4;
3752 /* Parse a directive saving FPA registers. */
3755 s_arm_unwind_save_fpa (int reg
)
3761 /* Get Number of registers to transfer. */
3762 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3765 exp
.X_op
= O_illegal
;
3767 if (exp
.X_op
!= O_constant
)
3769 as_bad (_("expected , <constant>"));
3770 ignore_rest_of_line ();
3774 num_regs
= exp
.X_add_number
;
3776 if (num_regs
< 1 || num_regs
> 4)
3778 as_bad (_("number of registers must be in the range [1:4]"));
3779 ignore_rest_of_line ();
3783 demand_empty_rest_of_line ();
3788 op
= 0xb4 | (num_regs
- 1);
3789 add_unwind_opcode (op
, 1);
3794 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3795 add_unwind_opcode (op
, 2);
3797 unwind
.frame_size
+= num_regs
* 12;
3801 /* Parse a directive saving VFP registers for ARMv6 and above. */
3804 s_arm_unwind_save_vfp_armv6 (void)
3809 int num_vfpv3_regs
= 0;
3810 int num_regs_below_16
;
3812 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3815 as_bad (_("expected register list"));
3816 ignore_rest_of_line ();
3820 demand_empty_rest_of_line ();
3822 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3823 than FSTMX/FLDMX-style ones). */
3825 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3827 num_vfpv3_regs
= count
;
3828 else if (start
+ count
> 16)
3829 num_vfpv3_regs
= start
+ count
- 16;
3831 if (num_vfpv3_regs
> 0)
3833 int start_offset
= start
> 16 ? start
- 16 : 0;
3834 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3835 add_unwind_opcode (op
, 2);
3838 /* Generate opcode for registers numbered in the range 0 .. 15. */
3839 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3840 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3841 if (num_regs_below_16
> 0)
3843 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3844 add_unwind_opcode (op
, 2);
3847 unwind
.frame_size
+= count
* 8;
3851 /* Parse a directive saving VFP registers for pre-ARMv6. */
3854 s_arm_unwind_save_vfp (void)
3860 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3863 as_bad (_("expected register list"));
3864 ignore_rest_of_line ();
3868 demand_empty_rest_of_line ();
3873 op
= 0xb8 | (count
- 1);
3874 add_unwind_opcode (op
, 1);
3879 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3880 add_unwind_opcode (op
, 2);
3882 unwind
.frame_size
+= count
* 8 + 4;
3886 /* Parse a directive saving iWMMXt data registers. */
3889 s_arm_unwind_save_mmxwr (void)
3897 if (*input_line_pointer
== '{')
3898 input_line_pointer
++;
3902 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3906 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3911 as_tsktsk (_("register list not in ascending order"));
3914 if (*input_line_pointer
== '-')
3916 input_line_pointer
++;
3917 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3920 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3923 else if (reg
>= hi_reg
)
3925 as_bad (_("bad register range"));
3928 for (; reg
< hi_reg
; reg
++)
3932 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3934 if (*input_line_pointer
== '}')
3935 input_line_pointer
++;
3937 demand_empty_rest_of_line ();
3939 /* Generate any deferred opcodes because we're going to be looking at
3941 flush_pending_unwind ();
3943 for (i
= 0; i
< 16; i
++)
3945 if (mask
& (1 << i
))
3946 unwind
.frame_size
+= 8;
3949 /* Attempt to combine with a previous opcode. We do this because gcc
3950 likes to output separate unwind directives for a single block of
3952 if (unwind
.opcode_count
> 0)
3954 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3955 if ((i
& 0xf8) == 0xc0)
3958 /* Only merge if the blocks are contiguous. */
3961 if ((mask
& 0xfe00) == (1 << 9))
3963 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3964 unwind
.opcode_count
--;
3967 else if (i
== 6 && unwind
.opcode_count
>= 2)
3969 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3973 op
= 0xffff << (reg
- 1);
3975 && ((mask
& op
) == (1u << (reg
- 1))))
3977 op
= (1 << (reg
+ i
+ 1)) - 1;
3978 op
&= ~((1 << reg
) - 1);
3980 unwind
.opcode_count
-= 2;
3987 /* We want to generate opcodes in the order the registers have been
3988 saved, ie. descending order. */
3989 for (reg
= 15; reg
>= -1; reg
--)
3991 /* Save registers in blocks. */
3993 || !(mask
& (1 << reg
)))
3995 /* We found an unsaved reg. Generate opcodes to save the
4002 op
= 0xc0 | (hi_reg
- 10);
4003 add_unwind_opcode (op
, 1);
4008 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4009 add_unwind_opcode (op
, 2);
4018 ignore_rest_of_line ();
4022 s_arm_unwind_save_mmxwcg (void)
4029 if (*input_line_pointer
== '{')
4030 input_line_pointer
++;
4034 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4038 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4044 as_tsktsk (_("register list not in ascending order"));
4047 if (*input_line_pointer
== '-')
4049 input_line_pointer
++;
4050 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4053 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4056 else if (reg
>= hi_reg
)
4058 as_bad (_("bad register range"));
4061 for (; reg
< hi_reg
; reg
++)
4065 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4067 if (*input_line_pointer
== '}')
4068 input_line_pointer
++;
4070 demand_empty_rest_of_line ();
4072 /* Generate any deferred opcodes because we're going to be looking at
4074 flush_pending_unwind ();
4076 for (reg
= 0; reg
< 16; reg
++)
4078 if (mask
& (1 << reg
))
4079 unwind
.frame_size
+= 4;
4082 add_unwind_opcode (op
, 2);
4085 ignore_rest_of_line ();
4089 /* Parse an unwind_save directive.
4090 If the argument is non-zero, this is a .vsave directive. */
4093 s_arm_unwind_save (int arch_v6
)
4096 struct reg_entry
*reg
;
4097 bfd_boolean had_brace
= FALSE
;
4099 if (!unwind
.proc_start
)
4100 as_bad (MISSING_FNSTART
);
4102 /* Figure out what sort of save we have. */
4103 peek
= input_line_pointer
;
4111 reg
= arm_reg_parse_multi (&peek
);
4115 as_bad (_("register expected"));
4116 ignore_rest_of_line ();
4125 as_bad (_("FPA .unwind_save does not take a register list"));
4126 ignore_rest_of_line ();
4129 input_line_pointer
= peek
;
4130 s_arm_unwind_save_fpa (reg
->number
);
4133 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4136 s_arm_unwind_save_vfp_armv6 ();
4138 s_arm_unwind_save_vfp ();
4140 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4141 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4144 as_bad (_(".unwind_save does not support this kind of register"));
4145 ignore_rest_of_line ();
4150 /* Parse an unwind_movsp directive. */
4153 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4159 if (!unwind
.proc_start
)
4160 as_bad (MISSING_FNSTART
);
4162 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4165 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4166 ignore_rest_of_line ();
4170 /* Optional constant. */
4171 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4173 if (immediate_for_directive (&offset
) == FAIL
)
4179 demand_empty_rest_of_line ();
4181 if (reg
== REG_SP
|| reg
== REG_PC
)
4183 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4187 if (unwind
.fp_reg
!= REG_SP
)
4188 as_bad (_("unexpected .unwind_movsp directive"));
4190 /* Generate opcode to restore the value. */
4192 add_unwind_opcode (op
, 1);
4194 /* Record the information for later. */
4195 unwind
.fp_reg
= reg
;
4196 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4197 unwind
.sp_restored
= 1;
4200 /* Parse an unwind_pad directive. */
4203 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4207 if (!unwind
.proc_start
)
4208 as_bad (MISSING_FNSTART
);
4210 if (immediate_for_directive (&offset
) == FAIL
)
4215 as_bad (_("stack increment must be multiple of 4"));
4216 ignore_rest_of_line ();
4220 /* Don't generate any opcodes, just record the details for later. */
4221 unwind
.frame_size
+= offset
;
4222 unwind
.pending_offset
+= offset
;
4224 demand_empty_rest_of_line ();
4227 /* Parse an unwind_setfp directive. */
4230 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4236 if (!unwind
.proc_start
)
4237 as_bad (MISSING_FNSTART
);
4239 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4240 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4243 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4245 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4247 as_bad (_("expected <reg>, <reg>"));
4248 ignore_rest_of_line ();
4252 /* Optional constant. */
4253 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4255 if (immediate_for_directive (&offset
) == FAIL
)
4261 demand_empty_rest_of_line ();
4263 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4265 as_bad (_("register must be either sp or set by a previous"
4266 "unwind_movsp directive"));
4270 /* Don't generate any opcodes, just record the information for later. */
4271 unwind
.fp_reg
= fp_reg
;
4273 if (sp_reg
== REG_SP
)
4274 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4276 unwind
.fp_offset
-= offset
;
4279 /* Parse an unwind_raw directive. */
4282 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4285 /* This is an arbitrary limit. */
4286 unsigned char op
[16];
4289 if (!unwind
.proc_start
)
4290 as_bad (MISSING_FNSTART
);
4293 if (exp
.X_op
== O_constant
4294 && skip_past_comma (&input_line_pointer
) != FAIL
)
4296 unwind
.frame_size
+= exp
.X_add_number
;
4300 exp
.X_op
= O_illegal
;
4302 if (exp
.X_op
!= O_constant
)
4304 as_bad (_("expected <offset>, <opcode>"));
4305 ignore_rest_of_line ();
4311 /* Parse the opcode. */
4316 as_bad (_("unwind opcode too long"));
4317 ignore_rest_of_line ();
4319 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4321 as_bad (_("invalid unwind opcode"));
4322 ignore_rest_of_line ();
4325 op
[count
++] = exp
.X_add_number
;
4327 /* Parse the next byte. */
4328 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4334 /* Add the opcode bytes in reverse order. */
4336 add_unwind_opcode (op
[count
], 1);
4338 demand_empty_rest_of_line ();
4342 /* Parse a .eabi_attribute directive. */
4345 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4347 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4349 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4350 attributes_set_explicitly
[tag
] = 1;
4353 /* Emit a tls fix for the symbol. */
4356 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4360 #ifdef md_flush_pending_output
4361 md_flush_pending_output ();
4364 #ifdef md_cons_align
4368 /* Since we're just labelling the code, there's no need to define a
4371 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4372 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4373 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4374 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4376 #endif /* OBJ_ELF */
4378 static void s_arm_arch (int);
4379 static void s_arm_object_arch (int);
4380 static void s_arm_cpu (int);
4381 static void s_arm_fpu (int);
4382 static void s_arm_arch_extension (int);
4387 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4394 if (exp
.X_op
== O_symbol
)
4395 exp
.X_op
= O_secrel
;
4397 emit_expr (&exp
, 4);
4399 while (*input_line_pointer
++ == ',');
4401 input_line_pointer
--;
4402 demand_empty_rest_of_line ();
4406 /* This table describes all the machine specific pseudo-ops the assembler
4407 has to support. The fields are:
4408 pseudo-op name without dot
4409 function to call to execute this pseudo-op
4410 Integer arg to pass to the function. */
4412 const pseudo_typeS md_pseudo_table
[] =
4414 /* Never called because '.req' does not start a line. */
4415 { "req", s_req
, 0 },
4416 /* Following two are likewise never called. */
4419 { "unreq", s_unreq
, 0 },
4420 { "bss", s_bss
, 0 },
4421 { "align", s_align
, 0 },
4422 { "arm", s_arm
, 0 },
4423 { "thumb", s_thumb
, 0 },
4424 { "code", s_code
, 0 },
4425 { "force_thumb", s_force_thumb
, 0 },
4426 { "thumb_func", s_thumb_func
, 0 },
4427 { "thumb_set", s_thumb_set
, 0 },
4428 { "even", s_even
, 0 },
4429 { "ltorg", s_ltorg
, 0 },
4430 { "pool", s_ltorg
, 0 },
4431 { "syntax", s_syntax
, 0 },
4432 { "cpu", s_arm_cpu
, 0 },
4433 { "arch", s_arm_arch
, 0 },
4434 { "object_arch", s_arm_object_arch
, 0 },
4435 { "fpu", s_arm_fpu
, 0 },
4436 { "arch_extension", s_arm_arch_extension
, 0 },
4438 { "word", s_arm_elf_cons
, 4 },
4439 { "long", s_arm_elf_cons
, 4 },
4440 { "inst.n", s_arm_elf_inst
, 2 },
4441 { "inst.w", s_arm_elf_inst
, 4 },
4442 { "inst", s_arm_elf_inst
, 0 },
4443 { "rel31", s_arm_rel31
, 0 },
4444 { "fnstart", s_arm_unwind_fnstart
, 0 },
4445 { "fnend", s_arm_unwind_fnend
, 0 },
4446 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4447 { "personality", s_arm_unwind_personality
, 0 },
4448 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4449 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4450 { "save", s_arm_unwind_save
, 0 },
4451 { "vsave", s_arm_unwind_save
, 1 },
4452 { "movsp", s_arm_unwind_movsp
, 0 },
4453 { "pad", s_arm_unwind_pad
, 0 },
4454 { "setfp", s_arm_unwind_setfp
, 0 },
4455 { "unwind_raw", s_arm_unwind_raw
, 0 },
4456 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4457 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4461 /* These are used for dwarf. */
4465 /* These are used for dwarf2. */
4466 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4467 { "loc", dwarf2_directive_loc
, 0 },
4468 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4470 { "extend", float_cons
, 'x' },
4471 { "ldouble", float_cons
, 'x' },
4472 { "packed", float_cons
, 'p' },
4474 {"secrel32", pe_directive_secrel
, 0},
4479 /* Parser functions used exclusively in instruction operands. */
4481 /* Generic immediate-value read function for use in insn parsing.
4482 STR points to the beginning of the immediate (the leading #);
4483 VAL receives the value; if the value is outside [MIN, MAX]
4484 issue an error. PREFIX_OPT is true if the immediate prefix is
4488 parse_immediate (char **str
, int *val
, int min
, int max
,
4489 bfd_boolean prefix_opt
)
4492 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4493 if (exp
.X_op
!= O_constant
)
4495 inst
.error
= _("constant expression required");
4499 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4501 inst
.error
= _("immediate value out of range");
4505 *val
= exp
.X_add_number
;
4509 /* Less-generic immediate-value read function with the possibility of loading a
4510 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4511 instructions. Puts the result directly in inst.operands[i]. */
4514 parse_big_immediate (char **str
, int i
)
4519 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4521 if (exp
.X_op
== O_constant
)
4523 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4524 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4525 O_constant. We have to be careful not to break compilation for
4526 32-bit X_add_number, though. */
4527 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4529 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4530 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4531 inst
.operands
[i
].regisimm
= 1;
4534 else if (exp
.X_op
== O_big
4535 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4537 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4539 /* Bignums have their least significant bits in
4540 generic_bignum[0]. Make sure we put 32 bits in imm and
4541 32 bits in reg, in a (hopefully) portable way. */
4542 gas_assert (parts
!= 0);
4544 /* Make sure that the number is not too big.
4545 PR 11972: Bignums can now be sign-extended to the
4546 size of a .octa so check that the out of range bits
4547 are all zero or all one. */
4548 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4550 LITTLENUM_TYPE m
= -1;
4552 if (generic_bignum
[parts
* 2] != 0
4553 && generic_bignum
[parts
* 2] != m
)
4556 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4557 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4561 inst
.operands
[i
].imm
= 0;
4562 for (j
= 0; j
< parts
; j
++, idx
++)
4563 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4564 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4565 inst
.operands
[i
].reg
= 0;
4566 for (j
= 0; j
< parts
; j
++, idx
++)
4567 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4568 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4569 inst
.operands
[i
].regisimm
= 1;
4579 /* Returns the pseudo-register number of an FPA immediate constant,
4580 or FAIL if there isn't a valid constant here. */
4583 parse_fpa_immediate (char ** str
)
4585 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4591 /* First try and match exact strings, this is to guarantee
4592 that some formats will work even for cross assembly. */
4594 for (i
= 0; fp_const
[i
]; i
++)
4596 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4600 *str
+= strlen (fp_const
[i
]);
4601 if (is_end_of_line
[(unsigned char) **str
])
4607 /* Just because we didn't get a match doesn't mean that the constant
4608 isn't valid, just that it is in a format that we don't
4609 automatically recognize. Try parsing it with the standard
4610 expression routines. */
4612 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4614 /* Look for a raw floating point number. */
4615 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4616 && is_end_of_line
[(unsigned char) *save_in
])
4618 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4620 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4622 if (words
[j
] != fp_values
[i
][j
])
4626 if (j
== MAX_LITTLENUMS
)
4634 /* Try and parse a more complex expression, this will probably fail
4635 unless the code uses a floating point prefix (eg "0f"). */
4636 save_in
= input_line_pointer
;
4637 input_line_pointer
= *str
;
4638 if (expression (&exp
) == absolute_section
4639 && exp
.X_op
== O_big
4640 && exp
.X_add_number
< 0)
4642 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4644 if (gen_to_words (words
, 5, (long) 15) == 0)
4646 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4648 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4650 if (words
[j
] != fp_values
[i
][j
])
4654 if (j
== MAX_LITTLENUMS
)
4656 *str
= input_line_pointer
;
4657 input_line_pointer
= save_in
;
4664 *str
= input_line_pointer
;
4665 input_line_pointer
= save_in
;
4666 inst
.error
= _("invalid FPA immediate expression");
4670 /* Returns 1 if a number has "quarter-precision" float format
4671 0baBbbbbbc defgh000 00000000 00000000. */
4674 is_quarter_float (unsigned imm
)
4676 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4677 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4680 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4681 0baBbbbbbc defgh000 00000000 00000000.
4682 The zero and minus-zero cases need special handling, since they can't be
4683 encoded in the "quarter-precision" float format, but can nonetheless be
4684 loaded as integer constants. */
4687 parse_qfloat_immediate (char **ccp
, int *immed
)
4691 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4692 int found_fpchar
= 0;
4694 skip_past_char (&str
, '#');
4696 /* We must not accidentally parse an integer as a floating-point number. Make
4697 sure that the value we parse is not an integer by checking for special
4698 characters '.' or 'e'.
4699 FIXME: This is a horrible hack, but doing better is tricky because type
4700 information isn't in a very usable state at parse time. */
4702 skip_whitespace (fpnum
);
4704 if (strncmp (fpnum
, "0x", 2) == 0)
4708 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4709 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4719 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4721 unsigned fpword
= 0;
4724 /* Our FP word must be 32 bits (single-precision FP). */
4725 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4727 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4731 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4744 /* Shift operands. */
4747 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4750 struct asm_shift_name
4753 enum shift_kind kind
;
4756 /* Third argument to parse_shift. */
4757 enum parse_shift_mode
4759 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4760 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4761 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4762 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4763 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4766 /* Parse a <shift> specifier on an ARM data processing instruction.
4767 This has three forms:
4769 (LSL|LSR|ASL|ASR|ROR) Rs
4770 (LSL|LSR|ASL|ASR|ROR) #imm
4773 Note that ASL is assimilated to LSL in the instruction encoding, and
4774 RRX to ROR #0 (which cannot be written as such). */
4777 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4779 const struct asm_shift_name
*shift_name
;
4780 enum shift_kind shift
;
4785 for (p
= *str
; ISALPHA (*p
); p
++)
4790 inst
.error
= _("shift expression expected");
4794 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4797 if (shift_name
== NULL
)
4799 inst
.error
= _("shift expression expected");
4803 shift
= shift_name
->kind
;
4807 case NO_SHIFT_RESTRICT
:
4808 case SHIFT_IMMEDIATE
: break;
4810 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4811 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4813 inst
.error
= _("'LSL' or 'ASR' required");
4818 case SHIFT_LSL_IMMEDIATE
:
4819 if (shift
!= SHIFT_LSL
)
4821 inst
.error
= _("'LSL' required");
4826 case SHIFT_ASR_IMMEDIATE
:
4827 if (shift
!= SHIFT_ASR
)
4829 inst
.error
= _("'ASR' required");
4837 if (shift
!= SHIFT_RRX
)
4839 /* Whitespace can appear here if the next thing is a bare digit. */
4840 skip_whitespace (p
);
4842 if (mode
== NO_SHIFT_RESTRICT
4843 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4845 inst
.operands
[i
].imm
= reg
;
4846 inst
.operands
[i
].immisreg
= 1;
4848 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4851 inst
.operands
[i
].shift_kind
= shift
;
4852 inst
.operands
[i
].shifted
= 1;
4857 /* Parse a <shifter_operand> for an ARM data processing instruction:
4860 #<immediate>, <rotate>
4864 where <shift> is defined by parse_shift above, and <rotate> is a
4865 multiple of 2 between 0 and 30. Validation of immediate operands
4866 is deferred to md_apply_fix. */
4869 parse_shifter_operand (char **str
, int i
)
4874 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4876 inst
.operands
[i
].reg
= value
;
4877 inst
.operands
[i
].isreg
= 1;
4879 /* parse_shift will override this if appropriate */
4880 inst
.reloc
.exp
.X_op
= O_constant
;
4881 inst
.reloc
.exp
.X_add_number
= 0;
4883 if (skip_past_comma (str
) == FAIL
)
4886 /* Shift operation on register. */
4887 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4890 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4893 if (skip_past_comma (str
) == SUCCESS
)
4895 /* #x, y -- ie explicit rotation by Y. */
4896 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4899 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4901 inst
.error
= _("constant expression expected");
4905 value
= exp
.X_add_number
;
4906 if (value
< 0 || value
> 30 || value
% 2 != 0)
4908 inst
.error
= _("invalid rotation");
4911 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4913 inst
.error
= _("invalid constant");
4917 /* Encode as specified. */
4918 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
4922 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4923 inst
.reloc
.pc_rel
= 0;
4927 /* Group relocation information. Each entry in the table contains the
4928 textual name of the relocation as may appear in assembler source
4929 and must end with a colon.
4930 Along with this textual name are the relocation codes to be used if
4931 the corresponding instruction is an ALU instruction (ADD or SUB only),
4932 an LDR, an LDRS, or an LDC. */
4934 struct group_reloc_table_entry
4945 /* Varieties of non-ALU group relocation. */
4952 static struct group_reloc_table_entry group_reloc_table
[] =
4953 { /* Program counter relative: */
4955 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4960 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4961 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4962 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4963 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4965 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4970 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4971 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4972 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4973 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4975 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4976 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4977 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4978 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4979 /* Section base relative */
4981 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4986 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4987 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4988 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4989 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4991 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4996 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4997 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4998 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4999 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5001 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5002 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5003 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5004 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5006 /* Given the address of a pointer pointing to the textual name of a group
5007 relocation as may appear in assembler source, attempt to find its details
5008 in group_reloc_table. The pointer will be updated to the character after
5009 the trailing colon. On failure, FAIL will be returned; SUCCESS
5010 otherwise. On success, *entry will be updated to point at the relevant
5011 group_reloc_table entry. */
5014 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5017 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5019 int length
= strlen (group_reloc_table
[i
].name
);
5021 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5022 && (*str
)[length
] == ':')
5024 *out
= &group_reloc_table
[i
];
5025 *str
+= (length
+ 1);
5033 /* Parse a <shifter_operand> for an ARM data processing instruction
5034 (as for parse_shifter_operand) where group relocations are allowed:
5037 #<immediate>, <rotate>
5038 #:<group_reloc>:<expression>
5042 where <group_reloc> is one of the strings defined in group_reloc_table.
5043 The hashes are optional.
5045 Everything else is as for parse_shifter_operand. */
5047 static parse_operand_result
5048 parse_shifter_operand_group_reloc (char **str
, int i
)
5050 /* Determine if we have the sequence of characters #: or just :
5051 coming next. If we do, then we check for a group relocation.
5052 If we don't, punt the whole lot to parse_shifter_operand. */
5054 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5055 || (*str
)[0] == ':')
5057 struct group_reloc_table_entry
*entry
;
5059 if ((*str
)[0] == '#')
5064 /* Try to parse a group relocation. Anything else is an error. */
5065 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5067 inst
.error
= _("unknown group relocation");
5068 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5071 /* We now have the group relocation table entry corresponding to
5072 the name in the assembler source. Next, we parse the expression. */
5073 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5074 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5076 /* Record the relocation type (always the ALU variant here). */
5077 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5078 gas_assert (inst
.reloc
.type
!= 0);
5080 return PARSE_OPERAND_SUCCESS
;
5083 return parse_shifter_operand (str
, i
) == SUCCESS
5084 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5086 /* Never reached. */
5089 /* Parse a Neon alignment expression. Information is written to
5090 inst.operands[i]. We assume the initial ':' has been skipped.
5092 align .imm = align << 8, .immisalign=1, .preind=0 */
5093 static parse_operand_result
5094 parse_neon_alignment (char **str
, int i
)
5099 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5101 if (exp
.X_op
!= O_constant
)
5103 inst
.error
= _("alignment must be constant");
5104 return PARSE_OPERAND_FAIL
;
5107 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5108 inst
.operands
[i
].immisalign
= 1;
5109 /* Alignments are not pre-indexes. */
5110 inst
.operands
[i
].preind
= 0;
5113 return PARSE_OPERAND_SUCCESS
;
5116 /* Parse all forms of an ARM address expression. Information is written
5117 to inst.operands[i] and/or inst.reloc.
5119 Preindexed addressing (.preind=1):
5121 [Rn, #offset] .reg=Rn .reloc.exp=offset
5122 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5123 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 .shift_kind=shift .reloc.exp=shift_imm
5126 These three may have a trailing ! which causes .writeback to be set also.
5128 Postindexed addressing (.postind=1, .writeback=1):
5130 [Rn], #offset .reg=Rn .reloc.exp=offset
5131 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5132 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5133 .shift_kind=shift .reloc.exp=shift_imm
5135 Unindexed addressing (.preind=0, .postind=0):
5137 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5141 [Rn]{!} shorthand for [Rn,#0]{!}
5142 =immediate .isreg=0 .reloc.exp=immediate
5143 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5145 It is the caller's responsibility to check for addressing modes not
5146 supported by the instruction, and to set inst.reloc.type. */
5148 static parse_operand_result
5149 parse_address_main (char **str
, int i
, int group_relocations
,
5150 group_reloc_type group_type
)
5155 if (skip_past_char (&p
, '[') == FAIL
)
5157 if (skip_past_char (&p
, '=') == FAIL
)
5159 /* Bare address - translate to PC-relative offset. */
5160 inst
.reloc
.pc_rel
= 1;
5161 inst
.operands
[i
].reg
= REG_PC
;
5162 inst
.operands
[i
].isreg
= 1;
5163 inst
.operands
[i
].preind
= 1;
5165 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5167 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5168 return PARSE_OPERAND_FAIL
;
5171 return PARSE_OPERAND_SUCCESS
;
5174 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5175 skip_whitespace (p
);
5177 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5179 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5180 return PARSE_OPERAND_FAIL
;
5182 inst
.operands
[i
].reg
= reg
;
5183 inst
.operands
[i
].isreg
= 1;
5185 if (skip_past_comma (&p
) == SUCCESS
)
5187 inst
.operands
[i
].preind
= 1;
5190 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5192 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5194 inst
.operands
[i
].imm
= reg
;
5195 inst
.operands
[i
].immisreg
= 1;
5197 if (skip_past_comma (&p
) == SUCCESS
)
5198 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5199 return PARSE_OPERAND_FAIL
;
5201 else if (skip_past_char (&p
, ':') == SUCCESS
)
5203 /* FIXME: '@' should be used here, but it's filtered out by generic
5204 code before we get to see it here. This may be subject to
5206 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5208 if (result
!= PARSE_OPERAND_SUCCESS
)
5213 if (inst
.operands
[i
].negative
)
5215 inst
.operands
[i
].negative
= 0;
5219 if (group_relocations
5220 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5222 struct group_reloc_table_entry
*entry
;
5224 /* Skip over the #: or : sequence. */
5230 /* Try to parse a group relocation. Anything else is an
5232 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5234 inst
.error
= _("unknown group relocation");
5235 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5238 /* We now have the group relocation table entry corresponding to
5239 the name in the assembler source. Next, we parse the
5241 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5242 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5244 /* Record the relocation type. */
5248 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5252 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5256 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5263 if (inst
.reloc
.type
== 0)
5265 inst
.error
= _("this group relocation is not allowed on this instruction");
5266 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5272 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5273 return PARSE_OPERAND_FAIL
;
5274 /* If the offset is 0, find out if it's a +0 or -0. */
5275 if (inst
.reloc
.exp
.X_op
== O_constant
5276 && inst
.reloc
.exp
.X_add_number
== 0)
5278 skip_whitespace (q
);
5282 skip_whitespace (q
);
5285 inst
.operands
[i
].negative
= 1;
5290 else if (skip_past_char (&p
, ':') == SUCCESS
)
5292 /* FIXME: '@' should be used here, but it's filtered out by generic code
5293 before we get to see it here. This may be subject to change. */
5294 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5296 if (result
!= PARSE_OPERAND_SUCCESS
)
5300 if (skip_past_char (&p
, ']') == FAIL
)
5302 inst
.error
= _("']' expected");
5303 return PARSE_OPERAND_FAIL
;
5306 if (skip_past_char (&p
, '!') == SUCCESS
)
5307 inst
.operands
[i
].writeback
= 1;
5309 else if (skip_past_comma (&p
) == SUCCESS
)
5311 if (skip_past_char (&p
, '{') == SUCCESS
)
5313 /* [Rn], {expr} - unindexed, with option */
5314 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5315 0, 255, TRUE
) == FAIL
)
5316 return PARSE_OPERAND_FAIL
;
5318 if (skip_past_char (&p
, '}') == FAIL
)
5320 inst
.error
= _("'}' expected at end of 'option' field");
5321 return PARSE_OPERAND_FAIL
;
5323 if (inst
.operands
[i
].preind
)
5325 inst
.error
= _("cannot combine index with option");
5326 return PARSE_OPERAND_FAIL
;
5329 return PARSE_OPERAND_SUCCESS
;
5333 inst
.operands
[i
].postind
= 1;
5334 inst
.operands
[i
].writeback
= 1;
5336 if (inst
.operands
[i
].preind
)
5338 inst
.error
= _("cannot combine pre- and post-indexing");
5339 return PARSE_OPERAND_FAIL
;
5343 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5345 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5347 /* We might be using the immediate for alignment already. If we
5348 are, OR the register number into the low-order bits. */
5349 if (inst
.operands
[i
].immisalign
)
5350 inst
.operands
[i
].imm
|= reg
;
5352 inst
.operands
[i
].imm
= reg
;
5353 inst
.operands
[i
].immisreg
= 1;
5355 if (skip_past_comma (&p
) == SUCCESS
)
5356 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5357 return PARSE_OPERAND_FAIL
;
5362 if (inst
.operands
[i
].negative
)
5364 inst
.operands
[i
].negative
= 0;
5367 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5368 return PARSE_OPERAND_FAIL
;
5369 /* If the offset is 0, find out if it's a +0 or -0. */
5370 if (inst
.reloc
.exp
.X_op
== O_constant
5371 && inst
.reloc
.exp
.X_add_number
== 0)
5373 skip_whitespace (q
);
5377 skip_whitespace (q
);
5380 inst
.operands
[i
].negative
= 1;
5386 /* If at this point neither .preind nor .postind is set, we have a
5387 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5388 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5390 inst
.operands
[i
].preind
= 1;
5391 inst
.reloc
.exp
.X_op
= O_constant
;
5392 inst
.reloc
.exp
.X_add_number
= 0;
5395 return PARSE_OPERAND_SUCCESS
;
5399 parse_address (char **str
, int i
)
5401 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5405 static parse_operand_result
5406 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5408 return parse_address_main (str
, i
, 1, type
);
5411 /* Parse an operand for a MOVW or MOVT instruction. */
5413 parse_half (char **str
)
5418 skip_past_char (&p
, '#');
5419 if (strncasecmp (p
, ":lower16:", 9) == 0)
5420 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5421 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5422 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5424 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5427 skip_whitespace (p
);
5430 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5433 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5435 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5437 inst
.error
= _("constant expression expected");
5440 if (inst
.reloc
.exp
.X_add_number
< 0
5441 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5443 inst
.error
= _("immediate value out of range");
5451 /* Miscellaneous. */
5453 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5454 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5456 parse_psr (char **str
, bfd_boolean lhs
)
5459 unsigned long psr_field
;
5460 const struct asm_psr
*psr
;
5462 bfd_boolean is_apsr
= FALSE
;
5463 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5465 /* PR gas/12698: If the user has specified -march=all then m_profile will
5466 be TRUE, but we want to ignore it in this case as we are building for any
5467 CPU type, including non-m variants. */
5468 if (selected_cpu
.core
== arm_arch_any
.core
)
5471 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5472 feature for ease of use and backwards compatibility. */
5474 if (strncasecmp (p
, "SPSR", 4) == 0)
5477 goto unsupported_psr
;
5479 psr_field
= SPSR_BIT
;
5481 else if (strncasecmp (p
, "CPSR", 4) == 0)
5484 goto unsupported_psr
;
5488 else if (strncasecmp (p
, "APSR", 4) == 0)
5490 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5491 and ARMv7-R architecture CPUs. */
5500 while (ISALNUM (*p
) || *p
== '_');
5502 if (strncasecmp (start
, "iapsr", 5) == 0
5503 || strncasecmp (start
, "eapsr", 5) == 0
5504 || strncasecmp (start
, "xpsr", 4) == 0
5505 || strncasecmp (start
, "psr", 3) == 0)
5506 p
= start
+ strcspn (start
, "rR") + 1;
5508 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5514 /* If APSR is being written, a bitfield may be specified. Note that
5515 APSR itself is handled above. */
5516 if (psr
->field
<= 3)
5518 psr_field
= psr
->field
;
5524 /* M-profile MSR instructions have the mask field set to "10", except
5525 *PSR variants which modify APSR, which may use a different mask (and
5526 have been handled already). Do that by setting the PSR_f field
5528 return psr
->field
| (lhs
? PSR_f
: 0);
5531 goto unsupported_psr
;
5537 /* A suffix follows. */
5543 while (ISALNUM (*p
) || *p
== '_');
5547 /* APSR uses a notation for bits, rather than fields. */
5548 unsigned int nzcvq_bits
= 0;
5549 unsigned int g_bit
= 0;
5552 for (bit
= start
; bit
!= p
; bit
++)
5554 switch (TOLOWER (*bit
))
5557 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5561 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5565 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5569 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5573 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5577 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5581 inst
.error
= _("unexpected bit specified after APSR");
5586 if (nzcvq_bits
== 0x1f)
5591 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5593 inst
.error
= _("selected processor does not "
5594 "support DSP extension");
5601 if ((nzcvq_bits
& 0x20) != 0
5602 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5603 || (g_bit
& 0x2) != 0)
5605 inst
.error
= _("bad bitmask specified after APSR");
5611 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5616 psr_field
|= psr
->field
;
5622 goto error
; /* Garbage after "[CS]PSR". */
5624 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5625 is deprecated, but allow it anyway. */
5629 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5632 else if (!m_profile
)
5633 /* These bits are never right for M-profile devices: don't set them
5634 (only code paths which read/write APSR reach here). */
5635 psr_field
|= (PSR_c
| PSR_f
);
5641 inst
.error
= _("selected processor does not support requested special "
5642 "purpose register");
5646 inst
.error
= _("flag for {c}psr instruction expected");
5650 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5651 value suitable for splatting into the AIF field of the instruction. */
5654 parse_cps_flags (char **str
)
5663 case '\0': case ',':
5666 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5667 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5668 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5671 inst
.error
= _("unrecognized CPS flag");
5676 if (saw_a_flag
== 0)
5678 inst
.error
= _("missing CPS flags");
5686 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5687 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5690 parse_endian_specifier (char **str
)
5695 if (strncasecmp (s
, "BE", 2))
5697 else if (strncasecmp (s
, "LE", 2))
5701 inst
.error
= _("valid endian specifiers are be or le");
5705 if (ISALNUM (s
[2]) || s
[2] == '_')
5707 inst
.error
= _("valid endian specifiers are be or le");
5712 return little_endian
;
5715 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5716 value suitable for poking into the rotate field of an sxt or sxta
5717 instruction, or FAIL on error. */
5720 parse_ror (char **str
)
5725 if (strncasecmp (s
, "ROR", 3) == 0)
5729 inst
.error
= _("missing rotation field after comma");
5733 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5738 case 0: *str
= s
; return 0x0;
5739 case 8: *str
= s
; return 0x1;
5740 case 16: *str
= s
; return 0x2;
5741 case 24: *str
= s
; return 0x3;
5744 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5749 /* Parse a conditional code (from conds[] below). The value returned is in the
5750 range 0 .. 14, or FAIL. */
5752 parse_cond (char **str
)
5755 const struct asm_cond
*c
;
5757 /* Condition codes are always 2 characters, so matching up to
5758 3 characters is sufficient. */
5763 while (ISALPHA (*q
) && n
< 3)
5765 cond
[n
] = TOLOWER (*q
);
5770 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5773 inst
.error
= _("condition required");
5781 /* If the given feature available in the selected CPU, mark it as used.
5782 Returns TRUE iff feature is available. */
5784 mark_feature_used (const arm_feature_set
*feature
)
5786 /* Ensure the option is valid on the current architecture. */
5787 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
5790 /* Add the appropriate architecture feature for the barrier option used.
5793 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
5795 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
5800 /* Parse an option for a barrier instruction. Returns the encoding for the
5803 parse_barrier (char **str
)
5806 const struct asm_barrier_opt
*o
;
5809 while (ISALPHA (*q
))
5812 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5817 if (!mark_feature_used (&o
->arch
))
5824 /* Parse the operands of a table branch instruction. Similar to a memory
5827 parse_tb (char **str
)
5832 if (skip_past_char (&p
, '[') == FAIL
)
5834 inst
.error
= _("'[' expected");
5838 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5840 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5843 inst
.operands
[0].reg
= reg
;
5845 if (skip_past_comma (&p
) == FAIL
)
5847 inst
.error
= _("',' expected");
5851 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5853 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5856 inst
.operands
[0].imm
= reg
;
5858 if (skip_past_comma (&p
) == SUCCESS
)
5860 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5862 if (inst
.reloc
.exp
.X_add_number
!= 1)
5864 inst
.error
= _("invalid shift");
5867 inst
.operands
[0].shifted
= 1;
5870 if (skip_past_char (&p
, ']') == FAIL
)
5872 inst
.error
= _("']' expected");
5879 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5880 information on the types the operands can take and how they are encoded.
5881 Up to four operands may be read; this function handles setting the
5882 ".present" field for each read operand itself.
5883 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5884 else returns FAIL. */
5887 parse_neon_mov (char **str
, int *which_operand
)
5889 int i
= *which_operand
, val
;
5890 enum arm_reg_type rtype
;
5892 struct neon_type_el optype
;
5894 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5896 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5897 inst
.operands
[i
].reg
= val
;
5898 inst
.operands
[i
].isscalar
= 1;
5899 inst
.operands
[i
].vectype
= optype
;
5900 inst
.operands
[i
++].present
= 1;
5902 if (skip_past_comma (&ptr
) == FAIL
)
5905 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5908 inst
.operands
[i
].reg
= val
;
5909 inst
.operands
[i
].isreg
= 1;
5910 inst
.operands
[i
].present
= 1;
5912 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5915 /* Cases 0, 1, 2, 3, 5 (D only). */
5916 if (skip_past_comma (&ptr
) == FAIL
)
5919 inst
.operands
[i
].reg
= val
;
5920 inst
.operands
[i
].isreg
= 1;
5921 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5922 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5923 inst
.operands
[i
].isvec
= 1;
5924 inst
.operands
[i
].vectype
= optype
;
5925 inst
.operands
[i
++].present
= 1;
5927 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5929 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5930 Case 13: VMOV <Sd>, <Rm> */
5931 inst
.operands
[i
].reg
= val
;
5932 inst
.operands
[i
].isreg
= 1;
5933 inst
.operands
[i
].present
= 1;
5935 if (rtype
== REG_TYPE_NQ
)
5937 first_error (_("can't use Neon quad register here"));
5940 else if (rtype
!= REG_TYPE_VFS
)
5943 if (skip_past_comma (&ptr
) == FAIL
)
5945 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5947 inst
.operands
[i
].reg
= val
;
5948 inst
.operands
[i
].isreg
= 1;
5949 inst
.operands
[i
].present
= 1;
5952 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5955 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5956 Case 1: VMOV<c><q> <Dd>, <Dm>
5957 Case 8: VMOV.F32 <Sd>, <Sm>
5958 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5960 inst
.operands
[i
].reg
= val
;
5961 inst
.operands
[i
].isreg
= 1;
5962 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5963 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5964 inst
.operands
[i
].isvec
= 1;
5965 inst
.operands
[i
].vectype
= optype
;
5966 inst
.operands
[i
].present
= 1;
5968 if (skip_past_comma (&ptr
) == SUCCESS
)
5973 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5976 inst
.operands
[i
].reg
= val
;
5977 inst
.operands
[i
].isreg
= 1;
5978 inst
.operands
[i
++].present
= 1;
5980 if (skip_past_comma (&ptr
) == FAIL
)
5983 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5986 inst
.operands
[i
].reg
= val
;
5987 inst
.operands
[i
].isreg
= 1;
5988 inst
.operands
[i
].present
= 1;
5991 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5992 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5993 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5994 Case 10: VMOV.F32 <Sd>, #<imm>
5995 Case 11: VMOV.F64 <Dd>, #<imm> */
5996 inst
.operands
[i
].immisfloat
= 1;
5997 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5998 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5999 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6003 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6007 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6010 inst
.operands
[i
].reg
= val
;
6011 inst
.operands
[i
].isreg
= 1;
6012 inst
.operands
[i
++].present
= 1;
6014 if (skip_past_comma (&ptr
) == FAIL
)
6017 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6019 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6020 inst
.operands
[i
].reg
= val
;
6021 inst
.operands
[i
].isscalar
= 1;
6022 inst
.operands
[i
].present
= 1;
6023 inst
.operands
[i
].vectype
= optype
;
6025 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6027 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6028 inst
.operands
[i
].reg
= val
;
6029 inst
.operands
[i
].isreg
= 1;
6030 inst
.operands
[i
++].present
= 1;
6032 if (skip_past_comma (&ptr
) == FAIL
)
6035 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6038 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6042 inst
.operands
[i
].reg
= val
;
6043 inst
.operands
[i
].isreg
= 1;
6044 inst
.operands
[i
].isvec
= 1;
6045 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6046 inst
.operands
[i
].vectype
= optype
;
6047 inst
.operands
[i
].present
= 1;
6049 if (rtype
== REG_TYPE_VFS
)
6053 if (skip_past_comma (&ptr
) == FAIL
)
6055 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6058 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6061 inst
.operands
[i
].reg
= val
;
6062 inst
.operands
[i
].isreg
= 1;
6063 inst
.operands
[i
].isvec
= 1;
6064 inst
.operands
[i
].issingle
= 1;
6065 inst
.operands
[i
].vectype
= optype
;
6066 inst
.operands
[i
].present
= 1;
6069 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6073 inst
.operands
[i
].reg
= val
;
6074 inst
.operands
[i
].isreg
= 1;
6075 inst
.operands
[i
].isvec
= 1;
6076 inst
.operands
[i
].issingle
= 1;
6077 inst
.operands
[i
].vectype
= optype
;
6078 inst
.operands
[i
].present
= 1;
6083 first_error (_("parse error"));
6087 /* Successfully parsed the operands. Update args. */
6093 first_error (_("expected comma"));
6097 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6101 /* Use this macro when the operand constraints are different
6102 for ARM and THUMB (e.g. ldrd). */
6103 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6104 ((arm_operand) | ((thumb_operand) << 16))
6106 /* Matcher codes for parse_operands. */
6107 enum operand_parse_code
6109 OP_stop
, /* end of line */
6111 OP_RR
, /* ARM register */
6112 OP_RRnpc
, /* ARM register, not r15 */
6113 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6114 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6115 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6116 optional trailing ! */
6117 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6118 OP_RCP
, /* Coprocessor number */
6119 OP_RCN
, /* Coprocessor register */
6120 OP_RF
, /* FPA register */
6121 OP_RVS
, /* VFP single precision register */
6122 OP_RVD
, /* VFP double precision register (0..15) */
6123 OP_RND
, /* Neon double precision register (0..31) */
6124 OP_RNQ
, /* Neon quad precision register */
6125 OP_RVSD
, /* VFP single or double precision register */
6126 OP_RNDQ
, /* Neon double or quad precision register */
6127 OP_RNSDQ
, /* Neon single, double or quad precision register */
6128 OP_RNSC
, /* Neon scalar D[X] */
6129 OP_RVC
, /* VFP control register */
6130 OP_RMF
, /* Maverick F register */
6131 OP_RMD
, /* Maverick D register */
6132 OP_RMFX
, /* Maverick FX register */
6133 OP_RMDX
, /* Maverick DX register */
6134 OP_RMAX
, /* Maverick AX register */
6135 OP_RMDS
, /* Maverick DSPSC register */
6136 OP_RIWR
, /* iWMMXt wR register */
6137 OP_RIWC
, /* iWMMXt wC register */
6138 OP_RIWG
, /* iWMMXt wCG register */
6139 OP_RXA
, /* XScale accumulator register */
6141 OP_REGLST
, /* ARM register list */
6142 OP_VRSLST
, /* VFP single-precision register list */
6143 OP_VRDLST
, /* VFP double-precision register list */
6144 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6145 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6146 OP_NSTRLST
, /* Neon element/structure list */
6148 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6149 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6150 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6151 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6152 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6153 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6154 OP_VMOV
, /* Neon VMOV operands. */
6155 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6156 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6157 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6159 OP_I0
, /* immediate zero */
6160 OP_I7
, /* immediate value 0 .. 7 */
6161 OP_I15
, /* 0 .. 15 */
6162 OP_I16
, /* 1 .. 16 */
6163 OP_I16z
, /* 0 .. 16 */
6164 OP_I31
, /* 0 .. 31 */
6165 OP_I31w
, /* 0 .. 31, optional trailing ! */
6166 OP_I32
, /* 1 .. 32 */
6167 OP_I32z
, /* 0 .. 32 */
6168 OP_I63
, /* 0 .. 63 */
6169 OP_I63s
, /* -64 .. 63 */
6170 OP_I64
, /* 1 .. 64 */
6171 OP_I64z
, /* 0 .. 64 */
6172 OP_I255
, /* 0 .. 255 */
6174 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6175 OP_I7b
, /* 0 .. 7 */
6176 OP_I15b
, /* 0 .. 15 */
6177 OP_I31b
, /* 0 .. 31 */
6179 OP_SH
, /* shifter operand */
6180 OP_SHG
, /* shifter operand with possible group relocation */
6181 OP_ADDR
, /* Memory address expression (any mode) */
6182 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6183 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6184 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6185 OP_EXP
, /* arbitrary expression */
6186 OP_EXPi
, /* same, with optional immediate prefix */
6187 OP_EXPr
, /* same, with optional relocation suffix */
6188 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6190 OP_CPSF
, /* CPS flags */
6191 OP_ENDI
, /* Endianness specifier */
6192 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6193 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6194 OP_COND
, /* conditional code */
6195 OP_TB
, /* Table branch. */
6197 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6199 OP_RRnpc_I0
, /* ARM register or literal 0 */
6200 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6201 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6202 OP_RF_IF
, /* FPA register or immediate */
6203 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6204 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6206 /* Optional operands. */
6207 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6208 OP_oI31b
, /* 0 .. 31 */
6209 OP_oI32b
, /* 1 .. 32 */
6210 OP_oI32z
, /* 0 .. 32 */
6211 OP_oIffffb
, /* 0 .. 65535 */
6212 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6214 OP_oRR
, /* ARM register */
6215 OP_oRRnpc
, /* ARM register, not the PC */
6216 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6217 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6218 OP_oRND
, /* Optional Neon double precision register */
6219 OP_oRNQ
, /* Optional Neon quad precision register */
6220 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6221 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6222 OP_oSHll
, /* LSL immediate */
6223 OP_oSHar
, /* ASR immediate */
6224 OP_oSHllar
, /* LSL or ASR immediate */
6225 OP_oROR
, /* ROR 0/8/16/24 */
6226 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6228 /* Some pre-defined mixed (ARM/THUMB) operands. */
6229 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6230 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6231 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6233 OP_FIRST_OPTIONAL
= OP_oI7b
6236 /* Generic instruction operand parser. This does no encoding and no
6237 semantic validation; it merely squirrels values away in the inst
6238 structure. Returns SUCCESS or FAIL depending on whether the
6239 specified grammar matched. */
6241 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6243 unsigned const int *upat
= pattern
;
6244 char *backtrack_pos
= 0;
6245 const char *backtrack_error
= 0;
6246 int i
, val
= 0, backtrack_index
= 0;
6247 enum arm_reg_type rtype
;
6248 parse_operand_result result
;
6249 unsigned int op_parse_code
;
6251 #define po_char_or_fail(chr) \
6254 if (skip_past_char (&str, chr) == FAIL) \
6259 #define po_reg_or_fail(regtype) \
6262 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6263 & inst.operands[i].vectype); \
6266 first_error (_(reg_expected_msgs[regtype])); \
6269 inst.operands[i].reg = val; \
6270 inst.operands[i].isreg = 1; \
6271 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6272 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6273 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6274 || rtype == REG_TYPE_VFD \
6275 || rtype == REG_TYPE_NQ); \
6279 #define po_reg_or_goto(regtype, label) \
6282 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6283 & inst.operands[i].vectype); \
6287 inst.operands[i].reg = val; \
6288 inst.operands[i].isreg = 1; \
6289 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6290 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6291 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6292 || rtype == REG_TYPE_VFD \
6293 || rtype == REG_TYPE_NQ); \
6297 #define po_imm_or_fail(min, max, popt) \
6300 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6302 inst.operands[i].imm = val; \
6306 #define po_scalar_or_goto(elsz, label) \
6309 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6312 inst.operands[i].reg = val; \
6313 inst.operands[i].isscalar = 1; \
6317 #define po_misc_or_fail(expr) \
6325 #define po_misc_or_fail_no_backtrack(expr) \
6329 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6330 backtrack_pos = 0; \
6331 if (result != PARSE_OPERAND_SUCCESS) \
6336 #define po_barrier_or_imm(str) \
6339 val = parse_barrier (&str); \
6342 if (ISALPHA (*str)) \
6349 if ((inst.instruction & 0xf0) == 0x60 \
6352 /* ISB can only take SY as an option. */ \
6353 inst.error = _("invalid barrier type"); \
6360 skip_whitespace (str
);
6362 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6364 op_parse_code
= upat
[i
];
6365 if (op_parse_code
>= 1<<16)
6366 op_parse_code
= thumb
? (op_parse_code
>> 16)
6367 : (op_parse_code
& ((1<<16)-1));
6369 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6371 /* Remember where we are in case we need to backtrack. */
6372 gas_assert (!backtrack_pos
);
6373 backtrack_pos
= str
;
6374 backtrack_error
= inst
.error
;
6375 backtrack_index
= i
;
6378 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6379 po_char_or_fail (',');
6381 switch (op_parse_code
)
6389 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6390 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6391 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6392 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6393 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6394 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6396 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6398 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6400 /* Also accept generic coprocessor regs for unknown registers. */
6402 po_reg_or_fail (REG_TYPE_CN
);
6404 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6405 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6406 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6407 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6408 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6409 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6410 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6411 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6412 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6413 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6415 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6417 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6418 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6420 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6422 /* Neon scalar. Using an element size of 8 means that some invalid
6423 scalars are accepted here, so deal with those in later code. */
6424 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6428 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6431 po_imm_or_fail (0, 0, TRUE
);
6436 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6441 po_scalar_or_goto (8, try_rr
);
6444 po_reg_or_fail (REG_TYPE_RN
);
6450 po_scalar_or_goto (8, try_nsdq
);
6453 po_reg_or_fail (REG_TYPE_NSDQ
);
6459 po_scalar_or_goto (8, try_ndq
);
6462 po_reg_or_fail (REG_TYPE_NDQ
);
6468 po_scalar_or_goto (8, try_vfd
);
6471 po_reg_or_fail (REG_TYPE_VFD
);
6476 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6477 not careful then bad things might happen. */
6478 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6483 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6486 /* There's a possibility of getting a 64-bit immediate here, so
6487 we need special handling. */
6488 if (parse_big_immediate (&str
, i
) == FAIL
)
6490 inst
.error
= _("immediate value is out of range");
6498 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6501 po_imm_or_fail (0, 63, TRUE
);
6506 po_char_or_fail ('[');
6507 po_reg_or_fail (REG_TYPE_RN
);
6508 po_char_or_fail (']');
6514 po_reg_or_fail (REG_TYPE_RN
);
6515 if (skip_past_char (&str
, '!') == SUCCESS
)
6516 inst
.operands
[i
].writeback
= 1;
6520 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6521 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6522 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6523 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6524 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6525 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6526 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6527 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6528 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6529 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6530 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6531 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6533 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6535 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6536 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6538 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6539 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6540 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6541 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6543 /* Immediate variants */
6545 po_char_or_fail ('{');
6546 po_imm_or_fail (0, 255, TRUE
);
6547 po_char_or_fail ('}');
6551 /* The expression parser chokes on a trailing !, so we have
6552 to find it first and zap it. */
6555 while (*s
&& *s
!= ',')
6560 inst
.operands
[i
].writeback
= 1;
6562 po_imm_or_fail (0, 31, TRUE
);
6570 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6575 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6580 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6582 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6584 val
= parse_reloc (&str
);
6587 inst
.error
= _("unrecognized relocation suffix");
6590 else if (val
!= BFD_RELOC_UNUSED
)
6592 inst
.operands
[i
].imm
= val
;
6593 inst
.operands
[i
].hasreloc
= 1;
6598 /* Operand for MOVW or MOVT. */
6600 po_misc_or_fail (parse_half (&str
));
6603 /* Register or expression. */
6604 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6605 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6607 /* Register or immediate. */
6608 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6609 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6611 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6613 if (!is_immediate_prefix (*str
))
6616 val
= parse_fpa_immediate (&str
);
6619 /* FPA immediates are encoded as registers 8-15.
6620 parse_fpa_immediate has already applied the offset. */
6621 inst
.operands
[i
].reg
= val
;
6622 inst
.operands
[i
].isreg
= 1;
6625 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6626 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6628 /* Two kinds of register. */
6631 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6633 || (rege
->type
!= REG_TYPE_MMXWR
6634 && rege
->type
!= REG_TYPE_MMXWC
6635 && rege
->type
!= REG_TYPE_MMXWCG
))
6637 inst
.error
= _("iWMMXt data or control register expected");
6640 inst
.operands
[i
].reg
= rege
->number
;
6641 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6647 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6649 || (rege
->type
!= REG_TYPE_MMXWC
6650 && rege
->type
!= REG_TYPE_MMXWCG
))
6652 inst
.error
= _("iWMMXt control register expected");
6655 inst
.operands
[i
].reg
= rege
->number
;
6656 inst
.operands
[i
].isreg
= 1;
6661 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6662 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6663 case OP_oROR
: val
= parse_ror (&str
); break;
6664 case OP_COND
: val
= parse_cond (&str
); break;
6665 case OP_oBARRIER_I15
:
6666 po_barrier_or_imm (str
); break;
6668 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6674 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6675 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6677 inst
.error
= _("Banked registers are not available with this "
6683 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6687 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6690 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6692 if (strncasecmp (str
, "APSR_", 5) == 0)
6699 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6700 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6701 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6702 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6703 default: found
= 16;
6707 inst
.operands
[i
].isvec
= 1;
6708 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6709 inst
.operands
[i
].reg
= REG_PC
;
6716 po_misc_or_fail (parse_tb (&str
));
6719 /* Register lists. */
6721 val
= parse_reg_list (&str
);
6724 inst
.operands
[1].writeback
= 1;
6730 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6734 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6738 /* Allow Q registers too. */
6739 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6744 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6746 inst
.operands
[i
].issingle
= 1;
6751 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6756 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6757 &inst
.operands
[i
].vectype
);
6760 /* Addressing modes */
6762 po_misc_or_fail (parse_address (&str
, i
));
6766 po_misc_or_fail_no_backtrack (
6767 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6771 po_misc_or_fail_no_backtrack (
6772 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6776 po_misc_or_fail_no_backtrack (
6777 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6781 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6785 po_misc_or_fail_no_backtrack (
6786 parse_shifter_operand_group_reloc (&str
, i
));
6790 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6794 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6798 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6802 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6805 /* Various value-based sanity checks and shared operations. We
6806 do not signal immediate failures for the register constraints;
6807 this allows a syntax error to take precedence. */
6808 switch (op_parse_code
)
6816 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6817 inst
.error
= BAD_PC
;
6822 if (inst
.operands
[i
].isreg
)
6824 if (inst
.operands
[i
].reg
== REG_PC
)
6825 inst
.error
= BAD_PC
;
6826 else if (inst
.operands
[i
].reg
== REG_SP
)
6827 inst
.error
= BAD_SP
;
6832 if (inst
.operands
[i
].isreg
6833 && inst
.operands
[i
].reg
== REG_PC
6834 && (inst
.operands
[i
].writeback
|| thumb
))
6835 inst
.error
= BAD_PC
;
6844 case OP_oBARRIER_I15
:
6853 inst
.operands
[i
].imm
= val
;
6860 /* If we get here, this operand was successfully parsed. */
6861 inst
.operands
[i
].present
= 1;
6865 inst
.error
= BAD_ARGS
;
6870 /* The parse routine should already have set inst.error, but set a
6871 default here just in case. */
6873 inst
.error
= _("syntax error");
6877 /* Do not backtrack over a trailing optional argument that
6878 absorbed some text. We will only fail again, with the
6879 'garbage following instruction' error message, which is
6880 probably less helpful than the current one. */
6881 if (backtrack_index
== i
&& backtrack_pos
!= str
6882 && upat
[i
+1] == OP_stop
)
6885 inst
.error
= _("syntax error");
6889 /* Try again, skipping the optional argument at backtrack_pos. */
6890 str
= backtrack_pos
;
6891 inst
.error
= backtrack_error
;
6892 inst
.operands
[backtrack_index
].present
= 0;
6893 i
= backtrack_index
;
6897 /* Check that we have parsed all the arguments. */
6898 if (*str
!= '\0' && !inst
.error
)
6899 inst
.error
= _("garbage following instruction");
6901 return inst
.error
? FAIL
: SUCCESS
;
6904 #undef po_char_or_fail
6905 #undef po_reg_or_fail
6906 #undef po_reg_or_goto
6907 #undef po_imm_or_fail
6908 #undef po_scalar_or_fail
6909 #undef po_barrier_or_imm
6911 /* Shorthand macro for instruction encoding functions issuing errors. */
6912 #define constraint(expr, err) \
6923 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6924 instructions are unpredictable if these registers are used. This
6925 is the BadReg predicate in ARM's Thumb-2 documentation. */
6926 #define reject_bad_reg(reg) \
6928 if (reg == REG_SP || reg == REG_PC) \
6930 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6935 /* If REG is R13 (the stack pointer), warn that its use is
6937 #define warn_deprecated_sp(reg) \
6939 if (warn_on_deprecated && reg == REG_SP) \
6940 as_warn (_("use of r13 is deprecated")); \
6943 /* Functions for operand encoding. ARM, then Thumb. */
6945 #define rotate_left(v, n) (v << n | v >> (32 - n))
6947 /* If VAL can be encoded in the immediate field of an ARM instruction,
6948 return the encoded form. Otherwise, return FAIL. */
6951 encode_arm_immediate (unsigned int val
)
6955 for (i
= 0; i
< 32; i
+= 2)
6956 if ((a
= rotate_left (val
, i
)) <= 0xff)
6957 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6962 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6963 return the encoded form. Otherwise, return FAIL. */
6965 encode_thumb32_immediate (unsigned int val
)
6972 for (i
= 1; i
<= 24; i
++)
6975 if ((val
& ~(0xff << i
)) == 0)
6976 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6980 if (val
== ((a
<< 16) | a
))
6982 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6986 if (val
== ((a
<< 16) | a
))
6987 return 0x200 | (a
>> 8);
6991 /* Encode a VFP SP or DP register number into inst.instruction. */
6994 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6996 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6999 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7002 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7005 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7010 first_error (_("D register out of range for selected VFP version"));
7018 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7022 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7026 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7030 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7034 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7038 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7046 /* Encode a <shift> in an ARM-format instruction. The immediate,
7047 if any, is handled by md_apply_fix. */
7049 encode_arm_shift (int i
)
7051 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7052 inst
.instruction
|= SHIFT_ROR
<< 5;
7055 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7056 if (inst
.operands
[i
].immisreg
)
7058 inst
.instruction
|= SHIFT_BY_REG
;
7059 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7062 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7067 encode_arm_shifter_operand (int i
)
7069 if (inst
.operands
[i
].isreg
)
7071 inst
.instruction
|= inst
.operands
[i
].reg
;
7072 encode_arm_shift (i
);
7076 inst
.instruction
|= INST_IMMEDIATE
;
7077 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7078 inst
.instruction
|= inst
.operands
[i
].imm
;
7082 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7084 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7087 Generate an error if the operand is not a register. */
7088 constraint (!inst
.operands
[i
].isreg
,
7089 _("Instruction does not support =N addresses"));
7091 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7093 if (inst
.operands
[i
].preind
)
7097 inst
.error
= _("instruction does not accept preindexed addressing");
7100 inst
.instruction
|= PRE_INDEX
;
7101 if (inst
.operands
[i
].writeback
)
7102 inst
.instruction
|= WRITE_BACK
;
7105 else if (inst
.operands
[i
].postind
)
7107 gas_assert (inst
.operands
[i
].writeback
);
7109 inst
.instruction
|= WRITE_BACK
;
7111 else /* unindexed - only for coprocessor */
7113 inst
.error
= _("instruction does not accept unindexed addressing");
7117 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7118 && (((inst
.instruction
& 0x000f0000) >> 16)
7119 == ((inst
.instruction
& 0x0000f000) >> 12)))
7120 as_warn ((inst
.instruction
& LOAD_BIT
)
7121 ? _("destination register same as write-back base")
7122 : _("source register same as write-back base"));
7125 /* inst.operands[i] was set up by parse_address. Encode it into an
7126 ARM-format mode 2 load or store instruction. If is_t is true,
7127 reject forms that cannot be used with a T instruction (i.e. not
7130 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7132 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7134 encode_arm_addr_mode_common (i
, is_t
);
7136 if (inst
.operands
[i
].immisreg
)
7138 constraint ((inst
.operands
[i
].imm
== REG_PC
7139 || (is_pc
&& inst
.operands
[i
].writeback
)),
7141 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7142 inst
.instruction
|= inst
.operands
[i
].imm
;
7143 if (!inst
.operands
[i
].negative
)
7144 inst
.instruction
|= INDEX_UP
;
7145 if (inst
.operands
[i
].shifted
)
7147 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7148 inst
.instruction
|= SHIFT_ROR
<< 5;
7151 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7152 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7156 else /* immediate offset in inst.reloc */
7158 if (is_pc
&& !inst
.reloc
.pc_rel
)
7160 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7162 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7163 cannot use PC in addressing.
7164 PC cannot be used in writeback addressing, either. */
7165 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7168 /* Use of PC in str is deprecated for ARMv7. */
7169 if (warn_on_deprecated
7171 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7172 as_warn (_("use of PC in this instruction is deprecated"));
7175 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7177 /* Prefer + for zero encoded value. */
7178 if (!inst
.operands
[i
].negative
)
7179 inst
.instruction
|= INDEX_UP
;
7180 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7185 /* inst.operands[i] was set up by parse_address. Encode it into an
7186 ARM-format mode 3 load or store instruction. Reject forms that
7187 cannot be used with such instructions. If is_t is true, reject
7188 forms that cannot be used with a T instruction (i.e. not
7191 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7193 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7195 inst
.error
= _("instruction does not accept scaled register index");
7199 encode_arm_addr_mode_common (i
, is_t
);
7201 if (inst
.operands
[i
].immisreg
)
7203 constraint ((inst
.operands
[i
].imm
== REG_PC
7204 || inst
.operands
[i
].reg
== REG_PC
),
7206 inst
.instruction
|= inst
.operands
[i
].imm
;
7207 if (!inst
.operands
[i
].negative
)
7208 inst
.instruction
|= INDEX_UP
;
7210 else /* immediate offset in inst.reloc */
7212 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7213 && inst
.operands
[i
].writeback
),
7215 inst
.instruction
|= HWOFFSET_IMM
;
7216 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7218 /* Prefer + for zero encoded value. */
7219 if (!inst
.operands
[i
].negative
)
7220 inst
.instruction
|= INDEX_UP
;
7222 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7227 /* inst.operands[i] was set up by parse_address. Encode it into an
7228 ARM-format instruction. Reject all forms which cannot be encoded
7229 into a coprocessor load/store instruction. If wb_ok is false,
7230 reject use of writeback; if unind_ok is false, reject use of
7231 unindexed addressing. If reloc_override is not 0, use it instead
7232 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7233 (in which case it is preserved). */
7236 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7238 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7240 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7242 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7244 gas_assert (!inst
.operands
[i
].writeback
);
7247 inst
.error
= _("instruction does not support unindexed addressing");
7250 inst
.instruction
|= inst
.operands
[i
].imm
;
7251 inst
.instruction
|= INDEX_UP
;
7255 if (inst
.operands
[i
].preind
)
7256 inst
.instruction
|= PRE_INDEX
;
7258 if (inst
.operands
[i
].writeback
)
7260 if (inst
.operands
[i
].reg
== REG_PC
)
7262 inst
.error
= _("pc may not be used with write-back");
7267 inst
.error
= _("instruction does not support writeback");
7270 inst
.instruction
|= WRITE_BACK
;
7274 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7275 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7276 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7277 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7280 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7282 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7285 /* Prefer + for zero encoded value. */
7286 if (!inst
.operands
[i
].negative
)
7287 inst
.instruction
|= INDEX_UP
;
7292 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7293 Determine whether it can be performed with a move instruction; if
7294 it can, convert inst.instruction to that move instruction and
7295 return TRUE; if it can't, convert inst.instruction to a literal-pool
7296 load and return FALSE. If this is not a valid thing to do in the
7297 current context, set inst.error and return TRUE.
7299 inst.operands[i] describes the destination register. */
7302 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7307 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7311 if ((inst
.instruction
& tbit
) == 0)
7313 inst
.error
= _("invalid pseudo operation");
7316 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7318 inst
.error
= _("constant expression expected");
7321 if (inst
.reloc
.exp
.X_op
== O_constant
)
7325 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7327 /* This can be done with a mov(1) instruction. */
7328 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7329 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7335 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7338 /* This can be done with a mov instruction. */
7339 inst
.instruction
&= LITERAL_MASK
;
7340 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7341 inst
.instruction
|= value
& 0xfff;
7345 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7348 /* This can be done with a mvn instruction. */
7349 inst
.instruction
&= LITERAL_MASK
;
7350 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7351 inst
.instruction
|= value
& 0xfff;
7357 if (add_to_lit_pool () == FAIL
)
7359 inst
.error
= _("literal pool insertion failed");
7362 inst
.operands
[1].reg
= REG_PC
;
7363 inst
.operands
[1].isreg
= 1;
7364 inst
.operands
[1].preind
= 1;
7365 inst
.reloc
.pc_rel
= 1;
7366 inst
.reloc
.type
= (thumb_p
7367 ? BFD_RELOC_ARM_THUMB_OFFSET
7369 ? BFD_RELOC_ARM_HWLITERAL
7370 : BFD_RELOC_ARM_LITERAL
));
7374 /* Functions for instruction encoding, sorted by sub-architecture.
7375 First some generics; their names are taken from the conventional
7376 bit positions for register arguments in ARM format instructions. */
7386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7392 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7393 inst
.instruction
|= inst
.operands
[1].reg
;
7399 inst
.instruction
|= inst
.operands
[0].reg
;
7400 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7406 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7407 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7413 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7414 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7418 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
7420 if (ARM_CPU_IS_ANY (cpu_variant
))
7422 as_warn ("%s", msg
);
7425 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
7437 unsigned Rn
= inst
.operands
[2].reg
;
7438 /* Enforce restrictions on SWP instruction. */
7439 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7441 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7442 _("Rn must not overlap other operands"));
7444 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7446 if (!check_obsolete (&arm_ext_v8
,
7447 _("swp{b} use is obsoleted for ARMv8 and later"))
7448 && warn_on_deprecated
7449 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
7450 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7453 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7454 inst
.instruction
|= inst
.operands
[1].reg
;
7455 inst
.instruction
|= Rn
<< 16;
7461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7462 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7463 inst
.instruction
|= inst
.operands
[2].reg
;
7469 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7470 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7471 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7472 || inst
.reloc
.exp
.X_add_number
!= 0),
7474 inst
.instruction
|= inst
.operands
[0].reg
;
7475 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7476 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7482 inst
.instruction
|= inst
.operands
[0].imm
;
7488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7489 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7492 /* ARM instructions, in alphabetical order by function name (except
7493 that wrapper functions appear immediately after the function they
7496 /* This is a pseudo-op of the form "adr rd, label" to be converted
7497 into a relative address of the form "add rd, pc, #label-.-8". */
7502 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7504 /* Frag hacking will turn this into a sub instruction if the offset turns
7505 out to be negative. */
7506 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7507 inst
.reloc
.pc_rel
= 1;
7508 inst
.reloc
.exp
.X_add_number
-= 8;
7511 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7512 into a relative address of the form:
7513 add rd, pc, #low(label-.-8)"
7514 add rd, rd, #high(label-.-8)" */
7519 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7521 /* Frag hacking will turn this into a sub instruction if the offset turns
7522 out to be negative. */
7523 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7524 inst
.reloc
.pc_rel
= 1;
7525 inst
.size
= INSN_SIZE
* 2;
7526 inst
.reloc
.exp
.X_add_number
-= 8;
7532 if (!inst
.operands
[1].present
)
7533 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7535 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7536 encode_arm_shifter_operand (2);
7542 if (inst
.operands
[0].present
)
7544 constraint ((inst
.instruction
& 0xf0) != 0x40
7545 && inst
.operands
[0].imm
> 0xf
7546 && inst
.operands
[0].imm
< 0x0,
7547 _("bad barrier type"));
7548 inst
.instruction
|= inst
.operands
[0].imm
;
7551 inst
.instruction
|= 0xf;
7557 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7558 constraint (msb
> 32, _("bit-field extends past end of register"));
7559 /* The instruction encoding stores the LSB and MSB,
7560 not the LSB and width. */
7561 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7562 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7563 inst
.instruction
|= (msb
- 1) << 16;
7571 /* #0 in second position is alternative syntax for bfc, which is
7572 the same instruction but with REG_PC in the Rm field. */
7573 if (!inst
.operands
[1].isreg
)
7574 inst
.operands
[1].reg
= REG_PC
;
7576 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7577 constraint (msb
> 32, _("bit-field extends past end of register"));
7578 /* The instruction encoding stores the LSB and MSB,
7579 not the LSB and width. */
7580 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7581 inst
.instruction
|= inst
.operands
[1].reg
;
7582 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7583 inst
.instruction
|= (msb
- 1) << 16;
7589 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7590 _("bit-field extends past end of register"));
7591 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7592 inst
.instruction
|= inst
.operands
[1].reg
;
7593 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7594 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7597 /* ARM V5 breakpoint instruction (argument parse)
7598 BKPT <16 bit unsigned immediate>
7599 Instruction is not conditional.
7600 The bit pattern given in insns[] has the COND_ALWAYS condition,
7601 and it is an error if the caller tried to override that. */
7606 /* Top 12 of 16 bits to bits 19:8. */
7607 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7609 /* Bottom 4 of 16 bits to bits 3:0. */
7610 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7614 encode_branch (int default_reloc
)
7616 if (inst
.operands
[0].hasreloc
)
7618 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7619 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7620 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7621 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7622 ? BFD_RELOC_ARM_PLT32
7623 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7626 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7627 inst
.reloc
.pc_rel
= 1;
7634 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7635 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7638 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7645 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7647 if (inst
.cond
== COND_ALWAYS
)
7648 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7650 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7654 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7657 /* ARM V5 branch-link-exchange instruction (argument parse)
7658 BLX <target_addr> ie BLX(1)
7659 BLX{<condition>} <Rm> ie BLX(2)
7660 Unfortunately, there are two different opcodes for this mnemonic.
7661 So, the insns[].value is not used, and the code here zaps values
7662 into inst.instruction.
7663 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7668 if (inst
.operands
[0].isreg
)
7670 /* Arg is a register; the opcode provided by insns[] is correct.
7671 It is not illegal to do "blx pc", just useless. */
7672 if (inst
.operands
[0].reg
== REG_PC
)
7673 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7675 inst
.instruction
|= inst
.operands
[0].reg
;
7679 /* Arg is an address; this instruction cannot be executed
7680 conditionally, and the opcode must be adjusted.
7681 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7682 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7683 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7684 inst
.instruction
= 0xfa000000;
7685 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7692 bfd_boolean want_reloc
;
7694 if (inst
.operands
[0].reg
== REG_PC
)
7695 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7697 inst
.instruction
|= inst
.operands
[0].reg
;
7698 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7699 it is for ARMv4t or earlier. */
7700 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7701 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7705 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7710 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7714 /* ARM v5TEJ. Jump to Jazelle code. */
7719 if (inst
.operands
[0].reg
== REG_PC
)
7720 as_tsktsk (_("use of r15 in bxj is not really useful"));
7722 inst
.instruction
|= inst
.operands
[0].reg
;
7725 /* Co-processor data operation:
7726 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7727 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7731 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7732 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7733 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7734 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7735 inst
.instruction
|= inst
.operands
[4].reg
;
7736 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7742 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7743 encode_arm_shifter_operand (1);
7746 /* Transfer between coprocessor and ARM registers.
7747 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7752 No special properties. */
7754 struct deprecated_coproc_regs_s
7761 arm_feature_set deprecated
;
7762 arm_feature_set obsoleted
;
7763 const char *dep_msg
;
7764 const char *obs_msg
;
7767 #define DEPR_ACCESS_V8 \
7768 N_("This coprocessor register access is deprecated in ARMv8")
7770 /* Table of all deprecated coprocessor registers. */
7771 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
7773 {15, 0, 7, 10, 5, /* CP15DMB. */
7774 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7775 DEPR_ACCESS_V8
, NULL
},
7776 {15, 0, 7, 10, 4, /* CP15DSB. */
7777 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7778 DEPR_ACCESS_V8
, NULL
},
7779 {15, 0, 7, 5, 4, /* CP15ISB. */
7780 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7781 DEPR_ACCESS_V8
, NULL
},
7782 {14, 6, 1, 0, 0, /* TEEHBR. */
7783 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7784 DEPR_ACCESS_V8
, NULL
},
7785 {14, 6, 0, 0, 0, /* TEECR. */
7786 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7787 DEPR_ACCESS_V8
, NULL
},
7790 #undef DEPR_ACCESS_V8
7792 static const size_t deprecated_coproc_reg_count
=
7793 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
7801 Rd
= inst
.operands
[2].reg
;
7804 if (inst
.instruction
== 0xee000010
7805 || inst
.instruction
== 0xfe000010)
7807 reject_bad_reg (Rd
);
7810 constraint (Rd
== REG_SP
, BAD_SP
);
7815 if (inst
.instruction
== 0xe000010)
7816 constraint (Rd
== REG_PC
, BAD_PC
);
7819 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
7821 const struct deprecated_coproc_regs_s
*r
=
7822 deprecated_coproc_regs
+ i
;
7824 if (inst
.operands
[0].reg
== r
->cp
7825 && inst
.operands
[1].imm
== r
->opc1
7826 && inst
.operands
[3].reg
== r
->crn
7827 && inst
.operands
[4].reg
== r
->crm
7828 && inst
.operands
[5].imm
== r
->opc2
)
7830 if (!check_obsolete (&r
->obsoleted
, r
->obs_msg
)
7831 && warn_on_deprecated
7832 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
7833 as_warn ("%s", r
->dep_msg
);
7837 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7838 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7839 inst
.instruction
|= Rd
<< 12;
7840 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7841 inst
.instruction
|= inst
.operands
[4].reg
;
7842 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7845 /* Transfer between coprocessor register and pair of ARM registers.
7846 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7851 Two XScale instructions are special cases of these:
7853 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7854 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7856 Result unpredictable if Rd or Rn is R15. */
7863 Rd
= inst
.operands
[2].reg
;
7864 Rn
= inst
.operands
[3].reg
;
7868 reject_bad_reg (Rd
);
7869 reject_bad_reg (Rn
);
7873 constraint (Rd
== REG_PC
, BAD_PC
);
7874 constraint (Rn
== REG_PC
, BAD_PC
);
7877 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7878 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7879 inst
.instruction
|= Rd
<< 12;
7880 inst
.instruction
|= Rn
<< 16;
7881 inst
.instruction
|= inst
.operands
[4].reg
;
7887 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7888 if (inst
.operands
[1].present
)
7890 inst
.instruction
|= CPSI_MMOD
;
7891 inst
.instruction
|= inst
.operands
[1].imm
;
7898 inst
.instruction
|= inst
.operands
[0].imm
;
7904 unsigned Rd
, Rn
, Rm
;
7906 Rd
= inst
.operands
[0].reg
;
7907 Rn
= (inst
.operands
[1].present
7908 ? inst
.operands
[1].reg
: Rd
);
7909 Rm
= inst
.operands
[2].reg
;
7911 constraint ((Rd
== REG_PC
), BAD_PC
);
7912 constraint ((Rn
== REG_PC
), BAD_PC
);
7913 constraint ((Rm
== REG_PC
), BAD_PC
);
7915 inst
.instruction
|= Rd
<< 16;
7916 inst
.instruction
|= Rn
<< 0;
7917 inst
.instruction
|= Rm
<< 8;
7923 /* There is no IT instruction in ARM mode. We
7924 process it to do the validation as if in
7925 thumb mode, just in case the code gets
7926 assembled for thumb using the unified syntax. */
7931 set_it_insn_type (IT_INSN
);
7932 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7933 now_it
.cc
= inst
.operands
[0].imm
;
7937 /* If there is only one register in the register list,
7938 then return its register number. Otherwise return -1. */
7940 only_one_reg_in_list (int range
)
7942 int i
= ffs (range
) - 1;
7943 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
7947 encode_ldmstm(int from_push_pop_mnem
)
7949 int base_reg
= inst
.operands
[0].reg
;
7950 int range
= inst
.operands
[1].imm
;
7953 inst
.instruction
|= base_reg
<< 16;
7954 inst
.instruction
|= range
;
7956 if (inst
.operands
[1].writeback
)
7957 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7959 if (inst
.operands
[0].writeback
)
7961 inst
.instruction
|= WRITE_BACK
;
7962 /* Check for unpredictable uses of writeback. */
7963 if (inst
.instruction
& LOAD_BIT
)
7965 /* Not allowed in LDM type 2. */
7966 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7967 && ((range
& (1 << REG_PC
)) == 0))
7968 as_warn (_("writeback of base register is UNPREDICTABLE"));
7969 /* Only allowed if base reg not in list for other types. */
7970 else if (range
& (1 << base_reg
))
7971 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7975 /* Not allowed for type 2. */
7976 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7977 as_warn (_("writeback of base register is UNPREDICTABLE"));
7978 /* Only allowed if base reg not in list, or first in list. */
7979 else if ((range
& (1 << base_reg
))
7980 && (range
& ((1 << base_reg
) - 1)))
7981 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7985 /* If PUSH/POP has only one register, then use the A2 encoding. */
7986 one_reg
= only_one_reg_in_list (range
);
7987 if (from_push_pop_mnem
&& one_reg
>= 0)
7989 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
7991 inst
.instruction
&= A_COND_MASK
;
7992 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
7993 inst
.instruction
|= one_reg
<< 12;
8000 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8003 /* ARMv5TE load-consecutive (argument parse)
8012 constraint (inst
.operands
[0].reg
% 2 != 0,
8013 _("first transfer register must be even"));
8014 constraint (inst
.operands
[1].present
8015 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8016 _("can only transfer two consecutive registers"));
8017 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8018 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8020 if (!inst
.operands
[1].present
)
8021 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8023 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8024 register and the first register written; we have to diagnose
8025 overlap between the base and the second register written here. */
8027 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8028 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8029 as_warn (_("base register written back, and overlaps "
8030 "second transfer register"));
8032 if (!(inst
.instruction
& V4_STR_BIT
))
8034 /* For an index-register load, the index register must not overlap the
8035 destination (even if not write-back). */
8036 if (inst
.operands
[2].immisreg
8037 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8038 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8039 as_warn (_("index register overlaps transfer register"));
8041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8042 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8048 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8049 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8050 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8051 || inst
.operands
[1].negative
8052 /* This can arise if the programmer has written
8054 or if they have mistakenly used a register name as the last
8057 It is very difficult to distinguish between these two cases
8058 because "rX" might actually be a label. ie the register
8059 name has been occluded by a symbol of the same name. So we
8060 just generate a general 'bad addressing mode' type error
8061 message and leave it up to the programmer to discover the
8062 true cause and fix their mistake. */
8063 || (inst
.operands
[1].reg
== REG_PC
),
8066 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8067 || inst
.reloc
.exp
.X_add_number
!= 0,
8068 _("offset must be zero in ARM encoding"));
8070 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8073 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8074 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8080 constraint (inst
.operands
[0].reg
% 2 != 0,
8081 _("even register required"));
8082 constraint (inst
.operands
[1].present
8083 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8084 _("can only load two consecutive registers"));
8085 /* If op 1 were present and equal to PC, this function wouldn't
8086 have been called in the first place. */
8087 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8090 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8093 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8094 which is not a multiple of four is UNPREDICTABLE. */
8096 check_ldr_r15_aligned (void)
8098 constraint (!(inst
.operands
[1].immisreg
)
8099 && (inst
.operands
[0].reg
== REG_PC
8100 && inst
.operands
[1].reg
== REG_PC
8101 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8102 _("ldr to register 15 must be 4-byte alligned"));
8108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8109 if (!inst
.operands
[1].isreg
)
8110 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
8112 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8113 check_ldr_r15_aligned ();
8119 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8121 if (inst
.operands
[1].preind
)
8123 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8124 || inst
.reloc
.exp
.X_add_number
!= 0,
8125 _("this instruction requires a post-indexed address"));
8127 inst
.operands
[1].preind
= 0;
8128 inst
.operands
[1].postind
= 1;
8129 inst
.operands
[1].writeback
= 1;
8131 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8132 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8135 /* Halfword and signed-byte load/store operations. */
8140 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8141 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8142 if (!inst
.operands
[1].isreg
)
8143 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
8145 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8151 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8153 if (inst
.operands
[1].preind
)
8155 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8156 || inst
.reloc
.exp
.X_add_number
!= 0,
8157 _("this instruction requires a post-indexed address"));
8159 inst
.operands
[1].preind
= 0;
8160 inst
.operands
[1].postind
= 1;
8161 inst
.operands
[1].writeback
= 1;
8163 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8164 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8167 /* Co-processor register load/store.
8168 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8172 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8173 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8174 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8180 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8181 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8182 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8183 && !(inst
.instruction
& 0x00400000))
8184 as_tsktsk (_("Rd and Rm should be different in mla"));
8186 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8187 inst
.instruction
|= inst
.operands
[1].reg
;
8188 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8189 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8195 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8196 encode_arm_shifter_operand (1);
8199 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8206 top
= (inst
.instruction
& 0x00400000) != 0;
8207 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8208 _(":lower16: not allowed this instruction"));
8209 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8210 _(":upper16: not allowed instruction"));
8211 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8212 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8214 imm
= inst
.reloc
.exp
.X_add_number
;
8215 /* The value is in two pieces: 0:11, 16:19. */
8216 inst
.instruction
|= (imm
& 0x00000fff);
8217 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8221 static void do_vfp_nsyn_opcode (const char *);
8224 do_vfp_nsyn_mrs (void)
8226 if (inst
.operands
[0].isvec
)
8228 if (inst
.operands
[1].reg
!= 1)
8229 first_error (_("operand 1 must be FPSCR"));
8230 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8231 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8232 do_vfp_nsyn_opcode ("fmstat");
8234 else if (inst
.operands
[1].isvec
)
8235 do_vfp_nsyn_opcode ("fmrx");
8243 do_vfp_nsyn_msr (void)
8245 if (inst
.operands
[0].isvec
)
8246 do_vfp_nsyn_opcode ("fmxr");
8256 unsigned Rt
= inst
.operands
[0].reg
;
8258 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
8260 inst
.error
= BAD_SP
;
8264 /* APSR_ sets isvec. All other refs to PC are illegal. */
8265 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
8267 inst
.error
= BAD_PC
;
8271 switch (inst
.operands
[1].reg
)
8278 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8281 first_error (_("operand 1 must be a VFP extension System Register"));
8284 inst
.instruction
|= (Rt
<< 12);
8290 unsigned Rt
= inst
.operands
[1].reg
;
8293 reject_bad_reg (Rt
);
8294 else if (Rt
== REG_PC
)
8296 inst
.error
= BAD_PC
;
8300 switch (inst
.operands
[0].reg
)
8305 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8308 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8311 inst
.instruction
|= (Rt
<< 12);
8319 if (do_vfp_nsyn_mrs () == SUCCESS
)
8322 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8323 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8325 if (inst
.operands
[1].isreg
)
8327 br
= inst
.operands
[1].reg
;
8328 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8329 as_bad (_("bad register for mrs"));
8333 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8334 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8336 _("'APSR', 'CPSR' or 'SPSR' expected"));
8337 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8340 inst
.instruction
|= br
;
8343 /* Two possible forms:
8344 "{C|S}PSR_<field>, Rm",
8345 "{C|S}PSR_f, #expression". */
8350 if (do_vfp_nsyn_msr () == SUCCESS
)
8353 inst
.instruction
|= inst
.operands
[0].imm
;
8354 if (inst
.operands
[1].isreg
)
8355 inst
.instruction
|= inst
.operands
[1].reg
;
8358 inst
.instruction
|= INST_IMMEDIATE
;
8359 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8360 inst
.reloc
.pc_rel
= 0;
8367 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8369 if (!inst
.operands
[2].present
)
8370 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8371 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8372 inst
.instruction
|= inst
.operands
[1].reg
;
8373 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8375 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8376 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8377 as_tsktsk (_("Rd and Rm should be different in mul"));
8380 /* Long Multiply Parser
8381 UMULL RdLo, RdHi, Rm, Rs
8382 SMULL RdLo, RdHi, Rm, Rs
8383 UMLAL RdLo, RdHi, Rm, Rs
8384 SMLAL RdLo, RdHi, Rm, Rs. */
8389 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8390 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8391 inst
.instruction
|= inst
.operands
[2].reg
;
8392 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8394 /* rdhi and rdlo must be different. */
8395 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8396 as_tsktsk (_("rdhi and rdlo must be different"));
8398 /* rdhi, rdlo and rm must all be different before armv6. */
8399 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8400 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8401 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8402 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8408 if (inst
.operands
[0].present
8409 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8411 /* Architectural NOP hints are CPSR sets with no bits selected. */
8412 inst
.instruction
&= 0xf0000000;
8413 inst
.instruction
|= 0x0320f000;
8414 if (inst
.operands
[0].present
)
8415 inst
.instruction
|= inst
.operands
[0].imm
;
8419 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8420 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8421 Condition defaults to COND_ALWAYS.
8422 Error if Rd, Rn or Rm are R15. */
8427 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8428 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8429 inst
.instruction
|= inst
.operands
[2].reg
;
8430 if (inst
.operands
[3].present
)
8431 encode_arm_shift (3);
8434 /* ARM V6 PKHTB (Argument Parse). */
8439 if (!inst
.operands
[3].present
)
8441 /* If the shift specifier is omitted, turn the instruction
8442 into pkhbt rd, rm, rn. */
8443 inst
.instruction
&= 0xfff00010;
8444 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8445 inst
.instruction
|= inst
.operands
[1].reg
;
8446 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8451 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8452 inst
.instruction
|= inst
.operands
[2].reg
;
8453 encode_arm_shift (3);
8457 /* ARMv5TE: Preload-Cache
8458 MP Extensions: Preload for write
8462 Syntactically, like LDR with B=1, W=0, L=1. */
8467 constraint (!inst
.operands
[0].isreg
,
8468 _("'[' expected after PLD mnemonic"));
8469 constraint (inst
.operands
[0].postind
,
8470 _("post-indexed expression used in preload instruction"));
8471 constraint (inst
.operands
[0].writeback
,
8472 _("writeback used in preload instruction"));
8473 constraint (!inst
.operands
[0].preind
,
8474 _("unindexed addressing used in preload instruction"));
8475 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8478 /* ARMv7: PLI <addr_mode> */
8482 constraint (!inst
.operands
[0].isreg
,
8483 _("'[' expected after PLI mnemonic"));
8484 constraint (inst
.operands
[0].postind
,
8485 _("post-indexed expression used in preload instruction"));
8486 constraint (inst
.operands
[0].writeback
,
8487 _("writeback used in preload instruction"));
8488 constraint (!inst
.operands
[0].preind
,
8489 _("unindexed addressing used in preload instruction"));
8490 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8491 inst
.instruction
&= ~PRE_INDEX
;
8497 inst
.operands
[1] = inst
.operands
[0];
8498 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8499 inst
.operands
[0].isreg
= 1;
8500 inst
.operands
[0].writeback
= 1;
8501 inst
.operands
[0].reg
= REG_SP
;
8502 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
8505 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8506 word at the specified address and the following word
8508 Unconditionally executed.
8509 Error if Rn is R15. */
8514 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8515 if (inst
.operands
[0].writeback
)
8516 inst
.instruction
|= WRITE_BACK
;
8519 /* ARM V6 ssat (argument parse). */
8524 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8525 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8526 inst
.instruction
|= inst
.operands
[2].reg
;
8528 if (inst
.operands
[3].present
)
8529 encode_arm_shift (3);
8532 /* ARM V6 usat (argument parse). */
8537 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8538 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8539 inst
.instruction
|= inst
.operands
[2].reg
;
8541 if (inst
.operands
[3].present
)
8542 encode_arm_shift (3);
8545 /* ARM V6 ssat16 (argument parse). */
8550 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8551 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8552 inst
.instruction
|= inst
.operands
[2].reg
;
8558 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8559 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8560 inst
.instruction
|= inst
.operands
[2].reg
;
8563 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8564 preserving the other bits.
8566 setend <endian_specifier>, where <endian_specifier> is either
8572 if (warn_on_deprecated
8573 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8574 as_warn (_("setend use is deprecated for ARMv8"));
8576 if (inst
.operands
[0].imm
)
8577 inst
.instruction
|= 0x200;
8583 unsigned int Rm
= (inst
.operands
[1].present
8584 ? inst
.operands
[1].reg
8585 : inst
.operands
[0].reg
);
8587 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8588 inst
.instruction
|= Rm
;
8589 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8591 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8592 inst
.instruction
|= SHIFT_BY_REG
;
8593 /* PR 12854: Error on extraneous shifts. */
8594 constraint (inst
.operands
[2].shifted
,
8595 _("extraneous shift as part of operand to shift insn"));
8598 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8604 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8605 inst
.reloc
.pc_rel
= 0;
8611 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8612 inst
.reloc
.pc_rel
= 0;
8618 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8619 inst
.reloc
.pc_rel
= 0;
8622 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8623 SMLAxy{cond} Rd,Rm,Rs,Rn
8624 SMLAWy{cond} Rd,Rm,Rs,Rn
8625 Error if any register is R15. */
8630 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8631 inst
.instruction
|= inst
.operands
[1].reg
;
8632 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8633 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8636 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8637 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8638 Error if any register is R15.
8639 Warning if Rdlo == Rdhi. */
8644 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8645 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8646 inst
.instruction
|= inst
.operands
[2].reg
;
8647 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8649 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8650 as_tsktsk (_("rdhi and rdlo must be different"));
8653 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8654 SMULxy{cond} Rd,Rm,Rs
8655 Error if any register is R15. */
8660 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8661 inst
.instruction
|= inst
.operands
[1].reg
;
8662 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8665 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8666 the same for both ARM and Thumb-2. */
8673 if (inst
.operands
[0].present
)
8675 reg
= inst
.operands
[0].reg
;
8676 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8681 inst
.instruction
|= reg
<< 16;
8682 inst
.instruction
|= inst
.operands
[1].imm
;
8683 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8684 inst
.instruction
|= WRITE_BACK
;
8687 /* ARM V6 strex (argument parse). */
8692 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8693 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8694 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8695 || inst
.operands
[2].negative
8696 /* See comment in do_ldrex(). */
8697 || (inst
.operands
[2].reg
== REG_PC
),
8700 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8701 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8703 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8704 || inst
.reloc
.exp
.X_add_number
!= 0,
8705 _("offset must be zero in ARM encoding"));
8707 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8708 inst
.instruction
|= inst
.operands
[1].reg
;
8709 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8710 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8716 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8717 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8718 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8719 || inst
.operands
[2].negative
,
8722 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8723 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8731 constraint (inst
.operands
[1].reg
% 2 != 0,
8732 _("even register required"));
8733 constraint (inst
.operands
[2].present
8734 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8735 _("can only store two consecutive registers"));
8736 /* If op 2 were present and equal to PC, this function wouldn't
8737 have been called in the first place. */
8738 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8740 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8741 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8742 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8745 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8746 inst
.instruction
|= inst
.operands
[1].reg
;
8747 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8754 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8755 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8763 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8764 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8769 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8770 extends it to 32-bits, and adds the result to a value in another
8771 register. You can specify a rotation by 0, 8, 16, or 24 bits
8772 before extracting the 16-bit value.
8773 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8774 Condition defaults to COND_ALWAYS.
8775 Error if any register uses R15. */
8780 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8781 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8782 inst
.instruction
|= inst
.operands
[2].reg
;
8783 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8788 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8789 Condition defaults to COND_ALWAYS.
8790 Error if any register uses R15. */
8795 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8796 inst
.instruction
|= inst
.operands
[1].reg
;
8797 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8800 /* VFP instructions. In a logical order: SP variant first, monad
8801 before dyad, arithmetic then move then load/store. */
8804 do_vfp_sp_monadic (void)
8806 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8807 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8811 do_vfp_sp_dyadic (void)
8813 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8814 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8815 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8819 do_vfp_sp_compare_z (void)
8821 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8825 do_vfp_dp_sp_cvt (void)
8827 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8828 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8832 do_vfp_sp_dp_cvt (void)
8834 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8835 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8839 do_vfp_reg_from_sp (void)
8841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8842 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8846 do_vfp_reg2_from_sp2 (void)
8848 constraint (inst
.operands
[2].imm
!= 2,
8849 _("only two consecutive VFP SP registers allowed here"));
8850 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8851 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8852 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8856 do_vfp_sp_from_reg (void)
8858 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8859 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8863 do_vfp_sp2_from_reg2 (void)
8865 constraint (inst
.operands
[0].imm
!= 2,
8866 _("only two consecutive VFP SP registers allowed here"));
8867 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8868 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8869 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8873 do_vfp_sp_ldst (void)
8875 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8876 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8880 do_vfp_dp_ldst (void)
8882 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8883 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8888 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8890 if (inst
.operands
[0].writeback
)
8891 inst
.instruction
|= WRITE_BACK
;
8893 constraint (ldstm_type
!= VFP_LDSTMIA
,
8894 _("this addressing mode requires base-register writeback"));
8895 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8896 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8897 inst
.instruction
|= inst
.operands
[1].imm
;
8901 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8905 if (inst
.operands
[0].writeback
)
8906 inst
.instruction
|= WRITE_BACK
;
8908 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8909 _("this addressing mode requires base-register writeback"));
8911 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8912 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8914 count
= inst
.operands
[1].imm
<< 1;
8915 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8918 inst
.instruction
|= count
;
8922 do_vfp_sp_ldstmia (void)
8924 vfp_sp_ldstm (VFP_LDSTMIA
);
8928 do_vfp_sp_ldstmdb (void)
8930 vfp_sp_ldstm (VFP_LDSTMDB
);
8934 do_vfp_dp_ldstmia (void)
8936 vfp_dp_ldstm (VFP_LDSTMIA
);
8940 do_vfp_dp_ldstmdb (void)
8942 vfp_dp_ldstm (VFP_LDSTMDB
);
8946 do_vfp_xp_ldstmia (void)
8948 vfp_dp_ldstm (VFP_LDSTMIAX
);
8952 do_vfp_xp_ldstmdb (void)
8954 vfp_dp_ldstm (VFP_LDSTMDBX
);
8958 do_vfp_dp_rd_rm (void)
8960 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8961 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8965 do_vfp_dp_rn_rd (void)
8967 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8968 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8972 do_vfp_dp_rd_rn (void)
8974 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8975 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8979 do_vfp_dp_rd_rn_rm (void)
8981 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8982 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8983 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8989 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8993 do_vfp_dp_rm_rd_rn (void)
8995 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8996 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8997 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9000 /* VFPv3 instructions. */
9002 do_vfp_sp_const (void)
9004 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9005 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9006 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9010 do_vfp_dp_const (void)
9012 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9013 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9014 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9018 vfp_conv (int srcsize
)
9020 int immbits
= srcsize
- inst
.operands
[1].imm
;
9022 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9024 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9025 i.e. immbits must be in range 0 - 16. */
9026 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9029 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9031 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9032 i.e. immbits must be in range 0 - 31. */
9033 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9037 inst
.instruction
|= (immbits
& 1) << 5;
9038 inst
.instruction
|= (immbits
>> 1);
9042 do_vfp_sp_conv_16 (void)
9044 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9049 do_vfp_dp_conv_16 (void)
9051 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9056 do_vfp_sp_conv_32 (void)
9058 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9063 do_vfp_dp_conv_32 (void)
9065 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9069 /* FPA instructions. Also in a logical order. */
9074 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9075 inst
.instruction
|= inst
.operands
[1].reg
;
9079 do_fpa_ldmstm (void)
9081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9082 switch (inst
.operands
[1].imm
)
9084 case 1: inst
.instruction
|= CP_T_X
; break;
9085 case 2: inst
.instruction
|= CP_T_Y
; break;
9086 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9091 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9093 /* The instruction specified "ea" or "fd", so we can only accept
9094 [Rn]{!}. The instruction does not really support stacking or
9095 unstacking, so we have to emulate these by setting appropriate
9096 bits and offsets. */
9097 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9098 || inst
.reloc
.exp
.X_add_number
!= 0,
9099 _("this instruction does not support indexing"));
9101 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9102 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9104 if (!(inst
.instruction
& INDEX_UP
))
9105 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9107 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9109 inst
.operands
[2].preind
= 0;
9110 inst
.operands
[2].postind
= 1;
9114 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9117 /* iWMMXt instructions: strictly in alphabetical order. */
9120 do_iwmmxt_tandorc (void)
9122 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9126 do_iwmmxt_textrc (void)
9128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9129 inst
.instruction
|= inst
.operands
[1].imm
;
9133 do_iwmmxt_textrm (void)
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9136 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9137 inst
.instruction
|= inst
.operands
[2].imm
;
9141 do_iwmmxt_tinsr (void)
9143 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9144 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9145 inst
.instruction
|= inst
.operands
[2].imm
;
9149 do_iwmmxt_tmia (void)
9151 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9152 inst
.instruction
|= inst
.operands
[1].reg
;
9153 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9157 do_iwmmxt_waligni (void)
9159 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9160 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9161 inst
.instruction
|= inst
.operands
[2].reg
;
9162 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9166 do_iwmmxt_wmerge (void)
9168 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9169 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9170 inst
.instruction
|= inst
.operands
[2].reg
;
9171 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9175 do_iwmmxt_wmov (void)
9177 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9178 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9179 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9180 inst
.instruction
|= inst
.operands
[1].reg
;
9184 do_iwmmxt_wldstbh (void)
9187 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9189 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9191 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9192 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9196 do_iwmmxt_wldstw (void)
9198 /* RIWR_RIWC clears .isreg for a control register. */
9199 if (!inst
.operands
[0].isreg
)
9201 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9202 inst
.instruction
|= 0xf0000000;
9205 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9206 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9210 do_iwmmxt_wldstd (void)
9212 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9213 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9214 && inst
.operands
[1].immisreg
)
9216 inst
.instruction
&= ~0x1a000ff;
9217 inst
.instruction
|= (0xf << 28);
9218 if (inst
.operands
[1].preind
)
9219 inst
.instruction
|= PRE_INDEX
;
9220 if (!inst
.operands
[1].negative
)
9221 inst
.instruction
|= INDEX_UP
;
9222 if (inst
.operands
[1].writeback
)
9223 inst
.instruction
|= WRITE_BACK
;
9224 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9225 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9226 inst
.instruction
|= inst
.operands
[1].imm
;
9229 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9233 do_iwmmxt_wshufh (void)
9235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9237 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9238 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9242 do_iwmmxt_wzero (void)
9244 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9245 inst
.instruction
|= inst
.operands
[0].reg
;
9246 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9247 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9251 do_iwmmxt_wrwrwr_or_imm5 (void)
9253 if (inst
.operands
[2].isreg
)
9256 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9257 _("immediate operand requires iWMMXt2"));
9259 if (inst
.operands
[2].imm
== 0)
9261 switch ((inst
.instruction
>> 20) & 0xf)
9267 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9268 inst
.operands
[2].imm
= 16;
9269 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9275 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9276 inst
.operands
[2].imm
= 32;
9277 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9284 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9286 wrn
= (inst
.instruction
>> 16) & 0xf;
9287 inst
.instruction
&= 0xff0fff0f;
9288 inst
.instruction
|= wrn
;
9289 /* Bail out here; the instruction is now assembled. */
9294 /* Map 32 -> 0, etc. */
9295 inst
.operands
[2].imm
&= 0x1f;
9296 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9300 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9301 operations first, then control, shift, and load/store. */
9303 /* Insns like "foo X,Y,Z". */
9306 do_mav_triple (void)
9308 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9309 inst
.instruction
|= inst
.operands
[1].reg
;
9310 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9313 /* Insns like "foo W,X,Y,Z".
9314 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9319 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9320 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9321 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9322 inst
.instruction
|= inst
.operands
[3].reg
;
9325 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9329 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9332 /* Maverick shift immediate instructions.
9333 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9334 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9339 int imm
= inst
.operands
[2].imm
;
9341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9342 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9344 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9345 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9346 Bit 4 should be 0. */
9347 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9349 inst
.instruction
|= imm
;
9352 /* XScale instructions. Also sorted arithmetic before move. */
9354 /* Xscale multiply-accumulate (argument parse)
9357 MIAxycc acc0,Rm,Rs. */
9362 inst
.instruction
|= inst
.operands
[1].reg
;
9363 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9366 /* Xscale move-accumulator-register (argument parse)
9368 MARcc acc0,RdLo,RdHi. */
9373 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9374 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9377 /* Xscale move-register-accumulator (argument parse)
9379 MRAcc RdLo,RdHi,acc0. */
9384 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9385 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9386 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9389 /* Encoding functions relevant only to Thumb. */
9391 /* inst.operands[i] is a shifted-register operand; encode
9392 it into inst.instruction in the format used by Thumb32. */
9395 encode_thumb32_shifted_operand (int i
)
9397 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9398 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9400 constraint (inst
.operands
[i
].immisreg
,
9401 _("shift by register not allowed in thumb mode"));
9402 inst
.instruction
|= inst
.operands
[i
].reg
;
9403 if (shift
== SHIFT_RRX
)
9404 inst
.instruction
|= SHIFT_ROR
<< 4;
9407 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9408 _("expression too complex"));
9410 constraint (value
> 32
9411 || (value
== 32 && (shift
== SHIFT_LSL
9412 || shift
== SHIFT_ROR
)),
9413 _("shift expression is too large"));
9417 else if (value
== 32)
9420 inst
.instruction
|= shift
<< 4;
9421 inst
.instruction
|= (value
& 0x1c) << 10;
9422 inst
.instruction
|= (value
& 0x03) << 6;
9427 /* inst.operands[i] was set up by parse_address. Encode it into a
9428 Thumb32 format load or store instruction. Reject forms that cannot
9429 be used with such instructions. If is_t is true, reject forms that
9430 cannot be used with a T instruction; if is_d is true, reject forms
9431 that cannot be used with a D instruction. If it is a store insn,
9435 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9437 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9439 constraint (!inst
.operands
[i
].isreg
,
9440 _("Instruction does not support =N addresses"));
9442 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9443 if (inst
.operands
[i
].immisreg
)
9445 constraint (is_pc
, BAD_PC_ADDRESSING
);
9446 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9447 constraint (inst
.operands
[i
].negative
,
9448 _("Thumb does not support negative register indexing"));
9449 constraint (inst
.operands
[i
].postind
,
9450 _("Thumb does not support register post-indexing"));
9451 constraint (inst
.operands
[i
].writeback
,
9452 _("Thumb does not support register indexing with writeback"));
9453 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9454 _("Thumb supports only LSL in shifted register indexing"));
9456 inst
.instruction
|= inst
.operands
[i
].imm
;
9457 if (inst
.operands
[i
].shifted
)
9459 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9460 _("expression too complex"));
9461 constraint (inst
.reloc
.exp
.X_add_number
< 0
9462 || inst
.reloc
.exp
.X_add_number
> 3,
9463 _("shift out of range"));
9464 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9466 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9468 else if (inst
.operands
[i
].preind
)
9470 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9471 constraint (is_t
&& inst
.operands
[i
].writeback
,
9472 _("cannot use writeback with this instruction"));
9473 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9474 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9478 inst
.instruction
|= 0x01000000;
9479 if (inst
.operands
[i
].writeback
)
9480 inst
.instruction
|= 0x00200000;
9484 inst
.instruction
|= 0x00000c00;
9485 if (inst
.operands
[i
].writeback
)
9486 inst
.instruction
|= 0x00000100;
9488 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9490 else if (inst
.operands
[i
].postind
)
9492 gas_assert (inst
.operands
[i
].writeback
);
9493 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9494 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9497 inst
.instruction
|= 0x00200000;
9499 inst
.instruction
|= 0x00000900;
9500 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9502 else /* unindexed - only for coprocessor */
9503 inst
.error
= _("instruction does not accept unindexed addressing");
9506 /* Table of Thumb instructions which exist in both 16- and 32-bit
9507 encodings (the latter only in post-V6T2 cores). The index is the
9508 value used in the insns table below. When there is more than one
9509 possible 16-bit encoding for the instruction, this table always
9511 Also contains several pseudo-instructions used during relaxation. */
9512 #define T16_32_TAB \
9513 X(_adc, 4140, eb400000), \
9514 X(_adcs, 4140, eb500000), \
9515 X(_add, 1c00, eb000000), \
9516 X(_adds, 1c00, eb100000), \
9517 X(_addi, 0000, f1000000), \
9518 X(_addis, 0000, f1100000), \
9519 X(_add_pc,000f, f20f0000), \
9520 X(_add_sp,000d, f10d0000), \
9521 X(_adr, 000f, f20f0000), \
9522 X(_and, 4000, ea000000), \
9523 X(_ands, 4000, ea100000), \
9524 X(_asr, 1000, fa40f000), \
9525 X(_asrs, 1000, fa50f000), \
9526 X(_b, e000, f000b000), \
9527 X(_bcond, d000, f0008000), \
9528 X(_bic, 4380, ea200000), \
9529 X(_bics, 4380, ea300000), \
9530 X(_cmn, 42c0, eb100f00), \
9531 X(_cmp, 2800, ebb00f00), \
9532 X(_cpsie, b660, f3af8400), \
9533 X(_cpsid, b670, f3af8600), \
9534 X(_cpy, 4600, ea4f0000), \
9535 X(_dec_sp,80dd, f1ad0d00), \
9536 X(_eor, 4040, ea800000), \
9537 X(_eors, 4040, ea900000), \
9538 X(_inc_sp,00dd, f10d0d00), \
9539 X(_ldmia, c800, e8900000), \
9540 X(_ldr, 6800, f8500000), \
9541 X(_ldrb, 7800, f8100000), \
9542 X(_ldrh, 8800, f8300000), \
9543 X(_ldrsb, 5600, f9100000), \
9544 X(_ldrsh, 5e00, f9300000), \
9545 X(_ldr_pc,4800, f85f0000), \
9546 X(_ldr_pc2,4800, f85f0000), \
9547 X(_ldr_sp,9800, f85d0000), \
9548 X(_lsl, 0000, fa00f000), \
9549 X(_lsls, 0000, fa10f000), \
9550 X(_lsr, 0800, fa20f000), \
9551 X(_lsrs, 0800, fa30f000), \
9552 X(_mov, 2000, ea4f0000), \
9553 X(_movs, 2000, ea5f0000), \
9554 X(_mul, 4340, fb00f000), \
9555 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9556 X(_mvn, 43c0, ea6f0000), \
9557 X(_mvns, 43c0, ea7f0000), \
9558 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9559 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9560 X(_orr, 4300, ea400000), \
9561 X(_orrs, 4300, ea500000), \
9562 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9563 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9564 X(_rev, ba00, fa90f080), \
9565 X(_rev16, ba40, fa90f090), \
9566 X(_revsh, bac0, fa90f0b0), \
9567 X(_ror, 41c0, fa60f000), \
9568 X(_rors, 41c0, fa70f000), \
9569 X(_sbc, 4180, eb600000), \
9570 X(_sbcs, 4180, eb700000), \
9571 X(_stmia, c000, e8800000), \
9572 X(_str, 6000, f8400000), \
9573 X(_strb, 7000, f8000000), \
9574 X(_strh, 8000, f8200000), \
9575 X(_str_sp,9000, f84d0000), \
9576 X(_sub, 1e00, eba00000), \
9577 X(_subs, 1e00, ebb00000), \
9578 X(_subi, 8000, f1a00000), \
9579 X(_subis, 8000, f1b00000), \
9580 X(_sxtb, b240, fa4ff080), \
9581 X(_sxth, b200, fa0ff080), \
9582 X(_tst, 4200, ea100f00), \
9583 X(_uxtb, b2c0, fa5ff080), \
9584 X(_uxth, b280, fa1ff080), \
9585 X(_nop, bf00, f3af8000), \
9586 X(_yield, bf10, f3af8001), \
9587 X(_wfe, bf20, f3af8002), \
9588 X(_wfi, bf30, f3af8003), \
9589 X(_sev, bf40, f3af8004), \
9590 X(_sevl, bf50, f3af8005)
9592 /* To catch errors in encoding functions, the codes are all offset by
9593 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9594 as 16-bit instructions. */
9595 #define X(a,b,c) T_MNEM##a
9596 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9599 #define X(a,b,c) 0x##b
9600 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9601 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9604 #define X(a,b,c) 0x##c
9605 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9606 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9607 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9611 /* Thumb instruction encoders, in alphabetical order. */
9616 do_t_add_sub_w (void)
9620 Rd
= inst
.operands
[0].reg
;
9621 Rn
= inst
.operands
[1].reg
;
9623 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9624 is the SP-{plus,minus}-immediate form of the instruction. */
9626 constraint (Rd
== REG_PC
, BAD_PC
);
9628 reject_bad_reg (Rd
);
9630 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9631 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9634 /* Parse an add or subtract instruction. We get here with inst.instruction
9635 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9642 Rd
= inst
.operands
[0].reg
;
9643 Rs
= (inst
.operands
[1].present
9644 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9645 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9648 set_it_insn_type_last ();
9656 flags
= (inst
.instruction
== T_MNEM_adds
9657 || inst
.instruction
== T_MNEM_subs
);
9659 narrow
= !in_it_block ();
9661 narrow
= in_it_block ();
9662 if (!inst
.operands
[2].isreg
)
9666 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9668 add
= (inst
.instruction
== T_MNEM_add
9669 || inst
.instruction
== T_MNEM_adds
);
9671 if (inst
.size_req
!= 4)
9673 /* Attempt to use a narrow opcode, with relaxation if
9675 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9676 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9677 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9678 opcode
= T_MNEM_add_sp
;
9679 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9680 opcode
= T_MNEM_add_pc
;
9681 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9684 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9686 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9690 inst
.instruction
= THUMB_OP16(opcode
);
9691 inst
.instruction
|= (Rd
<< 4) | Rs
;
9692 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9693 if (inst
.size_req
!= 2)
9694 inst
.relax
= opcode
;
9697 constraint (inst
.size_req
== 2, BAD_HIREG
);
9699 if (inst
.size_req
== 4
9700 || (inst
.size_req
!= 2 && !opcode
))
9704 constraint (add
, BAD_PC
);
9705 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9706 _("only SUBS PC, LR, #const allowed"));
9707 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9708 _("expression too complex"));
9709 constraint (inst
.reloc
.exp
.X_add_number
< 0
9710 || inst
.reloc
.exp
.X_add_number
> 0xff,
9711 _("immediate value out of range"));
9712 inst
.instruction
= T2_SUBS_PC_LR
9713 | inst
.reloc
.exp
.X_add_number
;
9714 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9717 else if (Rs
== REG_PC
)
9719 /* Always use addw/subw. */
9720 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9721 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9725 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9726 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9729 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9731 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9733 inst
.instruction
|= Rd
<< 8;
9734 inst
.instruction
|= Rs
<< 16;
9739 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9740 unsigned int shift
= inst
.operands
[2].shift_kind
;
9742 Rn
= inst
.operands
[2].reg
;
9743 /* See if we can do this with a 16-bit instruction. */
9744 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9746 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9751 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9752 || inst
.instruction
== T_MNEM_add
)
9755 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9759 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9761 /* Thumb-1 cores (except v6-M) require at least one high
9762 register in a narrow non flag setting add. */
9763 if (Rd
> 7 || Rn
> 7
9764 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9765 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9772 inst
.instruction
= T_OPCODE_ADD_HI
;
9773 inst
.instruction
|= (Rd
& 8) << 4;
9774 inst
.instruction
|= (Rd
& 7);
9775 inst
.instruction
|= Rn
<< 3;
9781 constraint (Rd
== REG_PC
, BAD_PC
);
9782 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9783 constraint (Rs
== REG_PC
, BAD_PC
);
9784 reject_bad_reg (Rn
);
9786 /* If we get here, it can't be done in 16 bits. */
9787 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9788 _("shift must be constant"));
9789 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9790 inst
.instruction
|= Rd
<< 8;
9791 inst
.instruction
|= Rs
<< 16;
9792 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
9793 _("shift value over 3 not allowed in thumb mode"));
9794 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
9795 _("only LSL shift allowed in thumb mode"));
9796 encode_thumb32_shifted_operand (2);
9801 constraint (inst
.instruction
== T_MNEM_adds
9802 || inst
.instruction
== T_MNEM_subs
,
9805 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9807 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9808 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9811 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9813 inst
.instruction
|= (Rd
<< 4) | Rs
;
9814 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9818 Rn
= inst
.operands
[2].reg
;
9819 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9821 /* We now have Rd, Rs, and Rn set to registers. */
9822 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9824 /* Can't do this for SUB. */
9825 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9826 inst
.instruction
= T_OPCODE_ADD_HI
;
9827 inst
.instruction
|= (Rd
& 8) << 4;
9828 inst
.instruction
|= (Rd
& 7);
9830 inst
.instruction
|= Rn
<< 3;
9832 inst
.instruction
|= Rs
<< 3;
9834 constraint (1, _("dest must overlap one source register"));
9838 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9839 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9840 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9850 Rd
= inst
.operands
[0].reg
;
9851 reject_bad_reg (Rd
);
9853 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9855 /* Defer to section relaxation. */
9856 inst
.relax
= inst
.instruction
;
9857 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9858 inst
.instruction
|= Rd
<< 4;
9860 else if (unified_syntax
&& inst
.size_req
!= 2)
9862 /* Generate a 32-bit opcode. */
9863 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9864 inst
.instruction
|= Rd
<< 8;
9865 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9866 inst
.reloc
.pc_rel
= 1;
9870 /* Generate a 16-bit opcode. */
9871 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9872 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9873 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9874 inst
.reloc
.pc_rel
= 1;
9876 inst
.instruction
|= Rd
<< 4;
9880 /* Arithmetic instructions for which there is just one 16-bit
9881 instruction encoding, and it allows only two low registers.
9882 For maximal compatibility with ARM syntax, we allow three register
9883 operands even when Thumb-32 instructions are not available, as long
9884 as the first two are identical. For instance, both "sbc r0,r1" and
9885 "sbc r0,r0,r1" are allowed. */
9891 Rd
= inst
.operands
[0].reg
;
9892 Rs
= (inst
.operands
[1].present
9893 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9894 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9895 Rn
= inst
.operands
[2].reg
;
9897 reject_bad_reg (Rd
);
9898 reject_bad_reg (Rs
);
9899 if (inst
.operands
[2].isreg
)
9900 reject_bad_reg (Rn
);
9904 if (!inst
.operands
[2].isreg
)
9906 /* For an immediate, we always generate a 32-bit opcode;
9907 section relaxation will shrink it later if possible. */
9908 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9909 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9910 inst
.instruction
|= Rd
<< 8;
9911 inst
.instruction
|= Rs
<< 16;
9912 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9918 /* See if we can do this with a 16-bit instruction. */
9919 if (THUMB_SETS_FLAGS (inst
.instruction
))
9920 narrow
= !in_it_block ();
9922 narrow
= in_it_block ();
9924 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9926 if (inst
.operands
[2].shifted
)
9928 if (inst
.size_req
== 4)
9934 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9935 inst
.instruction
|= Rd
;
9936 inst
.instruction
|= Rn
<< 3;
9940 /* If we get here, it can't be done in 16 bits. */
9941 constraint (inst
.operands
[2].shifted
9942 && inst
.operands
[2].immisreg
,
9943 _("shift must be constant"));
9944 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9945 inst
.instruction
|= Rd
<< 8;
9946 inst
.instruction
|= Rs
<< 16;
9947 encode_thumb32_shifted_operand (2);
9952 /* On its face this is a lie - the instruction does set the
9953 flags. However, the only supported mnemonic in this mode
9955 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9957 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9958 _("unshifted register required"));
9959 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9960 constraint (Rd
!= Rs
,
9961 _("dest and source1 must be the same register"));
9963 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9964 inst
.instruction
|= Rd
;
9965 inst
.instruction
|= Rn
<< 3;
9969 /* Similarly, but for instructions where the arithmetic operation is
9970 commutative, so we can allow either of them to be different from
9971 the destination operand in a 16-bit instruction. For instance, all
9972 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9979 Rd
= inst
.operands
[0].reg
;
9980 Rs
= (inst
.operands
[1].present
9981 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9982 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9983 Rn
= inst
.operands
[2].reg
;
9985 reject_bad_reg (Rd
);
9986 reject_bad_reg (Rs
);
9987 if (inst
.operands
[2].isreg
)
9988 reject_bad_reg (Rn
);
9992 if (!inst
.operands
[2].isreg
)
9994 /* For an immediate, we always generate a 32-bit opcode;
9995 section relaxation will shrink it later if possible. */
9996 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9997 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9998 inst
.instruction
|= Rd
<< 8;
9999 inst
.instruction
|= Rs
<< 16;
10000 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10004 bfd_boolean narrow
;
10006 /* See if we can do this with a 16-bit instruction. */
10007 if (THUMB_SETS_FLAGS (inst
.instruction
))
10008 narrow
= !in_it_block ();
10010 narrow
= in_it_block ();
10012 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10014 if (inst
.operands
[2].shifted
)
10016 if (inst
.size_req
== 4)
10023 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10024 inst
.instruction
|= Rd
;
10025 inst
.instruction
|= Rn
<< 3;
10030 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10031 inst
.instruction
|= Rd
;
10032 inst
.instruction
|= Rs
<< 3;
10037 /* If we get here, it can't be done in 16 bits. */
10038 constraint (inst
.operands
[2].shifted
10039 && inst
.operands
[2].immisreg
,
10040 _("shift must be constant"));
10041 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10042 inst
.instruction
|= Rd
<< 8;
10043 inst
.instruction
|= Rs
<< 16;
10044 encode_thumb32_shifted_operand (2);
10049 /* On its face this is a lie - the instruction does set the
10050 flags. However, the only supported mnemonic in this mode
10051 says it doesn't. */
10052 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10054 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10055 _("unshifted register required"));
10056 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10058 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10059 inst
.instruction
|= Rd
;
10062 inst
.instruction
|= Rn
<< 3;
10064 inst
.instruction
|= Rs
<< 3;
10066 constraint (1, _("dest must overlap one source register"));
10071 do_t_barrier (void)
10073 if (inst
.operands
[0].present
)
10075 constraint ((inst
.instruction
& 0xf0) != 0x40
10076 && inst
.operands
[0].imm
> 0xf
10077 && inst
.operands
[0].imm
< 0x0,
10078 _("bad barrier type"));
10079 inst
.instruction
|= inst
.operands
[0].imm
;
10082 inst
.instruction
|= 0xf;
10089 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10090 constraint (msb
> 32, _("bit-field extends past end of register"));
10091 /* The instruction encoding stores the LSB and MSB,
10092 not the LSB and width. */
10093 Rd
= inst
.operands
[0].reg
;
10094 reject_bad_reg (Rd
);
10095 inst
.instruction
|= Rd
<< 8;
10096 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10097 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10098 inst
.instruction
|= msb
- 1;
10107 Rd
= inst
.operands
[0].reg
;
10108 reject_bad_reg (Rd
);
10110 /* #0 in second position is alternative syntax for bfc, which is
10111 the same instruction but with REG_PC in the Rm field. */
10112 if (!inst
.operands
[1].isreg
)
10116 Rn
= inst
.operands
[1].reg
;
10117 reject_bad_reg (Rn
);
10120 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10121 constraint (msb
> 32, _("bit-field extends past end of register"));
10122 /* The instruction encoding stores the LSB and MSB,
10123 not the LSB and width. */
10124 inst
.instruction
|= Rd
<< 8;
10125 inst
.instruction
|= Rn
<< 16;
10126 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10127 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10128 inst
.instruction
|= msb
- 1;
10136 Rd
= inst
.operands
[0].reg
;
10137 Rn
= inst
.operands
[1].reg
;
10139 reject_bad_reg (Rd
);
10140 reject_bad_reg (Rn
);
10142 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10143 _("bit-field extends past end of register"));
10144 inst
.instruction
|= Rd
<< 8;
10145 inst
.instruction
|= Rn
<< 16;
10146 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10147 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10148 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10151 /* ARM V5 Thumb BLX (argument parse)
10152 BLX <target_addr> which is BLX(1)
10153 BLX <Rm> which is BLX(2)
10154 Unfortunately, there are two different opcodes for this mnemonic.
10155 So, the insns[].value is not used, and the code here zaps values
10156 into inst.instruction.
10158 ??? How to take advantage of the additional two bits of displacement
10159 available in Thumb32 mode? Need new relocation? */
10164 set_it_insn_type_last ();
10166 if (inst
.operands
[0].isreg
)
10168 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10169 /* We have a register, so this is BLX(2). */
10170 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10174 /* No register. This must be BLX(1). */
10175 inst
.instruction
= 0xf000e800;
10176 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10188 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10190 if (in_it_block ())
10192 /* Conditional branches inside IT blocks are encoded as unconditional
10194 cond
= COND_ALWAYS
;
10199 if (cond
!= COND_ALWAYS
)
10200 opcode
= T_MNEM_bcond
;
10202 opcode
= inst
.instruction
;
10205 && (inst
.size_req
== 4
10206 || (inst
.size_req
!= 2
10207 && (inst
.operands
[0].hasreloc
10208 || inst
.reloc
.exp
.X_op
== O_constant
))))
10210 inst
.instruction
= THUMB_OP32(opcode
);
10211 if (cond
== COND_ALWAYS
)
10212 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10215 gas_assert (cond
!= 0xF);
10216 inst
.instruction
|= cond
<< 22;
10217 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10222 inst
.instruction
= THUMB_OP16(opcode
);
10223 if (cond
== COND_ALWAYS
)
10224 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10227 inst
.instruction
|= cond
<< 8;
10228 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10230 /* Allow section relaxation. */
10231 if (unified_syntax
&& inst
.size_req
!= 2)
10232 inst
.relax
= opcode
;
10234 inst
.reloc
.type
= reloc
;
10235 inst
.reloc
.pc_rel
= 1;
10238 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10239 between the two is the maximum immediate allowed - which is passed in
10242 do_t_bkpt_hlt1 (int range
)
10244 constraint (inst
.cond
!= COND_ALWAYS
,
10245 _("instruction is always unconditional"));
10246 if (inst
.operands
[0].present
)
10248 constraint (inst
.operands
[0].imm
> range
,
10249 _("immediate value out of range"));
10250 inst
.instruction
|= inst
.operands
[0].imm
;
10253 set_it_insn_type (NEUTRAL_IT_INSN
);
10259 do_t_bkpt_hlt1 (63);
10265 do_t_bkpt_hlt1 (255);
10269 do_t_branch23 (void)
10271 set_it_insn_type_last ();
10272 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10274 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10275 this file. We used to simply ignore the PLT reloc type here --
10276 the branch encoding is now needed to deal with TLSCALL relocs.
10277 So if we see a PLT reloc now, put it back to how it used to be to
10278 keep the preexisting behaviour. */
10279 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10280 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10282 #if defined(OBJ_COFF)
10283 /* If the destination of the branch is a defined symbol which does not have
10284 the THUMB_FUNC attribute, then we must be calling a function which has
10285 the (interfacearm) attribute. We look for the Thumb entry point to that
10286 function and change the branch to refer to that function instead. */
10287 if ( inst
.reloc
.exp
.X_op
== O_symbol
10288 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10289 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10290 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10291 inst
.reloc
.exp
.X_add_symbol
=
10292 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10299 set_it_insn_type_last ();
10300 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10301 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10302 should cause the alignment to be checked once it is known. This is
10303 because BX PC only works if the instruction is word aligned. */
10311 set_it_insn_type_last ();
10312 Rm
= inst
.operands
[0].reg
;
10313 reject_bad_reg (Rm
);
10314 inst
.instruction
|= Rm
<< 16;
10323 Rd
= inst
.operands
[0].reg
;
10324 Rm
= inst
.operands
[1].reg
;
10326 reject_bad_reg (Rd
);
10327 reject_bad_reg (Rm
);
10329 inst
.instruction
|= Rd
<< 8;
10330 inst
.instruction
|= Rm
<< 16;
10331 inst
.instruction
|= Rm
;
10337 set_it_insn_type (OUTSIDE_IT_INSN
);
10338 inst
.instruction
|= inst
.operands
[0].imm
;
10344 set_it_insn_type (OUTSIDE_IT_INSN
);
10346 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10347 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10349 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10350 inst
.instruction
= 0xf3af8000;
10351 inst
.instruction
|= imod
<< 9;
10352 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10353 if (inst
.operands
[1].present
)
10354 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10358 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10359 && (inst
.operands
[0].imm
& 4),
10360 _("selected processor does not support 'A' form "
10361 "of this instruction"));
10362 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10363 _("Thumb does not support the 2-argument "
10364 "form of this instruction"));
10365 inst
.instruction
|= inst
.operands
[0].imm
;
10369 /* THUMB CPY instruction (argument parse). */
10374 if (inst
.size_req
== 4)
10376 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10377 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10378 inst
.instruction
|= inst
.operands
[1].reg
;
10382 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10383 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10384 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10391 set_it_insn_type (OUTSIDE_IT_INSN
);
10392 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10393 inst
.instruction
|= inst
.operands
[0].reg
;
10394 inst
.reloc
.pc_rel
= 1;
10395 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10401 inst
.instruction
|= inst
.operands
[0].imm
;
10407 unsigned Rd
, Rn
, Rm
;
10409 Rd
= inst
.operands
[0].reg
;
10410 Rn
= (inst
.operands
[1].present
10411 ? inst
.operands
[1].reg
: Rd
);
10412 Rm
= inst
.operands
[2].reg
;
10414 reject_bad_reg (Rd
);
10415 reject_bad_reg (Rn
);
10416 reject_bad_reg (Rm
);
10418 inst
.instruction
|= Rd
<< 8;
10419 inst
.instruction
|= Rn
<< 16;
10420 inst
.instruction
|= Rm
;
10426 if (unified_syntax
&& inst
.size_req
== 4)
10427 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10429 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10435 unsigned int cond
= inst
.operands
[0].imm
;
10437 set_it_insn_type (IT_INSN
);
10438 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10440 now_it
.warn_deprecated
= FALSE
;
10442 /* If the condition is a negative condition, invert the mask. */
10443 if ((cond
& 0x1) == 0x0)
10445 unsigned int mask
= inst
.instruction
& 0x000f;
10447 if ((mask
& 0x7) == 0)
10449 /* No conversion needed. */
10450 now_it
.block_length
= 1;
10452 else if ((mask
& 0x3) == 0)
10455 now_it
.block_length
= 2;
10457 else if ((mask
& 0x1) == 0)
10460 now_it
.block_length
= 3;
10465 now_it
.block_length
= 4;
10468 inst
.instruction
&= 0xfff0;
10469 inst
.instruction
|= mask
;
10472 inst
.instruction
|= cond
<< 4;
10475 /* Helper function used for both push/pop and ldm/stm. */
10477 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10481 load
= (inst
.instruction
& (1 << 20)) != 0;
10483 if (mask
& (1 << 13))
10484 inst
.error
= _("SP not allowed in register list");
10486 if ((mask
& (1 << base
)) != 0
10488 inst
.error
= _("having the base register in the register list when "
10489 "using write back is UNPREDICTABLE");
10493 if (mask
& (1 << 15))
10495 if (mask
& (1 << 14))
10496 inst
.error
= _("LR and PC should not both be in register list");
10498 set_it_insn_type_last ();
10503 if (mask
& (1 << 15))
10504 inst
.error
= _("PC not allowed in register list");
10507 if ((mask
& (mask
- 1)) == 0)
10509 /* Single register transfers implemented as str/ldr. */
10512 if (inst
.instruction
& (1 << 23))
10513 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10515 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10519 if (inst
.instruction
& (1 << 23))
10520 inst
.instruction
= 0x00800000; /* ia -> [base] */
10522 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10525 inst
.instruction
|= 0xf8400000;
10527 inst
.instruction
|= 0x00100000;
10529 mask
= ffs (mask
) - 1;
10532 else if (writeback
)
10533 inst
.instruction
|= WRITE_BACK
;
10535 inst
.instruction
|= mask
;
10536 inst
.instruction
|= base
<< 16;
10542 /* This really doesn't seem worth it. */
10543 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10544 _("expression too complex"));
10545 constraint (inst
.operands
[1].writeback
,
10546 _("Thumb load/store multiple does not support {reglist}^"));
10548 if (unified_syntax
)
10550 bfd_boolean narrow
;
10554 /* See if we can use a 16-bit instruction. */
10555 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10556 && inst
.size_req
!= 4
10557 && !(inst
.operands
[1].imm
& ~0xff))
10559 mask
= 1 << inst
.operands
[0].reg
;
10561 if (inst
.operands
[0].reg
<= 7)
10563 if (inst
.instruction
== T_MNEM_stmia
10564 ? inst
.operands
[0].writeback
10565 : (inst
.operands
[0].writeback
10566 == !(inst
.operands
[1].imm
& mask
)))
10568 if (inst
.instruction
== T_MNEM_stmia
10569 && (inst
.operands
[1].imm
& mask
)
10570 && (inst
.operands
[1].imm
& (mask
- 1)))
10571 as_warn (_("value stored for r%d is UNKNOWN"),
10572 inst
.operands
[0].reg
);
10574 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10575 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10576 inst
.instruction
|= inst
.operands
[1].imm
;
10579 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10581 /* This means 1 register in reg list one of 3 situations:
10582 1. Instruction is stmia, but without writeback.
10583 2. lmdia without writeback, but with Rn not in
10585 3. ldmia with writeback, but with Rn in reglist.
10586 Case 3 is UNPREDICTABLE behaviour, so we handle
10587 case 1 and 2 which can be converted into a 16-bit
10588 str or ldr. The SP cases are handled below. */
10589 unsigned long opcode
;
10590 /* First, record an error for Case 3. */
10591 if (inst
.operands
[1].imm
& mask
10592 && inst
.operands
[0].writeback
)
10594 _("having the base register in the register list when "
10595 "using write back is UNPREDICTABLE");
10597 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10599 inst
.instruction
= THUMB_OP16 (opcode
);
10600 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10601 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10605 else if (inst
.operands
[0] .reg
== REG_SP
)
10607 if (inst
.operands
[0].writeback
)
10610 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10611 ? T_MNEM_push
: T_MNEM_pop
);
10612 inst
.instruction
|= inst
.operands
[1].imm
;
10615 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10618 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10619 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10620 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10628 if (inst
.instruction
< 0xffff)
10629 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10631 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10632 inst
.operands
[0].writeback
);
10637 constraint (inst
.operands
[0].reg
> 7
10638 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10639 constraint (inst
.instruction
!= T_MNEM_ldmia
10640 && inst
.instruction
!= T_MNEM_stmia
,
10641 _("Thumb-2 instruction only valid in unified syntax"));
10642 if (inst
.instruction
== T_MNEM_stmia
)
10644 if (!inst
.operands
[0].writeback
)
10645 as_warn (_("this instruction will write back the base register"));
10646 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10647 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10648 as_warn (_("value stored for r%d is UNKNOWN"),
10649 inst
.operands
[0].reg
);
10653 if (!inst
.operands
[0].writeback
10654 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10655 as_warn (_("this instruction will write back the base register"));
10656 else if (inst
.operands
[0].writeback
10657 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10658 as_warn (_("this instruction will not write back the base register"));
10661 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10662 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10663 inst
.instruction
|= inst
.operands
[1].imm
;
10670 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10671 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10672 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10673 || inst
.operands
[1].negative
,
10676 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10678 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10679 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10680 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10686 if (!inst
.operands
[1].present
)
10688 constraint (inst
.operands
[0].reg
== REG_LR
,
10689 _("r14 not allowed as first register "
10690 "when second register is omitted"));
10691 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10693 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10696 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10697 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10698 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10704 unsigned long opcode
;
10707 if (inst
.operands
[0].isreg
10708 && !inst
.operands
[0].preind
10709 && inst
.operands
[0].reg
== REG_PC
)
10710 set_it_insn_type_last ();
10712 opcode
= inst
.instruction
;
10713 if (unified_syntax
)
10715 if (!inst
.operands
[1].isreg
)
10717 if (opcode
<= 0xffff)
10718 inst
.instruction
= THUMB_OP32 (opcode
);
10719 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10722 if (inst
.operands
[1].isreg
10723 && !inst
.operands
[1].writeback
10724 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10725 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10726 && opcode
<= 0xffff
10727 && inst
.size_req
!= 4)
10729 /* Insn may have a 16-bit form. */
10730 Rn
= inst
.operands
[1].reg
;
10731 if (inst
.operands
[1].immisreg
)
10733 inst
.instruction
= THUMB_OP16 (opcode
);
10735 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10737 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10738 reject_bad_reg (inst
.operands
[1].imm
);
10740 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10741 && opcode
!= T_MNEM_ldrsb
)
10742 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10743 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10750 if (inst
.reloc
.pc_rel
)
10751 opcode
= T_MNEM_ldr_pc2
;
10753 opcode
= T_MNEM_ldr_pc
;
10757 if (opcode
== T_MNEM_ldr
)
10758 opcode
= T_MNEM_ldr_sp
;
10760 opcode
= T_MNEM_str_sp
;
10762 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10766 inst
.instruction
= inst
.operands
[0].reg
;
10767 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10769 inst
.instruction
|= THUMB_OP16 (opcode
);
10770 if (inst
.size_req
== 2)
10771 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10773 inst
.relax
= opcode
;
10777 /* Definitely a 32-bit variant. */
10779 /* Warning for Erratum 752419. */
10780 if (opcode
== T_MNEM_ldr
10781 && inst
.operands
[0].reg
== REG_SP
10782 && inst
.operands
[1].writeback
== 1
10783 && !inst
.operands
[1].immisreg
)
10785 if (no_cpu_selected ()
10786 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10787 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10788 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10789 as_warn (_("This instruction may be unpredictable "
10790 "if executed on M-profile cores "
10791 "with interrupts enabled."));
10794 /* Do some validations regarding addressing modes. */
10795 if (inst
.operands
[1].immisreg
)
10796 reject_bad_reg (inst
.operands
[1].imm
);
10798 constraint (inst
.operands
[1].writeback
== 1
10799 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10802 inst
.instruction
= THUMB_OP32 (opcode
);
10803 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10804 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10805 check_ldr_r15_aligned ();
10809 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10811 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10813 /* Only [Rn,Rm] is acceptable. */
10814 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10815 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10816 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10817 || inst
.operands
[1].negative
,
10818 _("Thumb does not support this addressing mode"));
10819 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10823 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10824 if (!inst
.operands
[1].isreg
)
10825 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10828 constraint (!inst
.operands
[1].preind
10829 || inst
.operands
[1].shifted
10830 || inst
.operands
[1].writeback
,
10831 _("Thumb does not support this addressing mode"));
10832 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10834 constraint (inst
.instruction
& 0x0600,
10835 _("byte or halfword not valid for base register"));
10836 constraint (inst
.operands
[1].reg
== REG_PC
10837 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10838 _("r15 based store not allowed"));
10839 constraint (inst
.operands
[1].immisreg
,
10840 _("invalid base register for register offset"));
10842 if (inst
.operands
[1].reg
== REG_PC
)
10843 inst
.instruction
= T_OPCODE_LDR_PC
;
10844 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10845 inst
.instruction
= T_OPCODE_LDR_SP
;
10847 inst
.instruction
= T_OPCODE_STR_SP
;
10849 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10850 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10854 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10855 if (!inst
.operands
[1].immisreg
)
10857 /* Immediate offset. */
10858 inst
.instruction
|= inst
.operands
[0].reg
;
10859 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10860 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10864 /* Register offset. */
10865 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10866 constraint (inst
.operands
[1].negative
,
10867 _("Thumb does not support this addressing mode"));
10870 switch (inst
.instruction
)
10872 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10873 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10874 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10875 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10876 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10877 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10878 case 0x5600 /* ldrsb */:
10879 case 0x5e00 /* ldrsh */: break;
10883 inst
.instruction
|= inst
.operands
[0].reg
;
10884 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10885 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10891 if (!inst
.operands
[1].present
)
10893 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10894 constraint (inst
.operands
[0].reg
== REG_LR
,
10895 _("r14 not allowed here"));
10896 constraint (inst
.operands
[0].reg
== REG_R12
,
10897 _("r12 not allowed here"));
10900 if (inst
.operands
[2].writeback
10901 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
10902 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
10903 as_warn (_("base register written back, and overlaps "
10904 "one of transfer registers"));
10906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10907 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10908 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10915 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10921 unsigned Rd
, Rn
, Rm
, Ra
;
10923 Rd
= inst
.operands
[0].reg
;
10924 Rn
= inst
.operands
[1].reg
;
10925 Rm
= inst
.operands
[2].reg
;
10926 Ra
= inst
.operands
[3].reg
;
10928 reject_bad_reg (Rd
);
10929 reject_bad_reg (Rn
);
10930 reject_bad_reg (Rm
);
10931 reject_bad_reg (Ra
);
10933 inst
.instruction
|= Rd
<< 8;
10934 inst
.instruction
|= Rn
<< 16;
10935 inst
.instruction
|= Rm
;
10936 inst
.instruction
|= Ra
<< 12;
10942 unsigned RdLo
, RdHi
, Rn
, Rm
;
10944 RdLo
= inst
.operands
[0].reg
;
10945 RdHi
= inst
.operands
[1].reg
;
10946 Rn
= inst
.operands
[2].reg
;
10947 Rm
= inst
.operands
[3].reg
;
10949 reject_bad_reg (RdLo
);
10950 reject_bad_reg (RdHi
);
10951 reject_bad_reg (Rn
);
10952 reject_bad_reg (Rm
);
10954 inst
.instruction
|= RdLo
<< 12;
10955 inst
.instruction
|= RdHi
<< 8;
10956 inst
.instruction
|= Rn
<< 16;
10957 inst
.instruction
|= Rm
;
10961 do_t_mov_cmp (void)
10965 Rn
= inst
.operands
[0].reg
;
10966 Rm
= inst
.operands
[1].reg
;
10969 set_it_insn_type_last ();
10971 if (unified_syntax
)
10973 int r0off
= (inst
.instruction
== T_MNEM_mov
10974 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10975 unsigned long opcode
;
10976 bfd_boolean narrow
;
10977 bfd_boolean low_regs
;
10979 low_regs
= (Rn
<= 7 && Rm
<= 7);
10980 opcode
= inst
.instruction
;
10981 if (in_it_block ())
10982 narrow
= opcode
!= T_MNEM_movs
;
10984 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10985 if (inst
.size_req
== 4
10986 || inst
.operands
[1].shifted
)
10989 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10990 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10991 && !inst
.operands
[1].shifted
10995 inst
.instruction
= T2_SUBS_PC_LR
;
10999 if (opcode
== T_MNEM_cmp
)
11001 constraint (Rn
== REG_PC
, BAD_PC
);
11004 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11006 warn_deprecated_sp (Rm
);
11007 /* R15 was documented as a valid choice for Rm in ARMv6,
11008 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11009 tools reject R15, so we do too. */
11010 constraint (Rm
== REG_PC
, BAD_PC
);
11013 reject_bad_reg (Rm
);
11015 else if (opcode
== T_MNEM_mov
11016 || opcode
== T_MNEM_movs
)
11018 if (inst
.operands
[1].isreg
)
11020 if (opcode
== T_MNEM_movs
)
11022 reject_bad_reg (Rn
);
11023 reject_bad_reg (Rm
);
11027 /* This is mov.n. */
11028 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11029 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11031 as_warn (_("Use of r%u as a source register is "
11032 "deprecated when r%u is the destination "
11033 "register."), Rm
, Rn
);
11038 /* This is mov.w. */
11039 constraint (Rn
== REG_PC
, BAD_PC
);
11040 constraint (Rm
== REG_PC
, BAD_PC
);
11041 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11045 reject_bad_reg (Rn
);
11048 if (!inst
.operands
[1].isreg
)
11050 /* Immediate operand. */
11051 if (!in_it_block () && opcode
== T_MNEM_mov
)
11053 if (low_regs
&& narrow
)
11055 inst
.instruction
= THUMB_OP16 (opcode
);
11056 inst
.instruction
|= Rn
<< 8;
11057 if (inst
.size_req
== 2)
11058 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11060 inst
.relax
= opcode
;
11064 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11065 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11066 inst
.instruction
|= Rn
<< r0off
;
11067 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11070 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11071 && (inst
.instruction
== T_MNEM_mov
11072 || inst
.instruction
== T_MNEM_movs
))
11074 /* Register shifts are encoded as separate shift instructions. */
11075 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11077 if (in_it_block ())
11082 if (inst
.size_req
== 4)
11085 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11091 switch (inst
.operands
[1].shift_kind
)
11094 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11097 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11100 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11103 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11109 inst
.instruction
= opcode
;
11112 inst
.instruction
|= Rn
;
11113 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11118 inst
.instruction
|= CONDS_BIT
;
11120 inst
.instruction
|= Rn
<< 8;
11121 inst
.instruction
|= Rm
<< 16;
11122 inst
.instruction
|= inst
.operands
[1].imm
;
11127 /* Some mov with immediate shift have narrow variants.
11128 Register shifts are handled above. */
11129 if (low_regs
&& inst
.operands
[1].shifted
11130 && (inst
.instruction
== T_MNEM_mov
11131 || inst
.instruction
== T_MNEM_movs
))
11133 if (in_it_block ())
11134 narrow
= (inst
.instruction
== T_MNEM_mov
);
11136 narrow
= (inst
.instruction
== T_MNEM_movs
);
11141 switch (inst
.operands
[1].shift_kind
)
11143 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11144 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11145 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11146 default: narrow
= FALSE
; break;
11152 inst
.instruction
|= Rn
;
11153 inst
.instruction
|= Rm
<< 3;
11154 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11158 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11159 inst
.instruction
|= Rn
<< r0off
;
11160 encode_thumb32_shifted_operand (1);
11164 switch (inst
.instruction
)
11167 /* In v4t or v5t a move of two lowregs produces unpredictable
11168 results. Don't allow this. */
11171 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11172 "MOV Rd, Rs with two low registers is not "
11173 "permitted on this architecture");
11174 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11178 inst
.instruction
= T_OPCODE_MOV_HR
;
11179 inst
.instruction
|= (Rn
& 0x8) << 4;
11180 inst
.instruction
|= (Rn
& 0x7);
11181 inst
.instruction
|= Rm
<< 3;
11185 /* We know we have low registers at this point.
11186 Generate LSLS Rd, Rs, #0. */
11187 inst
.instruction
= T_OPCODE_LSL_I
;
11188 inst
.instruction
|= Rn
;
11189 inst
.instruction
|= Rm
<< 3;
11195 inst
.instruction
= T_OPCODE_CMP_LR
;
11196 inst
.instruction
|= Rn
;
11197 inst
.instruction
|= Rm
<< 3;
11201 inst
.instruction
= T_OPCODE_CMP_HR
;
11202 inst
.instruction
|= (Rn
& 0x8) << 4;
11203 inst
.instruction
|= (Rn
& 0x7);
11204 inst
.instruction
|= Rm
<< 3;
11211 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11213 /* PR 10443: Do not silently ignore shifted operands. */
11214 constraint (inst
.operands
[1].shifted
,
11215 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11217 if (inst
.operands
[1].isreg
)
11219 if (Rn
< 8 && Rm
< 8)
11221 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11222 since a MOV instruction produces unpredictable results. */
11223 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11224 inst
.instruction
= T_OPCODE_ADD_I3
;
11226 inst
.instruction
= T_OPCODE_CMP_LR
;
11228 inst
.instruction
|= Rn
;
11229 inst
.instruction
|= Rm
<< 3;
11233 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11234 inst
.instruction
= T_OPCODE_MOV_HR
;
11236 inst
.instruction
= T_OPCODE_CMP_HR
;
11242 constraint (Rn
> 7,
11243 _("only lo regs allowed with immediate"));
11244 inst
.instruction
|= Rn
<< 8;
11245 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11256 top
= (inst
.instruction
& 0x00800000) != 0;
11257 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11259 constraint (top
, _(":lower16: not allowed this instruction"));
11260 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11262 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11264 constraint (!top
, _(":upper16: not allowed this instruction"));
11265 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11268 Rd
= inst
.operands
[0].reg
;
11269 reject_bad_reg (Rd
);
11271 inst
.instruction
|= Rd
<< 8;
11272 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11274 imm
= inst
.reloc
.exp
.X_add_number
;
11275 inst
.instruction
|= (imm
& 0xf000) << 4;
11276 inst
.instruction
|= (imm
& 0x0800) << 15;
11277 inst
.instruction
|= (imm
& 0x0700) << 4;
11278 inst
.instruction
|= (imm
& 0x00ff);
11283 do_t_mvn_tst (void)
11287 Rn
= inst
.operands
[0].reg
;
11288 Rm
= inst
.operands
[1].reg
;
11290 if (inst
.instruction
== T_MNEM_cmp
11291 || inst
.instruction
== T_MNEM_cmn
)
11292 constraint (Rn
== REG_PC
, BAD_PC
);
11294 reject_bad_reg (Rn
);
11295 reject_bad_reg (Rm
);
11297 if (unified_syntax
)
11299 int r0off
= (inst
.instruction
== T_MNEM_mvn
11300 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11301 bfd_boolean narrow
;
11303 if (inst
.size_req
== 4
11304 || inst
.instruction
> 0xffff
11305 || inst
.operands
[1].shifted
11306 || Rn
> 7 || Rm
> 7)
11308 else if (inst
.instruction
== T_MNEM_cmn
)
11310 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11311 narrow
= !in_it_block ();
11313 narrow
= in_it_block ();
11315 if (!inst
.operands
[1].isreg
)
11317 /* For an immediate, we always generate a 32-bit opcode;
11318 section relaxation will shrink it later if possible. */
11319 if (inst
.instruction
< 0xffff)
11320 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11321 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11322 inst
.instruction
|= Rn
<< r0off
;
11323 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11327 /* See if we can do this with a 16-bit instruction. */
11330 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11331 inst
.instruction
|= Rn
;
11332 inst
.instruction
|= Rm
<< 3;
11336 constraint (inst
.operands
[1].shifted
11337 && inst
.operands
[1].immisreg
,
11338 _("shift must be constant"));
11339 if (inst
.instruction
< 0xffff)
11340 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11341 inst
.instruction
|= Rn
<< r0off
;
11342 encode_thumb32_shifted_operand (1);
11348 constraint (inst
.instruction
> 0xffff
11349 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11350 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11351 _("unshifted register required"));
11352 constraint (Rn
> 7 || Rm
> 7,
11355 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11356 inst
.instruction
|= Rn
;
11357 inst
.instruction
|= Rm
<< 3;
11366 if (do_vfp_nsyn_mrs () == SUCCESS
)
11369 Rd
= inst
.operands
[0].reg
;
11370 reject_bad_reg (Rd
);
11371 inst
.instruction
|= Rd
<< 8;
11373 if (inst
.operands
[1].isreg
)
11375 unsigned br
= inst
.operands
[1].reg
;
11376 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11377 as_bad (_("bad register for mrs"));
11379 inst
.instruction
|= br
& (0xf << 16);
11380 inst
.instruction
|= (br
& 0x300) >> 4;
11381 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11385 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11387 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11389 /* PR gas/12698: The constraint is only applied for m_profile.
11390 If the user has specified -march=all, we want to ignore it as
11391 we are building for any CPU type, including non-m variants. */
11392 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11393 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
11394 "not support requested special purpose register"));
11397 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11399 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11400 _("'APSR', 'CPSR' or 'SPSR' expected"));
11402 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11403 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11404 inst
.instruction
|= 0xf0000;
11414 if (do_vfp_nsyn_msr () == SUCCESS
)
11417 constraint (!inst
.operands
[1].isreg
,
11418 _("Thumb encoding does not support an immediate here"));
11420 if (inst
.operands
[0].isreg
)
11421 flags
= (int)(inst
.operands
[0].reg
);
11423 flags
= inst
.operands
[0].imm
;
11425 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11427 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11429 /* PR gas/12698: The constraint is only applied for m_profile.
11430 If the user has specified -march=all, we want to ignore it as
11431 we are building for any CPU type, including non-m variants. */
11432 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11433 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11434 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11435 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11436 && bits
!= PSR_f
)) && m_profile
,
11437 _("selected processor does not support requested special "
11438 "purpose register"));
11441 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11442 "requested special purpose register"));
11444 Rn
= inst
.operands
[1].reg
;
11445 reject_bad_reg (Rn
);
11447 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11448 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11449 inst
.instruction
|= (flags
& 0x300) >> 4;
11450 inst
.instruction
|= (flags
& 0xff);
11451 inst
.instruction
|= Rn
<< 16;
11457 bfd_boolean narrow
;
11458 unsigned Rd
, Rn
, Rm
;
11460 if (!inst
.operands
[2].present
)
11461 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11463 Rd
= inst
.operands
[0].reg
;
11464 Rn
= inst
.operands
[1].reg
;
11465 Rm
= inst
.operands
[2].reg
;
11467 if (unified_syntax
)
11469 if (inst
.size_req
== 4
11475 else if (inst
.instruction
== T_MNEM_muls
)
11476 narrow
= !in_it_block ();
11478 narrow
= in_it_block ();
11482 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11483 constraint (Rn
> 7 || Rm
> 7,
11490 /* 16-bit MULS/Conditional MUL. */
11491 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11492 inst
.instruction
|= Rd
;
11495 inst
.instruction
|= Rm
<< 3;
11497 inst
.instruction
|= Rn
<< 3;
11499 constraint (1, _("dest must overlap one source register"));
11503 constraint (inst
.instruction
!= T_MNEM_mul
,
11504 _("Thumb-2 MUL must not set flags"));
11506 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11507 inst
.instruction
|= Rd
<< 8;
11508 inst
.instruction
|= Rn
<< 16;
11509 inst
.instruction
|= Rm
<< 0;
11511 reject_bad_reg (Rd
);
11512 reject_bad_reg (Rn
);
11513 reject_bad_reg (Rm
);
11520 unsigned RdLo
, RdHi
, Rn
, Rm
;
11522 RdLo
= inst
.operands
[0].reg
;
11523 RdHi
= inst
.operands
[1].reg
;
11524 Rn
= inst
.operands
[2].reg
;
11525 Rm
= inst
.operands
[3].reg
;
11527 reject_bad_reg (RdLo
);
11528 reject_bad_reg (RdHi
);
11529 reject_bad_reg (Rn
);
11530 reject_bad_reg (Rm
);
11532 inst
.instruction
|= RdLo
<< 12;
11533 inst
.instruction
|= RdHi
<< 8;
11534 inst
.instruction
|= Rn
<< 16;
11535 inst
.instruction
|= Rm
;
11538 as_tsktsk (_("rdhi and rdlo must be different"));
11544 set_it_insn_type (NEUTRAL_IT_INSN
);
11546 if (unified_syntax
)
11548 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11550 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11551 inst
.instruction
|= inst
.operands
[0].imm
;
11555 /* PR9722: Check for Thumb2 availability before
11556 generating a thumb2 nop instruction. */
11557 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11559 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11560 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11563 inst
.instruction
= 0x46c0;
11568 constraint (inst
.operands
[0].present
,
11569 _("Thumb does not support NOP with hints"));
11570 inst
.instruction
= 0x46c0;
11577 if (unified_syntax
)
11579 bfd_boolean narrow
;
11581 if (THUMB_SETS_FLAGS (inst
.instruction
))
11582 narrow
= !in_it_block ();
11584 narrow
= in_it_block ();
11585 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11587 if (inst
.size_req
== 4)
11592 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11593 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11594 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11598 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11599 inst
.instruction
|= inst
.operands
[0].reg
;
11600 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11605 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11607 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11609 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11610 inst
.instruction
|= inst
.operands
[0].reg
;
11611 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11620 Rd
= inst
.operands
[0].reg
;
11621 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11623 reject_bad_reg (Rd
);
11624 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11625 reject_bad_reg (Rn
);
11627 inst
.instruction
|= Rd
<< 8;
11628 inst
.instruction
|= Rn
<< 16;
11630 if (!inst
.operands
[2].isreg
)
11632 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11633 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11639 Rm
= inst
.operands
[2].reg
;
11640 reject_bad_reg (Rm
);
11642 constraint (inst
.operands
[2].shifted
11643 && inst
.operands
[2].immisreg
,
11644 _("shift must be constant"));
11645 encode_thumb32_shifted_operand (2);
11652 unsigned Rd
, Rn
, Rm
;
11654 Rd
= inst
.operands
[0].reg
;
11655 Rn
= inst
.operands
[1].reg
;
11656 Rm
= inst
.operands
[2].reg
;
11658 reject_bad_reg (Rd
);
11659 reject_bad_reg (Rn
);
11660 reject_bad_reg (Rm
);
11662 inst
.instruction
|= Rd
<< 8;
11663 inst
.instruction
|= Rn
<< 16;
11664 inst
.instruction
|= Rm
;
11665 if (inst
.operands
[3].present
)
11667 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11668 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11669 _("expression too complex"));
11670 inst
.instruction
|= (val
& 0x1c) << 10;
11671 inst
.instruction
|= (val
& 0x03) << 6;
11678 if (!inst
.operands
[3].present
)
11682 inst
.instruction
&= ~0x00000020;
11684 /* PR 10168. Swap the Rm and Rn registers. */
11685 Rtmp
= inst
.operands
[1].reg
;
11686 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11687 inst
.operands
[2].reg
= Rtmp
;
11695 if (inst
.operands
[0].immisreg
)
11696 reject_bad_reg (inst
.operands
[0].imm
);
11698 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11702 do_t_push_pop (void)
11706 constraint (inst
.operands
[0].writeback
,
11707 _("push/pop do not support {reglist}^"));
11708 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11709 _("expression too complex"));
11711 mask
= inst
.operands
[0].imm
;
11712 if ((mask
& ~0xff) == 0)
11713 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11714 else if ((inst
.instruction
== T_MNEM_push
11715 && (mask
& ~0xff) == 1 << REG_LR
)
11716 || (inst
.instruction
== T_MNEM_pop
11717 && (mask
& ~0xff) == 1 << REG_PC
))
11719 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11720 inst
.instruction
|= THUMB_PP_PC_LR
;
11721 inst
.instruction
|= mask
& 0xff;
11723 else if (unified_syntax
)
11725 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11726 encode_thumb2_ldmstm (13, mask
, TRUE
);
11730 inst
.error
= _("invalid register list to push/pop instruction");
11740 Rd
= inst
.operands
[0].reg
;
11741 Rm
= inst
.operands
[1].reg
;
11743 reject_bad_reg (Rd
);
11744 reject_bad_reg (Rm
);
11746 inst
.instruction
|= Rd
<< 8;
11747 inst
.instruction
|= Rm
<< 16;
11748 inst
.instruction
|= Rm
;
11756 Rd
= inst
.operands
[0].reg
;
11757 Rm
= inst
.operands
[1].reg
;
11759 reject_bad_reg (Rd
);
11760 reject_bad_reg (Rm
);
11762 if (Rd
<= 7 && Rm
<= 7
11763 && inst
.size_req
!= 4)
11765 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11766 inst
.instruction
|= Rd
;
11767 inst
.instruction
|= Rm
<< 3;
11769 else if (unified_syntax
)
11771 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11772 inst
.instruction
|= Rd
<< 8;
11773 inst
.instruction
|= Rm
<< 16;
11774 inst
.instruction
|= Rm
;
11777 inst
.error
= BAD_HIREG
;
11785 Rd
= inst
.operands
[0].reg
;
11786 Rm
= inst
.operands
[1].reg
;
11788 reject_bad_reg (Rd
);
11789 reject_bad_reg (Rm
);
11791 inst
.instruction
|= Rd
<< 8;
11792 inst
.instruction
|= Rm
;
11800 Rd
= inst
.operands
[0].reg
;
11801 Rs
= (inst
.operands
[1].present
11802 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11803 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11805 reject_bad_reg (Rd
);
11806 reject_bad_reg (Rs
);
11807 if (inst
.operands
[2].isreg
)
11808 reject_bad_reg (inst
.operands
[2].reg
);
11810 inst
.instruction
|= Rd
<< 8;
11811 inst
.instruction
|= Rs
<< 16;
11812 if (!inst
.operands
[2].isreg
)
11814 bfd_boolean narrow
;
11816 if ((inst
.instruction
& 0x00100000) != 0)
11817 narrow
= !in_it_block ();
11819 narrow
= in_it_block ();
11821 if (Rd
> 7 || Rs
> 7)
11824 if (inst
.size_req
== 4 || !unified_syntax
)
11827 if (inst
.reloc
.exp
.X_op
!= O_constant
11828 || inst
.reloc
.exp
.X_add_number
!= 0)
11831 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11832 relaxation, but it doesn't seem worth the hassle. */
11835 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11836 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11837 inst
.instruction
|= Rs
<< 3;
11838 inst
.instruction
|= Rd
;
11842 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11843 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11847 encode_thumb32_shifted_operand (2);
11853 if (warn_on_deprecated
11854 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11855 as_warn (_("setend use is deprecated for ARMv8"));
11857 set_it_insn_type (OUTSIDE_IT_INSN
);
11858 if (inst
.operands
[0].imm
)
11859 inst
.instruction
|= 0x8;
11865 if (!inst
.operands
[1].present
)
11866 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11868 if (unified_syntax
)
11870 bfd_boolean narrow
;
11873 switch (inst
.instruction
)
11876 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11878 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11880 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11882 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11886 if (THUMB_SETS_FLAGS (inst
.instruction
))
11887 narrow
= !in_it_block ();
11889 narrow
= in_it_block ();
11890 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11892 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11894 if (inst
.operands
[2].isreg
11895 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11896 || inst
.operands
[2].reg
> 7))
11898 if (inst
.size_req
== 4)
11901 reject_bad_reg (inst
.operands
[0].reg
);
11902 reject_bad_reg (inst
.operands
[1].reg
);
11906 if (inst
.operands
[2].isreg
)
11908 reject_bad_reg (inst
.operands
[2].reg
);
11909 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11910 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11911 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11912 inst
.instruction
|= inst
.operands
[2].reg
;
11914 /* PR 12854: Error on extraneous shifts. */
11915 constraint (inst
.operands
[2].shifted
,
11916 _("extraneous shift as part of operand to shift insn"));
11920 inst
.operands
[1].shifted
= 1;
11921 inst
.operands
[1].shift_kind
= shift_kind
;
11922 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11923 ? T_MNEM_movs
: T_MNEM_mov
);
11924 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11925 encode_thumb32_shifted_operand (1);
11926 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11927 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11932 if (inst
.operands
[2].isreg
)
11934 switch (shift_kind
)
11936 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11937 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11938 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11939 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11943 inst
.instruction
|= inst
.operands
[0].reg
;
11944 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11946 /* PR 12854: Error on extraneous shifts. */
11947 constraint (inst
.operands
[2].shifted
,
11948 _("extraneous shift as part of operand to shift insn"));
11952 switch (shift_kind
)
11954 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11955 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11956 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11959 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11960 inst
.instruction
|= inst
.operands
[0].reg
;
11961 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11967 constraint (inst
.operands
[0].reg
> 7
11968 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11969 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11971 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11973 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11974 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11975 _("source1 and dest must be same register"));
11977 switch (inst
.instruction
)
11979 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11980 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11981 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11982 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11986 inst
.instruction
|= inst
.operands
[0].reg
;
11987 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11989 /* PR 12854: Error on extraneous shifts. */
11990 constraint (inst
.operands
[2].shifted
,
11991 _("extraneous shift as part of operand to shift insn"));
11995 switch (inst
.instruction
)
11997 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11998 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11999 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12000 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12003 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12004 inst
.instruction
|= inst
.operands
[0].reg
;
12005 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12013 unsigned Rd
, Rn
, Rm
;
12015 Rd
= inst
.operands
[0].reg
;
12016 Rn
= inst
.operands
[1].reg
;
12017 Rm
= inst
.operands
[2].reg
;
12019 reject_bad_reg (Rd
);
12020 reject_bad_reg (Rn
);
12021 reject_bad_reg (Rm
);
12023 inst
.instruction
|= Rd
<< 8;
12024 inst
.instruction
|= Rn
<< 16;
12025 inst
.instruction
|= Rm
;
12031 unsigned Rd
, Rn
, Rm
;
12033 Rd
= inst
.operands
[0].reg
;
12034 Rm
= inst
.operands
[1].reg
;
12035 Rn
= inst
.operands
[2].reg
;
12037 reject_bad_reg (Rd
);
12038 reject_bad_reg (Rn
);
12039 reject_bad_reg (Rm
);
12041 inst
.instruction
|= Rd
<< 8;
12042 inst
.instruction
|= Rn
<< 16;
12043 inst
.instruction
|= Rm
;
12049 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12050 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12051 _("SMC is not permitted on this architecture"));
12052 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12053 _("expression too complex"));
12054 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12055 inst
.instruction
|= (value
& 0xf000) >> 12;
12056 inst
.instruction
|= (value
& 0x0ff0);
12057 inst
.instruction
|= (value
& 0x000f) << 16;
12063 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12065 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12066 inst
.instruction
|= (value
& 0x0fff);
12067 inst
.instruction
|= (value
& 0xf000) << 4;
12071 do_t_ssat_usat (int bias
)
12075 Rd
= inst
.operands
[0].reg
;
12076 Rn
= inst
.operands
[2].reg
;
12078 reject_bad_reg (Rd
);
12079 reject_bad_reg (Rn
);
12081 inst
.instruction
|= Rd
<< 8;
12082 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12083 inst
.instruction
|= Rn
<< 16;
12085 if (inst
.operands
[3].present
)
12087 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12089 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12091 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12092 _("expression too complex"));
12094 if (shift_amount
!= 0)
12096 constraint (shift_amount
> 31,
12097 _("shift expression is too large"));
12099 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12100 inst
.instruction
|= 0x00200000; /* sh bit. */
12102 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12103 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12111 do_t_ssat_usat (1);
12119 Rd
= inst
.operands
[0].reg
;
12120 Rn
= inst
.operands
[2].reg
;
12122 reject_bad_reg (Rd
);
12123 reject_bad_reg (Rn
);
12125 inst
.instruction
|= Rd
<< 8;
12126 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12127 inst
.instruction
|= Rn
<< 16;
12133 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12134 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12135 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12136 || inst
.operands
[2].negative
,
12139 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12141 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12142 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12143 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12144 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12150 if (!inst
.operands
[2].present
)
12151 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12153 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12154 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12155 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12158 inst
.instruction
|= inst
.operands
[0].reg
;
12159 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12160 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12161 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12167 unsigned Rd
, Rn
, Rm
;
12169 Rd
= inst
.operands
[0].reg
;
12170 Rn
= inst
.operands
[1].reg
;
12171 Rm
= inst
.operands
[2].reg
;
12173 reject_bad_reg (Rd
);
12174 reject_bad_reg (Rn
);
12175 reject_bad_reg (Rm
);
12177 inst
.instruction
|= Rd
<< 8;
12178 inst
.instruction
|= Rn
<< 16;
12179 inst
.instruction
|= Rm
;
12180 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12188 Rd
= inst
.operands
[0].reg
;
12189 Rm
= inst
.operands
[1].reg
;
12191 reject_bad_reg (Rd
);
12192 reject_bad_reg (Rm
);
12194 if (inst
.instruction
<= 0xffff
12195 && inst
.size_req
!= 4
12196 && Rd
<= 7 && Rm
<= 7
12197 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12199 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12200 inst
.instruction
|= Rd
;
12201 inst
.instruction
|= Rm
<< 3;
12203 else if (unified_syntax
)
12205 if (inst
.instruction
<= 0xffff)
12206 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12207 inst
.instruction
|= Rd
<< 8;
12208 inst
.instruction
|= Rm
;
12209 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12213 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12214 _("Thumb encoding does not support rotation"));
12215 constraint (1, BAD_HIREG
);
12222 /* We have to do the following check manually as ARM_EXT_OS only applies
12224 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12226 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12227 /* This only applies to the v6m howver, not later architectures. */
12228 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12229 as_bad (_("SVC is not permitted on this architecture"));
12230 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12233 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12242 half
= (inst
.instruction
& 0x10) != 0;
12243 set_it_insn_type_last ();
12244 constraint (inst
.operands
[0].immisreg
,
12245 _("instruction requires register index"));
12247 Rn
= inst
.operands
[0].reg
;
12248 Rm
= inst
.operands
[0].imm
;
12250 constraint (Rn
== REG_SP
, BAD_SP
);
12251 reject_bad_reg (Rm
);
12253 constraint (!half
&& inst
.operands
[0].shifted
,
12254 _("instruction does not allow shifted index"));
12255 inst
.instruction
|= (Rn
<< 16) | Rm
;
12261 do_t_ssat_usat (0);
12269 Rd
= inst
.operands
[0].reg
;
12270 Rn
= inst
.operands
[2].reg
;
12272 reject_bad_reg (Rd
);
12273 reject_bad_reg (Rn
);
12275 inst
.instruction
|= Rd
<< 8;
12276 inst
.instruction
|= inst
.operands
[1].imm
;
12277 inst
.instruction
|= Rn
<< 16;
12280 /* Neon instruction encoder helpers. */
12282 /* Encodings for the different types for various Neon opcodes. */
12284 /* An "invalid" code for the following tables. */
12287 struct neon_tab_entry
12290 unsigned float_or_poly
;
12291 unsigned scalar_or_imm
;
12294 /* Map overloaded Neon opcodes to their respective encodings. */
12295 #define NEON_ENC_TAB \
12296 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12297 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12298 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12299 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12300 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12301 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12302 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12303 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12304 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12305 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12306 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12307 /* Register variants of the following two instructions are encoded as
12308 vcge / vcgt with the operands reversed. */ \
12309 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12310 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12311 X(vfma, N_INV, 0x0000c10, N_INV), \
12312 X(vfms, N_INV, 0x0200c10, N_INV), \
12313 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12314 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12315 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12316 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12317 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12318 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12319 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12320 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12321 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12322 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12323 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12324 X(vshl, 0x0000400, N_INV, 0x0800510), \
12325 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12326 X(vand, 0x0000110, N_INV, 0x0800030), \
12327 X(vbic, 0x0100110, N_INV, 0x0800030), \
12328 X(veor, 0x1000110, N_INV, N_INV), \
12329 X(vorn, 0x0300110, N_INV, 0x0800010), \
12330 X(vorr, 0x0200110, N_INV, 0x0800010), \
12331 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12332 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12333 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12334 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12335 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12336 X(vst1, 0x0000000, 0x0800000, N_INV), \
12337 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12338 X(vst2, 0x0000100, 0x0800100, N_INV), \
12339 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12340 X(vst3, 0x0000200, 0x0800200, N_INV), \
12341 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12342 X(vst4, 0x0000300, 0x0800300, N_INV), \
12343 X(vmovn, 0x1b20200, N_INV, N_INV), \
12344 X(vtrn, 0x1b20080, N_INV, N_INV), \
12345 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12346 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12347 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12348 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12349 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12350 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12351 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12352 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12353 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12354 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12355 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12356 X(vseleq, 0xe000a00, N_INV, N_INV), \
12357 X(vselvs, 0xe100a00, N_INV, N_INV), \
12358 X(vselge, 0xe200a00, N_INV, N_INV), \
12359 X(vselgt, 0xe300a00, N_INV, N_INV), \
12360 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12361 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12362 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12363 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12364 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12365 X(aes, 0x3b00300, N_INV, N_INV), \
12366 X(sha3op, 0x2000c00, N_INV, N_INV), \
12367 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12368 X(sha2op, 0x3ba0380, N_INV, N_INV)
12372 #define X(OPC,I,F,S) N_MNEM_##OPC
12377 static const struct neon_tab_entry neon_enc_tab
[] =
12379 #define X(OPC,I,F,S) { (I), (F), (S) }
12384 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12385 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12386 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12387 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12388 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12389 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12390 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12391 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12392 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12393 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12394 #define NEON_ENC_SINGLE_(X) \
12395 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12396 #define NEON_ENC_DOUBLE_(X) \
12397 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12398 #define NEON_ENC_FPV8_(X) \
12399 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12401 #define NEON_ENCODE(type, inst) \
12404 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12405 inst.is_neon = 1; \
12409 #define check_neon_suffixes \
12412 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12414 as_bad (_("invalid neon suffix for non neon instruction")); \
12420 /* Define shapes for instruction operands. The following mnemonic characters
12421 are used in this table:
12423 F - VFP S<n> register
12424 D - Neon D<n> register
12425 Q - Neon Q<n> register
12429 L - D<n> register list
12431 This table is used to generate various data:
12432 - enumerations of the form NS_DDR to be used as arguments to
12434 - a table classifying shapes into single, double, quad, mixed.
12435 - a table used to drive neon_select_shape. */
12437 #define NEON_SHAPE_DEF \
12438 X(3, (D, D, D), DOUBLE), \
12439 X(3, (Q, Q, Q), QUAD), \
12440 X(3, (D, D, I), DOUBLE), \
12441 X(3, (Q, Q, I), QUAD), \
12442 X(3, (D, D, S), DOUBLE), \
12443 X(3, (Q, Q, S), QUAD), \
12444 X(2, (D, D), DOUBLE), \
12445 X(2, (Q, Q), QUAD), \
12446 X(2, (D, S), DOUBLE), \
12447 X(2, (Q, S), QUAD), \
12448 X(2, (D, R), DOUBLE), \
12449 X(2, (Q, R), QUAD), \
12450 X(2, (D, I), DOUBLE), \
12451 X(2, (Q, I), QUAD), \
12452 X(3, (D, L, D), DOUBLE), \
12453 X(2, (D, Q), MIXED), \
12454 X(2, (Q, D), MIXED), \
12455 X(3, (D, Q, I), MIXED), \
12456 X(3, (Q, D, I), MIXED), \
12457 X(3, (Q, D, D), MIXED), \
12458 X(3, (D, Q, Q), MIXED), \
12459 X(3, (Q, Q, D), MIXED), \
12460 X(3, (Q, D, S), MIXED), \
12461 X(3, (D, Q, S), MIXED), \
12462 X(4, (D, D, D, I), DOUBLE), \
12463 X(4, (Q, Q, Q, I), QUAD), \
12464 X(2, (F, F), SINGLE), \
12465 X(3, (F, F, F), SINGLE), \
12466 X(2, (F, I), SINGLE), \
12467 X(2, (F, D), MIXED), \
12468 X(2, (D, F), MIXED), \
12469 X(3, (F, F, I), MIXED), \
12470 X(4, (R, R, F, F), SINGLE), \
12471 X(4, (F, F, R, R), SINGLE), \
12472 X(3, (D, R, R), DOUBLE), \
12473 X(3, (R, R, D), DOUBLE), \
12474 X(2, (S, R), SINGLE), \
12475 X(2, (R, S), SINGLE), \
12476 X(2, (F, R), SINGLE), \
12477 X(2, (R, F), SINGLE)
12479 #define S2(A,B) NS_##A##B
12480 #define S3(A,B,C) NS_##A##B##C
12481 #define S4(A,B,C,D) NS_##A##B##C##D
12483 #define X(N, L, C) S##N L
12496 enum neon_shape_class
12504 #define X(N, L, C) SC_##C
12506 static enum neon_shape_class neon_shape_class
[] =
12524 /* Register widths of above. */
12525 static unsigned neon_shape_el_size
[] =
12536 struct neon_shape_info
12539 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12542 #define S2(A,B) { SE_##A, SE_##B }
12543 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12544 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12546 #define X(N, L, C) { N, S##N L }
12548 static struct neon_shape_info neon_shape_tab
[] =
12558 /* Bit masks used in type checking given instructions.
12559 'N_EQK' means the type must be the same as (or based on in some way) the key
12560 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12561 set, various other bits can be set as well in order to modify the meaning of
12562 the type constraint. */
12564 enum neon_type_mask
12588 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12589 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12590 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12591 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
12592 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12593 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12594 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12595 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12596 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12597 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12598 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12600 N_MAX_NONSPECIAL
= N_P64
12603 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12605 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12606 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12607 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12608 #define N_SUF_32 (N_SU_32 | N_F32)
12609 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12610 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12612 /* Pass this as the first type argument to neon_check_type to ignore types
12614 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12616 /* Select a "shape" for the current instruction (describing register types or
12617 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12618 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12619 function of operand parsing, so this function doesn't need to be called.
12620 Shapes should be listed in order of decreasing length. */
12622 static enum neon_shape
12623 neon_select_shape (enum neon_shape shape
, ...)
12626 enum neon_shape first_shape
= shape
;
12628 /* Fix missing optional operands. FIXME: we don't know at this point how
12629 many arguments we should have, so this makes the assumption that we have
12630 > 1. This is true of all current Neon opcodes, I think, but may not be
12631 true in the future. */
12632 if (!inst
.operands
[1].present
)
12633 inst
.operands
[1] = inst
.operands
[0];
12635 va_start (ap
, shape
);
12637 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12642 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12644 if (!inst
.operands
[j
].present
)
12650 switch (neon_shape_tab
[shape
].el
[j
])
12653 if (!(inst
.operands
[j
].isreg
12654 && inst
.operands
[j
].isvec
12655 && inst
.operands
[j
].issingle
12656 && !inst
.operands
[j
].isquad
))
12661 if (!(inst
.operands
[j
].isreg
12662 && inst
.operands
[j
].isvec
12663 && !inst
.operands
[j
].isquad
12664 && !inst
.operands
[j
].issingle
))
12669 if (!(inst
.operands
[j
].isreg
12670 && !inst
.operands
[j
].isvec
))
12675 if (!(inst
.operands
[j
].isreg
12676 && inst
.operands
[j
].isvec
12677 && inst
.operands
[j
].isquad
12678 && !inst
.operands
[j
].issingle
))
12683 if (!(!inst
.operands
[j
].isreg
12684 && !inst
.operands
[j
].isscalar
))
12689 if (!(!inst
.operands
[j
].isreg
12690 && inst
.operands
[j
].isscalar
))
12700 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
12701 /* We've matched all the entries in the shape table, and we don't
12702 have any left over operands which have not been matched. */
12708 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12709 first_error (_("invalid instruction shape"));
12714 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12715 means the Q bit should be set). */
12718 neon_quad (enum neon_shape shape
)
12720 return neon_shape_class
[shape
] == SC_QUAD
;
12724 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12727 /* Allow modification to be made to types which are constrained to be
12728 based on the key element, based on bits set alongside N_EQK. */
12729 if ((typebits
& N_EQK
) != 0)
12731 if ((typebits
& N_HLF
) != 0)
12733 else if ((typebits
& N_DBL
) != 0)
12735 if ((typebits
& N_SGN
) != 0)
12736 *g_type
= NT_signed
;
12737 else if ((typebits
& N_UNS
) != 0)
12738 *g_type
= NT_unsigned
;
12739 else if ((typebits
& N_INT
) != 0)
12740 *g_type
= NT_integer
;
12741 else if ((typebits
& N_FLT
) != 0)
12742 *g_type
= NT_float
;
12743 else if ((typebits
& N_SIZ
) != 0)
12744 *g_type
= NT_untyped
;
12748 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12749 operand type, i.e. the single type specified in a Neon instruction when it
12750 is the only one given. */
12752 static struct neon_type_el
12753 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12755 struct neon_type_el dest
= *key
;
12757 gas_assert ((thisarg
& N_EQK
) != 0);
12759 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12764 /* Convert Neon type and size into compact bitmask representation. */
12766 static enum neon_type_mask
12767 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12774 case 8: return N_8
;
12775 case 16: return N_16
;
12776 case 32: return N_32
;
12777 case 64: return N_64
;
12785 case 8: return N_I8
;
12786 case 16: return N_I16
;
12787 case 32: return N_I32
;
12788 case 64: return N_I64
;
12796 case 16: return N_F16
;
12797 case 32: return N_F32
;
12798 case 64: return N_F64
;
12806 case 8: return N_P8
;
12807 case 16: return N_P16
;
12808 case 64: return N_P64
;
12816 case 8: return N_S8
;
12817 case 16: return N_S16
;
12818 case 32: return N_S32
;
12819 case 64: return N_S64
;
12827 case 8: return N_U8
;
12828 case 16: return N_U16
;
12829 case 32: return N_U32
;
12830 case 64: return N_U64
;
12841 /* Convert compact Neon bitmask type representation to a type and size. Only
12842 handles the case where a single bit is set in the mask. */
12845 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12846 enum neon_type_mask mask
)
12848 if ((mask
& N_EQK
) != 0)
12851 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12853 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
12855 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12857 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
12862 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12864 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12865 *type
= NT_unsigned
;
12866 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12867 *type
= NT_integer
;
12868 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12869 *type
= NT_untyped
;
12870 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
12872 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
12880 /* Modify a bitmask of allowed types. This is only needed for type
12884 modify_types_allowed (unsigned allowed
, unsigned mods
)
12887 enum neon_el_type type
;
12893 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12895 if (el_type_of_type_chk (&type
, &size
,
12896 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12898 neon_modify_type_size (mods
, &type
, &size
);
12899 destmask
|= type_chk_of_el_type (type
, size
);
12906 /* Check type and return type classification.
12907 The manual states (paraphrase): If one datatype is given, it indicates the
12909 - the second operand, if there is one
12910 - the operand, if there is no second operand
12911 - the result, if there are no operands.
12912 This isn't quite good enough though, so we use a concept of a "key" datatype
12913 which is set on a per-instruction basis, which is the one which matters when
12914 only one data type is written.
12915 Note: this function has side-effects (e.g. filling in missing operands). All
12916 Neon instructions should call it before performing bit encoding. */
12918 static struct neon_type_el
12919 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12922 unsigned i
, pass
, key_el
= 0;
12923 unsigned types
[NEON_MAX_TYPE_ELS
];
12924 enum neon_el_type k_type
= NT_invtype
;
12925 unsigned k_size
= -1u;
12926 struct neon_type_el badtype
= {NT_invtype
, -1};
12927 unsigned key_allowed
= 0;
12929 /* Optional registers in Neon instructions are always (not) in operand 1.
12930 Fill in the missing operand here, if it was omitted. */
12931 if (els
> 1 && !inst
.operands
[1].present
)
12932 inst
.operands
[1] = inst
.operands
[0];
12934 /* Suck up all the varargs. */
12936 for (i
= 0; i
< els
; i
++)
12938 unsigned thisarg
= va_arg (ap
, unsigned);
12939 if (thisarg
== N_IGNORE_TYPE
)
12944 types
[i
] = thisarg
;
12945 if ((thisarg
& N_KEY
) != 0)
12950 if (inst
.vectype
.elems
> 0)
12951 for (i
= 0; i
< els
; i
++)
12952 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12954 first_error (_("types specified in both the mnemonic and operands"));
12958 /* Duplicate inst.vectype elements here as necessary.
12959 FIXME: No idea if this is exactly the same as the ARM assembler,
12960 particularly when an insn takes one register and one non-register
12962 if (inst
.vectype
.elems
== 1 && els
> 1)
12965 inst
.vectype
.elems
= els
;
12966 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12967 for (j
= 0; j
< els
; j
++)
12969 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12972 else if (inst
.vectype
.elems
== 0 && els
> 0)
12975 /* No types were given after the mnemonic, so look for types specified
12976 after each operand. We allow some flexibility here; as long as the
12977 "key" operand has a type, we can infer the others. */
12978 for (j
= 0; j
< els
; j
++)
12979 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12980 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12982 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12984 for (j
= 0; j
< els
; j
++)
12985 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12986 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12991 first_error (_("operand types can't be inferred"));
12995 else if (inst
.vectype
.elems
!= els
)
12997 first_error (_("type specifier has the wrong number of parts"));
13001 for (pass
= 0; pass
< 2; pass
++)
13003 for (i
= 0; i
< els
; i
++)
13005 unsigned thisarg
= types
[i
];
13006 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13007 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13008 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13009 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13011 /* Decay more-specific signed & unsigned types to sign-insensitive
13012 integer types if sign-specific variants are unavailable. */
13013 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13014 && (types_allowed
& N_SU_ALL
) == 0)
13015 g_type
= NT_integer
;
13017 /* If only untyped args are allowed, decay any more specific types to
13018 them. Some instructions only care about signs for some element
13019 sizes, so handle that properly. */
13020 if (((types_allowed
& N_UNT
) == 0)
13021 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13022 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13023 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13024 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13025 g_type
= NT_untyped
;
13029 if ((thisarg
& N_KEY
) != 0)
13033 key_allowed
= thisarg
& ~N_KEY
;
13038 if ((thisarg
& N_VFP
) != 0)
13040 enum neon_shape_el regshape
;
13041 unsigned regwidth
, match
;
13043 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13046 first_error (_("invalid instruction shape"));
13049 regshape
= neon_shape_tab
[ns
].el
[i
];
13050 regwidth
= neon_shape_el_size
[regshape
];
13052 /* In VFP mode, operands must match register widths. If we
13053 have a key operand, use its width, else use the width of
13054 the current operand. */
13060 if (regwidth
!= match
)
13062 first_error (_("operand size must match register width"));
13067 if ((thisarg
& N_EQK
) == 0)
13069 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13071 if ((given_type
& types_allowed
) == 0)
13073 first_error (_("bad type in Neon instruction"));
13079 enum neon_el_type mod_k_type
= k_type
;
13080 unsigned mod_k_size
= k_size
;
13081 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13082 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13084 first_error (_("inconsistent types in Neon instruction"));
13092 return inst
.vectype
.el
[key_el
];
13095 /* Neon-style VFP instruction forwarding. */
13097 /* Thumb VFP instructions have 0xE in the condition field. */
13100 do_vfp_cond_or_thumb (void)
13105 inst
.instruction
|= 0xe0000000;
13107 inst
.instruction
|= inst
.cond
<< 28;
13110 /* Look up and encode a simple mnemonic, for use as a helper function for the
13111 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13112 etc. It is assumed that operand parsing has already been done, and that the
13113 operands are in the form expected by the given opcode (this isn't necessarily
13114 the same as the form in which they were parsed, hence some massaging must
13115 take place before this function is called).
13116 Checks current arch version against that in the looked-up opcode. */
13119 do_vfp_nsyn_opcode (const char *opname
)
13121 const struct asm_opcode
*opcode
;
13123 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13128 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13129 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13136 inst
.instruction
= opcode
->tvalue
;
13137 opcode
->tencode ();
13141 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13142 opcode
->aencode ();
13147 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13149 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13154 do_vfp_nsyn_opcode ("fadds");
13156 do_vfp_nsyn_opcode ("fsubs");
13161 do_vfp_nsyn_opcode ("faddd");
13163 do_vfp_nsyn_opcode ("fsubd");
13167 /* Check operand types to see if this is a VFP instruction, and if so call
13171 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13173 enum neon_shape rs
;
13174 struct neon_type_el et
;
13179 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13180 et
= neon_check_type (2, rs
,
13181 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13185 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13186 et
= neon_check_type (3, rs
,
13187 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13194 if (et
.type
!= NT_invtype
)
13205 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13207 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13212 do_vfp_nsyn_opcode ("fmacs");
13214 do_vfp_nsyn_opcode ("fnmacs");
13219 do_vfp_nsyn_opcode ("fmacd");
13221 do_vfp_nsyn_opcode ("fnmacd");
13226 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13228 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13233 do_vfp_nsyn_opcode ("ffmas");
13235 do_vfp_nsyn_opcode ("ffnmas");
13240 do_vfp_nsyn_opcode ("ffmad");
13242 do_vfp_nsyn_opcode ("ffnmad");
13247 do_vfp_nsyn_mul (enum neon_shape rs
)
13250 do_vfp_nsyn_opcode ("fmuls");
13252 do_vfp_nsyn_opcode ("fmuld");
13256 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13258 int is_neg
= (inst
.instruction
& 0x80) != 0;
13259 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13264 do_vfp_nsyn_opcode ("fnegs");
13266 do_vfp_nsyn_opcode ("fabss");
13271 do_vfp_nsyn_opcode ("fnegd");
13273 do_vfp_nsyn_opcode ("fabsd");
13277 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13278 insns belong to Neon, and are handled elsewhere. */
13281 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13283 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13287 do_vfp_nsyn_opcode ("fldmdbs");
13289 do_vfp_nsyn_opcode ("fldmias");
13294 do_vfp_nsyn_opcode ("fstmdbs");
13296 do_vfp_nsyn_opcode ("fstmias");
13301 do_vfp_nsyn_sqrt (void)
13303 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13304 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13307 do_vfp_nsyn_opcode ("fsqrts");
13309 do_vfp_nsyn_opcode ("fsqrtd");
13313 do_vfp_nsyn_div (void)
13315 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13316 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13317 N_F32
| N_F64
| N_KEY
| N_VFP
);
13320 do_vfp_nsyn_opcode ("fdivs");
13322 do_vfp_nsyn_opcode ("fdivd");
13326 do_vfp_nsyn_nmul (void)
13328 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13329 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13330 N_F32
| N_F64
| N_KEY
| N_VFP
);
13334 NEON_ENCODE (SINGLE
, inst
);
13335 do_vfp_sp_dyadic ();
13339 NEON_ENCODE (DOUBLE
, inst
);
13340 do_vfp_dp_rd_rn_rm ();
13342 do_vfp_cond_or_thumb ();
13346 do_vfp_nsyn_cmp (void)
13348 if (inst
.operands
[1].isreg
)
13350 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13351 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13355 NEON_ENCODE (SINGLE
, inst
);
13356 do_vfp_sp_monadic ();
13360 NEON_ENCODE (DOUBLE
, inst
);
13361 do_vfp_dp_rd_rm ();
13366 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13367 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13369 switch (inst
.instruction
& 0x0fffffff)
13372 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13375 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13383 NEON_ENCODE (SINGLE
, inst
);
13384 do_vfp_sp_compare_z ();
13388 NEON_ENCODE (DOUBLE
, inst
);
13392 do_vfp_cond_or_thumb ();
13396 nsyn_insert_sp (void)
13398 inst
.operands
[1] = inst
.operands
[0];
13399 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13400 inst
.operands
[0].reg
= REG_SP
;
13401 inst
.operands
[0].isreg
= 1;
13402 inst
.operands
[0].writeback
= 1;
13403 inst
.operands
[0].present
= 1;
13407 do_vfp_nsyn_push (void)
13410 if (inst
.operands
[1].issingle
)
13411 do_vfp_nsyn_opcode ("fstmdbs");
13413 do_vfp_nsyn_opcode ("fstmdbd");
13417 do_vfp_nsyn_pop (void)
13420 if (inst
.operands
[1].issingle
)
13421 do_vfp_nsyn_opcode ("fldmias");
13423 do_vfp_nsyn_opcode ("fldmiad");
13426 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13427 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13430 neon_dp_fixup (struct arm_it
* insn
)
13432 unsigned int i
= insn
->instruction
;
13437 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13448 insn
->instruction
= i
;
13451 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13455 neon_logbits (unsigned x
)
13457 return ffs (x
) - 4;
13460 #define LOW4(R) ((R) & 0xf)
13461 #define HI1(R) (((R) >> 4) & 1)
13463 /* Encode insns with bit pattern:
13465 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13466 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13468 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13469 different meaning for some instruction. */
13472 neon_three_same (int isquad
, int ubit
, int size
)
13474 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13475 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13476 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13477 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13478 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13479 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13480 inst
.instruction
|= (isquad
!= 0) << 6;
13481 inst
.instruction
|= (ubit
!= 0) << 24;
13483 inst
.instruction
|= neon_logbits (size
) << 20;
13485 neon_dp_fixup (&inst
);
13488 /* Encode instructions of the form:
13490 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13491 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13493 Don't write size if SIZE == -1. */
13496 neon_two_same (int qbit
, int ubit
, int size
)
13498 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13499 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13500 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13501 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13502 inst
.instruction
|= (qbit
!= 0) << 6;
13503 inst
.instruction
|= (ubit
!= 0) << 24;
13506 inst
.instruction
|= neon_logbits (size
) << 18;
13508 neon_dp_fixup (&inst
);
13511 /* Neon instruction encoders, in approximate order of appearance. */
13514 do_neon_dyadic_i_su (void)
13516 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13517 struct neon_type_el et
= neon_check_type (3, rs
,
13518 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13519 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13523 do_neon_dyadic_i64_su (void)
13525 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13526 struct neon_type_el et
= neon_check_type (3, rs
,
13527 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13528 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13532 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13535 unsigned size
= et
.size
>> 3;
13536 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13537 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13538 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13539 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13540 inst
.instruction
|= (isquad
!= 0) << 6;
13541 inst
.instruction
|= immbits
<< 16;
13542 inst
.instruction
|= (size
>> 3) << 7;
13543 inst
.instruction
|= (size
& 0x7) << 19;
13545 inst
.instruction
|= (uval
!= 0) << 24;
13547 neon_dp_fixup (&inst
);
13551 do_neon_shl_imm (void)
13553 if (!inst
.operands
[2].isreg
)
13555 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13556 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13557 NEON_ENCODE (IMMED
, inst
);
13558 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13562 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13563 struct neon_type_el et
= neon_check_type (3, rs
,
13564 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13567 /* VSHL/VQSHL 3-register variants have syntax such as:
13569 whereas other 3-register operations encoded by neon_three_same have
13572 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13574 tmp
= inst
.operands
[2].reg
;
13575 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13576 inst
.operands
[1].reg
= tmp
;
13577 NEON_ENCODE (INTEGER
, inst
);
13578 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13583 do_neon_qshl_imm (void)
13585 if (!inst
.operands
[2].isreg
)
13587 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13588 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13590 NEON_ENCODE (IMMED
, inst
);
13591 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13592 inst
.operands
[2].imm
);
13596 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13597 struct neon_type_el et
= neon_check_type (3, rs
,
13598 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13601 /* See note in do_neon_shl_imm. */
13602 tmp
= inst
.operands
[2].reg
;
13603 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13604 inst
.operands
[1].reg
= tmp
;
13605 NEON_ENCODE (INTEGER
, inst
);
13606 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13611 do_neon_rshl (void)
13613 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13614 struct neon_type_el et
= neon_check_type (3, rs
,
13615 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13618 tmp
= inst
.operands
[2].reg
;
13619 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13620 inst
.operands
[1].reg
= tmp
;
13621 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13625 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13627 /* Handle .I8 pseudo-instructions. */
13630 /* Unfortunately, this will make everything apart from zero out-of-range.
13631 FIXME is this the intended semantics? There doesn't seem much point in
13632 accepting .I8 if so. */
13633 immediate
|= immediate
<< 8;
13639 if (immediate
== (immediate
& 0x000000ff))
13641 *immbits
= immediate
;
13644 else if (immediate
== (immediate
& 0x0000ff00))
13646 *immbits
= immediate
>> 8;
13649 else if (immediate
== (immediate
& 0x00ff0000))
13651 *immbits
= immediate
>> 16;
13654 else if (immediate
== (immediate
& 0xff000000))
13656 *immbits
= immediate
>> 24;
13659 if ((immediate
& 0xffff) != (immediate
>> 16))
13660 goto bad_immediate
;
13661 immediate
&= 0xffff;
13664 if (immediate
== (immediate
& 0x000000ff))
13666 *immbits
= immediate
;
13669 else if (immediate
== (immediate
& 0x0000ff00))
13671 *immbits
= immediate
>> 8;
13676 first_error (_("immediate value out of range"));
13680 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13684 neon_bits_same_in_bytes (unsigned imm
)
13686 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13687 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13688 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13689 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13692 /* For immediate of above form, return 0bABCD. */
13695 neon_squash_bits (unsigned imm
)
13697 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13698 | ((imm
& 0x01000000) >> 21);
13701 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13704 neon_qfloat_bits (unsigned imm
)
13706 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13709 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13710 the instruction. *OP is passed as the initial value of the op field, and
13711 may be set to a different value depending on the constant (i.e.
13712 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13713 MVN). If the immediate looks like a repeated pattern then also
13714 try smaller element sizes. */
13717 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13718 unsigned *immbits
, int *op
, int size
,
13719 enum neon_el_type type
)
13721 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13723 if (type
== NT_float
&& !float_p
)
13726 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13728 if (size
!= 32 || *op
== 1)
13730 *immbits
= neon_qfloat_bits (immlo
);
13736 if (neon_bits_same_in_bytes (immhi
)
13737 && neon_bits_same_in_bytes (immlo
))
13741 *immbits
= (neon_squash_bits (immhi
) << 4)
13742 | neon_squash_bits (immlo
);
13747 if (immhi
!= immlo
)
13753 if (immlo
== (immlo
& 0x000000ff))
13758 else if (immlo
== (immlo
& 0x0000ff00))
13760 *immbits
= immlo
>> 8;
13763 else if (immlo
== (immlo
& 0x00ff0000))
13765 *immbits
= immlo
>> 16;
13768 else if (immlo
== (immlo
& 0xff000000))
13770 *immbits
= immlo
>> 24;
13773 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13775 *immbits
= (immlo
>> 8) & 0xff;
13778 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13780 *immbits
= (immlo
>> 16) & 0xff;
13784 if ((immlo
& 0xffff) != (immlo
>> 16))
13791 if (immlo
== (immlo
& 0x000000ff))
13796 else if (immlo
== (immlo
& 0x0000ff00))
13798 *immbits
= immlo
>> 8;
13802 if ((immlo
& 0xff) != (immlo
>> 8))
13807 if (immlo
== (immlo
& 0x000000ff))
13809 /* Don't allow MVN with 8-bit immediate. */
13819 /* Write immediate bits [7:0] to the following locations:
13821 |28/24|23 19|18 16|15 4|3 0|
13822 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13824 This function is used by VMOV/VMVN/VORR/VBIC. */
13827 neon_write_immbits (unsigned immbits
)
13829 inst
.instruction
|= immbits
& 0xf;
13830 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13831 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13834 /* Invert low-order SIZE bits of XHI:XLO. */
13837 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13839 unsigned immlo
= xlo
? *xlo
: 0;
13840 unsigned immhi
= xhi
? *xhi
: 0;
13845 immlo
= (~immlo
) & 0xff;
13849 immlo
= (~immlo
) & 0xffff;
13853 immhi
= (~immhi
) & 0xffffffff;
13854 /* fall through. */
13857 immlo
= (~immlo
) & 0xffffffff;
13872 do_neon_logic (void)
13874 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13876 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13877 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13878 /* U bit and size field were set as part of the bitmask. */
13879 NEON_ENCODE (INTEGER
, inst
);
13880 neon_three_same (neon_quad (rs
), 0, -1);
13884 const int three_ops_form
= (inst
.operands
[2].present
13885 && !inst
.operands
[2].isreg
);
13886 const int immoperand
= (three_ops_form
? 2 : 1);
13887 enum neon_shape rs
= (three_ops_form
13888 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13889 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13890 struct neon_type_el et
= neon_check_type (2, rs
,
13891 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13892 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13896 if (et
.type
== NT_invtype
)
13899 if (three_ops_form
)
13900 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13901 _("first and second operands shall be the same register"));
13903 NEON_ENCODE (IMMED
, inst
);
13905 immbits
= inst
.operands
[immoperand
].imm
;
13908 /* .i64 is a pseudo-op, so the immediate must be a repeating
13910 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13911 inst
.operands
[immoperand
].reg
: 0))
13913 /* Set immbits to an invalid constant. */
13914 immbits
= 0xdeadbeef;
13921 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13925 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13929 /* Pseudo-instruction for VBIC. */
13930 neon_invert_size (&immbits
, 0, et
.size
);
13931 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13935 /* Pseudo-instruction for VORR. */
13936 neon_invert_size (&immbits
, 0, et
.size
);
13937 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13947 inst
.instruction
|= neon_quad (rs
) << 6;
13948 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13949 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13950 inst
.instruction
|= cmode
<< 8;
13951 neon_write_immbits (immbits
);
13953 neon_dp_fixup (&inst
);
13958 do_neon_bitfield (void)
13960 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13961 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13962 neon_three_same (neon_quad (rs
), 0, -1);
13966 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13969 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13970 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13972 if (et
.type
== NT_float
)
13974 NEON_ENCODE (FLOAT
, inst
);
13975 neon_three_same (neon_quad (rs
), 0, -1);
13979 NEON_ENCODE (INTEGER
, inst
);
13980 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13985 do_neon_dyadic_if_su (void)
13987 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13991 do_neon_dyadic_if_su_d (void)
13993 /* This version only allow D registers, but that constraint is enforced during
13994 operand parsing so we don't need to do anything extra here. */
13995 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13999 do_neon_dyadic_if_i_d (void)
14001 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14002 affected if we specify unsigned args. */
14003 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14006 enum vfp_or_neon_is_neon_bits
14009 NEON_CHECK_ARCH
= 2,
14010 NEON_CHECK_ARCH8
= 4
14013 /* Call this function if an instruction which may have belonged to the VFP or
14014 Neon instruction sets, but turned out to be a Neon instruction (due to the
14015 operand types involved, etc.). We have to check and/or fix-up a couple of
14018 - Make sure the user hasn't attempted to make a Neon instruction
14020 - Alter the value in the condition code field if necessary.
14021 - Make sure that the arch supports Neon instructions.
14023 Which of these operations take place depends on bits from enum
14024 vfp_or_neon_is_neon_bits.
14026 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14027 current instruction's condition is COND_ALWAYS, the condition field is
14028 changed to inst.uncond_value. This is necessary because instructions shared
14029 between VFP and Neon may be conditional for the VFP variants only, and the
14030 unconditional Neon version must have, e.g., 0xF in the condition field. */
14033 vfp_or_neon_is_neon (unsigned check
)
14035 /* Conditions are always legal in Thumb mode (IT blocks). */
14036 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14038 if (inst
.cond
!= COND_ALWAYS
)
14040 first_error (_(BAD_COND
));
14043 if (inst
.uncond_value
!= -1)
14044 inst
.instruction
|= inst
.uncond_value
<< 28;
14047 if ((check
& NEON_CHECK_ARCH
)
14048 && !mark_feature_used (&fpu_neon_ext_v1
))
14050 first_error (_(BAD_FPU
));
14054 if ((check
& NEON_CHECK_ARCH8
)
14055 && !mark_feature_used (&fpu_neon_ext_armv8
))
14057 first_error (_(BAD_FPU
));
14065 do_neon_addsub_if_i (void)
14067 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14070 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14073 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14074 affected if we specify unsigned args. */
14075 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14078 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14080 V<op> A,B (A is operand 0, B is operand 2)
14085 so handle that case specially. */
14088 neon_exchange_operands (void)
14090 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14091 if (inst
.operands
[1].present
)
14093 /* Swap operands[1] and operands[2]. */
14094 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14095 inst
.operands
[1] = inst
.operands
[2];
14096 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14100 inst
.operands
[1] = inst
.operands
[2];
14101 inst
.operands
[2] = inst
.operands
[0];
14106 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14108 if (inst
.operands
[2].isreg
)
14111 neon_exchange_operands ();
14112 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14116 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14117 struct neon_type_el et
= neon_check_type (2, rs
,
14118 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14120 NEON_ENCODE (IMMED
, inst
);
14121 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14122 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14123 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14124 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14125 inst
.instruction
|= neon_quad (rs
) << 6;
14126 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14127 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14129 neon_dp_fixup (&inst
);
14136 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14140 do_neon_cmp_inv (void)
14142 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14148 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14151 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14152 scalars, which are encoded in 5 bits, M : Rm.
14153 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14154 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14158 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14160 unsigned regno
= NEON_SCALAR_REG (scalar
);
14161 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14166 if (regno
> 7 || elno
> 3)
14168 return regno
| (elno
<< 3);
14171 if (regno
> 15 || elno
> 1)
14173 return regno
| (elno
<< 4);
14177 first_error (_("scalar out of range for multiply instruction"));
14183 /* Encode multiply / multiply-accumulate scalar instructions. */
14186 neon_mul_mac (struct neon_type_el et
, int ubit
)
14190 /* Give a more helpful error message if we have an invalid type. */
14191 if (et
.type
== NT_invtype
)
14194 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14195 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14196 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14197 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14198 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14199 inst
.instruction
|= LOW4 (scalar
);
14200 inst
.instruction
|= HI1 (scalar
) << 5;
14201 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14202 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14203 inst
.instruction
|= (ubit
!= 0) << 24;
14205 neon_dp_fixup (&inst
);
14209 do_neon_mac_maybe_scalar (void)
14211 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14214 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14217 if (inst
.operands
[2].isscalar
)
14219 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14220 struct neon_type_el et
= neon_check_type (3, rs
,
14221 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14222 NEON_ENCODE (SCALAR
, inst
);
14223 neon_mul_mac (et
, neon_quad (rs
));
14227 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14228 affected if we specify unsigned args. */
14229 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14234 do_neon_fmac (void)
14236 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14239 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14242 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14248 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14249 struct neon_type_el et
= neon_check_type (3, rs
,
14250 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14251 neon_three_same (neon_quad (rs
), 0, et
.size
);
14254 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14255 same types as the MAC equivalents. The polynomial type for this instruction
14256 is encoded the same as the integer type. */
14261 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14264 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14267 if (inst
.operands
[2].isscalar
)
14268 do_neon_mac_maybe_scalar ();
14270 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14274 do_neon_qdmulh (void)
14276 if (inst
.operands
[2].isscalar
)
14278 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14279 struct neon_type_el et
= neon_check_type (3, rs
,
14280 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14281 NEON_ENCODE (SCALAR
, inst
);
14282 neon_mul_mac (et
, neon_quad (rs
));
14286 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14287 struct neon_type_el et
= neon_check_type (3, rs
,
14288 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14289 NEON_ENCODE (INTEGER
, inst
);
14290 /* The U bit (rounding) comes from bit mask. */
14291 neon_three_same (neon_quad (rs
), 0, et
.size
);
14296 do_neon_fcmp_absolute (void)
14298 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14299 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14300 /* Size field comes from bit mask. */
14301 neon_three_same (neon_quad (rs
), 1, -1);
14305 do_neon_fcmp_absolute_inv (void)
14307 neon_exchange_operands ();
14308 do_neon_fcmp_absolute ();
14312 do_neon_step (void)
14314 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14315 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14316 neon_three_same (neon_quad (rs
), 0, -1);
14320 do_neon_abs_neg (void)
14322 enum neon_shape rs
;
14323 struct neon_type_el et
;
14325 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14328 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14331 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14332 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14334 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14335 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14336 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14337 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14338 inst
.instruction
|= neon_quad (rs
) << 6;
14339 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14340 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14342 neon_dp_fixup (&inst
);
14348 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14349 struct neon_type_el et
= neon_check_type (2, rs
,
14350 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14351 int imm
= inst
.operands
[2].imm
;
14352 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14353 _("immediate out of range for insert"));
14354 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14360 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14361 struct neon_type_el et
= neon_check_type (2, rs
,
14362 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14363 int imm
= inst
.operands
[2].imm
;
14364 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14365 _("immediate out of range for insert"));
14366 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14370 do_neon_qshlu_imm (void)
14372 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14373 struct neon_type_el et
= neon_check_type (2, rs
,
14374 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14375 int imm
= inst
.operands
[2].imm
;
14376 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14377 _("immediate out of range for shift"));
14378 /* Only encodes the 'U present' variant of the instruction.
14379 In this case, signed types have OP (bit 8) set to 0.
14380 Unsigned types have OP set to 1. */
14381 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14382 /* The rest of the bits are the same as other immediate shifts. */
14383 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14387 do_neon_qmovn (void)
14389 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14390 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14391 /* Saturating move where operands can be signed or unsigned, and the
14392 destination has the same signedness. */
14393 NEON_ENCODE (INTEGER
, inst
);
14394 if (et
.type
== NT_unsigned
)
14395 inst
.instruction
|= 0xc0;
14397 inst
.instruction
|= 0x80;
14398 neon_two_same (0, 1, et
.size
/ 2);
14402 do_neon_qmovun (void)
14404 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14405 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14406 /* Saturating move with unsigned results. Operands must be signed. */
14407 NEON_ENCODE (INTEGER
, inst
);
14408 neon_two_same (0, 1, et
.size
/ 2);
14412 do_neon_rshift_sat_narrow (void)
14414 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14415 or unsigned. If operands are unsigned, results must also be unsigned. */
14416 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14417 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14418 int imm
= inst
.operands
[2].imm
;
14419 /* This gets the bounds check, size encoding and immediate bits calculation
14423 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14424 VQMOVN.I<size> <Dd>, <Qm>. */
14427 inst
.operands
[2].present
= 0;
14428 inst
.instruction
= N_MNEM_vqmovn
;
14433 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14434 _("immediate out of range"));
14435 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14439 do_neon_rshift_sat_narrow_u (void)
14441 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14442 or unsigned. If operands are unsigned, results must also be unsigned. */
14443 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14444 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14445 int imm
= inst
.operands
[2].imm
;
14446 /* This gets the bounds check, size encoding and immediate bits calculation
14450 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14451 VQMOVUN.I<size> <Dd>, <Qm>. */
14454 inst
.operands
[2].present
= 0;
14455 inst
.instruction
= N_MNEM_vqmovun
;
14460 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14461 _("immediate out of range"));
14462 /* FIXME: The manual is kind of unclear about what value U should have in
14463 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14465 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14469 do_neon_movn (void)
14471 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14472 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14473 NEON_ENCODE (INTEGER
, inst
);
14474 neon_two_same (0, 1, et
.size
/ 2);
14478 do_neon_rshift_narrow (void)
14480 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14481 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14482 int imm
= inst
.operands
[2].imm
;
14483 /* This gets the bounds check, size encoding and immediate bits calculation
14487 /* If immediate is zero then we are a pseudo-instruction for
14488 VMOVN.I<size> <Dd>, <Qm> */
14491 inst
.operands
[2].present
= 0;
14492 inst
.instruction
= N_MNEM_vmovn
;
14497 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14498 _("immediate out of range for narrowing operation"));
14499 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14503 do_neon_shll (void)
14505 /* FIXME: Type checking when lengthening. */
14506 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14507 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14508 unsigned imm
= inst
.operands
[2].imm
;
14510 if (imm
== et
.size
)
14512 /* Maximum shift variant. */
14513 NEON_ENCODE (INTEGER
, inst
);
14514 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14515 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14516 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14517 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14518 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14520 neon_dp_fixup (&inst
);
14524 /* A more-specific type check for non-max versions. */
14525 et
= neon_check_type (2, NS_QDI
,
14526 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14527 NEON_ENCODE (IMMED
, inst
);
14528 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14532 /* Check the various types for the VCVT instruction, and return which version
14533 the current instruction is. */
14535 #define CVT_FLAVOUR_VAR \
14536 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14537 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14538 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14539 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14540 /* Half-precision conversions. */ \
14541 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14542 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14543 /* VFP instructions. */ \
14544 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14545 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14546 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14547 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14548 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14549 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14550 /* VFP instructions with bitshift. */ \
14551 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14552 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14553 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14554 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14555 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14556 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14557 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14558 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14560 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14561 neon_cvt_flavour_##C,
14563 /* The different types of conversions we can do. */
14564 enum neon_cvt_flavour
14567 neon_cvt_flavour_invalid
,
14568 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
14573 static enum neon_cvt_flavour
14574 get_neon_cvt_flavour (enum neon_shape rs
)
14576 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14577 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14578 if (et.type != NT_invtype) \
14580 inst.error = NULL; \
14581 return (neon_cvt_flavour_##C); \
14584 struct neon_type_el et
;
14585 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14586 || rs
== NS_FF
) ? N_VFP
: 0;
14587 /* The instruction versions which take an immediate take one register
14588 argument, which is extended to the width of the full register. Thus the
14589 "source" and "destination" registers must have the same width. Hack that
14590 here by making the size equal to the key (wider, in this case) operand. */
14591 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14595 return neon_cvt_flavour_invalid
;
14610 /* Neon-syntax VFP conversions. */
14613 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
14615 const char *opname
= 0;
14617 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14619 /* Conversions with immediate bitshift. */
14620 const char *enc
[] =
14622 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14628 if (flavour
< (int) ARRAY_SIZE (enc
))
14630 opname
= enc
[flavour
];
14631 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14632 _("operands 0 and 1 must be the same register"));
14633 inst
.operands
[1] = inst
.operands
[2];
14634 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14639 /* Conversions without bitshift. */
14640 const char *enc
[] =
14642 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14648 if (flavour
< (int) ARRAY_SIZE (enc
))
14649 opname
= enc
[flavour
];
14653 do_vfp_nsyn_opcode (opname
);
14657 do_vfp_nsyn_cvtz (void)
14659 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14660 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
14661 const char *enc
[] =
14663 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14669 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14670 do_vfp_nsyn_opcode (enc
[flavour
]);
14674 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
14675 enum neon_cvt_mode mode
)
14680 set_it_insn_type (OUTSIDE_IT_INSN
);
14684 case neon_cvt_flavour_s32_f64
:
14688 case neon_cvt_flavour_s32_f32
:
14692 case neon_cvt_flavour_u32_f64
:
14696 case neon_cvt_flavour_u32_f32
:
14701 first_error (_("invalid instruction shape"));
14707 case neon_cvt_mode_a
: rm
= 0; break;
14708 case neon_cvt_mode_n
: rm
= 1; break;
14709 case neon_cvt_mode_p
: rm
= 2; break;
14710 case neon_cvt_mode_m
: rm
= 3; break;
14711 default: first_error (_("invalid rounding mode")); return;
14714 NEON_ENCODE (FPV8
, inst
);
14715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14716 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
14717 inst
.instruction
|= sz
<< 8;
14718 inst
.instruction
|= op
<< 7;
14719 inst
.instruction
|= rm
<< 16;
14720 inst
.instruction
|= 0xf0000000;
14721 inst
.is_neon
= TRUE
;
14725 do_neon_cvt_1 (enum neon_cvt_mode mode
)
14727 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14728 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14729 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
14731 /* PR11109: Handle round-to-zero for VCVT conversions. */
14732 if (mode
== neon_cvt_mode_z
14733 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14734 && (flavour
== neon_cvt_flavour_s32_f32
14735 || flavour
== neon_cvt_flavour_u32_f32
14736 || flavour
== neon_cvt_flavour_s32_f64
14737 || flavour
== neon_cvt_flavour_u32_f64
)
14738 && (rs
== NS_FD
|| rs
== NS_FF
))
14740 do_vfp_nsyn_cvtz ();
14744 /* VFP rather than Neon conversions. */
14745 if (flavour
>= neon_cvt_flavour_first_fp
)
14747 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
14748 do_vfp_nsyn_cvt (rs
, flavour
);
14750 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
14761 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14763 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14766 /* Fixed-point conversion with #0 immediate is encoded as an
14767 integer conversion. */
14768 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14770 immbits
= 32 - inst
.operands
[2].imm
;
14771 NEON_ENCODE (IMMED
, inst
);
14772 if (flavour
!= neon_cvt_flavour_invalid
)
14773 inst
.instruction
|= enctab
[flavour
];
14774 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14775 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14776 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14777 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14778 inst
.instruction
|= neon_quad (rs
) << 6;
14779 inst
.instruction
|= 1 << 21;
14780 inst
.instruction
|= immbits
<< 16;
14782 neon_dp_fixup (&inst
);
14788 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
14790 NEON_ENCODE (FLOAT
, inst
);
14791 set_it_insn_type (OUTSIDE_IT_INSN
);
14793 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
14796 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14797 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14798 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14799 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14800 inst
.instruction
|= neon_quad (rs
) << 6;
14801 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
14802 inst
.instruction
|= mode
<< 8;
14804 inst
.instruction
|= 0xfc000000;
14806 inst
.instruction
|= 0xf0000000;
14812 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14814 NEON_ENCODE (INTEGER
, inst
);
14816 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14819 if (flavour
!= neon_cvt_flavour_invalid
)
14820 inst
.instruction
|= enctab
[flavour
];
14822 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14823 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14824 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14825 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14826 inst
.instruction
|= neon_quad (rs
) << 6;
14827 inst
.instruction
|= 2 << 18;
14829 neon_dp_fixup (&inst
);
14834 /* Half-precision conversions for Advanced SIMD -- neon. */
14839 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14841 as_bad (_("operand size must match register width"));
14846 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14848 as_bad (_("operand size must match register width"));
14853 inst
.instruction
= 0x3b60600;
14855 inst
.instruction
= 0x3b60700;
14857 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14858 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14859 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14860 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14861 neon_dp_fixup (&inst
);
14865 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14866 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
14867 do_vfp_nsyn_cvt (rs
, flavour
);
14869 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
14874 do_neon_cvtr (void)
14876 do_neon_cvt_1 (neon_cvt_mode_x
);
14882 do_neon_cvt_1 (neon_cvt_mode_z
);
14886 do_neon_cvta (void)
14888 do_neon_cvt_1 (neon_cvt_mode_a
);
14892 do_neon_cvtn (void)
14894 do_neon_cvt_1 (neon_cvt_mode_n
);
14898 do_neon_cvtp (void)
14900 do_neon_cvt_1 (neon_cvt_mode_p
);
14904 do_neon_cvtm (void)
14906 do_neon_cvt_1 (neon_cvt_mode_m
);
14910 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
14913 mark_feature_used (&fpu_vfp_ext_armv8
);
14915 encode_arm_vfp_reg (inst
.operands
[0].reg
,
14916 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
14917 encode_arm_vfp_reg (inst
.operands
[1].reg
,
14918 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
14919 inst
.instruction
|= to
? 0x10000 : 0;
14920 inst
.instruction
|= t
? 0x80 : 0;
14921 inst
.instruction
|= is_double
? 0x100 : 0;
14922 do_vfp_cond_or_thumb ();
14926 do_neon_cvttb_1 (bfd_boolean t
)
14928 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
14932 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
14935 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
14937 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
14940 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
14942 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
14945 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
14947 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
14950 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
14957 do_neon_cvtb (void)
14959 do_neon_cvttb_1 (FALSE
);
14964 do_neon_cvtt (void)
14966 do_neon_cvttb_1 (TRUE
);
14970 neon_move_immediate (void)
14972 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14973 struct neon_type_el et
= neon_check_type (2, rs
,
14974 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14975 unsigned immlo
, immhi
= 0, immbits
;
14976 int op
, cmode
, float_p
;
14978 constraint (et
.type
== NT_invtype
,
14979 _("operand size must be specified for immediate VMOV"));
14981 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14982 op
= (inst
.instruction
& (1 << 5)) != 0;
14984 immlo
= inst
.operands
[1].imm
;
14985 if (inst
.operands
[1].regisimm
)
14986 immhi
= inst
.operands
[1].reg
;
14988 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14989 _("immediate has bits set outside the operand size"));
14991 float_p
= inst
.operands
[1].immisfloat
;
14993 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14994 et
.size
, et
.type
)) == FAIL
)
14996 /* Invert relevant bits only. */
14997 neon_invert_size (&immlo
, &immhi
, et
.size
);
14998 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14999 with one or the other; those cases are caught by
15000 neon_cmode_for_move_imm. */
15002 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15003 &op
, et
.size
, et
.type
)) == FAIL
)
15005 first_error (_("immediate out of range"));
15010 inst
.instruction
&= ~(1 << 5);
15011 inst
.instruction
|= op
<< 5;
15013 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15014 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15015 inst
.instruction
|= neon_quad (rs
) << 6;
15016 inst
.instruction
|= cmode
<< 8;
15018 neon_write_immbits (immbits
);
15024 if (inst
.operands
[1].isreg
)
15026 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15028 NEON_ENCODE (INTEGER
, inst
);
15029 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15030 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15032 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15033 inst
.instruction
|= neon_quad (rs
) << 6;
15037 NEON_ENCODE (IMMED
, inst
);
15038 neon_move_immediate ();
15041 neon_dp_fixup (&inst
);
15044 /* Encode instructions of form:
15046 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15047 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15050 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15052 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15053 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15054 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15055 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15056 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15057 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15058 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15059 inst
.instruction
|= neon_logbits (size
) << 20;
15061 neon_dp_fixup (&inst
);
15065 do_neon_dyadic_long (void)
15067 /* FIXME: Type checking for lengthening op. */
15068 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15069 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15070 neon_mixed_length (et
, et
.size
);
15074 do_neon_abal (void)
15076 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15077 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15078 neon_mixed_length (et
, et
.size
);
15082 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15084 if (inst
.operands
[2].isscalar
)
15086 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15087 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15088 NEON_ENCODE (SCALAR
, inst
);
15089 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15093 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15094 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15095 NEON_ENCODE (INTEGER
, inst
);
15096 neon_mixed_length (et
, et
.size
);
15101 do_neon_mac_maybe_scalar_long (void)
15103 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15107 do_neon_dyadic_wide (void)
15109 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15110 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15111 neon_mixed_length (et
, et
.size
);
15115 do_neon_dyadic_narrow (void)
15117 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15118 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15119 /* Operand sign is unimportant, and the U bit is part of the opcode,
15120 so force the operand type to integer. */
15121 et
.type
= NT_integer
;
15122 neon_mixed_length (et
, et
.size
/ 2);
15126 do_neon_mul_sat_scalar_long (void)
15128 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15132 do_neon_vmull (void)
15134 if (inst
.operands
[2].isscalar
)
15135 do_neon_mac_maybe_scalar_long ();
15138 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15139 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15141 if (et
.type
== NT_poly
)
15142 NEON_ENCODE (POLY
, inst
);
15144 NEON_ENCODE (INTEGER
, inst
);
15146 /* For polynomial encoding the U bit must be zero, and the size must
15147 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15148 obviously, as 0b10). */
15151 /* Check we're on the correct architecture. */
15152 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15154 _("Instruction form not available on this architecture.");
15159 neon_mixed_length (et
, et
.size
);
15166 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15167 struct neon_type_el et
= neon_check_type (3, rs
,
15168 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15169 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15171 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15172 _("shift out of range"));
15173 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15174 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15175 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15176 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15177 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15178 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15179 inst
.instruction
|= neon_quad (rs
) << 6;
15180 inst
.instruction
|= imm
<< 8;
15182 neon_dp_fixup (&inst
);
15188 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15189 struct neon_type_el et
= neon_check_type (2, rs
,
15190 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15191 unsigned op
= (inst
.instruction
>> 7) & 3;
15192 /* N (width of reversed regions) is encoded as part of the bitmask. We
15193 extract it here to check the elements to be reversed are smaller.
15194 Otherwise we'd get a reserved instruction. */
15195 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15196 gas_assert (elsize
!= 0);
15197 constraint (et
.size
>= elsize
,
15198 _("elements must be smaller than reversal region"));
15199 neon_two_same (neon_quad (rs
), 1, et
.size
);
15205 if (inst
.operands
[1].isscalar
)
15207 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15208 struct neon_type_el et
= neon_check_type (2, rs
,
15209 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15210 unsigned sizebits
= et
.size
>> 3;
15211 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15212 int logsize
= neon_logbits (et
.size
);
15213 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15215 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15218 NEON_ENCODE (SCALAR
, inst
);
15219 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15220 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15221 inst
.instruction
|= LOW4 (dm
);
15222 inst
.instruction
|= HI1 (dm
) << 5;
15223 inst
.instruction
|= neon_quad (rs
) << 6;
15224 inst
.instruction
|= x
<< 17;
15225 inst
.instruction
|= sizebits
<< 16;
15227 neon_dp_fixup (&inst
);
15231 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15232 struct neon_type_el et
= neon_check_type (2, rs
,
15233 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15234 /* Duplicate ARM register to lanes of vector. */
15235 NEON_ENCODE (ARMREG
, inst
);
15238 case 8: inst
.instruction
|= 0x400000; break;
15239 case 16: inst
.instruction
|= 0x000020; break;
15240 case 32: inst
.instruction
|= 0x000000; break;
15243 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15244 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15245 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15246 inst
.instruction
|= neon_quad (rs
) << 21;
15247 /* The encoding for this instruction is identical for the ARM and Thumb
15248 variants, except for the condition field. */
15249 do_vfp_cond_or_thumb ();
15253 /* VMOV has particularly many variations. It can be one of:
15254 0. VMOV<c><q> <Qd>, <Qm>
15255 1. VMOV<c><q> <Dd>, <Dm>
15256 (Register operations, which are VORR with Rm = Rn.)
15257 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15258 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15260 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15261 (ARM register to scalar.)
15262 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15263 (Two ARM registers to vector.)
15264 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15265 (Scalar to ARM register.)
15266 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15267 (Vector to two ARM registers.)
15268 8. VMOV.F32 <Sd>, <Sm>
15269 9. VMOV.F64 <Dd>, <Dm>
15270 (VFP register moves.)
15271 10. VMOV.F32 <Sd>, #imm
15272 11. VMOV.F64 <Dd>, #imm
15273 (VFP float immediate load.)
15274 12. VMOV <Rd>, <Sm>
15275 (VFP single to ARM reg.)
15276 13. VMOV <Sd>, <Rm>
15277 (ARM reg to VFP single.)
15278 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15279 (Two ARM regs to two VFP singles.)
15280 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15281 (Two VFP singles to two ARM regs.)
15283 These cases can be disambiguated using neon_select_shape, except cases 1/9
15284 and 3/11 which depend on the operand type too.
15286 All the encoded bits are hardcoded by this function.
15288 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15289 Cases 5, 7 may be used with VFPv2 and above.
15291 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15292 can specify a type where it doesn't make sense to, and is ignored). */
15297 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15298 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15300 struct neon_type_el et
;
15301 const char *ldconst
= 0;
15305 case NS_DD
: /* case 1/9. */
15306 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15307 /* It is not an error here if no type is given. */
15309 if (et
.type
== NT_float
&& et
.size
== 64)
15311 do_vfp_nsyn_opcode ("fcpyd");
15314 /* fall through. */
15316 case NS_QQ
: /* case 0/1. */
15318 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15320 /* The architecture manual I have doesn't explicitly state which
15321 value the U bit should have for register->register moves, but
15322 the equivalent VORR instruction has U = 0, so do that. */
15323 inst
.instruction
= 0x0200110;
15324 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15325 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15326 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15327 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15328 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15329 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15330 inst
.instruction
|= neon_quad (rs
) << 6;
15332 neon_dp_fixup (&inst
);
15336 case NS_DI
: /* case 3/11. */
15337 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15339 if (et
.type
== NT_float
&& et
.size
== 64)
15341 /* case 11 (fconstd). */
15342 ldconst
= "fconstd";
15343 goto encode_fconstd
;
15345 /* fall through. */
15347 case NS_QI
: /* case 2/3. */
15348 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15350 inst
.instruction
= 0x0800010;
15351 neon_move_immediate ();
15352 neon_dp_fixup (&inst
);
15355 case NS_SR
: /* case 4. */
15357 unsigned bcdebits
= 0;
15359 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15360 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15362 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15363 logsize
= neon_logbits (et
.size
);
15365 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15367 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15368 && et
.size
!= 32, _(BAD_FPU
));
15369 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15370 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15374 case 8: bcdebits
= 0x8; break;
15375 case 16: bcdebits
= 0x1; break;
15376 case 32: bcdebits
= 0x0; break;
15380 bcdebits
|= x
<< logsize
;
15382 inst
.instruction
= 0xe000b10;
15383 do_vfp_cond_or_thumb ();
15384 inst
.instruction
|= LOW4 (dn
) << 16;
15385 inst
.instruction
|= HI1 (dn
) << 7;
15386 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15387 inst
.instruction
|= (bcdebits
& 3) << 5;
15388 inst
.instruction
|= (bcdebits
>> 2) << 21;
15392 case NS_DRR
: /* case 5 (fmdrr). */
15393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15396 inst
.instruction
= 0xc400b10;
15397 do_vfp_cond_or_thumb ();
15398 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15399 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15400 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15401 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15404 case NS_RS
: /* case 6. */
15407 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15408 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15409 unsigned abcdebits
= 0;
15411 et
= neon_check_type (2, NS_NULL
,
15412 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15413 logsize
= neon_logbits (et
.size
);
15415 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15417 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15418 && et
.size
!= 32, _(BAD_FPU
));
15419 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15420 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15424 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15425 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15426 case 32: abcdebits
= 0x00; break;
15430 abcdebits
|= x
<< logsize
;
15431 inst
.instruction
= 0xe100b10;
15432 do_vfp_cond_or_thumb ();
15433 inst
.instruction
|= LOW4 (dn
) << 16;
15434 inst
.instruction
|= HI1 (dn
) << 7;
15435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15436 inst
.instruction
|= (abcdebits
& 3) << 5;
15437 inst
.instruction
|= (abcdebits
>> 2) << 21;
15441 case NS_RRD
: /* case 7 (fmrrd). */
15442 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15445 inst
.instruction
= 0xc500b10;
15446 do_vfp_cond_or_thumb ();
15447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15448 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15449 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15450 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15453 case NS_FF
: /* case 8 (fcpys). */
15454 do_vfp_nsyn_opcode ("fcpys");
15457 case NS_FI
: /* case 10 (fconsts). */
15458 ldconst
= "fconsts";
15460 if (is_quarter_float (inst
.operands
[1].imm
))
15462 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15463 do_vfp_nsyn_opcode (ldconst
);
15466 first_error (_("immediate out of range"));
15469 case NS_RF
: /* case 12 (fmrs). */
15470 do_vfp_nsyn_opcode ("fmrs");
15473 case NS_FR
: /* case 13 (fmsr). */
15474 do_vfp_nsyn_opcode ("fmsr");
15477 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15478 (one of which is a list), but we have parsed four. Do some fiddling to
15479 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15481 case NS_RRFF
: /* case 14 (fmrrs). */
15482 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15483 _("VFP registers must be adjacent"));
15484 inst
.operands
[2].imm
= 2;
15485 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15486 do_vfp_nsyn_opcode ("fmrrs");
15489 case NS_FFRR
: /* case 15 (fmsrr). */
15490 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15491 _("VFP registers must be adjacent"));
15492 inst
.operands
[1] = inst
.operands
[2];
15493 inst
.operands
[2] = inst
.operands
[3];
15494 inst
.operands
[0].imm
= 2;
15495 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15496 do_vfp_nsyn_opcode ("fmsrr");
15505 do_neon_rshift_round_imm (void)
15507 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15508 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15509 int imm
= inst
.operands
[2].imm
;
15511 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15514 inst
.operands
[2].present
= 0;
15519 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15520 _("immediate out of range for shift"));
15521 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15526 do_neon_movl (void)
15528 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15529 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15530 unsigned sizebits
= et
.size
>> 3;
15531 inst
.instruction
|= sizebits
<< 19;
15532 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15538 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15539 struct neon_type_el et
= neon_check_type (2, rs
,
15540 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15541 NEON_ENCODE (INTEGER
, inst
);
15542 neon_two_same (neon_quad (rs
), 1, et
.size
);
15546 do_neon_zip_uzp (void)
15548 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15549 struct neon_type_el et
= neon_check_type (2, rs
,
15550 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15551 if (rs
== NS_DD
&& et
.size
== 32)
15553 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15554 inst
.instruction
= N_MNEM_vtrn
;
15558 neon_two_same (neon_quad (rs
), 1, et
.size
);
15562 do_neon_sat_abs_neg (void)
15564 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15565 struct neon_type_el et
= neon_check_type (2, rs
,
15566 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15567 neon_two_same (neon_quad (rs
), 1, et
.size
);
15571 do_neon_pair_long (void)
15573 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15574 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15575 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15576 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15577 neon_two_same (neon_quad (rs
), 1, et
.size
);
15581 do_neon_recip_est (void)
15583 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15584 struct neon_type_el et
= neon_check_type (2, rs
,
15585 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15586 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15587 neon_two_same (neon_quad (rs
), 1, et
.size
);
15593 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15594 struct neon_type_el et
= neon_check_type (2, rs
,
15595 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15596 neon_two_same (neon_quad (rs
), 1, et
.size
);
15602 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15603 struct neon_type_el et
= neon_check_type (2, rs
,
15604 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15605 neon_two_same (neon_quad (rs
), 1, et
.size
);
15611 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15612 struct neon_type_el et
= neon_check_type (2, rs
,
15613 N_EQK
| N_INT
, N_8
| N_KEY
);
15614 neon_two_same (neon_quad (rs
), 1, et
.size
);
15620 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15621 neon_two_same (neon_quad (rs
), 1, -1);
15625 do_neon_tbl_tbx (void)
15627 unsigned listlenbits
;
15628 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15630 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15632 first_error (_("bad list length for table lookup"));
15636 listlenbits
= inst
.operands
[1].imm
- 1;
15637 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15638 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15639 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15640 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15641 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15642 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15643 inst
.instruction
|= listlenbits
<< 8;
15645 neon_dp_fixup (&inst
);
15649 do_neon_ldm_stm (void)
15651 /* P, U and L bits are part of bitmask. */
15652 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15653 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15655 if (inst
.operands
[1].issingle
)
15657 do_vfp_nsyn_ldm_stm (is_dbmode
);
15661 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15662 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15664 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15665 _("register list must contain at least 1 and at most 16 "
15668 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15669 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15670 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15671 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15673 inst
.instruction
|= offsetbits
;
15675 do_vfp_cond_or_thumb ();
15679 do_neon_ldr_str (void)
15681 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15683 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15684 And is UNPREDICTABLE in thumb mode. */
15686 && inst
.operands
[1].reg
== REG_PC
15687 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15689 if (!thumb_mode
&& warn_on_deprecated
)
15690 as_warn (_("Use of PC here is deprecated"));
15692 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15695 if (inst
.operands
[0].issingle
)
15698 do_vfp_nsyn_opcode ("flds");
15700 do_vfp_nsyn_opcode ("fsts");
15705 do_vfp_nsyn_opcode ("fldd");
15707 do_vfp_nsyn_opcode ("fstd");
15711 /* "interleave" version also handles non-interleaving register VLD1/VST1
15715 do_neon_ld_st_interleave (void)
15717 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15718 N_8
| N_16
| N_32
| N_64
);
15719 unsigned alignbits
= 0;
15721 /* The bits in this table go:
15722 0: register stride of one (0) or two (1)
15723 1,2: register list length, minus one (1, 2, 3, 4).
15724 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15725 We use -1 for invalid entries. */
15726 const int typetable
[] =
15728 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15729 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15730 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15731 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15735 if (et
.type
== NT_invtype
)
15738 if (inst
.operands
[1].immisalign
)
15739 switch (inst
.operands
[1].imm
>> 8)
15741 case 64: alignbits
= 1; break;
15743 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15744 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15745 goto bad_alignment
;
15749 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15750 goto bad_alignment
;
15755 first_error (_("bad alignment"));
15759 inst
.instruction
|= alignbits
<< 4;
15760 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15762 /* Bits [4:6] of the immediate in a list specifier encode register stride
15763 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15764 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15765 up the right value for "type" in a table based on this value and the given
15766 list style, then stick it back. */
15767 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15768 | (((inst
.instruction
>> 8) & 3) << 3);
15770 typebits
= typetable
[idx
];
15772 constraint (typebits
== -1, _("bad list type for instruction"));
15774 inst
.instruction
&= ~0xf00;
15775 inst
.instruction
|= typebits
<< 8;
15778 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15779 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15780 otherwise. The variable arguments are a list of pairs of legal (size, align)
15781 values, terminated with -1. */
15784 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15787 int result
= FAIL
, thissize
, thisalign
;
15789 if (!inst
.operands
[1].immisalign
)
15795 va_start (ap
, do_align
);
15799 thissize
= va_arg (ap
, int);
15800 if (thissize
== -1)
15802 thisalign
= va_arg (ap
, int);
15804 if (size
== thissize
&& align
== thisalign
)
15807 while (result
!= SUCCESS
);
15811 if (result
== SUCCESS
)
15814 first_error (_("unsupported alignment for instruction"));
15820 do_neon_ld_st_lane (void)
15822 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15823 int align_good
, do_align
= 0;
15824 int logsize
= neon_logbits (et
.size
);
15825 int align
= inst
.operands
[1].imm
>> 8;
15826 int n
= (inst
.instruction
>> 8) & 3;
15827 int max_el
= 64 / et
.size
;
15829 if (et
.type
== NT_invtype
)
15832 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15833 _("bad list length"));
15834 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15835 _("scalar index out of range"));
15836 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15838 _("stride of 2 unavailable when element size is 8"));
15842 case 0: /* VLD1 / VST1. */
15843 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15845 if (align_good
== FAIL
)
15849 unsigned alignbits
= 0;
15852 case 16: alignbits
= 0x1; break;
15853 case 32: alignbits
= 0x3; break;
15856 inst
.instruction
|= alignbits
<< 4;
15860 case 1: /* VLD2 / VST2. */
15861 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15863 if (align_good
== FAIL
)
15866 inst
.instruction
|= 1 << 4;
15869 case 2: /* VLD3 / VST3. */
15870 constraint (inst
.operands
[1].immisalign
,
15871 _("can't use alignment with this instruction"));
15874 case 3: /* VLD4 / VST4. */
15875 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15876 16, 64, 32, 64, 32, 128, -1);
15877 if (align_good
== FAIL
)
15881 unsigned alignbits
= 0;
15884 case 8: alignbits
= 0x1; break;
15885 case 16: alignbits
= 0x1; break;
15886 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15889 inst
.instruction
|= alignbits
<< 4;
15896 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15897 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15898 inst
.instruction
|= 1 << (4 + logsize
);
15900 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15901 inst
.instruction
|= logsize
<< 10;
15904 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15907 do_neon_ld_dup (void)
15909 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15910 int align_good
, do_align
= 0;
15912 if (et
.type
== NT_invtype
)
15915 switch ((inst
.instruction
>> 8) & 3)
15917 case 0: /* VLD1. */
15918 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15919 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15920 &do_align
, 16, 16, 32, 32, -1);
15921 if (align_good
== FAIL
)
15923 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15926 case 2: inst
.instruction
|= 1 << 5; break;
15927 default: first_error (_("bad list length")); return;
15929 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15932 case 1: /* VLD2. */
15933 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15934 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15935 if (align_good
== FAIL
)
15937 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15938 _("bad list length"));
15939 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15940 inst
.instruction
|= 1 << 5;
15941 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15944 case 2: /* VLD3. */
15945 constraint (inst
.operands
[1].immisalign
,
15946 _("can't use alignment with this instruction"));
15947 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15948 _("bad list length"));
15949 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15950 inst
.instruction
|= 1 << 5;
15951 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15954 case 3: /* VLD4. */
15956 int align
= inst
.operands
[1].imm
>> 8;
15957 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15958 16, 64, 32, 64, 32, 128, -1);
15959 if (align_good
== FAIL
)
15961 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15962 _("bad list length"));
15963 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15964 inst
.instruction
|= 1 << 5;
15965 if (et
.size
== 32 && align
== 128)
15966 inst
.instruction
|= 0x3 << 6;
15968 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15975 inst
.instruction
|= do_align
<< 4;
15978 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15979 apart from bits [11:4]. */
15982 do_neon_ldx_stx (void)
15984 if (inst
.operands
[1].isreg
)
15985 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15987 switch (NEON_LANE (inst
.operands
[0].imm
))
15989 case NEON_INTERLEAVE_LANES
:
15990 NEON_ENCODE (INTERLV
, inst
);
15991 do_neon_ld_st_interleave ();
15994 case NEON_ALL_LANES
:
15995 NEON_ENCODE (DUP
, inst
);
16000 NEON_ENCODE (LANE
, inst
);
16001 do_neon_ld_st_lane ();
16004 /* L bit comes from bit mask. */
16005 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16006 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16007 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16009 if (inst
.operands
[1].postind
)
16011 int postreg
= inst
.operands
[1].imm
& 0xf;
16012 constraint (!inst
.operands
[1].immisreg
,
16013 _("post-index must be a register"));
16014 constraint (postreg
== 0xd || postreg
== 0xf,
16015 _("bad register for post-index"));
16016 inst
.instruction
|= postreg
;
16018 else if (inst
.operands
[1].writeback
)
16020 inst
.instruction
|= 0xd;
16023 inst
.instruction
|= 0xf;
16026 inst
.instruction
|= 0xf9000000;
16028 inst
.instruction
|= 0xf4000000;
16033 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16035 NEON_ENCODE (FPV8
, inst
);
16038 do_vfp_sp_dyadic ();
16040 do_vfp_dp_rd_rn_rm ();
16043 inst
.instruction
|= 0x100;
16045 inst
.instruction
|= 0xf0000000;
16051 set_it_insn_type (OUTSIDE_IT_INSN
);
16053 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16054 first_error (_("invalid instruction shape"));
16060 set_it_insn_type (OUTSIDE_IT_INSN
);
16062 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16065 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16068 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16072 do_vrint_1 (enum neon_cvt_mode mode
)
16074 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16075 struct neon_type_el et
;
16080 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16081 if (et
.type
!= NT_invtype
)
16083 /* VFP encodings. */
16084 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16085 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16086 set_it_insn_type (OUTSIDE_IT_INSN
);
16088 NEON_ENCODE (FPV8
, inst
);
16090 do_vfp_sp_monadic ();
16092 do_vfp_dp_rd_rm ();
16096 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16097 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16098 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16099 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16100 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16101 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16102 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16106 inst
.instruction
|= (rs
== NS_DD
) << 8;
16107 do_vfp_cond_or_thumb ();
16111 /* Neon encodings (or something broken...). */
16113 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16115 if (et
.type
== NT_invtype
)
16118 set_it_insn_type (OUTSIDE_IT_INSN
);
16119 NEON_ENCODE (FLOAT
, inst
);
16121 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16124 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16125 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16126 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16127 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16128 inst
.instruction
|= neon_quad (rs
) << 6;
16131 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16132 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16133 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16134 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16135 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16136 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16137 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16142 inst
.instruction
|= 0xfc000000;
16144 inst
.instruction
|= 0xf0000000;
16151 do_vrint_1 (neon_cvt_mode_x
);
16157 do_vrint_1 (neon_cvt_mode_z
);
16163 do_vrint_1 (neon_cvt_mode_r
);
16169 do_vrint_1 (neon_cvt_mode_a
);
16175 do_vrint_1 (neon_cvt_mode_n
);
16181 do_vrint_1 (neon_cvt_mode_p
);
16187 do_vrint_1 (neon_cvt_mode_m
);
16190 /* Crypto v1 instructions. */
16192 do_crypto_2op_1 (unsigned elttype
, int op
)
16194 set_it_insn_type (OUTSIDE_IT_INSN
);
16196 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16202 NEON_ENCODE (INTEGER
, inst
);
16203 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16204 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16205 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16206 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16208 inst
.instruction
|= op
<< 6;
16211 inst
.instruction
|= 0xfc000000;
16213 inst
.instruction
|= 0xf0000000;
16217 do_crypto_3op_1 (int u
, int op
)
16219 set_it_insn_type (OUTSIDE_IT_INSN
);
16221 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16222 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16227 NEON_ENCODE (INTEGER
, inst
);
16228 neon_three_same (1, u
, 8 << op
);
16234 do_crypto_2op_1 (N_8
, 0);
16240 do_crypto_2op_1 (N_8
, 1);
16246 do_crypto_2op_1 (N_8
, 2);
16252 do_crypto_2op_1 (N_8
, 3);
16258 do_crypto_3op_1 (0, 0);
16264 do_crypto_3op_1 (0, 1);
16270 do_crypto_3op_1 (0, 2);
16276 do_crypto_3op_1 (0, 3);
16282 do_crypto_3op_1 (1, 0);
16288 do_crypto_3op_1 (1, 1);
16292 do_sha256su1 (void)
16294 do_crypto_3op_1 (1, 2);
16300 do_crypto_2op_1 (N_32
, -1);
16306 do_crypto_2op_1 (N_32
, 0);
16310 do_sha256su0 (void)
16312 do_crypto_2op_1 (N_32
, 1);
16315 /* Overall per-instruction processing. */
16317 /* We need to be able to fix up arbitrary expressions in some statements.
16318 This is so that we can handle symbols that are an arbitrary distance from
16319 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16320 which returns part of an address in a form which will be valid for
16321 a data instruction. We do this by pushing the expression into a symbol
16322 in the expr_section, and creating a fix for that. */
16325 fix_new_arm (fragS
* frag
,
16339 /* Create an absolute valued symbol, so we have something to
16340 refer to in the object file. Unfortunately for us, gas's
16341 generic expression parsing will already have folded out
16342 any use of .set foo/.type foo %function that may have
16343 been used to set type information of the target location,
16344 that's being specified symbolically. We have to presume
16345 the user knows what they are doing. */
16349 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
16351 symbol
= symbol_find_or_make (name
);
16352 S_SET_SEGMENT (symbol
, absolute_section
);
16353 symbol_set_frag (symbol
, &zero_address_frag
);
16354 S_SET_VALUE (symbol
, exp
->X_add_number
);
16355 exp
->X_op
= O_symbol
;
16356 exp
->X_add_symbol
= symbol
;
16357 exp
->X_add_number
= 0;
16363 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
16364 (enum bfd_reloc_code_real
) reloc
);
16368 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
16369 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
16373 /* Mark whether the fix is to a THUMB instruction, or an ARM
16375 new_fix
->tc_fix_data
= thumb_mode
;
16378 /* Create a frg for an instruction requiring relaxation. */
16380 output_relax_insn (void)
16386 /* The size of the instruction is unknown, so tie the debug info to the
16387 start of the instruction. */
16388 dwarf2_emit_insn (0);
16390 switch (inst
.reloc
.exp
.X_op
)
16393 sym
= inst
.reloc
.exp
.X_add_symbol
;
16394 offset
= inst
.reloc
.exp
.X_add_number
;
16398 offset
= inst
.reloc
.exp
.X_add_number
;
16401 sym
= make_expr_symbol (&inst
.reloc
.exp
);
16405 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
16406 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
16407 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
16410 /* Write a 32-bit thumb instruction to buf. */
16412 put_thumb32_insn (char * buf
, unsigned long insn
)
16414 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
16415 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
16419 output_inst (const char * str
)
16425 as_bad ("%s -- `%s'", inst
.error
, str
);
16430 output_relax_insn ();
16433 if (inst
.size
== 0)
16436 to
= frag_more (inst
.size
);
16437 /* PR 9814: Record the thumb mode into the current frag so that we know
16438 what type of NOP padding to use, if necessary. We override any previous
16439 setting so that if the mode has changed then the NOPS that we use will
16440 match the encoding of the last instruction in the frag. */
16441 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
16443 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
16445 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
16446 put_thumb32_insn (to
, inst
.instruction
);
16448 else if (inst
.size
> INSN_SIZE
)
16450 gas_assert (inst
.size
== (2 * INSN_SIZE
));
16451 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
16452 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
16455 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
16457 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
16458 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
16459 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
16462 dwarf2_emit_insn (inst
.size
);
16466 output_it_inst (int cond
, int mask
, char * to
)
16468 unsigned long instruction
= 0xbf00;
16471 instruction
|= mask
;
16472 instruction
|= cond
<< 4;
16476 to
= frag_more (2);
16478 dwarf2_emit_insn (2);
16482 md_number_to_chars (to
, instruction
, 2);
16487 /* Tag values used in struct asm_opcode's tag field. */
16490 OT_unconditional
, /* Instruction cannot be conditionalized.
16491 The ARM condition field is still 0xE. */
16492 OT_unconditionalF
, /* Instruction cannot be conditionalized
16493 and carries 0xF in its ARM condition field. */
16494 OT_csuffix
, /* Instruction takes a conditional suffix. */
16495 OT_csuffixF
, /* Some forms of the instruction take a conditional
16496 suffix, others place 0xF where the condition field
16498 OT_cinfix3
, /* Instruction takes a conditional infix,
16499 beginning at character index 3. (In
16500 unified mode, it becomes a suffix.) */
16501 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
16502 tsts, cmps, cmns, and teqs. */
16503 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
16504 character index 3, even in unified mode. Used for
16505 legacy instructions where suffix and infix forms
16506 may be ambiguous. */
16507 OT_csuf_or_in3
, /* Instruction takes either a conditional
16508 suffix or an infix at character index 3. */
16509 OT_odd_infix_unc
, /* This is the unconditional variant of an
16510 instruction that takes a conditional infix
16511 at an unusual position. In unified mode,
16512 this variant will accept a suffix. */
16513 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
16514 are the conditional variants of instructions that
16515 take conditional infixes in unusual positions.
16516 The infix appears at character index
16517 (tag - OT_odd_infix_0). These are not accepted
16518 in unified mode. */
16521 /* Subroutine of md_assemble, responsible for looking up the primary
16522 opcode from the mnemonic the user wrote. STR points to the
16523 beginning of the mnemonic.
16525 This is not simply a hash table lookup, because of conditional
16526 variants. Most instructions have conditional variants, which are
16527 expressed with a _conditional affix_ to the mnemonic. If we were
16528 to encode each conditional variant as a literal string in the opcode
16529 table, it would have approximately 20,000 entries.
16531 Most mnemonics take this affix as a suffix, and in unified syntax,
16532 'most' is upgraded to 'all'. However, in the divided syntax, some
16533 instructions take the affix as an infix, notably the s-variants of
16534 the arithmetic instructions. Of those instructions, all but six
16535 have the infix appear after the third character of the mnemonic.
16537 Accordingly, the algorithm for looking up primary opcodes given
16540 1. Look up the identifier in the opcode table.
16541 If we find a match, go to step U.
16543 2. Look up the last two characters of the identifier in the
16544 conditions table. If we find a match, look up the first N-2
16545 characters of the identifier in the opcode table. If we
16546 find a match, go to step CE.
16548 3. Look up the fourth and fifth characters of the identifier in
16549 the conditions table. If we find a match, extract those
16550 characters from the identifier, and look up the remaining
16551 characters in the opcode table. If we find a match, go
16556 U. Examine the tag field of the opcode structure, in case this is
16557 one of the six instructions with its conditional infix in an
16558 unusual place. If it is, the tag tells us where to find the
16559 infix; look it up in the conditions table and set inst.cond
16560 accordingly. Otherwise, this is an unconditional instruction.
16561 Again set inst.cond accordingly. Return the opcode structure.
16563 CE. Examine the tag field to make sure this is an instruction that
16564 should receive a conditional suffix. If it is not, fail.
16565 Otherwise, set inst.cond from the suffix we already looked up,
16566 and return the opcode structure.
16568 CM. Examine the tag field to make sure this is an instruction that
16569 should receive a conditional infix after the third character.
16570 If it is not, fail. Otherwise, undo the edits to the current
16571 line of input and proceed as for case CE. */
16573 static const struct asm_opcode
*
16574 opcode_lookup (char **str
)
16578 const struct asm_opcode
*opcode
;
16579 const struct asm_cond
*cond
;
16582 /* Scan up to the end of the mnemonic, which must end in white space,
16583 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16584 for (base
= end
= *str
; *end
!= '\0'; end
++)
16585 if (*end
== ' ' || *end
== '.')
16591 /* Handle a possible width suffix and/or Neon type suffix. */
16596 /* The .w and .n suffixes are only valid if the unified syntax is in
16598 if (unified_syntax
&& end
[1] == 'w')
16600 else if (unified_syntax
&& end
[1] == 'n')
16605 inst
.vectype
.elems
= 0;
16607 *str
= end
+ offset
;
16609 if (end
[offset
] == '.')
16611 /* See if we have a Neon type suffix (possible in either unified or
16612 non-unified ARM syntax mode). */
16613 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
16616 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
16622 /* Look for unaffixed or special-case affixed mnemonic. */
16623 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16628 if (opcode
->tag
< OT_odd_infix_0
)
16630 inst
.cond
= COND_ALWAYS
;
16634 if (warn_on_deprecated
&& unified_syntax
)
16635 as_warn (_("conditional infixes are deprecated in unified syntax"));
16636 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
16637 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16640 inst
.cond
= cond
->value
;
16644 /* Cannot have a conditional suffix on a mnemonic of less than two
16646 if (end
- base
< 3)
16649 /* Look for suffixed mnemonic. */
16651 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16652 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16654 if (opcode
&& cond
)
16657 switch (opcode
->tag
)
16659 case OT_cinfix3_legacy
:
16660 /* Ignore conditional suffixes matched on infix only mnemonics. */
16664 case OT_cinfix3_deprecated
:
16665 case OT_odd_infix_unc
:
16666 if (!unified_syntax
)
16668 /* else fall through */
16672 case OT_csuf_or_in3
:
16673 inst
.cond
= cond
->value
;
16676 case OT_unconditional
:
16677 case OT_unconditionalF
:
16679 inst
.cond
= cond
->value
;
16682 /* Delayed diagnostic. */
16683 inst
.error
= BAD_COND
;
16684 inst
.cond
= COND_ALWAYS
;
16693 /* Cannot have a usual-position infix on a mnemonic of less than
16694 six characters (five would be a suffix). */
16695 if (end
- base
< 6)
16698 /* Look for infixed mnemonic in the usual position. */
16700 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16704 memcpy (save
, affix
, 2);
16705 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
16706 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16708 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
16709 memcpy (affix
, save
, 2);
16712 && (opcode
->tag
== OT_cinfix3
16713 || opcode
->tag
== OT_cinfix3_deprecated
16714 || opcode
->tag
== OT_csuf_or_in3
16715 || opcode
->tag
== OT_cinfix3_legacy
))
16718 if (warn_on_deprecated
&& unified_syntax
16719 && (opcode
->tag
== OT_cinfix3
16720 || opcode
->tag
== OT_cinfix3_deprecated
))
16721 as_warn (_("conditional infixes are deprecated in unified syntax"));
16723 inst
.cond
= cond
->value
;
16730 /* This function generates an initial IT instruction, leaving its block
16731 virtually open for the new instructions. Eventually,
16732 the mask will be updated by now_it_add_mask () each time
16733 a new instruction needs to be included in the IT block.
16734 Finally, the block is closed with close_automatic_it_block ().
16735 The block closure can be requested either from md_assemble (),
16736 a tencode (), or due to a label hook. */
16739 new_automatic_it_block (int cond
)
16741 now_it
.state
= AUTOMATIC_IT_BLOCK
;
16742 now_it
.mask
= 0x18;
16744 now_it
.block_length
= 1;
16745 mapping_state (MAP_THUMB
);
16746 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
16747 now_it
.warn_deprecated
= FALSE
;
16748 now_it
.insn_cond
= TRUE
;
16751 /* Close an automatic IT block.
16752 See comments in new_automatic_it_block (). */
16755 close_automatic_it_block (void)
16757 now_it
.mask
= 0x10;
16758 now_it
.block_length
= 0;
16761 /* Update the mask of the current automatically-generated IT
16762 instruction. See comments in new_automatic_it_block (). */
16765 now_it_add_mask (int cond
)
16767 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16768 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16769 | ((bitvalue) << (nbit)))
16770 const int resulting_bit
= (cond
& 1);
16772 now_it
.mask
&= 0xf;
16773 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
16775 (5 - now_it
.block_length
));
16776 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
16778 ((5 - now_it
.block_length
) - 1) );
16779 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
16782 #undef SET_BIT_VALUE
16785 /* The IT blocks handling machinery is accessed through the these functions:
16786 it_fsm_pre_encode () from md_assemble ()
16787 set_it_insn_type () optional, from the tencode functions
16788 set_it_insn_type_last () ditto
16789 in_it_block () ditto
16790 it_fsm_post_encode () from md_assemble ()
16791 force_automatic_it_block_close () from label habdling functions
16794 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16795 initializing the IT insn type with a generic initial value depending
16796 on the inst.condition.
16797 2) During the tencode function, two things may happen:
16798 a) The tencode function overrides the IT insn type by
16799 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16800 b) The tencode function queries the IT block state by
16801 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16803 Both set_it_insn_type and in_it_block run the internal FSM state
16804 handling function (handle_it_state), because: a) setting the IT insn
16805 type may incur in an invalid state (exiting the function),
16806 and b) querying the state requires the FSM to be updated.
16807 Specifically we want to avoid creating an IT block for conditional
16808 branches, so it_fsm_pre_encode is actually a guess and we can't
16809 determine whether an IT block is required until the tencode () routine
16810 has decided what type of instruction this actually it.
16811 Because of this, if set_it_insn_type and in_it_block have to be used,
16812 set_it_insn_type has to be called first.
16814 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16815 determines the insn IT type depending on the inst.cond code.
16816 When a tencode () routine encodes an instruction that can be
16817 either outside an IT block, or, in the case of being inside, has to be
16818 the last one, set_it_insn_type_last () will determine the proper
16819 IT instruction type based on the inst.cond code. Otherwise,
16820 set_it_insn_type can be called for overriding that logic or
16821 for covering other cases.
16823 Calling handle_it_state () may not transition the IT block state to
16824 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16825 still queried. Instead, if the FSM determines that the state should
16826 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16827 after the tencode () function: that's what it_fsm_post_encode () does.
16829 Since in_it_block () calls the state handling function to get an
16830 updated state, an error may occur (due to invalid insns combination).
16831 In that case, inst.error is set.
16832 Therefore, inst.error has to be checked after the execution of
16833 the tencode () routine.
16835 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16836 any pending state change (if any) that didn't take place in
16837 handle_it_state () as explained above. */
16840 it_fsm_pre_encode (void)
16842 if (inst
.cond
!= COND_ALWAYS
)
16843 inst
.it_insn_type
= INSIDE_IT_INSN
;
16845 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
16847 now_it
.state_handled
= 0;
16850 /* IT state FSM handling function. */
16853 handle_it_state (void)
16855 now_it
.state_handled
= 1;
16856 now_it
.insn_cond
= FALSE
;
16858 switch (now_it
.state
)
16860 case OUTSIDE_IT_BLOCK
:
16861 switch (inst
.it_insn_type
)
16863 case OUTSIDE_IT_INSN
:
16866 case INSIDE_IT_INSN
:
16867 case INSIDE_IT_LAST_INSN
:
16868 if (thumb_mode
== 0)
16871 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
16872 as_tsktsk (_("Warning: conditional outside an IT block"\
16877 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
16878 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
16880 /* Automatically generate the IT instruction. */
16881 new_automatic_it_block (inst
.cond
);
16882 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
16883 close_automatic_it_block ();
16887 inst
.error
= BAD_OUT_IT
;
16893 case IF_INSIDE_IT_LAST_INSN
:
16894 case NEUTRAL_IT_INSN
:
16898 now_it
.state
= MANUAL_IT_BLOCK
;
16899 now_it
.block_length
= 0;
16904 case AUTOMATIC_IT_BLOCK
:
16905 /* Three things may happen now:
16906 a) We should increment current it block size;
16907 b) We should close current it block (closing insn or 4 insns);
16908 c) We should close current it block and start a new one (due
16909 to incompatible conditions or
16910 4 insns-length block reached). */
16912 switch (inst
.it_insn_type
)
16914 case OUTSIDE_IT_INSN
:
16915 /* The closure of the block shall happen immediatelly,
16916 so any in_it_block () call reports the block as closed. */
16917 force_automatic_it_block_close ();
16920 case INSIDE_IT_INSN
:
16921 case INSIDE_IT_LAST_INSN
:
16922 case IF_INSIDE_IT_LAST_INSN
:
16923 now_it
.block_length
++;
16925 if (now_it
.block_length
> 4
16926 || !now_it_compatible (inst
.cond
))
16928 force_automatic_it_block_close ();
16929 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16930 new_automatic_it_block (inst
.cond
);
16934 now_it
.insn_cond
= TRUE
;
16935 now_it_add_mask (inst
.cond
);
16938 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16939 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16940 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16941 close_automatic_it_block ();
16944 case NEUTRAL_IT_INSN
:
16945 now_it
.block_length
++;
16946 now_it
.insn_cond
= TRUE
;
16948 if (now_it
.block_length
> 4)
16949 force_automatic_it_block_close ();
16951 now_it_add_mask (now_it
.cc
& 1);
16955 close_automatic_it_block ();
16956 now_it
.state
= MANUAL_IT_BLOCK
;
16961 case MANUAL_IT_BLOCK
:
16963 /* Check conditional suffixes. */
16964 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16967 now_it
.mask
&= 0x1f;
16968 is_last
= (now_it
.mask
== 0x10);
16969 now_it
.insn_cond
= TRUE
;
16971 switch (inst
.it_insn_type
)
16973 case OUTSIDE_IT_INSN
:
16974 inst
.error
= BAD_NOT_IT
;
16977 case INSIDE_IT_INSN
:
16978 if (cond
!= inst
.cond
)
16980 inst
.error
= BAD_IT_COND
;
16985 case INSIDE_IT_LAST_INSN
:
16986 case IF_INSIDE_IT_LAST_INSN
:
16987 if (cond
!= inst
.cond
)
16989 inst
.error
= BAD_IT_COND
;
16994 inst
.error
= BAD_BRANCH
;
16999 case NEUTRAL_IT_INSN
:
17000 /* The BKPT instruction is unconditional even in an IT block. */
17004 inst
.error
= BAD_IT_IT
;
17014 struct depr_insn_mask
17016 unsigned long pattern
;
17017 unsigned long mask
;
17018 const char* description
;
17021 /* List of 16-bit instruction patterns deprecated in an IT block in
17023 static const struct depr_insn_mask depr_it_insns
[] = {
17024 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17025 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17026 { 0xa000, 0xb800, N_("ADR") },
17027 { 0x4800, 0xf800, N_("Literal loads") },
17028 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17029 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17034 it_fsm_post_encode (void)
17038 if (!now_it
.state_handled
)
17039 handle_it_state ();
17041 if (now_it
.insn_cond
17042 && !now_it
.warn_deprecated
17043 && warn_on_deprecated
17044 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17046 if (inst
.instruction
>= 0x10000)
17048 as_warn (_("it blocks containing wide Thumb instructions are "
17049 "deprecated in ARMv8"));
17050 now_it
.warn_deprecated
= TRUE
;
17054 const struct depr_insn_mask
*p
= depr_it_insns
;
17056 while (p
->mask
!= 0)
17058 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17060 as_warn (_("it blocks containing 16-bit Thumb intsructions "
17061 "of the following class are deprecated in ARMv8: "
17062 "%s"), p
->description
);
17063 now_it
.warn_deprecated
= TRUE
;
17071 if (now_it
.block_length
> 1)
17073 as_warn (_("it blocks of more than one conditional instruction are "
17074 "deprecated in ARMv8"));
17075 now_it
.warn_deprecated
= TRUE
;
17079 is_last
= (now_it
.mask
== 0x10);
17082 now_it
.state
= OUTSIDE_IT_BLOCK
;
17088 force_automatic_it_block_close (void)
17090 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17092 close_automatic_it_block ();
17093 now_it
.state
= OUTSIDE_IT_BLOCK
;
17101 if (!now_it
.state_handled
)
17102 handle_it_state ();
17104 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17108 md_assemble (char *str
)
17111 const struct asm_opcode
* opcode
;
17113 /* Align the previous label if needed. */
17114 if (last_label_seen
!= NULL
)
17116 symbol_set_frag (last_label_seen
, frag_now
);
17117 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17118 S_SET_SEGMENT (last_label_seen
, now_seg
);
17121 memset (&inst
, '\0', sizeof (inst
));
17122 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17124 opcode
= opcode_lookup (&p
);
17127 /* It wasn't an instruction, but it might be a register alias of
17128 the form alias .req reg, or a Neon .dn/.qn directive. */
17129 if (! create_register_alias (str
, p
)
17130 && ! create_neon_reg_alias (str
, p
))
17131 as_bad (_("bad instruction `%s'"), str
);
17136 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17137 as_warn (_("s suffix on comparison instruction is deprecated"));
17139 /* The value which unconditional instructions should have in place of the
17140 condition field. */
17141 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17145 arm_feature_set variant
;
17147 variant
= cpu_variant
;
17148 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17149 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17150 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17151 /* Check that this instruction is supported for this CPU. */
17152 if (!opcode
->tvariant
17153 || (thumb_mode
== 1
17154 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17156 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17159 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17160 && opcode
->tencode
!= do_t_branch
)
17162 as_bad (_("Thumb does not support conditional execution"));
17166 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17168 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17169 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17170 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17172 /* Two things are addressed here.
17173 1) Implicit require narrow instructions on Thumb-1.
17174 This avoids relaxation accidentally introducing Thumb-2
17176 2) Reject wide instructions in non Thumb-2 cores. */
17177 if (inst
.size_req
== 0)
17179 else if (inst
.size_req
== 4)
17181 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17187 inst
.instruction
= opcode
->tvalue
;
17189 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17191 /* Prepare the it_insn_type for those encodings that don't set
17193 it_fsm_pre_encode ();
17195 opcode
->tencode ();
17197 it_fsm_post_encode ();
17200 if (!(inst
.error
|| inst
.relax
))
17202 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17203 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17204 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17206 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17211 /* Something has gone badly wrong if we try to relax a fixed size
17213 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17215 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17216 *opcode
->tvariant
);
17217 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17218 set those bits when Thumb-2 32-bit instructions are seen. ie.
17219 anything other than bl/blx and v6-M instructions.
17220 This is overly pessimistic for relaxable instructions. */
17221 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17223 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17224 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17225 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17228 check_neon_suffixes
;
17232 mapping_state (MAP_THUMB
);
17235 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17239 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17240 is_bx
= (opcode
->aencode
== do_bx
);
17242 /* Check that this instruction is supported for this CPU. */
17243 if (!(is_bx
&& fix_v4bx
)
17244 && !(opcode
->avariant
&&
17245 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17247 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17252 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17256 inst
.instruction
= opcode
->avalue
;
17257 if (opcode
->tag
== OT_unconditionalF
)
17258 inst
.instruction
|= 0xF << 28;
17260 inst
.instruction
|= inst
.cond
<< 28;
17261 inst
.size
= INSN_SIZE
;
17262 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17264 it_fsm_pre_encode ();
17265 opcode
->aencode ();
17266 it_fsm_post_encode ();
17268 /* Arm mode bx is marked as both v4T and v5 because it's still required
17269 on a hypothetical non-thumb v5 core. */
17271 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17273 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17274 *opcode
->avariant
);
17276 check_neon_suffixes
;
17280 mapping_state (MAP_ARM
);
17285 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17293 check_it_blocks_finished (void)
17298 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17299 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17300 == MANUAL_IT_BLOCK
)
17302 as_warn (_("section '%s' finished with an open IT block."),
17306 if (now_it
.state
== MANUAL_IT_BLOCK
)
17307 as_warn (_("file finished with an open IT block."));
17311 /* Various frobbings of labels and their addresses. */
17314 arm_start_line_hook (void)
17316 last_label_seen
= NULL
;
17320 arm_frob_label (symbolS
* sym
)
17322 last_label_seen
= sym
;
17324 ARM_SET_THUMB (sym
, thumb_mode
);
17326 #if defined OBJ_COFF || defined OBJ_ELF
17327 ARM_SET_INTERWORK (sym
, support_interwork
);
17330 force_automatic_it_block_close ();
17332 /* Note - do not allow local symbols (.Lxxx) to be labelled
17333 as Thumb functions. This is because these labels, whilst
17334 they exist inside Thumb code, are not the entry points for
17335 possible ARM->Thumb calls. Also, these labels can be used
17336 as part of a computed goto or switch statement. eg gcc
17337 can generate code that looks like this:
17339 ldr r2, [pc, .Laaa]
17349 The first instruction loads the address of the jump table.
17350 The second instruction converts a table index into a byte offset.
17351 The third instruction gets the jump address out of the table.
17352 The fourth instruction performs the jump.
17354 If the address stored at .Laaa is that of a symbol which has the
17355 Thumb_Func bit set, then the linker will arrange for this address
17356 to have the bottom bit set, which in turn would mean that the
17357 address computation performed by the third instruction would end
17358 up with the bottom bit set. Since the ARM is capable of unaligned
17359 word loads, the instruction would then load the incorrect address
17360 out of the jump table, and chaos would ensue. */
17361 if (label_is_thumb_function_name
17362 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
17363 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
17365 /* When the address of a Thumb function is taken the bottom
17366 bit of that address should be set. This will allow
17367 interworking between Arm and Thumb functions to work
17370 THUMB_SET_FUNC (sym
, 1);
17372 label_is_thumb_function_name
= FALSE
;
17375 dwarf2_emit_label (sym
);
17379 arm_data_in_code (void)
17381 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
17383 *input_line_pointer
= '/';
17384 input_line_pointer
+= 5;
17385 *input_line_pointer
= 0;
17393 arm_canonicalize_symbol_name (char * name
)
17397 if (thumb_mode
&& (len
= strlen (name
)) > 5
17398 && streq (name
+ len
- 5, "/data"))
17399 *(name
+ len
- 5) = 0;
17404 /* Table of all register names defined by default. The user can
17405 define additional names with .req. Note that all register names
17406 should appear in both upper and lowercase variants. Some registers
17407 also have mixed-case names. */
17409 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17410 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17411 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17412 #define REGSET(p,t) \
17413 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17414 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17415 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17416 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17417 #define REGSETH(p,t) \
17418 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17419 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17420 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17421 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17422 #define REGSET2(p,t) \
17423 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17424 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17425 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17426 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17427 #define SPLRBANK(base,bank,t) \
17428 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17429 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17430 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17431 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17432 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17433 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17435 static const struct reg_entry reg_names
[] =
17437 /* ARM integer registers. */
17438 REGSET(r
, RN
), REGSET(R
, RN
),
17440 /* ATPCS synonyms. */
17441 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
17442 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
17443 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
17445 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
17446 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
17447 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
17449 /* Well-known aliases. */
17450 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
17451 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
17453 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
17454 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
17456 /* Coprocessor numbers. */
17457 REGSET(p
, CP
), REGSET(P
, CP
),
17459 /* Coprocessor register numbers. The "cr" variants are for backward
17461 REGSET(c
, CN
), REGSET(C
, CN
),
17462 REGSET(cr
, CN
), REGSET(CR
, CN
),
17464 /* ARM banked registers. */
17465 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
17466 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
17467 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
17468 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
17469 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
17470 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
17471 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
17473 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
17474 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
17475 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
17476 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
17477 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
17478 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
17479 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
17480 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
17482 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
17483 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
17484 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
17485 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
17486 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
17487 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
17488 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
17489 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17490 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17492 /* FPA registers. */
17493 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
17494 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
17496 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
17497 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
17499 /* VFP SP registers. */
17500 REGSET(s
,VFS
), REGSET(S
,VFS
),
17501 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
17503 /* VFP DP Registers. */
17504 REGSET(d
,VFD
), REGSET(D
,VFD
),
17505 /* Extra Neon DP registers. */
17506 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
17508 /* Neon QP registers. */
17509 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
17511 /* VFP control registers. */
17512 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
17513 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
17514 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
17515 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
17516 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
17517 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
17519 /* Maverick DSP coprocessor registers. */
17520 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
17521 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
17523 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
17524 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
17525 REGDEF(dspsc
,0,DSPSC
),
17527 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
17528 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
17529 REGDEF(DSPSC
,0,DSPSC
),
17531 /* iWMMXt data registers - p0, c0-15. */
17532 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
17534 /* iWMMXt control registers - p1, c0-3. */
17535 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
17536 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
17537 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
17538 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
17540 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17541 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
17542 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
17543 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
17544 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
17546 /* XScale accumulator registers. */
17547 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
17553 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17554 within psr_required_here. */
17555 static const struct asm_psr psrs
[] =
17557 /* Backward compatibility notation. Note that "all" is no longer
17558 truly all possible PSR bits. */
17559 {"all", PSR_c
| PSR_f
},
17563 /* Individual flags. */
17569 /* Combinations of flags. */
17570 {"fs", PSR_f
| PSR_s
},
17571 {"fx", PSR_f
| PSR_x
},
17572 {"fc", PSR_f
| PSR_c
},
17573 {"sf", PSR_s
| PSR_f
},
17574 {"sx", PSR_s
| PSR_x
},
17575 {"sc", PSR_s
| PSR_c
},
17576 {"xf", PSR_x
| PSR_f
},
17577 {"xs", PSR_x
| PSR_s
},
17578 {"xc", PSR_x
| PSR_c
},
17579 {"cf", PSR_c
| PSR_f
},
17580 {"cs", PSR_c
| PSR_s
},
17581 {"cx", PSR_c
| PSR_x
},
17582 {"fsx", PSR_f
| PSR_s
| PSR_x
},
17583 {"fsc", PSR_f
| PSR_s
| PSR_c
},
17584 {"fxs", PSR_f
| PSR_x
| PSR_s
},
17585 {"fxc", PSR_f
| PSR_x
| PSR_c
},
17586 {"fcs", PSR_f
| PSR_c
| PSR_s
},
17587 {"fcx", PSR_f
| PSR_c
| PSR_x
},
17588 {"sfx", PSR_s
| PSR_f
| PSR_x
},
17589 {"sfc", PSR_s
| PSR_f
| PSR_c
},
17590 {"sxf", PSR_s
| PSR_x
| PSR_f
},
17591 {"sxc", PSR_s
| PSR_x
| PSR_c
},
17592 {"scf", PSR_s
| PSR_c
| PSR_f
},
17593 {"scx", PSR_s
| PSR_c
| PSR_x
},
17594 {"xfs", PSR_x
| PSR_f
| PSR_s
},
17595 {"xfc", PSR_x
| PSR_f
| PSR_c
},
17596 {"xsf", PSR_x
| PSR_s
| PSR_f
},
17597 {"xsc", PSR_x
| PSR_s
| PSR_c
},
17598 {"xcf", PSR_x
| PSR_c
| PSR_f
},
17599 {"xcs", PSR_x
| PSR_c
| PSR_s
},
17600 {"cfs", PSR_c
| PSR_f
| PSR_s
},
17601 {"cfx", PSR_c
| PSR_f
| PSR_x
},
17602 {"csf", PSR_c
| PSR_s
| PSR_f
},
17603 {"csx", PSR_c
| PSR_s
| PSR_x
},
17604 {"cxf", PSR_c
| PSR_x
| PSR_f
},
17605 {"cxs", PSR_c
| PSR_x
| PSR_s
},
17606 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
17607 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
17608 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
17609 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
17610 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
17611 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
17612 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
17613 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
17614 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
17615 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
17616 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
17617 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
17618 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
17619 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
17620 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
17621 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
17622 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
17623 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
17624 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
17625 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
17626 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
17627 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
17628 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
17629 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
17632 /* Table of V7M psr names. */
17633 static const struct asm_psr v7m_psrs
[] =
17635 {"apsr", 0 }, {"APSR", 0 },
17636 {"iapsr", 1 }, {"IAPSR", 1 },
17637 {"eapsr", 2 }, {"EAPSR", 2 },
17638 {"psr", 3 }, {"PSR", 3 },
17639 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17640 {"ipsr", 5 }, {"IPSR", 5 },
17641 {"epsr", 6 }, {"EPSR", 6 },
17642 {"iepsr", 7 }, {"IEPSR", 7 },
17643 {"msp", 8 }, {"MSP", 8 },
17644 {"psp", 9 }, {"PSP", 9 },
17645 {"primask", 16}, {"PRIMASK", 16},
17646 {"basepri", 17}, {"BASEPRI", 17},
17647 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17648 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17649 {"faultmask", 19}, {"FAULTMASK", 19},
17650 {"control", 20}, {"CONTROL", 20}
17653 /* Table of all shift-in-operand names. */
17654 static const struct asm_shift_name shift_names
[] =
17656 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
17657 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
17658 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
17659 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
17660 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
17661 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
17664 /* Table of all explicit relocation names. */
17666 static struct reloc_entry reloc_names
[] =
17668 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
17669 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
17670 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
17671 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
17672 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
17673 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
17674 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
17675 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
17676 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
17677 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
17678 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
17679 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
17680 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
17681 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
17682 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
17683 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
17684 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
17685 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
17689 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17690 static const struct asm_cond conds
[] =
17694 {"cs", 0x2}, {"hs", 0x2},
17695 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17709 #define UL_BARRIER(L,U,CODE,FEAT) \
17710 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17711 { U, CODE, ARM_FEATURE (FEAT, 0) }
17713 static struct asm_barrier_opt barrier_opt_names
[] =
17715 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
17716 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
17717 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
17718 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
17719 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
17720 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
17721 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
17722 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
17723 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
17724 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
17725 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
17726 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
17727 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
17728 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
17729 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
17730 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
17735 /* Table of ARM-format instructions. */
17737 /* Macros for gluing together operand strings. N.B. In all cases
17738 other than OPS0, the trailing OP_stop comes from default
17739 zero-initialization of the unspecified elements of the array. */
17740 #define OPS0() { OP_stop, }
17741 #define OPS1(a) { OP_##a, }
17742 #define OPS2(a,b) { OP_##a,OP_##b, }
17743 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17744 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17745 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17746 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17748 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17749 This is useful when mixing operands for ARM and THUMB, i.e. using the
17750 MIX_ARM_THUMB_OPERANDS macro.
17751 In order to use these macros, prefix the number of operands with _
17753 #define OPS_1(a) { a, }
17754 #define OPS_2(a,b) { a,b, }
17755 #define OPS_3(a,b,c) { a,b,c, }
17756 #define OPS_4(a,b,c,d) { a,b,c,d, }
17757 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17758 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17760 /* These macros abstract out the exact format of the mnemonic table and
17761 save some repeated characters. */
17763 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17764 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17765 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17766 THUMB_VARIANT, do_##ae, do_##te }
17768 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17769 a T_MNEM_xyz enumerator. */
17770 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17771 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17772 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17773 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17775 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17776 infix after the third character. */
17777 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17778 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17779 THUMB_VARIANT, do_##ae, do_##te }
17780 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17781 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17782 THUMB_VARIANT, do_##ae, do_##te }
17783 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17784 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17785 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17786 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17787 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17788 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17789 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17790 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17792 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17793 field is still 0xE. Many of the Thumb variants can be executed
17794 conditionally, so this is checked separately. */
17795 #define TUE(mnem, op, top, nops, ops, ae, te) \
17796 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17797 THUMB_VARIANT, do_##ae, do_##te }
17799 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17800 condition code field. */
17801 #define TUF(mnem, op, top, nops, ops, ae, te) \
17802 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17803 THUMB_VARIANT, do_##ae, do_##te }
17805 /* ARM-only variants of all the above. */
17806 #define CE(mnem, op, nops, ops, ae) \
17807 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17809 #define C3(mnem, op, nops, ops, ae) \
17810 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17812 /* Legacy mnemonics that always have conditional infix after the third
17814 #define CL(mnem, op, nops, ops, ae) \
17815 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17816 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17818 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17819 #define cCE(mnem, op, nops, ops, ae) \
17820 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17822 /* Legacy coprocessor instructions where conditional infix and conditional
17823 suffix are ambiguous. For consistency this includes all FPA instructions,
17824 not just the potentially ambiguous ones. */
17825 #define cCL(mnem, op, nops, ops, ae) \
17826 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17827 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17829 /* Coprocessor, takes either a suffix or a position-3 infix
17830 (for an FPA corner case). */
17831 #define C3E(mnem, op, nops, ops, ae) \
17832 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17833 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17835 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17836 { m1 #m2 m3, OPS##nops ops, \
17837 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17838 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17840 #define CM(m1, m2, op, nops, ops, ae) \
17841 xCM_ (m1, , m2, op, nops, ops, ae), \
17842 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17843 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17844 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17845 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17846 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17847 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17848 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17849 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17850 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17851 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17852 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17853 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17854 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17855 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17856 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17857 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17858 xCM_ (m1, le, m2, op, nops, ops, ae), \
17859 xCM_ (m1, al, m2, op, nops, ops, ae)
17861 #define UE(mnem, op, nops, ops, ae) \
17862 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17864 #define UF(mnem, op, nops, ops, ae) \
17865 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17867 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17868 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17869 use the same encoding function for each. */
17870 #define NUF(mnem, op, nops, ops, enc) \
17871 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17872 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17874 /* Neon data processing, version which indirects through neon_enc_tab for
17875 the various overloaded versions of opcodes. */
17876 #define nUF(mnem, op, nops, ops, enc) \
17877 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17878 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17880 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17882 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17883 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17884 THUMB_VARIANT, do_##enc, do_##enc }
17886 #define NCE(mnem, op, nops, ops, enc) \
17887 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17889 #define NCEF(mnem, op, nops, ops, enc) \
17890 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17892 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17893 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17894 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17895 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17897 #define nCE(mnem, op, nops, ops, enc) \
17898 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17900 #define nCEF(mnem, op, nops, ops, enc) \
17901 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17905 static const struct asm_opcode insns
[] =
17907 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17908 #define THUMB_VARIANT &arm_ext_v4t
17909 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17910 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17911 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17912 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17913 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17914 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17915 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17916 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17917 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17918 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17919 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17920 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17921 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17922 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17923 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17924 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17926 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17927 for setting PSR flag bits. They are obsolete in V6 and do not
17928 have Thumb equivalents. */
17929 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17930 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17931 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
17932 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17933 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17934 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
17935 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17936 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17937 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
17939 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17940 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17941 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17942 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17944 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
17945 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17946 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
17948 OP_ADDRGLDR
),ldst
, t_ldst
),
17949 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17951 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17952 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17953 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17954 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17955 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17956 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17958 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17959 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17960 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
17961 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17964 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17965 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17966 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17968 /* Thumb-compatibility pseudo ops. */
17969 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17970 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17971 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17972 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17973 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17974 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17975 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17976 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17977 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17978 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17979 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17980 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17982 /* These may simplify to neg. */
17983 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17984 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17986 #undef THUMB_VARIANT
17987 #define THUMB_VARIANT & arm_ext_v6
17989 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17991 /* V1 instructions with no Thumb analogue prior to V6T2. */
17992 #undef THUMB_VARIANT
17993 #define THUMB_VARIANT & arm_ext_v6t2
17995 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17996 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17997 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17999 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18000 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18001 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18002 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18004 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18005 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18007 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18008 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18010 /* V1 instructions with no Thumb analogue at all. */
18011 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18012 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18014 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18015 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18016 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18017 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18018 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18019 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18020 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18021 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18024 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18025 #undef THUMB_VARIANT
18026 #define THUMB_VARIANT & arm_ext_v4t
18028 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18029 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18031 #undef THUMB_VARIANT
18032 #define THUMB_VARIANT & arm_ext_v6t2
18034 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18035 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18037 /* Generic coprocessor instructions. */
18038 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18039 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18040 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18041 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18042 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18043 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18044 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18047 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18049 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18050 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18053 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18054 #undef THUMB_VARIANT
18055 #define THUMB_VARIANT & arm_ext_msr
18057 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18058 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18061 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18062 #undef THUMB_VARIANT
18063 #define THUMB_VARIANT & arm_ext_v6t2
18065 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18066 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18067 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18068 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18069 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18070 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18071 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18072 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18075 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18076 #undef THUMB_VARIANT
18077 #define THUMB_VARIANT & arm_ext_v4t
18079 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18080 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18081 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18082 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18083 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18084 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18087 #define ARM_VARIANT & arm_ext_v4t_5
18089 /* ARM Architecture 4T. */
18090 /* Note: bx (and blx) are required on V5, even if the processor does
18091 not support Thumb. */
18092 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18095 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18096 #undef THUMB_VARIANT
18097 #define THUMB_VARIANT & arm_ext_v5t
18099 /* Note: blx has 2 variants; the .value coded here is for
18100 BLX(2). Only this variant has conditional execution. */
18101 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18102 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18104 #undef THUMB_VARIANT
18105 #define THUMB_VARIANT & arm_ext_v6t2
18107 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18108 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18109 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18110 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18111 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18112 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18113 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18114 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18117 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18118 #undef THUMB_VARIANT
18119 #define THUMB_VARIANT &arm_ext_v5exp
18121 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18122 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18123 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18124 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18126 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18127 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18129 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18130 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18131 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18132 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18134 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18135 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18136 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18137 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18139 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18140 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18142 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18143 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18144 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18145 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18148 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18149 #undef THUMB_VARIANT
18150 #define THUMB_VARIANT &arm_ext_v6t2
18152 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18153 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18155 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18156 ADDRGLDRS
), ldrd
, t_ldstd
),
18158 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18159 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18162 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18164 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18167 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18168 #undef THUMB_VARIANT
18169 #define THUMB_VARIANT & arm_ext_v6
18171 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18172 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18173 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18174 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18175 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18176 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18177 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18178 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18179 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18180 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18182 #undef THUMB_VARIANT
18183 #define THUMB_VARIANT & arm_ext_v6t2
18185 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18186 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18188 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18189 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18191 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18192 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18194 /* ARM V6 not included in V7M. */
18195 #undef THUMB_VARIANT
18196 #define THUMB_VARIANT & arm_ext_v6_notm
18197 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18198 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18199 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18200 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18201 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18202 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18203 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18204 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18205 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18206 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18207 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18208 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18209 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18210 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18211 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18212 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18213 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18214 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18216 /* ARM V6 not included in V7M (eg. integer SIMD). */
18217 #undef THUMB_VARIANT
18218 #define THUMB_VARIANT & arm_ext_v6_dsp
18219 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18220 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18221 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18222 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18223 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18224 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18225 /* Old name for QASX. */
18226 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18227 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18228 /* Old name for QSAX. */
18229 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18230 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18231 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18232 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18233 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18234 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18235 /* Old name for SASX. */
18236 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18237 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18238 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18239 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18240 /* Old name for SHASX. */
18241 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18242 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18243 /* Old name for SHSAX. */
18244 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18245 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18246 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18247 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18248 /* Old name for SSAX. */
18249 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18250 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18251 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18252 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18253 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18254 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18255 /* Old name for UASX. */
18256 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18257 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18258 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18259 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18260 /* Old name for UHASX. */
18261 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18262 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18263 /* Old name for UHSAX. */
18264 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18265 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18266 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18267 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18268 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18269 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18270 /* Old name for UQASX. */
18271 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18272 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18273 /* Old name for UQSAX. */
18274 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18275 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18276 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18277 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18278 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18279 /* Old name for USAX. */
18280 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18281 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18282 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18283 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18284 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18285 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18286 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18287 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18288 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18289 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18290 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18291 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18292 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18293 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18294 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18295 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18296 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18297 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18298 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18299 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18300 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18301 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18302 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18303 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18304 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18305 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18306 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18307 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18308 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18309 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18310 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18311 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18312 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18313 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18316 #define ARM_VARIANT & arm_ext_v6k
18317 #undef THUMB_VARIANT
18318 #define THUMB_VARIANT & arm_ext_v6k
18320 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18321 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18322 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18323 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18325 #undef THUMB_VARIANT
18326 #define THUMB_VARIANT & arm_ext_v6_notm
18327 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
18329 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
18330 RRnpcb
), strexd
, t_strexd
),
18332 #undef THUMB_VARIANT
18333 #define THUMB_VARIANT & arm_ext_v6t2
18334 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
18336 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
18338 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18340 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18342 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
18345 #define ARM_VARIANT & arm_ext_sec
18346 #undef THUMB_VARIANT
18347 #define THUMB_VARIANT & arm_ext_sec
18349 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
18352 #define ARM_VARIANT & arm_ext_virt
18353 #undef THUMB_VARIANT
18354 #define THUMB_VARIANT & arm_ext_virt
18356 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
18357 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
18360 #define ARM_VARIANT & arm_ext_v6t2
18361 #undef THUMB_VARIANT
18362 #define THUMB_VARIANT & arm_ext_v6t2
18364 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
18365 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
18366 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18367 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18369 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18370 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18371 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18372 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
18374 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18375 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18376 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18377 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18379 /* Thumb-only instructions. */
18381 #define ARM_VARIANT NULL
18382 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
18383 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
18385 /* ARM does not really have an IT instruction, so always allow it.
18386 The opcode is copied from Thumb in order to allow warnings in
18387 -mimplicit-it=[never | arm] modes. */
18389 #define ARM_VARIANT & arm_ext_v1
18391 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
18392 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
18393 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
18394 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
18395 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
18396 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
18397 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
18398 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
18399 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
18400 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
18401 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
18402 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
18403 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
18404 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
18405 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
18406 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18407 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18408 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18410 /* Thumb2 only instructions. */
18412 #define ARM_VARIANT NULL
18414 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18415 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18416 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18417 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18418 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
18419 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
18421 /* Hardware division instructions. */
18423 #define ARM_VARIANT & arm_ext_adiv
18424 #undef THUMB_VARIANT
18425 #define THUMB_VARIANT & arm_ext_div
18427 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18428 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18430 /* ARM V6M/V7 instructions. */
18432 #define ARM_VARIANT & arm_ext_barrier
18433 #undef THUMB_VARIANT
18434 #define THUMB_VARIANT & arm_ext_barrier
18436 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
18437 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
18438 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
18440 /* ARM V7 instructions. */
18442 #define ARM_VARIANT & arm_ext_v7
18443 #undef THUMB_VARIANT
18444 #define THUMB_VARIANT & arm_ext_v7
18446 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
18447 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
18450 #define ARM_VARIANT & arm_ext_mp
18451 #undef THUMB_VARIANT
18452 #define THUMB_VARIANT & arm_ext_mp
18454 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
18456 /* AArchv8 instructions. */
18458 #define ARM_VARIANT & arm_ext_v8
18459 #undef THUMB_VARIANT
18460 #define THUMB_VARIANT & arm_ext_v8
18462 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
18463 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
18464 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18465 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
18467 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
18468 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18469 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18471 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
18473 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18475 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18477 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18478 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18479 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18480 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18481 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18482 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18484 /* ARMv8 T32 only. */
18486 #define ARM_VARIANT NULL
18487 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
18488 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
18489 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
18491 /* FP for ARMv8. */
18493 #define ARM_VARIANT & fpu_vfp_ext_armv8
18494 #undef THUMB_VARIANT
18495 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18497 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18498 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18499 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18500 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18501 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
18502 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
18503 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
18504 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
18505 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
18506 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
18507 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
18508 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
18509 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
18510 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
18511 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
18512 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
18513 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
18515 /* Crypto v1 extensions. */
18517 #define ARM_VARIANT & fpu_crypto_ext_armv8
18518 #undef THUMB_VARIANT
18519 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18521 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
18522 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
18523 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
18524 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
18525 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
18526 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
18527 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
18528 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
18529 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
18530 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
18531 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
18532 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
18533 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
18534 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
18537 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18538 #undef THUMB_VARIANT
18539 #define THUMB_VARIANT NULL
18541 cCE("wfs", e200110
, 1, (RR
), rd
),
18542 cCE("rfs", e300110
, 1, (RR
), rd
),
18543 cCE("wfc", e400110
, 1, (RR
), rd
),
18544 cCE("rfc", e500110
, 1, (RR
), rd
),
18546 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18547 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18548 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18549 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18551 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18552 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18553 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18554 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18556 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
18557 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
18558 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
18559 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
18560 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
18561 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
18562 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
18563 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
18564 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
18565 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
18566 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
18567 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
18569 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
18570 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
18571 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
18572 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
18573 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
18574 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
18575 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
18576 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
18577 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
18578 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
18579 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
18580 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
18582 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
18583 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
18584 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
18585 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
18586 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
18587 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
18588 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
18589 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
18590 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
18591 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
18592 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
18593 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
18595 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
18596 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
18597 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
18598 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
18599 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
18600 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
18601 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
18602 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
18603 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
18604 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
18605 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
18606 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
18608 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
18609 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
18610 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
18611 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
18612 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
18613 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
18614 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
18615 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
18616 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
18617 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
18618 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
18619 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
18621 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
18622 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
18623 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
18624 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
18625 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
18626 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
18627 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
18628 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
18629 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
18630 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
18631 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
18632 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
18634 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
18635 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
18636 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
18637 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
18638 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
18639 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
18640 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
18641 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
18642 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
18643 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
18644 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
18645 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
18647 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
18648 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
18649 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
18650 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
18651 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
18652 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
18653 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
18654 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
18655 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
18656 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
18657 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
18658 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
18660 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
18661 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
18662 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
18663 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
18664 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
18665 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
18666 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
18667 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
18668 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
18669 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
18670 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
18671 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
18673 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
18674 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
18675 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
18676 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
18677 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
18678 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
18679 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
18680 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
18681 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
18682 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
18683 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
18684 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
18686 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
18687 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
18688 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
18689 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
18690 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
18691 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
18692 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
18693 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
18694 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
18695 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
18696 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
18697 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
18699 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
18700 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
18701 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
18702 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
18703 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
18704 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
18705 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
18706 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
18707 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
18708 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
18709 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
18710 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
18712 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
18713 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
18714 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
18715 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
18716 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
18717 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
18718 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
18719 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
18720 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
18721 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
18722 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
18723 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
18725 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
18726 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
18727 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
18728 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
18729 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
18730 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
18731 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
18732 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
18733 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
18734 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
18735 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
18736 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
18738 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
18739 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
18740 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
18741 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
18742 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
18743 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
18744 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
18745 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
18746 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
18747 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
18748 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
18749 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
18751 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
18752 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
18753 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
18754 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
18755 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
18756 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
18757 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
18758 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
18759 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
18760 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
18761 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
18762 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
18764 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18765 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18766 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18767 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18768 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18769 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18770 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18771 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18772 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18773 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18774 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18775 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18777 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18778 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18779 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18780 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18781 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18782 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18783 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18784 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18785 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18786 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18787 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18788 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18790 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18791 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18792 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18793 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18794 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18795 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18796 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18797 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18798 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18799 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18800 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18801 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18803 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18804 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18805 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18806 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18807 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18808 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18809 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18810 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18811 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18812 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18813 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18814 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18816 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18817 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18818 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18819 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18820 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18821 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18822 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18823 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18824 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18825 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18826 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18827 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18829 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18830 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18831 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18832 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18833 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18834 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18835 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18836 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18837 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18838 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18839 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18840 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18842 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18843 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18844 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18845 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18846 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18847 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18848 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18849 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18850 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18851 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18852 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18853 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18855 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18856 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18857 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18858 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18859 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18860 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18861 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18862 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18863 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18864 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18865 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18866 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18868 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18869 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18870 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18871 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18872 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18873 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18874 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18875 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18876 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18877 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18878 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18879 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18881 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18882 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18883 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18884 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18885 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18886 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18887 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18888 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18889 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18890 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18891 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18892 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18894 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18895 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18896 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18897 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18898 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18899 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18900 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18901 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18902 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18903 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18904 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18905 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18907 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18908 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18909 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18910 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18911 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18912 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18913 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18914 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18915 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18916 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18917 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18918 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18920 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18921 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18922 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18923 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18924 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18925 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18926 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18927 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18928 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18929 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18930 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18931 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18933 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18934 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18935 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18936 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18938 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
18939 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
18940 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
18941 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
18942 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
18943 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
18944 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
18945 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
18946 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
18947 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
18948 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
18949 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
18951 /* The implementation of the FIX instruction is broken on some
18952 assemblers, in that it accepts a precision specifier as well as a
18953 rounding specifier, despite the fact that this is meaningless.
18954 To be more compatible, we accept it as well, though of course it
18955 does not set any bits. */
18956 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
18957 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
18958 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
18959 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
18960 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
18961 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
18962 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
18963 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
18964 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
18965 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
18966 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
18967 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
18968 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
18970 /* Instructions that were new with the real FPA, call them V2. */
18972 #define ARM_VARIANT & fpu_fpa_ext_v2
18974 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18975 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18976 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18977 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18978 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18979 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18982 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18984 /* Moves and type conversions. */
18985 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18986 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
18987 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
18988 cCE("fmstat", ef1fa10
, 0, (), noargs
),
18989 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
18990 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
18991 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18992 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18993 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18994 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18995 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18996 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18997 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
18998 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19000 /* Memory operations. */
19001 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19002 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19003 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19004 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19005 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19006 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19007 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19008 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19009 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19010 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19011 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19012 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19013 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19014 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19015 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19016 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19017 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19018 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19020 /* Monadic operations. */
19021 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19022 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19023 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19025 /* Dyadic operations. */
19026 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19027 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19028 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19029 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19030 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19031 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19032 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19033 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19034 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19037 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19038 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19039 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19040 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19042 /* Double precision load/store are still present on single precision
19043 implementations. */
19044 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19045 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19046 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19047 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19048 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19049 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19050 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19051 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19052 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19053 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19056 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19058 /* Moves and type conversions. */
19059 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19060 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19061 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19062 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19063 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19064 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19065 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19066 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19067 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19068 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19069 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19070 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19071 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19073 /* Monadic operations. */
19074 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19075 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19076 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19078 /* Dyadic operations. */
19079 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19080 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19081 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19082 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19083 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19084 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19085 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19086 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19087 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19090 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19091 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19092 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19093 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19096 #define ARM_VARIANT & fpu_vfp_ext_v2
19098 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19099 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19100 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19101 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19103 /* Instructions which may belong to either the Neon or VFP instruction sets.
19104 Individual encoder functions perform additional architecture checks. */
19106 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19107 #undef THUMB_VARIANT
19108 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19110 /* These mnemonics are unique to VFP. */
19111 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19112 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19113 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19114 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19115 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19116 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
19117 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
19118 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19119 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19120 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19122 /* Mnemonics shared by Neon and VFP. */
19123 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19124 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19125 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19127 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19128 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19130 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19131 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19133 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19134 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19135 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19136 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19137 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19138 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19139 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19140 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19142 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19143 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19144 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19145 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19148 /* NOTE: All VMOV encoding is special-cased! */
19149 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19150 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19152 #undef THUMB_VARIANT
19153 #define THUMB_VARIANT & fpu_neon_ext_v1
19155 #define ARM_VARIANT & fpu_neon_ext_v1
19157 /* Data processing with three registers of the same length. */
19158 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19159 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19160 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19161 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19162 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19163 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19164 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19165 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19166 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19167 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19168 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19169 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19170 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19171 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19172 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19173 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19174 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19175 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19176 /* If not immediate, fall back to neon_dyadic_i64_su.
19177 shl_imm should accept I8 I16 I32 I64,
19178 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19179 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19180 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19181 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19182 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19183 /* Logic ops, types optional & ignored. */
19184 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19185 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19186 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19187 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19188 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19189 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19190 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19191 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19192 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19193 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19194 /* Bitfield ops, untyped. */
19195 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19196 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19197 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19198 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19199 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19200 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19201 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19202 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19203 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19204 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19205 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19206 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19207 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19208 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19209 back to neon_dyadic_if_su. */
19210 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19211 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19212 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19213 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19214 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19215 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19216 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19217 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19218 /* Comparison. Type I8 I16 I32 F32. */
19219 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19220 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19221 /* As above, D registers only. */
19222 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19223 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19224 /* Int and float variants, signedness unimportant. */
19225 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19226 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19227 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19228 /* Add/sub take types I8 I16 I32 I64 F32. */
19229 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19230 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19231 /* vtst takes sizes 8, 16, 32. */
19232 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19233 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19234 /* VMUL takes I8 I16 I32 F32 P8. */
19235 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19236 /* VQD{R}MULH takes S16 S32. */
19237 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19238 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19239 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19240 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19241 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19242 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19243 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19244 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19245 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19246 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19247 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19248 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19249 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19250 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19251 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19252 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19254 /* Two address, int/float. Types S8 S16 S32 F32. */
19255 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19256 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19258 /* Data processing with two registers and a shift amount. */
19259 /* Right shifts, and variants with rounding.
19260 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19261 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19262 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19263 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19264 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19265 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19266 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19267 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19268 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19269 /* Shift and insert. Sizes accepted 8 16 32 64. */
19270 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19271 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19272 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19273 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19274 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19275 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19276 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19277 /* Right shift immediate, saturating & narrowing, with rounding variants.
19278 Types accepted S16 S32 S64 U16 U32 U64. */
19279 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19280 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19281 /* As above, unsigned. Types accepted S16 S32 S64. */
19282 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19283 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19284 /* Right shift narrowing. Types accepted I16 I32 I64. */
19285 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19286 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19287 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19288 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19289 /* CVT with optional immediate for fixed-point variant. */
19290 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19292 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19293 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19295 /* Data processing, three registers of different lengths. */
19296 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19297 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19298 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19299 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19300 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19301 /* If not scalar, fall back to neon_dyadic_long.
19302 Vector types as above, scalar types S16 S32 U16 U32. */
19303 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19304 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19305 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19306 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19307 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19308 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19309 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19310 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19311 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19312 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19313 /* Saturating doubling multiplies. Types S16 S32. */
19314 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19315 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19316 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19317 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19318 S16 S32 U16 U32. */
19319 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
19321 /* Extract. Size 8. */
19322 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
19323 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
19325 /* Two registers, miscellaneous. */
19326 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19327 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
19328 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
19329 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
19330 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
19331 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
19332 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
19333 /* Vector replicate. Sizes 8 16 32. */
19334 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
19335 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
19336 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19337 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
19338 /* VMOVN. Types I16 I32 I64. */
19339 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
19340 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19341 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
19342 /* VQMOVUN. Types S16 S32 S64. */
19343 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
19344 /* VZIP / VUZP. Sizes 8 16 32. */
19345 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19346 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19347 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19348 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19349 /* VQABS / VQNEG. Types S8 S16 S32. */
19350 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19351 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19352 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19353 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19354 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19355 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19356 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
19357 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19358 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
19359 /* Reciprocal estimates. Types U32 F32. */
19360 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19361 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
19362 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19363 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
19364 /* VCLS. Types S8 S16 S32. */
19365 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
19366 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
19367 /* VCLZ. Types I8 I16 I32. */
19368 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
19369 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
19370 /* VCNT. Size 8. */
19371 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
19372 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
19373 /* Two address, untyped. */
19374 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
19375 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
19376 /* VTRN. Sizes 8 16 32. */
19377 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
19378 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
19380 /* Table lookup. Size 8. */
19381 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19382 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19384 #undef THUMB_VARIANT
19385 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19387 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19389 /* Neon element/structure load/store. */
19390 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19391 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19392 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19393 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19394 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19395 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19396 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19397 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19399 #undef THUMB_VARIANT
19400 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
19402 #define ARM_VARIANT &fpu_vfp_ext_v3xd
19403 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
19404 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19405 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19406 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19407 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19408 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19409 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19410 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19411 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19413 #undef THUMB_VARIANT
19414 #define THUMB_VARIANT & fpu_vfp_ext_v3
19416 #define ARM_VARIANT & fpu_vfp_ext_v3
19418 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
19419 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19420 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19421 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19422 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19423 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19424 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19425 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19426 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19429 #define ARM_VARIANT &fpu_vfp_ext_fma
19430 #undef THUMB_VARIANT
19431 #define THUMB_VARIANT &fpu_vfp_ext_fma
19432 /* Mnemonics shared by Neon and VFP. These are included in the
19433 VFP FMA variant; NEON and VFP FMA always includes the NEON
19434 FMA instructions. */
19435 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19436 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19437 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19438 the v form should always be used. */
19439 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19440 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19441 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19442 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19443 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19444 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19446 #undef THUMB_VARIANT
19448 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19450 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19451 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19452 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19453 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19454 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19455 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19456 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
19457 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
19460 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19462 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
19463 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
19464 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
19465 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
19466 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
19467 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
19468 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
19469 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
19470 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
19471 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19472 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19473 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19474 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19475 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19476 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19477 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19478 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19479 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19480 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
19481 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
19482 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19483 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19484 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19485 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19486 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19487 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19488 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
19489 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
19490 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
19491 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
19492 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
19493 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
19494 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
19495 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
19496 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19497 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19498 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19499 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19500 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19501 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19502 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19503 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19504 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19505 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19506 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19507 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19508 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
19509 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19510 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19511 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19512 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19513 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19514 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19515 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19516 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19517 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19518 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19519 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19520 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19521 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19522 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19523 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19524 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19525 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19526 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19527 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19528 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19529 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19530 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19531 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19532 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19533 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19534 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19535 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19536 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19537 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19538 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19539 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19540 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19541 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19542 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19543 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19544 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19545 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19546 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19547 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19548 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19549 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19550 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
19551 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19552 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19553 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19554 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19555 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19556 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19557 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19558 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19559 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19560 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19561 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19562 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19563 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19564 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19565 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19566 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19567 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19568 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19569 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19570 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19571 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19572 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
19573 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19574 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19575 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19576 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19577 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19578 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19579 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19580 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19581 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19582 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19583 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19584 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19585 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19586 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19587 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19588 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19589 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19590 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19591 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19592 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19593 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19594 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19595 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19596 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19597 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19598 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19599 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19600 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19601 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19602 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19603 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19604 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19605 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19606 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19607 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19608 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19609 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19610 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19611 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19612 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19613 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19614 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19615 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19616 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19617 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19618 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19619 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19620 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19621 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19622 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19623 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
19626 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19628 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
19629 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
19630 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
19631 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19632 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19633 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19634 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19635 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19636 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19637 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19638 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19639 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19640 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19641 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19642 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19643 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19644 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19645 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19646 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19647 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19648 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
19649 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19650 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19651 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19652 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19653 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19654 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19655 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19656 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19657 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19658 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19659 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19660 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19661 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19662 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19663 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19664 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19665 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19666 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19667 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19668 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19669 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19670 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19671 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19672 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19673 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19674 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19675 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19676 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19677 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19678 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19679 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19680 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19681 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19682 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19683 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19684 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19687 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19689 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19690 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19691 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19692 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19693 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19694 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19695 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19696 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19697 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
19698 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
19699 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
19700 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
19701 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
19702 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
19703 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
19704 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
19705 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
19706 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
19707 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
19708 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
19709 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
19710 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
19711 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
19712 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
19713 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
19714 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
19715 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
19716 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
19717 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
19718 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
19719 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
19720 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
19721 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
19722 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
19723 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
19724 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
19725 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
19726 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
19727 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
19728 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
19729 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
19730 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
19731 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
19732 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
19733 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
19734 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
19735 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
19736 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
19737 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
19738 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
19739 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
19740 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
19741 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
19742 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
19743 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
19744 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
19745 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
19746 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
19747 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
19748 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
19749 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
19750 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
19751 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
19752 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
19753 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19754 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
19755 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19756 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
19757 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19758 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
19759 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19760 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
19761 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
19762 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
19763 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
19764 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
19767 #undef THUMB_VARIANT
19793 /* MD interface: bits in the object file. */
19795 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19796 for use in the a.out file, and stores them in the array pointed to by buf.
19797 This knows about the endian-ness of the target machine and does
19798 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19799 2 (short) and 4 (long) Floating numbers are put out as a series of
19800 LITTLENUMS (shorts, here at least). */
19803 md_number_to_chars (char * buf
, valueT val
, int n
)
19805 if (target_big_endian
)
19806 number_to_chars_bigendian (buf
, val
, n
);
19808 number_to_chars_littleendian (buf
, val
, n
);
19812 md_chars_to_number (char * buf
, int n
)
19815 unsigned char * where
= (unsigned char *) buf
;
19817 if (target_big_endian
)
19822 result
|= (*where
++ & 255);
19830 result
|= (where
[n
] & 255);
19837 /* MD interface: Sections. */
19839 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19840 that an rs_machine_dependent frag may reach. */
19843 arm_frag_max_var (fragS
*fragp
)
19845 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19846 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19848 Note that we generate relaxable instructions even for cases that don't
19849 really need it, like an immediate that's a trivial constant. So we're
19850 overestimating the instruction size for some of those cases. Rather
19851 than putting more intelligence here, it would probably be better to
19852 avoid generating a relaxation frag in the first place when it can be
19853 determined up front that a short instruction will suffice. */
19855 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
19859 /* Estimate the size of a frag before relaxing. Assume everything fits in
19863 md_estimate_size_before_relax (fragS
* fragp
,
19864 segT segtype ATTRIBUTE_UNUSED
)
19870 /* Convert a machine dependent frag. */
19873 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
19875 unsigned long insn
;
19876 unsigned long old_op
;
19884 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19886 old_op
= bfd_get_16(abfd
, buf
);
19887 if (fragp
->fr_symbol
)
19889 exp
.X_op
= O_symbol
;
19890 exp
.X_add_symbol
= fragp
->fr_symbol
;
19894 exp
.X_op
= O_constant
;
19896 exp
.X_add_number
= fragp
->fr_offset
;
19897 opcode
= fragp
->fr_subtype
;
19900 case T_MNEM_ldr_pc
:
19901 case T_MNEM_ldr_pc2
:
19902 case T_MNEM_ldr_sp
:
19903 case T_MNEM_str_sp
:
19910 if (fragp
->fr_var
== 4)
19912 insn
= THUMB_OP32 (opcode
);
19913 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
19915 insn
|= (old_op
& 0x700) << 4;
19919 insn
|= (old_op
& 7) << 12;
19920 insn
|= (old_op
& 0x38) << 13;
19922 insn
|= 0x00000c00;
19923 put_thumb32_insn (buf
, insn
);
19924 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
19928 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
19930 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
19933 if (fragp
->fr_var
== 4)
19935 insn
= THUMB_OP32 (opcode
);
19936 insn
|= (old_op
& 0xf0) << 4;
19937 put_thumb32_insn (buf
, insn
);
19938 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
19942 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19943 exp
.X_add_number
-= 4;
19951 if (fragp
->fr_var
== 4)
19953 int r0off
= (opcode
== T_MNEM_mov
19954 || opcode
== T_MNEM_movs
) ? 0 : 8;
19955 insn
= THUMB_OP32 (opcode
);
19956 insn
= (insn
& 0xe1ffffff) | 0x10000000;
19957 insn
|= (old_op
& 0x700) << r0off
;
19958 put_thumb32_insn (buf
, insn
);
19959 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19963 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
19968 if (fragp
->fr_var
== 4)
19970 insn
= THUMB_OP32(opcode
);
19971 put_thumb32_insn (buf
, insn
);
19972 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
19975 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
19979 if (fragp
->fr_var
== 4)
19981 insn
= THUMB_OP32(opcode
);
19982 insn
|= (old_op
& 0xf00) << 14;
19983 put_thumb32_insn (buf
, insn
);
19984 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
19987 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
19990 case T_MNEM_add_sp
:
19991 case T_MNEM_add_pc
:
19992 case T_MNEM_inc_sp
:
19993 case T_MNEM_dec_sp
:
19994 if (fragp
->fr_var
== 4)
19996 /* ??? Choose between add and addw. */
19997 insn
= THUMB_OP32 (opcode
);
19998 insn
|= (old_op
& 0xf0) << 4;
19999 put_thumb32_insn (buf
, insn
);
20000 if (opcode
== T_MNEM_add_pc
)
20001 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20003 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20006 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20014 if (fragp
->fr_var
== 4)
20016 insn
= THUMB_OP32 (opcode
);
20017 insn
|= (old_op
& 0xf0) << 4;
20018 insn
|= (old_op
& 0xf) << 16;
20019 put_thumb32_insn (buf
, insn
);
20020 if (insn
& (1 << 20))
20021 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20023 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20026 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20032 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20033 (enum bfd_reloc_code_real
) reloc_type
);
20034 fixp
->fx_file
= fragp
->fr_file
;
20035 fixp
->fx_line
= fragp
->fr_line
;
20036 fragp
->fr_fix
+= fragp
->fr_var
;
20039 /* Return the size of a relaxable immediate operand instruction.
20040 SHIFT and SIZE specify the form of the allowable immediate. */
20042 relax_immediate (fragS
*fragp
, int size
, int shift
)
20048 /* ??? Should be able to do better than this. */
20049 if (fragp
->fr_symbol
)
20052 low
= (1 << shift
) - 1;
20053 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20054 offset
= fragp
->fr_offset
;
20055 /* Force misaligned offsets to 32-bit variant. */
20058 if (offset
& ~mask
)
20063 /* Get the address of a symbol during relaxation. */
20065 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20071 sym
= fragp
->fr_symbol
;
20072 sym_frag
= symbol_get_frag (sym
);
20073 know (S_GET_SEGMENT (sym
) != absolute_section
20074 || sym_frag
== &zero_address_frag
);
20075 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20077 /* If frag has yet to be reached on this pass, assume it will
20078 move by STRETCH just as we did. If this is not so, it will
20079 be because some frag between grows, and that will force
20083 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20087 /* Adjust stretch for any alignment frag. Note that if have
20088 been expanding the earlier code, the symbol may be
20089 defined in what appears to be an earlier frag. FIXME:
20090 This doesn't handle the fr_subtype field, which specifies
20091 a maximum number of bytes to skip when doing an
20093 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20095 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20098 stretch
= - ((- stretch
)
20099 & ~ ((1 << (int) f
->fr_offset
) - 1));
20101 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20113 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20116 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20121 /* Assume worst case for symbols not known to be in the same section. */
20122 if (fragp
->fr_symbol
== NULL
20123 || !S_IS_DEFINED (fragp
->fr_symbol
)
20124 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20125 || S_IS_WEAK (fragp
->fr_symbol
))
20128 val
= relaxed_symbol_addr (fragp
, stretch
);
20129 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20130 addr
= (addr
+ 4) & ~3;
20131 /* Force misaligned targets to 32-bit variant. */
20135 if (val
< 0 || val
> 1020)
20140 /* Return the size of a relaxable add/sub immediate instruction. */
20142 relax_addsub (fragS
*fragp
, asection
*sec
)
20147 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20148 op
= bfd_get_16(sec
->owner
, buf
);
20149 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20150 return relax_immediate (fragp
, 8, 0);
20152 return relax_immediate (fragp
, 3, 0);
20156 /* Return the size of a relaxable branch instruction. BITS is the
20157 size of the offset field in the narrow instruction. */
20160 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20166 /* Assume worst case for symbols not known to be in the same section. */
20167 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20168 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20169 || S_IS_WEAK (fragp
->fr_symbol
))
20173 if (S_IS_DEFINED (fragp
->fr_symbol
)
20174 && ARM_IS_FUNC (fragp
->fr_symbol
))
20177 /* PR 12532. Global symbols with default visibility might
20178 be preempted, so do not relax relocations to them. */
20179 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
20180 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
20184 val
= relaxed_symbol_addr (fragp
, stretch
);
20185 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20188 /* Offset is a signed value *2 */
20190 if (val
>= limit
|| val
< -limit
)
20196 /* Relax a machine dependent frag. This returns the amount by which
20197 the current size of the frag should change. */
20200 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20205 oldsize
= fragp
->fr_var
;
20206 switch (fragp
->fr_subtype
)
20208 case T_MNEM_ldr_pc2
:
20209 newsize
= relax_adr (fragp
, sec
, stretch
);
20211 case T_MNEM_ldr_pc
:
20212 case T_MNEM_ldr_sp
:
20213 case T_MNEM_str_sp
:
20214 newsize
= relax_immediate (fragp
, 8, 2);
20218 newsize
= relax_immediate (fragp
, 5, 2);
20222 newsize
= relax_immediate (fragp
, 5, 1);
20226 newsize
= relax_immediate (fragp
, 5, 0);
20229 newsize
= relax_adr (fragp
, sec
, stretch
);
20235 newsize
= relax_immediate (fragp
, 8, 0);
20238 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20241 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20243 case T_MNEM_add_sp
:
20244 case T_MNEM_add_pc
:
20245 newsize
= relax_immediate (fragp
, 8, 2);
20247 case T_MNEM_inc_sp
:
20248 case T_MNEM_dec_sp
:
20249 newsize
= relax_immediate (fragp
, 7, 2);
20255 newsize
= relax_addsub (fragp
, sec
);
20261 fragp
->fr_var
= newsize
;
20262 /* Freeze wide instructions that are at or before the same location as
20263 in the previous pass. This avoids infinite loops.
20264 Don't freeze them unconditionally because targets may be artificially
20265 misaligned by the expansion of preceding frags. */
20266 if (stretch
<= 0 && newsize
> 2)
20268 md_convert_frag (sec
->owner
, sec
, fragp
);
20272 return newsize
- oldsize
;
20275 /* Round up a section size to the appropriate boundary. */
20278 md_section_align (segT segment ATTRIBUTE_UNUSED
,
20281 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20282 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
20284 /* For a.out, force the section size to be aligned. If we don't do
20285 this, BFD will align it for us, but it will not write out the
20286 final bytes of the section. This may be a bug in BFD, but it is
20287 easier to fix it here since that is how the other a.out targets
20291 align
= bfd_get_section_alignment (stdoutput
, segment
);
20292 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
20299 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20300 of an rs_align_code fragment. */
20303 arm_handle_align (fragS
* fragP
)
20305 static char const arm_noop
[2][2][4] =
20308 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20309 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20312 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20313 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20316 static char const thumb_noop
[2][2][2] =
20319 {0xc0, 0x46}, /* LE */
20320 {0x46, 0xc0}, /* BE */
20323 {0x00, 0xbf}, /* LE */
20324 {0xbf, 0x00} /* BE */
20327 static char const wide_thumb_noop
[2][4] =
20328 { /* Wide Thumb-2 */
20329 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20330 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20333 unsigned bytes
, fix
, noop_size
;
20336 const char *narrow_noop
= NULL
;
20341 if (fragP
->fr_type
!= rs_align_code
)
20344 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
20345 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
20348 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20349 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
20351 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
20353 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
20355 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
20357 narrow_noop
= thumb_noop
[1][target_big_endian
];
20358 noop
= wide_thumb_noop
[target_big_endian
];
20361 noop
= thumb_noop
[0][target_big_endian
];
20369 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
20370 [target_big_endian
];
20377 fragP
->fr_var
= noop_size
;
20379 if (bytes
& (noop_size
- 1))
20381 fix
= bytes
& (noop_size
- 1);
20383 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
20385 memset (p
, 0, fix
);
20392 if (bytes
& noop_size
)
20394 /* Insert a narrow noop. */
20395 memcpy (p
, narrow_noop
, noop_size
);
20397 bytes
-= noop_size
;
20401 /* Use wide noops for the remainder */
20405 while (bytes
>= noop_size
)
20407 memcpy (p
, noop
, noop_size
);
20409 bytes
-= noop_size
;
20413 fragP
->fr_fix
+= fix
;
20416 /* Called from md_do_align. Used to create an alignment
20417 frag in a code section. */
20420 arm_frag_align_code (int n
, int max
)
20424 /* We assume that there will never be a requirement
20425 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20426 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20431 _("alignments greater than %d bytes not supported in .text sections."),
20432 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
20433 as_fatal ("%s", err_msg
);
20436 p
= frag_var (rs_align_code
,
20437 MAX_MEM_FOR_RS_ALIGN_CODE
,
20439 (relax_substateT
) max
,
20446 /* Perform target specific initialisation of a frag.
20447 Note - despite the name this initialisation is not done when the frag
20448 is created, but only when its type is assigned. A frag can be created
20449 and used a long time before its type is set, so beware of assuming that
20450 this initialisationis performed first. */
20454 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
20456 /* Record whether this frag is in an ARM or a THUMB area. */
20457 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20460 #else /* OBJ_ELF is defined. */
20462 arm_init_frag (fragS
* fragP
, int max_chars
)
20464 /* If the current ARM vs THUMB mode has not already
20465 been recorded into this frag then do so now. */
20466 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
20468 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20470 /* Record a mapping symbol for alignment frags. We will delete this
20471 later if the alignment ends up empty. */
20472 switch (fragP
->fr_type
)
20475 case rs_align_test
:
20477 mapping_state_2 (MAP_DATA
, max_chars
);
20479 case rs_align_code
:
20480 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
20488 /* When we change sections we need to issue a new mapping symbol. */
20491 arm_elf_change_section (void)
20493 /* Link an unlinked unwind index table section to the .text section. */
20494 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
20495 && elf_linked_to_section (now_seg
) == NULL
)
20496 elf_linked_to_section (now_seg
) = text_section
;
20500 arm_elf_section_type (const char * str
, size_t len
)
20502 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
20503 return SHT_ARM_EXIDX
;
20508 /* Code to deal with unwinding tables. */
20510 static void add_unwind_adjustsp (offsetT
);
20512 /* Generate any deferred unwind frame offset. */
20515 flush_pending_unwind (void)
20519 offset
= unwind
.pending_offset
;
20520 unwind
.pending_offset
= 0;
20522 add_unwind_adjustsp (offset
);
20525 /* Add an opcode to this list for this function. Two-byte opcodes should
20526 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20530 add_unwind_opcode (valueT op
, int length
)
20532 /* Add any deferred stack adjustment. */
20533 if (unwind
.pending_offset
)
20534 flush_pending_unwind ();
20536 unwind
.sp_restored
= 0;
20538 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
20540 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
20541 if (unwind
.opcodes
)
20542 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
20543 unwind
.opcode_alloc
);
20545 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
20550 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
20552 unwind
.opcode_count
++;
20556 /* Add unwind opcodes to adjust the stack pointer. */
20559 add_unwind_adjustsp (offsetT offset
)
20563 if (offset
> 0x200)
20565 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20570 /* Long form: 0xb2, uleb128. */
20571 /* This might not fit in a word so add the individual bytes,
20572 remembering the list is built in reverse order. */
20573 o
= (valueT
) ((offset
- 0x204) >> 2);
20575 add_unwind_opcode (0, 1);
20577 /* Calculate the uleb128 encoding of the offset. */
20581 bytes
[n
] = o
& 0x7f;
20587 /* Add the insn. */
20589 add_unwind_opcode (bytes
[n
- 1], 1);
20590 add_unwind_opcode (0xb2, 1);
20592 else if (offset
> 0x100)
20594 /* Two short opcodes. */
20595 add_unwind_opcode (0x3f, 1);
20596 op
= (offset
- 0x104) >> 2;
20597 add_unwind_opcode (op
, 1);
20599 else if (offset
> 0)
20601 /* Short opcode. */
20602 op
= (offset
- 4) >> 2;
20603 add_unwind_opcode (op
, 1);
20605 else if (offset
< 0)
20608 while (offset
> 0x100)
20610 add_unwind_opcode (0x7f, 1);
20613 op
= ((offset
- 4) >> 2) | 0x40;
20614 add_unwind_opcode (op
, 1);
20618 /* Finish the list of unwind opcodes for this function. */
20620 finish_unwind_opcodes (void)
20624 if (unwind
.fp_used
)
20626 /* Adjust sp as necessary. */
20627 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
20628 flush_pending_unwind ();
20630 /* After restoring sp from the frame pointer. */
20631 op
= 0x90 | unwind
.fp_reg
;
20632 add_unwind_opcode (op
, 1);
20635 flush_pending_unwind ();
20639 /* Start an exception table entry. If idx is nonzero this is an index table
20643 start_unwind_section (const segT text_seg
, int idx
)
20645 const char * text_name
;
20646 const char * prefix
;
20647 const char * prefix_once
;
20648 const char * group_name
;
20652 size_t sec_name_len
;
20659 prefix
= ELF_STRING_ARM_unwind
;
20660 prefix_once
= ELF_STRING_ARM_unwind_once
;
20661 type
= SHT_ARM_EXIDX
;
20665 prefix
= ELF_STRING_ARM_unwind_info
;
20666 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
20667 type
= SHT_PROGBITS
;
20670 text_name
= segment_name (text_seg
);
20671 if (streq (text_name
, ".text"))
20674 if (strncmp (text_name
, ".gnu.linkonce.t.",
20675 strlen (".gnu.linkonce.t.")) == 0)
20677 prefix
= prefix_once
;
20678 text_name
+= strlen (".gnu.linkonce.t.");
20681 prefix_len
= strlen (prefix
);
20682 text_len
= strlen (text_name
);
20683 sec_name_len
= prefix_len
+ text_len
;
20684 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
20685 memcpy (sec_name
, prefix
, prefix_len
);
20686 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
20687 sec_name
[prefix_len
+ text_len
] = '\0';
20693 /* Handle COMDAT group. */
20694 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
20696 group_name
= elf_group_name (text_seg
);
20697 if (group_name
== NULL
)
20699 as_bad (_("Group section `%s' has no group signature"),
20700 segment_name (text_seg
));
20701 ignore_rest_of_line ();
20704 flags
|= SHF_GROUP
;
20708 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
20710 /* Set the section link for index tables. */
20712 elf_linked_to_section (now_seg
) = text_seg
;
20716 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20717 personality routine data. Returns zero, or the index table value for
20718 and inline entry. */
20721 create_unwind_entry (int have_data
)
20726 /* The current word of data. */
20728 /* The number of bytes left in this word. */
20731 finish_unwind_opcodes ();
20733 /* Remember the current text section. */
20734 unwind
.saved_seg
= now_seg
;
20735 unwind
.saved_subseg
= now_subseg
;
20737 start_unwind_section (now_seg
, 0);
20739 if (unwind
.personality_routine
== NULL
)
20741 if (unwind
.personality_index
== -2)
20744 as_bad (_("handlerdata in cantunwind frame"));
20745 return 1; /* EXIDX_CANTUNWIND. */
20748 /* Use a default personality routine if none is specified. */
20749 if (unwind
.personality_index
== -1)
20751 if (unwind
.opcode_count
> 3)
20752 unwind
.personality_index
= 1;
20754 unwind
.personality_index
= 0;
20757 /* Space for the personality routine entry. */
20758 if (unwind
.personality_index
== 0)
20760 if (unwind
.opcode_count
> 3)
20761 as_bad (_("too many unwind opcodes for personality routine 0"));
20765 /* All the data is inline in the index table. */
20768 while (unwind
.opcode_count
> 0)
20770 unwind
.opcode_count
--;
20771 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
20775 /* Pad with "finish" opcodes. */
20777 data
= (data
<< 8) | 0xb0;
20784 /* We get two opcodes "free" in the first word. */
20785 size
= unwind
.opcode_count
- 2;
20789 gas_assert (unwind
.personality_index
== -1);
20791 /* An extra byte is required for the opcode count. */
20792 size
= unwind
.opcode_count
+ 1;
20795 size
= (size
+ 3) >> 2;
20797 as_bad (_("too many unwind opcodes"));
20799 frag_align (2, 0, 0);
20800 record_alignment (now_seg
, 2);
20801 unwind
.table_entry
= expr_build_dot ();
20803 /* Allocate the table entry. */
20804 ptr
= frag_more ((size
<< 2) + 4);
20805 /* PR 13449: Zero the table entries in case some of them are not used. */
20806 memset (ptr
, 0, (size
<< 2) + 4);
20807 where
= frag_now_fix () - ((size
<< 2) + 4);
20809 switch (unwind
.personality_index
)
20812 /* ??? Should this be a PLT generating relocation? */
20813 /* Custom personality routine. */
20814 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
20815 BFD_RELOC_ARM_PREL31
);
20820 /* Set the first byte to the number of additional words. */
20821 data
= size
> 0 ? size
- 1 : 0;
20825 /* ABI defined personality routines. */
20827 /* Three opcodes bytes are packed into the first word. */
20834 /* The size and first two opcode bytes go in the first word. */
20835 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
20840 /* Should never happen. */
20844 /* Pack the opcodes into words (MSB first), reversing the list at the same
20846 while (unwind
.opcode_count
> 0)
20850 md_number_to_chars (ptr
, data
, 4);
20855 unwind
.opcode_count
--;
20857 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
20860 /* Finish off the last word. */
20863 /* Pad with "finish" opcodes. */
20865 data
= (data
<< 8) | 0xb0;
20867 md_number_to_chars (ptr
, data
, 4);
20872 /* Add an empty descriptor if there is no user-specified data. */
20873 ptr
= frag_more (4);
20874 md_number_to_chars (ptr
, 0, 4);
20881 /* Initialize the DWARF-2 unwind information for this procedure. */
20884 tc_arm_frame_initial_instructions (void)
20886 cfi_add_CFA_def_cfa (REG_SP
, 0);
20888 #endif /* OBJ_ELF */
20890 /* Convert REGNAME to a DWARF-2 register number. */
20893 tc_arm_regname_to_dw2regnum (char *regname
)
20895 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
20905 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
20909 exp
.X_op
= O_secrel
;
20910 exp
.X_add_symbol
= symbol
;
20911 exp
.X_add_number
= 0;
20912 emit_expr (&exp
, size
);
20916 /* MD interface: Symbol and relocation handling. */
20918 /* Return the address within the segment that a PC-relative fixup is
20919 relative to. For ARM, PC-relative fixups applied to instructions
20920 are generally relative to the location of the fixup plus 8 bytes.
20921 Thumb branches are offset by 4, and Thumb loads relative to PC
20922 require special handling. */
20925 md_pcrel_from_section (fixS
* fixP
, segT seg
)
20927 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20929 /* If this is pc-relative and we are going to emit a relocation
20930 then we just want to put out any pipeline compensation that the linker
20931 will need. Otherwise we want to use the calculated base.
20932 For WinCE we skip the bias for externals as well, since this
20933 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20935 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20936 || (arm_force_relocation (fixP
)
20938 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20944 switch (fixP
->fx_r_type
)
20946 /* PC relative addressing on the Thumb is slightly odd as the
20947 bottom two bits of the PC are forced to zero for the
20948 calculation. This happens *after* application of the
20949 pipeline offset. However, Thumb adrl already adjusts for
20950 this, so we need not do it again. */
20951 case BFD_RELOC_ARM_THUMB_ADD
:
20954 case BFD_RELOC_ARM_THUMB_OFFSET
:
20955 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20956 case BFD_RELOC_ARM_T32_ADD_PC12
:
20957 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20958 return (base
+ 4) & ~3;
20960 /* Thumb branches are simply offset by +4. */
20961 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20962 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20963 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20964 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20965 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20968 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20970 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20971 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20972 && ARM_IS_FUNC (fixP
->fx_addsy
)
20973 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20974 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20977 /* BLX is like branches above, but forces the low two bits of PC to
20979 case BFD_RELOC_THUMB_PCREL_BLX
:
20981 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20982 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20983 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20984 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20985 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20986 return (base
+ 4) & ~3;
20988 /* ARM mode branches are offset by +8. However, the Windows CE
20989 loader expects the relocation not to take this into account. */
20990 case BFD_RELOC_ARM_PCREL_BLX
:
20992 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20993 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20994 && ARM_IS_FUNC (fixP
->fx_addsy
)
20995 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20996 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20999 case BFD_RELOC_ARM_PCREL_CALL
:
21001 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21002 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21003 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21004 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21005 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21008 case BFD_RELOC_ARM_PCREL_BRANCH
:
21009 case BFD_RELOC_ARM_PCREL_JUMP
:
21010 case BFD_RELOC_ARM_PLT32
:
21012 /* When handling fixups immediately, because we have already
21013 discovered the value of a symbol, or the address of the frag involved
21014 we must account for the offset by +8, as the OS loader will never see the reloc.
21015 see fixup_segment() in write.c
21016 The S_IS_EXTERNAL test handles the case of global symbols.
21017 Those need the calculated base, not just the pipe compensation the linker will need. */
21019 && fixP
->fx_addsy
!= NULL
21020 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21021 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21029 /* ARM mode loads relative to PC are also offset by +8. Unlike
21030 branches, the Windows CE loader *does* expect the relocation
21031 to take this into account. */
21032 case BFD_RELOC_ARM_OFFSET_IMM
:
21033 case BFD_RELOC_ARM_OFFSET_IMM8
:
21034 case BFD_RELOC_ARM_HWLITERAL
:
21035 case BFD_RELOC_ARM_LITERAL
:
21036 case BFD_RELOC_ARM_CP_OFF_IMM
:
21040 /* Other PC-relative relocations are un-offset. */
21046 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21047 Otherwise we have no need to default values of symbols. */
21050 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21053 if (name
[0] == '_' && name
[1] == 'G'
21054 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21058 if (symbol_find (name
))
21059 as_bad (_("GOT already in the symbol table"));
21061 GOT_symbol
= symbol_new (name
, undefined_section
,
21062 (valueT
) 0, & zero_address_frag
);
21072 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21073 computed as two separate immediate values, added together. We
21074 already know that this value cannot be computed by just one ARM
21077 static unsigned int
21078 validate_immediate_twopart (unsigned int val
,
21079 unsigned int * highpart
)
21084 for (i
= 0; i
< 32; i
+= 2)
21085 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21091 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21093 else if (a
& 0xff0000)
21095 if (a
& 0xff000000)
21097 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21101 gas_assert (a
& 0xff000000);
21102 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21105 return (a
& 0xff) | (i
<< 7);
21112 validate_offset_imm (unsigned int val
, int hwse
)
21114 if ((hwse
&& val
> 255) || val
> 4095)
21119 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21120 negative immediate constant by altering the instruction. A bit of
21125 by inverting the second operand, and
21128 by negating the second operand. */
21131 negate_data_op (unsigned long * instruction
,
21132 unsigned long value
)
21135 unsigned long negated
, inverted
;
21137 negated
= encode_arm_immediate (-value
);
21138 inverted
= encode_arm_immediate (~value
);
21140 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21143 /* First negates. */
21144 case OPCODE_SUB
: /* ADD <-> SUB */
21145 new_inst
= OPCODE_ADD
;
21150 new_inst
= OPCODE_SUB
;
21154 case OPCODE_CMP
: /* CMP <-> CMN */
21155 new_inst
= OPCODE_CMN
;
21160 new_inst
= OPCODE_CMP
;
21164 /* Now Inverted ops. */
21165 case OPCODE_MOV
: /* MOV <-> MVN */
21166 new_inst
= OPCODE_MVN
;
21171 new_inst
= OPCODE_MOV
;
21175 case OPCODE_AND
: /* AND <-> BIC */
21176 new_inst
= OPCODE_BIC
;
21181 new_inst
= OPCODE_AND
;
21185 case OPCODE_ADC
: /* ADC <-> SBC */
21186 new_inst
= OPCODE_SBC
;
21191 new_inst
= OPCODE_ADC
;
21195 /* We cannot do anything. */
21200 if (value
== (unsigned) FAIL
)
21203 *instruction
&= OPCODE_MASK
;
21204 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21208 /* Like negate_data_op, but for Thumb-2. */
21210 static unsigned int
21211 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
21215 unsigned int negated
, inverted
;
21217 negated
= encode_thumb32_immediate (-value
);
21218 inverted
= encode_thumb32_immediate (~value
);
21220 rd
= (*instruction
>> 8) & 0xf;
21221 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
21224 /* ADD <-> SUB. Includes CMP <-> CMN. */
21225 case T2_OPCODE_SUB
:
21226 new_inst
= T2_OPCODE_ADD
;
21230 case T2_OPCODE_ADD
:
21231 new_inst
= T2_OPCODE_SUB
;
21235 /* ORR <-> ORN. Includes MOV <-> MVN. */
21236 case T2_OPCODE_ORR
:
21237 new_inst
= T2_OPCODE_ORN
;
21241 case T2_OPCODE_ORN
:
21242 new_inst
= T2_OPCODE_ORR
;
21246 /* AND <-> BIC. TST has no inverted equivalent. */
21247 case T2_OPCODE_AND
:
21248 new_inst
= T2_OPCODE_BIC
;
21255 case T2_OPCODE_BIC
:
21256 new_inst
= T2_OPCODE_AND
;
21261 case T2_OPCODE_ADC
:
21262 new_inst
= T2_OPCODE_SBC
;
21266 case T2_OPCODE_SBC
:
21267 new_inst
= T2_OPCODE_ADC
;
21271 /* We cannot do anything. */
21276 if (value
== (unsigned int)FAIL
)
21279 *instruction
&= T2_OPCODE_MASK
;
21280 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
21284 /* Read a 32-bit thumb instruction from buf. */
21285 static unsigned long
21286 get_thumb32_insn (char * buf
)
21288 unsigned long insn
;
21289 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
21290 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21296 /* We usually want to set the low bit on the address of thumb function
21297 symbols. In particular .word foo - . should have the low bit set.
21298 Generic code tries to fold the difference of two symbols to
21299 a constant. Prevent this and force a relocation when the first symbols
21300 is a thumb function. */
21303 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
21305 if (op
== O_subtract
21306 && l
->X_op
== O_symbol
21307 && r
->X_op
== O_symbol
21308 && THUMB_IS_FUNC (l
->X_add_symbol
))
21310 l
->X_op
= O_subtract
;
21311 l
->X_op_symbol
= r
->X_add_symbol
;
21312 l
->X_add_number
-= r
->X_add_number
;
21316 /* Process as normal. */
21320 /* Encode Thumb2 unconditional branches and calls. The encoding
21321 for the 2 are identical for the immediate values. */
21324 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
21326 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21329 addressT S
, I1
, I2
, lo
, hi
;
21331 S
= (value
>> 24) & 0x01;
21332 I1
= (value
>> 23) & 0x01;
21333 I2
= (value
>> 22) & 0x01;
21334 hi
= (value
>> 12) & 0x3ff;
21335 lo
= (value
>> 1) & 0x7ff;
21336 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21337 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21338 newval
|= (S
<< 10) | hi
;
21339 newval2
&= ~T2I1I2MASK
;
21340 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
21341 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21342 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21346 md_apply_fix (fixS
* fixP
,
21350 offsetT value
= * valP
;
21352 unsigned int newimm
;
21353 unsigned long temp
;
21355 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
21357 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
21359 /* Note whether this will delete the relocation. */
21361 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
21364 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21365 consistency with the behaviour on 32-bit hosts. Remember value
21367 value
&= 0xffffffff;
21368 value
^= 0x80000000;
21369 value
-= 0x80000000;
21372 fixP
->fx_addnumber
= value
;
21374 /* Same treatment for fixP->fx_offset. */
21375 fixP
->fx_offset
&= 0xffffffff;
21376 fixP
->fx_offset
^= 0x80000000;
21377 fixP
->fx_offset
-= 0x80000000;
21379 switch (fixP
->fx_r_type
)
21381 case BFD_RELOC_NONE
:
21382 /* This will need to go in the object file. */
21386 case BFD_RELOC_ARM_IMMEDIATE
:
21387 /* We claim that this fixup has been processed here,
21388 even if in fact we generate an error because we do
21389 not have a reloc for it, so tc_gen_reloc will reject it. */
21392 if (fixP
->fx_addsy
)
21394 const char *msg
= 0;
21396 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21397 msg
= _("undefined symbol %s used as an immediate value");
21398 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21399 msg
= _("symbol %s is in a different section");
21400 else if (S_IS_WEAK (fixP
->fx_addsy
))
21401 msg
= _("symbol %s is weak and may be overridden later");
21405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21406 msg
, S_GET_NAME (fixP
->fx_addsy
));
21411 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21413 /* If the offset is negative, we should use encoding A2 for ADR. */
21414 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
21415 newimm
= negate_data_op (&temp
, value
);
21418 newimm
= encode_arm_immediate (value
);
21420 /* If the instruction will fail, see if we can fix things up by
21421 changing the opcode. */
21422 if (newimm
== (unsigned int) FAIL
)
21423 newimm
= negate_data_op (&temp
, value
);
21426 if (newimm
== (unsigned int) FAIL
)
21428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21429 _("invalid constant (%lx) after fixup"),
21430 (unsigned long) value
);
21434 newimm
|= (temp
& 0xfffff000);
21435 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21438 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21440 unsigned int highpart
= 0;
21441 unsigned int newinsn
= 0xe1a00000; /* nop. */
21443 if (fixP
->fx_addsy
)
21445 const char *msg
= 0;
21447 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21448 msg
= _("undefined symbol %s used as an immediate value");
21449 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21450 msg
= _("symbol %s is in a different section");
21451 else if (S_IS_WEAK (fixP
->fx_addsy
))
21452 msg
= _("symbol %s is weak and may be overridden later");
21456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21457 msg
, S_GET_NAME (fixP
->fx_addsy
));
21462 newimm
= encode_arm_immediate (value
);
21463 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21465 /* If the instruction will fail, see if we can fix things up by
21466 changing the opcode. */
21467 if (newimm
== (unsigned int) FAIL
21468 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
21470 /* No ? OK - try using two ADD instructions to generate
21472 newimm
= validate_immediate_twopart (value
, & highpart
);
21474 /* Yes - then make sure that the second instruction is
21476 if (newimm
!= (unsigned int) FAIL
)
21478 /* Still No ? Try using a negated value. */
21479 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
21480 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
21481 /* Otherwise - give up. */
21484 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21485 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21490 /* Replace the first operand in the 2nd instruction (which
21491 is the PC) with the destination register. We have
21492 already added in the PC in the first instruction and we
21493 do not want to do it again. */
21494 newinsn
&= ~ 0xf0000;
21495 newinsn
|= ((newinsn
& 0x0f000) << 4);
21498 newimm
|= (temp
& 0xfffff000);
21499 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21501 highpart
|= (newinsn
& 0xfffff000);
21502 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
21506 case BFD_RELOC_ARM_OFFSET_IMM
:
21507 if (!fixP
->fx_done
&& seg
->use_rela_p
)
21510 case BFD_RELOC_ARM_LITERAL
:
21516 if (validate_offset_imm (value
, 0) == FAIL
)
21518 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
21519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21520 _("invalid literal constant: pool needs to be closer"));
21522 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21523 _("bad immediate value for offset (%ld)"),
21528 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21530 newval
&= 0xfffff000;
21533 newval
&= 0xff7ff000;
21534 newval
|= value
| (sign
? INDEX_UP
: 0);
21536 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21539 case BFD_RELOC_ARM_OFFSET_IMM8
:
21540 case BFD_RELOC_ARM_HWLITERAL
:
21546 if (validate_offset_imm (value
, 1) == FAIL
)
21548 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
21549 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21550 _("invalid literal constant: pool needs to be closer"));
21552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21553 _("bad immediate value for 8-bit offset (%ld)"),
21558 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21560 newval
&= 0xfffff0f0;
21563 newval
&= 0xff7ff0f0;
21564 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
21566 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21569 case BFD_RELOC_ARM_T32_OFFSET_U8
:
21570 if (value
< 0 || value
> 1020 || value
% 4 != 0)
21571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21572 _("bad immediate value for offset (%ld)"), (long) value
);
21575 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
21577 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
21580 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21581 /* This is a complicated relocation used for all varieties of Thumb32
21582 load/store instruction with immediate offset:
21584 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21585 *4, optional writeback(W)
21586 (doubleword load/store)
21588 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21589 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21590 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21591 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21592 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21594 Uppercase letters indicate bits that are already encoded at
21595 this point. Lowercase letters are our problem. For the
21596 second block of instructions, the secondary opcode nybble
21597 (bits 8..11) is present, and bit 23 is zero, even if this is
21598 a PC-relative operation. */
21599 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21601 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
21603 if ((newval
& 0xf0000000) == 0xe0000000)
21605 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21607 newval
|= (1 << 23);
21610 if (value
% 4 != 0)
21612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21613 _("offset not a multiple of 4"));
21619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21620 _("offset out of range"));
21625 else if ((newval
& 0x000f0000) == 0x000f0000)
21627 /* PC-relative, 12-bit offset. */
21629 newval
|= (1 << 23);
21634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21635 _("offset out of range"));
21640 else if ((newval
& 0x00000100) == 0x00000100)
21642 /* Writeback: 8-bit, +/- offset. */
21644 newval
|= (1 << 9);
21649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21650 _("offset out of range"));
21655 else if ((newval
& 0x00000f00) == 0x00000e00)
21657 /* T-instruction: positive 8-bit offset. */
21658 if (value
< 0 || value
> 0xff)
21660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21661 _("offset out of range"));
21669 /* Positive 12-bit or negative 8-bit offset. */
21673 newval
|= (1 << 23);
21683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21684 _("offset out of range"));
21691 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
21692 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
21695 case BFD_RELOC_ARM_SHIFT_IMM
:
21696 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21697 if (((unsigned long) value
) > 32
21699 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
21701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21702 _("shift expression is too large"));
21707 /* Shifts of zero must be done as lsl. */
21709 else if (value
== 32)
21711 newval
&= 0xfffff07f;
21712 newval
|= (value
& 0x1f) << 7;
21713 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21716 case BFD_RELOC_ARM_T32_IMMEDIATE
:
21717 case BFD_RELOC_ARM_T32_ADD_IMM
:
21718 case BFD_RELOC_ARM_T32_IMM12
:
21719 case BFD_RELOC_ARM_T32_ADD_PC12
:
21720 /* We claim that this fixup has been processed here,
21721 even if in fact we generate an error because we do
21722 not have a reloc for it, so tc_gen_reloc will reject it. */
21726 && ! S_IS_DEFINED (fixP
->fx_addsy
))
21728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21729 _("undefined symbol %s used as an immediate value"),
21730 S_GET_NAME (fixP
->fx_addsy
));
21734 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21736 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
21739 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21740 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
21742 newimm
= encode_thumb32_immediate (value
);
21743 if (newimm
== (unsigned int) FAIL
)
21744 newimm
= thumb32_negate_data_op (&newval
, value
);
21746 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
21747 && newimm
== (unsigned int) FAIL
)
21749 /* Turn add/sum into addw/subw. */
21750 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
21751 newval
= (newval
& 0xfeffffff) | 0x02000000;
21752 /* No flat 12-bit imm encoding for addsw/subsw. */
21753 if ((newval
& 0x00100000) == 0)
21755 /* 12 bit immediate for addw/subw. */
21759 newval
^= 0x00a00000;
21762 newimm
= (unsigned int) FAIL
;
21768 if (newimm
== (unsigned int)FAIL
)
21770 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21771 _("invalid constant (%lx) after fixup"),
21772 (unsigned long) value
);
21776 newval
|= (newimm
& 0x800) << 15;
21777 newval
|= (newimm
& 0x700) << 4;
21778 newval
|= (newimm
& 0x0ff);
21780 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
21781 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
21784 case BFD_RELOC_ARM_SMC
:
21785 if (((unsigned long) value
) > 0xffff)
21786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21787 _("invalid smc expression"));
21788 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21789 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
21790 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21793 case BFD_RELOC_ARM_HVC
:
21794 if (((unsigned long) value
) > 0xffff)
21795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21796 _("invalid hvc expression"));
21797 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21798 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
21799 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21802 case BFD_RELOC_ARM_SWI
:
21803 if (fixP
->tc_fix_data
!= 0)
21805 if (((unsigned long) value
) > 0xff)
21806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21807 _("invalid swi expression"));
21808 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21810 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21814 if (((unsigned long) value
) > 0x00ffffff)
21815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21816 _("invalid swi expression"));
21817 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21819 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21823 case BFD_RELOC_ARM_MULTI
:
21824 if (((unsigned long) value
) > 0xffff)
21825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21826 _("invalid expression in load/store multiple"));
21827 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
21828 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21832 case BFD_RELOC_ARM_PCREL_CALL
:
21834 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
21836 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21837 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21838 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21839 /* Flip the bl to blx. This is a simple flip
21840 bit here because we generate PCREL_CALL for
21841 unconditional bls. */
21843 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21844 newval
= newval
| 0x10000000;
21845 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21851 goto arm_branch_common
;
21853 case BFD_RELOC_ARM_PCREL_JUMP
:
21854 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
21856 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21857 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21858 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21860 /* This would map to a bl<cond>, b<cond>,
21861 b<always> to a Thumb function. We
21862 need to force a relocation for this particular
21864 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21868 case BFD_RELOC_ARM_PLT32
:
21870 case BFD_RELOC_ARM_PCREL_BRANCH
:
21872 goto arm_branch_common
;
21874 case BFD_RELOC_ARM_PCREL_BLX
:
21877 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
21879 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21880 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21881 && ARM_IS_FUNC (fixP
->fx_addsy
))
21883 /* Flip the blx to a bl and warn. */
21884 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21885 newval
= 0xeb000000;
21886 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21887 _("blx to '%s' an ARM ISA state function changed to bl"),
21889 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21895 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21896 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
21900 /* We are going to store value (shifted right by two) in the
21901 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21902 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21903 also be be clear. */
21905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21906 _("misaligned branch destination"));
21907 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
21908 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
21909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21911 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21913 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21914 newval
|= (value
>> 2) & 0x00ffffff;
21915 /* Set the H bit on BLX instructions. */
21919 newval
|= 0x01000000;
21921 newval
&= ~0x01000000;
21923 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21927 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
21928 /* CBZ can only branch forward. */
21930 /* Attempts to use CBZ to branch to the next instruction
21931 (which, strictly speaking, are prohibited) will be turned into
21934 FIXME: It may be better to remove the instruction completely and
21935 perform relaxation. */
21938 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21939 newval
= 0xbf00; /* NOP encoding T1 */
21940 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21947 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21949 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21950 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
21951 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21956 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
21957 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
21958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21960 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21962 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21963 newval
|= (value
& 0x1ff) >> 1;
21964 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21968 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
21969 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
21970 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
21972 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21974 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21975 newval
|= (value
& 0xfff) >> 1;
21976 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21980 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21982 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21983 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21984 && ARM_IS_FUNC (fixP
->fx_addsy
)
21985 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21987 /* Force a relocation for a branch 20 bits wide. */
21990 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
21991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21992 _("conditional branch out of range"));
21994 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21997 addressT S
, J1
, J2
, lo
, hi
;
21999 S
= (value
& 0x00100000) >> 20;
22000 J2
= (value
& 0x00080000) >> 19;
22001 J1
= (value
& 0x00040000) >> 18;
22002 hi
= (value
& 0x0003f000) >> 12;
22003 lo
= (value
& 0x00000ffe) >> 1;
22005 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22006 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22007 newval
|= (S
<< 10) | hi
;
22008 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22009 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22010 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22014 case BFD_RELOC_THUMB_PCREL_BLX
:
22015 /* If there is a blx from a thumb state function to
22016 another thumb function flip this to a bl and warn
22020 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22021 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22022 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22024 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22025 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22026 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22028 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22029 newval
= newval
| 0x1000;
22030 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22031 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22036 goto thumb_bl_common
;
22038 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22039 /* A bl from Thumb state ISA to an internal ARM state function
22040 is converted to a blx. */
22042 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22043 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22044 && ARM_IS_FUNC (fixP
->fx_addsy
)
22045 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22047 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22048 newval
= newval
& ~0x1000;
22049 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22050 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22056 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22057 /* For a BLX instruction, make sure that the relocation is rounded up
22058 to a word boundary. This follows the semantics of the instruction
22059 which specifies that bit 1 of the target address will come from bit
22060 1 of the base address. */
22061 value
= (value
+ 3) & ~ 3;
22064 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22065 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22066 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22069 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22071 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22073 else if ((value
& ~0x1ffffff)
22074 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22076 _("Thumb2 branch out of range"));
22079 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22080 encode_thumb2_b_bl_offset (buf
, value
);
22084 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22085 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22088 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22089 encode_thumb2_b_bl_offset (buf
, value
);
22094 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22095 md_number_to_chars (buf
, value
, 1);
22099 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22100 md_number_to_chars (buf
, value
, 2);
22104 case BFD_RELOC_ARM_TLS_CALL
:
22105 case BFD_RELOC_ARM_THM_TLS_CALL
:
22106 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22107 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22108 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22111 case BFD_RELOC_ARM_TLS_GOTDESC
:
22112 case BFD_RELOC_ARM_TLS_GD32
:
22113 case BFD_RELOC_ARM_TLS_LE32
:
22114 case BFD_RELOC_ARM_TLS_IE32
:
22115 case BFD_RELOC_ARM_TLS_LDM32
:
22116 case BFD_RELOC_ARM_TLS_LDO32
:
22117 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22120 case BFD_RELOC_ARM_GOT32
:
22121 case BFD_RELOC_ARM_GOTOFF
:
22122 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22123 md_number_to_chars (buf
, 0, 4);
22126 case BFD_RELOC_ARM_GOT_PREL
:
22127 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22128 md_number_to_chars (buf
, value
, 4);
22131 case BFD_RELOC_ARM_TARGET2
:
22132 /* TARGET2 is not partial-inplace, so we need to write the
22133 addend here for REL targets, because it won't be written out
22134 during reloc processing later. */
22135 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22136 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22140 case BFD_RELOC_RVA
:
22142 case BFD_RELOC_ARM_TARGET1
:
22143 case BFD_RELOC_ARM_ROSEGREL32
:
22144 case BFD_RELOC_ARM_SBREL32
:
22145 case BFD_RELOC_32_PCREL
:
22147 case BFD_RELOC_32_SECREL
:
22149 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22151 /* For WinCE we only do this for pcrel fixups. */
22152 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22154 md_number_to_chars (buf
, value
, 4);
22158 case BFD_RELOC_ARM_PREL31
:
22159 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22161 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22162 if ((value
^ (value
>> 1)) & 0x40000000)
22164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22165 _("rel31 relocation overflow"));
22167 newval
|= value
& 0x7fffffff;
22168 md_number_to_chars (buf
, newval
, 4);
22173 case BFD_RELOC_ARM_CP_OFF_IMM
:
22174 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22175 if (value
< -1023 || value
> 1023 || (value
& 3))
22176 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22177 _("co-processor offset out of range"));
22182 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22183 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22184 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22186 newval
= get_thumb32_insn (buf
);
22188 newval
&= 0xffffff00;
22191 newval
&= 0xff7fff00;
22192 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22194 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22195 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22196 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22198 put_thumb32_insn (buf
, newval
);
22201 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22202 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22203 if (value
< -255 || value
> 255)
22204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22205 _("co-processor offset out of range"));
22207 goto cp_off_common
;
22209 case BFD_RELOC_ARM_THUMB_OFFSET
:
22210 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22211 /* Exactly what ranges, and where the offset is inserted depends
22212 on the type of instruction, we can establish this from the
22214 switch (newval
>> 12)
22216 case 4: /* PC load. */
22217 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22218 forced to zero for these loads; md_pcrel_from has already
22219 compensated for this. */
22221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22222 _("invalid offset, target not word aligned (0x%08lX)"),
22223 (((unsigned long) fixP
->fx_frag
->fr_address
22224 + (unsigned long) fixP
->fx_where
) & ~3)
22225 + (unsigned long) value
);
22227 if (value
& ~0x3fc)
22228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22229 _("invalid offset, value too big (0x%08lX)"),
22232 newval
|= value
>> 2;
22235 case 9: /* SP load/store. */
22236 if (value
& ~0x3fc)
22237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22238 _("invalid offset, value too big (0x%08lX)"),
22240 newval
|= value
>> 2;
22243 case 6: /* Word load/store. */
22245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22246 _("invalid offset, value too big (0x%08lX)"),
22248 newval
|= value
<< 4; /* 6 - 2. */
22251 case 7: /* Byte load/store. */
22253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22254 _("invalid offset, value too big (0x%08lX)"),
22256 newval
|= value
<< 6;
22259 case 8: /* Halfword load/store. */
22261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22262 _("invalid offset, value too big (0x%08lX)"),
22264 newval
|= value
<< 5; /* 6 - 1. */
22268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22269 "Unable to process relocation for thumb opcode: %lx",
22270 (unsigned long) newval
);
22273 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22276 case BFD_RELOC_ARM_THUMB_ADD
:
22277 /* This is a complicated relocation, since we use it for all of
22278 the following immediate relocations:
22282 9bit ADD/SUB SP word-aligned
22283 10bit ADD PC/SP word-aligned
22285 The type of instruction being processed is encoded in the
22292 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22294 int rd
= (newval
>> 4) & 0xf;
22295 int rs
= newval
& 0xf;
22296 int subtract
= !!(newval
& 0x8000);
22298 /* Check for HI regs, only very restricted cases allowed:
22299 Adjusting SP, and using PC or SP to get an address. */
22300 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
22301 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
22302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22303 _("invalid Hi register with immediate"));
22305 /* If value is negative, choose the opposite instruction. */
22309 subtract
= !subtract
;
22311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22312 _("immediate value out of range"));
22317 if (value
& ~0x1fc)
22318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22319 _("invalid immediate for stack address calculation"));
22320 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
22321 newval
|= value
>> 2;
22323 else if (rs
== REG_PC
|| rs
== REG_SP
)
22325 if (subtract
|| value
& ~0x3fc)
22326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22327 _("invalid immediate for address calculation (value = 0x%08lX)"),
22328 (unsigned long) value
);
22329 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
22331 newval
|= value
>> 2;
22336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22337 _("immediate value out of range"));
22338 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
22339 newval
|= (rd
<< 8) | value
;
22344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22345 _("immediate value out of range"));
22346 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
22347 newval
|= rd
| (rs
<< 3) | (value
<< 6);
22350 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22353 case BFD_RELOC_ARM_THUMB_IMM
:
22354 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22355 if (value
< 0 || value
> 255)
22356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22357 _("invalid immediate: %ld is out of range"),
22360 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22363 case BFD_RELOC_ARM_THUMB_SHIFT
:
22364 /* 5bit shift value (0..32). LSL cannot take 32. */
22365 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
22366 temp
= newval
& 0xf800;
22367 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
22368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22369 _("invalid shift value: %ld"), (long) value
);
22370 /* Shifts of zero must be encoded as LSL. */
22372 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
22373 /* Shifts of 32 are encoded as zero. */
22374 else if (value
== 32)
22376 newval
|= value
<< 6;
22377 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22380 case BFD_RELOC_VTABLE_INHERIT
:
22381 case BFD_RELOC_VTABLE_ENTRY
:
22385 case BFD_RELOC_ARM_MOVW
:
22386 case BFD_RELOC_ARM_MOVT
:
22387 case BFD_RELOC_ARM_THUMB_MOVW
:
22388 case BFD_RELOC_ARM_THUMB_MOVT
:
22389 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22391 /* REL format relocations are limited to a 16-bit addend. */
22392 if (!fixP
->fx_done
)
22394 if (value
< -0x8000 || value
> 0x7fff)
22395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22396 _("offset out of range"));
22398 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22399 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22404 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22405 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22407 newval
= get_thumb32_insn (buf
);
22408 newval
&= 0xfbf08f00;
22409 newval
|= (value
& 0xf000) << 4;
22410 newval
|= (value
& 0x0800) << 15;
22411 newval
|= (value
& 0x0700) << 4;
22412 newval
|= (value
& 0x00ff);
22413 put_thumb32_insn (buf
, newval
);
22417 newval
= md_chars_to_number (buf
, 4);
22418 newval
&= 0xfff0f000;
22419 newval
|= value
& 0x0fff;
22420 newval
|= (value
& 0xf000) << 4;
22421 md_number_to_chars (buf
, newval
, 4);
22426 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
22427 case BFD_RELOC_ARM_ALU_PC_G0
:
22428 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
22429 case BFD_RELOC_ARM_ALU_PC_G1
:
22430 case BFD_RELOC_ARM_ALU_PC_G2
:
22431 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
22432 case BFD_RELOC_ARM_ALU_SB_G0
:
22433 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
22434 case BFD_RELOC_ARM_ALU_SB_G1
:
22435 case BFD_RELOC_ARM_ALU_SB_G2
:
22436 gas_assert (!fixP
->fx_done
);
22437 if (!seg
->use_rela_p
)
22440 bfd_vma encoded_addend
;
22441 bfd_vma addend_abs
= abs (value
);
22443 /* Check that the absolute value of the addend can be
22444 expressed as an 8-bit constant plus a rotation. */
22445 encoded_addend
= encode_arm_immediate (addend_abs
);
22446 if (encoded_addend
== (unsigned int) FAIL
)
22447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22448 _("the offset 0x%08lX is not representable"),
22449 (unsigned long) addend_abs
);
22451 /* Extract the instruction. */
22452 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22454 /* If the addend is positive, use an ADD instruction.
22455 Otherwise use a SUB. Take care not to destroy the S bit. */
22456 insn
&= 0xff1fffff;
22462 /* Place the encoded addend into the first 12 bits of the
22464 insn
&= 0xfffff000;
22465 insn
|= encoded_addend
;
22467 /* Update the instruction. */
22468 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22472 case BFD_RELOC_ARM_LDR_PC_G0
:
22473 case BFD_RELOC_ARM_LDR_PC_G1
:
22474 case BFD_RELOC_ARM_LDR_PC_G2
:
22475 case BFD_RELOC_ARM_LDR_SB_G0
:
22476 case BFD_RELOC_ARM_LDR_SB_G1
:
22477 case BFD_RELOC_ARM_LDR_SB_G2
:
22478 gas_assert (!fixP
->fx_done
);
22479 if (!seg
->use_rela_p
)
22482 bfd_vma addend_abs
= abs (value
);
22484 /* Check that the absolute value of the addend can be
22485 encoded in 12 bits. */
22486 if (addend_abs
>= 0x1000)
22487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22488 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22489 (unsigned long) addend_abs
);
22491 /* Extract the instruction. */
22492 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22494 /* If the addend is negative, clear bit 23 of the instruction.
22495 Otherwise set it. */
22497 insn
&= ~(1 << 23);
22501 /* Place the absolute value of the addend into the first 12 bits
22502 of the instruction. */
22503 insn
&= 0xfffff000;
22504 insn
|= addend_abs
;
22506 /* Update the instruction. */
22507 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22511 case BFD_RELOC_ARM_LDRS_PC_G0
:
22512 case BFD_RELOC_ARM_LDRS_PC_G1
:
22513 case BFD_RELOC_ARM_LDRS_PC_G2
:
22514 case BFD_RELOC_ARM_LDRS_SB_G0
:
22515 case BFD_RELOC_ARM_LDRS_SB_G1
:
22516 case BFD_RELOC_ARM_LDRS_SB_G2
:
22517 gas_assert (!fixP
->fx_done
);
22518 if (!seg
->use_rela_p
)
22521 bfd_vma addend_abs
= abs (value
);
22523 /* Check that the absolute value of the addend can be
22524 encoded in 8 bits. */
22525 if (addend_abs
>= 0x100)
22526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22527 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22528 (unsigned long) addend_abs
);
22530 /* Extract the instruction. */
22531 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22533 /* If the addend is negative, clear bit 23 of the instruction.
22534 Otherwise set it. */
22536 insn
&= ~(1 << 23);
22540 /* Place the first four bits of the absolute value of the addend
22541 into the first 4 bits of the instruction, and the remaining
22542 four into bits 8 .. 11. */
22543 insn
&= 0xfffff0f0;
22544 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
22546 /* Update the instruction. */
22547 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22551 case BFD_RELOC_ARM_LDC_PC_G0
:
22552 case BFD_RELOC_ARM_LDC_PC_G1
:
22553 case BFD_RELOC_ARM_LDC_PC_G2
:
22554 case BFD_RELOC_ARM_LDC_SB_G0
:
22555 case BFD_RELOC_ARM_LDC_SB_G1
:
22556 case BFD_RELOC_ARM_LDC_SB_G2
:
22557 gas_assert (!fixP
->fx_done
);
22558 if (!seg
->use_rela_p
)
22561 bfd_vma addend_abs
= abs (value
);
22563 /* Check that the absolute value of the addend is a multiple of
22564 four and, when divided by four, fits in 8 bits. */
22565 if (addend_abs
& 0x3)
22566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22567 _("bad offset 0x%08lX (must be word-aligned)"),
22568 (unsigned long) addend_abs
);
22570 if ((addend_abs
>> 2) > 0xff)
22571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22572 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22573 (unsigned long) addend_abs
);
22575 /* Extract the instruction. */
22576 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22578 /* If the addend is negative, clear bit 23 of the instruction.
22579 Otherwise set it. */
22581 insn
&= ~(1 << 23);
22585 /* Place the addend (divided by four) into the first eight
22586 bits of the instruction. */
22587 insn
&= 0xfffffff0;
22588 insn
|= addend_abs
>> 2;
22590 /* Update the instruction. */
22591 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22595 case BFD_RELOC_ARM_V4BX
:
22596 /* This will need to go in the object file. */
22600 case BFD_RELOC_UNUSED
:
22602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22603 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
22607 /* Translate internal representation of relocation info to BFD target
22611 tc_gen_reloc (asection
*section
, fixS
*fixp
)
22614 bfd_reloc_code_real_type code
;
22616 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
22618 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
22619 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
22620 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
22622 if (fixp
->fx_pcrel
)
22624 if (section
->use_rela_p
)
22625 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
22627 fixp
->fx_offset
= reloc
->address
;
22629 reloc
->addend
= fixp
->fx_offset
;
22631 switch (fixp
->fx_r_type
)
22634 if (fixp
->fx_pcrel
)
22636 code
= BFD_RELOC_8_PCREL
;
22641 if (fixp
->fx_pcrel
)
22643 code
= BFD_RELOC_16_PCREL
;
22648 if (fixp
->fx_pcrel
)
22650 code
= BFD_RELOC_32_PCREL
;
22654 case BFD_RELOC_ARM_MOVW
:
22655 if (fixp
->fx_pcrel
)
22657 code
= BFD_RELOC_ARM_MOVW_PCREL
;
22661 case BFD_RELOC_ARM_MOVT
:
22662 if (fixp
->fx_pcrel
)
22664 code
= BFD_RELOC_ARM_MOVT_PCREL
;
22668 case BFD_RELOC_ARM_THUMB_MOVW
:
22669 if (fixp
->fx_pcrel
)
22671 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
22675 case BFD_RELOC_ARM_THUMB_MOVT
:
22676 if (fixp
->fx_pcrel
)
22678 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
22682 case BFD_RELOC_NONE
:
22683 case BFD_RELOC_ARM_PCREL_BRANCH
:
22684 case BFD_RELOC_ARM_PCREL_BLX
:
22685 case BFD_RELOC_RVA
:
22686 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22687 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22688 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22689 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22690 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22691 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22692 case BFD_RELOC_VTABLE_ENTRY
:
22693 case BFD_RELOC_VTABLE_INHERIT
:
22695 case BFD_RELOC_32_SECREL
:
22697 code
= fixp
->fx_r_type
;
22700 case BFD_RELOC_THUMB_PCREL_BLX
:
22702 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22703 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22706 code
= BFD_RELOC_THUMB_PCREL_BLX
;
22709 case BFD_RELOC_ARM_LITERAL
:
22710 case BFD_RELOC_ARM_HWLITERAL
:
22711 /* If this is called then the a literal has
22712 been referenced across a section boundary. */
22713 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22714 _("literal referenced across section boundary"));
22718 case BFD_RELOC_ARM_TLS_CALL
:
22719 case BFD_RELOC_ARM_THM_TLS_CALL
:
22720 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22721 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22722 case BFD_RELOC_ARM_GOT32
:
22723 case BFD_RELOC_ARM_GOTOFF
:
22724 case BFD_RELOC_ARM_GOT_PREL
:
22725 case BFD_RELOC_ARM_PLT32
:
22726 case BFD_RELOC_ARM_TARGET1
:
22727 case BFD_RELOC_ARM_ROSEGREL32
:
22728 case BFD_RELOC_ARM_SBREL32
:
22729 case BFD_RELOC_ARM_PREL31
:
22730 case BFD_RELOC_ARM_TARGET2
:
22731 case BFD_RELOC_ARM_TLS_LE32
:
22732 case BFD_RELOC_ARM_TLS_LDO32
:
22733 case BFD_RELOC_ARM_PCREL_CALL
:
22734 case BFD_RELOC_ARM_PCREL_JUMP
:
22735 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
22736 case BFD_RELOC_ARM_ALU_PC_G0
:
22737 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
22738 case BFD_RELOC_ARM_ALU_PC_G1
:
22739 case BFD_RELOC_ARM_ALU_PC_G2
:
22740 case BFD_RELOC_ARM_LDR_PC_G0
:
22741 case BFD_RELOC_ARM_LDR_PC_G1
:
22742 case BFD_RELOC_ARM_LDR_PC_G2
:
22743 case BFD_RELOC_ARM_LDRS_PC_G0
:
22744 case BFD_RELOC_ARM_LDRS_PC_G1
:
22745 case BFD_RELOC_ARM_LDRS_PC_G2
:
22746 case BFD_RELOC_ARM_LDC_PC_G0
:
22747 case BFD_RELOC_ARM_LDC_PC_G1
:
22748 case BFD_RELOC_ARM_LDC_PC_G2
:
22749 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
22750 case BFD_RELOC_ARM_ALU_SB_G0
:
22751 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
22752 case BFD_RELOC_ARM_ALU_SB_G1
:
22753 case BFD_RELOC_ARM_ALU_SB_G2
:
22754 case BFD_RELOC_ARM_LDR_SB_G0
:
22755 case BFD_RELOC_ARM_LDR_SB_G1
:
22756 case BFD_RELOC_ARM_LDR_SB_G2
:
22757 case BFD_RELOC_ARM_LDRS_SB_G0
:
22758 case BFD_RELOC_ARM_LDRS_SB_G1
:
22759 case BFD_RELOC_ARM_LDRS_SB_G2
:
22760 case BFD_RELOC_ARM_LDC_SB_G0
:
22761 case BFD_RELOC_ARM_LDC_SB_G1
:
22762 case BFD_RELOC_ARM_LDC_SB_G2
:
22763 case BFD_RELOC_ARM_V4BX
:
22764 code
= fixp
->fx_r_type
;
22767 case BFD_RELOC_ARM_TLS_GOTDESC
:
22768 case BFD_RELOC_ARM_TLS_GD32
:
22769 case BFD_RELOC_ARM_TLS_IE32
:
22770 case BFD_RELOC_ARM_TLS_LDM32
:
22771 /* BFD will include the symbol's address in the addend.
22772 But we don't want that, so subtract it out again here. */
22773 if (!S_IS_COMMON (fixp
->fx_addsy
))
22774 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
22775 code
= fixp
->fx_r_type
;
22779 case BFD_RELOC_ARM_IMMEDIATE
:
22780 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22781 _("internal relocation (type: IMMEDIATE) not fixed up"));
22784 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22785 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22786 _("ADRL used for a symbol not defined in the same file"));
22789 case BFD_RELOC_ARM_OFFSET_IMM
:
22790 if (section
->use_rela_p
)
22792 code
= fixp
->fx_r_type
;
22796 if (fixp
->fx_addsy
!= NULL
22797 && !S_IS_DEFINED (fixp
->fx_addsy
)
22798 && S_IS_LOCAL (fixp
->fx_addsy
))
22800 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22801 _("undefined local label `%s'"),
22802 S_GET_NAME (fixp
->fx_addsy
));
22806 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22807 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22814 switch (fixp
->fx_r_type
)
22816 case BFD_RELOC_NONE
: type
= "NONE"; break;
22817 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
22818 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
22819 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
22820 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
22821 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
22822 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
22823 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
22824 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
22825 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
22826 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
22827 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
22828 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
22829 default: type
= _("<unknown>"); break;
22831 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22832 _("cannot represent %s relocation in this object file format"),
22839 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
22841 && fixp
->fx_addsy
== GOT_symbol
)
22843 code
= BFD_RELOC_ARM_GOTPC
;
22844 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
22848 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
22850 if (reloc
->howto
== NULL
)
22852 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22853 _("cannot represent %s relocation in this object file format"),
22854 bfd_get_reloc_code_name (code
));
22858 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22859 vtable entry to be used in the relocation's section offset. */
22860 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
22861 reloc
->address
= fixp
->fx_offset
;
22866 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22869 cons_fix_new_arm (fragS
* frag
,
22874 bfd_reloc_code_real_type type
;
22878 FIXME: @@ Should look at CPU word size. */
22882 type
= BFD_RELOC_8
;
22885 type
= BFD_RELOC_16
;
22889 type
= BFD_RELOC_32
;
22892 type
= BFD_RELOC_64
;
22897 if (exp
->X_op
== O_secrel
)
22899 exp
->X_op
= O_symbol
;
22900 type
= BFD_RELOC_32_SECREL
;
22904 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
22907 #if defined (OBJ_COFF)
22909 arm_validate_fix (fixS
* fixP
)
22911 /* If the destination of the branch is a defined symbol which does not have
22912 the THUMB_FUNC attribute, then we must be calling a function which has
22913 the (interfacearm) attribute. We look for the Thumb entry point to that
22914 function and change the branch to refer to that function instead. */
22915 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
22916 && fixP
->fx_addsy
!= NULL
22917 && S_IS_DEFINED (fixP
->fx_addsy
)
22918 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
22920 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
22927 arm_force_relocation (struct fix
* fixp
)
22929 #if defined (OBJ_COFF) && defined (TE_PE)
22930 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
22934 /* In case we have a call or a branch to a function in ARM ISA mode from
22935 a thumb function or vice-versa force the relocation. These relocations
22936 are cleared off for some cores that might have blx and simple transformations
22940 switch (fixp
->fx_r_type
)
22942 case BFD_RELOC_ARM_PCREL_JUMP
:
22943 case BFD_RELOC_ARM_PCREL_CALL
:
22944 case BFD_RELOC_THUMB_PCREL_BLX
:
22945 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
22949 case BFD_RELOC_ARM_PCREL_BLX
:
22950 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22951 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22952 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22953 if (ARM_IS_FUNC (fixp
->fx_addsy
))
22962 /* Resolve these relocations even if the symbol is extern or weak.
22963 Technically this is probably wrong due to symbol preemption.
22964 In practice these relocations do not have enough range to be useful
22965 at dynamic link time, and some code (e.g. in the Linux kernel)
22966 expects these references to be resolved. */
22967 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
22968 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
22969 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
22970 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
22971 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22972 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
22973 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
22974 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
22975 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22976 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
22977 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
22978 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
22979 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
22980 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
22983 /* Always leave these relocations for the linker. */
22984 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22985 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22986 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22989 /* Always generate relocations against function symbols. */
22990 if (fixp
->fx_r_type
== BFD_RELOC_32
22992 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
22995 return generic_force_reloc (fixp
);
22998 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22999 /* Relocations against function names must be left unadjusted,
23000 so that the linker can use this information to generate interworking
23001 stubs. The MIPS version of this function
23002 also prevents relocations that are mips-16 specific, but I do not
23003 know why it does this.
23006 There is one other problem that ought to be addressed here, but
23007 which currently is not: Taking the address of a label (rather
23008 than a function) and then later jumping to that address. Such
23009 addresses also ought to have their bottom bit set (assuming that
23010 they reside in Thumb code), but at the moment they will not. */
23013 arm_fix_adjustable (fixS
* fixP
)
23015 if (fixP
->fx_addsy
== NULL
)
23018 /* Preserve relocations against symbols with function type. */
23019 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23022 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23023 && fixP
->fx_subsy
== NULL
)
23026 /* We need the symbol name for the VTABLE entries. */
23027 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23028 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23031 /* Don't allow symbols to be discarded on GOT related relocs. */
23032 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23033 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23034 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23035 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23036 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23037 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23038 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23039 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23040 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23041 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23042 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23043 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23044 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23045 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23048 /* Similarly for group relocations. */
23049 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23050 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23051 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23054 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23055 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23056 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23057 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23058 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23059 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23060 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23061 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23062 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23067 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23072 elf32_arm_target_format (void)
23075 return (target_big_endian
23076 ? "elf32-bigarm-symbian"
23077 : "elf32-littlearm-symbian");
23078 #elif defined (TE_VXWORKS)
23079 return (target_big_endian
23080 ? "elf32-bigarm-vxworks"
23081 : "elf32-littlearm-vxworks");
23082 #elif defined (TE_NACL)
23083 return (target_big_endian
23084 ? "elf32-bigarm-nacl"
23085 : "elf32-littlearm-nacl");
23087 if (target_big_endian
)
23088 return "elf32-bigarm";
23090 return "elf32-littlearm";
23095 armelf_frob_symbol (symbolS
* symp
,
23098 elf_frob_symbol (symp
, puntp
);
23102 /* MD interface: Finalization. */
23107 literal_pool
* pool
;
23109 /* Ensure that all the IT blocks are properly closed. */
23110 check_it_blocks_finished ();
23112 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23114 /* Put it at the end of the relevant section. */
23115 subseg_set (pool
->section
, pool
->sub_section
);
23117 arm_elf_change_section ();
23124 /* Remove any excess mapping symbols generated for alignment frags in
23125 SEC. We may have created a mapping symbol before a zero byte
23126 alignment; remove it if there's a mapping symbol after the
23129 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23130 void *dummy ATTRIBUTE_UNUSED
)
23132 segment_info_type
*seginfo
= seg_info (sec
);
23135 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23138 for (fragp
= seginfo
->frchainP
->frch_root
;
23140 fragp
= fragp
->fr_next
)
23142 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23143 fragS
*next
= fragp
->fr_next
;
23145 /* Variable-sized frags have been converted to fixed size by
23146 this point. But if this was variable-sized to start with,
23147 there will be a fixed-size frag after it. So don't handle
23149 if (sym
== NULL
|| next
== NULL
)
23152 if (S_GET_VALUE (sym
) < next
->fr_address
)
23153 /* Not at the end of this frag. */
23155 know (S_GET_VALUE (sym
) == next
->fr_address
);
23159 if (next
->tc_frag_data
.first_map
!= NULL
)
23161 /* Next frag starts with a mapping symbol. Discard this
23163 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23167 if (next
->fr_next
== NULL
)
23169 /* This mapping symbol is at the end of the section. Discard
23171 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23172 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23176 /* As long as we have empty frags without any mapping symbols,
23178 /* If the next frag is non-empty and does not start with a
23179 mapping symbol, then this mapping symbol is required. */
23180 if (next
->fr_address
!= next
->fr_next
->fr_address
)
23183 next
= next
->fr_next
;
23185 while (next
!= NULL
);
23190 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23194 arm_adjust_symtab (void)
23199 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23201 if (ARM_IS_THUMB (sym
))
23203 if (THUMB_IS_FUNC (sym
))
23205 /* Mark the symbol as a Thumb function. */
23206 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
23207 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
23208 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
23210 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
23211 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
23213 as_bad (_("%s: unexpected function type: %d"),
23214 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
23216 else switch (S_GET_STORAGE_CLASS (sym
))
23219 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
23222 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
23225 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
23233 if (ARM_IS_INTERWORK (sym
))
23234 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
23241 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23243 if (ARM_IS_THUMB (sym
))
23245 elf_symbol_type
* elf_sym
;
23247 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
23248 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
23250 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
23251 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
23253 /* If it's a .thumb_func, declare it as so,
23254 otherwise tag label as .code 16. */
23255 if (THUMB_IS_FUNC (sym
))
23256 elf_sym
->internal_elf_sym
.st_target_internal
23257 = ST_BRANCH_TO_THUMB
;
23258 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23259 elf_sym
->internal_elf_sym
.st_info
=
23260 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
23265 /* Remove any overlapping mapping symbols generated by alignment frags. */
23266 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
23267 /* Now do generic ELF adjustments. */
23268 elf_adjust_symtab ();
23272 /* MD interface: Initialization. */
23275 set_constant_flonums (void)
23279 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
23280 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
23284 /* Auto-select Thumb mode if it's the only available instruction set for the
23285 given architecture. */
23288 autoselect_thumb_from_cpu_variant (void)
23290 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23291 opcode_select (16);
23300 if ( (arm_ops_hsh
= hash_new ()) == NULL
23301 || (arm_cond_hsh
= hash_new ()) == NULL
23302 || (arm_shift_hsh
= hash_new ()) == NULL
23303 || (arm_psr_hsh
= hash_new ()) == NULL
23304 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
23305 || (arm_reg_hsh
= hash_new ()) == NULL
23306 || (arm_reloc_hsh
= hash_new ()) == NULL
23307 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
23308 as_fatal (_("virtual memory exhausted"));
23310 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
23311 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
23312 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
23313 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
23314 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
23315 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
23316 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
23317 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
23318 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
23319 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
23320 (void *) (v7m_psrs
+ i
));
23321 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
23322 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
23324 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
23326 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
23327 (void *) (barrier_opt_names
+ i
));
23329 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
23331 struct reloc_entry
* entry
= reloc_names
+ i
;
23333 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
23334 /* This makes encode_branch() use the EABI versions of this relocation. */
23335 entry
->reloc
= BFD_RELOC_UNUSED
;
23337 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
23341 set_constant_flonums ();
23343 /* Set the cpu variant based on the command-line options. We prefer
23344 -mcpu= over -march= if both are set (as for GCC); and we prefer
23345 -mfpu= over any other way of setting the floating point unit.
23346 Use of legacy options with new options are faulted. */
23349 if (mcpu_cpu_opt
|| march_cpu_opt
)
23350 as_bad (_("use of old and new-style options to set CPU type"));
23352 mcpu_cpu_opt
= legacy_cpu
;
23354 else if (!mcpu_cpu_opt
)
23355 mcpu_cpu_opt
= march_cpu_opt
;
23360 as_bad (_("use of old and new-style options to set FPU type"));
23362 mfpu_opt
= legacy_fpu
;
23364 else if (!mfpu_opt
)
23366 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23367 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23368 /* Some environments specify a default FPU. If they don't, infer it
23369 from the processor. */
23371 mfpu_opt
= mcpu_fpu_opt
;
23373 mfpu_opt
= march_fpu_opt
;
23375 mfpu_opt
= &fpu_default
;
23381 if (mcpu_cpu_opt
!= NULL
)
23382 mfpu_opt
= &fpu_default
;
23383 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
23384 mfpu_opt
= &fpu_arch_vfp_v2
;
23386 mfpu_opt
= &fpu_arch_fpa
;
23392 mcpu_cpu_opt
= &cpu_default
;
23393 selected_cpu
= cpu_default
;
23397 selected_cpu
= *mcpu_cpu_opt
;
23399 mcpu_cpu_opt
= &arm_arch_any
;
23402 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23404 autoselect_thumb_from_cpu_variant ();
23406 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
23408 #if defined OBJ_COFF || defined OBJ_ELF
23410 unsigned int flags
= 0;
23412 #if defined OBJ_ELF
23413 flags
= meabi_flags
;
23415 switch (meabi_flags
)
23417 case EF_ARM_EABI_UNKNOWN
:
23419 /* Set the flags in the private structure. */
23420 if (uses_apcs_26
) flags
|= F_APCS26
;
23421 if (support_interwork
) flags
|= F_INTERWORK
;
23422 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
23423 if (pic_code
) flags
|= F_PIC
;
23424 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
23425 flags
|= F_SOFT_FLOAT
;
23427 switch (mfloat_abi_opt
)
23429 case ARM_FLOAT_ABI_SOFT
:
23430 case ARM_FLOAT_ABI_SOFTFP
:
23431 flags
|= F_SOFT_FLOAT
;
23434 case ARM_FLOAT_ABI_HARD
:
23435 if (flags
& F_SOFT_FLOAT
)
23436 as_bad (_("hard-float conflicts with specified fpu"));
23440 /* Using pure-endian doubles (even if soft-float). */
23441 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
23442 flags
|= F_VFP_FLOAT
;
23444 #if defined OBJ_ELF
23445 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
23446 flags
|= EF_ARM_MAVERICK_FLOAT
;
23449 case EF_ARM_EABI_VER4
:
23450 case EF_ARM_EABI_VER5
:
23451 /* No additional flags to set. */
23458 bfd_set_private_flags (stdoutput
, flags
);
23460 /* We have run out flags in the COFF header to encode the
23461 status of ATPCS support, so instead we create a dummy,
23462 empty, debug section called .arm.atpcs. */
23467 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
23471 bfd_set_section_flags
23472 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
23473 bfd_set_section_size (stdoutput
, sec
, 0);
23474 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
23480 /* Record the CPU type as well. */
23481 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
23482 mach
= bfd_mach_arm_iWMMXt2
;
23483 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
23484 mach
= bfd_mach_arm_iWMMXt
;
23485 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
23486 mach
= bfd_mach_arm_XScale
;
23487 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
23488 mach
= bfd_mach_arm_ep9312
;
23489 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
23490 mach
= bfd_mach_arm_5TE
;
23491 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
23493 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
23494 mach
= bfd_mach_arm_5T
;
23496 mach
= bfd_mach_arm_5
;
23498 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
23500 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
23501 mach
= bfd_mach_arm_4T
;
23503 mach
= bfd_mach_arm_4
;
23505 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
23506 mach
= bfd_mach_arm_3M
;
23507 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
23508 mach
= bfd_mach_arm_3
;
23509 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
23510 mach
= bfd_mach_arm_2a
;
23511 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
23512 mach
= bfd_mach_arm_2
;
23514 mach
= bfd_mach_arm_unknown
;
23516 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
23519 /* Command line processing. */
23522 Invocation line includes a switch not recognized by the base assembler.
23523 See if it's a processor-specific option.
23525 This routine is somewhat complicated by the need for backwards
23526 compatibility (since older releases of gcc can't be changed).
23527 The new options try to make the interface as compatible as
23530 New options (supported) are:
23532 -mcpu=<cpu name> Assemble for selected processor
23533 -march=<architecture name> Assemble for selected architecture
23534 -mfpu=<fpu architecture> Assemble for selected FPU.
23535 -EB/-mbig-endian Big-endian
23536 -EL/-mlittle-endian Little-endian
23537 -k Generate PIC code
23538 -mthumb Start in Thumb mode
23539 -mthumb-interwork Code supports ARM/Thumb interworking
23541 -m[no-]warn-deprecated Warn about deprecated features
23543 For now we will also provide support for:
23545 -mapcs-32 32-bit Program counter
23546 -mapcs-26 26-bit Program counter
23547 -macps-float Floats passed in FP registers
23548 -mapcs-reentrant Reentrant code
23550 (sometime these will probably be replaced with -mapcs=<list of options>
23551 and -matpcs=<list of options>)
23553 The remaining options are only supported for back-wards compatibility.
23554 Cpu variants, the arm part is optional:
23555 -m[arm]1 Currently not supported.
23556 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23557 -m[arm]3 Arm 3 processor
23558 -m[arm]6[xx], Arm 6 processors
23559 -m[arm]7[xx][t][[d]m] Arm 7 processors
23560 -m[arm]8[10] Arm 8 processors
23561 -m[arm]9[20][tdmi] Arm 9 processors
23562 -mstrongarm[110[0]] StrongARM processors
23563 -mxscale XScale processors
23564 -m[arm]v[2345[t[e]]] Arm architectures
23565 -mall All (except the ARM1)
23567 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23568 -mfpe-old (No float load/store multiples)
23569 -mvfpxd VFP Single precision
23571 -mno-fpu Disable all floating point instructions
23573 The following CPU names are recognized:
23574 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23575 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23576 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23577 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23578 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23579 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23580 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23584 const char * md_shortopts
= "m:k";
23586 #ifdef ARM_BI_ENDIAN
23587 #define OPTION_EB (OPTION_MD_BASE + 0)
23588 #define OPTION_EL (OPTION_MD_BASE + 1)
23590 #if TARGET_BYTES_BIG_ENDIAN
23591 #define OPTION_EB (OPTION_MD_BASE + 0)
23593 #define OPTION_EL (OPTION_MD_BASE + 1)
23596 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23598 struct option md_longopts
[] =
23601 {"EB", no_argument
, NULL
, OPTION_EB
},
23604 {"EL", no_argument
, NULL
, OPTION_EL
},
23606 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
23607 {NULL
, no_argument
, NULL
, 0}
23610 size_t md_longopts_size
= sizeof (md_longopts
);
23612 struct arm_option_table
23614 char *option
; /* Option name to match. */
23615 char *help
; /* Help information. */
23616 int *var
; /* Variable to change. */
23617 int value
; /* What to change it to. */
23618 char *deprecated
; /* If non-null, print this message. */
23621 struct arm_option_table arm_opts
[] =
23623 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
23624 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
23625 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23626 &support_interwork
, 1, NULL
},
23627 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
23628 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
23629 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
23631 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
23632 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
23633 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
23634 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
23637 /* These are recognized by the assembler, but have no affect on code. */
23638 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
23639 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
23641 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
23642 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23643 &warn_on_deprecated
, 0, NULL
},
23644 {NULL
, NULL
, NULL
, 0, NULL
}
23647 struct arm_legacy_option_table
23649 char *option
; /* Option name to match. */
23650 const arm_feature_set
**var
; /* Variable to change. */
23651 const arm_feature_set value
; /* What to change it to. */
23652 char *deprecated
; /* If non-null, print this message. */
23655 const struct arm_legacy_option_table arm_legacy_opts
[] =
23657 /* DON'T add any new processors to this list -- we want the whole list
23658 to go away... Add them to the processors table instead. */
23659 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23660 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23661 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23662 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23663 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23664 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23665 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23666 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23667 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23668 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23669 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23670 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23671 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23672 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23673 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23674 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23675 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23676 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23677 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23678 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23679 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23680 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23681 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23682 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23683 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23684 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23685 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23686 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23687 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23688 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23689 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23690 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23691 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23692 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23693 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23694 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23695 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23696 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23697 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23698 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23699 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23700 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23701 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23702 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23703 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23704 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23705 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23706 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23707 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23708 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23709 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
23710 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
23711 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
23712 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
23713 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
23714 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
23715 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
23716 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
23717 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
23718 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
23719 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
23720 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
23721 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
23722 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
23723 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
23724 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
23725 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
23726 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
23727 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
23728 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
23729 N_("use -mcpu=strongarm110")},
23730 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
23731 N_("use -mcpu=strongarm1100")},
23732 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
23733 N_("use -mcpu=strongarm1110")},
23734 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
23735 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
23736 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
23738 /* Architecture variants -- don't add any more to this list either. */
23739 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
23740 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
23741 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
23742 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
23743 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
23744 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
23745 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
23746 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
23747 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
23748 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
23749 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
23750 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
23751 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
23752 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
23753 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
23754 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
23755 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
23756 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
23758 /* Floating point variants -- don't add any more to this list either. */
23759 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
23760 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
23761 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
23762 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
23763 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23765 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
23768 struct arm_cpu_option_table
23772 const arm_feature_set value
;
23773 /* For some CPUs we assume an FPU unless the user explicitly sets
23775 const arm_feature_set default_fpu
;
23776 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23778 const char *canonical_name
;
23781 /* This list should, at a minimum, contain all the cpu names
23782 recognized by GCC. */
23783 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23784 static const struct arm_cpu_option_table arm_cpus
[] =
23786 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
23787 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
23788 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
23789 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
23790 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
23791 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23792 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23793 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23794 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23795 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23796 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23797 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
23798 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23799 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
23800 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23801 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
23802 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23803 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23804 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23805 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23806 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23807 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23808 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23809 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23810 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23811 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23812 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23813 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
23814 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23815 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23816 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23817 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23818 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23819 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23820 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23821 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23822 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23823 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23824 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23825 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
23826 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23827 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23828 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23829 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
23830 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23831 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
23832 /* For V5 or later processors we default to using VFP; but the user
23833 should really set the FPU type explicitly. */
23834 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
23835 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23836 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
23837 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
23838 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
23839 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
23840 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
23841 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23842 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
23843 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
23844 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23845 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23846 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
23847 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
23848 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23849 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
23850 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
23851 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23852 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23853 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
23855 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
23856 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23857 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23858 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23859 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23860 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
23861 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
23862 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
23863 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
23865 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
23866 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
23867 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
23868 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
23869 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
23870 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
23871 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
23872 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
23873 FPU_NONE
, "Cortex-A5"),
23874 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
23875 FPU_ARCH_NEON_VFP_V4
,
23877 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
23878 ARM_FEATURE (0, FPU_VFP_V3
23879 | FPU_NEON_EXT_V1
),
23881 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
23882 ARM_FEATURE (0, FPU_VFP_V3
23883 | FPU_NEON_EXT_V1
),
23885 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
23886 FPU_ARCH_NEON_VFP_V4
,
23888 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
23889 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
23891 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
23892 FPU_NONE
, "Cortex-R5"),
23893 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
23894 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
23895 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
23896 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
23897 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
23898 /* ??? XSCALE is really an architecture. */
23899 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
23900 /* ??? iwmmxt is not a processor. */
23901 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
23902 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
23903 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
23905 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
23908 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
23912 struct arm_arch_option_table
23916 const arm_feature_set value
;
23917 const arm_feature_set default_fpu
;
23920 /* This list should, at a minimum, contain all the architecture names
23921 recognized by GCC. */
23922 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23923 static const struct arm_arch_option_table arm_archs
[] =
23925 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
23926 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
23927 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
23928 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
23929 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
23930 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
23931 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
23932 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
23933 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
23934 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
23935 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
23936 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
23937 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
23938 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
23939 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
23940 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
23941 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
23942 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
23943 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
23944 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
23945 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
23946 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
23947 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
23948 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
23949 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
23950 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
23951 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
23952 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
23953 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
23954 /* The official spelling of the ARMv7 profile variants is the dashed form.
23955 Accept the non-dashed form for compatibility with old toolchains. */
23956 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
23957 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
23958 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
23959 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
23960 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
23961 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
23962 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
23963 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
23964 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
23965 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
23966 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
23967 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
23969 #undef ARM_ARCH_OPT
23971 /* ISA extensions in the co-processor and main instruction set space. */
23972 struct arm_option_extension_value_table
23976 const arm_feature_set value
;
23977 const arm_feature_set allowed_archs
;
23980 /* The following table must be in alphabetical order with a NULL last entry.
23982 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23983 static const struct arm_option_extension_value_table arm_extensions
[] =
23985 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
23986 ARM_FEATURE (ARM_EXT_V8
, 0)),
23987 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
,
23988 ARM_FEATURE (ARM_EXT_V8
, 0)),
23989 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
23990 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
23991 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
),
23992 ARM_EXT_OPT ("iwmmxt2",
23993 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
),
23994 ARM_EXT_OPT ("maverick",
23995 ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
),
23996 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP
, 0),
23997 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
23998 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
23999 ARM_FEATURE (ARM_EXT_V8
, 0)),
24000 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS
, 0),
24001 ARM_FEATURE (ARM_EXT_V6M
, 0)),
24002 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
24003 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)),
24004 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
24006 ARM_FEATURE (ARM_EXT_V7A
, 0)),
24007 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
),
24008 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24012 /* ISA floating-point and Advanced SIMD extensions. */
24013 struct arm_option_fpu_value_table
24016 const arm_feature_set value
;
24019 /* This list should, at a minimum, contain all the fpu names
24020 recognized by GCC. */
24021 static const struct arm_option_fpu_value_table arm_fpus
[] =
24023 {"softfpa", FPU_NONE
},
24024 {"fpe", FPU_ARCH_FPE
},
24025 {"fpe2", FPU_ARCH_FPE
},
24026 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24027 {"fpa", FPU_ARCH_FPA
},
24028 {"fpa10", FPU_ARCH_FPA
},
24029 {"fpa11", FPU_ARCH_FPA
},
24030 {"arm7500fe", FPU_ARCH_FPA
},
24031 {"softvfp", FPU_ARCH_VFP
},
24032 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24033 {"vfp", FPU_ARCH_VFP_V2
},
24034 {"vfp9", FPU_ARCH_VFP_V2
},
24035 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24036 {"vfp10", FPU_ARCH_VFP_V2
},
24037 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24038 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24039 {"vfpv2", FPU_ARCH_VFP_V2
},
24040 {"vfpv3", FPU_ARCH_VFP_V3
},
24041 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24042 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24043 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24044 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24045 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24046 {"arm1020t", FPU_ARCH_VFP_V1
},
24047 {"arm1020e", FPU_ARCH_VFP_V2
},
24048 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24049 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24050 {"maverick", FPU_ARCH_MAVERICK
},
24051 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24052 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24053 {"vfpv4", FPU_ARCH_VFP_V4
},
24054 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24055 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24056 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24057 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24058 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24059 {"crypto-neon-fp-armv8",
24060 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24061 {NULL
, ARM_ARCH_NONE
}
24064 struct arm_option_value_table
24070 static const struct arm_option_value_table arm_float_abis
[] =
24072 {"hard", ARM_FLOAT_ABI_HARD
},
24073 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24074 {"soft", ARM_FLOAT_ABI_SOFT
},
24079 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24080 static const struct arm_option_value_table arm_eabis
[] =
24082 {"gnu", EF_ARM_EABI_UNKNOWN
},
24083 {"4", EF_ARM_EABI_VER4
},
24084 {"5", EF_ARM_EABI_VER5
},
24089 struct arm_long_option_table
24091 char * option
; /* Substring to match. */
24092 char * help
; /* Help information. */
24093 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24094 char * deprecated
; /* If non-null, print this message. */
24098 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24100 arm_feature_set
*ext_set
= (arm_feature_set
*)
24101 xmalloc (sizeof (arm_feature_set
));
24103 /* We insist on extensions being specified in alphabetical order, and with
24104 extensions being added before being removed. We achieve this by having
24105 the global ARM_EXTENSIONS table in alphabetical order, and using the
24106 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24107 or removing it (0) and only allowing it to change in the order
24109 const struct arm_option_extension_value_table
* opt
= NULL
;
24110 int adding_value
= -1;
24112 /* Copy the feature set, so that we can modify it. */
24113 *ext_set
= **opt_p
;
24116 while (str
!= NULL
&& *str
!= 0)
24123 as_bad (_("invalid architectural extension"));
24128 ext
= strchr (str
, '+');
24133 len
= strlen (str
);
24135 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
24137 if (adding_value
!= 0)
24140 opt
= arm_extensions
;
24148 if (adding_value
== -1)
24151 opt
= arm_extensions
;
24153 else if (adding_value
!= 1)
24155 as_bad (_("must specify extensions to add before specifying "
24156 "those to remove"));
24163 as_bad (_("missing architectural extension"));
24167 gas_assert (adding_value
!= -1);
24168 gas_assert (opt
!= NULL
);
24170 /* Scan over the options table trying to find an exact match. */
24171 for (; opt
->name
!= NULL
; opt
++)
24172 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24174 /* Check we can apply the extension to this architecture. */
24175 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
24177 as_bad (_("extension does not apply to the base architecture"));
24181 /* Add or remove the extension. */
24183 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
24185 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
24190 if (opt
->name
== NULL
)
24192 /* Did we fail to find an extension because it wasn't specified in
24193 alphabetical order, or because it does not exist? */
24195 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24196 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24199 if (opt
->name
== NULL
)
24200 as_bad (_("unknown architectural extension `%s'"), str
);
24202 as_bad (_("architectural extensions must be specified in "
24203 "alphabetical order"));
24209 /* We should skip the extension we've just matched the next time
24221 arm_parse_cpu (char *str
)
24223 const struct arm_cpu_option_table
*opt
;
24224 char *ext
= strchr (str
, '+');
24230 len
= strlen (str
);
24234 as_bad (_("missing cpu name `%s'"), str
);
24238 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
24239 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24241 mcpu_cpu_opt
= &opt
->value
;
24242 mcpu_fpu_opt
= &opt
->default_fpu
;
24243 if (opt
->canonical_name
)
24244 strcpy (selected_cpu_name
, opt
->canonical_name
);
24249 for (i
= 0; i
< len
; i
++)
24250 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24251 selected_cpu_name
[i
] = 0;
24255 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
24260 as_bad (_("unknown cpu `%s'"), str
);
24265 arm_parse_arch (char *str
)
24267 const struct arm_arch_option_table
*opt
;
24268 char *ext
= strchr (str
, '+');
24274 len
= strlen (str
);
24278 as_bad (_("missing architecture name `%s'"), str
);
24282 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
24283 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24285 march_cpu_opt
= &opt
->value
;
24286 march_fpu_opt
= &opt
->default_fpu
;
24287 strcpy (selected_cpu_name
, opt
->name
);
24290 return arm_parse_extension (ext
, &march_cpu_opt
);
24295 as_bad (_("unknown architecture `%s'\n"), str
);
24300 arm_parse_fpu (char * str
)
24302 const struct arm_option_fpu_value_table
* opt
;
24304 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24305 if (streq (opt
->name
, str
))
24307 mfpu_opt
= &opt
->value
;
24311 as_bad (_("unknown floating point format `%s'\n"), str
);
24316 arm_parse_float_abi (char * str
)
24318 const struct arm_option_value_table
* opt
;
24320 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
24321 if (streq (opt
->name
, str
))
24323 mfloat_abi_opt
= opt
->value
;
24327 as_bad (_("unknown floating point abi `%s'\n"), str
);
24333 arm_parse_eabi (char * str
)
24335 const struct arm_option_value_table
*opt
;
24337 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
24338 if (streq (opt
->name
, str
))
24340 meabi_flags
= opt
->value
;
24343 as_bad (_("unknown EABI `%s'\n"), str
);
24349 arm_parse_it_mode (char * str
)
24351 bfd_boolean ret
= TRUE
;
24353 if (streq ("arm", str
))
24354 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
24355 else if (streq ("thumb", str
))
24356 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
24357 else if (streq ("always", str
))
24358 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
24359 else if (streq ("never", str
))
24360 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
24363 as_bad (_("unknown implicit IT mode `%s', should be "\
24364 "arm, thumb, always, or never."), str
);
24371 struct arm_long_option_table arm_long_opts
[] =
24373 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24374 arm_parse_cpu
, NULL
},
24375 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24376 arm_parse_arch
, NULL
},
24377 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24378 arm_parse_fpu
, NULL
},
24379 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24380 arm_parse_float_abi
, NULL
},
24382 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24383 arm_parse_eabi
, NULL
},
24385 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24386 arm_parse_it_mode
, NULL
},
24387 {NULL
, NULL
, 0, NULL
}
24391 md_parse_option (int c
, char * arg
)
24393 struct arm_option_table
*opt
;
24394 const struct arm_legacy_option_table
*fopt
;
24395 struct arm_long_option_table
*lopt
;
24401 target_big_endian
= 1;
24407 target_big_endian
= 0;
24411 case OPTION_FIX_V4BX
:
24416 /* Listing option. Just ignore these, we don't support additional
24421 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
24423 if (c
== opt
->option
[0]
24424 && ((arg
== NULL
&& opt
->option
[1] == 0)
24425 || streq (arg
, opt
->option
+ 1)))
24427 /* If the option is deprecated, tell the user. */
24428 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
24429 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
24430 arg
? arg
: "", _(opt
->deprecated
));
24432 if (opt
->var
!= NULL
)
24433 *opt
->var
= opt
->value
;
24439 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
24441 if (c
== fopt
->option
[0]
24442 && ((arg
== NULL
&& fopt
->option
[1] == 0)
24443 || streq (arg
, fopt
->option
+ 1)))
24445 /* If the option is deprecated, tell the user. */
24446 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
24447 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
24448 arg
? arg
: "", _(fopt
->deprecated
));
24450 if (fopt
->var
!= NULL
)
24451 *fopt
->var
= &fopt
->value
;
24457 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
24459 /* These options are expected to have an argument. */
24460 if (c
== lopt
->option
[0]
24462 && strncmp (arg
, lopt
->option
+ 1,
24463 strlen (lopt
->option
+ 1)) == 0)
24465 /* If the option is deprecated, tell the user. */
24466 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
24467 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
24468 _(lopt
->deprecated
));
24470 /* Call the sup-option parser. */
24471 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
24482 md_show_usage (FILE * fp
)
24484 struct arm_option_table
*opt
;
24485 struct arm_long_option_table
*lopt
;
24487 fprintf (fp
, _(" ARM-specific assembler options:\n"));
24489 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
24490 if (opt
->help
!= NULL
)
24491 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
24493 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
24494 if (lopt
->help
!= NULL
)
24495 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
24499 -EB assemble code for a big-endian cpu\n"));
24504 -EL assemble code for a little-endian cpu\n"));
24508 --fix-v4bx Allow BX in ARMv4 code\n"));
24516 arm_feature_set flags
;
24517 } cpu_arch_ver_table
;
24519 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24520 least features first. */
24521 static const cpu_arch_ver_table cpu_arch_ver
[] =
24527 {4, ARM_ARCH_V5TE
},
24528 {5, ARM_ARCH_V5TEJ
},
24532 {11, ARM_ARCH_V6M
},
24533 {12, ARM_ARCH_V6SM
},
24534 {8, ARM_ARCH_V6T2
},
24535 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
},
24536 {10, ARM_ARCH_V7R
},
24537 {10, ARM_ARCH_V7M
},
24538 {14, ARM_ARCH_V8A
},
24542 /* Set an attribute if it has not already been set by the user. */
24544 aeabi_set_attribute_int (int tag
, int value
)
24547 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24548 || !attributes_set_explicitly
[tag
])
24549 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
24553 aeabi_set_attribute_string (int tag
, const char *value
)
24556 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24557 || !attributes_set_explicitly
[tag
])
24558 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
24561 /* Set the public EABI object attributes. */
24563 aeabi_set_public_attributes (void)
24568 int fp16_optional
= 0;
24569 arm_feature_set flags
;
24570 arm_feature_set tmp
;
24571 const cpu_arch_ver_table
*p
;
24573 /* Choose the architecture based on the capabilities of the requested cpu
24574 (if any) and/or the instructions actually used. */
24575 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
24576 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
24577 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
24579 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
24580 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
24582 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
24583 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
24585 /* Allow the user to override the reported architecture. */
24588 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
24589 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
24592 /* We need to make sure that the attributes do not identify us as v6S-M
24593 when the only v6S-M feature in use is the Operating System Extensions. */
24594 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
24595 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
24596 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
24600 for (p
= cpu_arch_ver
; p
->val
; p
++)
24602 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
24605 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
24609 /* The table lookup above finds the last architecture to contribute
24610 a new feature. Unfortunately, Tag13 is a subset of the union of
24611 v6T2 and v7-M, so it is never seen as contributing a new feature.
24612 We can not search for the last entry which is entirely used,
24613 because if no CPU is specified we build up only those flags
24614 actually used. Perhaps we should separate out the specified
24615 and implicit cases. Avoid taking this path for -march=all by
24616 checking for contradictory v7-A / v7-M features. */
24618 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
24619 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
24620 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
24623 /* Tag_CPU_name. */
24624 if (selected_cpu_name
[0])
24628 q
= selected_cpu_name
;
24629 if (strncmp (q
, "armv", 4) == 0)
24634 for (i
= 0; q
[i
]; i
++)
24635 q
[i
] = TOUPPER (q
[i
]);
24637 aeabi_set_attribute_string (Tag_CPU_name
, q
);
24640 /* Tag_CPU_arch. */
24641 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
24643 /* Tag_CPU_arch_profile. */
24644 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
24646 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
24648 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
24653 if (profile
!= '\0')
24654 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
24656 /* Tag_ARM_ISA_use. */
24657 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
24659 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
24661 /* Tag_THUMB_ISA_use. */
24662 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
24664 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
24665 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
24667 /* Tag_VFP_arch. */
24668 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8
))
24669 aeabi_set_attribute_int (Tag_VFP_arch
, 7);
24670 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
24671 aeabi_set_attribute_int (Tag_VFP_arch
,
24672 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
24674 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
24677 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
24679 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
24681 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
24684 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
24685 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
24686 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
24687 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
24688 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
24690 /* Tag_ABI_HardFP_use. */
24691 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
24692 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
24693 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
24695 /* Tag_WMMX_arch. */
24696 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
24697 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
24698 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
24699 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
24701 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24702 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
24703 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
24704 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
24706 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
24708 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
24712 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
24717 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24718 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
24719 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
24723 We set Tag_DIV_use to two when integer divide instructions have been used
24724 in ARM state, or when Thumb integer divide instructions have been used,
24725 but we have no architecture profile set, nor have we any ARM instructions.
24727 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24730 For new architectures we will have to check these tests. */
24731 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
24732 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
24733 aeabi_set_attribute_int (Tag_DIV_use
, 0);
24734 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
24735 || (profile
== '\0'
24736 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
24737 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
24738 aeabi_set_attribute_int (Tag_DIV_use
, 2);
24740 /* Tag_MP_extension_use. */
24741 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
24742 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
24744 /* Tag Virtualization_use. */
24745 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
24747 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
24750 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
24753 /* Add the default contents for the .ARM.attributes section. */
24757 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24760 aeabi_set_public_attributes ();
24762 #endif /* OBJ_ELF */
24765 /* Parse a .cpu directive. */
24768 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
24770 const struct arm_cpu_option_table
*opt
;
24774 name
= input_line_pointer
;
24775 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24776 input_line_pointer
++;
24777 saved_char
= *input_line_pointer
;
24778 *input_line_pointer
= 0;
24780 /* Skip the first "all" entry. */
24781 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
24782 if (streq (opt
->name
, name
))
24784 mcpu_cpu_opt
= &opt
->value
;
24785 selected_cpu
= opt
->value
;
24786 if (opt
->canonical_name
)
24787 strcpy (selected_cpu_name
, opt
->canonical_name
);
24791 for (i
= 0; opt
->name
[i
]; i
++)
24792 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24794 selected_cpu_name
[i
] = 0;
24796 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24797 *input_line_pointer
= saved_char
;
24798 demand_empty_rest_of_line ();
24801 as_bad (_("unknown cpu `%s'"), name
);
24802 *input_line_pointer
= saved_char
;
24803 ignore_rest_of_line ();
24807 /* Parse a .arch directive. */
24810 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
24812 const struct arm_arch_option_table
*opt
;
24816 name
= input_line_pointer
;
24817 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24818 input_line_pointer
++;
24819 saved_char
= *input_line_pointer
;
24820 *input_line_pointer
= 0;
24822 /* Skip the first "all" entry. */
24823 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
24824 if (streq (opt
->name
, name
))
24826 mcpu_cpu_opt
= &opt
->value
;
24827 selected_cpu
= opt
->value
;
24828 strcpy (selected_cpu_name
, opt
->name
);
24829 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24830 *input_line_pointer
= saved_char
;
24831 demand_empty_rest_of_line ();
24835 as_bad (_("unknown architecture `%s'\n"), name
);
24836 *input_line_pointer
= saved_char
;
24837 ignore_rest_of_line ();
24841 /* Parse a .object_arch directive. */
24844 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
24846 const struct arm_arch_option_table
*opt
;
24850 name
= input_line_pointer
;
24851 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24852 input_line_pointer
++;
24853 saved_char
= *input_line_pointer
;
24854 *input_line_pointer
= 0;
24856 /* Skip the first "all" entry. */
24857 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
24858 if (streq (opt
->name
, name
))
24860 object_arch
= &opt
->value
;
24861 *input_line_pointer
= saved_char
;
24862 demand_empty_rest_of_line ();
24866 as_bad (_("unknown architecture `%s'\n"), name
);
24867 *input_line_pointer
= saved_char
;
24868 ignore_rest_of_line ();
24871 /* Parse a .arch_extension directive. */
24874 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
24876 const struct arm_option_extension_value_table
*opt
;
24879 int adding_value
= 1;
24881 name
= input_line_pointer
;
24882 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24883 input_line_pointer
++;
24884 saved_char
= *input_line_pointer
;
24885 *input_line_pointer
= 0;
24887 if (strlen (name
) >= 2
24888 && strncmp (name
, "no", 2) == 0)
24894 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24895 if (streq (opt
->name
, name
))
24897 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
24899 as_bad (_("architectural extension `%s' is not allowed for the "
24900 "current base architecture"), name
);
24905 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
24907 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
24909 mcpu_cpu_opt
= &selected_cpu
;
24910 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24911 *input_line_pointer
= saved_char
;
24912 demand_empty_rest_of_line ();
24916 if (opt
->name
== NULL
)
24917 as_bad (_("unknown architecture `%s'\n"), name
);
24919 *input_line_pointer
= saved_char
;
24920 ignore_rest_of_line ();
24923 /* Parse a .fpu directive. */
24926 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
24928 const struct arm_option_fpu_value_table
*opt
;
24932 name
= input_line_pointer
;
24933 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
24934 input_line_pointer
++;
24935 saved_char
= *input_line_pointer
;
24936 *input_line_pointer
= 0;
24938 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24939 if (streq (opt
->name
, name
))
24941 mfpu_opt
= &opt
->value
;
24942 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24943 *input_line_pointer
= saved_char
;
24944 demand_empty_rest_of_line ();
24948 as_bad (_("unknown floating point format `%s'\n"), name
);
24949 *input_line_pointer
= saved_char
;
24950 ignore_rest_of_line ();
24953 /* Copy symbol information. */
24956 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
24958 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
24962 /* Given a symbolic attribute NAME, return the proper integer value.
24963 Returns -1 if the attribute is not known. */
24966 arm_convert_symbolic_attribute (const char *name
)
24968 static const struct
24973 attribute_table
[] =
24975 /* When you modify this table you should
24976 also modify the list in doc/c-arm.texi. */
24977 #define T(tag) {#tag, tag}
24978 T (Tag_CPU_raw_name
),
24981 T (Tag_CPU_arch_profile
),
24982 T (Tag_ARM_ISA_use
),
24983 T (Tag_THUMB_ISA_use
),
24987 T (Tag_Advanced_SIMD_arch
),
24988 T (Tag_PCS_config
),
24989 T (Tag_ABI_PCS_R9_use
),
24990 T (Tag_ABI_PCS_RW_data
),
24991 T (Tag_ABI_PCS_RO_data
),
24992 T (Tag_ABI_PCS_GOT_use
),
24993 T (Tag_ABI_PCS_wchar_t
),
24994 T (Tag_ABI_FP_rounding
),
24995 T (Tag_ABI_FP_denormal
),
24996 T (Tag_ABI_FP_exceptions
),
24997 T (Tag_ABI_FP_user_exceptions
),
24998 T (Tag_ABI_FP_number_model
),
24999 T (Tag_ABI_align_needed
),
25000 T (Tag_ABI_align8_needed
),
25001 T (Tag_ABI_align_preserved
),
25002 T (Tag_ABI_align8_preserved
),
25003 T (Tag_ABI_enum_size
),
25004 T (Tag_ABI_HardFP_use
),
25005 T (Tag_ABI_VFP_args
),
25006 T (Tag_ABI_WMMX_args
),
25007 T (Tag_ABI_optimization_goals
),
25008 T (Tag_ABI_FP_optimization_goals
),
25009 T (Tag_compatibility
),
25010 T (Tag_CPU_unaligned_access
),
25011 T (Tag_FP_HP_extension
),
25012 T (Tag_VFP_HP_extension
),
25013 T (Tag_ABI_FP_16bit_format
),
25014 T (Tag_MPextension_use
),
25016 T (Tag_nodefaults
),
25017 T (Tag_also_compatible_with
),
25018 T (Tag_conformance
),
25020 T (Tag_Virtualization_use
),
25021 /* We deliberately do not include Tag_MPextension_use_legacy. */
25029 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25030 if (streq (name
, attribute_table
[i
].name
))
25031 return attribute_table
[i
].tag
;
25037 /* Apply sym value for relocations only in the case that
25038 they are for local symbols and you have the respective
25039 architectural feature for blx and simple switches. */
25041 arm_apply_sym_value (struct fix
* fixP
)
25044 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25045 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25047 switch (fixP
->fx_r_type
)
25049 case BFD_RELOC_ARM_PCREL_BLX
:
25050 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25051 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25055 case BFD_RELOC_ARM_PCREL_CALL
:
25056 case BFD_RELOC_THUMB_PCREL_BLX
:
25057 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25068 #endif /* OBJ_ELF */